commit 06413ff513600ecb7ef7bf486d8871cce01b7d70
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Sun Oct 26 01:20:20 2014 +0200

    drivers/spi: add Macronix MX25U6435F and MX25L6495F support
    
    Contributed by MXIC: http://www.coreboot.org/pipermail/coreboot/2014-October/078835.html
    
    Change-Id: I07f872a5cbb2b0ea63794edb8fbca40d7856ce10
    Author: Alex Lu <alexlu6@mxic.com.tw>
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/7194
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit f21bdc3020b24cce585c4df69b06913177c94182
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Oct 21 07:43:41 2014 +1100

    superio/*/superio.c: Don't hide pointer types behind typedefs
    
    Hiding pointer types behind 'typedef's is usually not a great
    idea at the best of times. Worse the typedef becomes an integer
    at different stages in Coreboot. Let us refrain from doing this
    at all.
    
    Change-Id: Ia2ca8c98bb489daaa58f379433875864f6efabc8
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/7136
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.h@gmx.de>

commit 85836c2215498ff18746b3a7e85ed684cf2e119e
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 9 20:26:25 2014 +1000

    superio: Use 'pnp_devfn_t' over 'device_t' in romstage component
    
    The romstage component of Super I/O support is in fact written around
    passing a lower and upper half packed integer. We currently have two
    typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of
    'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the
    ramstage context and so is really a conflicting definition. This helps
    solve problems down the road to having the 'real' 'device_t' definition
    usable in romstage later.
    
    This follows on from the rational given in:
    c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32'
    
    Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6231
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    Tested-by: build bot (Jenkins)

commit 377fd754932922e8c907994ef3e4d8ab925c6132
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Oct 21 07:51:24 2014 +1100

    superio/common/conf_mode.c: Don't hide pointers with typedefs
    
    Change-Id: Ia1bbf2f885acf601b8a8360a7cd72819f70ef6a6
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/7137
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    Tested-by: build bot (Jenkins)

commit 795f96e2b947a950e4c56e34d1706308f8b2cec6
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Oct 27 02:45:22 2014 +0100

    lenovo/x2[23]0: Handle Ricoh SD cardreader
    
    Change-Id: Id0aecbd3e45bdf9661168ebd0e55f17dc6febaaa
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7203
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit dc878b45adff2f21bb209d8abdf3ccecc2dc32d8
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 9 18:41:12 2014 +1000

    include/device/device.h: Deduplicate '*_pnp_devfn_t' typedefs
    
    'pci_devfn_t' and 'pnp_devfn_t' are already defined in arch/io.h
    
    Change-Id: I006182bf6933fae21fe6671659b76e7031e74b71
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6230
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    Tested-by: build bot (Jenkins)

commit 5962b4ce9c87f8d34bfc00b14820645ab8281e5f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Sep 6 10:37:21 2014 +0300

    Use spelling LENOVO troughout instead of using Lenovo sometimes
    
    Change-Id: Ia4060831236d72f880eeff6263ada40cf195fb12
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7180
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    Tested-by: build bot (Jenkins)

commit 6a63c8cf5c6de6121e3a2306d7a26c568f97fa23
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Sep 6 10:12:47 2014 +0300

    lenovo/{x60,t60}: Change PARTNUMBER for consistency
    
    Change-Id: I0ace5f49b84170ab4701ad1b70d3c50c99066e53
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7178
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    Tested-by: build bot (Jenkins)

commit 1d33b7a5a66fa49a05317c9af91e8d1d4a526f6e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Sep 6 10:10:21 2014 +0300

    lenovo: Use readable name as part number.
    
    Part number is used only for coreboot ROM identification and
    in coreboot tables. Rather than guessing the P/N, just use readable name.
    
    SMBIOS uses information from EEPROM and so isn't affected.
    
    Change-Id: I33534c3acb83f20d5b493c82bfc98896bf64ff1a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7177
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    Tested-by: build bot (Jenkins)

commit 06c294619920aaf52d5a45ec98dde6482336dd19
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Sep 6 10:22:31 2014 +0300

    lenovo/*: Remove unused MAINBOARD_VERSION
    
    Change-Id: I88e889efe43b32e7efc59ea40d13e79209a27264
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7179
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    Tested-by: build bot (Jenkins)

commit 498c32a6e8d06e3989cb83def86952e9301b84ee
Author: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Date:   Tue Oct 14 17:29:36 2014 +0200

    siemens/sitemp_g1p1: Fix serial output for simo board
    
    The simo board with console output at UART port 1 (COM2) will not produce
    any output if CONFIG_UART_FOR_CONSOLE=1 is set correctly.
    Commit f29200240e428761827ab8d179fa23068bfa9d59
    (superio/ite/*: Factor out generic romstage component)
    will only and always activate UART port 0 unregarded to
    CONFIG_UART_FOR_CONSOLE value.
    Now the UART port which was selected by CONFIG_UART_FOR_CONSOLE
    will be enabled and used for console output
    
    Change-Id: Ibbd2b5115b1ed4763962ba32fc9c19431a906c78
    Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
    Reviewed-on: http://review.coreboot.org/7060
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.h@gmx.de>

commit 7d6b0afdf5dee7e0149c7a62217ee3cdcc9b53b8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 19 03:07:26 2014 +0200

    sandybridge: Kill CONFIG_HAVE_MRC_CACHE
    
    Change-Id: I54955fa44d126b7a3d382f57b4aa0dac01688104
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7129
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit fa1d688a787971bffd16c90b5a98bfc43b5cee2e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 19 02:50:45 2014 +0200

    sandy/ivy native: dedup romstage.c main()
    
    Change-Id: I9909a5b2bdb4b59219db6304fa4332802fe0301c
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7127
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit b640fd39062194819cfb0ed4ff40b75fc383cac6
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Wed Oct 22 13:47:18 2014 +0800

    AMD Hudson: enable IMC fan control using ACPI code
    
    IMC fan control should be enabled after OS launched.
    I have tested on OliveHill and Parmer with Windows 7 and Ubuntu 13.10.
    
    Change-Id: I16d6ff6b1272d16b840e803e0a95f6e363c79704
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/7165
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 29d9c5675865e902cfd46df4b2f948c195de8884
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Oct 16 21:35:48 2014 +0300

    AMD Trinity and Kabini: fix fan control
    
    The fan can stop but can't run again. "AGESA: Call get_bus_conf() just
    once" (commit ef40ca57) results to this problem.
    This patch can resolve this problem.
    
    Change-Id: I1b5bf3f6f7a66c60743f78918dc5442cdfc8b6e4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6981
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit a10bde9048952c7a9a2f63d8450da35bbeda08c0
Author: Damien Zammit <damien@zamaudio.com>
Date:   Thu Oct 23 13:29:32 2014 +1100

    intel/sandybridge: Add VGA pci device ID 0x0162
    
    for Ivy Bridge.  Tested on Gigabyte ga-b75m-d3h.
    
    Change-Id: I7a1b1e8bac38789321960ebbe8c97d68a5aebfe2
    Signed-off-by: Damien Zammit <damien@zamaudio.com>
    Reviewed-on: http://review.coreboot.org/7173
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 36750462d2bc1e0a014888e5190bf8c364e96cd1
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 19 02:23:07 2014 +0200

    t530: Move to common gpio.h inrastructure
    
    Change-Id: I5cf6dbab64f3eda02e6418be65f21e28ddf0d9ff
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7125
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 3b9795bb2dc213c4fd73689bee7a073c19d0edf7
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Apr 8 13:34:11 2014 -0700

    libpayload: usb: Make OHCI work with ARM systems
    
    This patch enables the OHCI driver to use DMA memory, which is necessary
    for ARM systems where DMA devices are not cache coherent. I really only
    need this to test some later OHCI changes, but it was easy enough...
    copied almost verbatim from ehci.c.
    
    Change-Id: Ia717eef28340bd6182a6782e83bfdd0693cf0db1
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/193730
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit e46b6ebc439e86a00e13bf656d60cf6c186a3777)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7010
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit bedd6aff10675f77f31431adecb9dab2970ab61f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Oct 20 07:13:48 2014 +0300

    amd/torpedo amd/dinar: Sanitize agesawrapper header
    
    Change-Id: I3badb18839773e38834de967a51c29a306975d20
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7152
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 88db14d788c768f1124eb4f9c8ddff3d150e6cb6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Oct 19 23:51:33 2014 +0300

    AGESA fam15tn fam16kb: Fix missing FCH function prototypes
    
    Change-Id: I242664032d368794d828fce73a20f75ded45051d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7151
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit a4c370a3e0dad412deaf79f6a455afd4caea1c14
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Oct 22 06:42:57 2014 +0300

    amd/olivehillplus: No global variables for romstage
    
    These functions are only used for ramstage.
    
    Change-Id: I089230ca625037637c7af061b0939fd981dbdfd2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7148
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 30fbb4c23e7b867c707d61520c05cc4c6c17e174
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Oct 20 07:04:55 2014 +0300

    AGESA boards: Fix early agesawrapper_amdinitmmio()
    
    Regression introduced with commit
    
       7b23ae0 AGESA: Trace execution with AGESAWRAPPER()
    
    As the call is made before console_init() is called it must
    not call any printk(). Debugging Olivehill and Parmer platforms
    using a custom FPGA (as these boards have no Super-IO UART) have
    been observed to halt and/or delay at early boot.
    
    Change-Id: I3ab4e5378db44aece9046c8636cde1053ce5390d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7059
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>

commit 22d824b1dd63ad47dcf7cbc40ffc4990ab88c987
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Aug 19 02:12:03 2014 +0200

    macbook11: Fix typo
    
    Change-Id: Iddd4d99af7e1c70384f13f18d785f491c47c7617
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6712
    Tested-by: build bot (Jenkins)
    Reviewed-by: Francis Rowe <info@gluglug.org.uk>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit c666e55b86d353dde42461cbe4d7ae253aa2e825
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Wed Apr 2 09:14:32 2014 -0700

    libpayload: usb: xhci: Fix STALL endpoint handling
    
    - Remove the call to clear_stall in xhci_reset_endpoint because we will
      call clear_stall from the mass-storage driver.
    - Remove the xhci_reset_endpoint call from xhci_bulk on STALL since we
      will reset on the next transfer anyway.
    - Remove the clear_halt parameter from xhci_bulk since it's now unused.
    
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Change-Id: I852b87621861109e596ec24b78a8f036d796ff14
    Reviewed-on: https://chromium-review.googlesource.com/192866
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    (cherry picked from commit e67e4f0545cbdc074328c83c7edccf9e712cd7be)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7011
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 0b4e8df7e8535f30a4fe12c92032f638fc7244ab
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Wed Oct 1 11:50:20 2014 -0600

    reg_script: include in romstage
    
    The new broadwell support uses the reg_script functions in romstage.
    
    Change-Id: Ic040bf947d35854711f4c1547858b0e4378ef759
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7003
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d2044ccdc09799a5019bb6dfb42f38658b075be6
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Wed Oct 1 13:37:36 2014 -0600

    reg_script: default to n for ARCH_X86
    
    The reg_script functionality is only used by specific chipsets so have
    it selected instead of defaulting to y for ARCH_X86.
    
    Change-Id: I8fb9466e148eed7896ca8ed80755c77ba1190583
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7006
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 64982c5002994270e1fc010cc8d2119c20f62184
Author: Tom Warren <twarren@nvidia.com>
Date:   Thu Jan 23 13:37:50 2014 -0700

    tegra/nyan*: sdram updates
    
    nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU
    Reviewed-on: https://chromium-review.googlesource.com/183939
    (cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1)
    
    nyan_big: Add initial 792MHz BCT
    Reviewed-on: https://chromium-review.googlesource.com/183975
    (cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a)
    
    nyan_big: use RAM_CODE[3:2] for ram code
    Reviewed-on: https://chromium-review.googlesource.com/184076
    (cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716)
    
    tegra124: support tri-state Board Id
    Reviewed-on: https://chromium-review.googlesource.com/183855
    (cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4)
    
    nyan*: Fix SPI pinmux configuration
    Reviewed-on: https://chromium-review.googlesource.com/184281
    (cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489)
    
    nyan_big: Add 4GB 204/792MHz BCTs
    Reviewed-on: https://chromium-review.googlesource.com/184159
    (cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e)
    
    tegra124: Add function for obtaining DRAM size via MC regs
    Reviewed-on: https://chromium-review.googlesource.com/184535
    (cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48)
    
    tegra124/nyan*: Obtain DRAM size dynamically
    Reviewed-on: https://chromium-review.googlesource.com/184431
    (cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3)
    
    tegra124: Rearrange iRAM layout to allow more space for romstage
    Reviewed-on: https://chromium-review.googlesource.com/184240
    (cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc)
    
    tegra124: Fix MemoryType field name in SDRAM parameters.
    Reviewed-on: https://chromium-review.googlesource.com/185113
    (cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97)
    
    nyan_big: Initialize SDRAM without BootROM.
    Reviewed-on: https://chromium-review.googlesource.com/183624
    (cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70)
    
    tegra124: move FB_SIZE_MB to a more appropriate location
    Reviewed-on: https://chromium-review.googlesource.com/184930
    (cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc)
    
    nyan: Initialize SDRAM without BootROM.
    Reviewed-on: https://chromium-review.googlesource.com/185114
    (cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b)
    
    tegra124: Save SDRAM parameters to PMC registers for LP0
    Reviewed-on: https://chromium-review.googlesource.com/182928
    (cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86)
    
    tegra124: Rewrite SDRAM parameter saving code to be more efficient
    Reviewed-on: https://chromium-review.googlesource.com/184388
    (cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6)
    
    nyan: Slightly change the way SDRAM parameter files are set up
    Reviewed-on: https://chromium-review.googlesource.com/185286
    (cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d)
    
    Squashed 16 commits for SDRAM support on nyan and nyan_big.
    
    Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6949
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit b3f08c61f15970ef3d9e197b02d6dedb8b2c5830
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Apr 30 17:12:25 2014 -0700

    cmos: Rename the CMOS related functions.
    
    Most of the code related to the mc146818 is not related to the RTC and is
    really for managing the CMOS storage. Since we intend to add a generic API
    for RTC drivers it's inconvenient for those functions to have an rtc_ prefix.
    This CL renames those functions so they start with cmos_ instead. There are
    some places where rtc_init was called with a comment that says something about
    starting the RTC. That wasn't correct before (the RTC is always running), but
    it looks a little odd now that the function is called cmos_init.
    
    This CL also opportunistically cleans up some style problems in this file.
    
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/197794
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 9a9ad24888b185fb58965457704e326bb508d788)
    
    Removed the addition of stdint.h to mc146818rtc.h since
    types.h is now included. Changed rtc_init to cmos_init for
    fsp_bd82x6x, fsp_rangeley, fsp_baytrail, ibexpeak, vortex86ex.
    
    Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6977
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 6dbc680a90353a5ac5553ca5686af6220f61191e
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Mar 27 20:50:25 2014 -0700

    spi: Remove unused constants from spi-generic.h.
    
    These constants aren't used anywhere.
    
    Change-Id: Ifdad9b088a281909892edb34dcb58419e0e123ba
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/192047
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 3cdaf9dd7de6ae71efc9e74335d876ec55f9ca0a)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7008
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 3f5644593de7ff5583595028896866fc91eaddca
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Mar 26 21:51:41 2014 -0700

    tpm: i2c: When probing the TPM, write a 0 into the TPM access register.
    
    Not doing so makes it fail when run at high frequency.
    
    Change-Id: I1cfb69c55f03cb90f66f437289803d897a1aad5c
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/191812
    Reviewed-by: Tom Warren <twarren@nvidia.com>
    Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: Tom Warren <twarren@nvidia.com>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 04452441d2bfe2cacd3e0b6990c0e9261b5350d1)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7007
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 1b969f672e84c1e96439943995376e6cd944cbfe
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 15 16:23:40 2014 -0700

    broadwell: Update Haswell and Broadwell E0 microcode
    
    Broadwell D0 updated to 0x10 (debug)
    Broadwell E0 updated to 0xD
    Haswell updated to 0x1C
    
    Change-Id: Ib3e27b3467fec1106c69d82c0b1522d58025d67e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/208212
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 048a8b68dbc79dd27dc3188dde407a95c4d729fc)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6984
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c09396785cb0cea0dbb251cb33cf25545a7abba9
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 21 14:54:41 2014 +0800

    broadwell: Update microcode
    
    40651: rev 00000018
    306D3: rev FFFF000F
    306D4: rev 00000009
    
    Change-Id: I47a6caadc83f0ed96b0a4b0c624ad105d9dee3b6
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/204819
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit f8f0703c7042a14c6807cbea74eae6e85ba6854e)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6983
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 61680274c1ded5ea095b15b689f83d5d670d2aae
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon May 5 12:42:35 2014 -0500

    broadwell: ACPI, romstage, and other updates
    
    broadwell: Add romstage usbdebug support
    Reviewed-on: https://chromium-review.googlesource.com/199412
    (cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5)
    
    broadwell: Add romstage code to configure PCH UART for console
    Reviewed-on: https://chromium-review.googlesource.com/199807
    (cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a)
    
    broadwell: Expand the PCI device convenience macros
    Reviewed-on: https://chromium-review.googlesource.com/199891
    (cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad)
    
    broadwell: Add ramstage driver for ADSP
    Reviewed-on: https://chromium-review.googlesource.com/199892
    (cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f)
    
    broadwell: Update ACPI devices
    Reviewed-on: https://chromium-review.googlesource.com/201080
    (cherry picked from commit 2446b35578eb36e0009415bec340059135751549)
    
    broadwell: Reserve DPR region
    Reviewed-on: https://chromium-review.googlesource.com/201081
    (cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6)
    
    broadwell: Remove old pei_data and add cpu function for romstage
    Reviewed-on: https://chromium-review.googlesource.com/201690
    (cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274)
    
    broadwell: Fixes for graphics without executing VBIOS
    Reviewed-on: https://chromium-review.googlesource.com/202356
    (cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa)
    
    broadwell: Fix compilation failure when loglevel is lowered
    Reviewed-on: https://chromium-review.googlesource.com/202357
    (cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc)
    
    broadwell: Disable GPIO controller interrupt
    Reviewed-on: https://chromium-review.googlesource.com/203645
    (cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9)
    
    broadwell: Add support for E0 stepping
    Reviewed-on: https://chromium-review.googlesource.com/205160
    (cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273)
    
    broadwell: misc updates for CPU driver
    Reviewed-on: https://chromium-review.googlesource.com/205161
    (cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97)
    
    broadwell: Read power state earlier and store in romstage params
    Reviewed-on: https://chromium-review.googlesource.com/208151
    (cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e)
    
    broadwell: Add parameters to pei_data structure
    Reviewed-on: https://chromium-review.googlesource.com/208153
    (cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af)
    
    broadwell: Move platform report output after power state is read
    Reviewed-on: https://chromium-review.googlesource.com/208213
    (cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78)
    
    Squashed 15 commits for broadwell support.
    
    Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6982
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit e256295218266325a77e8b6a207e71bedd9a9359
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu May 1 09:07:53 2014 -0700

    broadwell: Update D0 microcode to FFFF000E
    
    New microcode released this week.
    
    Change-Id: I426d0e00d1c03650049cbe033b53a909a7d944c9
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/198896
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 63ec6438b566d14a2b878474ca068cf70d9aa9d6)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6966
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 842bcd3c723796ca9392b9e561f138f94b1bfb2b
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu May 1 09:07:53 2014 -0700

    broadwell: Update microcode for supported CPUs
    
    This broadwell implementation will support Haswell ULT in
    addition to broadwell CPUs.  Add the latest available microcode
    for the broadwell C0 and D0 parts as well as Haswell ULT.
    
    Change-Id: I1beb71e0e28af3508e2260751b6fdfe47d53d90d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/198742
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 69d5b7c834a4f52656ab14562ea913477418e588)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6965
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit c88c54c667124851eb82c5271536fd0f4ad6616c
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Apr 30 16:36:13 2014 -0700

    broadwell: add new intel SOC
    
    broadwell: Import files from haswell/lynxpoint into soc/broadwell
    Reviewed-on: https://chromium-review.googlesource.com/198425
    (cherry picked from commit 178400e5709d676dd41e6a75df06faa829e0e3af)
    
    broadwell: Unify and clean up license
    Reviewed-on: https://chromium-review.googlesource.com/198426
    (cherry picked from commit 30d3c25a0abc76be68477c39a654b95a5975f55d)
    
    broadwell: pch.h: split PM into new header
    Reviewed-on: https://chromium-review.googlesource.com/198427
    (cherry picked from commit 97a8d0b051f476d0edc06301f57326a718df1373)
    
    broadwell: pch.h: split RCBA into new header
    Reviewed-on: https://chromium-review.googlesource.com/198428
    (cherry picked from commit fa217361b28fdb8d3a3e85f070dfaf13c0d48135)
    
    broadwell: pch.h: split SATA into new header
    Reviewed-on: https://chromium-review.googlesource.com/198429
    (cherry picked from commit bf8795ca92f9f0467e7869c701038abb4529ac71)
    
    broadwell: pch.h: split SPI into new header
    Reviewed-on: https://chromium-review.googlesource.com/198550
    (cherry picked from commit 099af14676a2654ca3e24e66d7b9f0b4ab13cd14)
    
    broadwell: pch.h: split SerialIO into new header
    Reviewed-on: https://chromium-review.googlesource.com/198551
    (cherry picked from commit 4f3c028686aed78fb07b8792dcf46aebd2268ea6)
    
    broadwell: pch.h: split LPC into new header
    Reviewed-on: https://chromium-review.googlesource.com/198552
    (cherry picked from commit 10bad5bbb6739c0277fd5330d26a89d60fd5c102)
    
    broadwell: pch.h: split GPIO into new header and clean up
    Reviewed-on: https://chromium-review.googlesource.com/198553
    (cherry picked from commit 9c97532460562215b78e10b011a29e092a07f3e5)
    
    broadwell: pch.h: split USB into new headers
    Reviewed-on: https://chromium-review.googlesource.com/198554
    (cherry picked from commit 86ef1a45a2e5f307467b3be48e377569f37b3068)
    
    broadwell: Split IOBP into separate files
    Reviewed-on: https://chromium-review.googlesource.com/198734
    (cherry picked from commit f93b8bda71728f1383937ad675d2d5fb5a927600)
    
    broadwell: smbus: Extract common code and split header
    Reviewed-on: https://chromium-review.googlesource.com/198735
    (cherry picked from commit 8052030a9d6b22e8a19938fa9b93e90d08f0057d)
    
    broadwell: Create iomap.h header with platform base addresses
    Reviewed-on: https://chromium-review.googlesource.com/198736
    (cherry picked from commit b35947d070b28871637dfe2b930a9f2be80958ee)
    
    broadwell: Add header for platform PCI devices
    Reviewed-on: https://chromium-review.googlesource.com/198737
    (cherry picked from commit 6ac4e56db6e489bb9eaf91a0c3c543399f691500)
    
    broadwell: Split SMM related defines/prototypes to new header
    Reviewed-on: https://chromium-review.googlesource.com/198738
    (cherry picked from commit 2a2595067077cd918bfd48cad79a684b8e1ff0f4)
    
    broadwell: cpu.h: Split MSR defines to separate header
    Reviewed-on: https://chromium-review.googlesource.com/198739
    (cherry picked from commit 01148cd2c9edd97cd0c8ef3cfed58bc8c33eb805)
    
    broadwell: Create romstage header file
    Reviewed-on: https://chromium-review.googlesource.com/198740
    (cherry picked from commit 31c91e811b9e07e7bcba6b9f8f5720a31322eb21)
    
    broadwell: Create ram stage header file
    Reviewed-on: https://chromium-review.googlesource.com/198741
    (cherry picked from commit 93dde85f98d43d4a1886b59004d1bab4924ad621)
    
    broadwell: Add reference code data interface
    Reviewed-on: https://chromium-review.googlesource.com/198743
    (cherry picked from commit 9059b8e2308892a48c838c3099404c9cf450df95)
    
    broadwell: Clean up ACPI NVS region
    Reviewed-on: https://chromium-review.googlesource.com/198897
    (cherry picked from commit d83cc82c36661556eb1e2e437b7ac51d5b8e4a14)
    
    broadwell: Move CTDP ACPI methods to new file
    Reviewed-on: https://chromium-review.googlesource.com/198898
    (cherry picked from commit fc1e711290df304d18c558d697eea8a5e57061b2)
    
    broadwell: Split EHCI and XHCI ACPI devices
    Reviewed-on: https://chromium-review.googlesource.com/198899
    (cherry picked from commit 26f437b27e00dbd5c92ea22e76404633a62fb7ca)
    
    broadwell: ACPI: Clean up SerialIO ACPI code
    Reviewed-on: https://chromium-review.googlesource.com/198910
    (cherry picked from commit ea3cd39566c1bb2ead463a6253b6204a62545d35)
    
    broadwell: ACPI: Remove special handling of LPT-LP chipset
    Reviewed-on: https://chromium-review.googlesource.com/198911
    (cherry picked from commit 2c54df159bf6759c8f866628e83541de6f4e28f6)
    
    broadwell: ACPI: Clean up use of base address defines
    Reviewed-on: https://chromium-review.googlesource.com/198912
    (cherry picked from commit 34e4788955bceff01631fd0b4dbf0aa24cf56b75)
    
    broadwell: ACPI: Clean up and fix formatting
    Reviewed-on: https://chromium-review.googlesource.com/198913
    (cherry picked from commit bc0f7c6d2f95681eb987bb6ff6baf2d16cc77050)
    
    broadwell: Add header for ACPI defines and prototypes
    Reviewed-on: https://chromium-review.googlesource.com/198914
    (cherry picked from commit 9951e7931942d2921f92f6e094b1cc32c190eab9)
    
    broadwell: Add reset_system function and header
    Reviewed-on: https://chromium-review.googlesource.com/198915
    (cherry picked from commit 6d1efb94bd39bcd6f7e3e0de2f3299a384b109ef)
    
    broadwell: Move PCODE MMIO defines to systemagent.h
    Reviewed-on: https://chromium-review.googlesource.com/198916
    (cherry picked from commit abb5f87e548fbde3a08e14a18714b4e4391c955f)
    
    broadwell: Unify chip.h and add chip.c
    Reviewed-on: https://chromium-review.googlesource.com/198917
    (cherry picked from commit a9c2d7ff3afa1e2a10be85ccc72b7db0f2aaafe1)
    
    broadwell: Rename HASWELL_BCLK to CPU_BCLK
    Reviewed-on: https://chromium-review.googlesource.com/198918
    (cherry picked from commit 65ac1a07abaf14eb42fec6c5df67d2d3688ad5a1)
    
    broadwell: Clean up broadwell/cpu.h
    Reviewed-on: https://chromium-review.googlesource.com/198919
    (cherry picked from commit 17353803babc8ace279e105c012130678226144e)
    
    broadwell: Clean up broadwell/systemagent.h
    Reviewed-on: https://chromium-review.googlesource.com/198920
    (cherry picked from commit 49d7a023f3ff04a65d16622aa9b2fa6004b693ae)
    
    broadwell: Clean up broadwell/pch.h
    Reviewed-on: https://chromium-review.googlesource.com/198921
    (cherry picked from commit 17da652b4408a91fcfea99dd35fe9f9e1bdcf03b)
    
    broadwell: Clean up management engine driver
    Reviewed-on: https://chromium-review.googlesource.com/198922
    (cherry picked from commit 4fce5fbb56dc4f31b77e5ada05463c043ad5be72)
    
    broadwell: Add common CPUID and PCI Device ID defines
    Reviewed-on: https://chromium-review.googlesource.com/198923
    (cherry picked from commit c6bf20309f33168ea2cc4634cbda5ec242824ba8)
    
    broadwell: Clean up and expand report_platform
    Reviewed-on: https://chromium-review.googlesource.com/198924
    (cherry picked from commit 5082d4824db149e867a2cd8be34c932b03754022)
    
    broadwell: Clean up the bootblock code
    Reviewed-on: https://chromium-review.googlesource.com/198925
    (cherry picked from commit ba0206ab76fe0b6834a14dc57f400d139094623c)
    
    broadwell: Clean up ramstage device and driver operations
    Reviewed-on: https://chromium-review.googlesource.com/199180
    (cherry picked from commit d8fc9daf129738713a5059286b7ead004f3b7569)
    
    broadwell: Clean up XHCI and EHCI ramstage drivers
    Reviewed-on: https://chromium-review.googlesource.com/199181
    (cherry picked from commit d355247333a828a146ce7cf9b92a63da74119c1d)
    
    broadwell: Clean up gpio handling code
    Reviewed-on: https://chromium-review.googlesource.com/199182
    (cherry picked from commit d62cef1970fe75f8166315016b3d8415cddcab20)
    
    broadwell: Clean up the PCH generic code
    Reviewed-on: https://chromium-review.googlesource.com/199183
    (cherry picked from commit 3b93b3ea79965d5ac831bf9015e49330f157b0ff)
    
    broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c
    Reviewed-on: https://chromium-review.googlesource.com/199184
    (cherry picked from commit 68955ba4ff8b49ff466d7badaa934bd143026ba7)
    
    broadwell: Clean up pmutil.c
    Reviewed-on: https://chromium-review.googlesource.com/199185
    (cherry picked from commit b6fb672ae879e17422f7449f70c3669055096f84)
    
    broadwell: pmutil: Add new acpi_sci_irq() function
    Reviewed-on: https://chromium-review.googlesource.com/199186
    (cherry picked from commit 80ad8bb9bdc75f180e667861fed42a3844226bc5)
    
    broadwell: Clean up HDA ramstage driver
    Reviewed-on: https://chromium-review.googlesource.com/199187
    (cherry picked from commit b4962acd706eaa66c1c3ef4d22eba313642fbb2d)
    
    broadwell: Clean up cache_as_ram assembly
    Reviewed-on: https://chromium-review.googlesource.com/199188
    (cherry picked from commit 8a457b82610b604ae7f69e2500815ce411c2d02d)
    
    broadwell: romstage: Separate stack helper functions
    Reviewed-on: https://chromium-review.googlesource.com/199189
    (cherry picked from commit c220383c90466fc2dbf4b6107679b08ecb4aadad)
    
    broadwell: Add function to read WPSR from SPI
    Reviewed-on: https://chromium-review.googlesource.com/199190
    (cherry picked from commit 935404da1157d606b913eff6c2635ae898e9980a)
    
    broadwell: Clean up SMBUS code in romstage and ramstage
    Reviewed-on: https://chromium-review.googlesource.com/199191
    (cherry picked from commit 6ae9d93c1a6f14da6429a4e5b01619c9ccaefdaa)
    
    broadwell: SPI: Clean up romstage and ramstage code
    Reviewed-on: https://chromium-review.googlesource.com/199192
    (cherry picked from commit 28ffd71a416aee2ab54bc5d782cfeef31d4d30bf)
    
    broadwell: Clean up PCIe root port ramstage driver
    Reviewed-on: https://chromium-review.googlesource.com/199193
    (cherry picked from commit 781f3a1b72c72f0bb05f5524edec471ad13ec90e)
    
    broadwell: Clean up minihd ramstage driver
    Reviewed-on: https://chromium-review.googlesource.com/199194
    (cherry picked from commit a52d275e41fdcbf9895d07350725609d9be1ff0e)
    
    broadwell: Update romstage main to follow baytrail format
    Reviewed-on: https://chromium-review.googlesource.com/199361
    (cherry picked from commit 0678c739af84c871922ffba5594132b25e471ddd)
    
    broadwell: Add CPU set_max_freq function for romstage
    Reviewed-on: https://chromium-review.googlesource.com/199362
    (cherry picked from commit 68b0122472af27f38502d42a8a6c80678ddbbba6)
    
    broadwell: romstage: Add chipset_power_state implementation
    Reviewed-on: https://chromium-review.googlesource.com/199363
    (cherry picked from commit 761cec3b6bb9bde579c3214f3f1196f65700757c)
    
    broadwell: romstage: Convert systemagent init to reg_script
    Reviewed-on: https://chromium-review.googlesource.com/199364
    (cherry picked from commit c2ea2d3a0c7555a353fb9a1d4a63e773ac8961b2)
    
    broadwell: romstage: Convert pch init to reg_script
    Reviewed-on: https://chromium-review.googlesource.com/199365
    (cherry picked from commit 4383de5846e97ca5aee6dd210459d8dba0af981c)
    
    broadwell: elog: Use chipset_power_state for events
    Reviewed-on: https://chromium-review.googlesource.com/199366
    (cherry picked from commit 0ef5961ebe3a7037d5fbe361fbc70a87ac2edad9)
    
    broadwell: Clean up SATA ramstage driver
    Reviewed-on: https://chromium-review.googlesource.com/199367
    (cherry picked from commit ffa5743f74551bd48aa7e5445ce7cd9dc7b07ce8)
    
    broadwell: Update ramstage graphics driver to support broadwell
    Reviewed-on: https://chromium-review.googlesource.com/199368
    (cherry picked from commit bb01deb8bbed56f15e1143504e4cf012ecf5a281)
    
    broadwell: Update raminit to follow baytrail layout
    Reviewed-on: https://chromium-review.googlesource.com/199369
    (cherry picked from commit 3f25c23dc58f85d2521916cd6edbe9deeeb8d523)
    
    broadwell: Update and unify the finalize steps
    Reviewed-on: https://chromium-review.googlesource.com/199390
    (cherry picked from commit ddc4c116b42d38dfdfc45ef4388fbfab32ca48fa)
    
    broadwell: Clean up SMM code
    Reviewed-on: https://chromium-review.googlesource.com/199391
    (cherry picked from commit 8295e56c9b643fd4b9267d70b5efd0cf94dd67dd)
    
    broadwell: Clean up LPC ramstage driver
    Reviewed-on: https://chromium-review.googlesource.com/199392
    (cherry picked from commit 28326aeaaf304c9262866588d91b79b37d1d9a2e)
    
    broadwell: Clean up systemagent ramstage driver
    Reviewed-on: https://chromium-review.googlesource.com/199393
    (cherry picked from commit 749988fff07eab8d2c9ebc731e3ed9e427b3f7b3)
    
    broadwell: Move C-state configuration information to acpi.c
    Reviewed-on: https://chromium-review.googlesource.com/199394
    (cherry picked from commit 198a3cd5cbd009be406298cbb53163f075fe9990)
    
    broadwell: Clean up CPU ramstage driver
    Reviewed-on: https://chromium-review.googlesource.com/199395
    (cherry picked from commit 8159689bba479bab6fd2e949e3e1c3f817088969)
    
    broadwell: Do not reserve SMM relocation region
    Reviewed-on: https://chromium-review.googlesource.com/199402
    (cherry picked from commit e2ab52340e3d3a97a3f8dbdad8fac9f7769d1b4c)
    
    broadwell: Add an early ramstage driver
    Reviewed-on: https://chromium-review.googlesource.com/199403
    (cherry picked from commit c7a8c867101b49a7f9f17ec1a8777a8db145f3e3)
    
    broadwell: Support for second reference code binary
    Reviewed-on: https://chromium-review.googlesource.com/199404
    (cherry picked from commit abb99b36e97c4f739b23abed6146fea370bbbec2)
    
    broadwell: Clean up serialio init code
    Reviewed-on: https://chromium-review.googlesource.com/199405
    (cherry picked from commit e09a1f8520a7b72451a1e2068b200f7c5451f489)
    
    broadwell: acpi: Add function to fill out FADT
    Reviewed-on: https://chromium-review.googlesource.com/199406
    (cherry picked from commit 7e58f43e46d4382cf4541057f81fe6be3e4d6e74)
    
    broadwell: Update C-state table creation
    Reviewed-on: https://chromium-review.googlesource.com/199407
    (cherry picked from commit 68b1f70e32e1d0c6fc4332dce402ad78334e0063)
    
    broadwell: acpi: Clean up acpi table creation code
    Reviewed-on: https://chromium-review.googlesource.com/199408
    (cherry picked from commit 49088b312b159bb17a9330eda6a88d6f324ea146)
    
    broadwell: acpi: Add ACPI table create helper functions
    Reviewed-on: https://chromium-review.googlesource.com/199409
    (cherry picked from commit 344c3c511d0341457525ef4d6eb70201404fc62c)
    
    broadwell: Add soc/intel/broadwell Makefiles
    Reviewed-on: https://chromium-review.googlesource.com/199410
    (cherry picked from commit ea8f97738eadd3b0b6a642754df7a7d22e547ffc)
    
    broadwell: Add Kconfig for broadwell soc
    Reviewed-on: https://chromium-review.googlesource.com/199411
    (cherry picked from commit 8c99038a5c20812497619134c66d45bc4f21c8fe)
    
    Squashed 78 commits for broadwell that form a solid code base.
    
    Change-Id: I365ca9a45978b5e0cc5237f884e20a44f62a0e63
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6964
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit f0aaa29989f4de7258430715d64c6d465fb0c457
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Apr 22 10:48:29 2014 -0700

    baytrail: Move HDA verb table to Intel SOC common directory
    
    This is common code for Intel SOC that can be shared.
    
    Change-Id: Ic703f36f56a8238d5cc1248b353d8c3a49827a9a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/196264
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 3a9057b9616c54a8404eee55511743d2492dbc28)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6968
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit d8c4f2b72462f60ae92a59a976437c2407ec6654
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Apr 22 10:46:06 2014 -0700

    baytrail: Move MRC cache code to a common directory
    
    This common code can be shared across Intel SOCs.
    
    Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/196263
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6967
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 3511023f341b4416ea61558bd5ecfa2ea8416782
Author: Kein Yuan <kein.yuan@intel.com>
Date:   Sat Feb 22 12:26:55 2014 -0800

    baytrail/rambi: S3 support and other updates
    
    baytrail: Change all GPIO related pull resistors from 10K to 20K
    Reviewed-on: https://chromium-review.googlesource.com/187570
    (cherry picked from commit 762e99861dd1ae61ddcf1ebdec8e698ede54405e)
    
    baytrail: workaround kernel using serial console on resume
    Reviewed-on: https://chromium-review.googlesource.com/188011
    (cherry picked from commit b0da3bdb5b6b417ad6cab0084359d4eae1cb4469)
    
    baytrail: allow dirty cache line evictions for SMRAM to stick
    Reviewed-on: https://chromium-review.googlesource.com/188015
    (cherry picked from commit 50fb1e6a844e1db05574c92625da23777ad7a0ca)
    
    baytrail: Optionally pull up TDO and TMS to avoid power loss in S3.
    Reviewed-on: https://chromium-review.googlesource.com/188260
    (cherry picked from commit e240856609b4eed5ed44ec4e021ed385965768d6)
    
    rambi: always load option rom
    Reviewed-on: https://chromium-review.googlesource.com/188721
    (cherry picked from commit d8a1d108548d20755f8683497c215e76d513b7a9)
    
    baytrail: use new chromeos ram oops API
    Reviewed-on: https://chromium-review.googlesource.com/186394
    (cherry picked from commit f38e6969df9b5453b10d49be60b5d033d38b4594)
    
    rambi: always show dev/rec screens on eDP connected panel
    Reviewed-on: https://chromium-review.googlesource.com/188731
    (cherry picked from commit 7d8570ac52f68492a2250fa536d55f7cbbd9ef95)
    
    baytrail: stop e820 reserving default SMM region
    Reviewed-on: https://chromium-review.googlesource.com/189084
    (cherry picked from commit 6fce823512f5db5a09a9c89048334c3524c69a24)
    
    baytrai: update MRC wrapper header
    Reviewed-on: https://chromium-review.googlesource.com/189196
    (cherry picked from commit 36b33a25b6603b6a74990b00d981226440b68970)
    
    rambi: Put LPE device into ACPI mode
    Reviewed-on: https://chromium-review.googlesource.com/189371
    (cherry picked from commit 5955350cd57fd1b3732b6db62911d824712a5413)
    
    baytrail: DPTF: Enable mainboard-specific PPCC
    Reviewed-on: https://chromium-review.googlesource.com/189576
    (cherry picked from commit 27fae3e670244b529b7c0241742fc2b55d52c612)
    
    baytrail: Add config option for PCIe wake
    Reviewed-on: https://chromium-review.googlesource.com/189994
    (cherry picked from commit 1cc31a7c021ec84311f1d4e89dd3e57ca8801ab5)
    
    rambi: Enable PCIe wake
    Reviewed-on: https://chromium-review.googlesource.com/189995
    (cherry picked from commit c98ae1fee54cfb2b3d3c21a19cdbbf56a0bfa1e6)
    
    Squashed 13 commits for baytrail/rambi.
    
    Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6957
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit a8cfb255fb7fc35ad6659a0c0225cbb915b67935
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 19 02:24:16 2014 +0200

    x220: Move to common gpio.h inrastructure
    
    Change-Id: Ic9734bf2672942a09f2136b0c066f2eda58486d9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7126
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 47432544242e025b151ed56739f6cf6cbdfd3f94
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 5 14:54:26 2014 +0200

    amd: rename model_fxx_powernow to powernow.
    
    Change-Id: Iee581183f9cd9f5fecd5604536b735f6a04a0f93
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7019
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit a3bdbcc11e9f2d9a83c0ee0a7cfc4fa318341c03
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 5 14:08:28 2014 +0200

    e7501: Move to perdev ACPI
    
    Change-Id: Ic8472745c2ff0c68fd63b51d1a149a11be1650e9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7047
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 26f297e98109d8dd6e09dcb69ec371463732e464
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon May 26 11:27:54 2014 +0300

    AGESA: Drop board and chipset -specific callout headers
    
    Change-Id: If973f28931e65a57cbb8d6739542a57c844f0d66
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7115
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 50c9637e15ddd78f896419f2335457de4fe22d77
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Oct 18 07:51:03 2014 +0300

    AGESA fam12 fam14 fam15: Sanitize BiosCallOuts headers
    
    Change-Id: Ic08f1f2fdbcf6164eb1a0330f9134da3fdb978d7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7114
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit a1ebbc42ad791369c2e4f626e46917bdb1459d72
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 17 22:33:22 2014 +0300

    AGESA fam12 fam14 fam15: Use common agesa_readSpd()
    
    Remove northbridge specific callouts for AGESA_READ_SPD.
    
    Move low-level SMBus code to southbridge.
    
    Change-Id: I5fc91c49d9ef8e0af1c4d8194f857c61ce417d1d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7113
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit c5cc9f233c9b2a1decf57b6e51438d03152fe54e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 17 22:33:22 2014 +0300

    AGESA fam15tn fam16kb 00730f01: Add common agesa_readSpd()
    
    Remove northbridge specific callouts for AGESA_READ_SPD.
    
    Move low-level SMBus code to southbridge.
    
    Change-Id: I3e272389e2a7db542fb48fca8606325af27b65a5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7112
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f5f9e38d124d97698cc1c6dad3219d6834902203
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 17 23:21:01 2014 +0300

    AGESA: Declare callout Fch_Oem_config static
    
    Change-Id: If5c62b868c4144845d79dc26068c500ab5d26947
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7111
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 7b14f08f45f54bc36510e4b12febc1831cd744ef
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Oct 16 20:58:47 2014 +0300

    ACPI: Allocate S3 resume backup in CBMEM earlier
    
    These allocations are not really part of write_tables() and the move
    opens possibilities to use CBMEM instead of SPI Flash to restore some
    parts of system state after S3 resume.
    
    Change-Id: I0c36bcee3f1da525af077fc1d18677ee85097e4d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7097
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 1729cd85744129104e3e41aac1f18e43b62f79ff
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Oct 16 12:47:25 2014 +0300

    x86 romstage: Move stack just below RAMTOP
    
    Placement of romstage stack in RAM was vulnerable for getting corrupted
    by decompressed ramstage.
    
    Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7096
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit d05d0db0d0cb76776addbd75d264e713dda47880
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Oct 16 14:54:03 2014 +0300

    haswell baytrail: Enable RELOCATABLE_RAMSTAGE
    
    Change-Id: I84ee953196ae9bed3392c2b9bab2e8d9f0d27908
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7095
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 1b409fd132f20f5f67f5717675a639683e6da61f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 12 00:26:21 2014 +0200

    lynxpoint: Consolidate common GNVS init
    
    Change-Id: Ie8e4fffcec308d1cd5e696605e78671f3ababf40
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7054
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit b6200969ec931db8a7805b899d16fde139309f6e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Sep 1 23:27:09 2014 +0200

    via/vt8454c: Migrate to per-device ACPI
    
    Change-Id: Ia3f6691ae7c33b5e22010e25a1f01996a594196e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6943
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 9a0b251680cf4aa9dbacde9c60d8579da81ed404
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Sep 1 22:35:20 2014 +0200

    i3100: Convert to per-device ACPI
    
    Change-Id: Id90db4f6ce1a5fb506c81bc3a6010d85b0aa8c43
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6940
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 6c71a684a43dfd05e8d4043039ee0ee621526461
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Sep 2 00:15:02 2014 +0200

    via/vx800: Migrate to collaborative ACPI
    
    Change-Id: I00d0d0e2556d4cd0553a2b3351ace26bf747ff6a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6944
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit e7ff9d8839b0f7718f208f31bb7e7e504a97c657
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Oct 10 09:38:44 2014 +0200

    fsp_sandybridge: Move to per-device ACPI.
    
    Just took combined sandybridge per-device ACPI patch and applied it
    on FSP flavour to avoid need of separate tests.
    
    Change-Id: I09838cc01ede504416078edcb1c267a11539e714
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7044
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit e6e5b5ef556904ab5d03f7b6f750b4d25df961f4
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 02:21:43 2014 +0200

    sch: Switch to per-device ACPI
    
    Change-Id: I4cf0a67b0251d2d3adff5de74bf56b7d4c4524ee
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6811
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 2fc0a1d457901171cc226390925f0a6320821549
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Oct 18 11:19:28 2014 +0000

    cimx/sb800: fix pedantic gcc error
    
    A cast did not work for me, but this variable did.
    This is one of the many issues with building e3501 I'm
    running into.
    
    Change-Id: Ifb19a17770604f2d63dfef762d08200add77ee34
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/7122
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 1ab4495204b5bfe145edb5f1d0cac0a7017d79f0
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Sep 29 19:40:51 2014 +0200

    intel/i82801bx: Minor log fixes in IDE driver
    
    Two issues:
    1. without config, there were two NULL derefs
    2. output for "Secondary" looked at ide0_enable
    
    Change-Id: I34ddbc0f9b27226981ccbc237e3d59e522076d55
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6989
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 667c7a3b23e154254a4b91286cbb0f6aedf4c410
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Sep 29 10:12:29 2014 +0200

    util/fletcher: fix debug option parsing
    
    sizeof(char[]-type+1) isn't very useful. Since one of
    the strings is constant, we also don't need to use
    strncmp that string's length. While at it, str*cmp don't
    return booleans, so check for value instead of faux bools.
    
    Change-Id: Iebb194a60eac454dafeade75f135df92068cf4ab
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6988
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 02802dfa5a7dcc4b848e52123efaf3da2a17b295
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Oct 18 11:57:11 2014 +0200

    abuild: skip boards for which we lack a cross compiler
    
    We don't support them, they won't ever pass the build test,
    so no need to report an error.
    
    Change-Id: I2409a79f3c0d66a79b0e065e6b9ebf62d0359b3e
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/7121
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0a76bccc947b4d1de0a87cf3a19efd79fce22d3c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Oct 18 11:32:18 2014 +0200

    abuild: don't track architecture
    
    This didn't work for a while, and we don't _really_ need it.
    
    Change-Id: I952243f30e985e7577cd511f40957066db6dd3c5
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/7120
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f0bd87153139e92fbcfa76b8fcab4558ce3cd52e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Sep 29 20:23:29 2014 +0200

    various AMD boards: fix buffer overflow
    
    "AMD\t " isn't 8 characters long.
    
    Change-Id: I47b2a39d7dca0201b7ee5dfd1f77e0714411257c
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6991
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>

commit 96990a285d775520c6279603371a1394bcdd8cd3
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Sep 29 10:08:35 2014 +0200

    cbfstool: free memory
    
    Change-Id: Ic53127a61154460fa3741a92a3b2de0eba446e9f
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6987
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 747c07f08a839f5b2b6220f2e61fdf99b9ff35eb
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Oct 17 13:46:12 2014 +0200

    util/cbmem: Fix CBMEM TOC printing
    
    Since commit c0199078 (cbmem utility: Find actual CBMEM area) [1], at least on
    the Lenovo X201, X230 and X60, printing the CBMEM table of contents did
    not work.  It still worked on the ASRock E350M1 though.
    
    	$ sudo /src/coreboot/util/cbmem/cbmem -l --verbose # Lenovo X60t
    	Looking for coreboot table at 0
    	Mapping 1MB of physical memory at 0x0.
    	Found!
    	  coreboot table entry 0x11
    	    Found forwarding entry.
    	Unmapping 1MB of virtual memory at 0xb74dc000.
    	Looking for coreboot table at 7f6c4000
    	Mapping 1MB of physical memory at 0x7f6c4000.
    	Found!
    	  coreboot table entry 0xc8
    	  coreboot table entry 0x01
    	    Found memory map.
    	  coreboot table entry 0x03
    	  coreboot table entry 0x04
    	  coreboot table entry 0x05
    	  coreboot table entry 0x06
    	  coreboot table entry 0x07
    	  coreboot table entry 0x08
    	  coreboot table entry 0x09
    	  coreboot table entry 0x0a
    	  coreboot table entry 0x16
    	    Found timestamp table.
    	      cbmem_addr = 7f7dd000
    	  coreboot table entry 0x17
    	    Found cbmem console.
    	      cbmem_addr = 7f7de000
    	Unmapping 1MB of virtual memory at 0xb74dc000.
    	No coreboot CBMEM area found!
    
    The address of the boot info record has to be used for checking, that reading
    takes place in the bounds of the boot info record.
    
    	$ sudo ~/src/coreboot/util/cbmem/cbmem -l # Lenovo X60
    	CBMEM table of contents:
    	    ID           START      LENGTH
    	[…]
    
    Big thanks to David and Stefan for their help.
    
    [1] http://review.coreboot.org/2117
    
    Change-Id: I1eb09a6445d9ea17e1e16b6866dece74315d3c73
    Found-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/7093
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit c7310d977ad6cafcc3a9f9ecfd7bfb7472ef8671
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Sep 1 09:45:05 2014 +0200

    e7505: Move to per-device ACPI
    
    Change-Id: I706891b9408cf14b559ef228766c04e98345ff6e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6938
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c21e07385f9b4048d6ddb67989b23999f566951d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Oct 16 12:48:19 2014 +0200

    i945: Consolidate FADT code
    
    Change-Id: I076cba7d21926cabf90d485de50268ae40c435f3
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7087
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit e4626bfc5be5f61f62af32733cbe551275094dd5
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Oct 17 12:54:13 2014 +0200

    util/cbmem/cbmem: Remove obsolete comment
    
    Originally the utility cbmem was just used for reading out the time
    stamps and was later extented. The removed comment is currently at the
    wrong place and `cbmem` does much more now, so that the comment is just
    removed.
    
    Change-Id: Ief1d7aef38a4b439e3e224e6e6c65f7aa57f821f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/7091
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Tested-by: build bot (Jenkins)

commit 30d0aa9cdb43f24275869456b3688d066f280e0e
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Fri Oct 17 12:08:05 2014 +0200

    lenovo/t520: Use native raminit over MRC blob
    
    Native raminit for sandy/ivybridge was introduced in:
    
    7686a56 sandy/ivybridge: Native raminit.
    
    An additional current level is needed.
    
    Change-Id: Ied73d168045c25d37afa5d9d7073de7f9c6435c7
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
    Reviewed-on: http://review.coreboot.org/7098
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Tested-by: build bot (Jenkins)

commit 39937cc2fd28bcc754c0595f1327467499af40ea
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Oct 17 13:17:00 2014 +0200

    boot/coreboot_tables.h: Use `it is` instead of `it easy` in comment
    
    Change-Id: I5c8a689a4923175fff1f38847b7cfbbaeeb0ea22
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/7092
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Tested-by: build bot (Jenkins)

commit 9ebb3f5efaf7ebf643210c8c0befadfcc47e24f1
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Fri Oct 17 15:06:29 2014 +0200

    lenovo/t520: Enable wake on LID and Fn key
    
    Change-Id: Ieb23728ba171733820830e86e77a4c6d8e1cc57d
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/7101
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 85f2e12b4f1d66e723652a91e8765019e71f1c16
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Fri Oct 17 15:09:05 2014 +0200

    lenovo/t520: Apply ME workaround for S3 resume
    
    Without this patch the laptop powers down after resume.
    
    Change-Id: Ic6486fd4c4cc55b1ac5695f9d6d83fc2193b7eba
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/7102
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit a9f429922212402d920007220c519a92ab4cbbb2
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Fri Oct 17 15:13:44 2014 +0200

    lenovo/t520: fix board info
    
    Change-Id: Ieeefbe4617ea6c131236d8c94e9990f7b797192b
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/7103
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 81da09e889e5edffda406f97a370958189e2d7f0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 17 16:44:48 2014 +0300

    asus/m5a88-v: Fix southbridge init
    
    This amdfam10 board was by mistake modified with commit
    
       b6f3da4 AGESA CIMx: Move late init out of get_bus_conf()
    
    Change-Id: I8edf6f7f4cc635d31e7e485e3f6de57ef8ed7b1e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/7104
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit de72d439bff80cb1ef298d3752ea528c94e760ca
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Fri Oct 17 13:01:02 2014 +0200

    lenovo/t520: Use native LVDS gfx init
    
    As introduced in:
    1783a3c ivybridge: LVDS gfx init.
    
    The panel on the T520 is a LP156WD1 40 pin LVDS (2 ch, 6-bit).
    Tx parameters derived from datasheet table.
    
    Change-Id: Ib733836e3233a7f14a79f36a27ed36b638e837f5
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/7100
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit df5a91dd0ec7ba0a253d6f05382ed11d121eb0b1
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Fri Oct 17 12:16:20 2014 +0200

    lenovo/T520: Remove butterfly DSP init.
    
    It's specific to butterfly. Doesn't do anything on lenovos.
    
    Change-Id: I98b7c3199de5d8515bd869936e1b95847321d264
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/7099
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Tested-by: build bot (Jenkins)

commit 93643e362d541b6ab32147e5886ca661a9eec1ac
Author: Philipp Deppenwiese <zaolin@das-labor.org>
Date:   Fri Oct 17 16:10:32 2014 +0200

    Fix ICH spi implementation which reads data from different chips.
    
    This patch adjusts the read timeout in order to support flash chips
    which needs more than 60ms to complete a spi command.
    
    This problem can be reproduced on a Thinkpad T520 with M25PX64 spi chip ( suspend to ram bug ).
    
    Change-Id: I22b2e59f1855ead6162a292b83b9b854b55c0235
    Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
    Reviewed-on: http://review.coreboot.org/7105
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 7f7fb6f9baea8df19190f637e1395658a6be0c4a
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Oct 15 22:30:16 2014 +0200

    macbook21: Kill empty gpe.asl
    
    Change-Id: I4ed04ecbc9e11200577cc2b6ede0e05af9f346fa
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7082
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit d4776c3b16bd4a62151e2a9e3e4ce558b7d3162d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Oct 15 22:58:10 2014 +0200

    macbook21: Kill empty Makefile.inc
    
    Change-Id: I2d946b9d757cc6158ff7f8927a81d7bf03a2e062
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7084
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Tested-by: build bot (Jenkins)

commit 6023ca4970116b38b9708b988dc87a38ad26c6bb
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Oct 17 13:28:15 2014 +0200

    Kconfig: move SMBIOS related options to SMBIOS table option
    
    Change-Id: I74943d0248f49796b9d31d6ed827c69f8cea13a5
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-on: http://review.coreboot.org/7090
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 007dbe130fcea076c9444f8184963ace1f99a607
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Oct 15 22:56:12 2014 +0200

    macbook21: Kill empty smi.h
    
    Change-Id: I387bb6154fe432ef2fc5f92faca69e67d7a6370a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7083
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Tested-by: build bot (Jenkins)

commit 58470e39b3958292e112e13251c5c811409a7a02
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Oct 17 13:08:36 2014 +0200

    Kconfig: clean up options in top level and device menu
    
    Move generic options to the "General Setup" menu.
    Move device specific options to the "Devices" menu.
    
    Change-Id: I514a021305d43f026b24fd3016477300700ed401
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-on: http://review.coreboot.org/7089
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 06c788db1ac6fd1faa1de67d4c0ddd03f3dbdbbe
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 12 00:17:11 2014 +0200

    bd82x6x: Consolidate common GNVS init
    
    Change-Id: Iea035f80695623e4e8d53eea7e3ec294d868fb5b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7053
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 1aff2e97ea242ce6c841d2dba945cfb2cec0ec80
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Oct 15 20:24:12 2014 +0200

    macbook21: Kill empty mainboard.asl
    
    Change-Id: I29c7d367df7d1ce911f6cd7ed5e5c56865b41dcc
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7063
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Tested-by: build bot (Jenkins)

commit f5fcedfbc4fe4682ac85bac49c62e59b840fb1f1
Author: Scott Radcliffe <sradcliffe@microind.com>
Date:   Tue Oct 14 15:40:59 2014 -0400

    drivers/spi: Add support for Micron N25Q128
    
    Support added for Micron N25Q128 SPI flash, which has
    the same manufacturer id as ST Micro. Jedec ID =
    0x20 0xBB 0x18. Since existing stmicro.c only compares
    the last device id byte, this flash is mistakenly
    identified as M25P128, which has ID = 0x20 0x20 0x18.
    
    To handle this situation and avoid breaking code for
    existing devices, a two byte .id member is added.
    New devices should be added to the beginning of the
    flash table array with .idcode = STM_ID_USE_ALT_ID and
    .id = the two byte jedec device id.
    
    A 4KB subsector erase capability is added and used for
    this new device. It requires using a different SPI
    op-code supported by adding .op_erase member. Previous
    devices defined in stmicro.c are assigned their original
    op-code for 64KB sector erase.
    
    N25Q128 is now working on a custom designed Bayley Bay
    based board. Tested by verifying the MRC fastboot cache
    is successfully (re)written. Note that previous devices
    were not retested.
    
    Change-Id: Ic63d86958bf8d301898a157b435f549a0dd9893c
    Signed-off-by: Scott Radcliffe <sradcliffe@microind.com>
    Reviewed-on: http://review.coreboot.org/7077
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 08c7018050e5af2c604c7b1ef35a66fb9f1171d5
Author: Nico Huber <nico.h@gmx.de>
Date:   Tue Oct 14 23:27:50 2014 +0200

    libpayload: Don't use default path for kconfig
    
    libpayload's kconfig is totally incompatible with other kconfig versions,
    today. Using other versions just doesn't work any more, so don't use the
    overridable $(obj)/util/kconfig path. Choose a path that reflects the
    incompatibility: $(obj)/util/lp_kconfig, instead.
    
    This whole every-(sub)project-has-it's-own-patched-kconfig-version makes
    me really, really sad :'-(
    
    Change-Id: I964772f3323dc20aa7c1cc26a384a2fbca1dbb5e
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/7061
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cbe3c7050fa57f8cd2cd0cd6bc8e4ac4fce7d35c
Author: Nico Huber <nico.h@gmx.de>
Date:   Sun Oct 12 16:37:42 2014 +0200

    libpayload: Fix missed CONFIG_ -> CONFIG_LP_ substitutions
    
    Change-Id: I1c64a9a649398ebe2eda179907c470f99caa9fc3
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/7056
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3dc12c1e19181bb9bacebeda706c39cfb57eb326
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Sep 17 02:38:51 2014 +0200

    bd82x6x: Consolidate early native USB init
    
    Change-Id: I6189930fd3c69c3497e4cf1a78035e6614761b13
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6923
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cb0d772eef12ce89d31197d0e71b103c7b3cf02c
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Oct 16 15:43:46 2014 +0200

    Add board_info for all Google/Intel boards mitting the file
    
    Change-Id: Iac53462ab3621d96ba15e2fde2800212584246db
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-on: http://review.coreboot.org/7072
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Tested-by: build bot (Jenkins)

commit b752e4f402b2a96d1b9545b5fed3df09d2990743
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Oct 3 09:39:31 2014 +0200

    acpi_add_ssdt_pstates: Remove function.
    
    Nowhere in database p_state_num is set. So this whole function ends up
    being a noop. Moreover the offsets used by it are wrong with any
    optimizing iasl. Remove it in preparation of move to per-device ACPI.
    
    Change-Id: I1f1f9743565aa8f0b8fca472ad4cb6d7542fcecb
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7012
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Tested-by: build bot (Jenkins)

commit af4d66edf88b9d1d493708557fc45dc12683106d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Oct 16 15:51:48 2014 +0200

    xe7501devkit: Kill unused cmos.layout
    
    Change-Id: I04b485945a1830deaf5a695507ea81809edbceeb
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7073
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Tested-by: build bot (Jenkins)

commit f21271edb5406577dc0a062ce3068ef17a09309d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Oct 16 18:00:27 2014 +0200

    Fix mismerge of ACPI patches
    
    Change-Id: I2a9960861465f4686113213d5e5793333b6274b2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7079
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 833bf20f92c38e8e3dfee12d3b81d47bcd35d906
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 16 10:55:39 2014 +0000

    RISCV: add this architecture to cbfstool
    
    Change-Id: I6d972e595f12585cda08e1a6d2b94b4bf4f212f5
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/7067
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a9db82fbaff166bf474fb6ead7345073a4d3a77d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Oct 16 13:21:47 2014 +0200

    smbios: Mark laptops as such
    
    Change-Id: I179a4cede2f826f72a400208748798737216c01a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7071
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 2adb297cf930ff5c2d78d828d801461feae3254b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 16 10:53:48 2014 +0000

    uarts: 32/64 cleanup
    
    We had lots of casts that caused warnings when compiling on RISCV.
    Clean them up.
    
    Change-Id: I46fcb33147ad6bf75e49ebfdfa05990e8c7ae4eb
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/7066
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ff178beee572564dcfabd96d04071edcb3412e5d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 16 10:57:01 2014 +0000

    lib/cbfs: more cleanup for 32/64 issues
    
    Change-Id: I5499a99cec82b464c5146cfc2008d683d079b23a
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/7068
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f33d270d972f101341d7273267b8215dfff61cf5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 16 10:58:09 2014 +0000

    cbmem: 64/32 cleanup
    
    Change-Id: I4b55b635cc233a9d48b284623399277d941b0d5a
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/7069
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit 6d7de4f64f6ee94631044b9574a4a5125c0faa6f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 16 11:00:16 2014 +0000

    qemu-armv7: 32/64
    
    This really is not critical but we might as well get it right.
    
    Change-Id: Ifec1e8dc35d7f5bb89d9a7a877d82410c83a3288
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/7070
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit 96afb6ff21ed63725e52541367f5dc11af0de914
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Oct 16 15:53:16 2014 +0200

    libpayload: also support armv7-a toolchain
    
    Change-Id: I9b80b72de96fb28489dcc8547b8f748ea4fcc355
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/7074
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>
    Tested-by: Patrick Georgi <pgeorgi@google.com>

commit 0253ee0ce4d92ef076c78f710443cb9dfac459e9
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Sep 6 01:38:55 2014 +0300

    x220, x230: Remove unused headers.
    
    Change-Id: Ia85e3b588c0e255e5c0f77114f051130596ce8d5
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6922
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 332f14b60b241d1793401ea50b22785ad81c97cd
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Sep 5 16:29:41 2014 +0200

    bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.
    
    Change-Id: I9ba1fa5f9ad38cb619466c6199eacd219bc53281
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6921
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit c845b43f0a404adaf96808a122c591c5552dc818
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Sep 5 03:37:44 2014 +0200

    sandybridge: Move common northbridge finalize to northbridge code.
    
    Change-Id: I6d4178e5aaffc1330b0953b0601bf6b448250a8e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6920
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit dca2c468fc4eaba3a6123eb3ab97463db0254650
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Sep 5 02:56:24 2014 +0200

    lenovo/{x2,t5}{2,3}0: Remove butterfly DSP init.
    
    It's specific to butterfly. Doesn't do anything on lenovos.
    
    Change-Id: I7b607196733225eace0f5e70b4cc02651488aa74
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6841
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Patrick Georgi <pgeorgi@google.com>

commit 6985d4ee075ff884315d566853be701e238faac6
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Sep 21 14:31:19 2014 +0200

    amdk8: Move to per-device ACPI
    
    Change-Id: I485791015aa7eaabba53813945c216f5725554b1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6948
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 822bc65b0e8cb9c17721b8b776ec7ecf6ac4129e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Jan 3 15:55:40 2014 +0100

    ACPI: Remove CONFIG_GENERATE_ACPI_TABLES
    
    As currently many systems would be barely functional without ACPI,
    always generate ACPI tables if supported.
    
    Change-Id: I372dbd03101030c904dab153552a1291f3b63518
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4609
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 0e64617d7d8adcd4d3db16eed7a34604691c2ee6
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 00:27:05 2014 +0200

    i945: Convert to per-device ACPI
    
    Change-Id: Iee3ee33ca58b8c722d2d38aae31e7130032512ad
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6804
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 33769a5caadca0ff82267ab5021bc85315e1d7f5
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 30 22:39:20 2014 +0200

    gm45: Convert to per-device ACPI
    
    Change-Id: Ib04b03b2dc2ad3bfa886b43df9dd6518bbb46e3f
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6803
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e
Author: Scott Radcliffe <sradcliffe@microind.com>
Date:   Fri Oct 10 16:09:52 2014 -0400

    intel/fsp_baytrail: Add padding so device_nvs location matches ACPI
    
    The offset of the device_nvs in the gnvs struct is expected to be
    0x1000. It is actually 0x100 so padding is needed to move device_nvs
    to the expected location. ACPI references to device_nvs objects will
    be correct with the padding.
    
    This was tested using a Micro Industries customized Baytrail-I board
    based on the Intel Bayley Bay CRB. In intel/baytrail/nvs.h, there's
    a Google customized structure located at 0x0100-0x0FFF that is
    removed from the fsp_baytrail/nvs.h which explains the mismatch here.
    
    Change-Id: I4721a79b53b5b3345ff9b0c053bdd31d2cf9cb61
    Signed-off-by: Scott Radcliffe <sradcliffe@microind.com>
    Reviewed-on: http://review.coreboot.org/7038
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit bf9d6a856788f7bae7c3732b1761adb99ac3914f
Author: Scott Radcliffe <sradcliffe@microind.com>
Date:   Fri Oct 10 16:15:01 2014 -0400

    baytrail: Add padding to the end of device_nvs to match ACPI
    
    ACPI globalnvs.asl expects the gnvs memory area size to be 0x2000.
    Padding has been added to device_nvs struct to reserve the full
    0x2000 bytes for gnvs usage.
    
    No known issues are caused by having the GNVS area shorter than
    what ACPI thinks. Since there's nothing defined in this area,
    O/S shouldn't try to access it. Only problem might be if O/S
    notices the SSDT is located within the GNVS defined area.
    
    I verified that the next table written to memory (SSDT) is 0x2000
    past GNVS start using a custom-designed Baytrail-I motherboard
    based on the Intel Bayley Bay CRB.
    
    Change-Id: I9792954c7a3403eba6f37d7e53ea4a9ed3a2e4ac
    Signed-off-by: Scott Radcliffe <sradcliffe@microind.com>
    Reviewed-on: http://review.coreboot.org/7039
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 375e6ce4aeee449c34a6d3efb6374c5684f7b32f
Author: Scott Radcliffe <sradcliffe@microind.com>
Date:   Fri Oct 10 16:26:05 2014 -0400

    intel/fsp_baytrail: Clear the GNVS area prior to filling
    
    Zero out the GNVS area so that uninitialized portions are defined.
    
    Tests using Microsoft Windows (XP/7/8) gave a bluescreen bugcheck: A5
    (ACPI_BIOS_ERROR) with the first parameter (0x00001000)
    (ACPI_BIOS_USING_OS_MEMORY). Some ACPI enumerated devices use the
    GNVS area to define whether they're enabled and their MMIO regions.
    On my custom baytrail-based board and build, these devices were
    disabled but GNVS had uninitialized data indicating the devices
    were enabled with improper MMIO regions.
    
    Should investigate further to see where the GNVS device values are
    set if enabled and make sure they're set to valid values even when
    the devices are disabled via the mainboard/devicetree.cb.
    
    Change-Id: I2b575c65bfaab58ae6206ac6f457c259c27a7d97
    Signed-off-by: Scott Radcliffe <sradcliffe@microind.com>
    Reviewed-on: http://review.coreboot.org/7040
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 9310df8d0351842e7bb9efe3cabc0ff82ec99c53
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Oct 10 20:40:41 2014 +0200

    acpi: Don't add an empty SSDT.
    
    It's harmless but useless.
    
    Change-Id: Iaaa5f6933d120a2071b2e32e62e36e63afa96be3
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7043
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>
    Tested-by: build bot (Jenkins)

commit 0a66991a345f437e957ecc0ddeed70bc304d2a43
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 5 14:34:17 2014 +0200

    acpi: Remove explicit pointer tracking in per-device ssdt.
    
    It's useless and error-prone.
    
    Change-Id: Ie385e147d42b05290ab8c3ca193c5c871306f4ac
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7018
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 334fd8e28b6f572dc8a82c7969696c6072709583
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 5 11:10:35 2014 +0200

    bd82x6x, ibexpeak, lynxpoint: Declare NVSA before its use.
    
    Windows chokes if it's not the case.
    
    Change-Id: I3df15228ed00c3124b8d42fc01d7d63ff3fe07ba
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7017
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit bf3e2dfaafb4b523a893a43aab4e0da661c94e5a
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Oct 11 03:49:24 2014 +0200

    early section: Don't add empty .car.cbmem_console.
    
    With handling of this section removed it confused the linker.
    
    Change-Id: Id096c1642c0bfed1007a4b7d7dfa89f8b4ffcae1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7042
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit 9215a89f1cf8dfdb62a6b8a55a2e89e4e322a2d3
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Sep 1 22:52:02 2014 +0200

    via/epia-m: Switch to per-device ACPI
    
    Change-Id: Ic63fc1f933fff5cd58adcd4299c4ac2a62c4bb68
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6941
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6b330f2a2462a72c2d10940b5e06b99f02b20297
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 5 11:08:40 2014 +0200

    lynxpoint: Change OEM table ID for serialio.
    
    According to ACPI spec all SSDTs should have distinct OEM table ID.
    We end up with 2 SSDTs named "COREBOOT". Fix this.
    
    Change-Id: I01bccb72758baf51c6b4263778716f4bb9d438c9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7016
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 7309c64d483abb4bf4ebe12901109320d88124ba
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 5 11:07:33 2014 +0200

    bd82x6x, ibexpeak, lynxpoint: Ensure 0-filling of uninited GNVS vars.
    
    Change-Id: I672c3ca9e7f30a21330cf1920a25b1ab38b3f282
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7015
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 60fccdc3d2ab5a3b0265f1a411d02b8504407e1c
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Oct 5 11:05:16 2014 +0200

    acpi_create_mcfg_mmconfig: Zero-out the structure before filling.
    
    Otherwise "reserved" fields end up with a garbage instead of predictable
    value.
    
    Change-Id: I8a036769a8f86f1d6752651601de2800f4f1bd00
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/7014
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 762d53d41897b3b2b13e47623c50cc94b5113333
Author: Kayalvizhi Dhandapani <kayalvizhid@ami.com>
Date:   Tue Oct 7 12:21:31 2014 -0400

    intel/fsp_baytrail: Include header for "southcluster_smm_save_gpio_route"
    
    Fix the error 'implicit declaration of function
    "southcluster_smm_save_gpio_route"', when SMM module is added.
    
    Change-Id: Ia050ab7e2b036541537b645d3fe4dc747cd1dff8
    Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com>
    Reviewed-on: http://review.coreboot.org/7024
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit a16055ae8ad2a04a7577aae351def4482d7bbab8
Author: Kayalvizhi Dhandapani <kayalvizhid@ami.com>
Date:   Tue Oct 7 14:11:20 2014 -0400

    intel/fsp_baytrail: fix error "unknown type device_t", when SMM Module added
    
    Change-Id: I6d8622c7f343619b915442d8056aa6672dfc4f6e
    Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com>
    Reviewed-on: http://review.coreboot.org/7025
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 454625c5cf4adecb5b80777503bc600c8b139004
Author: Kayalvizhi Dhandapani <kayalvizhid@ami.com>
Date:   Tue Oct 7 14:34:01 2014 -0400

    intel/fsp_baytrail: Fix SMM/SMI
    
    With SMM enabled the boot stopped while patching up global NVS in DSDT.
    The cause is that both CPUs are assigned the same SMBASE address.
    So update the "cpu_smm_do_relocation()" function so that each
    CPU gets a different SMBASE address
    
    Based on rmodule work that wasn't propagated to the FSP
    version: commit 3eb8eb7eba55cdfd64c8d50181ea066526ff6485
    
    Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b
    Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com>
    Reviewed-on: http://review.coreboot.org/7026
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Tested-by: build bot (Jenkins)

commit 2c0f46afbbee078881ad9e9a99f5c219c2ed528e
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Thu Sep 25 16:45:45 2014 -0600

    AGESA stub 00730F01: Add config.h and kconfig.h to Makefile.inc
    
    The static library builder for the stub that interfaces to the
    AGESA binary does not include config.h and kconfig.h, so any
    header file changes that depend on Kconfig variables fail.  Force
    these two system headers to be included in the build of any AGESA
    stub files.
    
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Change-Id: I2e8d38fa5aa21cc31b995ee3abe68ab3c3c55a68
    Reviewed-on: http://review.coreboot.org/6979
    Reviewed-by: Martin Roth <gaumless@gmail.com>
    Tested-by: build bot (Jenkins)

commit b9a0809faeeef67e46cda17cf8f7a839c6fe614c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Oct 7 05:18:51 2014 +0000

    xcompile: detect and use RISCV binaries
    
    RISCV is a new architecture. This change simply setups up xcompile
    to detect and use RISCV compilers if they are found.
    
    Change-Id: Iad1a88ef2e3c8dd1e601549aeca26fb29b2bc7ae
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/7023
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 34fc4ab80b507739e2580d490dff67fcfdde11ea
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Oct 6 15:30:37 2014 +0000

    mkelfimage: remove
    
    It's not been needed for years, is definitely not needed now
    that cbfstool parses bzImages, and its presence keeps confusing
    people.
    
    Also, rewrite history. We never mentioned mkelfimage in the
    documentation. Never, ever, ever.
    
    Change-Id: Id96a57906ba6a423b06a8f4140d2efde6f280d55
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/7021
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <gaumless@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 076c317d479b701af1b1561d0cd53ec1102016aa
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Apr 3 21:13:11 2014 +0800

    edid: Relax EDID 1.3 requirements.
    
    In E-EDID (EDID v1.3), Monitor Name (0xfc) and Monitor Range Limits (0xfd) are
    always required. However, some panels do not really have these fields. As a
    workaround (and since we don't really use these fields), we only print warning
    messages for that case.
    
    Change-Id: I81b1db7d7f6c6f9320a862608dec4c7be298d7db
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/193742
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit c633215ef8342664d9a4478e821fc8aad368b7f3)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7009
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 35382a6eeb6634c291ffb67a3c4fa7a4601a7328
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Apr 2 17:57:05 2014 -0700

    cbmem console: Locate the preram console with a symbol instead of a section.
    
    On non-x86 systems, the location of the preram CBMEM console may not be in a
    predictable place relative to other things in the linker script. That makes it
    difficult to work with as its own section because the linker will complain if
    you try to move backwards as it lays out memory. If the console header is
    treated as an actual blob of memory which has to be put in the image, we'd
    have to predict where to put it so that it isn't before something with a lower
    address or after something with a higher address. Symbols, on the other hand,
    can be defined arbitrarily.
    
    Change-Id: I3257b981eee0c15bb997a9f2c55a03494c6ec6f0
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/193164
    Reviewed-by: Tom Warren <twarren@nvidia.com>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit a492761c27076bcac080013d509ae4aafd6dc3e3)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7013
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 34c5933a66caf839ac82c2bdf3e50bcce816b36d
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Feb 21 16:22:52 2014 +0800

    gen: Add "assert" in assert.h.
    
    Typically assert.h should provide assert().
    
    Change-Id: I465f4a616b212f7b00d445c575866b13eecfa6fb
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/187410
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    (cherry picked from commit 3990584ac8e1ec9b3838bd9dfdf8a9cb2d20fbd0)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6961
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 6eaaafa2c32029bd9dc5fb4196fe2b22cb5b4d9b
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Feb 21 16:21:00 2014 +0800

    vendorcode: Add ChromeOS VPD parser.
    
    Copied (and unmodified) the minimal bits from ChromeOS libVPD:
     https://chromium.googlesource.com/chromiumos/platform/vpd
    
    Old-Change-Id: Id75d1bfd16263ac1b94c22979f9892cf7908d5e6
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/187411
    Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
    (cherry picked from commit a10ca23686299f3fd5b639631242cadaa2ca9e8a)
    
    vendorcode: Update ChromeOS VPD Parser.
    
    Merge recent changes in ChromeOS VPD that allows non-memory-mapped firmware
    to load VPD easier and faster (ref:
     https://chromium-review.googlesource.com/188134 ).
    
    Old-Change-Id: I3ee0b89c703f476f3d77cdde52cc7588724f7686
    Reviewed-on: https://chromium-review.googlesource.com/188743
    Tested-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Hung-Te Lin <hungte@chromium.org>
    (cherry picked from commit 03f4d521a7fa711b963b0e1822e92eac16a691b1)
    
    vendorcode: Access to ChromeOS VPD on default CBFS media.
    
    The new function "cros_vpd_gets(key, buf, size)" provides an easy and quick way
    to retrieve values in ChromeOS VPD section.
    
    Old-Change-Id: I38e50615e515707ffaecdc4c4fae65043541b687
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/187430
    Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
    (cherry picked from commit bcd3832c06e8ed357c50f19396da21a218dc4b39)
    
    Squashed 3 related commits for a ChromeOS VPD parser.
    
    Change-Id: I4ba8fce16ea123c78d7b543c8353ab9bc1e2aa9f
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6959
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit ffda804b52768467ea7b3394a3e2fe9039f87362
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Sep 3 12:40:15 2014 -0500

    sconfig: add cpu device type
    
    In order to enumerate CPU devices that are non-x86 (read: no lapic)
    provide a generic 'cpu' device.
    
    Change-Id: Ifeafdad8076935c3448784e6958117002509acbf
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6824
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a296f9e3d385d2d310aae1cdfd4a20c592de1d20
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Sep 13 03:43:49 2014 +1000

    Kconfig: Allow native vga init to be selectable for SeaBIOS payload
    
    Change-Id: I1508f3d3c56cb9afbf4a23355831549552a62866
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6891
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit d63b97f9ab5bda1b696a53c66a3b802316762bfe
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 12 16:12:43 2014 +1000

    mainboard/amd: Sanitise headers in PlatformGnbPcie.c
    
    It is hard to see where things are coming from without correct headers.
    
    Change-Id: I8e2195b101501ffd25464196283fb2bddb5b8f51
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5980
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 55cdc160bbe1827e8ab1a2370ab1ebb0162e9768
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Apr 22 17:06:43 2014 -0700

    Provide a way to compile some files with -O0 option
    
    When preparing an image for source level debugging, it is convenient
    to be able to compile some modules with -O0, which makes it much
    easier to follow the execution flow.
    
    This patch allows to do it by defining GDB_DEBUG=1 in the environment
    before invoking make. Adding this feature as a common config flag is
    problematic, because we don't want to compile the entire image with
    -O0.
    
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/196359
    (cherry picked from commit dde4928c045d12e502cb109015a710cd9fdf2a04)
    
    Changed from CFLAGS to CFLAGS_common.
    
    Change-Id: Ie0be653509509eeb64ea3a7229f54c0c812840a9
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7005
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit daecc449ca1708a2412df6cd394e299ede36bfe2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon May 12 10:20:45 2014 -0700

    elog: Add event type for CPU thermal trip
    
    There is a status bit for this event in most intel chipsets that
    we can read and report.  Start by adding the new event type.
    
    Change-Id: Ib06411e3b87a1d069fb469943dd445bee6c1291f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/199370
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 386a06170ec5afb31d0fe93ace3afbaab897a598)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7004
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e1dad0c0b9f3aaf7a5f09a48f44fa8d2d9ef1b72
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Mon Mar 10 14:46:06 2014 -0700

    libpayload: usb: xhci: Treat port reset as a port status change
    
    If a port is connected before and after an xhci controller reset, the
    PORTSC CSC bit may not be asserted. Add an additional check in
    xhci_rh_port_status_changed for the PRC bit so we can correctly handle
    ports in such a state.
    
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Change-Id: I2d623aae647ab13711badd7211ab467afdc69548
    Reviewed-on: https://chromium-review.googlesource.com/189394
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    (cherry picked from commit ee7c3ea182b35bb6ce3c62f301c4515714f6e654)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7002
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a16029a93d06dc73f7ee2796db7c90b2211ee776
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Mon Mar 10 14:12:29 2014 -0700

    libpayload: usb: Remove generic roothub reset port function
    
    The generic roothub reset port function is overly broad and does some
    things which may be undesirable, such as issuing multiple resets to a
    port if the reset is deemed to have finished too quickly. Remove the
    generic function and replace it with a controller-specific function,
    currently only implemented for xhci.
    
    Change-Id: Id46f73ea3341d4d01d2b517c6bf687402022d272
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/189495
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    (cherry picked from commit 54e1da075b0106b0a1f736641fa52c39401d349d)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7001
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 758f26aa2dd7447267ac7e08b32ef157fc55a755
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Sep 27 11:37:46 2014 +0200

    nvidia/cbootimage: avoid upstream's build system
    
    It brings in useless dependencies, a weird autotools
    configuration, and tons of pain everywhere.
    
    Instead just build things ourselves.
    
    Change-Id: I67f06e711cb9dcd594363bc1a4f99d3273074549
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6986
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e87ee14449fb549be09d6a5de10185f182efdc79
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Wed Mar 26 11:17:58 2014 -0700

    baytrail: update C0 microcode
    
    baytrail: Add 811 microcode for C0 parts
    
    Incorporate 811 microcode version for C0 stepping parts.
    
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Old-Change-Id: Ic34c233df28fa2c94db3a886faad8239a05f475d
    Reviewed-on: https://chromium-review.googlesource.com/191693
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 57c9cbdb9e4bb1cf721849ace8958eb6ec032594)
    
    baytrail: Add 813 microcode for C0 parts
    
    Incorporate 813 microcode version for C0 stepping parts.
    
    Old-Change-Id: I513ce5cc1470fa0154bee088547c5cb8a5902fb5
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/195200
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit bf15a48c6bd71c2b0ab91530713afb26e139ad9c)
    
    baytrail: Update microcode to version 816
    
    Version 816 of microcode.
    
    Old-Change-Id: I868702ec94a265013bb5e378a2345ff1cf0dc364
    Original-Change-Id: I9a9cacf2d16bdabdb7ec84607bf6c96e4ac3f3c4
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/197692
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 16512b09e399c05cf42694854277aa7f1753e49e)
    
    Squashed 3 successive updates for baytrail C0 microcode.
    
    Change-Id: I76714ae636b119348e6bb9f8a4639c68be32ba3a
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/7000
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3cb86de4747593253a3b2d8d383784669b3e660b
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Sep 29 20:42:33 2014 +0200

    intel/i945: Another magic number
    
    Replace it with the existing #define
    
    Change-Id: I6e67ed1a455cd4f9eeed1865b9ef981e7ef0a874
    Found-by: Idwer Vollering
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6992
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit a341a77177c3e4b6c8de16b368f457d3d23c549a
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Sep 29 19:51:21 2014 +0200

    intel/i945: Fix "always false" statement
    
    Also replace magic number with already existing #define
    
    Change-Id: I64d22aca185bf43ff0ac126584b41920182a1112
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6990
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 21fd2f4801bc7761981e509d135663f1a76f98fe
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Apr 22 11:14:12 2014 -0700

    reg_script: Fix bug in IO macros
    
    These have apparently never been used because they are
    incorrect.
    
    Change-Id: I3624cb2548a0ee3da56a2cca62ed50b0dfbf7817
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/196266
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit bc0187702061fe326422c070c592a18cd93de723)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6999
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 08f6c80d34db90124e7937ac92e930958fb47ca3
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Apr 3 21:13:11 2014 +0800

    edid: Support EDID 1.4.
    
    EDID v1.4 has changed some fields (0xfc - Monitor Name, 0xfd - Monitor Range
    Limits) to optional so we need to list the requirements explicitly instead of
    sharing v1.3 requirements.
    
    Change-Id: I5c7ca06893bd20e178bc35164c4ca639c881e00b
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/193013
    (cherry picked from commit 2ad598b8bd620117e70e13347365d74a7c6b87ef)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6998
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b2c1062116ec2adce60cbc75908a921b9a35a2b4
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Apr 3 19:59:37 2014 +0800

    edid: Accept valid detail blocks without timing descriptor.
    
    The detail block may contain timing descriptor, or other fields like monitor
    descriptor, so we should return 1 in detailed_block function when a valid
    structure is found, otherwise for any EDID containing monitor descriptor we will
    see following error messages:
    
    	EDID block does not conform at all!
    		Detailed blocks filled with garbage
    
    Change-Id: Ib4e91d648741e5b54a558d53a1152273c7341427
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/193002
    (cherry picked from commit a1f212d6aaa14d5f795beeabdb8b7b8a79578c33)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6997
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2536c1ac76790b12554fe8e277ef2dcbc5f58242
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Apr 3 19:21:03 2014 +0800

    edid: Fix string extraction in Monitor Descriptors.
    
    The ASCII Data String in EDID Monitor Descriptor (3.10.3) is "Stored as ASCII,
    code page #437" and may contain special characters like '-'. The isalnum check
    should be removed.
    
    Also, the "Monitor Name" (0xfc) does not need to always end with 0Ah, so the
    name_descriptor_terminated should be replaced by has_valid_string_termination.
    
    Change-Id: I12a670237e12577fc971c0fbd9b2a61c82040ad3
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/193001
    (cherry picked from commit 671f82fd5963e32e72d3886aa242cb3e8519f226)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6996
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit da01d9435163a1799fdbf8c60c988bb2f8566f29
Author: Furquan Shaikh <furquan@google.com>
Date:   Wed Mar 19 14:31:23 2014 -0700

    storm: Add generic support skeleton for storm
    
    Skeleton for storm mainboard
    
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/190724
    Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    (cherry picked from commit ba371d410768fae169da929a23c40139d26a55d3)
    
    Removed 'select ARCH_ARM' and added 'select BOARD_ROMSIZE_KB_1024' to
    the Kconfig.
    
    Change-Id: I55c0ad6a47515ba4124b99a69d5776db2365f06e
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6975
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan@google.com>

commit 79445817aedacb5b1edbd6db2e3b6edab97eb5e0
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Apr 3 18:35:58 2014 +0800

    edid: Fix extension parsing when EDID blob does not have any extensions.
    
    When parsing "extensions", we should skip the first EDID (main) block and start
    from offset 128 (EDID may have only main block, so an EDID without any
    extension is fine) because the header format for main block and extensions are
    different.
    
    Without this we will see "Unknown extension block" on all EDIDs, and seeing an
    error (1) return value for EDIDs without extension.
    
    Also, after the first "unknown" error is fixed, we can now collect all return
    values from parse_extension, and return an error when any of the extensions are
    wrong (not just last one).
    
    Change-Id: I0ee029ac8ec6800687cd7749e23989399e721109
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/193011
    (cherry picked from commit fdf0cc2e9573c19b550fa2b5e4e06337b114f864)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6995
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fc0d244b39ec640ba8040b64e09e2fb5c931f95f
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Apr 3 18:33:01 2014 +0800

    edid: Fix source indent.
    
    Some lines in decode_edid have incorrect indent levels.
    
    Change-Id: Icc9cb57ff8dd2e2056599b3dc733fe5ac4e41c16
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/193010
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 3211ac0a29a037c5414f9ed1736c8f7822ad116b)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6994
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0e8e0991e2897b61cf7b3c49ab04826f1b7d7ee4
Author: Matt DeVillier <matt.devillier@gmail.com>
Date:   Thu Sep 11 12:06:19 2014 -0500

    google/panther: add board_info.txt
    
    Change-Id: Iec0397a981c31c8af3def04b8c170884f79a50cc
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Reviewed-on: http://review.coreboot.org/6871
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit f9f53eb72f37b71f2dad62157dd43ea31e392a17
Author: Mohan D'Costa <mohan@ndr.co.jp>
Date:   Thu Sep 25 18:17:08 2014 +0900

    intel/minnowmax: Enable S3 suspend/resume
    
    This enables S3 Suspend / Resume support for MinnowMax board
    using Intel's Bay Trail FSP
    
    Tested resume from Power Button and Magic Packet.
    
    Change-Id: I021122a68c05f2e725cabb8f3946249afe802bbe
    Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp>
    Reviewed-on: http://review.coreboot.org/6972
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <gaumless@gmail.com>
    Tested-by: build bot (Jenkins)

commit ed0c83877f453b94a5e68bef62d6dbba1b97f0d2
Author: Mohan D'Costa <mohan@ndr.co.jp>
Date:   Thu Sep 18 15:57:06 2014 +0900

    intel/fsp_baytrail: Add S3 suspend/resume Support
    
    This adds S3 Suspend / Resume support to Intel's Bay Trail FSP
    
    It is based on the "src/soc/intel/baytrail/romstage/romstage.c"
    implementation.
    
    Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008
    Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp>
    Reviewed-on: http://review.coreboot.org/6937
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <gaumless@gmail.com>
    Tested-by: build bot (Jenkins)

commit bdae9bedcdf5650abee089564c47ecbf2ba70f79
Author: Mohan D'Costa <mohan@ndr.co.jp>
Date:   Thu Sep 25 14:40:44 2014 +0900

    spi: Add support for Winbond W25Q128FW
    
    The W25Q128FW spi part is programatically equivalent
    to the other W25Q128 parts except it operates at 1.8V.
    Just add a new entry with the appropriate ID.
    
    Tested on a modified MinnowMax Board.
    
    Change-Id: Id6a426418a7f785a9d959b02a9e3d2ffc421804f
    Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp>
    Reviewed-on: http://review.coreboot.org/6971
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <gaumless@gmail.com>
    Tested-by: build bot (Jenkins)

commit 02b5a74d6cf7f0b5132b13363847098414eea9cf
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Aug 16 07:31:19 2014 +0200

    asrock/imb-a180/BiosCallOuts.c: Fix typo in temperatu*re* in comment
    
    Change-Id: If50685505143ccbd51098e92de72545c71b24892
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6684
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 61d07d63ec5e1d6c4a8af2090ca6ee9be4448732
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Dec 16 04:02:48 2013 -0800

    libpayload: Build libpayload with debugging info turned up all the way.
    
    Pass -ggdb3 to the compiler when building libpayload, -ggdb  so that it uses
    "the most expressive format available", and 3 so that the debugging level is
    set to 3, the highest value currently supported. The debugging information can
    be stripped by the payload consuming the library, and will definitely be
    stripped by cbfstool when installing that payload into an image.
    
    Change-Id: Ifd6c4a928fbb0b9fa9b3b2e0ea298abff31baf3b
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/180252
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit dc04daaf099c53c57508b66e08f40945345a56ca)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6980
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8404dca5a6c20f7b0e947011d9a185e6060ad157
Author: Marcelo Povoa <marcelogp@chromium.org>
Date:   Fri Feb 14 15:42:49 2014 -0800

    Remove stale char[] initialization causing unaligned memory access
    
    This throws an alignment fault when run in ARMv8 Foundation
    model and seems unnecessary, so remove it.
    
    Change-Id: I2e3aa54502c292958ba44ff4e2e71c27653f2e1a
    Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/186744
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 57510d553c56ca5dfb4765836ddb901744e29e20)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6974
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit be1d1e7f838e09e67b8cc0e84cd842f4cf71f9ae
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Mar 3 15:08:10 2014 -0800

    google/panther: Be safe about invalid thermal readings
    
    In case we get an invalid thermal reading, let's run the fan
    at full speed rather than at low speed. This might impact the
    user experiance slightly in cases where the bad reading does
    not happen while the system is hot, but it will increase stability
    in the cases where the system is actually overheating.
    
    Also, set the critical temperature below tjmax, because otherwise
    thermal shutdown by the OS will never be triggered.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: Iab262f1f17a5dff875c596d9e8d50e4e50ee90f9
    Reviewed-on: https://chromium-review.googlesource.com/188556
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit 721fc2361ea9c6fea75409be57726294ce840f03)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6962
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3f1500f54f7d5d0bdc4b2f3a99cb7768d31066cc
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Mar 6 08:37:49 2014 -0800

    google/chromeec: Notify DPTF charger participant on AC state change
    
    The DPTF charger particpant device needs to be notified when the
    AC state changes so it can re-evaluate the PPCC object and apply
    the proper charge rate limit if necessary.
    
    Change-Id: I6723754e2fe12862f50709875140fcadcddb18eb
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/189029
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Brad Geltz <brad.geltz@intel.com>
    (cherry picked from commit ed1ee577014421b021e8814edc91a1b696bf9eed)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6951
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1f8d246d2f69e9f130a736204faa77685a0cc937
Author: Julius Werner <jwerner@chromium.org>
Date:   Wed Jan 15 14:13:25 2014 -0800

    arm: Fix up new cache flush algorithm and replace dcache_*_all() with it
    
    This patch fixes the remaining few bugs in our shiny new cache iteration
    by set/way/level algorithm to actually make it work: It makes it start
    from cache level 0 (previously it would always start at LoC and be
    "done" instantly), fixes up the two shifts that isolate the set bits at
    the end (which didn't seem to account for the fact that the first shift
    affects the second), and throws an S bit on that last shift so that it
    actually affects the conditionals after it.
    
    In addition, also moves the next_level block to the top so that we can
    share (and thus eliminate) some code at initialization, and turns the
    whole thing into a thrice-instantiated macro to create functions that
    fit our existing interface.
    
    Change-Id: I1338a589cbb37d74ea6e7a3d4f67ff827e24edbe
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/183879
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 6d94f8330191c316fe093ddb5288329453da8a4b)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6932
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 12de698c248e52a14cbb56f5fc3c4598115d72ef
Author: Julius Werner <jwerner@chromium.org>
Date:   Mon Jan 13 11:13:23 2014 -0800

    arm: Import armv7_dcache_wbinv_all function from NetBSD
    
    This patch pulls in NetBSD's full cache flushing algorithm for ARM, to
    replace our old, slow and slightly overzealous C-only implementation.
    It's a beautiful piece of code that manages to run on only caller-saved
    registers (meaning it doesn't need to write to memory) in a very tight
    loop, and it's BSD-licensed to boot (which we need for libpayload).
    Unfortunately it's also not quite correct, but I can fix that. Pulling
    the original in a separate commit to make it more obvious what changes
    are mine.
    
    Change-Id: I7a71c9e570866a6e25f756cb09ae2b6445048d83
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/183878
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 4698467320613d7ddc39714f40aacbc990af9399)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6931
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 81f90c58d2eacf8ee2baf2334fd38bbfa0ef7274
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Wed Sep 24 14:59:32 2014 -0600

    x86/mtrr: Enable MTRR's before enabling caching
    
    Fix up the following commit by enabling the MTRR's before enabling caching.
    
    7756fe7 x86: Minimize work done with the caches disabled in mtrr functions.
    
    Also fix two typos in comments.
    
    Change-Id: If751b815f9dab781fc38c898cf692f0940c57695
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6969
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit d2f3aa91e0096b087214ee5fc368fa0091d6c52c
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Mon Dec 30 09:09:31 2013 -0800

    Peppy/Falco: always use native graphics
    
    The products having shipped, and living in their own branch,
    we might as well enable native graphics since:
    1. it works
    2. it removes a blob and the only good blob is a dead blob
    3. it's faster
    4. when we have problems, we can diagnose them more easily
    5. when we get to newer kernels the boot time will magically get faster
    as the driver realizes graphics is running. Where else do you get a 3-4 second
    speedup for free?
    
    Change-Id: Iad937320e7f46b1de7ab00dace04115a7f182ed1
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/181225
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    (cherry picked from commit 7b567d87a9fcf6736e90e730bd052e4465d57bdf)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6912
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit dbd006b0820098ab1bc042a16853db7131cf91af
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Feb 20 23:38:49 2014 -0800

    cbfstool: Propogate compression errors back to the caller.
    
    When compression fails for whatever reason, the caller should know about it
    rather than blindly assuming it worked correctly. That can prevent half
    compressed data from ending up in the image.
    
    This is currently happening for a segment of depthcharge which is triggering
    a failure in LZMA. The size of the "compressed" data is never set and is
    recorded as zero, and that segment effectively isn't loaded during boot.
    
    Change-Id: Idbff01f5413d030bbf5382712780bbd0b9e83bc7
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/187364
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit be48f3e41eaf0eaf6686c61c439095fc56883cec)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6960
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 49c98dc42b706897e802af12d16349ff65a9bd43
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jan 22 21:06:32 2014 -0800

    snow: Rename snow to daisy.
    
    The name snow goes by in many places in chromeos is daisy. Snow is technically
    a variant of daisy and should really be called daisy_snow, but for historical
    reasons the daisy board with no variant was used instead. To make it easier to
    work with within chromeos, this change renames the snow board to daisy.
    
    Change-Id: I569b31bf417db55be91832f15271bea4bc30f163
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/183553
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 13f24d967251c18dce2a00bcea915f448c4c6aa7)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6929
    Tested-by: build bot (Jenkins)

commit 765705789213e1914cad540bb7868d2154cdbedf
Author: Furquan Shaikh <furquan@google.com>
Date:   Wed Mar 19 14:29:48 2014 -0700

    soc/qualcomm: Add generic support skeleton for ipq806x
    
    Skeleton for soc ipq806x
    
    Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/190723
    Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    (cherry picked from commit e71d45733d86e77717fd2f592ef06113246db911)
    
    soc/ipq806x: Disable LPAE mode.
    
    LPAE (large physical address extension) is not available on this SOC
    core, do not enable it.
    
    Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b
    Signed-off-by: Deepa Dinamani <deepad@codeaurora.com>
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/198023
    Reviewed-by: deepa dinamani <deepad@quicinc.com>
    (cherry picked from commit e6e12c39efd54e4fcbd444134bf30e211948a71b)
    
    Squashed 2 commits for the Qualcomm ipq806x SOC.
    
    Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6963
    Reviewed-by: Furquan Shaikh <furquan@google.com>
    Tested-by: build bot (Jenkins)

commit 6481cfb15d62784b87eabe972a742fa1e3da129d
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Dec 17 15:21:54 2013 -0800

    peppy and falco: set panel power timings in northbridge, using devicetree, not mainboards
    
    Historically we had set panel timing in the mainboard gma code. This goes
    back to the replay-attack video startup.
    
    We can let the haswell gma code set these values from the device tree
    settings.
    
    Change-Id: If32150d2857241ca2d2c88880086f49d25815d76
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/180521
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    (cherry picked from commit 406eab3ca6a9bc59382866817786bf96bbb19d56)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6911
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e9e31892d20646be1bba0ee4175344f37e43469a
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Jan 14 13:45:37 2014 -0800

    libpayload: Add missing cache API stub to x86
    
    This patch adds another cache invalidation stub to the x86 arch to
    make it usable in common code. This whole stuff should probably be
    redesigned anyway but I just want to get it working and unblock my CL
    for now... more cleanups coming later.
    
    Change-Id: I2e8bdd8aa0e6723209384c24042f053f2e993fe6
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182534
    Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
    (cherry picked from commit cafce5182a7a2a9ce17ad40d9d893a40ebd5aafd)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6919
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 04bfbf50950df6ef78aa354698b226928a4024bc
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jan 22 20:50:27 2014 -0800

    pit: Rename pit to peach_pit.
    
    The name pit goes by in many places in chromeos is peach_pit, where peach is
    the base name and pit is the name of this particular variant. To make it
    easier to work with within chromeos and to make the board names a little less
    ambiguous, this change renames the pit board to peach_pit, and from Pit to
    Peach Pit.
    
    Change-Id: I51c89ba3785cf4cb9769a989b1cac71bcd1b0a05
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/183552
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit cbbe1e9f04e34436a1bbae28628e0b5630d41054)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6928
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 7756fe70eb568e1429e244306be9401357cefa43
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Feb 25 01:40:34 2014 -0800

    x86: Minimize work done with the caches disabled in mtrr functions.
    
    The code in src/cpu/x86/mtrr/mtrr.c disables caching in a few places when
    changing mtrr settings. While I can't find anything that says that's actually
    required, I can believe it's necessary. With that said, other code around the
    wrmsr instructions which actually modify the settings should be able to run
    with caching enabled with no ill effects.
    
    This is particularly true for two calls to printk, one in the fixed mtrr code
    and one in the variable, which could result in an arbitrary amount of work
    being done without caching. When changing the implementation of the cbmem
    console, these two printks caused a significant regression in boot performance
    on link of about 70ms which is about 10% of total firmware boot time. When the
    window where the cache is disabled is minimized, both this and the new
    implementation were about 30ms faster than the original boot time.
    
    For the variable MTRRs, we now store what we want to set the MSRs to and then
    write them all at once at the end of commit_var_mtrrs(). This way we don't
    have some set and some not, but we still minimize the time we spend with the
    caches disabled.
    
    Change-Id: I5139b262bd2d13f79afd88e2e2c0f514fb3e27c9
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/187811
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 31529d6d965676c6cedeb62137eabc26819956fc)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6952
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit cd0f2283e8cd1dc43c17cb12a5e5b934f69dd657
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Feb 25 11:00:37 2014 -0600

    baytrail: add 80c microcode for C0 parts
    
    Incoprorate 80c microcode version for C0 stepping parts.
    
    Change-Id: I2a76b4c92cac0aca5949313060f1d315ebd8e1a9
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/187842
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    (cherry picked from commit 318027a8853060e7223524dbd2ad7c3b6cc9b766)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6950
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 5c8d3d22c82c5f67d1c8ae1c9479b1baee49ceb2
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Jan 17 22:11:35 2014 -0800

    big: Create a nyan_big mainboard which is a copy of nyan.
    
    The nyan_big mainboard is very similar to nyan, but will be different in a few
    ways. For instance, the BCT will be different, and the GPIOs may need to be
    configured slightly differently.
    
    This change also adds prefixes to the kconfig variables in "choice" blocks
    for both boards since having multiple instances of choice blocks with the same
    options confuses kconfig even if all of the instances have mutually exclusive
    dependencies.
    
    Change-Id: I290a32e47fc118bd4b86d543df617ad324325dbc
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/183532
    Reviewed-by: Tom Warren <twarren@nvidia.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit d1a453fe1aa68b3d12936dd48cc6c94b54f81579)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6927
    Tested-by: build bot (Jenkins)

commit 1893fd7c2b39c6167fafdc8294a5216170a810e2
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Mon Sep 22 17:18:11 2014 -0600

    arm: add missing gc-sections for ramstage
    
    This is a fix up for recent patch:
    c505837 arm: Have the linker garbage-collect unused functions and variables
    
    I missed adding --gc-sections to a couple of the ramstage lines.
    
    Change-Id: I81178eb99fddbd99c603c79ba506db51af975b27
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6956
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit ea8f3b4aa0029871ee36a953a927c1af081343c5
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Sep 21 12:21:36 2014 +0200

    northbridge/intel/i945/Kconfig: Select VGA
    
    Commit 0092c999 (i945: Support text mode gfx init) [1] broke building
    the Lenovo X60 with native graphics initialization by selecting
    `CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT`.
    
            CC         northbridge/intel/i945/gma.ramstage.o
        src/northbridge/intel/i945/gma.c: In function 'intel_gma_init':
        src/northbridge/intel/i945/gma.c:398:2: error: implicit declaration of function 'vga_textmode_init' [-Werror=implicit-function-declaration]
    
    Selecting the Kconfig variable VGA makes the declaration of the
    function `vga_textmode_init()` to be included by the preprocessor.
    
    [1] http://review.coreboot.org/6723
    
    Change-Id: Iecbb2898193078b8738425cea13cb7e6da508cab
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6947
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7eb809af40a79eacf2648e734a605f8003779403
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Aug 26 15:17:35 2014 -0700

    cbfstool: Add AARCH64 reloc types to elf.h
    
    Change-Id: Ifd4726491e01c3acebd3dfc326c1be994b0aefb8
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/214328
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6955
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 4194338e6232912fb17a5f46bb0ec6a310000a28
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Aug 26 15:05:01 2014 -0700

    mkelfimage: Add EM_AARCH64 as elf image type for arm64
    
    Change-Id: I5510a4fe5085430b767161133113578b7cffa237
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/214327
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6954
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 9ceca503554ba585a49e298ff4b1d2e017c6ef5b
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Aug 26 15:01:41 2014 -0700

    rmodule: Fix rmodule.ld for 64-bit
    
    Fix the alignment for 64-bit systems
    
    Change-Id: I7fcb1683d760b96307759b7d44d8770dd49a02e3
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/214326
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6953
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit b237c108991c46f9ed67130b57828bef1b1f423a
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Aug 26 14:59:36 2014 -0700

    rmodtool: Allow rmodules with 0 relocations
    
    Currently, rmodules with 0 relocations are not allowed. Fix this by skipping
    addition of .rmodules section on 0 relocs.
    
    Change-Id: I7a39cf409a5f2bc808967d2b5334a15891c4748e
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: http://review.coreboot.org/6774
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 2af76f4bdc81df699bad55f65335ff518381d7dd
Author: Furquan Shaikh <furquan@google.com>
Date:   Mon Apr 28 16:39:40 2014 -0700

    coreboot arm64: Add support for arm64 into coreboot framework
    
    Add support for enabling different coreboot stages (bootblock, romstage and
    ramstage) to have arm64 architecture. Most of the files have been copied over
    from arm/ or arm64-generic work.
    
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/197397
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    (cherry picked from commit 033ba96516805502673ac7404bc97e6ce4e2a934)
    
    This patch is essentially a squash of aarch64 changes made by
    these patches:
    
    d955885 coreboot: Rename coreboot_ram stage to ramstage
    a492761 cbmem console: Locate the preram console with a symbol instead of a sect
    96e7f0e aarch64: Enable early icache and migrate SCTLR from EL3
    3f854dc aarch64: Pass coreboot table in jmp_to_elf_entry
    ab3ecaf aarch64/foundation-armv8: Set up RAM area and enter ramstage
    25fd2e9 aarch64: Remove CAR definitions from early_variables.h
    65bf77d aarch64/foundation-armv8: Enable DYNAMIC_CBMEM
    9484873 aarch64: Change default exception level to EL2
    7a152c3 aarch64: Fix formatting of exception registers dump
    6946464 aarch64: Implement basic exception handling
    c732a9d aarch64/foundation-armv8: Basic bootblock implementation
    3bc412c aarch64: Comment out some parts of code to allow build
    ab5be71 Add initial aarch64 support
    
    The ramstage support is the only portion that has been tested
    on actual hardware. Bootblock and romstage support may require
    modifications to run on hardware.
    
    Change-Id: Icd59bec55c963a471a50e30972a8092e4c9d2fb2
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6915
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Furquan Shaikh <furquan@google.com>

commit 804702602c017f9aebb66f409f8ed9a5d9200a4e
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Sep 21 11:53:56 2014 +0200

    google/{falco,peppy}/gma.c: Do not include non-existent "hda.h"
    
    Commit 75c83870 (azalia: Shrink boilerplate) [1] removed the header
    file `hda_verb.h`. This header is still included in the mainboard’s
    `gma.c`, causing the following build error, when native graphics
    initialization is enabled.
    
            CC         mainboard/google/falco/gma.ramstage.o
        src/mainboard/google/falco/gma.c:34:22: fatal error: hda_verb.h: No such file or directory
    
    This was not caught, as native graphics initialization is not enabled
    for the build tests.
    
    It turns out that the array `mainboard_cim_verb_data` is not used in
    `src/mainboard/intel/wtm2/hda_verb.h`, so fix the problem by removing
    the inclusion.
    
    [1] http://review.coreboot.org/6840
    
    Change-Id: I91e4f00a3030bdef0278102df2783258389bca13
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6946
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 9625264137a28832c2239e10edfed2d48a3e3b96
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Sep 21 11:28:39 2014 +0200

    google/link, intel/wtm2: Do not include non-existent "hda.h" in i915.c
    
    Commit 75c83870 (azalia: Shrink boilerplate) [1] removed the header
    file `hda_verb.h`. This header is still included in the mainboard’s
    `i915.c`, causing the following build error, when native graphics
    initialization is enabled.
    
            CC         mainboard/intel/wtm2/i915.ramstage.o
        src/mainboard/intel/wtm2/i915.c:34:22: fatal error: hda_verb.h: No such file or directory
    
    This was not caught, as native graphics initialization is not enabled
    for the build tests.
    
    It turns out that the array `mainboard_cim_verb_data` is not used in
    `src/mainboard/intel/wtm2/hda_verb.h`, so fix the problem by removing
    the inclusion.
    
    [1] http://review.coreboot.org/6840
    
    Change-Id: Ic902581c6809a1069e169cc874678146a24d75f3
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6945
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit c6e566a07b281c4bb11198c65236e18d1281dfdb
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 17:43:51 2014 +0200

    haswell: Move to per-device ACPI
    
    Change-Id: Ic724dcf516d9cb78e89698da603151a32d24e978
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6814
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 24d4f7f8defca9c68d4a96ba5cbedf5b01ca6e53
Author: Andrew Bresticker <abrestic@chromium.org>
Date:   Wed Dec 18 22:41:34 2013 -0800

    tegra124/nyan: memory and display updates
    
    tegra124: use pll_c_out1 as sclk parent
    Reviewed-on: https://chromium-review.googlesource.com/180865
    (cherry picked from commit 418337a5bde70df6a770222201c51bf3e8892d5f)
    
    tegra124: take LP cluster out of reset
    Reviewed-on: https://chromium-review.googlesource.com/180866
    (cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3)
    
    tegra124: norrin: display code clean up
    Reviewed-on: https://chromium-review.googlesource.com/181003
    (cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17)
    
    tegra124: Change the display hack to use window A
    Reviewed-on: https://chromium-review.googlesource.com/182001
    (cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a)
    
    tegra124: norrin: Initialize frame buffer
    Reviewed-on: https://chromium-review.googlesource.com/182090
    (cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167)
    
    nyan: do not enable pull-ups on SPI1 (EC) data pins
    Reviewed-on: https://chromium-review.googlesource.com/181063
    (cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c)
    
    tegra124: Add source for the LP0 resume blob.
    Reviewed-on: https://chromium-review.googlesource.com/183152
    (cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b)
    
    tegra124: Revise Memory Controller registers structure definition.
    Reviewed-on: https://chromium-review.googlesource.com/182992
    (cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1)
    
    tegra124: Add more PMC register details.
    Reviewed-on: https://chromium-review.googlesource.com/183231
    (cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829)
    
    tegra124: Add SDRAM configuration header file from cbootimage.
    Reviewed-on: https://chromium-review.googlesource.com/182613
    (cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4)
    
    tegra124: Revise sdram_param.h for Coreboot.
    Reviewed-on: https://chromium-review.googlesource.com/182614
    (cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8)
    
    tegra124: Fix EMC base address.
    Reviewed-on: https://chromium-review.googlesource.com/183602
    (cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e)
    
    tegra124: Add EMC registers definition.
    Reviewed-on: https://chromium-review.googlesource.com/183622
    (cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a)
    
    tegra124: Never touch MEM(MC)/EMC clocks in ramstage.
    Reviewed-on: https://chromium-review.googlesource.com/183623
    (cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023)
    
    tegra124: use RAM_CODE[3:2] for ram code
    Reviewed-on: https://chromium-review.googlesource.com/183833
    (cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d)
    
    tegra124: Allow setting PLLM (clock for SDRAM).
    Reviewed-on: https://chromium-review.googlesource.com/183621
    (cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683)
    
    tegra124: SDRAM Initialization.
    Reviewed-on: https://chromium-review.googlesource.com/182615
    (cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce)
    
    tegra124: Get RAM_CODE for SDRAM initialization.
    Reviewed-on: https://chromium-review.googlesource.com/183781
    (cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8)
    
    Squashed 18 nyan/tegra commits for memory and display.
    
    Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6914
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit d65e214d666269d0bd20d88ba2bc83349810c668
Author: Julius Werner <jwerner@chromium.org>
Date:   Fri Dec 13 12:59:57 2013 -0800

    arm: Update mem* functions to newer versions
    
    The memcpy/memset/memmove assembly implementations have been taken from
    U-Boot, which originally got them from Linux. I turns out that they are
    actually not that bad, but they could use an update. This patch pulls in
    the current Linux upstream versions of those files, removing some old
    U-Boot cruft such as checking whether the two pointers in a memcpy() are
    equal (really now?) or side-stepping the R8 register because it was used
    for special purposes. It also returns to the good old Linux
    ENTRY/ENDPROC macros since we have them now anyway, and straightens out
    the W() macro in preparation for unified thumb support.
    
    Change-Id: I138af269b423bef0a237759ac29f1ee58ca206a0
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182179
    Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
    (cherry picked from commit 777127997bde5785b21d422d0b6eb04c4328b478)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6918
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 64b9ca9d4eb5eccdea86d967220c67b503a4519b
Author: Julius Werner <jwerner@chromium.org>
Date:   Thu Dec 12 20:24:48 2013 -0800

    arm: Move libgcc assembly macros to arch/asm.h
    
    libgcc/macros.h contains some useful assembly macros that are common in
    Linux kernel code and facilitate things such as unified ARM/THUMB
    assembly. This patch moves it to a more general place where it can be
    used by other code as well.
    
    Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182178
    Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
    (cherry picked from commit a780670def94a969829811fa8cf257f12b88f085)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6917
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 406bad127bf7ac7da25261a30d239751b24e22af
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Nov 13 15:28:01 2013 -0800

    libpayload: Add vboot handoff parsing on ARM
    
    This is needed by depthcharge on ARM if coreboot is loading its
    ramstage from the RW section of the ROM.
    
    Change-Id: I96c6c04a0cee39854b45f2eda169e93461da0694
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/176757
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit cf26be4cb527b0fc4212d401a8c77ceb1c7992d0)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6906
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 03784fa97a764be81ca9bcf79222e7b37e2e7692
Author: Julius Werner <jwerner@chromium.org>
Date:   Mon Dec 9 17:46:22 2013 -0800

    Add check_member macro to allow clean and easy struct offset checking
    
    This patch adds a new static assertion macro that can be used to check
    the offsets in structures that overlay register sets at compile time. It
    uses the _Static_assert() declaration from the new ISO C11 standard,
    which is supported (even without -std=c11) by GCC after version 4.6.
    (There is supposedly also support in clang, although I haven't tried
    it... let's deal with compiler issues when/if they turn up.)
    
    I've added it to all structures for our current ARM SoCs for now, and I
    think every new register overlay we add going forward should use them
    (at least for the last member, but feel free to add more if you think
    it's useful).
    
    Change-Id: If32510e7049739ad05618d363a854dc372d64386
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179412
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit cef5fa13c31375a316ca4556c0039b17c8ea7900)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6905
    Tested-by: build bot (Jenkins)

commit c505837e67aa4fb89964c849d905fa8d44459152
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Oct 15 17:36:17 2013 -0700

    arm: Have the linker garbage-collect unused functions and variables
    
    This patch activates -ffunction-sections and -fdata-sections for the
    compiler and --gc-sections for the linker. This will strip out all
    unused functions and static/global variables from the final binaries and
    reduce the amount of data we need to read over SPI.
    
    A quick test with ToT images shows a 2.5k (13%) / 10k (29%) / 12k (28%)
    reduction on Nyan and 3k (38%) / 23k (50%) / 13k (29%) on Pit,
    respectively for bootblock / romstage / ramstage.
    
    Change-Id: I052411d4ad190d0395921ac4d4677341fb91568a
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/177111
    (cherry picked from commit 5635b138778dea67a5f179e13003132be07f7e59)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6904
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 08539b3b986a1eb564815f72897b448e2bd69b5b
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Thu Sep 11 11:14:15 2014 -0600

    snow/pit: include chromeos.c in romstage
    
    When CONFIG_CHROMEOS is enabled, both systems currently fail to build
    romstage due to undefined symbols.
    
    Change-Id: I0edcb141b9a79fad6b1a629bf77cae656c3d6319
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6873
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4177db52a29b28a023a9ae84ed76c40ed6ce4daf
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Feb 5 14:55:26 2014 -0600

    baytrail/rambi: spi, charger, and audio updates
    
    baytrail: combine SPI configuration in romstage
    Reviewed-on: https://chromium-review.googlesource.com/185140
    (cherry picked from commit 4e7f0e8ae1138e478ae7106d54719cf05e13b402)
    
    baytrail: lock down registers before handoff
    Reviewed-on: https://chromium-review.googlesource.com/185200
    (cherry picked from commit 82cce4d2b46ccc554b71efa179b5d95756e2ad5e)
    
    baytrail: invoke SMM finalization on handoff
    Reviewed-on: https://chromium-review.googlesource.com/185201
    (cherry picked from commit 1b50affb1fdda52a5986c9429713930ed517a86a)
    
    rambi: don't invoke SMM finalization
    Reviewed-on: https://chromium-review.googlesource.com/185202
    (cherry picked from commit 6eff475dae7f4536eb846ccf6d51fce262b8ffef)
    
    rambi: remove handling of APM_CNT_FINALIZE
    Reviewed-on: https://chromium-review.googlesource.com/185203
    (cherry picked from commit 9fc310d7e2730466cc7fcc84999502a2d4d08bab)
    
    baytrail: don't increment boot count on S3 resume
    Reviewed-on: https://chromium-review.googlesource.com/185381
    (cherry picked from commit 940a0fa4df1ce335229eb6f80143b93a84ba358c)
    
    rambi: enable HDA device
    Reviewed-on: https://chromium-review.googlesource.com/184574
    (cherry picked from commit 334f2a5c7c6540e744b6aaf7e1da0b55e1368196)
    
    baytrail: lock down spi controller according to mainboard
    Reviewed-on: https://chromium-review.googlesource.com/185631
    (cherry picked from commit 696ece68cb6d522c248e800f168e675e4b4a7317)
    
    rambi: implement mainboard_get_spi_config() to lock dow spi controller
    Reviewed-on: https://chromium-review.googlesource.com/185632
    (cherry picked from commit 1d9ba15858fd421a4fe5a47f7171273128e89524)
    
    baytrail: introduce ssus_disable_internal_pull()
    Reviewed-on: https://chromium-review.googlesource.com/185740
    (cherry picked from commit 9d6056dd70b27183dab6a4656f4f9612ae870a4d)
    
    rambi: fix write-protect gpio reading at romstage
    Reviewed-on: https://chromium-review.googlesource.com/185741
    (cherry picked from commit c64627689b1afec59be6fdab323d5492046f0bc7)
    
    baytrail: DPTF: implement charger current limit
    Reviewed-on: https://chromium-review.googlesource.com/185759
    (cherry picked from commit 287e8936613a7a83281ff692b20383dacf7fcaf6)
    
    rambi: Enable charger participant and define states
    Reviewed-on: https://chromium-review.googlesource.com/185760
    (cherry picked from commit 2f62a11927ecf10cb2c76a9f5d368d4050404137)
    
    baytrail: increase command wait timeout
    Reviewed-on: https://chromium-review.googlesource.com/185874
    (cherry picked from commit 962a79ef72169b5d52fc746d1889d3b652fd9bcc)
    
    baytrail: make caching MRC data more robust
    Reviewed-on: https://chromium-review.googlesource.com/185875
    (cherry picked from commit b5e10ad47b9e4f330caaee4faf69702f24d6bdd8)
    
    baytrail: upgrade MRC wrapper header
    Reviewed-on: https://chromium-review.googlesource.com/186391
    (cherry picked from commit 8c1a62f1f4261d4f38aacbbb353c9d6218ec2885)
    
    rambi: instruct MRC to use weaker memory ODT settings
    Reviewed-on: https://chromium-review.googlesource.com/186420
    (cherry picked from commit b9329126ca08d20ce1d8c5db0fcabd39140c7292)
    
    rambi: Move touch wakeup resource GPIO to separate device
    Reviewed-on: https://chromium-review.googlesource.com/186932
    (cherry picked from commit ba44e2e04f9469c629cb61a911c8cd339f52b0ef)
    
    baytrail: Set some MSRs related to turbo power
    Reviewed-on: https://chromium-review.googlesource.com/186933
    (cherry picked from commit 76b25df5a31914ae58d47d17af448216011e425c)
    
    baytrail: change power consumption number for ACPI_C3/C6FS.
    Reviewed-on: https://chromium-review.googlesource.com/186934
    (cherry picked from commit 5192e2464fbb88ea6fc117070240c9733e34f065)
    
    baytrail: Fix use of ConcatenateResTemplate() in ACPI LPE device
    Reviewed-on: https://chromium-review.googlesource.com/186928
    (cherry picked from commit 8d1ab5de1d43b0790d140f6d0e36a990a5049ece)
    
    baytrail: Disable P-state HW coordination on 4-core SKU
    Reviewed-on: https://chromium-review.googlesource.com/187575
    (cherry picked from commit c19c0f1d7cb3cb2635766c186ba9598933424a78)
    
    baytrail: DPTF: Enable mainboard-specific _PDL
    Reviewed-on: https://chromium-review.googlesource.com/187576
    (cherry picked from commit 5412ac5c07bee22017a0ee6d1e2433917b98ea87)
    
    rambi: Apply DPTF tuning parameters
    Reviewed-on: https://chromium-review.googlesource.com/187577
    (cherry picked from commit 932a5a3803ceaf430ad2934b371ac0886c25efca)
    
    rambi : change lpe_codec_clk_freq to 19.2
    Reviewed-on: https://chromium-review.googlesource.com/187594
    (cherry picked from commit f64cb1ae77076ad5ec994670f4a83dc561ea80c4)
    
    Squashed 25 commits for baytrail/rambi.
    
    Change-Id: Ibe628ac974d117a09361f7f3131a488911ddd27d
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6933
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

commit e6b280e24b02552dc43510ed7fadce4a7105e4a2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Feb 10 16:21:05 2014 -0800

    chrome ec: Add support for limiting charger current
    
    Update the ec_commands header (direct from EC source) and
    add support for the new charger current limit interface
    which will be used by DPTF.
    
    Change-Id: Ia9a2a84b612a2982dbe996f07a856be6cd53ebdb
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/185758
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 1fcca2d75856ecefd3aeb1c551182aa76d649466)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6925
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 0c0efa7e50fdd75c6154af67d2ddbebe317c7b55
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Wed Sep 17 16:14:18 2014 -0600

    exynos5250: remove unused ret variable in cpu.c
    
    Showed up as an error when '--gc-sections' was added as a flag to the
    compiler.
    
    Change-Id: I214d3e16a72fca0becc677d7af66097464d64247
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6926
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit e23f3b8ca21dc95fb92e5b86fd10af8c4990caf2
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Sep 15 05:53:57 2014 +1000

    mainboard/lenovo/t530: Make native VGA init 'user-friendly'
    
    Default to do native VGA init since this machine is a laptop
    and the user would likely want to use it as such. Also, if you
    know what this is you know how to turn it off if you want to.
    
    Change-Id: I55f91a48affbd0ec93b0bb0c88c531d15c32ba21
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6903
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit f7c308edeac2c8886afab13c5e8052cc15d84575
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Dec 18 10:55:48 2013 -0800

    samus: Enable XHCI mode by default
    
    - Enable xhci_default setting in devicetree
    - Enable usb_xhci_on_resume setting for PEI
    
    Change-Id: I2a3965a222ce571a2ad43f568fc2d0ecb94a77bc
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/180673
    (cherry picked from commit c5ef875f6d148964b8ad62a3fe79916c758dbc57)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6908
    Tested-by: build bot (Jenkins)

commit d5acaaf8451d727107b53882c9d3bae4482fe0b8
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Dec 17 15:35:51 2013 -0800

    lynxpoint: Don't enable SMI handling of TCO
    
    We have no good reason to be handling the TCO timeout
    as an SMI since we aren't doing anything special with it
    and clearing the status in the handler prevents the reboot
    from actually happening.
    
    Change-Id: I074ac0cfa7230606690e3f0e4c40ebc2a8713635
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/180672
    (cherry picked from commit 608a2c5768e9300c81b7c72fb8ab7a0c7c142bec)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6907
    Tested-by: build bot (Jenkins)

commit 51d787a5cf8b65aff0800743437443e416845655
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Thu Jan 16 17:52:21 2014 -0800

    rambi/baytrail: ACPI, GPIO, audio, misc updates
    
    rambi: Change RAM_ID GPIOs to GPIO_INPUT
    Reviewed-on: https://chromium-review.googlesource.com/182934
    (cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0)
    
    baytrail: initialize rtc device
    Reviewed-on: https://chromium-review.googlesource.com/183051
    (cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821)
    
    baytrail: Set SOC power budget values for SdpProfile 2&3
    Reviewed-on: https://chromium-review.googlesource.com/183101
    (cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55)
    
    baytrail: Set PMC PTPS register correctly
    Reviewed-on: https://chromium-review.googlesource.com/183280
    (cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad)
    
    baytrail: update to version 809 microcode for c0
    Reviewed-on: https://chromium-review.googlesource.com/183256
    (cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e)
    
    baytrail: Add a shared GNVS init function
    Reviewed-on: https://chromium-review.googlesource.com/183332
    (cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c)
    
    baytrail: Add basic support for ACPI System Wake Source
    Reviewed-on: https://chromium-review.googlesource.com/183333
    (cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619)
    
    baytrail: allow configuration of io hole size
    Reviewed-on: https://chromium-review.googlesource.com/183269
    (cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919)
    
    baytrail: add in C0 stepping idenitification support.
    Reviewed-on: https://chromium-review.googlesource.com/183594
    (cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4)
    
    baytrail: add option for enabling PS2 mode
    Reviewed-on: https://chromium-review.googlesource.com/183595
    (cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f)
    
    rambi: enable PS2 mode for VNN and VCC
    Reviewed-on: https://chromium-review.googlesource.com/183596
    (cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9)
    
    baytrail: add config option for disabling slp_x stretching
    Reviewed-on: https://chromium-review.googlesource.com/183587
    (cherry picked from commit f99804c2649bef436644dd300be2a595659ceece)
    
    rambi: disable slp_x stretching after sus fail
    Reviewed-on: https://chromium-review.googlesource.com/183588
    (cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880)
    
    baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI
    Reviewed-on: https://chromium-review.googlesource.com/183597
    (cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906)
    
    rambi: fix trackpad and touchscreen wake sources
    Reviewed-on: https://chromium-review.googlesource.com/183598
    (cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5)
    
    baytrail: Add support for LPE device in ACPI mode
    Reviewed-on: https://chromium-review.googlesource.com/184006
    (cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f)
    
    rambi: Add LPE GPIOs for Jack/Mic detect
    Reviewed-on: https://chromium-review.googlesource.com/184007
    (cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578)
    
    rambi: Set TSRx passive threshold to 60C
    Reviewed-on: https://chromium-review.googlesource.com/184008
    (cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee)
    
    baytrail: DPTF: Add PPCC object for power limit information
    Reviewed-on: https://chromium-review.googlesource.com/184158
    (cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b)
    
    baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant
    Reviewed-on: https://chromium-review.googlesource.com/184442
    (cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd)
    
    rambi: Move the CPU passive/critical threshold config to DPTF
    Reviewed-on: https://chromium-review.googlesource.com/184443
    (cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac)
    
    baytrail: Fix XHCI controller reset on resume
    Reviewed-on: https://chromium-review.googlesource.com/184500
    (cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd)
    
    baytrail: update lpe audio firmware location
    Reviewed-on: https://chromium-review.googlesource.com/184481
    (cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6)
    
    rambi: Put LPSS devices in ACPI mode
    Reviewed-on: https://chromium-review.googlesource.com/184530
    (cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1)
    
    baytrail: initialize HDA device and HDMI codec
    Reviewed-on: https://chromium-review.googlesource.com/184710
    (cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961)
    
    baytrail: provide GPIO_ACPI_WAKE configuration
    Reviewed-on: https://chromium-review.googlesource.com/184718
    (cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b)
    
    rambi: configure wake pins as just wake sources
    Reviewed-on: https://chromium-review.googlesource.com/184719
    (cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115)
    
    baytrail: I2C: Add config data to ACPI Device
    Reviewed-on: https://chromium-review.googlesource.com/184922
    (cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8)
    
    Squashed 28 commits for rambi and baytrail.
    
    Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6916
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 1f279b68b6fe312b99b8969c659c87c57760c450
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Dec 17 15:24:24 2013 -0800

    slippy: remove FUI support
    
    There's no reason to keep maintaining support on this mainboard, since nobody has one.
    
    Change-Id: I5c7c8ea4640170ba231fec82a94a54ee1876b845
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/180503
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    (cherry picked from commit e291d82acbc8bf0d1372e11ac100a7dd340a0040)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6913
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1101a71219794b3c070dc67df2f9530b05c4c0fb
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Nov 22 18:41:38 2013 -0800

    spi: add Kconfig variable for dual-output read enable
    
    Add a Kconfig variable so that driver code knows whether
    or not to use dual-output reads.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: I31d23bfedd91521d719378ec573e33b381ebd2c5
    Reviewed-on: https://chromium-review.googlesource.com/177834
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit de6869a3350041c6823427787971efc9fcf469b8)
    
    tegra124: implement x2 mode for SPI transfers on CBFS media
    
    This implements x2 mode when reading CBFS media over SPI.
    
    In theory this effectively doubles our throughput, though the initial
    results were almost negligibly better. Using a logic analyzer we see
    a pattern of 12 clocks, ~70ns delay, 4 clocks, ~310ns delay. So if we
    want to see further gains here then we'll probably need to tune AHB
    arbitration and utilization to eliminate bubbles/stalls when copying
    from APB DMA.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: I33d6ae30923fc42b4dc7103d029085985472cf3e
    Reviewed-on: https://chromium-review.googlesource.com/177835
    Reviewed-by: Tom Warren <twarren@nvidia.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 29289223362b12e84da5cbb130f285c6b9d314cc)
    
    nyan: turn on dual-output reads for SPI flash
    
    Nyan's SPI chip is capable of dual-output reads, so let's use it.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: I51a97c05aa25442d8ddcc4e3e35a2507d91a64df
    Reviewed-on: https://chromium-review.googlesource.com/177836
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 62de0889a9cfc5686800645d05e21e272e4beb5c)
    
    Squashed three commits to enable dual output spi reads for nyan.
    Also fixed the spi_xfer interface that has been updated to use bytes
    instead of bits.
    
    Change-Id: I750a177576175b297f61e1b10eac6db15e75aa6e
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6909
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 0108b936bf0f2d185691d8719c30193af39abefe
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Dec 11 11:06:08 2013 -0800

    pnp: Allow setting of misc register 0xf4 in device tree
    
    Change-Id: I602f970e0ee2fd634a74fd4c25358c2e78ca58f9
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/179536
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    (cherry picked from commit 02b0583e632f1ba53557f8cfe4293ad4ed29ff4d)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6910
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit a7991515347364504d0bd319d6a41b3750488bf3
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Dec 7 04:25:01 2013 -0800

    libpayload: x86: Add support for catching processor exceptions.
    
    This functionality is already available for ARM, so lets add it to x86 as
    well. We'll want to be able to hook exceptions when running as a remote GDB
    target.
    
    Change-Id: I42f640b08eb9eb86a1bcab3c327f7780191a2eb5
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/179601
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 5b8cf0c9f70a7e14766a2b095e6739a8d6321a34)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6898
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 125a6a22f81b3cf11732ce2a0e77652661fa0764
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Dec 6 23:30:10 2013 -0800

    libpayload: Add a timer_us() function.
    
    This function returns the number of microseconds scaled from the number of raw
    timer ticks. It accepts a base parameter which is subtracted from the current
    time, which makes it easy to keep track of relative times.
    
    Change-Id: I55f2f9e90c0e12cda430bbe88b044f12b0b563c8
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/179600
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 4dd549e18d170dbf918c5b4b11bbe1f4e99b6695)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6897
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5f43184349e75415126937c60b0fbb9dc6bd2a35
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Nov 12 09:03:33 2013 -0800

    cbfstool: add aarch64 as a name
    
    The aarch64 is not really an arm variant, it's sufficiently
    different that it can be considered (for purposes of cbfs, certainly)
    to be a new architecture.
    
    Add a constant in cbfs.h and strings to correspond to it.
    Note that with the new cbfstool support that we added earlier,
    the actual use of aarch64 ELF files actually "just works" (at
    least when tested earlier).
    
    Change-Id: Ib4900900d99c9aae6eef858d8ee097709368c4d4
    Reviewed-on: https://chromium-review.googlesource.com/180221
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    (cherry picked from commit f836e14695827b2667804bc1058e08ec7b297921)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6896
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 04b01893a94cdeb9516224e241272448d948686c
Author: Julius Werner <jwerner@chromium.org>
Date:   Mon Dec 9 15:42:53 2013 -0800

    exynos5250: Fix PMU register address map
    
    Patch 12b121f3fef61d introduced an off-by-one error in the offsets of the
    PMU register struct, which put both the newly added register and the
    PSHOLD that comes after it in the wrong place. This patch corrects the
    offsets (5420 had already been correct).
    
    Change-Id: I1d9d31a6a73ee91890824e94fbd247d5feb4f6ae
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179411
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 5fdc74bc18bcb1066a0ce3ba94829af1b175173b)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6892
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fa73875f3c016fb544c4daa8a7053905dbd1a33e
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Nov 23 00:54:40 2013 -0800

    libpayload: Add wrappers for malloc which check its return value.
    
    The xmalloc wrapper checks whether the malloc succeeded, and if not stops
    execution and prints a message. xmalloc always returns a valid pointer. The
    xzalloc wrapper does the same thing, but also zeroes the memory before
    returning it.
    
    Old-Change-Id: I00e7de04a5c368ab3603530b98bd3e3596e10632
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/178001
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 4029796d4f66601e33ae3038dbfc3299f56baf89)
    
    libpayload: malloc: Fix xmalloc() for zero byte allocations
    
    The C standard considers it legal to return a NULL pointer for zero
    length memory allocations, and our malloc implementation does in fact
    make use of that. xmalloc() and xzmalloc() should therefore not consider
    this case a failure.
    
    Also fixed a minor formatting issue.
    
    Old-Change-Id: Ib9b75df9458ce2ba75fd0bc0af9814a3323298eb
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178725
    Reviewed-by: Mike Frysinger <vapier@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 3033437e9d89c6072464860ea50ea27dcb76fe54)
    
    Squashed 2 libpayload malloc related commits.
    
    Change-Id: I682ef5f4aad58c93ae2be40e2edc1fd29e5d0438
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6890
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit d84afd3e61af870e01b5be66530ea5df4469b0c8
Author: Julius Werner <jwerner@chromium.org>
Date:   Wed Nov 13 16:06:34 2013 -0800

    arm: Remove CAR_MIGRATE Kconfig and associated cruft
    
    This is essentially a revert of commit 10bd772d. The CAR_MIGRATE
    mechanism is only useful to migrate variables from a special region
    (e.g. cache as RAM) into DRAM-backed CBMEM between different parts of
    the romstage (it does not persist into ramstage). Since ARM devices use
    SRAM for which there is no reason to become inaccessible in later parts
    of the romstage, this mechanism isn't useful for them. Removing it makes
    the romstage.ld script much simpler, which has the nice side-effect of
    putting the BSS at the end of the memory image (so that cbfstool can
    actually figure out that it doesn't need to be part of the ROM image).
    
    Old-Change-Id: I50e91d8bd51b5deb19446d9da48699edecbef6ea
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176761
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit ebfd698e57c902e2f39a0cfc1bc2b02665e47ec6)
    
    console: Make cbmem depend on x86.
    
    The cbmem implementation isn't supported on anything other than x86 right now
    and actually causes memory corruption on ARM machines. Until that's fixed, this
    will prevent people from turning it on and causing hard to track down errors.
    
    Old-Change-Id: I00e8aacf008acfe2f76d4eab82570f7c1cc89cab
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/191107
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit e54f16e346a7f2c66d802fb78a6b24e53b732b83)
    
    Squashed two related commits for cbmem support on arm.
    
    Change-Id: I2be48cea348ee5dc8ca3632d743500aa111bab08
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6888
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit 7c7b5ffabbaa55faa17adb18ebbd1de79a9c61eb
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Nov 23 00:38:49 2013 -0800

    libpayload: Add a new "die" function to fatally signal programming errors.
    
    If a programming error is detected, die can be used to print a message and
    stop execution similar to failing an assert. There's also a "die_if" function
    which is conditional.
    
    die functions, like asserts, should be used to trap programming errors and not
    when the hardware does something wrong. If all code was written perfectly, no
    die function would ever be called. In other words, it would be appropriate to
    use die if a function was called with a value that was out of bounds or if
    malloc failed. It wouldn't be appropriate if an external device doesn't
    respond.
    
    In the future, the die family of functions might print a stack trace or show
    other debugging info.
    
    Old-Change-Id: I653fc8cb0b4e459522f1b86f7fac280836d57916
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/178000
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 59df109d56a0f5346562de9b3124666a4443adf0)
    
    libpayload: Fix the license in some files which were accidentally made GPL.
    
    Some files were accidentally made GPL when they were added to libpayload. This
    change changes them over to a BSD license to be in line with the intended
    license of libpayload.
    
    Old-Change-Id: Ia95ac4951b173dcb93cb489705680e7313df3c92
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/182202
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 5f47600e50e82de226f2fa6ea81d4a3d1c56277b)
    
    Squashed the initial patch for "die" functions and a later update to
    the license header.
    
    Change-Id: I3a62cd820e676f4458e61808733d81edd3d76e87
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6889
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit aca67ed0d218fb551ef29416f079d548e77fc26f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Sep 13 20:43:45 2014 +1000

    payloads/external/SeaBIOS: Bump version to 1.7.5
    
    Change-Id: Ie4b58b739ea411035b1801348e3e73e607299846
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6900
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit eb67a04cb3c1c6149eb54a7e015d53e6e5e17de8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Sep 13 20:55:58 2014 +0200

    cbmemc: Bump default to 128K
    
    board_status shows that truncation of few KiB is pretty common.
    So bump this value.
    
    Change-Id: I78a16974846a59ee4eae782380e6d01d2fa324f2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6902
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 0650cd0bad2816886745c4a7ffe0e7a1aefb9957
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 15:03:50 2014 +0100

    southbridge/bd82x6x: Reserve 16 MiB for flash and not 8.
    
    X230 has 12 MiB flash. SPI controller supports up to 2 x 16 MiB of flash
    but address map limits this to 16MiB.
    
    Change-Id: Icc39c3c8d45d2d14e437bdfce920f8b4b039789d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5133
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 76998336aa82b692c1b0cf1e2427602b5b655fac
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 16 19:14:02 2014 +0200

    to-wiki: Add IVYBRIDGE_NATIVE to the list of ivybridge names.
    
    Change-Id: I6e63abd9491a76e362347b7616e00104305827ee
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6691
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f4ea9b2551214d5b4cf9ac528c227f2242815383
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 16 17:16:20 2014 +0200

    towiki.sh: Rename GM45 slot and cpu to correct ones.
    
    Change-Id: Idc8135911549ac39c28932065897ca6643c13656
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6690
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit a71bdc318195b864c427cddc60e69a6145a8ab28
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 30 00:35:39 2014 +0200

    intel/gma: consolidate vbt code
    
    Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6800
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 85620db107d587a8341987162d403f4b7aee9a81
Author: Julius Werner <jwerner@chromium.org>
Date:   Wed Nov 13 18:22:15 2013 -0800

    arm: Move exception_init() close to console_init()
    
    This patch adds stub implementations of exception_init() to all archs
    so that it can be called from src/lib/hardwaremain.c. It also moves/adds
    all other invocations of exception_init() (which needs to be rerun in
    every stage) close to console_init(), in the hopes that it will be less
    likely overlooked when creating future boards. Also added (an
    ineffective) one to the armv4 bootblock implementations for consistency
    and in case we want to implement it later.
    
    Change-Id: Iecad10172d25f6c1fc54b0fec8165d7ef60e3414
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176764
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 2960623f4a59d841a13793ee906db8d1b1c16c5d)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6884
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 813f305e26755aba6826c0f5baf60a65cafbefd6
Author: Julius Werner <jwerner@chromium.org>
Date:   Wed Nov 13 12:49:45 2013 -0800

    arm: Put exception_stack into BSS
    
    "Hey guys, I have this awesome idea! How about we put a huge array
    filled with 0xa5 into the data segment of our uncompressed romstage
    for no particular reason? Give our SPI driver something to do so it
    doesn't get too bored, you know?"
    
    Guess it pays off to just hexdump our image and sanity-check it top to
    bottom every once in a while...
    
    Also reduces the size because 8K is crazy just to print a bunch of
    registers (256 bytes ought to be enough for anybody).
    
    Old-Change-Id: Icec0a711a1b5140d2ebcd98338ec638a4b6262fa
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176762
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 61c360a1c3f445535c9ff383a389e643cfe4527c)
    
    arm: Remove exception_test()
    
    The exception_test() mechanism might have been useful when exceptions
    were first implemented, but now that they are pretty stable it's really
    not necessary anymore (especially not on every single boot in production
    Chromebooks). It forces a simple unaligned access, and as we start
    having exceptions in stages that might not have paging turned on yet,
    it's better to remove that completely.
    
    Also removed the duplicated implementations of SCTLR-stuff and switched
    to the existing ones in cache.h.
    
    Old-Change-Id: I85e66269f5e2f2dfd3e8aaaa18441493514b62f8
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/177101
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit d0706b848572fbea26e0e432ec5827503b9603c9)
    
    Squashed 2 exception related commits.
    
    Change-Id: Id2c115ee39a0732c375472afc0194436e2f5e069
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6885
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit edf6b57f73e3cafaecd67a71fdf7313e75c1b3e8
Author: Julius Werner <jwerner@chromium.org>
Date:   Fri Oct 25 17:49:26 2013 -0700

    tegra124/nyan: display, clock, and other updates
    
    tegra124: Set Tx FIFO threshold value to recommended setting
    Reviewed-on: https://chromium-review.googlesource.com/175200
    (cherry picked from commit c8f086711c6ae2db70fc8e0d84b54f5952fbe0ad)
    
    tegra124: add CLK_X definitions
    Reviewed-on: https://chromium-review.googlesource.com/175220
    (cherry picked from commit 3f8a844bd2f151e06d82d1a7fac4492c6bc9417d)
    
    tegra124: fix incorrect struct member in clk_rst.h
    Reviewed-on: https://chromium-review.googlesource.com/175270
    (cherry picked from commit 967193d5984a086c297988caa580b61cb4d0414c)
    
    tegra124: add the _x clocks to clock_enable_clear_reset
    Reviewed-on: https://chromium-review.googlesource.com/175539
    (cherry picked from commit df4c515d73b02061e5c98f51efd50e04b10d63f5)
    
    tegra124: add clock support code for graphics.
    Reviewed-on: https://chromium-review.googlesource.com/175162
    (cherry picked from commit b8eb6ab4cdc5a583636c10fa05f947a244f94819)
    
    tegra124: Clean up some #defines for DMA
    Reviewed-on: https://chromium-review.googlesource.com/175631
    (cherry picked from commit 1a0a900f2d060916c9878781b82113b16a7945d9)
    
    tegra124: enable flow control for APBDMA in SPI driver
    Reviewed-on: https://chromium-review.googlesource.com/175630
    (cherry picked from commit 873e6f9e95f6cb0162fa06216682fbc71ab0202d)
    
    nyan: move clock setup for the display out of dca_init
    Reviewed-on: https://chromium-review.googlesource.com/175656
    (cherry picked from commit 32dd9947a60298ff9488c911629802c257ed6afc)
    
    tegra124: more display PLL setup and clock hardcode removal.
    Reviewed-on: https://chromium-review.googlesource.com/175732
    (cherry picked from commit 80402876b5daa9e9389fd4fab5f539d89c37fa7f)
    
    tegra124: move dp.c from tegra to tegra124
    Reviewed-on: https://chromium-review.googlesource.com/175830
    (cherry picked from commit e98be569b0ba7f4d565ce677343a317db08344e0)
    
    tegra124: clean up tabbing; nyan: add a comment and setting to devicetree.cb
    Reviewed-on: https://chromium-review.googlesource.com/175889
    (cherry picked from commit 4e513196b0014c5a82079f3aa87c2efbeb645484)
    
    tegra: get rid of struct members that are not used
    Reviewed-on: https://chromium-review.googlesource.com/176023
    (cherry picked from commit 032b8a0c9fe0152ebc27344e93128865ecb918a6)
    
    tegra124: Increase SCLK (AVP) to 300MHz
    Reviewed-on: https://chromium-review.googlesource.com/175489
    (cherry picked from commit 7e082f2c2f030950d652f1f87f637e15dee38552)
    
    tegra124: Address old main CPU starting review feedback.
    Reviewed-on: https://chromium-review.googlesource.com/175933
    (cherry picked from commit 1d76ac71bd839dff9198e65132ec25212dd55ffd)
    
    tegra124: Revise clock source configuration for irregular peripherals.
    Reviewed-on: https://chromium-review.googlesource.com/176109
    (cherry picked from commit 1021c215190602a2b8c1ab97d6c8313d89597d99)
    
    nyan: add timestamps in romstage
    Reviewed-on: https://chromium-review.googlesource.com/176172
    (cherry picked from commit cd626aa10b56cd4da6ebda36fe487e44b08f3935)
    
    tegra124: Allow enabling clock output for external peripherals.
    Reviewed-on: https://chromium-review.googlesource.com/176108
    (cherry picked from commit ea9fb6393ee80da77c9fbc30f605859c7009c9ed)
    
    nyan: Enable and configure clocks for I2S and audio codec.
    Reviewed-on: https://chromium-review.googlesource.com/176104
    (cherry picked from commit 1fb659b3e73285ff8218c0f229734edd3b979ca4)
    
    tegra124: Fix typo in pinmux name.
    Reviewed-on: https://chromium-review.googlesource.com/176215
    (cherry picked from commit c7915ad41a3f1d1452aa6d6d287aaa8eb9e85c34)
    
    nyan: Add pinmux settings for audio peripherals.
    Reviewed-on: https://chromium-review.googlesource.com/176212
    (cherry picked from commit 37412f3201590e47a06d4678fa833164d370b41c)
    
    nyan: De-array-ify the PMIC setup code.
    Reviewed-on: https://chromium-review.googlesource.com/176903
    (cherry picked from commit 86ab1ce9fbf6d5362af1ee37de1394412366f247)
    
    nyan: Add a kconfig for building for the original nyans in pixel cases.
    Reviewed-on: https://chromium-review.googlesource.com/176904
    (cherry picked from commit 1d05fd5bc40d727826510ec81496ce4a49e257ed)
    
    nyan: Set the CPU voltage differently depending on which PMIC is in use.
    Reviewed-on: https://chromium-review.googlesource.com/176905
    (cherry picked from commit 31507f6a575220737ee5683b312cd162600f89cc)
    
    nyan: Increase the CPU voltage to 1.2V.
    Reviewed-on: https://chromium-review.googlesource.com/176906
    (cherry picked from commit fe4795e66b515c2523df09a8800ecac9a3f63557)
    
    tegra124: Flesh out/tidy up the flow controller constants.
    Reviewed-on: https://chromium-review.googlesource.com/177085
    (cherry picked from commit b50d315506a5ab9c81b6bbaf8cf580dbb3e78794)
    
    tegra124: When leaving the bootblock/AVP, really stop the AVP.
    Reviewed-on: https://chromium-review.googlesource.com/177086
    (cherry picked from commit 06c10df889d4d935bc99792df860d93766ae44dd)
    
    nyan: Set SPI4 speed to 33MHz
    Reviewed-on: https://chromium-review.googlesource.com/177038
    (cherry picked from commit c98de65482fabdb5c76944fe3bf762191b3a0a55)
    
    nyan: Do console_init() in romstage
    Reviewed-on: https://chromium-review.googlesource.com/176763
    (cherry picked from commit 0bec32e09eab28bc5ea49b7896a8b6f489143b03)
    
    nyan: Add a prompt to the CONFIG_NYAN_IN_A_PIXEL option.
    Reviewed-on: https://chromium-review.googlesource.com/177486
    (cherry picked from commit 7cbb801d000dac4b39f76266ebef2585fe48faba)
    
    nyan: Separate the SDRAM BCT config for the two nyans, and turn down norrin.
    Reviewed-on: https://chromium-review.googlesource.com/177487
    (cherry picked from commit 6b119685f6626d79d924af9f856ebb90af45a73f)
    
    tegra124: Bump up HCLK and PCLK
    Reviewed-on: https://chromium-review.googlesource.com/177563
    (cherry picked from commit c25337dac8c3ecdd8ffe5b4d11acebb216132405)
    
    nyan: Add some code for reading the board ID.
    Reviewed-on: https://chromium-review.googlesource.com/177488
    (cherry picked from commit 5fccbce99e7db312e2e3caf806c438c9b04c0a8f)
    
    nyan: Use the board ID to decide how to initialize the PMIC.
    Reviewed-on: https://chromium-review.googlesource.com/177489
    (cherry picked from commit 677bdb9df55248da3a0c6be0089098f6d6807d3c)
    
    nyan: Create kconfig variables for each SDRAM config.
    Reviewed-on: https://chromium-review.googlesource.com/177580
    (cherry picked from commit d7ddcf262a321f06289c4f2b2a6b43982dd96377)
    
    tegra124: Mux some unused pins away from UARTA, and pull up the serial RX line.
    Reviewed-on: https://chromium-review.googlesource.com/177637
    (cherry picked from commit bd533cc109b0acf3495b04fa6622e250ba454fe9)
    
    tegra124: Initialize the MCR when setting up the UART.
    Reviewed-on: https://chromium-review.googlesource.com/177638
    (cherry picked from commit 38c84786fc3e8fab913aebca176ac7b038cb0be6)
    
    tegra124: fix SPI AHB burst length
    Reviewed-on: https://chromium-review.googlesource.com/177564
    (cherry picked from commit f29235263202c9b4a3dbb65da5727c8eefe44315)
    
    tegra124: remove unneeded debug print in SPI code
    Reviewed-on: https://chromium-review.googlesource.com/177833
    (cherry picked from commit 34a50040268dbde1c326d315f8042a3905ddfb06)
    
    nyan: Set up the SOC and TPM reset pin.
    Reviewed-on: https://chromium-review.googlesource.com/177965
    (cherry picked from commit b81a5bd15a2979ee009b9f7bc4a39a304e6a759a)
    
    tegra124: Allow some time for packets to appear in Rx FIFO
    Reviewed-on: https://chromium-review.googlesource.com/177832
    (cherry picked from commit 8f70a25b1eea865a448525749ac18393f5b9ad84)
    
    nyan: PMIC: Slam default init values for SDOs/LDOs in AS3722
    Reviewed-on: https://chromium-review.googlesource.com/178226
    (cherry picked from commit c536b0d82fd6fffbc0e2448e0d19d3f06df5d86a)
    
    nyan: change devicetree for the new display settings.
    Reviewed-on: https://chromium-review.googlesource.com/177958
    (cherry picked from commit 43abed730f222c8a685c250a58c981268994a65d)
    
    nyan: Switch USB VBUS GPIOs from outputs to pulled-up inputs
    Reviewed-on: https://chromium-review.googlesource.com/178914
    (cherry picked from commit e47b6a609b9d23694a466b56960d9d14ca5d6242)
    
    Tegra124: nyan: Disable VPR
    Reviewed-on: https://chromium-review.googlesource.com/179327
    (cherry picked from commit 441aa276446141f1b92ed8fb98c9578597487f4d)
    
    tegra124: norrin: fix display issue
    Reviewed-on: https://chromium-review.googlesource.com/179745
    (cherry picked from commit c1c1ae69f6058ed901f532e2c532d1e6ba1f81fb)
    
    tegra124: Add iRAM layout information.
    Reviewed-on: https://chromium-review.googlesource.com/179814
    (cherry picked from commit d00f135c93a52ad4dced2edecb74e2dfc54bb2fa)
    
    tegra124: Run bootblock and ROM stage out of DRAM.
    Reviewed-on: https://chromium-review.googlesource.com/179822
    (cherry picked from commit 2d3ec06ec39a489d02e798bb22bce4d7465b20ce)
    
    nyan: clean up a comment regarding video
    Reviewed-on: https://chromium-review.googlesource.com/180161
    (cherry picked from commit 03b5e88a66b9c96df2ef3d9ce5ba4a62a8bb2447)
    
    tegra124: norrin: the first step to clean up display code
    Reviewed-on: https://chromium-review.googlesource.com/180135
    (cherry picked from commit 9d0c12dfef28a1161604df9b3fcc113049b2747d)
    
    Squashed 49 commits for tegra124/nyan.
    
    Change-Id: Id67bfee725e703d3e2d8ac17f40844dc193e901d
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6883
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 75c83870e51e6bc48a83114c64177432d3204b1f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Sep 5 01:01:31 2014 +0200

    azalia: Shrink boilerplate
    
    Change-Id: Ib3e09644c0ee71aacb067adaa85653d151b52078
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6840
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit a812643723419f4fe3f079731a9d10d2dc083aae
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Sep 13 06:53:20 2014 +1000

    mainboard/lenovo/t530: Enable PCIe Bridge for discrete graphics
    
    Change-Id: I80f1e27268d0be58514d110611fd3c18cbe81829
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6895
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Tested-by: build bot (Jenkins)

commit cf6f9b9464732b9deb862a60d0fa2b1fe1c8ae9f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Sep 13 06:06:05 2014 +1000

    mainboard/lenovo/t530: Make cdrom drive work by fixing devicetree
    
    Change-Id: I804aff0fa53609e5fc70301053f075aa54b9bde5
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6893
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 4d7d25f38abac4bcd3ea88a50b5f529f1e9ddb44
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Fri Jul 25 14:39:05 2014 -0600

    payloads/external/SeaBIOS: Allow setting buffers below 0xC0000
    
    Add the option to coreboot to set the SeaBIOS buffers below 0xC0000.
    This is a requirement on the Intel Rangeley processor
    because it is designed so that only the processor can write
    the higher memory areas.  This prevents USB and SATA from bus-mastering
    into the buffers when they're set in the typical 0xE0000 area.
    
    This will be set to Y unless defaulted to N by the mainboard or
    chipset.
    
    Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak
    
    Change-Id: I15638605d1c66a2277d4b852796db89978551a34
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6364
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit b3997ba6f2ba26e0dfa851caed98f030ac25ffd0
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Nov 12 14:46:07 2013 -0800

    arm: Remove some pointless CFLAGS
    
    This patch removes the -ffixed-r8 CFLAG from the coreboot and libpayload
    Makefiles. This seems to be a relic from U-Boot, which uses that
    register to keep it's global data structure pointer. There's no reason
    for us to throw away a perfectly fine register on this already pretty
    constrained architecture.
    
    Also removed a config.h inclusion from the Makefile because that should
    really be done inside the C files.
    
    Change-Id: Ia176c0f323c1be07cddf88fa5488788786a27cdf
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/177110
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 2a81112abde284ba09020db6afa363169911a7f6)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6880
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 8f50e53a4bb4c6f4b95398bb57d58f32fecdad93
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Nov 13 14:34:57 2013 -0800

    cbfstool: Fix architecture check when adding payload
    
    In the process of rewriting cbfstool for ARM and using
    a new internal API a regression was introduced that would
    silently let you add an ARM payload into an x86 CBFS image
    and the other way around. This patch fixes cbfstool to
    produce an error in that case again.
    
    Change-Id: I37ee65a467d9658d0846c2cf43b582e285f1a8f8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/176711
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit 8f74f3f5227e440ae46b59f8fd692f679f3ada2d)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6879
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 1b54cc919c362c63630bf134329d7f547ed586fe
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Nov 13 15:41:13 2013 -0800

    stack check: cosmetics
    
    Print a space after a full stop.
    
    Change-Id: Ic7d0522ae35079b64ce61956d06ea59843ef9d80
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/176756
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit c7ff63038b6888b17a96783b1169c5f335022b24)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6878
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 07e6bd2a5576aea1479a96b12824a794035e5d0f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Sep 12 04:01:31 2014 +1000

    lenovo/t530: Enable wake on LID and Fn key
    
    Change-Id: I09a8fe94b33c3cc1da62f7a5a527944638bd6f0c
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6877
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 3a677dbd86716ef27ad02daea09f249cd184f293
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Sep 12 03:53:43 2014 +1000

    lenovo/t530: Apply ME workaround for S3 resume
    
    Upon S3 resume, the machine powers off due to the ME not being awake yet.
    
    Change-Id: I0255dd0fa6b4cb3b539e11a69a618c770c44f4b0
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6876
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 2fc3b6281f9ac461da7dc5f916cc3e3e51e51ae6
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Oct 21 21:43:03 2013 +0800

    tegra124/nyan: various fixes and additions
    
    Tegra124: SDMMC: Configure base clock frequency.
    Reviewed-on: https://chromium-review.googlesource.com/173841
    (cherry picked from commit d3157e9a380cfb018cc69a1f23f277c3c5b680a6)
    
    Tegra124: SDMMC: Configure pinmux for MMC 3/4.
    Reviewed-on: https://chromium-review.googlesource.com/174011
    (cherry picked from commit 55af9a86a56d6bc0ce9bcff4fd5226a60ae2033b)
    
    tegra124: Move DMA-related #defines and definitions to header
    Reviewed-on: https://chromium-review.googlesource.com/174444
    (cherry picked from commit 9d917927a5b7151958289469b9049ac91efa41e3)
    
    tegra124: Assign console address for kernel.
    Reviewed-on: https://chromium-review.googlesource.com/174486
    (cherry picked from commit 36e9370f30bd173879958d164156997841ec4e9c)
    
    nyan: Fix up the gpio indices in chromeos.c.
    Reviewed-on: https://chromium-review.googlesource.com/174418
    (cherry picked from commit fba4ae1080c19f11abe1205b871ada14db996c61)
    
    Nyan: turn on the backlight.
    Reviewed-on: https://chromium-review.googlesource.com/174533
    (cherry picked from commit 12649c9611981dd8d6567ba0238c8b8247c52215)
    
    tegra124: Fix the disp1 source field.
    Reviewed-on: https://chromium-review.googlesource.com/174701
    (cherry picked from commit eed380e09075e1eef0bde7d1bb15c4343f30bfe0)
    
    nyan: set up the aux channel i2c interface
    Reviewed-on: https://chromium-review.googlesource.com/174620
    (cherry picked from commit ea81cb44a1c11cd78643c69ac818304cd393749e)
    
    tegra124: fix typos in the clock code.
    Reviewed-on: https://chromium-review.googlesource.com/174684
    (cherry picked from commit 72365c33693db4eb6e01032938221f592b7e5a02)
    
    tegra124: Revamp clock source/divisor configuration
    Reviewed-on: https://chromium-review.googlesource.com/174804
    (cherry picked from commit 3f31a634f69595bcc6a473301d1492c97a767809)
    
    tegra: Add gpio_output_open_drain() function
    Reviewed-on: https://chromium-review.googlesource.com/174650
    (cherry picked from commit bc1c28926810e722e9b82339ea0585d083e3fa8c)
    
    tegra124: add nvidia-generated files
    Reviewed-on: https://chromium-review.googlesource.com/174610
    (cherry picked from commit 7706f3200f7fc11b7a443f336bff6a37afa94652)
    
    nyan: Ignore the dev mode GPIO.
    Reviewed-on: https://chromium-review.googlesource.com/174837
    (cherry picked from commit 9513e608f3063fdb3e9d8bd04e6e5fe35a5bfcee)
    
    Tegra124: Add support for the ARM architectural timer.
    Reviewed-on: https://chromium-review.googlesource.com/174835
    (cherry picked from commit 25a91fcf7e79cc450caa59bc6b65f954bb96ac6c)
    
    nyan: Initialize the ARM architectural timer in the RAM stage.
    Reviewed-on: https://chromium-review.googlesource.com/174836
    (cherry picked from commit 581f592c12de91c0cf8279ede2850e38dd0cd2e8)
    
    tegra124: nyan: Move mainboard level clock stuff into the mainboard source.
    Reviewed-on: https://chromium-review.googlesource.com/174843
    (cherry picked from commit 5ab100b0bad22814261f9b755b59394562c9145a)
    
    tegra124: add some explanatory text about U7.1 computations.
    Reviewed-on: https://chromium-review.googlesource.com/173910
    (cherry picked from commit 822cad0ceeceeb5160c8216e05eec13fd04a6413)
    
    Set the EC SPI clock source to PLLP and divide down to around 5MHz
    Reviewed-on: https://chromium-review.googlesource.com/173954
    (cherry picked from commit c0e22d76d3887ca1f727443a47db38dec12c0b74)
    
    nyan: Move non-essential configuration out of bootblock and into ram stage.
    Reviewed-on: https://chromium-review.googlesource.com/174844
    (cherry picked from commit dad7f68c76f7b83edacd8b22c9dbd3f0ff027397)
    
    tegra124: clocks: Save some IOs in clock_enable_clear_reset.
    Reviewed-on: https://chromium-review.googlesource.com/174845
    (cherry picked from commit 81b977a2758d42471667e2cbe31f160dfda5bca4)
    
    tegra124: re-write SPI driver w/ full duplex support
    Reviewed-on: https://chromium-review.googlesource.com/174446
    (cherry picked from commit 51c9a34240d6a068780a7d1c27b032b56b2d3e54)
    
    tegra124: move SPI-related structures from .c to .h
    Reviewed-on: https://chromium-review.googlesource.com/174637
    (cherry picked from commit 36760a4463c2c33f494ca7ea5a36810fa4502058)
    
    tegra124: add frame header info to SPI channel struct
    Reviewed-on: https://chromium-review.googlesource.com/174638
    (cherry picked from commit e24773eb946e2c4cb5e828f055d45d92bd1a4f9f)
    
    tegra124: re-factor tegra_spi_init()
    Reviewed-on: https://chromium-review.googlesource.com/174639
    (cherry picked from commit 88354b996459a702c36604f5f92c24e63df8de7e)
    
    nyan: Set CrOS EC frame header parameters for SPI
    Reviewed-on: https://chromium-review.googlesource.com/174710
    (cherry picked from commit 29173ba5863eebb2864a8384435cde2f0d5ca233)
    
    tegra124: Add Rx frame header support to SPI code
    Reviewed-on: https://chromium-review.googlesource.com/174711
    (cherry picked from commit 1d1630e770804649ef74d31db194d3bde9968832)
    
    tegra124: add support for the Serial Output Resource (sor)
    Reviewed-on: https://chromium-review.googlesource.com/174612
    (cherry picked from commit 3eebd10afea4498380582e04560af89126911ed9)
    
    nyan: tegra124: Enable I, D and L2 caches in romstage.
    Reviewed-on: https://chromium-review.googlesource.com/173777
    (cherry picked from commit 74512b7ecfbd50f01a25677307084699ee8c6007)
    
    tegra and tegra124: Bring up graphics
    Reviewed-on: https://chromium-review.googlesource.com/174613
    (cherry picked from commit 7e944208a176cdac44a31e2a9961c8bd5dc4ece8)
    
    nyan: Move the DMA memory region.
    Reviewed-on: https://chromium-review.googlesource.com/174953
    (cherry picked from commit c66e22859252eaebceb07a3118ac61f4cf6289eb)
    
    tegra124: Increase CBFS cache buffer size
    Reviewed-on: https://chromium-review.googlesource.com/174950
    (cherry picked from commit 6dbb4e5f0d66c68df45ac73e3f223b856b715026)
    
    tegra124: Add USB PLL, PHY and EHCI setup code
    Reviewed-on: https://chromium-review.googlesource.com/174651
    (cherry picked from commit ecd5c398ff6748a7d40089019471357b58d3a6ea)
    
    tegra124: add in some undocument clock source and PLL registers
    Reviewed-on: https://chromium-review.googlesource.com/174948
    (cherry picked from commit 73fcc4981da6e4415b514eaafb42bc265ab0cd9a)
    
    tegra124: small cleanups of the code
    Reviewed-on: https://chromium-review.googlesource.com/174995
    (cherry picked from commit 7256aba07e9567ef8d73f05e1f80c4d45fd57bda)
    
    Squashed 34 commits for tegra124 / nyan support.
    
    Change-Id: I050c7ad962e0d24550b0b33c9318e89c80d01f00
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6870
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit bca446d47162233232209b04d1c8f78a01fcd41f
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Thu Sep 11 11:02:29 2014 -0600

    panther: update chromeos.c
    
    The google mainboards were updated to unconditionally include
    chromeos.c except for panther.
    
    Change-Id: I35bbd56326ee0f94ee542bae28f9c23980e9a9ed
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6874
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3f0f300bcf16c91c3b7763051be648caf778ec69
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Jul 8 23:15:20 2014 +0200

    cpu/intel/fsp_model_206ax/model_206ax_init.c: Correct comment
    
    Currently there is no way to enable or disable VMX during runtime using
    CMOS/NVRAM. It is only possible to configure it during build time by
    setting the Kconfig option `CONFIG_ENABLE_VMX`. So update the comment
    accordingly.
    
    Change-Id: I4e3294cb39a40cf30d294fd566bc97420592262f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6228
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8eb7c7d0a76c5586beed33fa57f38d5e4e335ca1
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 02:10:34 2014 +0200

    sch: make separate copy of nvs.h
    
    Change-Id: Ie3a843a76ebf9f5d825e14c4359fb3ecaa052e38
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6809
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5fcae806531a0c4a9a8216c2a1a16d326eb2a1db
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jul 29 14:42:26 2014 +1000

    lenovo/t530: Use native LVDS gfx init
    
    As introduced in:
    1783a3c ivybridge: LVDS gfx init.
    
    The panel on the T530 is a AUO B156HW01 V.4, 40 pin LVDS (2 ch, 6-bit).
    Tx parameters derived from datasheet table.
    
    Change-Id: I2e3b56a2a3d1ede08a704b839cc11fe6d685cf5b
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6395
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 1633261979a9cdec4e6b0ebeb12dac361d3cd8a4
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jul 29 14:09:27 2014 +1000

    lenovo/t530: Use native raminit over MRC blob
    
    We now have Native raminit for both sandy/ivybridge introduced in:
    
    7686a56 sandy/ivybridge: Native raminit.
    
    Let us make good use of this support over using the Intel MRC blob to
    initialise memory.
    
    USB RCBA configuration data taken between base of 0x3500 up to 0x3600
    from `inteltool -r`.
    
    Remark: Note the current port is poorly tested at the moment and I am the
    sole maintainer, however one less blob invites more interest for better
    support. More to come hopefully.
    
    Change-Id: I41d0ef8303dfd369c5565b823e68a6bee09c44f5
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6394
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit de40e0dd1172f6091fbc4b9bc7b0d9825ff532ba
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Sep 12 04:00:44 2014 +1000

    lenovo/t530: Remove empty mainboard.asl
    
    Change-Id: Iaccaf5246e7ac5da2b51dd915c3f3ef807fc6467
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6875
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <gaumless@gmail.com>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 47d37b9ab255fded3df1163b126397b4ee6d9830
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Aug 28 01:14:00 2014 +0200

    ec/lenovo/h8: return correctly typed package if battery is absent
    
    Fixes "Discharge rate invalid message" and fwts error.
    
    Change-Id: I51f9d819f164552567d75f83c95ba7523e97343e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6793
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 08ba7d0c27f359919e707b563169e9d54decb1aa
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Oct 31 15:58:50 2013 -0700

    pnp: Allow setting of misc register 0xfa in device tree
    
    Change-Id: I45885905f0adaa8f0ad9137d7034e6f7a0dc43de
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/175356
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit 7fe642543a8de249e13c3d63c3302a20910c247d)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6859
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d40be1107c27417cb4e08d25ddcca54049d4f7a0
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Oct 9 23:45:07 2013 -0700

    tegra124/nyan: rougly stable code base
    
    nyan: Clock setup.
    Reviewed-on: https://chromium-review.googlesource.com/172106
    (cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1)
    
    tegra124: Call into the mainboard bootblock init if one exists.
    Reviewed-on: https://chromium-review.googlesource.com/172581
    (cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec)
    
    nyan: Add a mainboard specific bootblock.
    Reviewed-on: https://chromium-review.googlesource.com/172582
    (cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69)
    
    nyan: tegra124: Redestribute the clock code between the mainboard and soc.
    Reviewed-on: https://chromium-review.googlesource.com/172583
    (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b)
    
    nyan: Initialize the i2c pins and controllers.
    Reviewed-on: https://chromium-review.googlesource.com/172584
    (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8)
    
    nyan: Initialize the PMIC.
    Reviewed-on: https://chromium-review.googlesource.com/172585
    (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a)
    
    tegra124: add a chip.h and use it in NYAN
    Reviewed-on: https://chromium-review.googlesource.com/172773
    (cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f)
    
    tegra: Reorder GPIO register accesses to avoid glitching
    Reviewed-on: https://chromium-review.googlesource.com/172730
    (cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5)
    
    tegra: Turn GPIO wrappers into macros to make them easier to write
    Reviewed-on: https://chromium-review.googlesource.com/172731
    (cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c)
    
    tegra: Change GPIO functions to allow variable arguments
    Reviewed-on: https://chromium-review.googlesource.com/172916
    (cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d)
    
    tegra124: Implement starting up the main CPUs.
    Reviewed-on: https://chromium-review.googlesource.com/172917
    (cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3)
    
    tegra: Simplify the I2C constants.
    Reviewed-on: https://chromium-review.googlesource.com/172953
    (cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76)
    
    tegra124: Fix SPI base addresses
    Reviewed-on: https://chromium-review.googlesource.com/173322
    (cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357)
    
    tegra124: Scrub the clock constants.
    Reviewed-on: https://chromium-review.googlesource.com/172954
    (cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4)
    
    tegra124: add DMA support
    Reviewed-on: https://chromium-review.googlesource.com/172951
    (cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8)
    
    tegra124: add basic SPI driver
    Reviewed-on: https://chromium-review.googlesource.com/172952
    (cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429)
    
    tegra124: Add an assembly stub which is run first on the main CPUs.
    Reviewed-on: https://chromium-review.googlesource.com/173541
    (cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de)
    
    nyan: tegra124: Set up dynamic cbmem.
    Reviewed-on: https://chromium-review.googlesource.com/173542
    (cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f)
    
    tegra124: Add an soc.c which sets up the chip operations and memory resource.
    Reviewed-on: https://chromium-review.googlesource.com/173543
    (cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4)
    
    tegra124: extend chip.h to include video settings
    Reviewed-on: https://chromium-review.googlesource.com/173600
    (cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29)
    
    tegra124 and nyan: fill in the devicetree a bit more, add defines
    Reviewed-on: https://chromium-review.googlesource.com/173684
    (cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147)
    
    tegra124: clean-ups for SPI driver
    Reviewed-on: https://chromium-review.googlesource.com/173599
    (cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7)
    
    tegra124: add a #define for DMA alignment size
    Reviewed-on: https://chromium-review.googlesource.com/173638
    (cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af)
    
    tegra124: Add FIFO transmit functions to SPI driver
    Reviewed-on: https://chromium-review.googlesource.com/173639
    (cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7)
    
    tegra124: clean-ups for DMA driver
    Reviewed-on: https://chromium-review.googlesource.com/173598
    (cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0)
    
    tegra124: early display and display code.
    Reviewed-on: https://chromium-review.googlesource.com/173622
    (cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558)
    
    tegra124: Move transfer size handling to spi_xfer()
    Reviewed-on: https://chromium-review.googlesource.com/173680
    (cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621)
    
    tegra124: strict error detection and reporting for SPI
    Reviewed-on: https://chromium-review.googlesource.com/173681
    (cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010)
    
    tegra124: add thread-friendly delays to SPI driver
    Reviewed-on: https://chromium-review.googlesource.com/173648
    (cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e)
    
    Tegra124: Take the SPI1 controller out of reset and enable its clock.
    Reviewed-on: https://chromium-review.googlesource.com/173787
    (cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2)
    
    tegra124: add two more clock setting values
    Reviewed-on: https://chromium-review.googlesource.com/173772
    (cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57)
    
    nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC.
    Reviewed-on: https://chromium-review.googlesource.com/173788
    (cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8)
    
    tegra124: Add some stub functions to the Tegra SPI driver.
    Reviewed-on: https://chromium-review.googlesource.com/173789
    (cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2)
    
    tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS.
    Reviewed-on: https://chromium-review.googlesource.com/173790
    (cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084)
    
    nyan: Implement the code which reads GPIOs for ChromeOS.
    Reviewed-on: https://chromium-review.googlesource.com/173791
    (cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3)
    
    nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options.
    Reviewed-on: https://chromium-review.googlesource.com/173792
    (cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e)
    
    Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks.
    Reviewed-on: https://chromium-review.googlesource.com/173793
    (cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88)
    
    tegra124: fix clear_fifo_status() in SPI driver
    Reviewed-on: https://chromium-review.googlesource.com/173738
    (cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f)
    
    ARM: Include stdint.h in cpu.h.
    Reviewed-on: https://chromium-review.googlesource.com/173774
    (cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6)
    
    tegra124: When setting up the main CPU, set its CPSR appropriately.
    Reviewed-on: https://chromium-review.googlesource.com/173775
    (cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead)
    
    tegra124: fix wrong names in clk_rst.h
    Reviewed-on: https://chromium-review.googlesource.com/173955
    (cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d)
    
    tegra124: Fix up the PLLX divider table.
    Reviewed-on: https://chromium-review.googlesource.com/173778
    (cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17)
    
    tegra124: clock: Get rid of cpcon and dccon.
    Reviewed-on: https://chromium-review.googlesource.com/173779
    (cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7)
    
    Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus.
    Reviewed-on: https://chromium-review.googlesource.com/173953
    (cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355)
    
    armv7: expose dcache_line_bytes() in cache API
    Reviewed-on: https://chromium-review.googlesource.com/173975
    (cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12)
    
    libpayload: expose dcache_line_bytes() in ARM cache API
    Reviewed-on: https://chromium-review.googlesource.com/174099
    (cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9)
    
    armv4: add a stub for dcache_line_bytes()
    Reviewed-on: https://chromium-review.googlesource.com/173976
    (cherry picked from commit 924f61ea895b9268c716791466637009bbac6469)
    
    tegra124: Base early UART on CLK_M to enable debugging of PLL init code
    Reviewed-on: https://chromium-review.googlesource.com/174339
    (cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa)
    
    tegra124: Add additional PLLs and redesign the divisor table
    Reviewed-on: https://chromium-review.googlesource.com/174380
    (cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384)
    
    Squashed 49 commits for tegra124/nyan that included a lot of churn on
    different pieces.
    
    Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6869
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 35c0f439fc2bc29817d643a7629a4d2b79d6b903
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Sep 2 22:25:36 2014 +0200

    Move nehalem/sandy/ivy to per-device acpi
    
    Change-Id: I3d664ab575bf9c49a7bff9a395fbab96748430d0
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6802
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 955ca5d948519e89573b1508bb85d3b01353ac60
Author: Andrew Litt <ajlitt@splunge.net>
Date:   Tue Sep 9 10:49:19 2014 -0500

    mainboard/google/parrot: fix ACPI interrupt storm on lid switch change
    
    This fixes the ACPI interrupt storm on Parrot that happens when
    closing the lid or entering suspend by lid close (seen in
    /sys/firmware/acpi/interrupts/gpe1F). This patch inverts the interrupt
    trigger level every time the interrupt is received so that it doesn't fire
    until the next state change.  http://askubuntu.com/questions/310196
    is a good example of what this is trying to solve.
    
    Change-Id: I8b095914e9330c3217a4ceb058613fa952f4a234
    Signed-off-by: Andrew Litt <ajlitt@splunge.net>
    Reviewed-on: http://review.coreboot.org/6858
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 802c910fa39d7245c96ad055988ccfc3a3ab26c1
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Aug 28 23:03:15 2014 +0200

    Increase space for ACPI tables when using dynamic CBMEM
    
    Unlike in old style CBMEM, dynamic CBMEM does not have a
    hand-calculated, hard-coded size, so allow up to 144K of
    space for ACPI tables.
    
    Change-Id: Id9dd7447c46d5fe7ed581be753d70e59add05320
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/6795
    Tested-by: build bot (Jenkins)
    Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit dac17a74156a3eea2cc92c336b552165741119cb
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Sep 5 23:53:39 2014 +0200

    roda/rk886ex: Move dummy DCC ON# to finalize stage
    
    During Vladimir's ACPI cleanups, this was moved into the mainboard's
    enable stage, which will prevent the VGA option rom from executing
    correctly. Move it to the finalize stage to make sure it runs after
    all initialize functions have been called.
    
    Change-Id: I0fcca4d4a95f89382f377ce923f82ecb71467fd8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/6845
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Tested-by: build bot (Jenkins)

commit 8932f11c91d9f8b80af562936c8b5c82af9a3c29
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Oct 9 23:45:07 2013 -0700

    tegra124: Make tegra124 compilable with serial turned off.
    
    The bootblock and romstage UART consoles were being built in based only on
    whether or not the bootblock and romstage consoles were selected, ignoring
    whether serial console support was compiled in generally.
    
    Change-Id: I3866519c422a990c44ced66885108eff24894563
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/172580
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit a4f2dd4902a05884693e6e350b6be29276d16981)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6862
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 58f306258067f1df231d9c01a60930c2ee815dbc
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Oct 4 06:17:22 2013 -0700

    nyan: Use the new pinmux functions as part of UART setup.
    
    The pins for the UART had been configured manually using hardcoded offsets and
    values. Now that we have pinmux functions for that sort of thing, we should
    use that instead. This also provides a very simple test for the pinmux code.
    
    Ultimately this code should be wrapped in a function which handles setting up
    any of the UARTs which is appropriately parameterized and which would be
    called from the bootblock main instead of being in it, but for now this is
    sufficient.
    
    Old-Change-Id: I69e36fa5fc9b6f3f5ef7f1be3e9f18cdbfdd7fe9
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171807
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit d29e655b68143e86199ab1d74f89e125b16b67cc)
    
    tegra124: Call the set_avp_clock_to_clkm function in the bootblock.
    
    We had a hardcoded version of the set_avp_clock_to_clkm function in the
    bootblock, and we had to use it until now because the real version uses
    udelay, and until now that hadn't been implemented. Also, replace the delay
    loop in the hacky_hardcoded_uart_setup_function with a call to the real thing.
    
    Old-Change-Id: I6df9421bcad484e0855c67649683d474d78e4883
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/172045
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 4c6dd4c7cade7d922a258e0371e43972bce77249)
    
    Squashed two tegra124 bootblock related commits.
    
    Change-Id: I0ce6321a04b11b7f1250ef3816fe46732777988d
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6861
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit dda0e66d9c0d834acb5cda6dc85c273eeaecd48a
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Nov 6 11:21:48 2013 -0800

    Exynos5420: Fix up the i2c driver for use with the TPM driver
    
    The TPM driver expects to call i2c_read with zero address length. The i2c
    driver wasn't prepared to handle that particularly in the case of reads
    because it expected to send an address before switching over to read mode for
    the data. This change also fixes up the read and write calls to consistently
    be read32 and write32 instead of readl and writel.
    
    Change-Id: I33dee89b83d4cd9d3e1b90e84b40e761bb8d4de4
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/175966
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit cf686269424ea938d6f953d0f76103182eb71297)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6857
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9b47231d2edfbdf47ade686ebc614810a26c0675
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Nov 13 14:49:51 2013 +0800

    samus: Fix 8GB SPD
    
    The 8GB variant is x16 with 11 column bits and 4Gb density.
    
    Change-Id: I3aa647aba88dbc928fefd826cbd01e4fa8273660
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176640
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit d18462f6fc0d40328e9619525240778ea6b1a426)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6856
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d518c7a2d7ba839f0480a933a7a7c6d7f797e3bf
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Nov 4 17:38:32 2013 -0800

    tpm: Clean up I2C TPM driver
    
    Drop a lot of u-boot-isms and share common TIS API
    between I2C driver and LPC driver.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I43be8eea0acbdaef58ef256a2bc5336b83368a0e
    Reviewed-on: https://chromium-review.googlesource.com/175670
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 3fc8515b9dcef66998658e1aa5c020d22509810c)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6855
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5c85e66b178c4fb4ddc6bcd98d13f43f9ad58792
Author: Julius Werner <jwerner@chromium.org>
Date:   Thu Oct 17 14:31:36 2013 -0700

    libpayload: usbhid: Fix typo on descriptor parsing
    
    Forgot an asterisk and everything goes to hell. Sorry about that.
    
    Change-Id: I6b2503ca3ea0f80d4e4e5d8b8c0e986fec5db2c9
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/173587
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: David James <davidjames@chromium.org>
    (cherry picked from commit 2a357560a697b56cc6022a4dd3dda47b33568d83)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6854
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8e7a9e1c4e760d8dc6e688b8c3adb9e0f5b40608
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Oct 29 11:31:40 2013 -0700

    libpayload: ehci: Fix byte count in dump_td()
    
    The dump_td() debug function in the EHCI stack incorrectly masks the
    amount of transferred bytes on output... the actual field is 15 bits
    wide (30:16). Let's just use the mask constant we already have for all
    the other code.
    
    Change-Id: I28c6f0ec75cc613e38d53b670645d19bf9ffe1b9
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174986
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit 570077da7f16bbe2204b4a80790e4bd8fe1a2bd7)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6853
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 587193d4613653d975ff6a3a707596450d0b0120
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Oct 31 11:31:20 2013 -0700

    samus: GPIO updates for Proto1b
    
    Move NFC_INT to GPIO9
    Swap CODEC_INT to GPIO46 and WLAN_DISABLE_L to GPIO42
    Swap ACCEL_INT to GPIO45 and PP1800_CODEC_EN to GPIO43
    Enable PP1800_CODEC_EN, CODEC_LDOENA, CODEC_RESET_L
    
    Old-Change-Id: I5547d34f1b7953808375aa5fe5e0a9640ae7e05e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175291
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 5bb4bc59e37ee4fe9a0556e08a53402c822e5bd6)
    
    samus: Misc fixes from proto1b bringup
    
    - NFC interrupt is expected in the kernel as a GPIO now,
    so set it back to that type
    - NFC FW update GPIO should be low
    - Accel/Codec interrupts were still set as GPIO type,
    they should be set as PIRQ type
    
    Old-Change-Id: I354c848ae7b158943f4745872b82a49e17e67e2f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176513
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 75a0944f320c80618f12732a23344ce40010a688)
    
    Squashed two small patches for samus.
    
    Change-Id: I7ec56191fe2b7f19e470df175ad0bbe320a442f5
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6852
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 91b30d364aaf7d9ca1a189189bfc6666e98553e2
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Sep 26 16:27:55 2013 -0700

    nyan: Add a stub mainboard.
    
    Old-Change-Id: Icdde4cf5e1abb3ae1ad14279ebc129919ba30074
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/170837
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit e9d87534ccacb42d508f1902786470798a2dbaea)
    
    nyan: Add a "special-class" for aggregating BCT files into bct.cfg.
    
    The config file which cbootimage processes to create a BCT could come from
    multiple different files, individually selected based on config options,
    and/or split up into different files for organizational purposes. This change
    adds a special-class which collects those files and concatenates them all
    together in a bct.cfg which can be processed more easily by other parts of the
    build.
    
    While the BCT files themselves are potentially very board specific, for
    instance ones that hold memory timing information, this bit of code which
    collects them is not. It has to be in each board file instead of alongside the
    CPU, however, to ensure that the special class is set up before another
    Makefile tries to use it. If we end up with lots of Tegra based boards which
    duplicate this code over and over, we might want to revisit how this works.
    
    Old-Change-Id: I58e1373434f89e69298990ea4643a19d8afdc309
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/170922
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 3ae44178b7084037a75e16ce161b1432abf4246a)
    
    nyan: Add bct files for nyan.
    
    There's a config option which selects between the emmc and spi config files
    depending on what the firmware is intended to boot from. These are copied from
    the files installed by the tegra-bct-nyan ebuild, except that the spi config
    file has been modified so that there's only one copy of the BCT and so that it
    only has one configuration. This is to save space in the final image.
    
    Old-Change-Id: Ibf1b895bb3ed060d394fc6ffcec67b6972bb21e3
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/170923
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 6bbcffe04e8ae73c86bc05c577a67f909857e1c0)
    
    Squashed three commits required to get nyan building since some patches
    were out of order. Added a select to the nyan mainboard Kconfig to have
    a rom size of 1024K to match the saved config on the chromium side.
    
    Change-Id: I346dbb02d216adfea9707e40adf0a4d1e0fabf36
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6669
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 3a92be72f868249e6b0ab3853cda4c22bcf81ff2
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Mon Sep 8 15:28:17 2014 -0600

    nvidia-cbootimage: integrate into coreboot make
    
    Add rules for building the nvidia-cbootimage utility and add dependencies
    to the tegra124 platform.
    
    Change-Id: Ia9f26981bccd217fe79e1b5dd432ee7da868d22a
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6851
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit a447e48453bf95dde41cd7597a2b0890c65bdd43
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Sun Sep 7 15:21:31 2014 +0200

    lenovo/t520/acpi/gpe.asl: fix ExpressCard gpe configExpre
    
    ExpressCard is connected to PCIe port 4.
    
    Change-Id: I0cffabd9d9435d24a7e9c178c2f96fb1a9390320
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/6850
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f98e66825b72dab5face6b771fa0d93e5bf49028
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Sat Sep 6 18:03:05 2014 +0200

    lenovo/t520/hda_verb.h: update azalia codec config
    
    Replace codec config copied form T530 with dumped values from T520
    /sys/class/sound/card0/hdaudioC0D0/init_pin_configs.
    Intel Azalia HDMI is always enabled, but DP isn't connected to a
    connector.
    
    Change-Id: Iabdae4a6669ff429d5769a1bb0c0fb1abc12ba82
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/6849
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 1bcb4078f92ee33de63e8f99d88e33d1842cea51
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Sat Sep 6 14:09:52 2014 +0200

    lenovo/t520/gpio.h: Fix current gpio configuration
    
    Change-Id: I67f321583211efd9ed917276cc3989c6dc4ac649
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/6848
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit a4a44a7b9a922da9bf3fbc692a05697715139814
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Oct 3 14:02:45 2013 -0700

    arm: Update a stale comment in bootblock .S files
    
    This just updates a comment which refers to "board_init_f". We use
    bootblock main() in coreboot.
    
    Change-Id: I4cb6b3c11f163b67fe48de495d13dce88710efc0
    Reviewed-on: https://chromium-review.googlesource.com/172095
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 65139f29682cedca8dfb58b3dfe67eab64299064)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6791
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit b6b1077eec1a2afa84d0c8d469ad2e339cb775ef
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Dec 8 12:48:45 2013 -0800

    exynos: Install the BL1 and set the checksum in the Makefile.
    
    Install the BL1 and set up the checksum in the Makefile instead of relying on
    post processing. Import the exynos checksum script, split it in two and
    simplify it significantly. Stop putting the CBFS header in the midst of the
    bootblock so that it can be checksummed before CBFS is put together. Stop
    saving space for it and leaving an anchor in the bootblock which nobody looks
    for.
    
    Change-Id: Icbb5a5914ece60b2827433b6dc29d80db996ea6c
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/179229
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit aa3a416705517c0a6ddfdeb19905ac8cafb33df1)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6834
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 063c410a5429cabffbabb11388b76740bea0e6ab
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Oct 3 19:18:44 2013 -0700

    ARMv4: Add a minimal version of cpu.h.
    
    All this version does is define asmlinkage to be nothing. It's required by the
    threading header file which is brought in by the timer implementation which I
    think is the hook for thread switching.
    
    Change-Id: Id57261d7c2c5ff8be00b0ad71bf7aaa9f3e24c1d
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171801
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit e00379f54802066fd3e0685b291cdec289078055)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6831
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 2ceb1d8be6ef09efd66153a9ad6023843b514996
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Oct 1 05:24:47 2013 -0700

    tegra124: Switch the bootblock over the ARMv4 impelementation.
    
    The bootblock for the tegra124 runs on the AVP coprocessor which uses the
    ARMv4 architecture. Switch it over to that architecture.
    
    Change-Id: Ie527bbff938e6148c58727d448f9c2e6862da872
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171402
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit c1aa76b7607ee40ff848628971a97eea5393aebe)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6784
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Tested-by: build bot (Jenkins)

commit f2f817ed1d5494b8ded166306564d16673fbf02c
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Oct 1 05:20:17 2013 -0700

    ARM: Add an ARMv4 architecture version.
    
    This is needed for the tegra124's bootblock and includes enough implementation
    to support that use. No caching is supported, although there are function
    prototypes and stub implementations to satisfy includes and linking.
    
    Change-Id: Ib79dde8c30eda98b3e823cba2ff6115a610bb2e8
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171401
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 221dc76b3ce4c1d73851c432333e091e1c60f0cb)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6783
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 70ad39e77524a45109830fdcba53143b0e0e2723
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Sep 6 16:06:57 2014 +0200

    getac/p470: Add some more board info data
    
    Change-Id: I7cf47a16928436734df29af951f987db9cf9530d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6847
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3a75e5e8642d05d644ee3bccb92d8657ac2dadf0
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Mon Oct 28 15:01:54 2013 -0700

    Haswell/falco/peppy/slippy: continue to clean up FUI.
    
    As a first step towards removing hardcodes from the FUI support,
    change the haswell call to i915_lightup to panel_lightup, and pass the
    intel_dp * as a parameter. Get rid of the scalar arguments and make
    them part of intel_dp. Get rid of file-scope variables and use the
    ones in the intel_dp struct. In falco, use functions that peppy
    uses. Drop slippy support for FUI, it's a dead board; if this is ok
    I'll remove the files next.
    
    And, incidentally, fix the broken RGBX constant and change it to BGRX.
    
    Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/174932
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    (cherry picked from commit 1e1ed410b445c8e2b7411e163d9d6f61499dc3f6)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6833
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 2120e0e200d41e4b29d5e035d8ae5c219a54c495
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Oct 9 15:53:43 2013 -0700

    FALCO: stop using the slippy graphics code
    
    It's time to start cleaning up the falco graphics code, but it needs
    to have its own files, not slippy's.
    
    Change-Id: I7dbe27eafbf247b5c7806819bf0059d8b10e842c
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/172501
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 262a0c16a39871d14972a92bff2dbc24de2ca3f0)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6832
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 79634759e5961c1c2538b1f96b97bbda277f5db0
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sun Oct 13 10:57:50 2013 +0800

    samus: Disable SMBus controller
    
    Nothing is connected to this port.
    
    Change-Id: If3e466a3053fa694a511c2335c16381f77f56f47
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174089
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 5ddb6a444d5c3141868eaf618ecb014b0262a796)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6827
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit d68932463f0a5c23ebe19cce4465ed5a17dbb5eb
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Wed Sep 3 15:34:05 2014 -0600

    tegra124: return the UART base address based on index
    
    Change-Id: I73a8e56559c7ffdaab39a5c19311221c91565004
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6830
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 33e295e66fe6fa5d7f2fead3bbbe30b6bfd5dca4
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Oct 22 16:37:39 2013 -0700

    samus: Tweaks from bringup
    
    - GPIO29 is no longer connected so we don't need the SMI workaround
    on the entry to sleep states.
    - Disable touchscreen wake source until the kernel driver is working
    so it does not wake immediately.
    - Update a few GPIOs and disable the codec for now as it is leaking
    into the 1.8V DDR rail.
    
    Change-Id: Ia67b17eb4a097627befd8f39aadc939da1bf3d40
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174122
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 0fdc9a83a434378499f825d072ce0adba5ffda59)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6829
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fe74092c4e802efbed76804fb43f0bd25a5721b2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Oct 22 16:35:12 2013 -0700

    samus: Fix up memory SPD information
    
    The LPDDR3 memory is x32 and dual rank with 14 row bits.
    
    In addition the memory is actually elpida, even though
    they are owned by micron it is confusing to label it as such.
    
    And the ram strap options were inverted from what I expected
    so the memory table needs to be updated.
    
    Change-Id: Ia29a23e8140d884fb84f940806f041b40562aab9
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174121
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 0d63d36b8035165f95db798ed40488519e622a65)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6828
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 50fc0b4cabcff9680aa53aaeaf1a54dc8e7d12de
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sun Oct 13 10:57:01 2013 +0800

    samus: Add onboard device configuration
    
    Change-Id: Ib7b6688982e9f74cffe40d11d4a9ec69acd55d37
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174088
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 41624b073fb59b1372ee5a8eba3ed64c7e633311)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6826
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1eca1d4e15c254b1f63336b991bf1a81b70712c0
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Oct 12 11:50:05 2013 +0800

    samus: Change thermal behavior to match other haswell platforms
    
    Change-Id: Ia835f16b156949f1841210c4a469223d5df28a54
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174087
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 8e51d1d74cdcadde9cbf10e8321d601b099c46bc)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6825
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 51edd54738b2248e92580caa317aa4e8e1694d40
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Sep 30 23:00:33 2013 -0700

    ARM: Generalize armv7 as arm.
    
    There are ARM systems which are essentially heterogeneous multicores where
    some cores implement a different ARM architecture version than other cores. A
    specific example is the tegra124 which boots on an ARMv4 coprocessor while
    most code, including most of the firmware, runs on the main ARMv7 core. To
    support SOCs like this, the plan is to generalize the ARM architecture so that
    all versions are available, and an SOC/CPU can then select what architecture
    variant should be used for each component of the firmware; bootblock,
    romstage, and ramstage.
    
    Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171338
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    
    ARM: Split out ARMv7 code and make it possible to have other arch versions.
    
    We don't always want to use ARMv7 code when building for ARM, so we should
    separate out the ARMv7 code so it can be excluded, and also make it possible
    to include code for some other version of the architecture instead, all per
    build component for cases where we need more than one architecture version
    at a time.
    
    The tegra124 bootblock will ultimately need to be ARMv4, but until we have
    some ARMv4 code to switch over to we can leave it set to ARMv7.
    
    Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7
    Reviewed-on: https://chromium-review.googlesource.com/171400
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483)
    
    Squashed two related patches for splitting ARM support into general
    ARM support and ARMv7 specific pieces.
    
    Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6782
    Tested-by: build bot (Jenkins)

commit 94b4a266fb4df1f2f59ed8052c150ee4bf3e6d41
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Thu Sep 4 11:17:56 2014 -0600

    nvidia-cbootimage: add submodule
    
    Change-Id: I3ad8eed42255db426987065190c197baead40673
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6836
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 34e76152351a9c846d850064990a37e3d453d97f
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Sep 5 23:54:04 2014 +0200

    romcc: avoid use-after-free
    
    Windows bugchecks on this for a while, so we ifndef'd the free() call out.
    Now some Linuxes (depending on their glibc) also fail on it, so just
    remove the call altogether at the cost of some leaked memory (couple
    hundred kilobytes) because tracking down the precise fix is too hard.
    
    In case someone wants to fix it, valgrind sees the issues, so
    revert this change and work on romcc's memory management until valgrind
    is happy.
    To get a fix in, provide a good explanation why your change is actually
    the right way to fix it - for silencing valgrind, this change will do.
    
    Change-Id: Iae3f847e09a0d7bcb8bb4f50983a1b0727570b23
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6846
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 2d7bd8a6ebf6844b0cdef80eaaef69f39d08f076
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 30 19:28:05 2014 +0200

    Implement ACPI in a per device way
    
    This approach avoids having same basic tables 150-lines mantra over 100 times
    in codebase.
    
    Change-Id: I76fb2fbcb9ca0654f2e5fd5d90bd62392165777c
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6801
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit a2a906e47a87acc3acdca0ee2790ff96409b9b46
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Sep 1 01:41:37 2014 +0200

    Consolidate intel vga int15 hooks
    
    Change-Id: I9366dded98bf15f6da44ce893dd10698ba09fd55
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6820
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit a4857052f756507e18a54beba704f183f128a057
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 01:09:12 2014 +0200

    i82801gx: Kill unused TCG and SMI1
    
    SMI1 is being written to but never read from.
    
    Change-Id: I82c0800713e3093eb1317b5e1f6f228771134857
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6808
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c403e42f21bc77af6db3a4222e796c102ac7e6d0
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Sep 4 18:32:52 2014 +0200

    what-jenkins-does: kill build results early
    
    This reduces disk use and simplifies using abuild on
    a ramdisk.
    
    Change-Id: I3fb8d273dcbb5008fa9cfaa9465a59e3bbcb974b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6835
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5dfd6819785590a1c4ea092160b78fe59a54a684
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 00:30:26 2014 +0200

    roda/rk886ex: Move device changes to mainboard code from acpi tables code
    
    Change-Id: I3d694e5b3092d78bce89f6baa7b2dedffddf3012
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6807
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 02d674ac2f9b238ea83ba31e3e4f32d25f9fedf6
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Sep 4 22:04:11 2014 +0200

    azalia: Use convenience macros throughout
    
    Change-Id: Ic044bf155bfcf93fa7cf3afd7287b7d0b615ef6d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6839
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f91ecce609ed8f90de5840e265cb3da3520ab591
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Sep 4 21:47:03 2014 +0200

    azalia: Change specific PIN_CFGs to generic AZALIA_PIN_CFG
    
    Change-Id: I3463d0c283793547b00a7628f27f2f1777c21238
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6838
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8f0da582abc8f522b7eacd4e35295091abb19be2
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Sep 4 21:34:13 2014 +0200

    azalia: Add convenience macros
    
    Change-Id: Ie605efdda3b486ae6ef780266e6c651e41bb5392
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6837
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 79f47cf8c0c54848ee13b727482ff8936a68e1f5
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Fri Aug 15 12:38:21 2014 -0600

    mainboard: Add AMD DB-FT3b (Olive Hill+) with Steppe Eagle SoC
    
    Create a new mainboard based on the AMD DB-FT3 development board
    (Olive Hill) using an AMD Steppe Eagle processor.  The actual DB-FT3
    and DB-FT3b mainboards are identical except for the soldered-down
    SoC device.  The new AMD DB-FT3b development board (Olive Hill+)
    features:
    
    	* Mini-ITX form factor
    	* 2x DisplayPort
    	* 1x VGA
    	* Integrated Realtek RTL8111-compatible Ethernet
    	* 2x USB 3.0 ports
    	* 2x USB 2.0 externally-accessible ports
    	* 2x USB 2.0 internally-accessible ports (via headers)
    	* micro LPC header
    	* Integrated platform security processor
    	* 2x Full-size DDR3 DIMM support (1 channel)
    	* Realtek ALC272 HD audio
    	* 2x SATA ports
    	* 1x SD card slot
    	* 1x PCIe (x4) slot
    	* 1x mini-PCIe slot
    	* 8-pin programming header
    
    Eliminate the extraneous headers included in PlatformGnbPcie.
    
    BiosCallOuts normally has a bunch of extraneous references to the
    mainboard name.  Rather than correct the spelling of a bunch of
    instances, just get rid of them.
    
    For the most part, use the Olive Hill ACPI definitions since the
    DB-FT3b board ("Olive Hill+") and Olive Hill are the same board
    with different processors.
    
    Change some function prototypes for functions without parameters
    to void instead of AGESA's VOID.  There are no parameters for
    these functions, so there is no real reason to use VOID.
    
    S3 and fan control are not supported.  HD audio is not working.
    
    Change-Id: I794d7a8f4f948346cfe7cbd443c9aed5f70c99ed
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6681
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 3c12cb03847d2db41809ae434530782a7dbef48b
Author: Curt Brune <curt@cumulusnetworks.com>
Date:   Fri Aug 29 10:43:36 2014 -0700

    cbfstool:linux_trampoline: config CS and DS segment descriptors
    
    The Linux trampoline code does not set up the segment descriptors for
    __BOOT_CS and __BOOT_DS as described in the Linux kernel
    documentation:
    
      ... a GDT must be loaded with the descriptors for selectors
      __BOOT_CS(0x10) and __BOOT_DS(0x18); both descriptors must be 4G
      flat segment; __BOOT_CS must have execute/read permission, and
      __BOOT_DS must have read/write permission;
    
    This is not a problem when launching a Linux payload from coreboot, as
    coreboot configures the segment descriptors at selectors 0x10 and
    0x18.  Coreboot configures these selectors in the ramstage to match
    what the Linux kernel expects (see
    coreboot/src/arch/x86/lib/c_start.S).
    
    When the cbfs payload is launched in other environments, SeaBIOS for
    example, the segment descriptors are configured differently and the
    cbfs Linux payload does not work.
    
    If the cbfs Linux payload is to be used in multiple environments
    should the trampoline needs to take care of the descriptors that Linux
    requires.
    
    This patch updates the Linux trampoline code to configure the 4G flat
    descriptors that Linux expects.  The configuration is borrowed from
    the descriptor configs in coreboot/src/arch/x86/lib/c_start.S for
    selectors 0x10 and 0x18.
    
    The linux_trampoline code is slightly refractored by defining the
    trampoline entry address, 0x40000, as TRAMPOLINE_ENTRY_LOC.  This
    definition is moved into a separate header file, linux_trampoline.h.
    This header file is now included by both the trampoline assembly
    language code and the trampoline loader C code.
    
    The trampoline assembly language code can now use TRAMPOLINE_ENTRY_LOC
    as scratch space for the sgdt CPU instruction.
    
    Testing Done:
    
    Verified the Linux payload is booted correctly in the following
    environments:
    
    1.  Coreboot -> Linux Payload
    
    2.  Coreboot -> SeaBIOS -> Linux Payload: (previously did not work)
    
    Change-Id: I888f74ff43073a6b7318f6713a8d4ecb804c0162
    Signed-off-by: Curt Brune <curt@cumulusnetworks.com>
    Reviewed-on: http://review.coreboot.org/6796
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 062e408bc77b935798145e29d4031f8105be5086
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Aug 29 20:10:38 2014 +0200

    build: add what-jenkins-does target
    
    This target does (pretty much) exactly the same what jenkins
    is doing on our build nodes:
     - complete abuild run of our tree with a given payload
     - building all libpayload configs we ship
     - building the cbmem utility
    
    In fact at some point we could tell jenkins to just run this command.
    
    For debugging, pass along V and Q variables so inner make processes
    are slightly more noisy on demand.
    
    Change-Id: Ib515170603a151cc3c3b10c743f1468a9875dbdc
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6797
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 230fe0ef2f2e565a1b67ffea946d77c3c24ac0d4
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Sun Aug 31 22:40:57 2014 -0600

    AMD Steppe Eagle: Disable "No Snoop Enable" to stop HDMI audio stutter
    
    Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can
    resolve this issue.  The posted amd_late_init.c northbridge code
    is missing a test for Steppe Eagle northbridges.  See coreboot Gerrit
    change 3934, commit ID 4ca721399c (AMD Olive Hill: Disable
    NoSnoopEnable to fix HDMI audio corruptions with Ubuntu).
    
    Change-Id: I89894d0ce4ad72ea16d61b445edb9e67920bca24
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6822
    Tested-by: build bot (Jenkins)
    Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d13e2c4ab769e526e6b2c0ae568bd84b34688c58
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Sep 17 22:16:04 2013 -0700

    libpayload: usb: Refactor USB enumeration to fix SuperSpeed devices
    
    This patch represents a major overhaul of the USB enumeration code in
    order to make it cleaner and much more robust to weird or malicious
    devices. The main improvement is that it correctly parses the USB
    descriptors even if there are unknown descriptors interspersed within,
    which is perfectly legal and in particular present on all SuperSpeed
    devices (due to the SuperSpeed Endpoint Companion Descriptor).
    
    In addition, it gets rid of the really whacky and special cased
    get_descriptor() function, which would read every descriptor twice
    whether it made sense or not. The new code makes the callers allocate
    descriptor memory and only read stuff twice when it's really necessary
    (i.e. the device and configuration descriptors).
    
    Finally, it also moves some more responsibilities into the
    controller-specific set_address() function in order to make sure things
    are initialized at the same stage for all controllers. In the new model
    it initializes the device entry (which zeroes the endpoint array), sets
    up endpoint 0 (including MPS), sets the device address and finally
    returns the whole usbdev_t structure with that address correctly set.
    
    Note that this should make SuperSpeed devices work, but SuperSpeed hubs
    are a wholly different story and would require a custom hub driver
    (since the hub descriptor and port status formats are different for USB
    3.0 ports, and the whole issue about the same hub showing up as two
    different devices on two different ports might present additional
    challenges). The stack currently just issues a warning and refuses to
    initialize this part of the hub, which means that 3.0 devices connected
    through a 3.0 hub may not work correctly.
    
    Change-Id: Ie0b82dca23b7a750658ccc1a85f9daae5fbc20e1
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170666
    Reviewed-by: Kees Cook <keescook@chromium.org>
    (cherry picked from commit ecec80e062f7efe32a9a17479dcf8cb678a4a98b)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6780
    Tested-by: build bot (Jenkins)

commit e231de2134440eedb00136a5a373480c5d4ec209
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Thu Oct 10 12:52:52 2013 -0700

    drivers/gma: remove unused code
    
    We had brought this code in from the kernel but found it best to
    use mainboard- or chipset specific versions. Firmware should
    strive to be as non-generic as possible.
    
    Change-Id: Ic1ca746cc52c3f9ea4de6895f2b32946229beada
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/172625
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit 7dba0dfd25bf9e367f9e5128b15edb018e958c3a)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6779
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit e00ba2168bf9e61535b83ab4320364fa8e26910c
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Sep 24 20:03:54 2013 -0700

    libpayload: usb: Unify USB speed between XHCI stack and USB core
    
    This patch removes the confusing concept of a special "xhci_speed" with
    a different numeric value from the usual speed used throughout the USB
    core (except for the places directly interacting with the xHC, which are
    explicitly marked). It also moves the MPS0 decoding function into the
    core and moves some definitions around in preparation of later changes
    that will make the stack SuperSpeed-ready. It makes both set_address
    implementations share a constant for the specification-defined
    SetAddress() recovery delay and removes pointless additional delays from
    the non-XHCI version.
    
    Change-Id: I422379d05d4a502b12dae183504e5231add5466a
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170664
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    (cherry picked from commit f160d4439c0d7cea1d2e6b97207935d61dcbb2f2)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6776
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f9d7252a8d869cfda08c872b49d3ce5d7c27b083
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 16 22:50:57 2014 +0200

    lint: simplify board-status check
    
    git can do lots of things by itself, no need to parse
    its output and redo that.
    
    Change-Id: Id2cdd2ea8d34c1ba2b0abddc88e1f3260d74f47d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6798
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit d942ed9aa5bb034c2664d27d09ff7b32ed91fb53
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 30 20:44:37 2014 +0200

    acpigen: Correctly handle root scope
    
    Change-Id: I9b3c9109b01e348259e64e93a4397212216ab152
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6799
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 55ab5ef393c727afaae1e971ae0d7cbff6471203
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Sep 2 02:08:32 2014 +0200

    smbios.c: Fix mismerge which led to laptop being default type
    
    Change-Id: I97ccd08a5e7f094908ed3a85ddae53b158124995
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6823
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ab728eb346b948d9b03fe280e6dcdbb30bc14320
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 00:37:32 2014 +0200

    acpi_tables: Remove roda-specific access to 60f [copy-paste error]
    
    Change-Id: I12ce0dda823d7733c473ed5ef3b0470d95d794ae
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6805
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 9772f8dcacef2ba4d4c91a60160ac181a00f7a87
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 22:12:24 2014 +0200

    google/link: Use common i915_reg.h.
    
    Checked by comparing binaries and seeing no differences other than
    build info.
    
    Change-Id: Ie702c540a18b50d6da0379f7c4e65adf3e4f18d4
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6819
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 68a57d6e608cfdc19e69f17afe13341af4024895
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 21:40:28 2014 +0200

    stout: Kill dead i915 files
    
    Not referenced anywhere.
    
    Change-Id: I6529f2ecbc34a2fa9ca720fea1224670eb98bdcd
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6815
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 23f04e47b81b382dda6348acab562ed6e7f45cca
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 21:58:13 2014 +0200

    lenovo/x60: Remove leftover declaration
    
    Change-Id: I1ab2118a3127dfacef6a389abd59050493e640fb
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6817
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 5eb400f0847b123f09ff520351a093cf0807222e
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Wed Aug 27 03:09:29 2014 -0600

    AMD Steppe Eagle: Update reference to BLOBs repo (3rdparty)
    
    The BLOBs repo has been updated with AMD PI header files, peripheral
    BLOBs for the new Avalon southbridge, the AGESA binary PI BLOB for
    Steppe Eagle, the Steppe Eagle video BIOS, and platform security
    processor firmware.
    
    Change-Id: I8bb58a5cc572d2d75de33b14843d7d1893fff532
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6770
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 598bf954e9050a1bf9cb77e647ca7e9fb44bef44
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Oct 4 11:49:29 2013 -0700

    samus: Change SPD to indicate LPDDR
    
    There is some magic new SPD SDRAM type 241 to indicate LPDDR.
    I cannot find it specificed in any JEDEC document but it is
    what the reference code uses.
    
    Change-Id: I21d7a943784435cb336ecdba7ca5eac0bf5fcd92
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171900
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 0a1385515c62fd1e534b12568df8aaf2170e06f4)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6777
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 49ba28339087cb1057fbb12071a0981013a88e55
Author: Julius Werner <jwerner@chromium.org>
Date:   Thu Sep 26 15:13:44 2013 -0700

    libpayload: xhci: Ensure to reset dequeue pointer on stopped endpoints
    
    This patch fixes a bug in the XHCI stack that occurs when a multi-TRB TD
    times out before the last TRB is processed. The driver will correctly
    issue a Stop Endpoint command in that case, but the xHC will still
    preserve the transfer state and just pick up right after that on the
    next doorbell ring. It will then process the leftover TRBs from the old
    TD the next time a transfer is issued. (cf. XHCI 4.6.9)
    
    We fix this by changing the existing xhci_reset_endpoint() calls in
    transfer functions to not only trigger on Halted (2) and Error (4), but
    also on Stopped (3). That function will not actually issue a Reset
    Endpoint command in this case, but it will nuke the whole transfer ring
    and issue a Set TR Dequeue Pointer command, which is sufficient (though
    slightly overkill) to solve our problem.
    
    Change-Id: I3abbe30ff9d4911a8af1f792324e018d427019e8
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170833
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: Kees Cook <keescook@chromium.org>
    (cherry picked from commit f12424af0e29ac12963e8e5a7970fadcc0bb6cee)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6787
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 6eb83f4bf0c6ac88594449f42d606cbb4887615c
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 00:28:47 2014 +0200

    lenovo/x200: Kill access to nonexisting device [copy-paste error]
    
    Change-Id: I1be939e870e8792f5ebb23623fe8f7f119adec36
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6806
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 7e8e313739138910b6d6da3e056a099a4ac72157
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 31 02:12:19 2014 +0200

    iWRainbowG6: Kill unused file
    
    Change-Id: I7b9b91519d87d70405b57920b3f1ab98c50526d1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6810
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 6abb33c7ba5f18ec3e3578cb1f804cbe60e49c49
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Aug 27 23:42:45 2014 +0200

    smbios: reorganise OEM strings handling.
    
    OEM strings should not be handled by mobo code but by common code with strings
    collected from all devices.
    
    Change-Id: Ibde61a1ca79845670bc0df87dc6c67fa868d48a9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6788
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit 8603513540f2d0016546db7e03292d4d70424b00
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Aug 28 01:41:20 2014 +0200

    ec/lenovo/h8: Implement thinkpad-acpi compatible LED function
    
    Change-Id: I9998b0b4a1413ab65f1dbdf59b2f84d331ce9c3d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6790
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 7096a0cb26d859f91b50853fa3ca41efdf100147
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Aug 28 01:31:33 2014 +0200

    ec/lenovo/h8: Rename LED to avoid conflicting with thinkpad-acpi
    
    Change-Id: I9fd7f894d0e611f61e8702e4eacb12d7b81154d8
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6789
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ed74dcd7f055e07f96562b0a866c185f251016ac
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Aug 27 23:22:50 2014 +0200

    lenovo: Read mainboard version from AT24RF08C.
    
    Tablets have different mainboard version than laptop variants.
    
    Change-Id: I77a1e2b50d30dcf3fa064e0c378ceca7ccf96e89
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6785
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit fc10c342661a8825af200a92822ea50ea636eed0
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Aug 25 22:58:11 2014 +0200

    lenovo/h8: Support tablet events
    
    _QXX numbers are determined experimentally, hotkey scancodes from thinkpad-acpi
    module.
    
    Change-Id: I1f7548ef62529ae25dcdcbed0fc74390b7529a2e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6765
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 5888d86868678469b3dbef6e2447afc2d2386249
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Fri Aug 15 12:15:33 2014 -0600

    AMD Steppe Eagle: CPU files for new SoC
    
    Add the CPU files required to support the Steppe Eagle and Mullins
    models of Family 16h SoC processors from AMD.  This CPU is based on
    the Jaguar core and is similar to Kabini.
    
    Change-Id: Ib48a3f03128f99a1242fe8c157e0e98feb53b1ea
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6679
    Tested-by: build bot (Jenkins)
    Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>

commit 27ed80bce1da2d17fecd342a8150f790939150a1
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Fri Aug 15 11:46:25 2014 -0600

    AMD Steppe Eagle: Add northbridge files for new SoC family
    
    Add the northbridge file for AMD's new Mullins and Steppe Eagle
    processor family.  Since the processor family name is not the
    same across AMD's sales and marketing channels, I have elected
    to use part of the processor ID as the family name.  The intent
    is to reduce confusion since the processor ID is the same for
    both families.  This northbridge support has only been validated
    on the AMD Embedded variants ("Steppe Eagle").
    
    The AGESA wrappers in coreboot have a function that is intended to
    mirror the UMA memory allocation performed during memory initialization
    by AGESA.  Update the Steppe Eagle memory allocation to mimic the
    memory reservation done inside the AGESA BLOB.
    
    Change the default CBMEM address, the default video BIOS device ID,
    and a couple of other defaults to match changes in coreboot community
    code.
    
    The northbridge chip.h specifies how many processor sockets, how
    many channels, and how many DIMM slots are supported by the
    northbridge.  Steppe Eagle does not permit multisocket systems
    and has only one memory controller channel.
    
    Change-Id: I20d8b78e3b153cda2dd05100fbb75e2ebadd9e08
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6678
    Tested-by: build bot (Jenkins)
    Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>

commit 1a59039c24cfe5c74a805064d3a360709ad16526
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Sun Aug 10 17:09:15 2014 -0600

    AMD Steppe Eagle: New integrated southbridge (Avalon)
    
    00730F01 contains the Avalon southbridge and a Platform Security
    Processor (PSP). Supporting the PSP requires specific binaries to
    be included in the ROM.  The fletcher utility is used to sign PSP
    binaries.
    
    The IMC access routines are not accessible for newer AMD parts that
    use pre-compiled AGESA.  Change the Hudson code such that the IMC
    code is not compiled if IMC is not selected in Kconfig.
    
    Disable compilation of resume.c if HAVE_ACPI_RESUME is disabled.
    The newer AMD mainboards will initially be released without ACPI
    resume support (S3) due to the use of AGESA internals in the
    existing Hudson routines.  The Makefile change allows newer
    mainboards to avoid the API issues.
    
    Change Kconfig such that the FWM flag is always set for PSP-enabled
    parts.  This has the side effect of forcing the generation of the
    FWM directory in the absence of GEC, IMC, and xHCI.
    
    Change-Id: I6d056f54b60a64300841599490b9fafd561c4a7d
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6677
    Tested-by: build bot (Jenkins)
    Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>

commit b266c6b5448b17647946eb926b07920c28524a55
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Sun Aug 10 23:56:45 2014 -0600

    AMD Steppe Eagle: Add binary PI vendorcode files
    
    Add all of the PI source that will remain part of coreboot to
    build with a binary AGESA PI BLOB.  This includes the gcc
    makefiles, some Kconfig, and the AGESA standard library
    functions.
    
    Change vendorcode Makefile and Kconfig so that they can compile
    AMD library files and use headers from outside the coreboot/src
    tree.
    
    The AGESA dispatcher is built using its own rules rather than
    generic library generation rules in coreboot/Makefile and
    coreboot/Makefile.inc.  The AGESA source files are initially
    copied from whereever they live into coreboot/build/agesa.
    They are compiled from there.  The binary PI directory has a
    mandatory structure that places the AGESA BLOB into the same
    directory as the support headers.  These will nominally be
    placed in the 3rdparty directory in coreboot.org.
    
    The copy commands that were added to the the vendorcode
    Makefile.inc ensure that only one thread will operate on each
    source file by using a macro to generate the copy targets.
    After the change, each copy target will operate on exactly one
    source file.
    
    Due to API issues, coreboot has no way to control the IMC to set up
    fan control.  Set a Kconfig flag that removes the ability to install
    an IMC BLOB into CBFS.
    
    Change-Id: I050b72a19086aaeba6cb65ce165297b10e3cfc45
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6595
    Tested-by: build bot (Jenkins)
    Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>

commit 94930e2622abe5b9e917f32c459041123ce2d273
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 24 22:40:33 2014 +0200

    lenovo/x220: New port
    
    Change-Id: Ic213948e4d31457dda9b9f2d5a4f92cd34d1e57d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6757
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 309fc4ce8bad334b88fc653a35baa4f0c5b67fd2
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 24 22:35:29 2014 +0200

    sandybridge: Add native sandybridge
    
    Change-Id: I1b51310b4387e588c4828563620b0e2770598503
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6753
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 3a2310e05c971e3b46e9e91886bbc467ae49cdb6
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Wed Jul 16 11:25:21 2014 -0600

    AMD Steppe Eagle: Add 32-bit Fletcher's Checksum computation
    
    The AMD Platform Security Processor (PSP) requires a Fletcher's
    Checksum at the end of the PSP directory.  This code implements
    a Fletcher's Checksum by reading bytes from stdin and writes the
    bytes back to stdout with a checksum inserted into the byte stream
    at the appropriate offset.
    
    This utility is used on PSP binaries during coreboot build.
    
    Include a runtime debug option such that the command:
    
    	fletcher --print <file.bin >file_with_cksum.bin
    
    will print out the computed checksum value for debugging.  The
    compile-time debug option is retained that allows -DDEBUG to
    be added to the compilation line.  This option has the same
    effect as "--print".
    
    Change-Id: I506a479d8204ca4f8267d53aa152ac4b473dbc75
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6676
    Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>

commit 71c0bf6202bee2c17b3e64b377038207f6018dc6
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Aug 27 23:23:14 2014 +0200

    smbios: Define and use enclosure types.
    
    Change-Id: Ib5b92120cbe2ca41c9813e8caeb03161f4d3954c
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6786
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit 04e6f070aa58338a8ac7852172f75914baab5382
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Oct 4 11:54:54 2013 -0700

    samus: Add ACPI MADT interrupt override for GPIO IRQ 14
    
    This interrupt needs to be specified in the MADT before it can
    be used by the kernel driver.
    
    Change-Id: Ic920a792a203cb06cd4529815680584a21532106
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171902
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit a330fddb62cb6346ad66ceb5b5c32b66aecd81e2)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6778
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ddc3e42c2267fe175dcc28e38f53f0adecf1aa4e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 2 16:10:54 2013 -0700

    samus: Add coreboot board
    
    Add the coreboot board files for samus
    - Based on Bolt
    - GPIO setup based on 0.91 schematic
    - Support both memory types
    - No HDA verb table for this platform
    - Some GPIO interrupts are shared and need to be passed to OS
    
    Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171694
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6775
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ca436cb247a78b234feb7975575883bdcbabc348
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Sep 29 07:06:08 2013 -0700

    tegra124: add custom uart
    
    tegra124: Add a test function which spams exclamation points on the UART.
    
    This function spews characters on the console and, until we have a working
    console, is an easy way to see whether the system boots to a particular point.
    For some reason waiting for transmitter to be empty hangs, but transmitting
    characters still works.
    
    Old-Change-Id: I1622c8a58849f4b8bdcaa67500b81042d7346df4
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171030
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit e0059181958cfe8afec2f3a7ea732e81f5d55e5d)
    
    tegra124: Re-enable waiting for the transmitter to empty in the test function.
    
    The compiler was emitting code compatible with armv7-a, but the bootblock was
    running on a core which uses armv4t. By coincidence, it was emitting an
    instruction which is unavailable on armv4t when checking the value of the
    UART's LSR register. Now that the bootblock is compiled with more appropriate
    flags, this code can be re-introduced.
    
    Old-Change-Id: I7ecada4138b0889b963d1a8b19a4bab8e0bb1add
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/170997
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 2a0adceb5029c8ee633d17c82dbb11e48d30349d)
    
    tegra124: Seperate out the non-UART specific hardcoded init in the bootblock.
    
    The hardcoded init in the test function in the bootblock is actually useful
    generally because it doesn't belong in the UART driver itself but is necessary
    for the UART to work. Until we have real implementations for the pinmux, etc.,
    we can use that code to get the UART and console going.
    
    Old-Change-Id: I2efe0b571d8b022eb2a2e5569620558540b28373
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171334
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit ae7d4d890be1936cc86dc15adeb33f3b46a51ae5)
    
    tegra124: Implement and enable serial console support for tegra124.
    
    The driver is very similar to the 8250 driver, except it isn't in two parts,
    and it also spaces its registers 4 bytes apart instead of having them directly
    adjacent to each other.
    
    Also, eliminate the UART test function in the bootblock. It's no longer needed
    since the actual console output serves the same purpose.
    
    Right now the clock divisor is fixed for now, and we'll want to actually
    figure out what value to use at some point.
    
    Old-Change-Id: Idd659222901eb76b0ed8cbb986deb5124096f2f6
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171337
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 86f5e2875b18901b349283cfbcd4f8cc88b7a019)
    
    Squashed 4 commits related to uart support for tegra124. Modified the
    new uart.c to look like the uart.c for exynos5420.
    
    Change-Id: I490cba014a43d58c30c48ca9ddcae2b00095b7a6
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6764
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit d81f409514b99189c943d06fa9a8fa01d8178fc8
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Oct 8 23:16:51 2013 -0700

    exynos: Fix the name of the chip_operations structures.
    
    The exynos directories had been moved from src/cpu to src/soc, but the name
    of the chip_operations structure wasn't updated properly. That meant that the
    SOCs never installed their memory resources and the ram stage would fail to
    load the payload.
    
    Change-Id: Ib60489b6d3434e3ebd13827a804452f762747f1b
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/172400
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 9100d475ebcc4dae23184583a6cc0162577e70d1)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6781
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f09f2247d7584975d17a7d4755b279c1c3f6f001
Author: Julius Werner <jwerner@chromium.org>
Date:   Wed Aug 28 14:43:14 2013 -0700

    arm: libpayload: Make cache invalidation take pointers instead of integers
    
    This minor refactoring patch changes the signature of all limited cache
    invalidation functions in coreboot and libpayload from unsigned long to
    void * for the address argument, since that's really what you have in
    95% of the cases and I think it's ugly to have casting boilerplate all
    over the place.
    
    Change-Id: Ic9d3b2ea70b6aa8aea6647adae43ee2183b4e065
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/167338
    (cherry picked from commit d550bec944736dfa29fcf109e30f17a94af03576)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6623
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7d7eeddbbdc3f39f351cf091bc1f920cf4799c85
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Aug 15 07:28:44 2014 +0200

    soc/intel/baytrail/Kconfig: Remove empty line at top file
    
    Change-Id: I932e4566ec6313a7f2dbd58784bde71bca12abd7
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6671
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit acfe1e5966ad2ea69c373ea613ec492007ac0129
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Wed Aug 27 13:21:43 2014 +0200

    qemu: log acpi table size
    
    Change-Id: Ib2d7a3d9bda94f80886da96c2b766d29fc15a834
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/6772
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2177f1bcb5420a69957e7146c1b77e8f4c4d8aa8
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Wed Aug 27 11:23:35 2014 +0200

    qemu: fix cirrus build
    
    commit 9518b56 (intel/gma: Clarify code and use dedicated init for
    Google Peppy) changed "struct edid" and thereby broke the build.
    Adapt drivers/emulation/qemu/bochs.c to the changes to fix this.
    
    Build failure triggers with CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y.
    
    Change-Id: I2d3cecde21d495e9b99ff8d2f741f8a462c75a4d
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/6771
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4f62732858ef5d332c6f646c3302b5e7c0f5e436
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Wed Aug 27 10:42:47 2014 +0200

    qemu: fix bochs build
    
    commit 9518b56 (intel/gma: Clarify code and use dedicated init for
    Google Peppy) changed "struct edid" and thereby broke the build.
    Adapt drivers/emulation/qemu/bochs.c to the changes to fix this.
    
    Build failure triggers with CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y.
    
    Change-Id: Ic295c6d31284555e1463af5bca673231b8722d54
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/6769
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9135cb4542dd0e11bb672a438bd18e673e58a323
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Sep 26 16:13:08 2013 -0700

    libpayload: Change CONFIG_X86_SERIAL_CONSOLE to CONFIG_8250_SERIAL_CONSOLE
    
    While the 8250 compatible serial port driver is primarily useful on x86
    systems because it works with the legacy x86 com ports, some devices which
    aren't x86 based have 8250 compatible UARTs as well. This change renames the
    CONFIG_X86_SERIAL_CONSOLE option to the more general and direct
    CONFIG_8250_SERIAL_CONSOLE and fixes up the dependencies so that non-x86
    systems can enable the driver, although it will default to on on x86 and off
    otherwise.
    
    Also, the default IO port address that's added to the sysinfo structure on x86
    and which is intended to be overwritten by a value in the coreboot tables is
    not used on ARM. That variable is adjusted so that it's more clear it's a
    default value, and made dependent on x86 since that's the only place its value
    is actually used.
    
    Change-Id: Ifeaade0e7bd76d382426e947275a9c933da4930e
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/170834
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 9a10e39a2da3cb0bfb316c0869cf5025078e287f)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6655
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 7f0747562ed43b8461aae6960f2615d2b84b6387
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Sep 29 06:32:27 2013 -0700

    tegra124: Add a custom bootblock implementation.
    
    This implementation is the same as the general one except that it removes all
    the things that don't work on an ARMv4.
    
    Change-Id: I1108a79cc656b26f7d48df20aef3016cf5ae3182
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171019
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit d1436288d3b025af27a8d28ba94b589940ead504)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6713
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a2a87d4bca39bdb2e0ffda88e50cab0a98a09621
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Sep 29 05:40:13 2013 -0700

    ARM: Make it possible to use a custom bootblock implementation.
    
    Tegra needs to use a custom bootblock implementation because it starts on a
    coprocessor which uses ARMv4. It doesn't have the same control registers,
    caches, etc., and the regular bootblock gets exceptions and dies.
    
    Change-Id: Id197db2939bc840ad64244d6e2017fc5c89e0cbd
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171018
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit a66393fdd6fe68757e394b8a611e610f1938771d)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6710
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Furquan Shaikh <furquan@google.com>

commit 74fade43ee6563505b29484ac5cf8c860a766650
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Oct 1 10:46:35 2013 -0700

    Peppy/Haswell: move more support functions from mainboard to the intel i915 driver
    
    Move (and rename to make it clearer) the function that computes display
    parameters from the dpcd and edid.
    
    Change-Id: Idfbb56fd312b23c742c52abca1a34ae117a8fece
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171366
    Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    (cherry picked from commit 8f2b3bafee7cb05db8fae1c52fc9e1ee64e5e35d)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6768
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit d7c25b357fb26c0bd9e7844e32529c90e994f4a3
Author: Julius Werner <jwerner@chromium.org>
Date:   Wed Sep 4 17:20:32 2013 -0700

    libpayload: usb: Allow direct instantiation of MMIO host controllers
    
    The existing USB_MEMORY mechanism to instantiate non-PCI host
    controllers is clunky and inflexible... most importantly, it doesn't
    allow multiple host controllers of the same kind. This patch replaces it
    with a function that allows payloads to directly instantiate as many
    host controllers of whatever type they need.
    
    Change-Id: Ic21d2016a4ef92c67fa420bdc0f0d8a6508b69e5
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/169454
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit b6e95c39dd91f654f0a345f17b3196f56adf4891)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6644
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fbcc8ceca13c92f0c885c8d760735412d33b99ba
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Dec 21 21:39:37 2013 +0100

    libpayload: Add ARM defconfig
    
    make junit.xml tries to build it, but fails
    (ARM port doesn't seem to be ready?)
    Useful test case to demonstrate a failing
    libpayload build.
    
    Change-Id: Iba4fe551b48f631e6a3bd90eb07930fc70761332
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4552
    Tested-by: build bot (Jenkins)
    Reviewed-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 518a322d5880a4dd29a943ec474484cd8b48876f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Aug 26 13:52:30 2014 -0500

    rmodtool: correct final memory size calculation
    
    Apparently when I originally wrote this I confused myself to no end.
    The code/data of an rmodule has a set memory size which is associated
    with the .payload section. The relocation entries may increase the
    overall footprint of the memory size if the rmodule has no bss but
    a lot of relocations. Therefore, just compare relocation entries size
    plus the file size of the .payload section with the memory size of the
    paylod section. The .empty section is added only when we have not met
    the final target size.
    
    Change-Id: I5521dff048ae64a9b6e3c8f84a390eba37c7d0f5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6767
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan@google.com>

commit 22d0ca0ceb802675cdcab1472b8477066f729373
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Sep 27 12:45:45 2013 +0800

    armv7: Move Exynos from 'cpu' to 'soc'.
    
    The Exynos family and most ARM products are SoC, not just CPU.
    
    We used to put ARM code in src/cpu to avoid polluting the code base for what was
    essentially an experiment at the time. Now that it's past the experimental phase
    and we're going to see more SoCs (including intel/baytrail) in coreboot.
    
    Change-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c
    Reviewed-on: https://chromium-review.googlesource.com/170891
    Tested-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Hung-Te Lin <hungte@chromium.org>
    (cherry picked from commit c8bb8fe0b20be37465f93c738d80e7e43033670a)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6739
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b123e0d3345554d7e93361bb4511a53bc95d41a1
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Mon Aug 25 23:59:42 2014 +0200

    util/inteltool: fix typo
    
    Change-Id: I8c30742f6cd759dce4c9641edad107d9e3154975
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/6766
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 4c8465cfac3a5b4bdc61e0f2f0bfb0b346b03ad2
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Mon Sep 30 15:57:21 2013 -0700

    Peppy, Haswell: refactor and create set_translation_table function in haswell/gma.c
    
    The code to set the graphics translation table has been in the
    mainboards, but should be in the northbridge support code.
    
    Move the function, give it a better name, and enable support for > 4
    GiB while we're at it, in the remote possibility that we get some 8
    GiB haswell boards.
    
    Change-Id: I72b4a0a88e53435e00d9b5e945479a51bd205130
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171160
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    (cherry picked from commit d5a429498147c479eb51477927e146de809effce)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6741
    Tested-by: build bot (Jenkins)

commit 8414d3c0b407d9afc6a2446dba3ca358da2c7bb6
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 10 12:44:11 2013 -0500

    xcompile: always use -march=i686
    
    When compiling coreboot for x86 on gcc the compiler is
    free to pick whatever defaults it is using at the time of
    gcc's compile/configuration when no -march is specified.
    Not properly specifying -march then opens up the use of SSE
    instructions for compilation units it should not be used such
    as the SMM module as this module doesn't save/restore SSE
    registers.
    
    Change-Id: I64d4a6c5fa9fadb4b35bc7097458e992a094dcba
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172640
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit d49358f7959bb52c3e7ff67d37c21a1b294adf72)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6716
    Tested-by: build bot (Jenkins)

commit 9518b56ab079f4c12eefe83cc9b4fa24b413ebe8
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 19 16:45:22 2013 -0700

    intel/gma: Clarify code and use dedicated init for Google Peppy
    
    Peppy had some issues with FUI. We decided it was time to create
    peppy-specific gma.c and i915io.c files. Using yabel and the i915tool,
    we generated a replay attack, then interpolated against the slippy
    i915io.c to get something working.
    
    Also, in preparation for moving code out of the mainboard gma.c to
    generic driver code, we got rid of some hardcodes in the mainboard
    gma.c that have no business being there. The worst were the
    computation of gmch_[m,n] and it turns out that we had some
    long-standing bugs related to confusion about 'bpp'. I've killed the
    word bpp everywhere I could because there are at least 3 things that
    correspond to bpp. We now have framebuffer, pipe, and panel bpp. The
    names are long because I want to avoid all the mistakes we've all been
    making in the last year :-) Sadly, that means a lot of changes not just
    peppy-related, but they are simple and in a good cause.
    
    The test pattern generation is driven by a global variable in
    mainboard/peppy/gma.c.  I've found in the past that it's very useful
    to have a function like this available, as one can activate it while
    using a jtag debugger: halt at the right place in ramstage, set the
    variable to 1, continue. It's not enough code to worry about always
    including.
    
    The last hard-codes for M and N registers are gone, and the function
    to set from generic intel_dp.c code works.  To avoid screen trash on a
    dev mode boot, which we liked but nobody else did :-), we now take the
    time to put a pleasing background color that sort of doubles as a
    power LED.
    
    Rough timing is ramstage start is at 2.2, and dev setup is done at
    3.3. These new platforms are depressingly slow to boot. Rom init alone
    is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash
    prompt. These CPUs are at least 10x faster and take much longer to get going.
    
    Future work, once we get this through, is to move more functions to the
    intel driver, and combine the mainboard i915io.c into the mainboard gma.c.
    That separation only existed because i915io.c was generated by a tool, and it
    had lots of ugliness. Most ugliness is gone.
    
    Old-Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: https://chromium-review.googlesource.com/170013
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
    (cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d)
    
    snow: Fix a typo in devicetree.cb that was breaking the snow build.
    
    A typo in a recent change broke the snow build.
    
    Old-Change-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171014
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 154876c126a6690930141df178485658533096d2)
    
    Squashed a fix into the initial patch and updated nehalem/gma.c
    to have a non-static gtt_poll.
    
    Change-Id: I2f4342c610d87335411da1d6d405171dc80c1f14
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6657
    Tested-by: build bot (Jenkins)

commit 58a67db092ad4742fa68699a8e56cfc7f39f7128
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 24 22:36:35 2014 +0200

    sandybridge: Show spew raminit messages only with raminit debug
    
    Change-Id: Ifbc59c28c8d8bd844801da9cb869c5dfbda09168
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6754
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2703b0bf5ae320fb3a9fb85218443b34fc52789d
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Fri Aug 15 12:25:28 2014 -0600

    AMD Steppe Eagle: Add northbridge HT link ID to pci_ids.h
    
    Add a #define for the HT northbridge link ID into the "known PCI
    device IDs" table.
    
    Change-Id: If0a32b2af5df6c20e0fb5af200c06d80fab3637a
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6680
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 77ffa0d3ad7686a9e697bf1fa05966f019249483
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Sep 30 21:25:49 2013 -0700

    UART 8250: Unconditionally provide register constants and use UART8250 prefix.
    
    The register indexes and bitfield masks were guarded by the UART8250 config
    options, but it might be (is) necessary to use them in a driver that is
    UART8250 like without actually using the 8250 driver itself. To avoid any name
    collision with other drivers, also change the constant prefix from UART_ to
    UART8250_.
    
    Change-Id: Ie606d9e0329132961c3004688176204a829569dc
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171336
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit a93900be8d8a8260db49e30737608f9161fbf249)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6715
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 3905e3d47c773e2c9664f09b7209711764683da6
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Aug 29 16:01:05 2013 -0700

    delay: Have mdelay() / delay() available in romstage, too
    
    Some drivers (like the I2C TPM driver) call mdelay instead of
    udelay. While it's a shame that these chips are so slow, the
    overhead of having those functions available in romstage is
    minimal.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I1fa888fc5ca4489def16ac92e2f8260ccc26d792
    Reviewed-on: https://chromium-review.googlesource.com/167542
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit 7083b6b843d803bd4ddbd8a5aaf9c5c05bad2044)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6531
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 69e66d10deba392341a9d389fbf8d29987a6b424
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Sun Aug 24 22:12:37 2014 +0200

    lenovo/t520: update Kconfig
    
    override default ivy VGA_BIOS_ID
    add model & part number
    Remove ARCH_X86 as is in,
      fd33781 Move ARCH_* from board/Kconfig to cpu or soc Kconfig.
    
    Change-Id: I61dc6434de7af2d8672f784df87a8b9d3f0fb068
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/6759
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit a41e5c7dc53b8849172dd357cf9f500cac19a897
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Sun Aug 24 19:49:35 2014 +0200

    lenovo/t520: fix PCIe interrupt and function disable config
    
    Change-Id: I33e71c0a246583885368dc3d3af761c190b2fb5c
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/6758
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 1065cc9a2568831d6c4ca415a45296f98024045a
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Sun Aug 24 22:14:29 2014 +0200

    lenovo/t5x0: replace invalid config DRAM_GATE_GPIO
    
    Change-Id: I3b13bddfc127353e0c13d8d2ae7918d5c3deb72c
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/6760
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 96555bf4deee042c89bb28dac79303bc28b41686
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 24 22:38:56 2014 +0200

    lenovo/x230: Add subsystem ids.
    
    Change-Id: I917a89da50d8efe998c368ba46206f2a1c580fd0
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6756
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 7cf3d226e225bdea9d9cf8f2c85ede64710e06b5
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Aug 1 20:30:21 2014 +1000

    lenovo/t530: Be safe by disabling blink gpio hw with a writeout
    
    This disables the blink hardware as it seems to be in the dump. This is
    safer as it does not rely on 0 as the reset value when '0x00040000' is
    the default according to the util/inteltool. As seen:
    
    gpiobase+0x0018: 0x00040000 (GPO_BLINK) DIFF
    
    Change-Id: Ia1fde108bf3752484f5e991600c435f776af0ced
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6436
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 9ba922f8bda1e4a7e201fadca2b0f1c38f89f4e0
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 24 22:38:07 2014 +0200

    sandybridge: Native gfx init.
    
    Change-Id: I07590086ffe3b1d068fa6ae6b156039cc2e55893
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6755
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9f2dae4ec0a420ef76a3672dbda29d104b9da4ff
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Aug 1 20:29:40 2014 +1000

    lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header
    
    Use defines of offsets rather than hard coded values.
    
    Change-Id: Id2471cd22aa402d74163473e48f86af9789cdaa7
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6435
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit a51064eb1a7eb04accbc371f37fd80ea851ab7e4
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Aug 23 14:25:30 2014 +1000

    lenovo/t530/romstage.c: Trivial - move include to top
    
    Change-Id: I6b80ad0da39e93072e28b48c40e1c71602133e7b
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6750
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 35d5ea97f6b1360ed36acdf0a0a5e608e3682a5c
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Fri Aug 22 16:47:07 2014 +0200

    lenovo/t520: replace dumped GPIO values with gpio.h
    
    GPIO pin wireing information from schematic
    
    Change-Id: I2d8dca151b6fbc15e0184ea07596039570843cda
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/6740
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 6ccc3465c3488411e6e743bb9a2822ac5902b6df
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Sat Aug 23 01:06:33 2014 +0200

    lenovo/t520: fix devicetree
    
    SATA Port documentation
    PCIe unused ports and documentation
    T520 have no keyboard backlight
    
    Change-Id: I517ff8519ea22a9a7a9b6e3136efd15d4a0f8fc4
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/6743
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 23aad4a83c3390dc39f7d1c1f5422f7ac54a80f3
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Sat Aug 23 00:51:49 2014 +0200

    lenovo/t520: fix usb config & documentation
    
    Change-Id: I71398ab2d7ef5b9256795861dd2bebbb0cf32d5f
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/6742
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit e4340b52ced8bddc796d15cce4c1a154c98dcabd
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Aug 15 15:58:36 2014 +0200

    ec/lenovo/h8/acpi/systemstatus.asl: Fix typo in o*n* in comment
    
    Change-Id: I655536f64faaa7e1600d4fec62ba80730e2cc45a
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6674
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit becf739b2ea49529d4c161804fe4d469b4e4ff6c
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Fri Aug 22 15:22:20 2014 +0200

    lenovo/t520: Remove empty smi.h
    
    Change-Id: I60fa19b72f91f16db5f354aeec631f661e3494d3
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/6736
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 6d790f730500ce6a79aeb9e4d57b0ea4c9e9ee69
Author: Nicolas Reinecke <nr@das-labor.org>
Date:   Fri Aug 22 15:10:49 2014 +0200

    lenovo/t520: Fix ExpressCard hotplug
    
    Thinkpad T520 ExpressCard Slot PCIe lanes are connected to port 4.
    Tested with Serial Port Card. Information read from schematic / lspci
    
    Change-Id: I459943d427578d135f9aed1aa66da269ddfeee87
    Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
    Reviewed-on: http://review.coreboot.org/6735
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit d2da65e3abd93840c81fbc30c6488b625baf359b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Aug 6 21:32:50 2014 +1000

    superio/smsc/sch4037: Cleanup and fix .c inclusion
    
    Clean up both ram and rom stage support and fix board to match.
    
    Change-Id: I55e3e7338c0551f0fb663eb9707f16ecdc1aca35
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6509
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 47b8075bb14de4dad4cfd2c2f42482e04644b28d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Aug 2 20:08:35 2014 +1000

    superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
    
    Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE
    as argument instead of hard coding and playing funny business with the
    pre-processor. Fix board to match.
    
    Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6463
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 8b685398a74065d832fe2a3dfcfb313f0f4f11c3
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Sep 29 03:02:55 2013 -0700

    ARM: Overhaul the ARM Makefile.
    
    The ARM Makefile was copied from x86 and then modified, and as a result it
    was carrying a lot of baggage. On top of that, the extra complication made it
    inflexible, and we need a lot of flexiblity in order to support the fact that
    the Tegra124 starts on an ARMv4 coprocessor instead of one of the ARMv7 main
    CPUs.
    
    Change-Id: Ia6ddc27619bdb51e152ad0c628ad6f3037c103ce
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171017
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 512d942788336c8d52470135b43ee4e6a1c95f6c)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6709
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit bc349b81e97350b13d7d70c400e46d0bb8e4d1aa
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Aug 22 14:05:00 2014 -0500

    elfheaders: fix 64-bit ELF writing
    
    The sh_flags for a 64-bit section header entry are
    64-bit in size. Correct this.
    
    Change-Id: I2fa79d9a0fb46cc1dfa97c172357bbd2394843e0
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6737
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan@google.com>

commit f99a62b65e0b2571a815f987144dc9c5db606444
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Aug 21 22:30:09 2014 +0200

    Remove dead video.asl
    
    Change-Id: Iadaa6172347ebb7d367d1faa6ed9462fff07d7e6
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6730
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 075422704437b893849f0a39d86130227e75f913
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Aug 21 21:15:54 2014 +0200

    lenovo/{x230,t530}: Remove empty smi.h
    
    Change-Id: I26fa6508f50faff7f1c1724884b5ffa30463b896
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6728
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit bcf58a44d19a213069ac404b15be792ac58e0c15
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Aug 21 21:14:31 2014 +0200

    lenovo/x230: Remove empty mainboard.asl
    
    Change-Id: Ic877d6285ce3983268b16ddb5b4e15743f5adf86
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6727
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit caf1d2c0f1353d5a52f45638fd058a5211892e23
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Aug 21 21:13:46 2014 +0200

    lenovo/x200: Remove empty mainboard.asl
    
    Change-Id: I560d693d0d72ca8dcd099eff6b0c40716fb0c0b0
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6726
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit bb1699ecbc867ebe3c592384bdb5233db9281695
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Aug 21 22:19:48 2014 +0200

    lenovo/x200: Move video ASL code to northbridge.
    
    Change-Id: I58760500252e78da947685c18201b6d446368333
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6729
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f3c472feedf416b8c9576536fe391ab62ab5263f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Aug 21 20:20:27 2014 +0200

    lenovo/x201: Remove empty mainboard.asl
    
    Change-Id: I37d48279b1b022c4573bd09d3db6bf536d5dab9a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6724
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit af906fd0646f275c66e981a3f162a494ff7e2314
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Aug 22 03:08:41 2014 +0200

    apple/macbook21: Remove useless seabios config
    
    Change-Id: If771a84f25710e1fb2228816e3ca0139e2f95aa7
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6732
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 251cbd837192aef656762186cb35da70eb45a848
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jul 29 20:52:17 2014 +1000

    lenovo/t530/mainboard.c: Add EC info to SMBIOS
    
    As is in:
    91175bb lenovo/x201 & x230: Add EC info to SMBIOS
    
    This is needed for the Linux driver for the Lenovo's to properly attach.
    
    Change-Id: Ib910b25f392d9d3d6362b6909ce9fd4eeae9a096
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6399
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 91b1f0b712f5419c8f66de1886a5abd15d1604ad
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Aug 20 22:39:21 2014 +0200

    Merge LCD on nehalem
    
    Change-Id: I09852ea56495da17e7607064d74d98f2296f34b1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6721
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 91337fd8da2e672438fe5e01b64207ccd8b44b36
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Aug 20 22:46:14 2014 +0200

    Merge LCD on sandy/ivy
    
    Change-Id: Ibf66d46f47fe465cc805f85de818a77327cd7258
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6722
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 0092c999c75ad7db4a43ae30dd815c2734b71c36
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Aug 21 01:06:53 2014 +0200

    i945: Support text mode gfx init
    
    Change-Id: I952fdb113e2696785695b416d9292b7107099994
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6723
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 055fe037954c3c7acefc7e59b7d568b400560878
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Aug 19 23:59:27 2014 +0200

    i945/gma: don't map the page table
    
    Change-Id: I20fb5323cde1f83a3d3adc98251b2f31de25ed24
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6718
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit a60fb4d2dbd7748a92c5811f22e62575b1640998
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Aug 19 22:49:50 2014 +0200

    i945: Remove GTT avoidance offset.
    
    Not needed anymore with GTT at the end of range.
    
    Change-Id: I57b02c7d605d3c43ac92bd744bb6472e3c3471e2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6717
    Tested-by: build bot (Jenkins)
    Reviewed-by: Francis Rowe <info@gluglug.org.uk>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4f3873d2cec66d1b72577e3c516287f356af3f23
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Sep 26 23:21:57 2013 -0700

    arm: Get rid of the INTERMEDIATE variable used on exynos.
    
    The INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for
    Exynos SOCs, but we can do that directly without having a special hook.
    
    Change-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/170921
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 8db03c387ad654227d064e2a7fa5ecf09d07e3c5)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6714
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit cc95f189731907dc5847cd62b398217e6f9f91f0
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Jun 5 22:45:35 2014 +0200

    intel/i945/gma: Place GTT below top of memory
    
    Since commit 17fec8a0 [1]
    
    	drm/i915: Use Graphics Base of Stolen Memory on all gen3+
    
    present in the Linux kernel since version 3.12, 3D does not work
    anymore [2].
    
    Comparing the graphics registers, in this case that means output of
    `intel_reg_dumper`, the vendor Video BIOS is setting the register
    PGTBL_CTL/PGETBL_CTL, only documented in the i965 datasheet [3], to
    `0x3ffc0001` on a system with 1 GB of RAM, while native graphics init
    sets it to `0x3f800001`.
    
    Currently native graphis init sets the GTT right above the base
    address of stolen memory. The Video BIOS sets it below the top of
    memory.  The Linux Intel driver expects it to be below top of memory, so
    do it this way, by setting the address to TOM minus the size of the GTT,
    which is hardcoded to 256 KiB.
    
    As `PGETBL_CTL` is zero by default, reading its value in the beginning
    is not necessary and is only confusing. Make it clear that the code
    calculates the value.
    
    There is still a PTE error reported during boot, but 3D works
    with Linux 3.12+ and no user visible problems are shown.
    
    [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=17fec8a08698bcab98788e1e89f5b8e7502ababd
    [2] https://bugs.freedesktop.org/show_bug.cgi?id=79038
    [3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_1_graphics_core_0.pdf
        Intel ® 965 Express Chipset Family and
          Intel ® G35 Express Chipset Graphics Controller
          Programmer’s Reference Manual
        Volume 1: Graphics Core
        Revision 1.0a
    
    Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Signed-off-by: Francis Rowe <info@gluglug.org.uk>
    Reviewed-on: http://review.coreboot.org/5927
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit d609e89adf584641202f80ea8dcab824e39cc7e6
Author: Julius Werner <jwerner@chromium.org>
Date:   Wed Sep 25 12:30:07 2013 -0700

    libpayload: usb: Fix several minor USB stack bugs
    
    This patch fixes the following minor bugs in the USB stack:
    
    1. Ensure that all dynamically allocated device structures are cleaned
    on detachment, and that the device address is correctly released again.
    2. Make sure MSC and HID drivers notice missing endpoints and actually
    detach the device in that case (to prevent it from being used).
    3. Make sure XHCI-specific set_address() cleans up all data structures
    on failure.
    4. Fix broken Slot ID range check that prevented XHCI devices from being
    correctly cleaned up.
    
    Change-Id: I7b2b9c8cd6c5e93cb19abcf01425bcd85d2e1f22
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170665
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    (cherry picked from commit 9671472263ddd0c30400ae3b6da780a18cd21ded)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6701
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 14eb43be984cc1f18fd950af9bf162b0104f8458
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Oct 7 01:57:42 2013 -0700

    tegra124: Implement the tegra i2c driver.
    
    This uses the packet mode of the controller since that allows transfering more
    data at a time.
    
    Change-Id: I8329e5f915123cb55464fc28f7df9f9037b0446d
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/172402
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 4444cd626a55c8c2486cda6ac9cfece4e53dd0d3)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6703
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 08d5a89fd0a64740b81d1319551ac580068d835d
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Oct 3 04:35:01 2013 -0700

    tegra124: Implement driver code for the pinmux, pingroup controls, and GPIOs.
    
    The pins on tegra are controlled by three different units, the pinmux, the
    pin group controls, and the GPIO banks. Each of these units controls some
    aspect of the pins, and they layer together and interact in interesting ways.
    
    By default, the GPIOs are configured to pass through the special purpose IO
    that the pinmux is configured to and so can be ignored unless a GPIO is needed.
    The pinmux controls which special purpose signal passes through, along with
    pull ups, downs, and whether the output is tristated. The pingroup controls
    change the parameters of a group of pins which all have to do with a related
    function unit.
    
    The enum which holds constants related to the pinmux is relatively involved
    and may not be entirely complete or correct due to slightly inconsistent,
    incomplete, or missing documentation related to the pinmux. Considerable
    effort has been made to make it as accurate as possible. It includes a
    constant which is the index into the pinmux control registers for that pin,
    what each of the functions supported by that pin are, and which GPIO it
    corresponds to. The GPIO constant is named after the GPIO and is the pinmux
    register index for the pin for that GPIO. That way, when you need to turn on
    a GPIO, you can use that constant along with the pinmux manipulating functions
    to enable its tristate and pull up/down mode in addition to setting up the
    GPIO controls.
    
    Also, while in general I prefer not to use macros or the preprocessor when
    writing C code, in this case the set of constants in the enums was too large
    and cumbersome to manage without them. Since they're being used to construct
    a table in a straightforward way, hopefully their negative aspects will be
    minimized.
    
    In addition to the low level functions in each driver, the GPIO code also
    includes some high level functions to set up input or output GPIOs since that
    will probably be a very common thing to want to do.
    
    Old-Change-Id: I48efa58d1b5520c0367043cef76b6d3a7a18530d
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171806
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 5cd9f17fe0196d13c1e10b8cde0f2d3989b5ae1a)
    
    tegra124: Add base address for the pinmux and pingroup registers.
    
    There weren't any constants for the pinmux or pingroup registers in the
    address map header.
    
    Old-Change-Id: I52b9042c7506cab0bedd7a734f346cc9fe4ac3fe
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/172081
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 79b61016bfd702b0ea5221658305d8bd359f4f62)
    
    Squashed two related commits.
    
    Change-Id: Ifeb6085128bd53f0ef5f82c930eda66a2b59499b
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6702
    Tested-by: build bot (Jenkins)

commit f40785c0c26c481fa19345dd5467045cf52876c5
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Oct 16 23:50:58 2013 -0700

    tegra124: Pick addresses to load the rom and ram stages.
    
    If these aren't set, the rom and ram stages will attempt to load at address
    zero which doesn't work.
    
    Change-Id: I0b9b37d6363e6b208248d8a1af6ebee4db602486
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/173540
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    (cherry picked from commit 6ac5cea39d423bfcf5bbd53c2cc6228ab89f08b2)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6704
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0fa5662886789850fa5e7f51abc9a15c538dc501
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Mon Aug 18 01:57:34 2014 +0200

    asrock/imb-a180/board_info.txt: add flash fields
    
    Change-Id: Ie686d20811f33c620156c149315807343dde7784
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/6700
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 96a400ebc82c95d3b5da9c1c35975ed782f96c4a
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Aug 18 01:12:36 2014 +0200

    macbook21: Support wake on LID
    
    Change-Id: Ifa1045abc761bef05977a8020cf6f18db042ad58
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6699
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Francis Rowe <info@gluglug.org.uk>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 244675d7bc4509c4c7e6a7d3c497bc8d860caec8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Aug 19 00:36:07 2014 +0200

    lenovo/x20[01]: Don't undock on disconnecting of power from dock station
    
    Change-Id: Id55bf259d5af187ba718de7e367395adcfc567b4
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6707
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit c5e040bd238af5a5ded58fc715e464bbd85b275a
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Aug 18 23:54:54 2014 +0200

    lenovo/x201: Fix dock recognition
    
    Change-Id: I8b210786f660e2b2bae0d9ddd594386fd107cbe4
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6706
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f319ae40d702b3012429d09a05633eadd18ea4c2
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Aug 19 00:48:39 2014 +0200

    lenovo/x201: Unpower USB on undocking
    
    Change-Id: I9b496e8ff92ee575d0b780eab0cb45ea05506d30
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6708
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit dc9cfa431e46d6083ebb83fff5be22de7969bb26
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Aug 18 23:52:53 2014 +0200

    lenovo/x200: Dock support
    
    Change-Id: I4e25630ae82e8030a9d6bfccb60844c301b1d635
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6705
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 8128a56c0ec7e147d4ad68e6ba55979e9ead25ae
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Sep 18 05:48:37 2013 -0700

    trustzone: Pull trustzone init out of cpu.c and do it in romstage.
    
    Trustzone needs to be initialized/disabled both on boot and on wake, so it
    needs to be done before ramstage which doesn't run on wake. cpu.c isn't
    compiled into romstage and fixing that causes other problems, so the trustzone
    functions were split out.
    
    Change-Id: I8fc630237ebec1f02a91600f8baf3d4e9ea66d0e
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/169817
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 055ed0e28476123b0bd666109af90baf40aadcee)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6666
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e97b6835f4dcd70ebf23941fb2f56c0d9d1d3e97
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Oct 6 06:13:24 2013 -0700

    tegra: Change how tegra124 and tegra include files from each other.
    
    A problem with including the tegra124 directory directly in the include path
    is that it makes all headers in that directory first level headers available
    everywhere including places that have nothing to do with the SOC, even headers
    which were only intended for local use by tegra124 code. This change modifies
    things a bit to be more like the way the arch headers are chosen. In the
    tegra124 directory, there's an include directory which has an soc subdirectory
    in it. That include directory is added to the include path, making it possible
    to have headers private to the tegra124. When files specific to whatever tegra
    is being built for are needed, you can include <soc/foo.h> and get the version
    specific to that particular soc.
    
    Also, the soc.h header file was overhauled to use enums instead of defines, to
    consistently name things as far as their prefix (the less cryptic TEGRA instead
    of NV_PA) and suffixes like "BASE", and to get rid of values which were
    specific to U-Boot which we don't need. Since the only thing in the file were
    address constants, I also renamed the file addressmap.h. It would be included
    as:
    
    <soc/addressmap.h>
    
    which I think is easy to remember, does what you'd think it does from the
    name, and won't conflict with other header files just minding their own
    business in some other directory.
    
    Change-Id: I6a1be1ba28417b7103ad8584e6ec5024a7ff4e55
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/172080
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 2c554f58f9ee18e151e824f01c03eb3f0e907858)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6659
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b59e8505d841bafb9ffdaf2086f46d62a0e1689a
Author: Julius Werner <jwerner@chromium.org>
Date:   Wed Sep 25 13:54:57 2013 -0700

    libpayload: usbmsc: Remove DETACHED state from MSC device structure
    
    The USB MSC device structure contains a "ready" state that can be either
    "ready", "not ready" or "detached". The last one can only be assigned
    when the device is completely unresponsive and gets forcefully logically
    detached via usb_detach_device(). This call (at least in the current
    version) also calls all destructors and frees the complete usbdev_t
    structure (including the MSC specific part), which unfortunately makes
    storing the "detached" state in that very structure a little pointless.
    
    This patch reduces the "ready" value to a simple boolean and makes sure
    that all detachment cases immediately return from the MSC driver,
    carefully avoiding any use-after-free opportunities.
    
    Change-Id: Iff1c0849f9ce7c95d399bb9a1a0a94469951194d
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170667
    (cherry picked from commit fd4529f37fdd1c93a8b902488ffeef7001b1a05a)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6654
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit f0cd03c142013e0f50705a1c8741c0f02bea43de
Author: Julius Werner <jwerner@chromium.org>
Date:   Thu Sep 19 20:15:45 2013 -0700

    exynos5420: Don't map low addresses that lead nowhere
    
    I just spent half a day (including the time to implement a stack dumper)
    to figure out that I am reading from a NULL pointer. A problem this
    simple should be more easy to catch. Let's mark the address range below
    SRAM as uncached so that the MMU can yell at you right away for being
    the bad programmer you are when you access a NULL pointer.
    
    Change-Id: I4a3a13f75bf21b25732be2ecb69d47503eff1b53
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170112
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    (cherry picked from commit 7316732ea0ccdc0d607bde81dbb38ca9abd29fa9)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6650
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 12b121f3fef61d6a346c2575266a9cb46bb9d31f
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Sep 24 15:51:05 2013 +0800

    arm/exynos: Allow releasing UART retention for resume.
    
    The UART / serial console is put in retention state by kernel during suspend /
    resume path, which caused Coreboot not able to print any messages during resume.
    
    Sending values to the padret_uart_opt inside PMU may release UART, but that may
    also cause unexpected output when kernel is back. However, it's still very
    helpful when we are debugging suspend/resume inside Coreboot.
    
    To get UART message on resume, call wakeup_enable_uart() in boot block or
    romstage (before console_init).
    
    Change-Id: Ib5759cb402c6e018d9dba14fad8b61f6a1b1a265
    Reviewed-on: https://chromium-review.googlesource.com/170440
    Tested-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Hung-Te Lin <hungte@chromium.org>
    (cherry picked from commit 547fbbfe2eeb6da4e161f36be2caf8099f9eac9b)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6649
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 68aef1169239cc5d33fb36f05cd32d7e062b7743
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Sep 3 15:07:31 2013 -0700

    exynos5: Implement support for USB 3.0 DRD PHYs/controllers
    
    This patch adds support for the DesignWare3 USB 3.0 DRD controller and
    PHY to the Exynos5250 and Exynos5420 CPUs. It also adds code to the
    Google Snow and Pit boards to turn these controllers on where
    applicable.
    
    Change-Id: Idcca627363a69f1d65402e1acb9a62b439f077ff
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/169452
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit e9809ae12ef8b8bd6cd61d3f604cb9e4718cf7eb)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6642
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9125d88596181549f9cd7988c6dd748d54b299ee
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Sep 10 10:58:28 2013 -0700

    console: conditionally include console in bootblock
    
    Right now some console specific objects are included
    in the bootblock even if CONFIG_BOOTBLOCK_CONSOLE is
    disabled while others are not. Make all of them conditional
    and also fix a preprocessor misuse in bootblock_simple.c
    and a stray (useless) die() in the Exynos wakeup code that
    made inclusion of those files necessary.
    
    Change-Id: Ia7f9d17654466f199b0e13afbdc9e14c9706530f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/168772
    Reviewed-by: David Hendrix <dhendrix@chromium.org>
    (cherry picked from commit 855da1f07b52898c7edcaffe5baabe9d485bbd83)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6637
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit e71928ca072b5c136f6d62382182b0b213bd063f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Aug 18 00:38:18 2014 +0200

    macbook11: New mainboard (macbook21 clone)
    
    Tested by marcus.
    
    Change-Id: Ifce2018ef49619b36fb07e5345d70c358a0397e4
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6698
    Tested-by: build bot (Jenkins)
    Reviewed-by: Francis Rowe <info@gluglug.org.uk>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 6a3a8ce1a81578d4461c9d4de6d59a3154f6a8a4
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 17 23:48:42 2014 +0200

    azalia: Move shared variable to separate file
    
    Change-Id: Icf46ad1397c67478887c80a627b8f4eb0a67e542
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6695
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit b46f5891d297e2440bf2f0845cb9a45de2575a40
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 17 23:53:14 2014 +0200

    board-info: Output errors to stdout like make lint-stable expects
    
    Change-Id: I7eb2283808cde86c79d6b770a176daee57a7f9f2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6696
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f7a7ec09d871c52bbf7cda016d2f814831de565e
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Aug 11 12:51:38 2014 -0600

    mainboard/intel/mohonpeak: code cleanup
    
    Code cleanup requested in commit 90957f88 -
    "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000"
    
    - Change com2 to COM2 in Kconfig text
    - clean up includes of headers
    - fix whitespace
    
    Change-Id: I828bc4781ee7de95be5546206c5d6033b75293d9
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6607
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 174a891121d5c474446a4fc1471387db454de6cf
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Aug 11 12:37:24 2014 -0600

    southbridge/intel/fsp_rangeley: fix to include irqroute.h twice
    
    This matches what was done on baytrail in commit bfca984b -
    soc/intel/fsp_baytrail: set up for including irqroute.h twice
    
    irq_helper.h intentionally gets included into irqroute.asl twice - once
    for pic mode and once for apic mode.  Since people are used to seeing
    guard statements on the .h files, add the guards to irqroute.h and add
    a comment to irq_helper.h explaining why they aren't there.
    
    Change-Id: I709f9370ce7db1b3ffac2297aeaba5cc670ec20c
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6606
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 73d5d4cb11832a9140abb847d67ac9f108d0691b
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Aug 11 11:59:30 2014 -0600

    mainboard/XXX/YYY/dsdt.asl: Whitespace fix
    
    Use tab between "COREBOOT", and comment.
    
    This fix was requested in 90957f88 -
    "mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000"
    
    Change-Id: If9fb6158cca95341ab57db1125e85648b616b72c
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6601
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 9ff030fb252a84b0acf88c1af272831b7f2be928
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Aug 11 11:47:47 2014 -0600

    cpu/intel/fsp_model_406dx: code cleanup
    
    Code cleanup requested in commit 09670265 -
    "cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)"
    
    - add guard statements to chip.h
    - remove excessive includes
    - whitespace cleanup
    - add an IS_ENABLED
    
    Change-Id: Iaa85bd66953df015f083b23f6fd32949bcfd17bc
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6599
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 7aa704b822008efbbd540e97ae73f1c7d95e2c7d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Mar 3 00:44:38 2014 +0100

    apple/macbook21: Fix audio.
    
    Change-Id: I0bb939ac377f84431d871b702fdb42651e9a2e96
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5324
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 66476ddd99b65711989847eba5f4ef1f35b7670e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 17 22:57:03 2014 +0200

    Revert "macbook21: Add CST entries"
    
    Some of C-states still cause hang. Revert C-states patch.
    
    This reverts commit fe661612d8e94d41dc0129533bb02f7c4faaf11a.
    
    Change-Id: I7534dac5d27b853d7b93947c38bf3742797fdcc2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6694
    Tested-by: build bot (Jenkins)
    Reviewed-by: Francis Rowe <info@gluglug.org.uk>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 8c22057b2d905daeb310215fca0c0a67ad95322c
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 16 14:18:21 2014 +0200

    gm45: Declare BIOS memory as RAM.
    
    So it's in line with other boards and those addresses are cached for faster
    access.
    
    Change-Id: I7794d75ef1e3ceea6b2a4acba01e4af5d1f005f5
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6689
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit fe661612d8e94d41dc0129533bb02f7c4faaf11a
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 17 16:50:46 2014 +0200

    macbook21: Add CST entries
    
    Change-Id: I9e8628d879a193e2f6ba561ee17f24ae94435e1a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6693
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit bd146e0c9767525de6f7e05ab7e54ee043e6da0f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Mar 2 20:24:21 2014 +0100

    apple/macbook21: EC handling ACPI implementation.
    
    Now battery indicator and lid work.
    
    Change-Id: I2f747a408e331a245d91dd5f9c7ead0729f02a67
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5323
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit 9b90824a1f8ec0e775f36a2811c059415f4de788
Author: Mono <mono@posteo.de>
Date:   Sun Mar 2 18:40:36 2014 +0100

    A new port apple/macbook21.
    
    Current problems:
    - Complete lack of EC support (no battery indicator, no temperature, ...)
    - No audio support
    
    Change-Id: I25d09629dd82e01fadca2b6c25f72aaf08eafae1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Signed-off-by: Axel Holewa <mono@posteo.de>
    Reviewed-on: http://review.coreboot.org/5321
    Tested-by: build bot (Jenkins)

commit 26ca08caf81ad2dcc9c8246a743d82ffb464c767
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jun 1 00:24:05 2014 +0200

    i945: Replace video gfx init.
    
    Old init was a replay not even meant to have been committed.
    This one really computes values and does its job. Tested on
    Macbook2,1 (1280x800) and X60 (1024x768).
    
    Change-Id: I61b6946c095fe06e20ae9a0db54696d0568225dd
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5320
    Reviewed-by: Francis Rowe <info@gluglug.org.uk>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit fb2a9a9e30e40f546628ea48296e5f9c0ddec9c7
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Aug 15 02:06:00 2014 +0200

    lint-stable: Check that modified boards contain meaningful board_info.txt.
    
    Change-Id: Idd3ff029e16b4b963f13d341dabdc1949c4e9275
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6670
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ae143f71e7287cb676ce165995fe8c1cc62e8a22
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Fri Aug 15 11:54:54 2014 -0600

    AMD Family 14: Fix permissions on one northbridge file
    
    fam14_callouts.h should not have the execute bit set.
    
    Change-Id: Iab44d04f2c9669e28d2d5028b0a11e565cc7bb07
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6675
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 56ae8a0b0faf1ca009e977dbd05cd9f0ea3fc2eb
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 16 10:59:02 2014 +0200

    gm45: Decrease MTRR usage
    
    Change-Id: I4c790b0eaf2af94286e6691281fcad3d14659a99
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6687
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 084ed45a95a6afaf238572259e976d01320cf08b
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 16 10:51:06 2014 +0200

    gm45: Make UMA size configurable.
    
    Change-Id: I27b2ec70b9c77f3caf9d52788f46f5dc16045d1b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6686
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 16de28ae92ac05dcfb3963cf72c243f6dd4ca02d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 16 11:06:49 2014 +0200

    lenovo/x200: Remove leftover roda rk9 devices.
    
    Change-Id: Ief3baa985cf83059255e64a8ab78cad9f8571199
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6688
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit efd1c6b8dda729695ca91ecce5b7db25fa98bed1
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 16 10:57:15 2014 +0200

    gm45: Recognize 48MiB gfx UMA.
    
    Change-Id: I33e6b357ea044d6ec00b119e84cbada7bf58317f
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6685
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 880101121e0cef5df3afda075809e2fbacf68ffe
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 16 03:35:33 2014 +0200

    intel/gm45: native gfx init.
    
    Tested on lenovo X200 in both text and gfx mode.
    
    Change-Id: I273971d0f34ca3529959d4228e9516775459b806
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6682
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 905e6f2b56c9a87418e35c8d2f2decdeb7e0b56d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Aug 14 20:23:51 2014 +0200

    exynos5xx0: rename local "main" variable
    
    Change-Id: I9a454c88c65e4e70d351f1ec781e75ba400ceb29
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6664
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 5c715ac3c50dd50089ae4d8547e91444874a5a16
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Aug 14 19:23:41 2014 +0200

    bootstate: don't use header in romstage code
    
    Change-Id: I0c2943bb0889552dc384d8efb5226cd6982a4d81
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6663
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 0ed7940c5d0d789ae1394b2a4ab70d8b6924b109
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Thu Aug 14 13:08:29 2014 -0600

    libpayload: add march flag for armv7
    
    The cache functions for armv7 require 'march=armv7-a' to use
    the 'isb' and 'dsb' instructions.
    
    Change-Id: I3b7ad8fc7da8c3167b38fd1a325090fe49e4ca42
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6668
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3efc52fc0801673ee578be825023bfd7ac32b30a
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Thu Aug 14 12:23:24 2014 -0600

    libpayload: change cb_range to lb_range
    
    Patch 'coreboot_tables: reduce redundant data structures' (1f5487a)
    added a new lb_range structure to coreboot and libpayload but the
    original chromium patch added cb_range to libpayload instead. A followup
    patch 'arm: libpayload: Add cache coherent DMA memory definition
    and management' (b8fad3d) used the incorrect cb_range structure but
    this wasn't caught since the current verification build doesn't
    build libpayload for arm.
    
    Change-Id: I7cedc66a4794bf4daa214f54be6e917f96418ff6
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6665
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit a0a3727dbbd7f3ae9f9021e0797ce2fc61d1b79e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Aug 14 08:35:11 2014 -0500

    intel/cpu: rename car.h to romstage.h
    
    This header has nothing to do with cache-as-ram. Therefore, 'car'
    is the wrong term to use. It is about providing a prototype for
    *romstage*.
    
    Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6661
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b7f1bfcf289f218f05dfb17561a5b868eea65b92
Author: Isaac Christensen <isaac.christensen@se-eng.com>
Date:   Wed Aug 13 17:29:44 2014 -0600

    tegra124: fix Kconfig ARCH settings
    
    The initial commit for tegra124 (396b072) was not updated for the new ARCH settings.
    
    Change-Id: I147bdf289e91031bd0c0a61e6da43e9c1a438f84
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6658
    Tested-by: build bot (Jenkins)

commit f1d6e7e2cb75c01ff547359c9e601eaeba7c4155
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 9 07:16:10 2014 +0200

    Move baytrail-specific config to baytrail.
    
    Stop polluting first screen of all boards.
    
    Change-Id: I1ab88075722f7f0d63550010e7c645281603c9c3
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6548
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9665d389e453d852eef4bc4ae3699ee11d15c999
Author: Julius Werner <jwerner@chromium.org>
Date:   Fri Sep 13 18:21:46 2013 -0700

    libpayload: dma_malloc: Prevent warm reboot problems and add debugging
    
    Since the DMA memory is allocated by Coreboot (outside of the payload's
    linker script), it won't get zeroed upon loading like the heap.
    Therefore, a warm reboot that doesn't reset memory may leave stale
    malloc cookies lying around and misinterpret them as memory that is
    still in use on the next boot. After several boots this may fill up the
    whole DMA memory and lead to OOM conditions.
    
    Therefore, this patch explicitly wipes the first cookie in
    init_dma_memory() to prevent that from happening. It also expands the
    existing memory allocator debugging code to cover the DMA parts, which
    was very helpful in identifying this particular problem.
    
    Change-Id: I6e2083c286ff8ec865b22dd922c39c456944b451
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/169455
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit 8e5e1784638563b865553125cd5dab1d36a5d2cb)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6645
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 1f86434227beaf9806de86269f8b42eed817ae3a
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Sep 3 17:15:31 2013 -0700

    libpayload: xhci: Make XHCI stack usable on ARM
    
    This patch updates the libpayload XHCI stack to run on ARM CPUs (tested
    with the DWC3 controller on an Exynos5420). Firstly, it adds support for
    64-byte Slot/Endpoint Context sizes. Since the existing context handling
    code represented the whole device context as a C struct (whose size has
    to be known at compile time), it was necessary to refactor the input and
    device context structures to consist of pointers to the actual contexts
    instead.
    
    Secondly, it moves all data structures that the xHC accesses through DMA
    to cache-coherent memory. With a similar rationale as in the ARM patches
    for EHCI, using explicit cache maintenance functions to correctly handle
    the actual transfer buffers in all cases is presumably impossible.
    Instead this patch also chooses to create a DMA bounce buffer in the
    XHCI stack where transfer buffers which are not already cache-coherent
    will be copied to/from.
    
    Change-Id: I14e82fffb43b4d52d687b65415f2e33920e088de
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/169453
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit 1fa9964063cce6cbd87ba68334806dde8aa2354c)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6643
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d96541f3fc934fa27b800a07ccf0597bd5a80dd5
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Sep 10 11:02:58 2013 -0700

    armv7: mark EABI compatibility symbols as used
    
    These symbols are not used anywhere in our C code, so
    when using GCC's link time optimization feature they
    will be dropped even though they're needed by libgcc.
    Hence we need to mark them as used so GCC does not stumble
    and fall over its own guts.
    
    Change-Id: Ib2e9ea2610b57ab8244d5b699dd56025a4f08a01
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/168773
    (cherry picked from commit 416ffc880bcf4122b5430fbd9d9547c83886af2f)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6640
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 509c37e7507c6d68019abb096df0374858f541f5
Author: Julius Werner <jwerner@chromium.org>
Date:   Wed Aug 28 12:29:28 2013 -0700

    libpayload: Make EHCI driver cache-aware
    
    This patch makes the EHCI driver work on ARM platforms which usually do
    not support automatic cache snooping. It uses the new DMA memory
    mechanism (which needs to be correctly set up in the Coreboot mainboard
    code) to allocate all EHCI-internal communication structures in
    cache-coherent memory, and cleans/invalidates the externally supplied
    transfer buffers in Bulk and Control functions with explicit calls as
    necessary.
    
    Old-Change-Id: Ie8a62545d905b7a4fdd2a56b9405774be69779e5
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/167339
    (cherry picked from commit 322338934add36a5372ffe7d2a45e61a4fdd4a54)
    
    libpayload: ehci: Cache management is hard, let's go copying...
    
    It turns out that my previous commit to make the EHCI stack cache aware
    on ARM devices wasn't quite correct, and the problem is actually much
    trickier than I thought. After having some fun with more weird transfer
    problems that appear/disappear based on stack alignment, this is my
    current worst-case threat model that any cache managing implementation
    would need to handle correctly:
    
    Some upper layer calls ehci_bulk() with a transfer buffer on its stack.
    Due to stack alignment, it happens to start just at the top of a cache
    line, so up to 64 - 4 bytes of ehci_bulk's stack will share that line.
    ehci_bulk() calls dcache_clean() and initializes the USB transfer.
    Between that point and the call to dcache_invalidate() at the end of
    ehci_bulk(), any access to the stack variables in that cache line (even
    a speculative prefetch) will refetch the line into the cache. Afterwards
    any other access to a random memory location that just happens to get
    aliased to the same cache line may evict it again, causing the processor
    to write out stale data to the transfer buffer and possibly overwrite
    data that has already been received over USB.
    
    In short, any dcache_clean/dcache_invalidate-based implementation that
    preserves correctness while allowing any arbitrary (non cache-aligned)
    memory location as a transfer buffer is presumed to be impossible.
    Instead, this patch causes all transfer data to be copied to/from a
    cache-coherent bounce buffer. It will still transfer directly if the
    supplied buffer is already cache-coherent, which can be used by callers
    to optimize their transfers (and is true by default on x86).
    
    Old-Change-Id: I112908410bdbc8ca028d44f2f5d388c529f8057f
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/169231
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit 702dc50f1d56fe206442079fa443437f4336daed)
    
    Squashed the initial commit and a follow up fix.
    
    Change-Id: Idf7e5aa855b4f0221f82fa380a76049f273e4c88
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6633
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e8eb86f570723cc6becf7712b815c41e305bee5a
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Sep 18 05:37:20 2013 -0700

    libpayload: Add in a missing "static".
    
    The readwrite_chunk was private to the usb mass storage driver, but wasn't
    marked as static which was upsetting the compiler.
    
    Change-Id: I0ef5c5f96a29f793dd43ff672a939902bad13c45
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/169816
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 8140e6145b3d072b7f12a924418570022207c065)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6648
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ab11a6a94cc4f7d33fb2f8f3c34414e6dc4da255
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Mon Aug 11 16:09:07 2014 +0200

    payloads/external/SeaBIOS: move build directory
    
    Move SeaBIOS' build directory out of build/
    This allows the user to delete build/ in the top dir
    and keep the built binary in payloads/external/SeaBIOS/seabios/out/
    
    Change-Id: Ia7d515cd7e349beebcd9b62c9d956137acb73c82
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/6460
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit df6d09d0fb319f5c834b75babad62a0221582fce
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Thu Sep 12 18:23:09 2013 -0700

    libpayload: Reduce media init timeout to 5 seconds.
    
    Currently, we wait for up to 30 seconds for a device to become ready to
    respond to a TEST_UNIT_READY command. In practice, all media devices become
    ready much sooner. But, certain devices do not function with libpayload's
    USB driver, and always timeout. To provide a better user experience when
    booting with such devices, reduce the timeout to 5 seconds.
    
    Change-Id: Icceab99fa266cdf441847627087eaa5de9b88ecc
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/169209
    (cherry picked from commit 9e55204e92adca0476d273565683f211d6803e7a)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6647
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7ecc912b32f3fa1f94c1aadaba275ddb3d5efac5
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Thu Sep 12 18:09:39 2013 -0700

    libpayload: Increase accuracy of timeout period for media init.
    
    When bringing up media, we claim to wait for up to 30 seconds for a
    device to respond to our TEST_UNIT_READY command. Actually, we can wait
    far longer because we do not take into account execution delay.
    
    To improve timeout accuracy, make use of gettimeofday(), which calculates
    time based upon a CPU counter. This improves the user experience
    slightly when certain non-working USB devices are used.
    
    Change-Id: Id9605ecfc0a522d7a0b039fd8eac541232605082
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/169208
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    (cherry picked from commit 1d3d535db83ff478c512e37f37015b43927b3efc)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6646
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6ada053709f24675bda1b3598e86426a712d63f9
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Sep 11 15:18:14 2013 -0700

    Exynos: de-duplicate mct timer initialization
    
    timer initialization is the first thing happening in
    the Exynos CPU's bootblock code. Hence we don't need
    to keep track of it in several places, and we don't
    need to do it over and over again (e.g. in each stage)
    
    Change-Id: I7bd9a0b7930fc9c37faabd62e3eecc3e5614a879
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/168994
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit 5a95bc2bcab5a92c5e6c144005861bf731f59de3)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6638
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit d29bf2068f27d632fd02db75634b746c594681f8
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Sep 12 06:23:51 2013 -0700

    pit: snow: Fix snow, fix up pit write protect.
    
    A recent change to support early firmware selection on ARM broke snow and was
    incompletely implemented on pit. This change fixes snow by applying
    the remaining part of the change that had been applied to pit,
    and also hooks up real values in the get_write_protect_state function.
    
    Change-Id: Ifef7ad1bf399f79353daec3dd46973f2b2022e37
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/169120
    Reviewed-by: David Hendrix <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 841773e048cd9cfbb64782059c24e29c467f17c8)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6635
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1ab202795532cdce155e42738d84e77a3e77ceb2
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon May 26 17:38:23 2014 +1000

    Intel: Add common header file for CAR setup
    
    When passing '-ffreestanding' the 'main' romstage.c may no longer
    necessarily be considered the entry point.
    
    From the C specification in 5.1.2.1 Freestanding environment;
    
    "In a freestanding environment (in which C program execution may take
    place without any benefit of an operating system), the name and type of
    the function called at program startup are implementation-defined."
    
    Clang complains about these being missing as Clang is somewhat more
    strict about the spec than GNU/GCC is. An advantage here is that a
    different entry-point type-signature shall now be warned about at
    compile time.
    
    Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5872
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 67584f210a95188a5ff0d517130ac3cad4f38964
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Aug 13 23:04:46 2014 +0200

    lenovo/x200: Fix black screen on quick boot.
    
    Otherwise without USB when coreboot boots too quickly
    EC is confused and thinks that LID is closed and so
    powers off the backlight until user flaps the lid.
    
    Change-Id: I14dfaa62582de83fd4c9f9518e9436b3a3035366
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6651
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit d25273e7d72b08c54eaf2b129e32542cf67643d5
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Aug 13 23:06:07 2014 +0200

    gm45: Set D0F0_SKPD on normal boot path
    
    Otherwise we get a warning on normal boot.
    
    Change-Id: Ida1e1d23e258438251d4ec2417f93ad14c3b9f7d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6652
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 79c4ab6bfc4f256b920f6cac1eadc22d3040070a
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Aug 13 23:06:48 2014 +0200

    gm45: Set acpi_slp_type only once.
    
    It doesn't harm to set several times but it pollutes the log.
    
    Change-Id: I7aad7f0229a7d9d071ba844a1cfa123dffc4cacf
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6653
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 3a65d857ead2fcb8dd30a52cf4f68554a4bff275
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Sep 12 13:27:15 2013 -0700

    libpayload: usbmsc: Split transfers into 64KB chunks
    
    Add a new function to split transfer requests into chunks of
    64KB in order to be as compatible as possible with devices that
    choke when sent large transfer requests.
    
    Change-Id: Id11990bd149af14af5535de4af47bda21d1ab51e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/169170
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    (cherry picked from commit 4c413b007aa23da830877127dd556c4c38b43042)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6636
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 8f993784ef71f451995dd67fc709b88399c8a7e9
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Sep 9 14:37:03 2013 -0700

    ARMv7/Exynos: Fix memory location assumptions
    
    This patch cleans out a lot of unused variables in the
    ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE
    which is similar to CONFIG_RAMBASE on x86.
    This gets rid of the hard coded assumption that on ARM
    coreboot is always executed at the lowest DRAM address.
    But in fact, this might not be true because we might want
    coreboot to live at the end of RAM, or in SRAM
    
    Change-Id: I03e992645f9eb730e39a521aa21f702959311f74
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/168645
    Reviewed-by: David Hendrix <dhendrix@chromium.org>
    Tested-by: David Hendrix <dhendrix@chromium.org>
    (cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6634
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit fa938c7508627c0dfcf03960957ef8631fc53f02
Author: Julius Werner <jwerner@chromium.org>
Date:   Thu Aug 29 14:17:36 2013 -0700

    exynos5: Refactor crazy old U-Boot base address macros away
    
    All this samsung_get_base_address_of_device_with_a_really_long_name()
    boilerplate makes my eyes bleed... I think there are so much cleaner
    ways to do this. Unfortunately changing this ends up touching nearly
    every Exynos5 file, but I hope you agree that it's worth it (and the
    sooner we get it over with, the better... I can't bring myself to make
    another device fit into that ugly scheme).
    
    This also removes the redundant EXYNOS5 base address definitions from
    the 5420 directory when there are EXYNOS5420 ones, to avoid complete
    confusion. The new scheme tries to use EXYNOS5 for base addresses and
    exynos5 for types that are common between the two processors, and
    EXYNOS5420/exynos5420 for things that have changes (although I probably
    didn't catch all differences).
    
    Change-Id: I87e58434490ed55a9bbe743af1f9bf2520dec13f
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/167579
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: ron minnich <rminnich@chromium.org>
    (cherry picked from commit 66c87693352c248eec029c1ce83fb295059e6b5b)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6632
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 755615a12310469b34fc4804bcf2622eb587949c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Aug 28 16:29:40 2013 -0700

    exynos5420: Enable relocatable module support
    
    Since we're now supporting ARMv7 relocations, we can enable
    rmodule support on Exynos 5420. This does not automatically
    enable relocatable ramstage.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: Ic3af1eabb3b816944587a46409224f778d941b8a
    Reviewed-on: https://chromium-review.googlesource.com/167403
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit 7b5afef4ee87fc3245ec887dfda873c529d8d04d)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6629
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 3eab7ed45ee80b2711419f448bb2bc8ae9ea8194
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Thu Oct 3 17:05:55 2013 -0700

    Tegra,Tegra124: proposed layout for file hierarchy with example
    
    This change shows the source structure for nvidia Tegra and Tegra124
    SOC.  The problem we are trying to solve is that there is a large
    amount of common code in the form of .c and .h files across many
    different Tegra SOCs. The solution is to provide common code in a
    single directory, but not to compile in the common code directory;
    rather, we compile in a directory for a given SOC. Different SOCs
    will sometimes need different bits of code from the common directory.
    
    Tegra common code lives in tegra/, but there is no makefile there: if
    a Tegra common file is needed in a SOC, it is referenced via a
    Makefile in a specific Tegra SOC.
    
    Another issue is includes. Include files in the common directory  might be
    accessed by a piece of code in an SOC directory. More problematically,
    code in the common directory might require a file in an SOC directory.
    We don't want to put the SOC name in an #include path, e.g.
    in a C file in tegra/ is very undesirable, since we might be compiling
    for a tegra114.
    
    On some systems this is solved by a pre-pass which creates a set of
    symbolic links; on others with nested #ifdef in the common code
    which include different .h files depending on CPP variables.
    In previous years, both LinuxBIOS and coreboot have tried these
    solutions and found them inconvenient and error-prone.
    
    We choose to solve it by requiring explicit naming of part of the path
    of files that are in the common directory. This requirement, coupled
    with two -I directives in the Makefile.inc, allows common and SOC
    C code to incorporate both common and SOC .h files.
    
    .c and .h files -- SOC or common -- name include
    files in the common directory with the prefix tegra/, e.g.
    SOC files will be included from the SOC directory if they have no prefix:
    The full patch of clock.h will depend on what SOC is being compiled, which
    is desirable.
    
    In this way, a common file can pick up a specific SOC file without
    creating symlinks or other such tricky magic.
    
    We show this usage with one file, soc/nvidia/tega124/clock.c. This compiles.
    
    The last question is where to put the prototype for the function
    defined in this file -- soc.h?
    
    Change-Id: Iecb635cec70f24a5b3e18caeda09d04a00d29409
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: https://chromium-review.googlesource.com/171569
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 53e3bed868953f3da588ec90661d316a6482e27e)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6621
    Tested-by: build bot (Jenkins)

commit 5f5b4fdce31f96c1220694f471063286695b5f03
Author: Furquan Shaikh <furquan@google.com>
Date:   Fri Aug 2 13:39:35 2013 -0700

    Falco: Patch to setup FUI (coreboot initializations) for falco
    
    For now using the same gma.c and i915io.c files as for slippy
    
    Change-Id: Ieb09d0152d525aa090eeb86ebfa253d450d22820
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64373
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    (cherry picked from commit 3e119c7e22cb82677754413e56a125f4a372ad54)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6603
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c1c6dcf0f3bb332cf493969082414df16c025a32
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Aug 6 13:48:12 2013 -0700

    Falco: Patch to enable correct port clock selection for dp
    
    This is required only for haswell since the register configs have changed.
    Also, created mainboard specific header file
    
    Original-Change-Id: I61bf8d7cef1f204735a2f72225c48d6e44a99945
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    
    Conflicts:
    	src/mainboard/google/slippy/gma.c
    	src/mainboard/google/slippy/i915io.c
    
    Conflicts:
    	src/mainboard/google/slippy/gma.c
    Change-Id: I77f2542ca8228358f59aafd99c0d13168ab47fb5
    Reviewed-on: https://gerrit.chromium.org/gerrit/66853
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    (cherry picked from commit 77f9d1ddd4376e2a290d466f0669a43997492c8e)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6602
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan@google.com>

commit 77f48cdeade7fc296fb5c973b6b0191ac5bd8c35
Author: Furquan Shaikh <furquan@google.com>
Date:   Mon Aug 19 10:16:50 2013 -0700

    Falco/Slippy: Patch to refactor haswell/gma.c and mainboard/google/slippy/i915io.c
    
    A large portion of documented registers have been initialized using macros. Only a few
    undocumented registers are left out. i915io.c looks lot more cleaner by removing redundant
    calls. However, some more work is required to correctly identify which calls are not required.
    
    All the io_writes are replaced by gtt_writes.
    
    Change-Id: I077a235652c7d5eb90346cd6e15cc48b5161e969
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66204
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    (cherry picked from commit 39f3289f68b527575b0a120960ff67f78415815e)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6600
    Tested-by: build bot (Jenkins)

commit 61ffb4ca2e53004d3a282bfc2c97e58131cc9ef3
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Aug 12 22:51:53 2014 +0200

    lenovo/x200: New mainboard.
    
    Change-Id: I64e59648064d5875907b5057e2f9f72f2c5997b1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6631
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 883e7acc65e1edba8b2453decf23c88eafeae8b0
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Aug 13 01:22:13 2014 +0200

    lenovo/h8: Support uwb radio.
    
    It's the third minipcie slot in x200.
    
    Change-Id: Ibfa8d787698cd23b4abcffe5cff2d62039cf0f86
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6641
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 020dc0e13cca062b8e1983cb5e77a9482dcf6e53
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Aug 12 22:50:40 2014 +0200

    gm45: Allow skiping voltage config.
    
    Change-Id: I81b9966212d09d4d2561b3adc20d6d8a8a200f4b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6630
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 951fc26a084b030abb7876598831d2f6e158b5ca
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Sep 11 10:24:11 2013 -0700

    ARMv7: drop dead code from Makefile.inc
    
    This commented out code is a left over from x86.
    
    Change-Id: Ice806000c73d5a068962914d067d4de7b3d75f45
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/168961
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: David Hendrix <dhendrix@chromium.org>
    (cherry picked from commit 9d700cf35d2283a088e704c0ebd34e6f58f54993)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6639
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ef3a17bd88f3c751ef98d3be94eb922da14ce3c5
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Aug 2 10:15:44 2014 +1000

    util/inteltool: Typo in dump output for 'GP_IO_SEL3'
    
    The GPIO offset of '0x44 - GP_IO_SEL3' as specified in the pch.h header
    is incorrectly reported as 'GPIO_SEL3'.
    
    Change-Id: I56dcdda109d5f57ed45938d60b995807bdfb46b1
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6459
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 691ff08e27b9f79e5178a0c3e6c51f9327f207d5
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Aug 3 19:42:02 2014 +1000

    southbridge/amd/cimx/sb800: Uninitialized variables in config func
    
    Both 'SbSpiSpeedSupport' and 'UsbRxMode' are uninitiated upon return from
    a 'sb800_cimx_config()' call.
    
    Change-Id: I32237ff97fafc3e69627d427e54268dcb039e12c
    Found-by: Coverity Scan
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6474
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit aaaf689007cb6d80d326e5a297899e6719bdac30
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Aug 29 15:57:11 2013 -0700

    chromeos: On ARM platforms VBNV lives in the EC
    
    This patch renames the x86 way of doing things to
    explicitly mention CMOS (which is not available on
    our ARM platforms) and adds an implementation to
    get VBNV through the Chrome EC. We might want to
    refine this further in the future to allow VBNV
    in the EC even on x86 platforms. Will be fixed when
    that appears. Also, not all ARM platforms running
    ChromeOS might use the Google EC in the future, in
    which case this code will need additional work.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: Ice09d0e277dbb131f9ad763e762e8877007db901
    Reviewed-on: https://chromium-review.googlesource.com/167540
    Reviewed-by: David Hendrix <dhendrix@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit 8df6cdbcacb082af88c069ef8b542b44ff21d97a)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6616
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit b8fad3d02986222fa162d455eca2ffe807b6a15a
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Aug 27 15:48:32 2013 -0700

    arm: libpayload: Add cache coherent DMA memory definition and management
    
    This patch adds a mechanism to set aside a region of cache-coherent
    (i.e. usually uncached) virtual memory, which can be used to communicate
    with DMA devices without automatic cache snooping (common on ARM)
    without the need of explicit flush/invalidation instructions in the
    driver code.
    
    This works by setting aside said region in the (board-specific) page
    table setup, as exemplary done in this patch for the Snow and Pit
    boards. It uses a new mechanism for adding board-specific Coreboot table
    entries to describe this region in an entry with the LB_DMA tag.
    
    Libpayload's memory allocator is enhanced to be able to operate on
    distinct types/regions of memory. It provides dma_malloc() and
    dma_memalign() functions for use in drivers, which by default just
    operate on the same heap as their traditional counterparts. However, if
    the Coreboot table parsing code finds a CB_DMA section, further requests
    through the dma_xxx() functions will return memory from the region
    described therein instead.
    
    Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/167155
    (cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6622
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4498f6a6e57aa3bc1ed9449e3ad153b1a60c4eb6
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Sep 3 16:44:15 2013 -0700

    libpayload: usbhub: Don't clear PSC unless it was set
    
    The current USB hub code always clears the port status change after
    checking it, regardless of whether it was set in the first place. Since
    this check runs on every poll, it might create a race condition where
    the port status changes right between the GET_PORT_STATUS and the
    CLEAR_FEATURE(C_PORT_CONNECT), thus clearing the statrus change flag
    before it was ever read. Let's add one extra if() to avoid that possible
    headache.
    
    Change-Id: Idd46c2199dc6c240bd9ef068fbe70cccc88bac42
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/168098
    (cherry picked from commit f7f6f008f701ab3e4a4f785032d8024d676e11cb)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6617
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit eb623ab2044f77648658f4b0763616f5e1bea57a
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Oct 6 10:54:53 2013 -0700

    tegra124: Implement the monotonic timer by reading the 1us timer register.
    
    It turns out there's a register in tegra which automatically counts at 1us
    increments. It's primarily intended for hardware to use (I think to drive
    other timers) but we can read it ourselves since a 1us timer is exactly what
    we need to support the monotonic timer API.
    
    Change-Id: I68e947944acec7b460e61f42dbb325643a9739e8
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/172044
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 161a39c53404ea0125221bbd54e54996967d6855)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6620
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 59ebc6e919b22595a0047d63d70db915f41ae871
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Sep 28 20:39:21 2013 -0700

    tegra124: Add stack related config options to the Kconfig.
    
    Otherwise the stack ends up down at 0 and has 0 bytes.
    
    Change-Id: I0e3c80a0c5b0180d95819ab44829c2a0b527a54d
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/171015
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 3e69a477474697bcbc40762ec166e8a515d8b0c2)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6619
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7980b08405d8c3f2c0b3edf6af482c679f2560b2
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Sep 27 03:06:34 2013 -0700

    tegra124: Add some make rules which will wrap the bootblock in the BCT.
    
    These rules slip into the normal bootblock preperation process and use the
    cbootimage utility to wrap it in a BCT.
    
    Change-Id: I8cf2a3fb6e9f1d792d536c533d4813acfb550cea
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/170924
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit cf4a9b0712c21b885bb59310671fb87e38abb665)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6618
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 06667a52474bae9f9c88ed5efa9df44cb20c9dd3
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Aug 12 09:07:13 2014 +0200

    gm45: Move S3 detection to enable stage.
    
    Also move it to NB to be in line with other.
    
    Change-Id: Ibd961d60dcd686899f34f6a494c14ff9d65e618b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6625
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b1f34ab8d53e74c178492d9b001d1f5ef696e884
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Aug 12 21:40:32 2014 +0200

    i82801ix: Make RP04 optionally hotpluggable.
    
    Change-Id: I34a1ae4bff22db6ee55fa511de39bdfd5dd92c7e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6627
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9907be4bbd7f40f5d7466969c8c735b9a84807aa
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Aug 12 21:51:28 2014 +0200

    gm45: Reserve RAM for ME if it's active.
    
    Change-Id: Icd2b075cec9461f9d6028a8c845f6900b6fe04c8
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6628
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b25a9e9d3035c6e3c6969fed97a5193b95df249f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Aug 12 20:39:28 2014 +0200

    gm45: Allow coexistance with ME firmware.
    
    Change-Id: I08ca5eec94c70b43789122266d68af149772385c
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6626
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 32193e1f208191c908a1f8c601291541e86667a2
Author: ChromeOS Developer <dparker@chromium.org>
Date:   Mon Dec 16 23:41:11 2013 -0800

    Haswell: Lower TJ_MAX to 100C. Adjust critical temps to match.
    
    Change-Id: I3326b6e3c412b6360af37030cefd13d95b704e70
    Signed-off-by: Dave Parker <dparker@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/180750
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 1978b0f91b2e91d2251721c7c6981d51a6930b61)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6615
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5a0fdb4565dc6baf89155268dd0f52e6885197d8
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 29 13:12:56 2013 -0700

    exynos5420: minor clean-up memory related stuff
    
    This cleans up a few minor things (mostly #defines) of the memory code
    for exynos5420, pit, and kirby. Specifically:
    
    - CONCONTROL.empty is read-only, so don't try to set it and also
      get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define.
    - MEMBASECONFIG* overlaps members of the mem_timings struct and
      are mainboard-dependent anyway, so get rid of 'em.
    - DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may
      have been deprecated.
    - Same with TIMING* #defines.
    - Clarify DDR_MODE_* usage and use mem->mem_type when appropriate.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17
    Reviewed-on: https://chromium-review.googlesource.com/167500
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: ron minnich <rminnich@chromium.org>
    (cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6614
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 122b6d6ce694cd55087b4956780b2bbde8ccc6fe
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 29 14:05:21 2013 -0700

    exynos5420/pit: re-factor membaseconfig0/1 usage
    
    membaseconfig0/1 are utterly dependent on the mainboard's particular
    DRAM setup. This defines their values in the mem_timings struct for
    pit.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0
    Reviewed-on: https://chromium-review.googlesource.com/167488
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: ron minnich <rminnich@chromium.org>
    (cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579)
    
    exynos5420: necessary updates for DRAM
    
    This updates DRAM usage for Exynos5420 so that we can actually
    use 3.5GB:
    
    - Memory chips used with Exynos5420 may have 16 row address lines.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2
    Reviewed-on: https://chromium-review.googlesource.com/167489
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: ron minnich <rminnich@chromium.org>
    (cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1)
    
    Squashed two related commits.
    
    Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6613
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 72a42886505f54e81f437b618af1ab57e95c4b71
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Aug 23 15:25:07 2013 -0700

    exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420
    
    This changes the number of chip selects that we configure from 2 to 1.
    On current setups with (x16 memory 4Gbit chips) that means that we're
    at 2GByte.
    
    Technically we should add a second setting in the ares_ddr3_timings
    and select between the two of the based on board strappings.  That
    would make the CONFIG_RUN_TIME_BANK_NUMBER work properly.  I've
    changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not
    actually doing the board strapping read right now.
    
    This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G
    systems will no longer put the system in a messed up state (leading to
    a hang).  It also prevents some of the weird boot behavior that we've
    seen that comes and goes depending on U-Boot alignment.  See
    <http://crosbug.com/p/20577>.
    
    This patch was ported from: https://gerrit.chromium.org/gerrit/66117
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d
    Reviewed-on: https://chromium-review.googlesource.com/167210
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: ron minnich <rminnich@chromium.org>
    (cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6612
    Tested-by: build bot (Jenkins)

commit dd1aab95a6eb74eac7ea0463f7933d186dbd0efb
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 9 17:06:20 2014 +0200

    nvramtool: plug some memory leaks
    
    Change-Id: I8f672b872862d3448ccd2cf28fd3c05b0108ff8b
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6561
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 42b1b8069c35a4e86772b600ea0264503bf20470
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Aug 26 15:12:12 2013 -0700

    Exynos5420: ddr3: fine tuning the DDR3 timing values
    
    Fine tuning DDR timings value for better stability
    
    * Changed Data Driver Strength from 34 ohms to 30 ohms, expected to
      enhance signal integrity.
    * Changed DQ signal from 0xf to 0x1f000f, to keep default value safe.
    * Changed mrs[2] and added new mrs direct command for setting WL/RL
      without resetting DLL.
    * Added explicit reset value write in phy_con0 instead of just setting
      a bit, to ensure that reset happens.
    * Added DREX automatic control for ctrl_pd in none read memory state.
    
    This is ported from: https://gerrit.chromium.org/gerrit/61405
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1
    Reviewed-on: https://chromium-review.googlesource.com/66995
    Reviewed-by: ron minnich <rminnich@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit ec34b711c6d270672c56d45c370ca14c0aa27ca3)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6611
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 4610f0e64f92639e6992dc242dabbfbfc1cb7453
Author: Julius Werner <jwerner@chromium.org>
Date:   Thu Aug 22 16:24:09 2013 -0700

    libpayload: ehci: Set explicit terminate bits in dummy_qh next pointers.
    
    The EHCI host controllers in Samsung Exynos SoC seem to be a little more
    picky than Intel ones. When they reach the dummy_qh in the periodic
    frame list, they try to access the next qTD pointer even though it's
    NULL, and run into a HostSystemError. This patch explicitly sets the
    Terminate bit on those pointers to mark them invalid.
    
    Change-Id: I50fa79bbf1c5fab306d7885c01efd66b13e279b8
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66884
    Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
    (cherry picked from commit c575a5c958ce88732d28044352c89418bcd5ea86)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6608
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3ffdafdfa4cabdae4828638c402a6a81780bc275
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Aug 23 15:47:06 2013 -0700

    Exynos5420: Remove code for enabling read leveling
    
    This patch intends to remove all code which enables hardware read
    leveling. We need to disable h/w read leveling because new ASV table
    is merged in kernel (which is based on the new characterization
    condition) and new characterization environment has h/w read leveling
    disabled, so we should also disable this. Also, disabling h/w read
    leveling improves the MIF LVcc value (LVcc value is the value at which
    DDR will fail to work properly), improve LVcc means we have enough
    voltage margin for MIF. When h/w leveling is enabled, we have almost
    zero volatge margin.
    
    This was ported from: https://gerrit.chromium.org/gerrit/66070
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: Id0a2d77e6214325f226d51ae08464b39424cea83
    Reviewed-on: https://chromium-review.googlesource.com/66994
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit d29add98f52876aaed4fee2b76edf6b4591e66e8)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6610
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 79bff70ac829f45b27650671f9c33028c4b8f6c7
Author: Julius Werner <jwerner@chromium.org>
Date:   Thu Aug 15 17:34:45 2013 -0700

    exynos5: Refactor board-specific parts out of USB PHY code
    
    This patch moves around some of the existing Exynos5 USB 2.0 PHY code
    to make it cleaner in preparation of the 3.0 PHYs. It moves the VBUS
    GPIOs (which are completely board-specific) into the mainboard code and
    makes sure to only initialize PHYs on the boards that actually need
    them. It also removes the USB 3.0 PLL hack that was needed on Snow from
    the Pit and Kirby boards (which do not have that PLL anymore).
    
    Change-Id: Ia35f47a765acff60481f0907f7448ec4f78e0937
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66887
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit c3b1a8b687b535f4d5ac1b3bd2a4760151698fdb)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6609
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e9738dbe2bb564f7be7930aa5b01e9ae3c1e2288
Author: Julius Werner <jwerner@chromium.org>
Date:   Thu Feb 21 13:41:40 2013 -0800

    libpayload: Make USB transfer functions return amount of bytes
    
    The USB bulk and control transfer functions in libpayload currently
    always return 0 for success and 1 for all errors. This is sufficient for
    current use cases (essentially just mass storage), but other classes
    (like certain Ethernet adapters) need to be able to tell if a transfer
    reached the intended amount of bytes, or if it fell short.
    
    This patch slightly changes that USB API to return -1 on errors, and the
    amount of transferred bytes on successes. All drivers in the current
    libpayload mainline are modified to conform to the new error detection
    model. Any third party users of this API will need to adapt their
    if (...<controller>->bulk/control(...)) checks to
    if (...<controller>->bulk/control(...) < 0) as well.
    
    The host controller drivers for OHCI and EHCI correctly implement the
    new behavior. UHCI and the XHCI stub just comply with the new API by
    returning 0 or -1, but do not actually count the returned bytes.
    
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48308
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    
    Updated the patch to support XHCI as well.
    
    Change-Id: Ic2ea2810c5edb992cbe185bc9711d2f8f557cae6
    (cherry picked from commit e39e2d84762a3804653d950a228ed2269c651458)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6390
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0f0c720621deacc3c51b409e10ea8100acc88c80
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 22 18:45:10 2013 -0700

    exynos5420: ddr3: Cleanup init to use constants for directcmd
    
    The old ddr3_mem_ctrl_init() for exynos5420 had hardcoded constants
    for accessing directcmd registers.  Modify to use #defines where
    possible.
    
    This is ported from: https://gerrit.chromium.org/gerrit/#/c/65616
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I01567fc6941608a570832de97259c55e84942d01
    Reviewed-on: https://gerrit.chromium.org/gerrit/66789
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit d751e019f450172f060ce255ae53e972bc4a19ea)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6605
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 2f3daddd28c95a134f2543e366f8ee9dd8d2be41
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Aug 20 17:13:01 2013 -0700

    exynos5420: Alter init sequence as per recommendation
    
    As per hardware recommendation, CKE PAD retention release must
    happen just before gate leveling enable and only in case of resume.
    Hence, this patch moves pad retention release from dmc_common.c to
    dmc_init_ddr3_exynos5420.c. In addition to this we are providing
    125 (+3 extra being safe) times auto refresh to DRAM by sending
    REFA direct command. This is required because when CKE PAD retention
    release happens, self refresh mode of DDR3 is disabled.
    Hence, auto refresh 125 times.
    
    This is ported from https://gerrit.chromium.org/gerrit/#/c/65573
    
    Note: Since WAKEUP_DIRECT does not go thru memory init, it should be
    safe to move CKE PAD retention out of bootblock.c.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: Idec5d6fbbe3c6344d47401ba7203079c52a9b866
    Reviewed-on: https://gerrit.chromium.org/gerrit/66788
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit 96cbcb09245d4df92d3e1998704ab440be42df25)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6604
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ad4556f2cb429d921a9e00e3937797ea6f6f4cd8
Author: Julius Werner <jwerner@chromium.org>
Date:   Wed Aug 21 17:33:31 2013 -0700

    exynos5420: Make USB A-A booting work with early data cache
    
    Apparently the IROM doesn't like data caches... the recently added
    dcache-in-bootblock makes A-A booting fail, and flushes/invalidations
    alone don't seem to fix it. It's pretty fast anyway, so we just disable
    the cache again for the duration of the IROM call.
    
    Also removes a superfluous invalidation line from the bootblock code...
    dcache_mmu_enable/disable already take care of that.
    
    Old-Change-Id: I35580d15664c7b4197d4ed14028720147adbf918
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66602
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit e9c28a6a7a88c8286e62764ee5ad2694da2e822f)
    
    exynos5: Implement booting from SDMMC media
    
    This patch augments the alternative CBFS media source implementation for
    Exynos5250 and Exynos5420 to allow booting from SDMMC devices (such as
    an SD or uSD card reader, if available). It also moves MMC
    initialization for the Snow, Pit and Kirby boards from romstage to
    ramstage (mainboard_init) to prevent it from interfering with the IROM
    during SDMMC boot.
    
    Old-Change-Id: Ic4adef80c28262d084a53c28ec59aa7ac3af50c8
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66154
    (cherry picked from commit 08de13b72432c076e3327c048df93d89d52b0ecc)
    
    snow and pit: turn on FET4 (for SD card) at bootup
    
    Explictly enable FET4 on Snow and Pit.
    
    Historically we haven't needed to do this because:
    * On snow there's a bypass around FET4 which effectively eliminates
      it.  Even if we don't turn on FET4 the SD card is still powered.
      Turning on FET4 doesn't hurt though and is technically correct.
    * On pit the EC turns on FET4 on cold bootup.
    
    On pit we run into a problem if the kernel turns off FET4 like in
    <https://gerrit.chromium.org/gerrit/#/c/65332/> and then we get a
    software reset or warm reset.  In this case the EC won't know to turn
    it back on.
    
    This was ported from: https://gerrit.chromium.org/gerrit/#/c/65673
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: I57337f12b38889e6afee8577cf8807ec4c41e91c
    Reviewed-on: https://gerrit.chromium.org/gerrit/66786
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit e910117047d898b6b1d0dc965ef2ec0237d17646)
    
    Squashed three commits for alternate cbfs SD support.
    
    Change-Id: Idbd1fd4776cbf8cb20d03e6b691104cd8540a1ec
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6530
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 32eeff4b6eaf5e0bf1979cc9d08ac60d8d011354
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Aug 11 09:27:18 2014 +0200

    util: replace fseek/ftell/rewind with fstat
    
    It's a more direct approach to get the file size.
    
    Change-Id: If49df26bf4996bd556c675f3a673d0003b4adf89
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6594
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 77b182a31a17e237da2350b0290301f5ce51d9d8
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 10 15:18:22 2014 +0200

    board-status: be protocol agnostic on upload
    
    Generate the board-status repo URL by replacing the
    last occurrence of "/coreboot" by "/board-status",
    which works across repo URL schemes (gerrit provides
    several).
    
    Change-Id: Iccb53bde994be619c1436815e13741d63738edf7
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6574
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 8f15f4715a8627c032c78636798fe9bf8d23c6e1
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sun Aug 10 16:58:23 2014 +0200

    Kconfig: do not set SB_HT_CHAIN_ON_BUS0 twice to the same value
    
    Change-Id: If7286abf91f758cfbac2c85dcad336f38f70d843
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6579
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit ea70a5068fb6df4adcdb43142e77fdb2e9ccac1e
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sun Aug 3 13:47:58 2014 +0200

    util/genprof: improve handling of command line arguments
    
    Accept only one command line argument (the input file name); close input
    stream both on error and on success; print more informative error messages
    when files could not be opened.
    
    Change-Id: Ib2f0622a332317d7a13f33f1e5787381804c43a9
    Found-by: missing fclose()'s found by Cppcheck 1.65
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6573
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 21fbc08d4b3f99ca606dc1b9e12bcffef65bfb50
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sun Aug 10 15:18:42 2014 +0200

    armv7/Makefile.inc, cpu/Makefile.inc: align output of printf
    
    Fix whitespace.
    
    Change-Id: I9e28b819d685851a84cee6c5a71458e07d0ec808
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6577
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b40c345947d7891070f46f67e9ded65d74d58f7a
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Aug 11 11:10:29 2014 -0600

    mainboard/intel/minnowmax: clean up includes & whitespace
    
    Clean up as requested in commit e6df041b.
    No functional changes.
    
    Change-Id: Iec3f7ee25fd8351c7e13d660e2df6461f7745478
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6597
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9944b28cc478914233d9e555df6b9ab0cc46d097
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Aug 11 11:24:55 2014 -0600

    cpu/intel/XXX/acpi.c: Fix coding style violation
    
    Clean up a coding style violation as requested in the review of
    commit 09670265.
    
    Change-Id: I2815635efbb70a1e5841ca79cf2b4845bc6c23f2
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6598
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6481e1052fa88a4dcfb7220775ff67ecd3c70384
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 10 23:48:11 2014 +0200

    gm45: Ensure that brightness register in gma contains sane value.
    
    Change-Id: Ia66c71c3adf2ae0d413750b5e59e3eaba3888a0b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6587
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 8845759a024e7c2fb2c16cec5338e388574f0c70
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jul 31 16:50:18 2014 -0600

    vendorcode/intel/fsp/baytrail/absf: add Minnow Max absf files
    
    The absf files contain the modifications to the default settings in
    the FSP.  They are used as input files for Intel's 'Binary Configuration
    Tool' (BCT) along with the FSP.bin file to generate customized FSP
    binaries.
    
    The Minnow Max absf files set up the values for the soldered down
    memory.  This requirement will go away with the release of the next
    Bay Trail FSP, and the memory settings will be configurable at
    runtime.
    
    Change-Id: Id72545d78a7e82d9a5090710a9c7a8a9b1e81208
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6432
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 3ab015cddd49475df4509c99564236f828af7027
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jun 12 12:08:26 2014 -0600

    bayleybay_fsp: Add bakersport board variant
    
    The Bakersport board is a variant of the Bayley Bay mainboard that uses
    one ECC DIMM instead of two non-ECC dimms.
    
    This commit uses the Bayley Bay mainboard directory and modifies the
    required pieces to add the Bakersport board variant.  It disables the
    second DIMM, points to an ECC version of the FSP, and sets the board
    name to be Bakersport instead of Bayley Bay.
    
    All of the code is still contained in the bayleybay_fsp directory.  It
    seems like duplicating the whole directory for the one line of code
    that's actually different between the two platforms.
    
    Change-Id: Ia31e9ee927a6810a01a1ae143fcb00cfb7d8a7aa
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5983
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 40c845d3529cfd1a58c63f2cf356388b5d76e955
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 10 19:32:34 2014 +0200

    lint: provide better GPL license text test
    
    Still not lint-stable due to too many open issues, but
    at least it doesn't try to touch files that aren't part
    of the repository anymore.
    
    Change-Id: I654b15480094c7731a7d0d17fa1622a0b41ac34a
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6584
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 4b65c2ad3300990ea6b471559c5d10b5c6111430
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 10 19:07:09 2014 +0200

    lint: improve whitespace test
    
    The whitespace test only trips on files that are part
    of the git index - in particular not temporary editor
    files or other cruft that doesn't hurt anyone.
    
    Change-Id: I793fcc773845ee02281d8614b07e9c5958126a5a
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6582
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f3155d205e6c78b09e4a69af89aa4853bf6a9f6d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 10 23:53:42 2014 +0200

    gm45: Declare brightness variables for ACPI use.
    
    Change-Id: I23a088919aaac16066e5dd8300a081a8095a93f0
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6589
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e6df041b8bf8e37debc0d6a871080b64eea7a372
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Jul 28 14:22:32 2014 -0600

    mainboard/intel/minnowmax: Add MinnowMax mainboard
    
    MinnowMax board using Intel's Bay Trail FSP
    
    Working:
    - Booting from SATA / USB / (USB3 with latest SeaBIOS)
    
    Not working:
    - Boot from SD
    - S3 Suspend / Resume
    
    ***** To configure the FSP *****
    Download the Bay Trail FSP and the binary config tool:
    
    Modify the standard Bay Trail FSP:
    run the bct tool with the command line options:
    bct --bin <Bay Trail FSP Binary> \
    	--absf src/vendorcode/intel/fsp/baytrail/absf/minnowmax_Xgb.absf \
    	--bout <path to save the updated FSP to>
    
    Here are the required changes for modifying the FSP manually:
    	Enable Memory Down: Enabled
    	DRAM Speed: 1066 MHz
    	DIMM_DWidth: x16
    	DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max)
    	tCL: 7
    	tRP_tRCD: 7
    	tWR: 8
    	tRRD: 6
    	tRTP: 4
    	tFAW: 27
    Other FSP values can remain the same.
    
    ***** To configure the vbios *****
    The vbios is in the Bay Trail FSP package.
    Download Intel's "Binary Modification Program" (BMP)
    Use it to disable all ports except HDMI on port B.
    
    Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6429
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 83da50173ce0547320f029bf3ff46df62c084aac
Author: Julius Werner <jwerner@chromium.org>
Date:   Fri Sep 27 12:45:11 2013 -0700

    libpayload: xhci: Use Event Data TRBs for transfer event generation
    
    The current XHCI code only sets IOC on the last TRB of a TD, and
    doesn't set ISP anywhere. On my Synopsys DesignWare3 controller, this
    won't generate an event at all when we have a short transfer that is not
    on the last TRB of a TD, resulting in event ring desync and everyone
    having a bad time. However, just setting ISP on other TRBs doesn't
    really make for a nice solution: we then need to do ugly special casing
    to fish out the spurious second transfer event you get for short
    packets, and we still need a way to figure out how many bytes were
    transferred. Since the Short Packet transfer event only reports
    untransferred bytes for the current TRB, we would have to manually walk
    the rest of the unprocessed TRB chain and add up the bytes. Check out
    U-Boot and the Linux kernel to see how complicated this looks in
    practice.
    
    Now what if we had a way to just tell the HC "I want an event at exactly
    *this* point in the TD, I want it to have the right completion code for
    the whole TD, and to contain the exact number of bytes written"? Enter
    the Event Data TRB: this little gizmo really does pretty much exactly
    what any sane XHCI driver would want, and I have no idea why it isn't
    used more often. It solves both the short packet event generation and
    counting the transferred bytes without requiring any special magic in
    software.
    
    Change-Id: Idab412d61edf30655ec69c80066bfffd80290403
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170980
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Kees Cook <keescook@chromium.org>
    (cherry picked from commit e512c8bcaa5b8e05cae3b9d04cd4947298de999d)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6516
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 20e2f3c6e4fb56d0242405fd3a6c229952dfaccd
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 9 20:52:21 2014 +0200

    x86/smm/smihandler.c: break case in switch
    
    The case doesn't look like a deliberate fall-through,
    since the next case (SNB/IVB/HSW) is more specific
    than the one before it, so break out.
    
    Change-Id: I55497aefe9e835842a82121270f2b2a9952f560d
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6571
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit e3cdbbeb8e320a53f5da24635dde08e68e3c5b00
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 26 22:33:03 2014 +1000

    northbridge/intel/*/gma.c: Remove dead code
    
    Remove some dead coded spotted in Clang builds.
    
    Change-Id: Ia23e16eae76593eee249e0894ef1d704a274616f
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6130
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 133096b6dc31163f59f658e15f2eb342a0de2ac6
Author: Furquan Shaikh <furquan@google.com>
Date:   Thu Jul 31 09:28:55 2014 -0700

    coreboot classes: Add dynamic classes to coreboot
    
    Provide functionality to create dynamic classes based on program name and
    architecture for which the program needs to be compiled/linked. define_class
    takes program_name and arch as its arguments and adds the program_name to
    classes-y to create dynamic class. Also, compiler toolset is created for the
    specified arch. All the files for this program can then be added to
    program_name-y += .. Ensure that define_class is called before any files are
    added to the class. Check subdirs-y for order of directory inclusion.
    
    One such example of dynamic class is rmodules. Multiple rmodules can be used
    which need to be compiled for different architectures. With dynamic classes,
    this is possible.
    
    Change-Id: Ie143ed6f79ced5f58c200394cff89b006bc9b342
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: http://review.coreboot.org/6426
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9d2cb7c11e7498d0fd56571edd03158fc0c96225
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 10 21:56:41 2014 +0200

    i82801ix: Declare gen decode registers.
    
    Change-Id: I999818833c9040eb4f4e19c313b5e9be216ffd86
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6585
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3108b1aa1bf0ce028f8fb469f1cd19c0a3b3b9cd
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 10 19:15:04 2014 +0200

    lint: always remove temporary files
    
    In the error case, they survived.
    
    Change-Id: I15167be12ff9ee03f1b3bb86b93f20cb5be02b10
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6583
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 4ef309e85db0f44888650f98eead220ad147aa14
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 10 15:44:04 2014 +0200

    board-status: avoid shell error
    
    [ $3 -eq 1 ] fails if no third argument is given.
    [ "$3" -eq 1 ] still fails.
    
    Doing a string comparison is robust across shells.
    
    Change-Id: I3ee388fdbe51b7ab9344d86e67827654714d3191
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6576
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit bfca984b782585fba7ff800dfa2190f518d2c521
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sat Aug 9 16:26:17 2014 -0600

    soc/intel/fsp_baytrail: set up for including irqroute.h twice
    
    irq_helper.h intentionally gets included into irqroute.asl twice - once
    for pic mode and once for apic mode.  Since people are used to seeing
    guard statements on the .h files, add the guards to irqroute.h and add
    a comment to irq_helper.h explaining why they aren't there.  Add a
    time.
    
    Change-Id: I882cbbff0f73bdb170bd0f1053767893722dc60a
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6572
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 61f767f6a4d2eb93e70f13ed21e3c59e4c9d816c
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sun Aug 10 16:11:38 2014 +0200

    .gitignore: add 3 executables that can be built in util/
    
    Change-Id: I16aa154ae0b6f21d5e160a950d39013820d7503c
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6578
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 466ea0c3d387445a2282e67de614d16f5478e48a
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 10 19:06:45 2014 +0200

    board-status: remove whitespace
    
    Change-Id: I76ae5e294c157e73d07fd30cdb1c191d78efd5eb
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6581
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit d668cceae091156f95a056170e23783193f68e21
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 10 21:58:23 2014 +0200

    gm45: Set default VGA PCIID.
    
    Change-Id: I2eba1ca27c1f8181a9c6288f6794922915575790
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6586
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b359adebc5030debdf67d94fde1e89db4ca0148a
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 10 23:52:04 2014 +0200

    lenovo/h8: Remove useless smi.h include.
    
    It's not really used.
    
    Change-Id: I760d5a4cbe46d17ef37ea34e29eecdb0721cb945
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6588
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c1a20f0cb8d326d3b6ef5477dc4d7ee9f095665c
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Aug 10 09:35:56 2013 -0700

    LZMA: Add a version of ulzma which takes the input and output buffer sizes.
    
    This new version is used to implement the version which doesn't take the
    input and output buffer sizes.
    
    Old-Change-Id: I8935024aca0849bc939263d7fc3036c586e63c68
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65510
    Reviewed-by: Kees Cook <keescook@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 465d167ad2f6a67d0b2c91fb6c68c8f9a09dd395)
    
    libpayload: Make lzma truncation non-fatal.
    
    If the size the lzma header claims it needs is bigger than the space we have,
    print a message and continue rather than erroring out. Apparently the encoder
    is lazy sometimes and just puts a large value there regardless of what the
    actual size is.
    
    This was the original intention for this code, but an outdated version of the
    patch ended up being submitted.
    
    Old-Change-Id: Ibcf7ac0fd4b65ce85377421a4ee67b82d92d29d3
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66235
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 30c628eeada274fc8b94f8f69f9df4f33cbfc773)
    
    Squashed two related commits and updated the commit message to be
    more clear.
    
    Change-Id: I484b5c1e3809781033d146609a35a9e5e666c8ed
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6408
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 586460b24276d944deed1d3c599bcae96457a1db
Author: Julius Werner <jwerner@chromium.org>
Date:   Mon Oct 28 20:00:50 2013 -0700

    cbfs: Check return value of map() for error
    
    The CBFS core checks the result of a media->map() operation in multiple
    places for CBFS_MEDIA_INVALID_MAP_ADDRESS, suggesting that this is a
    valid response. However, it ironically fails to do so when actually
    mapping the CBFS file itself, which can fail on buffer-constrained
    systems since the size is much larger than when mapping metadata. This
    patch adds a check with an error message and a NULL pointer return for
    that case to make it easier to understand this condition.
    
    Change-Id: Icae3dd20d3d111cdfc4f2dc6397b52174349b140
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174951
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    (cherry picked from commit 63f2c4465f9633a637186e69bc3862d5413106ac)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6537
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 141512161b40666e83094d8d99c544ce9a74ab8f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Sep 16 14:23:16 2013 -0700

    vboot: Implement VbExGetTimer using monotonic timers
    
    On x86 VbExGetTimer() uses rdtsc. However, on all
    other platforms, let's just use coreboot's monotonic timers.
    
    Change-Id: I0cd359f298be33776740305b111624147e2c850d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/169620
    (cherry picked from commit e910bb17522d5de42c0fc3cc945278e733fa2553)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6534
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7cb01e0bcfe4287df83b0bc07928dae33e29a9c8
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Aug 29 16:05:02 2013 -0700

    drivers: Add I2C TPM driver to coreboot
    
    On ARM platforms the TPM is not attached through LPC but through I2C.
    This patch adds an I2C TPM driver that supports the following chips:
     * Infineon SLB9635
     * Infineon SLB9645
    In order to select the correct TPM implementation cleanly, CONFIG_TPM
    is moved to src/Kconfig and does the correct choice.
    
    Old-Change-Id: I2def0e0f86a869d6fcf56fc4ccab0bc935de2bf1
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/167543
    Reviewed-by: ron minnich <rminnich@chromium.org>
    (cherry picked from commit b4049a0e96f6335a93877e1e884f9a440487c421)
    
    i2c tpm: Remove mostly useless delay code/tables.
    
    I assume from the code in the TPM driver that the TPM spec defines
    different types of delays and timeouts which each have a particular
    duration, and that the TPM can tell you how long each type is if you ask
    it. There was a large table, some members of a data structure, and a
    function or two which managed the timeouts and figured their value for
    different operations.  The timeout values for the various "ordinals"
    were never set in the vendor specific data structure, however, and
    always defaulted to 2 minutes.  Similarly the timeouts a, b, c, and d
    were never overridden from their defaults.  This change gets rid of all
    the timeout management code and makes the "ordinal" timeout 2 minutes
    and the a, b, c, and d timeouts 2 seconds, the larger of the two default
    values.
    
    This is a port from depthcharge to coreboot, original change:
    https://chromium-review.googlesource.com/#/c/168363/
    
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Old-Change-Id: I79696d6329184ca07f6a1be4f6ca85e1655a7aaf
    Reviewed-on: https://chromium-review.googlesource.com/168583
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit b22395a73f361c38626911808332a3706b2334fe)
    
    TPM: Stop requesting/releasing the TPM locality.
    
    The locality is requested when the TPM is initialized and released when
    it's cleaned up. There's no reason to set it to the same thing again and
    restore it back to the same value before and after every transaction.
    
    forward ported from https://chromium-review.googlesource.com/#/c/168400
    
    Old-Change-Id: I291d1f86f220ef0eff6809c6cb00459bf95aa5e0
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/168584
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit cc866c20c6f936f349d2f1773dd492dca9bbf0c1)
    
    Squashed three commits for the i2c tpm driver.
    
    Change-Id: Ie7a50c50fda8ee986c02de7fe27551666998229d
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6519
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e17843c4a75ce440e19d545ddb2e04372f548c07
Author: Steven Sherk <steven.sherk@se-eng.com>
Date:   Wed Aug 14 14:55:57 2013 -0600

    cbfs: Fix overwalk on file scan
    
    A bootblock overwalk was occuring when deriving the actual
    length, the bootblock size was not taken into account and bootblock
    size was not aligned.
    
    Resolved merge conflict.
    
    Change-Id: I7eb42f8deaaf223dcf07b37bb7dde4643acd508f
    Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65989
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Steve Sherk <ssherk70@gmail.com>
    Tested-by: Steve Sherk <ssherk70@gmail.com>
    (cherry picked from commit 20b0ba479b01755fbdc7f3dd9214e8af923402ba)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6539
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1f5487a7c0687b910a898b1fe704e9b75947b5dc
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Aug 27 15:38:54 2013 -0700

    coreboot_tables: reduce redundant data structures
    
    There are three coreboot table tags that all define some kind of memory
    region, and each has their own homologous struct. I'm about to add a
    fourth so I'll just clean this up and turn it into a generic struct
    lb_range instead.
    
    Change-Id: Id148b2737d442e0636d2c05e74efa1fdf844a0d3
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/167154
    (cherry picked from commit 22d82ffa3f5500fbc1b785e343add25e61f4f194)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6456
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 579538b5c764e813866b3eae60f79bfc1d801471
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Oct 4 11:54:04 2013 -0700

    lynxpoint: Add interrupt for GPIO controller in ACPI device
    
    The GPIO controller uses IRQ14 as an active high level triggered
    source for GPIOs that are configured to trigger shared interrupt.
    
    This was also tested on bolt by configuring the touchscreen to use
    a shared GPIO interrupt:
    
    localhost ~ $ grep atmel_mxt_ts /proc/interrupts
    54:    24    188    93    124    LP-GPIO-demux    atmel_mxt_ts
    
    Change-Id: I3765120112bae11407e5b2020399d0d0b8e3cef8
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171901
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 63a0c80ce5a19410d0608fede5a9fe0ec1c8e5c1)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6541
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d988b612c76cb34f689c567e9e983e496f65008a
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Sep 25 14:05:31 2013 -0700

    bolt: Set GPIO29 as input in S0, output+high in S3/S5
    
    This resolves WiFi issues after suspend/resume.
    
    It needs related SPI descriptor soft strap change to
    enable SLP_WLAN as a GPIO instead of owned by the ME.
    
    Change-Id: I03f4458d1e52a913770d391061baa6cfa41e8558
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170577
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit cf1fe0524ad4793c8c422dc3fed3007b7fc96038)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6533
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit cff6667eba803498e2f93af68e6e2edbba2353e5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Aug 29 09:16:25 2013 -0700

    exynos5420: Tighten up displayport timing loops
    
    We were running this loop 100 times with 5 ms delays. Change it
    to run 500 times with 1 ms delays, which gives us the same
    overall timeout but lets us bail out a bit sooner -- in practice,
    at most, 4 ms sooner but every bit counts. Note, however, that
    the tighter timing does reduce opportunities for threading. There
    is a non-obvious set of tradeoffs on timeouts.
    
    Change-Id: I4af671c2a791aa92e446e66ac2fe5710d1e6aa4c
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: https://chromium-review.googlesource.com/167387
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: ron minnich <rminnich@chromium.org>
    Tested-by: ron minnich <rminnich@chromium.org>
    (cherry picked from commit 575e910127dc74416018f182ef27ef223e61daef)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6543
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 985ff36bee24d1e5a8bd698409a0a05e15528c01
Author: Julius Werner <jwerner@chromium.org>
Date:   Wed Sep 18 14:39:50 2013 -0700

    armv7: Support stack dump after exceptions
    
    This patch enhances the armv7 exception handlers in Coreboot and
    libpayload to show the correct SP and LR registers from the aborted
    context, and also dump a part of the current stack. Since we cannot
    access the banked registers of SVC mode from a different exception mode,
    it changes Coreboot (and its payloads) to run in System mode instead. As
    both modes can execute all privileged instructions, this should not have
    any noticeable effect on firmware operation (please correct me if I'm
    wrong!).
    
    Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170045
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
    (cherry picked from commit d0db2f5e938200e3f5899c5e1f1606ab2dd5b334)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6538
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 802ad521804b8a9f473780fdff4058dd3f8520c3
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 9 17:12:23 2014 +0200

    ifdtool: Provide bounds on string parser
    
    While the result will not be pretty (ie. ifdtool will
    mis-parse string components longer than 255 characters),
    at least it doesn't overflow stack variables anymore.
    
    Change-Id: I263c5cf823a2d8a863dcece7c4ee0b26475f9fc4
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6562
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit a438049422fae85fe4df3ab3f89dbca797d6f5a9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Sep 17 22:01:48 2013 -0500

    model_106cx: don't blindly set Kconfig settings
    
    The CPU_ADDR_BITS was being unconditionally set.
    Don't do that.
    
    Change-Id: Idbc63328fade8f5f05f7f46282139b86e6694989
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/169711
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    (cherry picked from commit 858f96d28d8d0aeffe58e1d4d1d559ad161aab66)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6535
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ba2468d8859b7204f91c28a022b76ae995cc08a2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 2 14:43:58 2013 -0700

    falco: Add support for Samsung memory
    
    New SPD and update to the SPD map.  Add both a 4GB and 2GB option.
    
    4GB = RAM_ID{1,1,0}
    2GB = RAM_ID{1,1,1}
    
    Original-Change-Id: I37318c1b5a6ee84b7c55da00d326f10fe8af6f1e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    (cherry picked from commit 7eb5a4ef1062a34e883c3f356ab0dc00ba07910d)
    
    Change-Id: I0f35a7f5191fefeb5910a2d28aea153516d9a11d
    Reviewed-on: https://chromium-review.googlesource.com/171693
    Tested-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
    (cherry picked from commit b02fa777aa5935021b2c69f7345dffd111cbd118)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6545
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b404511f13972adbeccc3c694d4f7758374a8f27
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Sep 24 03:05:12 2013 -0700

    ARM: Eliminate the unused interrupts.c.
    
    This file isn't compiled into anything, and probably wouldn't since it has a
    lot of baggage from it's U-Boot origins.
    
    Change-Id: I29d87afd2a283010a653d3d48fdd3a79622e3b99
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/170423
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-by: David Hendrix <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 1146c570f0e448f7db4ec82749e91099c946a2dc)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6544
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7d8a91d0a50f1ede9d902563dfff3eda701943ee
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Sep 24 02:36:36 2013 -0700

    exynos: Get rid of the unused reset.c.
    
    The source file reset.c, present in both the exynos5250 and 5420 directories,
    is not being built for either SOC. Let's get rid of the clutter.
    
    Change-Id: Iab4c7982a271d08cbaf3207b6f5431f0ef52697e
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/170402
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-by: David Hendrix <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 0ce3898276ff49d171a0d8a650806f0305c0576f)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6542
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit cb61ea7a13dd7adea1f2fa3e06ec702ec86b4a88
Author: Furquan Shaikh <furquan@google.com>
Date:   Thu Aug 15 15:23:58 2013 -0700

    Falco/Slippy: Patch to remove redundant graphics initializations
    
    gma_fui_init repeats the initializations already performed in gma_setup_panel.
    These redundant initializations reset any gtt settings done before this call.
    Hence, they had to be done again after call to gma_fui_init. However, the call
    gma_fui_init is not required at all. Does not affect the behavior of suspend/resume.
    
    Old-Change-Id: Idfb9f9930624694b878ddc0fe8648b3c8dd80e55
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65997
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    (cherry picked from commit c376aea1b89c9a829874d5c657693993a3bb1f13)
    
    Falco/Slippy: Patch to fix garbage on screen during graphics initialization in normal mode
    
    Depending on the init_fb parameter:
    1) For normal mode, first page is filled with zeroes and setgtt is used make all GTT entries point to this
    same page
    2) For developer/recovery mode, we init the gtt to consecutive pages
    
    Old-Change-Id: I281b0b7efe01f7892e98b19ff9a63c04b087bd2c
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65633
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    (cherry picked from commit 97c99dfe52ef3a87d387fdbf27ad3a28ad81c722)
    
    Squashed two graphics related commits for Falco/Slippy.
    
    Change-Id: I7ddb92672c026fe66f9fb0caba9d8fdc3f8a9d0a
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6536
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0f027e421a9c7040d232a1a41b3940243b1cba1f
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Jan 21 14:30:51 2014 +0100

    libpayload: hexdump.c: Change type of length argument to size_t
    
    Representing a (non-negative) length with a signed integer is not
    optimal, so change its type to `size_t`.
    
    Change-Id: Ic0c2b7e081ba32d917409568ee53007d9ab7f8f3
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/4768
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d0cdcaeb086ce215915b098d08ff6ec2d5198327
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Aug 8 15:24:31 2014 +0200

    southbridge/ricoh,ti: Remove trailing whitespace in debug output
    
    Change-Id: If58854c35dce83bf6db7a84a8cb441cc3e60d6d4
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6529
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9ed8a82d265fde1df1a01be7568d8f0979020108
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Dec 3 21:25:35 2013 -0800

    serial: Separate the serial hardware init and the serial console init.
    
    You might want to use the serial hardware for something other than a console,
    or you might want to intercede in the serial stream to wrap it in another
    protocol. This is what you'd do to send output to GDB while using it to debug
    the payload.
    
    Change-Id: I2218c0dbb988dacb64e5bdaf5d92138828eff8b6
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/179559
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit da9ab46d974745125fe7d8b29ce43336c3586cd5)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6547
    Tested-by: build bot (Jenkins)

commit e211bd9b7878009e4736fd9d15d6b03164e02267
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 9 17:16:24 2014 +0200

    src/lib/edid.c: missing break statement
    
    While vendor specific extension blocks are mostly opaque to us,
    they're not exactly "unknown".
    
    Change-Id: I9136c04d12045ad13ef4f942c0814c4df88bdf6b
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6563
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a65c21eeb52103698555996eb541eae34a6c2adb
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 9 16:58:00 2014 +0200

    cbfstool: free stale memory
    
    The process probably terminates not much later, but in
    case anyone reuses the function in something with
    longer life-time, free unused resources.
    
    Change-Id: I10c471ee3d9dc9a3ebf08fe4605f223ea59b990e
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6559
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c5d179123df5e7d8b72e613935b9e1bd278886f9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 9 17:02:00 2014 +0200

    nvramtool: check for successful seek
    
    Otherwise the following write might end up anywhere.
    
    Change-Id: Ie42d984824e9308bd58b8bb905b6ea823543adf0
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6560
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b6239b81aa3a3ac9cb08aa70d1f1179e1619f429
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 9 19:42:08 2014 +0200

    romcc: properly check out-of-range unsigned longs
    
    Testing if an unsigned long is greater than ULONG_T_MAX isn't very
    useful. The second half of the test checked for too small values
    (ie. <= -ULONG_T_MAX).
    
    In both cases errno is set to ERANGE, so just check for that.
    
    Change-Id: I92bad9d1715673531bef5d5d5756feddeb7674b4
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6568
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f17c58b415219d889fe57a06be63f826f7a7c1b7
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 9 20:48:12 2014 +0200

    cpu/intel/model_1067x: avoid null-pointer dereference
    
    Change-Id: I7467d4a947e9e447707e1370b7e639ddddc20d3d
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6570
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 77c9508f58d93e44e30952618c1b95fbc7b6faaa
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 9 19:50:15 2014 +0200

    intel/fsp_bd82x6x: Fix cycle error some more
    
    As a follow up to #6479 (63e1948643fcbd763c83b6baa6cd9a077d49f1fc),
    fix the remaining faulty loop.
    
    Change-Id: I2c77efe620c71e939f4d74e48f90a166c782e5f5
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6569
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit e887ca5a745720e3d35527e4fd4e21b8c0b3b3b9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 9 17:44:39 2014 +0200

    cbfstool: fix option parsing
    
    "cbfstool create -B bootblock -s size" (in this order)
    would break bootblock selection.
    
    Change-Id: I9a9f5660827c8bf60dae81b519c6f026f3aaa0f3
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6564
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit a0a019698d29a869eaf299cadcfda11e331f995f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Aug 10 02:09:13 2014 +1000

    cpu/amd/geode_lx: Trivial - remove useless comment
    
    Change-Id: I4b04f84fb2be7da4b7ffab71bb2c41142f455440
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6567
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 1882527399ab835bc24cb44b08774c3f101c4396
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Aug 9 18:07:42 2014 +0200

    ivybridge: Don't propose to include systemagent on native boards.
    
    Change-Id: Ib70a6741b55609840b6fd2fca16bcf9883bf143c
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6566
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 8a57b3922342bbe4557a9efcd05125dd18c79e84
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Aug 8 00:10:28 2014 +0200

    lenovo/x201: Enable wake on LID and Fn key.
    
    Change-Id: I485da5b8e9084c73f16b5df1c42879697fc0ac3d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6528
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 309a7ffc6624f4fad4d7904c78c1a4d35a84bbcf
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Aug 9 21:38:56 2014 +1000

    southbridge/amd/cs5536: Trivial style fix for trailing comment
    
    Change-Id: Ia3a846497c220866e950a4b0bb53cb05c0e0cee2
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6557
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cd2c1245f03c9f23192b499a3995cf794663dc02
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Aug 9 15:51:19 2014 +1000

    cpu/amd/geode_lx: Reduce fancy ASCII art with embedded comments
    
    Lets try not to play games with the Lexer with fancy ASCII art. Doxygen
    has a more well defined and useful syntax for annotations.
    
    Change-Id: I6f6c58971f509064ae1e28a1740e50e2ae721513
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6550
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 728ff392e7aa11260675721e87c31c9070c1903f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Aug 9 15:48:51 2014 +1000

    cpu/amd/geode_lx/cache_as_ram.inc: Trivial - Fix indent with tabs
    
    Change-Id: Ic65f8d2cbb5bc459cf513c6b34a5f1846cb2b897
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6549
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ff0df2bba5f29dc992c0ab59b44337b7277c231a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Sep 17 14:08:29 2013 -0700

    Exynos5420: clean up SPI driver
    
    That extra struct is not needed, we already defined it earlier on.
    Also fix coding style in the file.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I586d290f2f3ba2f44aca7fdee400b88547465599
    Reviewed-on: https://chromium-review.googlesource.com/169780
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit f7df9f05fb707cac7976cd8a0b36bcf30cef8e0f)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6532
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 2f6b0a9a4b7dd7c6b04c6f17f024db8643afde5f
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Wed Oct 16 18:23:25 2013 -0700

    Set check-lxdialog.sh mode properly
    
    This script is used by 'make menuconfig', but being non executable it
    fails to run, causing the make invocation failure.
    
    Setting 'x' mode bits fixes the problem.
    
    Change-Id: I925ca4ee056937b6c38ad34f5520fd621f9d9eb0
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/173564
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit 3ddb9d221ecc3df968853d765b566cf0648a7525)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6540
    Tested-by: build bot (Jenkins)

commit 6ed2a242ee800201a98456cafce7f6232c30816c
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Wed Jul 30 14:16:07 2014 +0200

    intel/eagleheights/Kconfig: Do not set twice MMCONF_BASE_ADDRESS
    
    Remove the lines added in an apparently unrelated commit 53ad9f58 (Make CONFIG_HAVE_HIGH_TABLES consistent in where and how it is set.)
    which touched the symbol HAVE_HIGH_TABLES in all files except this one and
    keep those added the same day in commit 6842c029 (Remove MAINBOARD_OPTIONS, which is a relic from early kconfig development.)
    
    Change-Id: Ib055c25a0a0795a50a36e65218c8f31e921f1502
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6417
    Tested-by: build bot (Jenkins)
    Reviewed-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 4e9f5e3f36ec5b497a74e5da0c202c1b62f9e620
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Aug 2 20:45:13 2014 +1000

    superio/smsc/sio1036: Clean up RAMstage superio.c component
    
    Remove spurious includes, unused variables and some wasted new lines.
    Re-organise things to be consistent with other superio's.
    
    Change-Id: I959bab2f7a83a1b9160d7f010a0de9638b30cf07
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6465
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit c14e961f239adb3635fb47ad4e4c5891b3b09a29
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Aug 22 10:19:25 2013 -0700

    falco: Remove RTD2132 chip and setup from devicetree
    
    This disables the spread spectrum clock and avoids errata.
    
    Old-Change-Id: I04eb767f1587bb64a215a92b66cd05e099d29964
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66673
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit a7bf0d818c431221f4d014e3a0130bec8db7406e)
    
    falco: Remove RTD2132 driver from kconfig
    
    Original-Change-Id: I89ad9fbfbc58878602ed85ada918524426b5bc77
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66946
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 1d732eb5e4743546b8ed50c8c44965a687f61ab2)
    
    Conflicts:
    	src/mainboard/google/falco/Kconfig
    
    Old-Change-Id: I317a0741779e272ad72b7272ef6f4a67abd66698
    Reviewed-on: https://chromium-review.googlesource.com/167311
    Tested-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
    (cherry picked from commit ffa6c89fbac04b4b6fceafd4ba97d39a285c4aa3)
    
    Squashed two commits and corrected the subject line from 2312
    to 2132.
    
    Change-Id: If4f1e59999b70efe2de45522ba78051d9ed88dd7
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6527
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 45f868d34f0116e092672b881c99a2aa0c773244
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Aug 13 16:09:33 2013 -0700

    Falco/Slippy: remove unwanted scratchpad writes
    
    Register range 0x4f000 - 0x4f08f includes scratchpad registers. Fastboot
    works fine with these registers removed and graphics is initialized properly
    
    Change-Id: Ic57c526a90619f4a073690440f6c5ac6ca96bf10
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65755
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    (cherry picked from commit 7e7befdc3956cbc28d346545669cb55c566cf3ea)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6525
    Tested-by: build bot (Jenkins)

commit 42b1c34f7ba94fe2a615e320e126fae10e8de521
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Sep 16 14:27:17 2013 -0700

    ARMv7: Add stdint types needed for vboot library
    
    Change-Id: I778ea787b20a7d7d7b202b1b5e7f956d2fde6629
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/169621
    (cherry picked from commit 499a4802b5ad070a0b82f3b291073aa05fa7946e)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6523
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9ad28b940f74a17c88069816df1f20c0b03a9552
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Sep 17 14:15:16 2013 -0700

    chromeos: Add code to read FMAP on ARM
    
    On ARM the SPI flash is not memory mapped. Use the CBFS
    interface to map the correct portion.
    
    Change-Id: I8ea9aa0119e90a892bf777313fdc389c4739154e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/169781
    Reviewed-by: David Hendrix <dhendrix@chromium.org>
    (cherry picked from commit a263d3717e82c43fe91e7c4e82d167e74bf27527)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6522
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit da36bcf0d4334695b797166b865006842a1ae7e2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Sep 9 11:20:47 2013 -0700

    qemu-armv7/media.c: fix coding style
    
    Change-Id: I01a11923fc1b250afeed36acc20793fd072421ba
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/168574
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 46b5f64096c55d0d9627cb9537fc4910e1bddcd9)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6520
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 9dd01eb416f371d3101d63a212439a9003c101b4
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Aug 28 09:53:57 2013 -0700

    falco: Add double function reset to ALC283 verb table
    
    The ALC283 needs a double function reset to ensure that all settings
    are reset and the firmware beep is functional.
    
    Original-Change-Id: Id9ddc6f4914957f39c5f9cdfaaac354808929146
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/167291
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie@google.com>
    (cherry picked from commit c59865ac464af308baedcd69aa662f46ff3a04d3)
    
    Change-Id: Ie6f3a8179376bc97a6d22712dd965f5e0e6ec5d6
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/167313
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit b31d7a31b838e67a4b7f33119a3baea049d30a36)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6518
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 3bb40b93f857256c8eafe9529de0e572522f71f0
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Sep 16 14:22:57 2013 -0700

    chromeec: Implement full battery workaround at 6%
    
    Currently the workaround for indicating a "full" battery kicks
    in at 3%, but this turns out to be too high for some devices.
    So move the workaround start point to 6% from full, or 94%.
    
    Change-Id: Ib4305df3a68e89f3a10a096d0e89d8105ea9037b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/169549
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 982dc496a0553c90dee56fda6411b7c21a5d7da9)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6521
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5b10fc5242191428ecec8b7c5b9068100d95f889
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 21 14:37:36 2013 -0700

    Pit: remove backlight delay
    
    Change-Id: Ia2e5427fec1bfff9babb9c59a3878323277f4f4c
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66555
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 2b96235123d55db3ff5ae5c2454b65de831a1c18)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6524
    Tested-by: build bot (Jenkins)

commit 45d2ff317c0c077e6f83602a81bc915aa195d3f7
Author: Julius Werner <jwerner@chromium.org>
Date:   Mon Aug 12 18:04:06 2013 -0700

    exynos5420: Implement support to boot with USB A-A firmware upload
    
    This patch ports the USB A-A firmware upload functionality from
    exynos5250 over to exynos5420. Essentially just like a conflictless
    cherry-pick of 9e69421f5f0eebf88c09913dee90082feab2856c. It also fixes
    the exact same bug with SPI initialization for Pit and Kirby.
    
    Old-Change-Id: Ief0ed54c0beb2701e51201041f9bc426b2167747
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65751
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 5dff43f929478f83939221df13b961a69f89b132)
    
    exynos5: Fix trivial style nits
    
    A few curly braces on the wrong line.
    
    Old-Change-Id: I4ddac4476c6509dc1716e8c1915fbdb67d346786
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66153
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit 41e3fd9eaafe36433723f4e96a6d94c04e5fbafb)
    
    Squashed two related commits.
    
    Change-Id: I22d579693b5e7270aacb45bbe3557e40893dd1f8
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6500
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 782ac36cfac8be208f0d1221f6586375e1b8c574
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Aug 8 00:00:20 2014 +0200

    lenovo/x230: Enable wake on LID and Fn key.
    
    Change-Id: Ifc7208400b0bdfa2b9b70773bd24e9f9df7f8048
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6526
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 91810ddf798be6067dd4a42dd4c708573645987d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 30 13:53:04 2014 +1000

    device/oprom/realmode: Sanitize header inclusion
    
    Alphabetise includes to avoid duplication.
    
    Change-Id: I7fa6998cd736bad2bab4a6b1a65d48a21d6220d9
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6415
    Tested-by: build bot (Jenkins)
    Reviewed-by: Isaac Christensen <isaac.christensen@se-eng.com>

commit 62997e0981dddd1ef6b2841fbaee204ed88b9733
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Aug 23 11:22:42 2013 -0700

    ARMV7: threading support for cooperative multitasking
    
    These functions add support for cooperative multitasking.
    Currently, since we only have one ARM SOC that uses or supports multitasking,
    arch_get_thread_stackbase returns CONFIG_STACK_BOTTOM for the thread stack.
    We may end up having to make a cpu-specific function that arch_get_thread_stackbase calls,
    but let's avoid adding complexity until we're sure we need to. We also wish to avoid
    creating Yet Another Config Variable but will do so if pressed.
    
    The switch code only saves r4-r11 and lr, which is consistent with the standard.
    
    Change-Id: I0338a9c11127351e1f3a190bc51a7a558420b141
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66845
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit 22b62af3c26b6b504498b434d29a56a8932f3061)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6517
    Tested-by: build bot (Jenkins)

commit ad4afe9b043bd2ab9482c677f29c6d74e250d5e2
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Aug 28 12:39:11 2013 -0700

    armv7: Fix dcache writethrough policy handling
    
    The "bufferable" bit was erroneously set for the writethrough policy
    making it the same as writeback.
    
    (credit to jwerner for pointing this out)
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I567d57f0e522cb4b82988894ba9b4638642bf8db
    Reviewed-on: https://chromium-review.googlesource.com/167323
    Reviewed-by: Julius Werner <jwerner@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: ron minnich <rminnich@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 36cf13839604c349692865475f3011afd08965b4)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6515
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 71e1c8303b1c5e805f32eda5a8b5a18f9f354399
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 27 14:06:19 2013 -0700

    Exynos 5420: skip the EDID read if there is already an EDID.
    
    For many boards, the EDID is known and is set in the ramstage. Reading
    the EDID is slow and if we have it we do not want to reread it.
    
    If the raw_edid struct member is non-null, skip reading the EDID.
    
    Change-Id: I63fb11aa90b2f739a351cdc3209faac2713ea451
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: https://chromium-review.googlesource.com/167116
    Reviewed-by: Gabe Black <gabeblack@google.com>
    Tested-by: ron minnich <rminnich@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@google.com>
    (cherry picked from commit 80f48655570de544a7e1939c4f5f28713f11d829)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6514
    Tested-by: build bot (Jenkins)

commit 34352d16a96b8096094274dddae98e37939857b9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 21 16:03:32 2013 -0700

    Possible thread stack implementation.
    
    Architecture provides a function for thread stack base, thread code uses it.
    Build and boot tested on Falco with multitasking on and off.
    
    Change-Id: I5016fab47f9954379acf7702ac7965b0a70c88ed
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66578
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit 3c6afef30c1a0ad6fba0fb76acc792184d924247)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6513
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 0ffa11bdbba48defc55cd38fb2aa2492ca2b5492
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 22 16:52:38 2013 -0700

    exynos5420: Set the CLK_DIV_CPERI1 value as per manual
    
    Set the CLK_DIV_CPERI1 value as recommended by the
    0.02 UM section 7.9.1.25.
    This suggests to use 0x3F3F0000 as the value to be
    set to save power.
    
    This is ported from https://gerrit.chromium.org/gerrit/#/c/64905
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I89a6a72d20374a513019a272628a05e139b31773
    Reviewed-on: https://gerrit.chromium.org/gerrit/66787
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit 34be13b008e262c641268b7c1c6a08e49f18fc37)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6512
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ee4bfbf3e142b17bf263f5ddb3840ed683a04635
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Aug 13 21:05:43 2013 -0700

    exynos: Set up caching in the bootblock.
    
    This improves firmware boot time substantially. Because cbmem isn't available
    yet, we need to allocate some space in sram for the ttb. Doing cache
    initialization in the bootblock means we can implement this once per CPU
    instead of once per mainboard.
    
    Old-Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65938
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit c32b9b32ad933e627b9ea98434b392239b1fea73)
    
    exynos5420: flush caches and disable MMU in resume path
    
    This patch flushes the caches and disables the MMU before resuming.
    
    c32b9b3 ("Set up caching in the bootblock.") had a bug where the
    dcache and MMU remained enabled in the resume path. This caused
    the machine to hang on resume. However, other bugs were preventing
    us from testing this properly earlier on so it went unnoticed until
    now.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: Ib1774f09d286a4d659da9fc2dad1d7a6fc1ebe5e
    Reviewed-on: https://chromium-review.googlesource.com/67007
    Reviewed-by: ron minnich <rminnich@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 4fdf9763d25f70fd1e3591f6ff9785f78dd6170d)
    
    Squashed two related commits.
    
    Change-Id: Ibd42b28bb06930159248130e5ceaddb3b4b6cc2a
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6511
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit e10ef42a55705530f54e1f04bc25b21aeda5693a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Aug 18 20:01:07 2013 -0700

    Exynos5420: invoke the cooperative threading in udelay
    
    Call thread_yield_microseconds in udelay. This works with and without
    COOP_MULTITASKING enabled.
    
    Change-Id: Ib3eab00d1630dc4daada850e7458ab89702d1864
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66327
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit 12e55ba8a68e5d40e08ad169848bdf274887ce0b)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6510
    Tested-by: build bot (Jenkins)

commit ca63027ef7627ba60f6776f2c9bd373cdb2afbb0
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Aug 5 10:48:20 2014 -0500

    cbfstool: process cbfs_payload_segment(s) in host byte order
    
    The printing routines of the cbfs_payload_segment assumed the type
    could be accessed in host order. Each of the fields need to be
    converted to the host order before inspecting the fields. In addition,
    this removes all the ntoh*() calls while processing the
    cbfs_payload_segment structures.
    
    cbfstool would crash adding entries or just printing entries
    containing a payload when -v was passed on the command line.
    
    Change-Id: Iff41c64a99001b9e3920e2e26828c5fd6e671239
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6498
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 4acd8ea778388392475ee14cb5efe5f453da3159
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Wed Aug 21 05:21:21 2013 -0600

    slippy/flaco/peppy: setup beep verbs
    
    Add verb setting for beep during recovery and dev mode.
    Requires depthcharge CL.
    
    Change-Id: I13cbb4e889ebc4c27bb4ab9fa49601b03e872d09
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66519
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Dylan Reid <dgreid@chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
    (cherry picked from commit c072543946b317192a8e80a744c1515deb414456)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6502
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 61fcd14561b226c4cca32148629c4ed42db9f645
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Aug 14 17:14:39 2013 -0700

    Exynos5: Remove unneeded USB delays
    
    Change-Id: I1144e9d6d6c4278842fdd36743c8a88555f81707
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65912
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    (cherry picked from commit 95b518877edc88347ce9725ffee32f3aed0de7dc)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6505
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit bc6cc112e2a4a2474c8ce946faea24980732762a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Aug 16 19:53:41 2013 -0700

    Exynos5420: tighten up display port delays
    
    Shorten a few delays, and make some delays shorter but let the
    loops have a higher termination count (i.e. give it the same
    amount of time to warm up, but check more frequently).
    
    Change-Id: Id9fe846ae3a8d792b14d62aea4e98d8aad05be43
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66156
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit a112e77f2f21f41f982ca22bebdac213cc8d233a)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6506
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f2c4241b810665bbeb5f9e2f8c00cb2d0d4e6622
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Aug 22 23:56:35 2013 +0800

    exynos5420: Fix mmc clock source.
    
    The DWMMC controller internally divided clock by values in CLKSEL registers,
    so we must adjust MMC clock for that.
    
    Change-Id: I44f55b634cfc6fd81d76631595b6928c862a219f
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66657
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 89ed6c9154f16c6b8d01af03c0b78914773eb469)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6504
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit d6b16f54b9c34a8095a3eefbaf334150c15cecb5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Aug 16 15:57:56 2013 -0700

    Set armv7 up for cpu_info to work as on x86 (so threads can work)
    
    On x86, cpu_info lives at the top of stack. Make the arm do that as
    well, as the threading model needs that and so will multicore support.
    
    As part of this change, make the stack size a power of 2.
    Also make it much smaller -- 2048 bytes is PLENTY for ram stage.
    
    Note that the small stack size is counterintuitive for rom stage.  How
    can this work in rom stage, which needs a HUGE stack for lzma? The
    main use of STACK_SIZE has always been in ram stage; since 2002 or so
    it was to size per-core stacks (see, e.g.,
    
    src/arch/x86/lib/c_start.S:.space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE
    
    and, more recently, thread stacks. So, we define the STACK_TOP for rom
    and ram stage, but the STACK_SIZE has no real effect on the ROM stage
    (no hardware red zones on the stack) and hence we're ok with actually
    defining the "wrong" stack size. In fact, the coreboot_ram ldscript
    for armv7 sizes the stack by subtracting CONFIG_STACK_BOTTOM from
    CONFIG_STACK_TOP, so we replicate that arithmetic in bootblock.inc
    
    Observed stack usage in ramstage:
    BS: BS_PAYLOAD_LOAD times (us): entry 1 run 153887 exit 1
    Jumping to boot code at 23104044
    CPU0: stack: 02072800 - 02073000, lowest used address 020728d4, stack used: 1836 bytes
    entry    = 23104044
    
    Which means we do need 2K, not 1K.
    
    Change-Id: I1a21db87081597efe463095bfd33c89eba1d569f
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66135
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit f011097e9f2bfb2f4c1109d465be89a79a65ba3e)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6501
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 7111835f3900aaf2e1a23a62029daa668963fbe1
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 3 14:55:14 2014 +0200

    lenovo/x201: Enable pcie lanes in wwan slot.
    
    Change-Id: I7332eeed244877252074e661f1c256a69a9b428a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6482
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1c07c2205e0513e0570597ae793425820ae0844a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 19:50:52 2014 +1000

    mainboard/amd: De-ASCIIartify AGESA board headers
    
    As was done for the reference boards in:
    
    cd30951 mainboard/amd: De-ASCIIartify reference boards
    
    Change-Id: Ie34aa5269388b771daa6934f8aff0314ac6778d5
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6290
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 70d4b5261e0667640ed9e137791388aa5c732a8e
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Tue Aug 5 10:20:59 2014 -0600

    gizmosphere/gizmo: Change the PCIe GPP to two x1 ports
    
    Gizmo sends two southbridge GPP PCIe lanes to its high speed
    edge connector. This change will allow developers to create
    two x1 slots on an extender card.
    
    Change-Id: Iba6c1a4caf7846d12e3960775d7bc906ca8ff385
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6499
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 5103cc3d531b3adf45a7ed70d0d05caa6b43335a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jul 29 20:49:55 2014 +1000

    lenovo/t530/mainboard.c: Include header `h8.h` for prototype
    
    Change-Id: I05cea020e77051bd3bc0e93b0c70e12b9b985d05
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6398
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 396b0722978f9254a3d012210a89ccdead23a916
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Sep 26 16:22:09 2013 -0700

    tegra124: Add a stub implementation of the tegra124 SOC.
    
    Most things still needs to be filled in, but this will allow us to build
    boards which use this SOC.
    
    Change-Id: Ic790685a78193ccb223f4d9355bd3db57812af39
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/170836
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 462456fd00164c10c80eff72240226a04445fe60)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6431
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 1ee2c6dbdfe7e35ab5e25a6136eab824ed2fec8f
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Aug 9 04:27:35 2013 -0700

    libpayload: Change CONFIG_* to CONFIG_LP_* in the kconfig.
    
    When libpayload header files are included in the payload itself, it's possible
    that the payloads config settings will conflict with the ones in libpayload.
    It's also possible for the libpayload config settings to conflict with the
    payloads. To avoid that, the libpayload config settings have _LP_ (for
    libpayload) added to them. The symbols themselves as defined in the Config.in files
    are still the same, but the prefix added to them is now CONFIG_LP_ instead of just
    CONFIG_.
    
    Change-Id: Ib8a46d202e7880afdeac7924d69a949bfbcc5f97
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65303
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 23e866da20862cace0ed2a67d6fb74056bc9ea9a)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6427
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit b77431336e44ba9721f18220e2a7dedafe250528
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Aug 9 18:19:29 2013 -0700

    exynos5420: get rid of old exynos5420_config_l2_cache()
    
    We set up L2 cache early in romstage now so the old
    function is now redundant.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: Icec93810ddd7feb48286d4b600cb2d58af38b7ef
    Reviewed-on: https://gerrit.chromium.org/gerrit/65428
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit bb91f1078ea55a7c8bdc19336cef2ec9a5f4511f)
    
    exynos: stack size: Increase the stack size to 16KB.
    
    The lzma decoding function in the RAM stage allocates nearly 16KB on the stack
    which is shared between the bootblock, rom stage, and ram stage. The stack had
    been much too small and needed to be expanded.
    
    Old-Change-Id: I1b74fff9b54e506320d58956b779b3a102e66868
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65937
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 243d8a80f68dd257ecc5b4e19614bc7f0f5d398b)
    
    exynos: gpio: add a bigger delay when reading board strappings
    
    Z-state pins were not reading reliably with a 5us delay, so increase
    it to 15us.
    
    This is ported from https://gerrit.chromium.org/gerrit/64338
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: Ife6ea2ef5989e1a4c17913278ab972f0fd7f7f35
    Reviewed-on: https://gerrit.chromium.org/gerrit/65727
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 76f0f8203f1af3f461745cefcc94e97c422d9084)
    
    exynos5420: enable DMC internal clock gating
    
    lets enable memory controller internal clock gating for ddr3.
    with these bits enabled we save some power out of ddr3.
    
    This is ported from https://gerrit.chromium.org/gerrit/#/c/60774
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f
    Reviewed-on: https://gerrit.chromium.org/gerrit/65728
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 022a81c44e655a9f81e974e730c0cecc1f048781)
    
    exynos5420: Correct the 600MHz PMS value
    
    In UM ver0.02, 600MHz clock PMS values differs from what is programed
    currently. Though this also results in 600MHz clock, but it is better to
    match what UM says. This patch chnage this as per UM
    
    This is ported from https://gerrit.chromium.org/gerrit/#/c/65106/3
    (Note: we already used the correct 600MHz value for KPLL)
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: I6786815ab33427a23436e6ee37295f6c37dcd3d5
    Reviewed-on: https://gerrit.chromium.org/gerrit/65726
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit ceabf57ca78449fa6e9cfd212bdf4774706de92f)
    
    Squashed five commits pertaining to  exynos.
    
    Change-Id: I3fd894aed15b8cd161c30904a46dac7e07eb8992
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6425
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 18fe07ed22e81c6315c199d5ae71b689163bac46
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Aug 4 09:58:30 2014 +1000

    northbridge/via/vx800: Fix out-of-bounds read due to off-by-one
    
    Change-Id: Ia7fda59b60b2148dd4d246686bd94d2334b23eb5
    Found-by: Coverity Scan
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6485
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 68a97164d3627bf277a7a5962e8006d163d40429
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Thu Jul 31 10:39:57 2014 +0200

    lenovo/t520/mainboard.c: Include header `h8.h` for prototype
    
    Change-Id: I5ac6608ebf78f2d48bc7f68bce9eae7a2be82332
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6424
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 650b00c1bf9811f502a6da025a5c1d5f4b4b16b5
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Wed Aug 21 11:47:11 2013 -0700

    peppy: Force enable ASPM on PCIe Root Port 1
    
    (Clone of Falco change Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8)
    
    Old-Change-Id: I5feba8fdbafba6d2de9f7d3de6170defc0d45a32
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66536
    Reviewed-by: Dave Parker <dparker@chromium.org>
    (cherry picked from commit b78a872a6647d7bb82f6c06a75e4075e451a1622)
    
    peppy: Disable unused clocks
    
    CLKOUT for PCIE ports 2-5 and CLKOUT_XDP are not used
    and can be disabled.
    
    This change was modled after the change made in Falco:
    Falco-Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b
    
    The only difference per schematic for Peppy was PCIe 1 supports
    a NGFF interface. PCIe 0 is connected to WLAN.
    
    Old-Change-Id: Ib4871cb2655316cb260ab33ada6b9d81f271377f
    Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66693
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    (cherry picked from commit 8f12335013a510dee3c21b55251ab00c0fbac609)
    
    Squashed two related commits.
    
    Change-Id: Ibc5b902018eec07fdccaa8c6cb066ce918f6a6b5
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6419
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 6fa6843a8d3ba9576a331c57818a5ecbe08a0f45
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 3 15:27:35 2014 +0200

    sconfig: improve argument parsing
    
    Running sconfig with four arguments where the third
    does not match /-./ made sconfig use uninitialized
    memory to build the output filename.
    
    Change-Id: If4a147ff23771ca9b6a913605af60249be1ca3d0
    Found-By: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6483
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 80fd01d2cc44a7a4077b5df25d5d09917e5ae04a
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Aug 4 08:25:05 2014 +0200

    util/sconfig/main.c: Remove assigned but unused variable `link`
    
    Cppcheck 1.65 report the style style issue below.
    
    	[main.c:434]: (style) Variable 'link' is assigned a value that is never used.
    
    So remove the variable `link` as it is not needed.
    
    Change-Id: Ib77b80b74a70985a76eaa3247c4a43832ef23a59
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6488
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 2b48b65b1980c4edb6391e4ccf6b1bd8313be944
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Aug 3 23:38:17 2014 +1000

    northbridge/intel: Out of bounds write to array in gma.h
    
    The signature[] array in the mailbox struct opregion_header_t has
    IGD_OPREGION_SIGNATURE written to it with a
    sizeof(IGD_OPREGION_SIGNATURE) and not a sizeof(signature[]). This
    resulted in a silent off-by-one out of bounds illegal write.
    
    Change-Id: I651620a753c743dd2ed2af51c012c27c14a5ea25
    Found-by: Coverity Scan
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6473
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5cfef13f8d13b378f72b61ba3e4d7eee065f6d26
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Aug 3 20:00:47 2014 +1000

    cpu/intel: Fix out-of-bounds read due to off-by-one in condition
    
    If power_limit_1_time > 129 is false then power_limit_1_time can have a
    value of up to 129 leading to an out-of-bounds illegal read indexing the
    power_limit_time_sec_to_msr[] array. Thankfully all call sites have been
    doing the right thing up until now so the issue has not been visible.
    
    Change-Id: Ic029d1af7fe43ca7da271043c2b08fe3088714af
    Found-by: Coverity Scan
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6478
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 18d9899be13ac518cfe65ed326df0b333a58eabf
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Aug 28 09:54:04 2013 -0700

    chrome ec: Add Methods for new EC events
    
    The EC recently added events for Thermal and Battery shutdown
    to provide some sort of notification to the OS that it is
    about to pull power.
    
    Original-Change-Id: Ibbdb5f11b8fa9fc80612a3cc10667c612420b1bb
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/167301
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie@google.com>
    (cherry picked from commit 03a53ed5e58caa018d49df193510d95bdf5bed7b)
    
    Change-Id: I0cdf89a60b541840029db58d49921340e7ab60eb
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/167314
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 16d00848f48da83f6d6c813137a35af45bb05c4b)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6458
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit cc6b924042a0ca1c2d46e05dbb98c15fd2730d47
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Aug 26 08:33:56 2013 -0700

    falco: Re-read critical temperatures in ACPI _TMP
    
    There seem to be a significant number of shutdowns during suspend resume
    tests related to critical temperatures.  It is possible that we are getting
    a bad reading from PECI and shutting down prematurely in some cases.
    
    If we get a reading that is above critical then wait for the EC to re-poll
    and then re-check the temperature in case it was just a bad reading.
    
    Also add some ACPI debug messages when this happens.
    
    Original-Change-Id: I0ab7bdcc50d133981c0f36fc696b06d4a1d939a7
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66937
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    
    (cherry picked from commit a39d7b11dd7b2af37fc2658542d56b32e3966ed4)
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    
    Change-Id: Ib612266511d90749ec6507f8467c71523ee8fb95
    Reviewed-on: https://chromium-review.googlesource.com/66939
    Tested-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
    (cherry picked from commit e98da983dca7819490464bddf08b9c53f28d2712)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6457
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 1f68880e50a2b847838bbdc6916484f9fd86a681
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 3 15:51:19 2014 +0200

    sconfig: more careful string resource handling
    
    When parsing a string to numbers, we don't need to copy it.
    And when creating strings, we should eventually free them.
    
    Change-Id: I9023fef6e97a1830bc68502be32e79879c1617d4
    Found-By: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6484
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 55391c422f8c45e40bb014d238769501aed65d56
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 3 14:51:00 2014 +0200

    nehalem: Make UMA size configurable in CMOS.
    
    All modes tested on X201.
    
    Change-Id: I23df81523196ea3f5fdb10eb04f4496c00aaeb9f
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6481
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 63e1948643fcbd763c83b6baa6cd9a077d49f1fc
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 3 12:41:29 2014 +0200

    intel/fsp_bd82x6x: Fix cycle error
    
    Some copy-pasta snuck in that reintroduced an error
    already fixed in #3435 (62f8083dfdf0c5e0046efe297b2bf88474928071)
    
    Change-Id: I47db23e88fa09c73b4cf3e99fe2d0ed2ac30fd80
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6479
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 38fa6edf2db155383e04bf8427377b7b684cede3
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 3 12:18:45 2014 +0200

    ifdtool: Check if file was opened
    
    Check if the new file could in fact be opened before
    writing to it.
    
    Change-Id: I6b2d31bf5c18f657fca4dc14fee2f2d5a2e33080
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6477
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 440daf786a85f8c1f4959c519811e3d6e10586bc
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 3 12:14:25 2014 +0200

    ifdtool: Avoid potential buffer overflow
    
    Filenames of 4091 bytes or more lead to a buffer overflow.
    
    Change-Id: I1b4b3932af096f0fcbfb783ab708ed273d3a844e
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6476
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit edb0a61be4030cc6bdc605332204bb27c9f1b98f
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Aug 3 12:10:53 2014 +0200

    nvramtool: Close file after use
    
    mmap builds a new reference to the file, so the file
    descriptor isn't necessary anymore. Close it.
    
    Change-Id: I639fd13ff8f13cbdfce1d199d75744e56f2b19b3
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6475
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 5fc04d1fdd2d4c763ba39c3d90e487e9f773b122
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Aug 3 01:59:38 2014 +0200

    sandy/ivybridge: Make UMA size configurable.
    
    Change-Id: I9aa3652d1b92cece01d024e19bdc065797896001
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6470
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 96639fb7db099dbaad4e70dd5179cd6f2f636b57
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sat Aug 2 13:45:17 2014 +0200

    arch/x86/Makefile.inc: trivial: fix indent of informative output about bootblock
    
    Fixes the 4th line of this sequence:
        ROMCC      generated/bootblock.inc
        GEN        generated/bootblock_inc.S
        CC         generated/bootblock.s
        CC        generated/bootblock.o
        GEN        generated/bootblock.ld
    
    Change-Id: Ic0704b83ec9c4191e26a94e0d69cbf4c0486ceed
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6466
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 9faacba66b9a96398feaecaa14e99fe4a62876e0
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sat Aug 2 20:55:09 2014 +0200

    cpu/x86/lapic/lapic.c: trivial: fix comment on #else
    
    The preprocessor symbol has only one "L".
    
    Change-Id: I3ec302f18d3bcc81bb45a9d53140f8aedd019317
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6469
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit b98ab4a893798a5bda9d143943f6930ffaae2b68
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Aug 16 12:17:50 2013 -0700

    armv7: add wrapper for DCCSW (data cache clean by set/way)
    
    This adds a wrapper for data cache clean (without invalidate)
    by set/way.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: I09ee1563890350a6c1d04f1b96ac5d0c042e2af2
    Reviewed-on: https://gerrit.chromium.org/gerrit/66118
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit 05bc4f8564c547eacb9cc840a03b916b3c1c6001)
    
    armv7: clean but do not invalidate caches between stages
    
    This cleans the caches without invalidating them between stages. The
    dcache content should still be valid when the next stage begins, so
    we should see a small performance gain.
    
    (thanks to gabeblack for pointing this out)
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: Ie18d163f3a78e2786e9fbc7479c8bd896b8ac3aa
    Reviewed-on: https://gerrit.chromium.org/gerrit/66119
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit 619bfe4cf9b93847e38d03d7076beb78fbfa1d1d)
    
    armv7: Make coreboot and libpayload cache files the same
    
    This merges the difference between the ARM version of cache.c and
    cache.h for libpayload and coreboot.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Old-Change-Id: I246d2ec98385100304266f4bb15337a8fcf8df93
    Reviewed-on: https://gerrit.chromium.org/gerrit/66120
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit 0c92f694034f1e94a8aa7811251738c9dc3db2c6)
    
    ARM: Fix cache cleaning operation.
    
    There was no behavior defined for OP_DCCSW in dcache_op_set_way, so it
    silently did nothing. Since we started using that to clean the cache between
    stages and I have a change that enables caches earlier on, this was preventing
    booting on pit.
    
    Old-Change-Id: I3615b6569bf8de195d19d26b62f02932322b7601
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66234
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 99241468cb9dcc86fcca9266ffe72baa88a1f79f)
    
    libpayload: Fix data cache cleaning on ARM.
    
    A similar fix was made to coreboot where OP_DCCSW was silently not doing
    anything in dcache_op_set_way.
    
    Old-Change-Id: Ia0798aef0cd02da7d1a14b7affa05038a002ab3b
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66236
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 6f6596a182a6780a2e997ac320733722697990c5)
    
    Squashed five related commits.
    
    Change-Id: I763d42bd5dd9f58734e1e21eb7c8ce3ce2ea56ee
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6418
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit caf1df0278ef743274b7811e0b4bfb58c122ce4e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Aug 1 02:49:27 2014 +0200

    i82801ix: Provide ramstage smbus functions.
    
    Change-Id: Idc62e382a4002274abe6c23d76fe0874c62846c5
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6433
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 2c3f94454dd29532569fd80f954e6289e7ee2fda
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jul 31 17:56:51 2014 +1000

    vendorcode/intel/fsp/rangeley/include: Missing 'fsptypes.h'
    
    Without the inclusion of 'fsptypes.h' the order of inclusion becomes
    tentative.
    
    Change-Id: I6360e4ebac6c414c380a19ef69d39d658ea203bd
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6423
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit aaaef061792f7904d75f401e1de376311d6cdd0b
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Jul 28 14:20:58 2014 -0600

    fsp_baytrail/.../gpio.h: Add GPIO_NC1 for GPIOS on func 1
    
    The GPIO_NC setting sets up the gpio as a no-connect - sets it as an
    input, and pulls it high.  It makes an assumption that the GPIO
    function is muxing function 0.  There are a few GPIOs that are on
    function 1 instead:
    * GPIO_S0_SC[092-93]
    * GPIO_S5[11-21]
    For these GPIOs, use the GPIO_NC1 setting instead of GPIO_NC.
    
    Change-Id: Iac6790b40e87ad4ac9a3b265a8e10662186c1201
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6428
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 0d7f133c38673af2dae06988d418606d7f5628ac
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Fri Jul 25 14:33:49 2014 -0600

    payloads/external/SeaBIOS: Use coreboot’s serial console settings
    
    Set up the serial console on SeaBIOS to match coreboot's settings.
    Previously, we were just forcing it on, and setting it to 0x3f8.
    
    Change-Id: I107245c8bd1ba2cf948c6671337c6169226aaaaf
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6363
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 97804520bdf63816a71663824b8c514f949a0225
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Fri Jul 25 14:24:32 2014 -0600

    payloads/external/SeaBIOS: Update makefile for olddefconfig
    
    Instead of creating the SeaBIOS .config file for QEMU, then changing
    things to be coreboot specific, create a default config for coreboot,
    then run olddefconfig to use the SeaBIOS defaults as they're set for
    coreboot.  This leads to a cleaner config.
    
    Note that CONFIG_THREAD_OPTIONROMS defaults to enabled for SeaBIOS if
    we're building for coreboot, so I reversed the logic.
    
    I *ASSUMED* that leaving CONFIG_QEMU_HARDWARE=y and CONFIG_DEBUG_IO=y
    previously was an oversight.  If this is not correct, please let me
    know and I'll add them it back in.  SeaBIOS disables these by default
    if building for coreboot.
    
    Change-Id: I42c6a56205bb15c6693a5f3a716b7876a4d78abe
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6362
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 6ccc45d7d57056c2b9f172859894739d94cc723e
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Aug 9 00:48:06 2013 -0700

    timer: Add functions to initialize absolute timer structures.
    
    Otherwise there's no good way to create an absolute timer structure without
    fiddling with its internal structure or assuming a zero initialized structure
    has a value of zero.
    
    Old-Change-Id: Iffe3b6b25ed7963fcfb66f749c531ea445ea4aeb
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65301
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit e2e5c1ef3bb2df95fdf0e33cb2d975a990d07a4a)
    
    exynos: Simplify the monotonic timer implementation.
    
    The previous implementation was overly complicated, and when used in the
    timestamp implementation produced some weird and broken results.
    
    Old-Change-Id: I3048028ddea0657b01b0c94f312764b38d1397e4
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65302
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    (cherry picked from commit 6a3fde9a5b80cdac76d79c65d20d7dd1f1d9e557)
    
    Squashed two closely related commits.
    
    Change-Id: Ifc32d773f4f93d34275a81781001d080357fe8ef
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6406
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 82683ab9d4435d46d4d61cf58de32d405cbda84f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue May 28 09:25:32 2013 -0500

    libpayload: provide missing cbfs symbol
    
    The generic cbfs code relies on the libpayload_init_default_cbfs_media
    symbol. However, none was provided for ARM. Provide an empty
    implementation that returns an error as there is no generic way
    to locate the default cbfs media.
    
    Old-Change-Id: Ie0d06fbe6fc790c9d92434cd2d60922908acdc69
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56805
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    (cherry picked from commit d3410c28ef9f37b832e2fa2d18351dda332bc9f7)
    
    libpayload: place dummy_media.c in correct object list
    
    The commit introducing dummy_media.c was placed in the
    libc object list. This wasn't correct. It should be in the
    libcbfs object list as well as guarded by CONFIG_CBFS.
    
    Old-Change-Id: Iace43fff8f85f60ecac5e6eb8350cd1f3ee9d35e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56925
    (cherry picked from commit 7937c7c5e95a934593bc0cedd5f4496b4770c303)
    
    Squashed two related commits.
    
    Change-Id: I84cd132b44cc2ea5b29acf109a3562baaeede9c6
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6411
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 0682cfefdb888807bef6ee7f3bb81615282e0390
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Aug 6 20:37:55 2013 +0800

    armv7/exynos5420: Configure CPU cores for kernel to enable SMP.
    
    The SMP on Exynos 5420 requires setting a special page and entry wrappers in
    firmware side (SRAM) so kernel can start cores (and to switch clusters).
    
    Change-Id: I77ca98bb6cff5b13e95dd29228e4536302f0aee9
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64770
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    (cherry picked from commit 4a11c7ab78cc0811df0f88763b0af8b9f24e5433)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6405
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit c3fda416a7e71eae4803c07f0fae4b0b931d1ca8
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 30 02:19:25 2014 +1000

    northbridge/amd/agesa/agesawrapper_call.h: Decode status codes
    
    Decode obscure AGESA status codes into their respective string forms.
    
    Change-Id: Iccf175ef62e5005af6ebbfb1bd0acec8aedc2eaa
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6402
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit 7842eb29972e8665da723566a2395e41621aedac
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jul 29 22:28:19 2014 +1000

    device/oprom/realmode/x86.c: Move includes to top of file
    
    Change-Id: Ib68e1f570092a69447d307c33b98f70b817f0ec1
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6401
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 51ca10f54837c0e6f08561c6f85dd0d766622a82
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jul 29 22:27:51 2014 +1000

    arch/x86/include/arch/interrupt.h: Add header guards
    
    Change-Id: I34c27bbce3ce958a33d547c727d9733d3b2d1670
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6400
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 370adeedb455a0d3880637ddfc3b8afee6080b5c
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 30 11:44:29 2014 +1000

    model_206ax_init.c: Trivial - fix indent
    
    Change-Id: I84876c95522fca5560bcbc8e81dfcb09faf3b326
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6412
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit d11ff6b9dfae82266fd9862421e395f6d9c436dc
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Jul 10 20:38:21 2014 +0200

    build system: remove duplicate architecture list
    
    Let xcompile pass the list of architectures, given
    that it already has it.
    
    Change-Id: I565512d3bef987c9a4e48a39bfd88bacf0b65de9
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6254
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit ad488d25b03c9abebe8187843f8d1301d242f106
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Wed Jul 30 12:23:35 2014 +0200

    src/console/Kconfig: Fix choice for showing POST codes on console
    
    Use CONSOLE_POST because the preprocessor conditional in post_code()
    in src/console/post.c depends on it, while POST_IO is used in another
    conditional for sending the codes to an I/O port.
    
    Change-Id: Ia044cffb5f0aad0f8b2bb04faa12df11a705757a
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6416
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 90957f885294527ff9342f56d2e07c5a23fb1ce2
Author: Martin Roth <gaumless@gmail.com>
Date:   Wed May 21 14:23:12 2014 -0600

    mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000
    
    Add the Mohon Peak CRB.
    
    Updates to come.
    
    Change-Id: I0a8496d502bab905c6f35eff9fcd7eda266831ed
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/6371
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 829c41da6cd9d8e9c9244c8c9ea2b181ea5ab930
Author: Martin Roth <gaumless@gmail.com>
Date:   Wed May 21 14:21:22 2014 -0600

    southbridge/intel: Add fsp_rangeley support
    
    This adds the southbridge initialization pieces for Intel's Atom C2000
    processor (formerly Rangeley).  It is intended to be used with the Intel
    Atom C2000 FSP and does not contain all of the pieces that would
    otherwise be required for initialization.
    
    Change-Id: I416e85bd6e9c9dcf79f97785074135902fdd18b7
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/6370
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 2963ae7fd49c7086ca9c4231f00a94e2f8a33080
Author: Martin Roth <gaumless@gmail.com>
Date:   Wed May 21 14:20:38 2014 -0600

    northbridge/intel: Add fsp_rangeley northbridge support
    
    This adds the northbridge initialization pieces for Intel's Atom C2000
    processor (Formerly Rangeley).  It is intended to be used with the Intel
    Atom C2000 FSP and does not contain all of the pieces that would
    otherwise be required for initialization.
    
    Not currently supported:
    S3 suspend/resume
    CAR memory Migration (No early cbmem console)
    SMM
    
    Change-Id: I7665212c892d9a08ecf35d7be70d0afe5fd2c77b
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/6369
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 09670265b63184f92d78fc8fe5311f3662cc528a
Author: Martin Roth <gaumless@gmail.com>
Date:   Wed May 21 13:40:21 2014 -0600

    cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)
    
    This adds the CPU initialization pieces for Intel's Atom C2000 processor
    (Formerly Rangeley).
    
    Change-Id: I77d69f42c959bbc294784f044b7b0dcc2e30f30c
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/6368
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ddf54b1c8b2ef6e8e3d2a673e0dd1ab43c7edc2c
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sun Jul 27 11:02:15 2014 +0200

    util/sconfig: fix check for count of command line arguments
    
    Valid invocations are when -s|b|k outputfile is missing (argc == 3)
    and when it is followed by the file name (argc == 5); it's an error
    when "outputfile" is missing (argc == 4) or when there are more
    arguments than expected (argc > 5).
    Fixes "Uninitialized argument value" error found by scan-build from
    clang version 3.2-11.
    
    Change-Id: I8c489863323eb60cbaa5e82a80f5d78a6ca893c2
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6378
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 201093ef6d24de27bc491947b9ab31d22f0aca8f
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sun Jul 27 18:45:30 2014 +0200

    util/i915tool: close the file also when fread() returned an error
    
    Change-Id: I92f816aa1351a295287ebbcc78665ac87c318c23
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6386
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 06b13a37f0f4b3545b899e3488762b3ed9c20812
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Aug 9 00:40:06 2013 -0700

    cbmem: Terminate the cbmem console at the cursor position.
    
    If the cbmem console buffer isn't zero filled before it's used, there won't be
    a terminator at the end. We need to put one at the cursor position manually.
    
    Change-Id: I69870c2b24b67ce3cbcd402b62f3574acb4c2a8f
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65300
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    (cherry picked from commit 8ec61e52a6a27ed518d0abb5a19d6261edf9dab1)
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6404
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 0dd5e4395e805e3d54b31f3eaf8b432af5bad5e2
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Jul 29 22:35:45 2014 +0200

    i82801ix: Allow configuration of SATA mode in CMOS.
    
    Change-Id: Ice0f0273b16a946143c038a90b61978269c1c56e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6409
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 8e89847af41656f82226e755f03fdcc178d3ef78
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sun Jul 27 12:01:40 2014 +0200

    util/cbfstool: free buffer on error path
    
    Fix memory leak found by scan-build from clang version 3.2-11.
    
    Change-Id: Id8f9db46cf42012a0eb0a632c9d83a4eec1989a2
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6379
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit b532b12b411d315b7799fc00a987bf21deb7e8a3
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sat Jul 26 10:32:34 2014 +0200

    model_fxx/processor_name.c, hudson/lpc.c: add missing break statements
    
    Found by Cppcheck 1.65. Fixes:
    (warning) Variable 'processor_name_string' is reassigned a value before the old one has been used. 'break;' missing?
    (warning) Variable 'rsize' is reassigned a value before the old one has been used. 'break;' missing?
    
    Change-Id: I4a5c947fd5cc5797eb026475ec7036bc5eaf58db
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6372
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit abb381607fabcea0a101273c29a42280064b5f9b
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Tue Jul 29 12:09:39 2014 +0200

    artecgroup/Kconfig, linutop/Kconfig: Add comment to endif
    
    All other Kconfig files at the mainboard vendor level have a comment
    on "endif" matching the corresponding "if", except these two.
    
    Change-Id: Ib03c4552c670178d6b09a2ca3037ee29e3524a2f
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6396
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit b8e96ed7b81c2d1816814a2a89cf79a5abc4c28f
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Tue Jul 29 12:13:12 2014 +0200

    Kconfig: Fix comments on endif to match the corresponding if
    
    Change-Id: I5c40de41a01d9c558f6c2795e19e643009804e70
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6397
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 76a1437dbe7fae07a5054971adadb703c19f5885
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 26 22:34:59 2014 +1000

    cpu/intel/model_2065x/model_2065x_init.c: Remove dead code
    
    Unused array is dead code. Spotted by Clang build.
    
    Change-Id: I11397716b39de08f1226413019e3beeeeaac6149
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6131
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 787cbaeedb4159c43e5e0875d9b7dbfc8a09ed8c
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Jul 29 22:40:05 2014 +0200

    i82801ix: Enable usbdebug options.
    
    Needed to be able to choose convenient usbdebug port.
    
    Change-Id: I84b304f0f8fa79cc8d4a136ee6d78dc7659601c9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6410
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit c4d894879775f66bdfe0a8f00fa847ab40fbe885
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jun 5 09:14:48 2014 +0200

    gm45: Move spd address map to board-specific config.
    
    Change-Id: I8f45a821ecd414dbd0129ae6d583d4e7dc06bc5a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5931
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit a838aafc63171cef3e3139228541eb785faf6f57
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Jul 29 22:07:59 2014 +0200

    northbridge/intel/sandybridge/raminit_native: Remove stale FIXME.
    
    S3 works just fine.
    
    Change-Id: Icd7ae5ad8941bf749a4450efc61e7cede52bf5ef
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6407
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 77acf42819ed93f77706089b024a771323d34c7a
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Aug 5 21:04:16 2013 -0700

    pit: setup voltage rails before system clocks
    
    This moves the call to setup_power() before system_clock_init().
    This causes the PMIC to set up the voltage rails earlier so that
    the CPU clock can be set up at a faster rate (in the follow-up
    patch). After system clock init, we re-initialize the PMIC's I2C
    bus since the input clock rate will have changed.
    
    Old-Change-Id: Ieb828ac25daad7ee95bfa4823aaaf161028c9c92
    Reviewed-on: https://gerrit.chromium.org/gerrit/64744
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 6c133a84ef4a32c35577a266905e02af8c2d9278)
    
    pit: save setup_power() status and die later if needed
    
    Since system clock and console initialization now happen after power
    setup, we cannot print error messages in setup_power(). This patch
    re-factors the code a little bit to save the status of setup_power()
    so that if we get an error during setup_power() we will wait until
    we can actually print something before dying.
    
    Old-Change-Id: Id7ff477224b104b3c7e221c1d2df460ca9125f3b
    Reviewed-on: https://gerrit.chromium.org/gerrit/65009
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    (cherry picked from commit 0c89f922b20bc1291ac7ba7b2c22bdce911be7a4)
    
    Squashed two closely related commits.
    
    Change-Id: I3efe29412738959e698c89d26e682536ceabdff8
    Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6403
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 91175bb493bd01d9a64d2179c48e07f4cd815642
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 23 09:06:50 2014 +0100

    lenovo/x201 & x230: Add EC info to SMBIOS.
    
    Based on X60 counterpart.
    
    Change-Id: I1556f75db08edf47c9313dae91072335240d46ad
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4780
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 0f92f630556b4bf2e4c0696cae4c2f8e97eda334
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Sun Jul 27 19:37:31 2014 +0200

    Uniformly spell frequency unit symbol as Hz
    
    Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6384
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 081651b6677c64a5f2861d831822b5f8f3517c21
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 26 22:15:29 2014 +1000

    northbridge/intel/nehalem/northbridge.c: Remove unused variable
    
    Spotted by Clang.
    
    Change-Id: I17e64ee989b611fac91072b9e97eab168cfae525
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6128
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit f2e206a7fd4ce9dbc2c033d6d13bb3c024526e46
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Feb 23 00:13:56 2014 +0100

    x230: Deploy VBT
    
    Change-Id: Ide31a56bfdbc31cd3b87993dfb4ed8ef0107cdba
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5396
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit e0ceac3856cb065e596843c7ff9975274109f5cc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Jul 29 00:51:31 2014 +0200

    ec/lenovo/h8: Apply ME workaround on X230 on S3 resume.
    
    This makes S3 work.
    
    Change-Id: Ife14372f5f9bb151d7e6e98c6069eb99d5369baf
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/6392
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 5aa28f5c1b966a10d90700a285a3173ce2579047
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat May 31 22:26:42 2014 +0200

    nehalem: Remove fake_vbt copying.
    
    Instead generate simple VBT in code. Tested on X201.
    
    Change-Id: I2244053edd24c22694161d9bf5f7f2f3eb4e2f57
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5895
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit 1783a3c1b571f3035a2697a1328902a01c1e3283
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Feb 23 00:10:35 2014 +0100

    ivybridge: LVDS gfx init.
    
    Change-Id: If71e9c94922cd4283d5e175dfd8757d398a72be1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5285
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit a014521b9021f5876594e8be038dfd93a24702eb
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jul 29 09:14:46 2014 +1000

    sandy/ivybridge: Native raminit (lint clean)
    
    Remove some trailing whitespaces and add header guards for code
    introduced in:
    
    7686a56 sandy/ivybridge: Native raminit
    
    Change-Id: Ifc9a785ea3a43cfe1f406b57eeba9b5f94f36711
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6393
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7686a56574a6773717b49a51786f301970d1c69c
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun May 18 11:05:56 2014 +0200

    sandy/ivybridge: Native raminit.
    
    Based on damo22's work and my X230 tracing.
    
    Works for my X230 in a variety of RAM configs.
    
    Also-By: Damien Zammit <damien@zamaudio.com>
    Change-Id: I1aa024c55a8416fc53b25e7123037df0e55a2769
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Signed-off-by: Damien Zammit <damien@zamaudio.com>
    Reviewed-on: http://review.coreboot.org/5786
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit b37ee1ee7c69836cfb333c13f787a1c3ba580b8f
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Wed Jul 16 22:22:59 2014 +0200

    util/board_status: use the right location of cbfstool
    
    The cbfstool binary in util/ doesn't exist as often as build/cbfstool does.
    Since cbfstool obtains details from coreboot.rom, use the binary in build/
    
    Change-Id: Id7d5632f4e5cbd5ede58cd136c37b0dacee9ff93
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/6299
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 6e3712f9e11582f98630d404ce48a538716d8fee
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sat Jul 26 11:37:41 2014 +0200

    device/oprom/yabel/vbe.c: Fix memory leak
    
    Do not allocate memory if the bootsplash was not found.
    Found by Cppcheck 1.65. Fixes:
    [src/device/oprom/yabel/vbe.c:734]: (error) Memory leak: decdata
    
    Change-Id: Ie2283165c9d7650dce9baf9e892dd055d44dcce5
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6377
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f9ce88e942a70a1aaa1f0951f8fab436a2ea82f5
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sat Jul 26 11:32:16 2014 +0200

    device/oprom/realmode/x86.c: Fix memory leak
    
    Do not allocate memory if the bootsplash was not found.
    Found by Cppcheck 1.65. Fixes:
    [src/device/oprom/realmode/x86.c:280]: (error) Memory leak: decdata
    
    Change-Id: I8f8160d3d349c0c2b2a3ed84461729e9210153d8
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6376
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit c2519e5a06ba5f70bfcb1e2e70ade440c9552f18
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sat Jul 26 11:17:03 2014 +0200

    dmp/vortex86ex/southbridge.c: Do not access arrays out of bound
    
    Found by Cppcheck 1.65. Fixes:
    [src/southbridge/dmp/vortex86ex/southbridge.c:498]: (error) Array 'rtc[7]' accessed at index 7, which is out of bounds.
    [src/southbridge/dmp/vortex86ex/southbridge.c:498]: (error) Array 'bin_rtc[7]' accessed at index 7, which is out of bounds.
    
    Change-Id: I8939fe1b326202bbe2784639b0e591f8ee470eeb
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6375
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Andrew Wu <arw@dmp.com.tw>

commit f8e96f07d40152a3b11a70ddbd909e9da8fabf7e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 22 15:24:15 2014 +0300

    AGESA boards: Drop get_bus_conf.c files
    
    The only remaining purpose for get_bus_conf() was to fill in obscure
    bus_sb800 (etc.) arrays containing partial PCI bus enumeration. Complete
    enumeration is available in devicetree and PCI configuration space so
    discard these arrays.
    
    Change-Id: I733115940afba3a50c58aedb9a04ecf5082b1234
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6360
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit b426107d1db17b606a90be83ddd3bf8a1c0d8751
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 22 10:24:20 2014 +0300

    AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()
    
    Change-Id: I7fd14c17242cd3deb7a784fc918ad6fe1191bd13
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6359
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit cdfb46240b4bba8a112c85a5f5d26447e90378b3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 22 15:24:15 2014 +0300

    AGESA boards: Use devicetree for PCI bus enumeration
    
    Previously MP table contained PCI_INT entries for PCI bus behind bridge
    0:14.4 even if said PCI bridge function was disabled.
    Remove these as invalid, indeterminate bus number could cause conflicts.
    
    PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2]
    were invalid as there is no PCI bridge hardware on device 0:14.0.
    Remove these as invalid, indeterminate bus number could cause conflicts.
    
    Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6358
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit e5523b808b2a29a3049a21a3b0339e80fbeef42a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 25 17:33:12 2014 +0300

    AGESA: Have IRQ routing in mptables
    
    MP table should be complete with IRQ routing information even
    when we have ACPI tables.
    
    Change-Id: Ieeaed442aea6217f4477b7ac7e06a1926eec8996
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6361
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 32d9e9296e6e7d542d18868110a419e09d8176b0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 22 19:27:52 2014 +0300

    AGESA fam16kb: Move NB config fam16kb out of get_bus_conf()
    
    Change-Id: Iedb5e1c72afe70f63f39c2dbce4896863d1d275f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6357
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 526c2fb278c6c4eccebaaaea9e1f7a00358d10e9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 10 22:16:58 2014 +0300

    AGESA: Drop some excessive agesawrapper.h includes
    
    Change-Id: I3807912b1dc68fae8248a66e37bbe642fb92d3ae
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6262
    Tested-by: build bot (Jenkins)

commit 78d0cab36d835c988ef6a75e0a47fb6349ca1300
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 11 09:44:54 2014 +0300

    IOAPIC: Fix missing stdint include
    
    Change-Id: Ib26f48d3ac66788246834cdc25d97910cd79fe98
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6264
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit b166628c302504f0223045b618c6c05c53a35e61
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jul 6 22:40:15 2014 +0300

    AGESA f15tn f16kb: Fix HUDSON_XHCI_ENABLE
    
    Control for XHCI was split to handle AMD_INIT_RESET in agesawrapper
    while AMD_INIT_ENV was already handled as part of BiosCallouts.
    
    OEM configuration is supposed to be implemented as part of BiosCallouts,
    leaving agesawrapper agnostic of platform details.
    
    TODO: S3 resume for XHCI1.
    
    Change-Id: Id5e9c25a227db4d821f1be4b176470547ca4ea84
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6241
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 9248bb35ab411c79467f5a79607994f4054baa7b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 22 15:56:59 2014 +0300

    AGESA hudson yangtze: Move IMC firmware init out of get_bus_conf()
    
    Change-Id: I5b3cbc4d25f06a5f916760d4474621abbf826ee4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6355
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0c797f1c28cd16c64482b2cea554e89baaa31445
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 21 19:35:16 2014 +0300

    AGESA: Drop offset on PCI device enumeration
    
    Integrated PCI devices in southbridge silicon have static BDFs,
    no need to have variables to store the parent bus or an offset
    with constant zero.
    
    Change-Id: I37d3794d36b5e5775da9215574ddc199696646d0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6333
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0ff17c9cae11b46535b99880f013d0ca084ea1f8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 21 19:20:29 2014 +0300

    AGESA: Drop unused extern declarations
    
    Change-Id: I7f681b40251f49ff717589ed5e7d7e00ee36c7c1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6332
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f62659f6431dfb932d15ffca8c43e1205b514d5f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 15 16:19:08 2014 +0300

    AGESA fam15: Drop code that was commented out
    
    Only references to bus_rd890, bus_sp5100 and bus_sr5650 were
    in code sections that had been commented out.
    
    Change-Id: If5552c409ce948c494345f49dbaad790b398bff8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6331
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 99c636f8581626c527ef5434738883feae06dbc2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 15 14:38:51 2014 +0300

    AGESA boards: Drop global bus_isa
    
    Only ever used as lvalue (except when incrementing) so this global
    is unused.
    
    Change-Id: I616721f937eb0bfdb28f356284efd70f99ccd2dd
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6330
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit da6d8b1048a4d804cb82b71e640b4ec2db7a4c79
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 21 18:45:14 2014 +0300

    AGESA fam15: Use local bus_isa storage
    
    Do not use a global as the value gets discarded anyway.
    
    Change-Id: I86aac304e073f0d74b011548d079e139891ec140
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6329
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 84283bcc12a84b473ee173d5c7af23d208141a23
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Jul 17 08:16:04 2014 +0200

    intel/i945/raminit.c: Remove trailing whitespace from `printk()`
    
    Remove a trailing whitespace after the ellipse in the debug messages in
    `sdram_program_row_boundaries()`.
    
    	Setting RAM size...
    	C0DRB = 0x20202010
    	C1DRB = 0x60606040
    	TOLUD = 0x00c0
    
    Change-Id: I3ee2886da6b048f509b50864bfcc21fbcb093e74
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6300
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b7ea95fa8ecf232bc22f8898cabf3f86eb75cf2c
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Tue Jul 22 23:33:40 2014 +0200

    southbridge/via: Remove trailing whitespace
    
    Change-Id: I28deda21a7070ea6f14f973b66fd5dd119bc6225
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6345
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f4d1d3b98622912e629c33c637d94c7e3c35098e
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Tue Jul 22 23:45:01 2014 +0200

    amd/dinar & torpedo: Remove trailing whitespace
    
    Change-Id: I4ac14c4f511eb6d56480e5167ce98b861cbed775
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6322
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1631c880ebcfd5456f72185b97d3c4859c8486b3
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Wed Jul 23 00:01:34 2014 +0200

    northbridge/amd: Remove trailing whitespace
    
    Change-Id: Iccad59ebac1c47ee3fd16c0c1244b62184cfd1bf
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6316
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 65fa598d2aba9d688d7506cdcaceb393d53e892b
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Tue Jul 22 23:12:38 2014 +0200

    southbridge/amd: Remove trailing whitespace
    
    Change-Id: I25cdfe6b3c8067793620677c62251e78704f7851
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6334
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit aedcc10ad30f3fcc1397035876672d235418393f
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Mon Jul 21 08:07:19 2014 +0200

    src/mainboard: Remove trailing whitespace
    
    Change-Id: I14a9dc99acb5d5365a3d7e99a3964120bb611b05
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6308
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 643646075019816c6ae441f613426caaf7b0bd2e
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Wed Jul 23 10:04:37 2014 +0200

    mainboard/msi/ms7135/devicetree.cb: Remove trailing whitespace
    
    Change-Id: I4151e8ac8903d0daa1e7b12ecadbab8ff7adaaeb
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6349
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5662311b69fc59b2a979f79b39d844e9d3947e14
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Wed Jul 23 10:20:32 2014 +0200

    mainboard/msi/ms9185/devicetree.cb: Remove trailing whitespace
    
    Change-Id: Ifea7c078b5246d4f48da2da1d58d4a5b2b05e6f5
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6350
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7a3ca74ee0ceca570b921e4d5274e9644515f5bf
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Wed Jul 23 10:32:34 2014 +0200

    msi/ms6156/devicetree.cb: Remove trailing whitespace
    
    Change-Id: Ib2c08b58ab98d681f34a435c5ddcb4a9cbab65c1
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6348
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4c9694f13c28267bdd4d0462221af816e94d305f
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Wed Jul 23 10:43:25 2014 +0200

    lippert/spacerunner-lx/devicetree.cb: Remove trailing whitespace
    
    Change-Id: I1a5b5d19ff72b028bbf5bb1c1414eebbf9827a2b
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6351
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9d19f3b85c441ba7d8779db39a8af2308fe5001c
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Wed Jul 23 10:47:40 2014 +0200

    lippert/literunner-lx/devicetree.cb: Remove trailing whitespace
    
    Change-Id: Ib71e25a33e7fe6d43f2ebac0494c263318fa243e
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6352
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a8c6dce51ee35ca5aefdf341c2b685a8660f9d82
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Wed Jul 23 11:12:57 2014 +0200

    thomson/ip1000/devicetree.cb: Remove trailing whitespace
    
    Change-Id: I79c1d1187b1fb44337c1a82bfd9b5871cd43e3e3
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6354
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0d9730216f3c83b1149e94143d101e559c93ecab
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Wed Jul 23 11:00:44 2014 +0200

    mainboard/lippert's devicetree.cb: Remove trailing whitespace
    
    Change-Id: I995b7946b56ed759dc2abac34797fa4747ea9f34
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6353
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d36905cdd586b782db6bf3d76e8622794b4a0bb9
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Wed Jul 23 09:23:29 2014 +0200

    mainboard/msi/ms9282: Remove trailing whitespace
    
    Change-Id: I93808f7798a18ab0993401af556fbb65dbcee32a
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6347
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 23fa3c245a62a1af8604b3522fbebf23b2525bf9
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Tue Jul 22 22:53:06 2014 +0200

    northbridge/intelsch/raminit.h: Remove a trailing whitespace
    
    Change-Id: Ic8d6007898a08ade9d6e5947cd368b7a0545928a
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6314
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9558c004466d3ba5e0d042130a5fa28284ebf255
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Tue Jul 22 19:01:45 2014 +0200

    siemens/sitemp_g1p1: Remove a trailing whitespace
    
    Change-Id: I88366c7cb80d65d84c9f4ea5d287639a9de95a2f
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6323
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4d529dab9279ab4ccb3768996c7a0262df843891
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Tue Jul 22 19:03:14 2014 +0200

    supermicro/h8qgi & h8scm: Remove a trailing whitespace
    
    Change-Id: I9d44679f32b917dae42b9a6920c3d3c54626dcda
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6324
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5cf47cc7905b861698bcf179d647e753702301b4
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Tue Jul 22 19:06:33 2014 +0200

    tyan/s8226: Remove a trailing whitespace
    
    Change-Id: Ic47cf1b55fc0d8b22d30d822b1744847e84d5a43
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6326
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 671ea84b17890d469d2d0f0243cc6f2284fd1f4d
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Tue Jul 22 20:53:42 2014 +0200

    broadcom/blast/devicetree.cb: Remove a trailing whitespace
    
    Change-Id: I76e54669a0e129adf6c7873585c62f692a5d509f
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6346
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e062baacbb1a7c2a824e2894f857af68a03f516f
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Tue Jul 22 18:28:21 2014 +0200

    northbridge/via: Remove a trailing whitespace
    
    Change-Id: I959f2d42bb3b6cd37a7876ad4dae712bdb5a69da
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6315
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e6f43d2e412f23dddb5943393332056be4167e19
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Jul 8 23:13:05 2014 +0200

    cpu/intel/fsp_model_206ax/model_206ax_init.c: Use macro `IS_ENABLED()`
    
    Change-Id: I91cd84d155a2cb1200cb82c31256cfa743e8ea9b
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6227
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f2fb7d916ced44452b6f329d5b407a1c7d48bb4c
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Thu Jul 17 11:59:41 2014 +0200

    src/device/Kconfig: make help for VGA_BIOS_ID and PXE_ROM_ID more similar
    
    Add to VGA_BIOS_ID the hint about lspci -nn and add to PXE_ROM_ID an
    empty line at the end for better readability in menuconfig.
    
    Change-Id: I56751c047c1ff08142e2af58ef3ba5fe1169eba5
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6301
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 53847a211bd78a9cbf838f63f155368c641f7cd5
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Tue Jul 22 18:00:56 2014 +0200

    src/.../Kconfig: various small fixes to texts
    
    Fixed spelling and added empty lines to separate the help
    from the text automatically added during make menuconfig.
    
    Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6313
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit e34a6275eeebf324e921f8aa06e7c1c9fc0179f8
Author: Elyes HAOUAS <ehaouas@noos.fr>
Date:   Mon Jul 21 08:11:18 2014 +0200

    src/drivers: Remove a trailing whitespace
    
    Change-Id: If357da5d84a255e0bdf8784d559ee0941045bbd6
    Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
    Reviewed-on: http://review.coreboot.org/6309
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit bcd09930d8ff78704cb98ad18805788d02687a31
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jul 10 15:02:19 2014 -0600

    board_status.sh minor fixes - no functional changes
    
    - Update some comments
    - Whitespace fixes
    - change from backticks to $() format for getting command data.
    
    Change-Id: Iaf424224abfd30a3581d0e43a1689cc7c887beec
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6261
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 8e0071b7982f5f72cc8e182f8eb5d77248f0b720
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jul 10 15:00:35 2014 -0600

    board_status.sh: Read coreboot boot log from a serial device
    
    - Read the boot log from a serial device.
    
    Change-Id: I9daf97fd9b7fc55d0d56d815b185f9b4e3ef9f5a
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6260
    Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
    Tested-by: build bot (Jenkins)

commit 13c7db8fe805e5b535356a7d86df17b81dff5d2a
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jul 10 14:59:11 2014 -0600

    board_status.sh: name temp dir and print the name
    
    - give a template to the temp dir so they're recognizable.
    - show the location of the temp files again at the end of the script.
    
    Change-Id: Ieb031ee249043697f6a75e42284c23d0b9bad1b3
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6259
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 224617752b7457c3eb086cb3ad52b468a94a0eb7
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jul 10 14:57:34 2014 -0600

    board_status.sh allow cmd() to not save output
    
    - allow for cmd() to be run, but not pipe to a file.
    
    Change-Id: I3e1650e421a49a06218e082ceb5a60b7b4808ce8
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6258
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 05560bfbe083190c0d1eeb87791696f66bffb218
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jul 19 10:55:30 2014 +0200

    build system: avoid warning about missing .xcompile
    
    That file will be generated, but not before make managed
    to complain about it.
    So let's just generate it if missing - it won't hurt the
    dependency tracking some lines later which is looking at
    time stamps.
    
    Change-Id: I615f38457eb27a8ffb4352b5234e262ee95d84ac
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6305
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ed3d0e8d428d497b1d680fec20054906d26990ab
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Sat Jul 19 15:40:40 2014 +0200

    src/device/Kconfig: fix typo in label "1024x768 256-color"
    
    It had an extraneous digit after 768.
    
    Change-Id: Ie415e365f3eac0ed326786cea4c4628c002c4762
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6306
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit b16f09238df063f3f829f34997aa8200af990acc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jun 7 16:27:27 2014 +0200

    nehalem: Move cbmem_recovery call to raminit.
    
    Currently cbmem_recovery is done in raminit only on non-S3-resume path
    do it on both paths to reduce confusion.
    
    Change-Id: I16161ad449b9802a855fcf834aa721f4f65c0bb4
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5954
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 4af1245ea1b3504c28bfc27b351af3195141631f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Jun 11 18:52:11 2014 +0000

    intel/model_2065x: Remove dead code.
    
    nehalem uses gm45-like approach to resume backup so this code is never
    used.
    
    Change-Id: Ic32aa73f8d5b164b1c57815f6f44b2732fdbdcdb
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5975
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit f2b3cd63cfa2fcf7874b1947c60c22b664a277c7
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Feb 15 17:00:46 2014 +0100

    lenovo/x60: Support digitizer on X60t and X201t.
    
    Change-Id: I5b0399a8edca3b73aa7d515d2c446c31b3239fa5
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5239
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c2956e7752213f9eae5064e63d16afa84b7cc23f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 9 04:55:16 2014 +1000

    device/pci_early.c: Mixes up variants of a typedefs to 'u32'
    
    Unfortunately coreboot has to deal with ROMCC's short comings which has
    lead to a little bit of confusion due to typedefs. Essentially, coreboot
    defines four typedefs:
    
     * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode
     * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined
     * 'typedef u32 pnp_devfn_t'
     * 'typedef u32 pci_devfn_t'
    
    Some early functions make use of 'device_t' over 'pci_devfn_t' and since
    the C type-checker does not enforce typedefs to the same type 'u32'
    these are never noticed. Fix these so that 'device_t' does not conflict
    in romstage for later work. We later plan to have 'pnp_devfn_t' and
    'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a
    struct pointer type exclusively.
    
    Change-Id: I948801f5be968a934798f1bad7722649758cd4d3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6225
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b666793925a1fa175f9b6cc12bec051a3a31d23b
Author: Felix Held <felix-coreboot@felixheld.de>
Date:   Tue Jul 15 19:36:43 2014 +0200

    superio/f71869ad: fix documentation of io_info mask values
    
    Change-Id: I5d0a945de45f8f4a77193135e63f480af14a0136
    Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
    Reviewed-on: http://review.coreboot.org/6279
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit cb70f79126a689da172c4851c5f2458604a6ef45
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 22:05:29 2014 +1000

    mainboard: Trivial - drop trailing blank lines at EOF
    
    Change-Id: If29a70be4fb56ebb0dbf6d510412cbe2f34480ef
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6291
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit cf5ac3d7ef1a0f4876f1df7368d19d57d168bae4
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jun 3 08:40:34 2014 +1000

    src/superio/smsc/lpc47m15x: Avoid #include early_serial.c
    
    Provide proper header and function type-signatures for Super I/O
    romstage component.
    
    Fix mainboard's bogous romstage component to match.
    
    Change-Id: Icd02199690d0c428b2daadf702d50714dc367692
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5924
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 031cf214c6626677312f25cd17ed391d8aec4b79
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Jul 18 06:37:27 2014 +1000

    superio/smsc: Add some missing header guards
    
    Change-Id: Id3f85929024208b150c378d7636607a0c9b8617c
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6302
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit ae141dd91b7960dd6ed87d57ad4dad0e06eb709e
Author: Matt DeVillier <matt.devillier@gmail.com>
Date:   Sun Jul 13 18:51:28 2014 -0500

    google/panther: general cleanup, file organization (non-functional)
    
    acpi_tables.c: consolidate/organize headers
    chromeos.c: consolidate/organize headers; move header, #defines outside
    of #ifdef
    fadt.c: organize headers
    gpio.h: rename include guard; add comment to trailing #endif
    had_verb.h: add include guard; replace manual array size calculation with std
    header macro
    lan.c: remove conditional header inclusion; organize headers; remove
    pre-processor directive indentations
    mainboard.c: remove conditional header inclusion; organize headers; replace
    spaced indentations with tab(s); add comment to trailing #endif
    onboard.h: move fn prototype after #defines; add comment to trailing #endif
    romstage.c: consolidate/organize headers
    smihandler.c: organize headers; remove commented-out/dead code; add comment
    to trailing #endif
    thermal.h: add comment to trailing #endif
    
    Change-Id: Iadafdd1092108c3f52435831fa0103f2457066f1
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Reviewed-on: http://review.coreboot.org/6270
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 1f9653a1bc737587deed507cd173595b180aad8f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 14 16:31:25 2014 +1000

    src/superio/ite/it8772f: Separate mainboard from SIO at obj level
    
    Remove #include early_serial.c and rename to early_init.c as no actual
    UART configuration is done here. Note that this SIO component still
    hard codes its base address to 0x2e.
    
    Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6271
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d5339ae0b73b46f65c1d88fd4066a0e98f09b6b3
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 19:58:53 2014 +1000

    mainboard: Make use of ARRAY_SIZE in buildOpts.c on AGESA platforms
    
    Found using coccinelle.
    
    Change-Id: I406de6cfe25d3b471dbb6f98d9c62addae008de3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6195
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cd47560f2ae0758012001d6d954653b4526811ad
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 21:08:23 2014 +1000

    vendorcode/amd/agesa: Use macros already defined in stdlib.h
    
    We already have these macros define in 'stdlib.h'. Make good use of them
    here to avoid redefinition conflicts of the pre-processor depending on
    header inclusion ordering. This has the nice side-effect of syncing up
    AGESA families in this particular regard.
    
    Change-Id: Icf911629a4a1a82b01062fe16af4c8f812b05717
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6199
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit 53584fa32f18eafa1f71be511f20d388550b918b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 15 14:38:51 2014 +0300

    AMD get_bus_conf(): Drop bus_type array
    
    Only ever used as lvalue, so no point creating the array.
    
    Change-Id: I6699dfae9377a895e9bc4a52579d00ddcfa60a9f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6277
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit c4561e24bbdc418e49aa6dbb2689c78a51061ce0
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 26 15:02:40 2014 +1000

    drivers/spi: Sanitize headers from preprocessor abuse
    
    Continuing on from the rational given in:
    
    a173a62 Remove guarding #includes by CONFIG_FOO combinations
    
    Change-Id: I35c636ee7c0b106323b3e4b90629f7262750f8bd
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6114
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0017c6ee87cafc65b8f0679cb2d4862c281a3043
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Jul 12 22:11:24 2014 +0200

    intel/lynxpoint/Kconfig: Remove duplicate option `IFD_BIN_PATH`
    
    Currently `IFD_BIN_PATH` is shown twice. Commit 5218e616
    (intel/lynxpoint: Allow building without IFD (descripter.bin)) [1]
    accidentally added the option another time.
    
    So fix up the commit and remove one of the two options `IFD_BIN_PATH`.
    Keep the one which depends on `!HAVE_IFD_BIN` and is around the IFD
    options.
    
    [1] http://review.coreboot.org/6046
    
    Change-Id: Id46f01ab8ee2e752e337e687a2ef0dfa374f44a5
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6269
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 0ff347129c18b77d3e8ed0bdfa974e09d31735ee
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 19:01:35 2014 +1000

    mainboard,Makefile.inc: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I6a95debbe86fddcaf94270dd380bc73ce3172e58
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6283
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit e6d4732c410e2ed84c691c783492d9f3fd6b5378
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 19:06:12 2014 +1000

    northbridge,Makefile.inc: Trivial - drop trailing blank lines at EOF
    
    Change-Id: Id1fcd3d1cd8a156a76e1a9a3ca4c7b4004c2c015
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6289
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 3c41876e71019cd5214c1939db49f80693104e93
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 19:05:51 2014 +1000

    southbridge,Makefile.inc: Trivial - drop trailing blank lines at EOF
    
    Change-Id: Ied03e8814ea13f0e677a1d34da19efe6dfebf72f
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6288
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit dc112e3515647f17b92ce5205041e03dd53096ef
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 19:03:55 2014 +1000

    cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I7e8866d76d7f286e10160d7dc4f21f01a913bfee
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6286
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 29794b7ad744ea8b2a8b91e2e31a90c599971f5b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 19:04:26 2014 +1000

    device,Makefile.inc: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I73fe6f37c363f4bff332ca90178a236590067170
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6287
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 4fc32be15279be50051e7a73f0e0437e9a973c0f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 19:03:17 2014 +1000

    drivers,Makefile.inc: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I2d1f6a571166924c929452fd0f70192670904220
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6285
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit a47ab1be121004a88a8c680f218ad0f04a374901
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 19:02:20 2014 +1000

    soc,Makefile.inc: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I6db4eada5be5f9a4340d9edb942924e2fd18b5ca
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6284
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit ff9e45e0b2a6bff85911e64572df3c9d1047feff
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 19:00:33 2014 +1000

    superio,Makefile.inc: Trivial - drop trailing blank lines at EOF
    
    Change-Id: Ia452e22af9491c1681c859691eb4ac1868eeb938
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6282
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 52f7043024ad581d7dc8294e8d7dc34fc3f0841d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 23:06:06 2014 +1000

    mainboard,ASL: Trivial - drop trailing blank lines at EOF
    
    Change-Id: Ib531a54db7df6b49a6218f689dcaab712e9dfb01
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6292
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 4202f5d3b3defb5218f95343438d05a7ec1df2ea
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 23:06:35 2014 +1000

    misc,ASL: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I5060052e268c6a6303d77fdf4380a55ac2ad5ae2
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6296
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 398bb142949d3e3960126ba2cca2270b845a97b7
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 23:04:55 2014 +1000

    soc,ASL: Trivial - drop trailing blank lines at EOF
    
    Change-Id: If70f5ad26d639d7366772f4468a25bca83ac0857
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6295
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit c1b1c8e9b3078ef93473634f98441d44af54566c
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 23:04:27 2014 +1000

    northbridge,ASL: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I8d4bf17fe9fd82499b1515a8e85dff9cba498350
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6294
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 5eb4d6327ee021f8398a44294dd47b04a0b8dcc3
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 16 23:04:03 2014 +1000

    southbridge,ASL: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I8ef5f1571ad14ead2d4cc0d61b6b7133d7fc8550
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6293
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit daf9e50ac11da825a60af48ded17ed0f58296ab4
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Jul 15 23:49:16 2014 +0200

    intel/i945/raminit.c: Remove trailing whitespace from `printk()`
    
    Remove a trailing space after the ellipse in the debug messages.
    
    	Setting Graphics Frequency...
    	FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz
    
    Change-Id: Iac8a5e89179104685dc54975ae7f833c1f3de69d
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6280
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ff7e676c9fedf2b9d5f028b66d601971bd67591d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jul 9 04:12:42 2014 +1000

    superio/fintek/f71869ad: config struct should be const qualified
    
    The 'superio_fintek_f71869ad_config' struct packed by devicetree.cb
    should have its type declared with the 'const' qualifier.
    
    Change-Id: Ieb86861ee821e77680cc4d0de202dbd7535b844d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6224
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 152e517877a5652e8ea4d3d4c86a0c5dcb4a9427
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jul 13 00:28:05 2014 +1000

    southbridge/intel/bd82x6x/me_8.x.c: Trivial - space to tab fix
    
    Change-Id: I5b6d0a1f5f96a8d6cfc5a14baaa0f9267339b072
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6268
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8f3de28af38e770808104dfda663dd942f616a6a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 20:04:41 2014 +1000

    drivers/intel/fsp/fsp_util: 'long unsigned int' is 'unsigned long'
    
    This is a bit of strange way to write 'unsigned long', fix that.
    
    Change-Id: I17caf971dac840e0f35f883dacfbd5c94d8c03d6
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6196
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 913e1718cdb3168117555287b99d00d6e6fed55d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Jul 15 12:28:12 2014 +0200

    build system: fix another cbfstool race
    
    It just doesn't work to have files depend on their parent
    directory: As soon as the files are written, the time stamp
    of the directory changes, too.
    
    This led to spurious updates of cbfstool and rmodtool, and
    related "permission denied" errors when linker and build
    system ran into each other.
    
    Change-Id: I44a7d7b4b1d47a1567ece1f57dfd6745d05ee651
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6276
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 18ff4f166beef62175a81e9ffc7390d4a0ae5b64
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Jul 10 21:06:04 2014 +0200

    build system: create .xcompile dependency
    
    It's probably safe to say that .xcompile needs an update if
    util/xcompile/xcompile changed, so tell make about this
    dependency.
    
    Updates are honored immediately due to GNU make's feature of
    reinterpreting everything when an included file changes.  See "How
    Makefiles Are Remade" in the GNU make documentation for details.
    
    Change-Id: Ide2f028eaddcee66028c6403688cc83e1622fa6b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6255
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 3bb0b7230c07cb1d5b71df6976a8323c1cb41ca0
Author: Daniele Forsi <dforsi@gmail.com>
Date:   Mon Jul 14 15:35:42 2014 +0200

    util/xcompile: Print fatal error messages to stderr instead of stdout
    
    This uses die() which was previously unused.
    Before this change an unhelpful error message was printed when make tried
    to parse English text as if it was part of the makefile:
    .xcompile:1: *** missing separator (did you mean TAB instead of 8 spaces?).  Stop.
    
    After this change the first error message at least mentions that iasl is
    missing:
    ERROR: no iasl found
    make: -print-libgcc-file-name: Command not found
    make: -print-libgcc-file-name: Command not found
    make: -print-libgcc-file-name: Command not found
    /bin/sh: 0: Illegal option -
    Makefile.inc:36: *** Please use the coreboot toolchain (or prove that your toolchain works).  Stop.
    
    Change-Id: I79d5de5993e3828460130192df376daa55f32aa0
    Signed-off-by: Daniele Forsi <dforsi@gmail.com>
    Reviewed-on: http://review.coreboot.org/6272
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit be5340bad23af53b4e78adb143fed926ff199c7c
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sun Jun 22 21:46:24 2014 -0600

    board_status.sh add non-fatal test_cmd
    
    - add a non-fatal option to test_cmd.
    
    Change-Id: If74693ea7ec8ea24104d5836e4c24bfb135ef0e1
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6257
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 2fa8cc35a8e65bfc9d1e1571069fc4d0bad83410
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 15 02:30:49 2014 +0300

    AGESA hudson: Fix SPI writes
    
    Only yangtze has longer FIFO in SPI controller. This was overlooked
    in commit
    
       9f0a2be AMD SPI: Optimise for longer writes
    
    which broke SPI writes and caused CBFS errors with fam15tn.
    
    Change-Id: I821e3f1fa186d2383b30eab9c5d52797c2ef22c5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6273
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit dfad0708311758d6a9377b0390df0707f5fb4291
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 10 06:32:36 2014 +0300

    AGESA Hudson: Fix typecasts in Fch_Oem_config()
    
    Like many other (but not all) BiosCallouts, StdHeader is also passed
    as ConfigPtr argument. Use that instead to make no assumptions of the
    real type of FchData as it changes depending of the StdHeader.
    
    Change-Id: Ibdf01d08e63b9e1b8e99ac16abb7f807d37a056e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6240
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 37ab729ec3a2af63c15739859e02255c02939f78
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 10 06:43:44 2014 +0300

    AGESA boards: Use IS_ENABLED() for HUDSON_LEGACY_FREE
    
    Change-Id: Ib2a015dac82cec8538f8b1a1c2d45b20b05747bc
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6239
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit d005f78d292f65506debb5546f085657f3e80237
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 7 18:16:55 2014 +0300

    AGESA fam15: Fix entry to cimx/sb900
    
    Move SB900 call to match comments and changes already made for
    family14 et al.
    
    Change-Id: I22aa0bbeeabf9cff929c49c23014005bc3d53ccb
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6238
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit b6f3da4ddcd306b8039743f1101d41b648e0194d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 7 15:06:00 2014 +0300

    AGESA CIMx: Move late init out of get_bus_conf()
    
    Followup deals further with Fam15 case. For unknown reasons calls
    were commented out for amd/dinar and they remain that way.
    
    Change-Id: Ie0a25fbb6f5378019fbf0f19a02acf024d79817e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6237
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 232ae17718a3d183a4effb0eb4c8633ac87505b7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 7 18:16:55 2014 +0300

    AGESA fam12: Fix entry to cimx/sb700
    
    Move SB700 calls to match comments and changes already made for
    family14 et al.
    
    Change-Id: I20a84e487ba346f63dd4454447077e0d2fd12c89
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6222
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 7b23ae0e8938eb71453cbc28c2cc74c14a4039ae
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 4 16:14:37 2014 +0300

    AGESA: Trace execution with AGESAWRAPPER()
    
    Implement logging just once to have uniform output.
    
    Change-Id: I8db694a3bf6b1af459bdf98f7acb99edf4dd07f7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6180
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 06ff7268f67d1345fd115fda0879d781eac2d6b1
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Jul 5 15:24:50 2014 +1000

    AGESA: Fix error status code return type to enum from UINT32
    
    AGESA correctly uses the enum AGESA_STATUS type whereas boards use a
    mess of UINT32 typecasts.
    
    Also no need to shout VOID. We are not that careful on changing
    all cases of VOID->void or whitespace issues as these files will
    get merged with follow-ups.
    
    Change-Id: I16ccfcc73cda6b917c7ff5fd42ee2cd04e7dc0dd
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6182
    Tested-by: build bot (Jenkins)

commit 9f0a2be1658cf6d329aefac2660a53a465312468
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jun 30 07:34:36 2014 +0300

    AMD SPI: Optimise for longer writes
    
    Leave it to the implementation of flash->write() to split the writes
    to match SPI controller and SPI flash part restrictions. This allows
    for some optimisation for auto-address-increment (AAI) commands.
    
    Kconfig AMD_SB_SPI_TX_LEN can be kept as local.
    
    Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6164
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 1110495de926db4b21b9969da522e5270c67f115
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jun 29 16:17:33 2014 +0300

    SPI: Split writes using spi_crop_chunk()
    
    SPI controllers in Intel and AMD bridges have a slightly different
    restriction on how long transactions they can handle.
    
    Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6163
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 77d1280d0c866a9f85e62f74c43fe8d021a4ff39
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jun 29 16:15:39 2014 +0300

    SPI flash: Fix alignment checks in Page Program commands
    
    There are two separate restrictions to take into account:
    
      Page Program command must not cross address boundaries defined by the
      flash part's page size.
    
      Total number of bytes for any command sent to flash part is restricted
      by the SPI controller capabilities.
    
    Consider
    
      CONTROLLER_PAGE_LIMIT=64, page_size=256, offset=62, len=4.
      This write would be split at offset 64 for no reason.
    
    Consider
    
      CONTROLLER_PAGE_LIMIT=40, page_size=256, offset=254, len=4.
      This write would not be split at page boundary as required.
    
    We do not really hit the second case. Nevertheless, CONTROLLER_PAGE_LIMIT
    is a misnomer for the maximum payload length supported by the SPI controller
    and is removed in a followup.
    
    Change-Id: I727f2e7de86a91b6a509460ff1f374acd006a0bc
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6162
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 562db3bb3fa16abf6f758e97f9e5496f1c14d423
Author: Luigi Semenzato <semenzato@chromium.org>
Date:   Mon Jan 13 17:45:54 2014 -0800

    libpayload: find source of input characters
    
    This change makes it possible for vboot to avoid an
    exploit that could cause involuntary switch to dev mode.
    It gives depthcharge/vboot some information on the
    type of input device that generated a key.
    
    BUG=chrome-os-partner:21729
    TEST=manually tested for panther
    BRANCH=none
    CQ-DEPEND=CL:182420,CL:182241,CL:182946
    
    Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: https://chromium-review.googlesource.com/182357
    Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
    Tested-by: Luigi Semenzato <semenzato@chromium.org>
    Commit-Queue: Luigi Semenzato <semenzato@chromium.org>
    Reviewed-on: http://review.coreboot.org/6003
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f4d1f3a4d9f57b0c36bf90cd9326fdc38ea78de3
Author: Matt DeVillier <matt.devillier@gmail.com>
Date:   Thu Jun 12 12:12:44 2014 -0500

    google/panther: adjust critical temp
    
    Set critical temp to match newer devices
    
    Change-Id: I11f32297a9b8c9a3554821b5d1cd723d8d9e2b69
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Reviewed-on: http://review.coreboot.org/6023
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4923c399f3ca1120aba3f4d5e16eaa2b815ea2aa
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Feb 19 15:05:15 2014 -0800

    google/panther: Force enable ASPM on PCIe Root Port 4
    
    BUG=chrome-os-partner:21535
    BUG=chrome-os-partner:25990
    BRANCH=panther
    TEST=manual: Boot on Panther and look in /sys/firmware/log for
    the string "PCIe Root Port 4 ASPM is enabled"
    
    Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/187153
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/6007
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c63ad997a5e4614cfb12f3d1743e86b21e6e31af
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Feb 14 13:41:39 2014 -0800

    google/panther: acpi: Fix unstable fan behavior on boot + resume
    
    FLVL is used to keep track of which thermal zones are active, but it is
    not initialized upon boot / resume. An initial value of zero corresponds
    to all zones being active, which causes the fan to spin at max speed
    until the OS changes zones. Fix this annoyance by initializing FLVL to
    the lowest temperature zone.
    
    Also, fix a related bug where FLVL may jump to an undesired value. For
    example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's
    already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4
    active!). Fix this by not taking zone ON / OFF actions if our zone is
    already ON / OFF.
    
    BUG=chrome-os-partner:25766, chrome-os-partner:24775
    TEST=Suspend / resume on Panther 20 times, verify that thermal zone after
    resume matches expectation based upon temperature. Also, stress system
    and verify thermal zones become active according to temperature
    increase.
    
    Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/186455
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/186669
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/6006
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 123fa689877a3ab30ffbc32586f3e23ca1f2fcf0
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Feb 14 13:22:30 2014 -0800

    google/panther: Fix RW ramstage index
    
    Without this patch coreboot will always use the read-only version
    of ramstage, even if there is a read-write version available.
    
    BRANCH=panther
    BUG=chrome-os-partner:25870
    TEST=Install different RO and RW version, check in cbmem log that
         coreboot's romstage and ramstage have different timestamps
         in their banners.
    
    Change-Id: I723a3d4479d59534660728d891a9f40a077b4ef0
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/186664
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/6005
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3d24edab2c2b5228277a96b8763d061343e3da00
Author: Mohammed Habibulla <moch@chromium.org>
Date:   Wed Feb 12 10:07:34 2014 -0800

    google/panther: Add new thermal values
    
    Based on latest thermal report
    
    BUG=chrome-os-partner:24532
    TEST=boot tested on panther
    BRANCH=panther
    
    Change-Id: I4b8639f926fc3cf57eb5329818b9b912bfbe222d
    Signed-off-by: Mohammed Habibulla <moch@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/186113
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/6004
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9b43edf36c8fabb63a1239849e7d2dc07bf3f2fb
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jan 13 17:40:37 2014 -0800

    google/panther: Avoid shutdown when thermal sensor is unavailable
    
    When the thermal sensor on Panther is unavailable (early on resume)
    it will return 0x80 which causes our AML thermal code to overflow,
    which causes the system to shut down. Instead, return a reasonable
    value in those cases so that the system will continue running until
    the sensor gets back on its feet.
    
    BUG=chrome-os-partner:24918
    BRANCH=panther
    TEST=suspend_resume_test survived more than 100 iterations on Panther
    
    Change-Id: Ib2d714c39d353ce2415361bc6590784a3f6837d2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182369
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/6002
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a0819eb38d032bb0610ef024f97b5c15aea4d1b2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Jan 10 16:06:03 2014 -0800

    google/panther: Re-read temperature if current reading would cause power-off
    
    Sometimes the SuperIO seems to provide wrong readings, especially early
    on after a resume from suspend. This will cause the system to power off.
    If that happens, wait for 1s and read again, to make sure the high
    temperature value was not just a flaky read.
    
    BUG=chrome-os-partner:24918
    BRANCH=panther
    TEST=Boot tested on Panther.
    
    Change-Id: Ib3768528d90e34448e96ad587b2503d8d8b1a775
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182188
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/6001
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 06946cabd986fb2d0f3e74c5e0eafbf5d2fbfd71
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jan 9 14:15:36 2014 -0800

    google/panther: Disconnect speaker and mic in verb table
    
    There is no speaker and no builtin microphone in this system,
    hence disable them in the verb table.
    
    BRANCH=panther
    BUG=chrome-os-partner:24230
    TEST=Boot Panther, see Microphone and Speaker disappear
         in Audio Settings
    
    Change-Id: I32bacec38ba3ba0c2359a8fc94e12af64f576012
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182006
    Reviewed-by: Dylan Reid <dgreid@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/6000
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a0eeba47a16e5339f02a02ae85418bd9699975a4
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jan 8 15:20:59 2014 -0800

    google/panther: Disable DEVSLP for SATA
    
    Some SSD modules don't support DEVSLP correctly due to their
    firmware. Since the power savings are minimal, don't use
    DEVSLP to prevent potential problems. Some of the symptoms
    are that sometimes this causes USB devices to not work properly.
    
    BUG=chrome-os-partner:23186,
    BRANCH=panther
    TEST=Boot tested on Panther
    
    Change-Id: Iba3f721c73e0e760b6a9861ca23480ddb923df40
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181957
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5999
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1abeef60054f8e3d5b618a88c411d98591a5f4a3
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jan 7 09:53:06 2014 -0800

    google/panther: Add ACPI code to support wake-on-lan
    
    There needs to be an ACPI linkage to provide the power resource
    needed to wake this device so the kernel will enable the SCI
    before going to suspend.
    
    A link is added for both NIC and WLAN, but it is only tested
    on the NIC.
    
    This is a forward port from Duncan's beltino patch.
    
    BUG=chrome-os-partner:24657
    BRANCH=panther
    TEST=build and boot on panther, suspend and wake with etherwake
    
    Change-Id: I2804d2e904e26d6e34f5a177f0dabc1aaa3f0288
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181752
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/5998
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 84570d6c5b8536ca9e7d267fbdcda6375661882a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jan 6 14:48:35 2014 -0800

    google/panther: Update Fan Policy
    
    Update fan policy according to Panther thermal report.
    
    CPU Temp. Readings | PWM
    -------------------+------
     40C               |  42%
     50C               |  42%
     83C               |  80%
     90C               |  90%
     96C               | 100%
    
    BUG=chrome-os-partner:24532
    BRANCH=panther
    TEST=boot tested on Panther
    
    Change-Id: I60f04d8b038c561b87dad505bbf058100119cc23
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181666
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/5997
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a3f061bf2202df5d30be50b8e81c77357a0fd1eb
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Dec 11 11:09:45 2013 -0800

    google/panther: Disable power-failure gating for the PSON# signal
    
    When the system loses AC power, the system will power back on
    automatically as soon as the AC power is reapplied.
    
    BUG=chrome-os-partner:24066
    BRANCH=firmware-panther-4920.24.B
    TEST=boot tested on panther
    
    Change-Id: I37ddc5a162afcce01c2df5f509bfd7f2d0c15ba1
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179537
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/5996
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e9b6155e463dff39cb7d055ea566786c380a6256
Author: Mohammed Habibulla <moch@chromium.org>
Date:   Wed Nov 20 16:30:09 2013 -0800

    google/panther: Configure USB_ILIM_SEL to low
    
    (panther port of Ib980100c648ae7472eac6f97e47f8ef3cbe72c7e)
    
    BUG=none
    BRANCH=none
    TEST=boot tested on Panther
    
    Change-Id: Iedcc107a43be170762d42d515c7e2a16ec395452
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: https://chromium-review.googlesource.com/177474
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Mohammed Habibulla <moch@google.com>
    Tested-by: Mohammed Habibulla <moch@google.com>
    Reviewed-on: http://review.coreboot.org/5995
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d2259dd3a144aa7be96ed5d56b34ad06b290c0dd
Author: Mohammed Habibulla <moch@chromium.org>
Date:   Wed Nov 20 16:24:58 2013 -0800

    google/panther: Set default interrupt value for Environmental Controller
    
    This writes the default value to the register, but it gets rid of
    the error that disturbs some of our tests:
    
    ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned
    (panther port of Ieab1c776b553c996a7d06e4059110943aaf41338)
    
    BRANCH=none
    BUG=chrome-os-partner:23945
    TEST=boot test on Panther
    
    Change-Id: Id45c3bdc0d2feaf6f75d984c41d1f6ffef592d4d
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: https://chromium-review.googlesource.com/177468
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Mohammed Habibulla <moch@google.com>
    Tested-by: Mohammed Habibulla <moch@google.com>
    Reviewed-on: http://review.coreboot.org/5994
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 74a4175912cfdb6d115dd0f7f58c80fb5ff192ca
Author: Mohammed Habibulla <moch@chromium.org>
Date:   Tue Nov 12 13:29:43 2013 -0800

    google/panther: Make sure the S5 power status is on track
    
    (panther port of I933c475f693b0271f86b5166eb2c9b3873f1c2c6)
    
    BUG=none
    BRANCH=none
    TEST=boot test on panther
    
    Change-Id: I5958a8d701901706eaa38df4323120c8352fea5c
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: https://chromium-review.googlesource.com/176563
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Mohammed Habibulla <moch@chromium.org>
    Tested-by: Mohammed Habibulla <moch@chromium.org>
    Reviewed-on: http://review.coreboot.org/5993
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fcb5270d54b9f0eb60deaa942e3475ef59cf5f0f
Author: Mohammed Habibulla <moch@chromium.org>
Date:   Tue Oct 29 11:13:14 2013 -0700

    google/panther: Disable LPSS I2C controllers
    
    There is nothing attached to these devices so we can disable
    them as well as the function 0 DMA controller.
    
    Also remove the EC SMI/SCI mappings since there is no EC.
    (panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87)
    
    BUG=chrome-os-partner:23563
    TEST=none
    BRANCH=panther
    
    Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: https://chromium-review.googlesource.com/174944
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Mohammed Habibulla <moch@chromium.org>
    Tested-by: Mohammed Habibulla <moch@chromium.org>
    Reviewed-on: http://review.coreboot.org/5992
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f0790e4e513203d962c000559dcb842202da3815
Author: Mohammed Habibulla <moch@chromium.org>
Date:   Tue Oct 29 11:02:30 2013 -0700

    google/panther: Fix thermal zone to use SIO PWM/TACH port 2
    
    Fan is attached to port 2 instead of 3.
    (panther port of I9878063a24b0b908c74522580f776a4ce7d03d75)
    
    BUG=chrome-os-partner:23563
    TEST=none
    BRANCH=panther
    
    Change-Id: I028e0e5a748fa0a20d34e27e870e14ed8c75e4d1
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: https://chromium-review.googlesource.com/174984
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Mohammed Habibulla <moch@chromium.org>
    Tested-by: Mohammed Habibulla <moch@chromium.org>
    Reviewed-on: http://review.coreboot.org/5991
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0fccebb5d9d6b888048cd0e3bdbba857f2ba21f8
Author: Matt DeVillier <matt.devillier@gmail.com>
Date:   Thu Jun 12 12:21:07 2014 -0500

    google/panther: Use ISO C99 syntax for designated initializers
    
    In C99 we defined a syntax for this. GCC’s old syntax is deprecated.
    
    Modelled after commit 8089f178 (mainboard/lenovo/x230 Fix usage of GNU field
    designator extension) [1].
    
    [1] http://review.coreboot.org/5392
    
    Change-Id: I51c72252800be64b9420d845e330fc0481c66470
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Reviewed-on: http://review.coreboot.org/6024
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 05497d037e0e4aac24798c8f6082ce320152101f
Author: Mohammed Habibulla <moch@chromium.org>
Date:   Thu Oct 24 16:44:06 2013 -0700

    mainboard: Add new board Google Panther
    
    (Panther clone of Ia41af8425ab6c24746253abd025acd3365dd5a18 by reinauer)
    
    BUG=chrome-os-partner:23563
    TEST=emerge-panther chromeos-coreboot-panther
    
    [pg: Drop configs/, which is chromeos stuff, adapted
         libpayload's config.panther to work with upstream]
    
    [pm: Add HAVE_IFD_BIN and HAVE_ME_BIN Kconfig options]
    [pm: rebase to master branch of coreboot upstream]
    [md: don't use FMAP to get MAC address if CONFIG_CHROMEOS not set]
    
    Change-Id: I50fd5c02da154e424dfefbe2020f4ce7ef9a4f8f
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: https://chromium-review.googlesource.com/174555
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Mohammed Habibulla <moch@chromium.org>
    Tested-by: Mohammed Habibulla <moch@chromium.org>
    Reviewed-on: http://review.coreboot.org/5990
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit d13059a5a2acfbd2e55484b5c6a161286d4e956c
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Jul 7 22:40:12 2014 +0200

    asus/f2a85-m: Switch off automatic fan control for fan2
    
    The fan2 (chasis fan) was set to automatic mode, but the
    registers for smart guardian have still default value which
    will stop it. Run it in manual mode for now.
    
    Change-Id: Ic2c2414ac88abba77a9e7a129788f9777e7e5ad5
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/6217
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 6dbbe2ee96406db44b8e890d315e6704eecef8b1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Oct 17 17:00:26 2013 -0700

    intel/lynxpoint: Allow to always route USB3 ports to XHCI
    
    This will make USB keyboards connected to USB3 ports work
    in libpayload on Beltino.
    
    BUG=chrome-os-partner:23396
    BRANCH=none
    TEST=Use USB keyboard on Beltino in dev mode screen
    
    Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/173640
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    [pm: rebase to master branch of coreboot upstream]
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6018
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 32d2e2b3608006b615521eb68f011aa72f44171e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Sep 25 14:08:32 2013 -0700

    intel/lynxpoint: Work around XHCI resume issues
    
    When USB3 devices are attached while in suspend, or two USB3 devices
    that are both plugged in are switched to the other port while in
    suspend the kernel does not seem to notice this -- despite the cold
    attach status bit.  This results in the devices showing up in the USB
    list at the old enumerated device numbers and higher layers continuing
    to think they are present but not reseponding.
    
    With the kernel workaround to deal with devices that are logically
    disconnected it is possible for firmware to send a warm port reset to
    devices that are in this state and then the kernel will see them disappear
    and handle it properly.
    
    This same issue exists in the EFI firmware on the Whitetip Mountain 2
    reference board so it is not specifically a coreboot bug.  If this
    behavior is fixed in the kernel then this workaround could be removed
    since it is in RW firmware.
    
    BUG=chrome-os-partner:22818
    BRANCH=falco,peppy,wolf,leon
    TEST=manual:
    
    1) attach two USB3 devices
    2) suspend system
    3) switch the ports that the USB3 devices are attatched to
    4) resume system
    5) confirm that the devices are re-enumerated and come up properly
    
    Original-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170335
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4)
    
    Change-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170579
    [pm: rebase to master branch of coreboot upstream]
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6017
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 16a0f5c4e3677ce93949bb5383ebd04a636d13e7
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Sep 25 14:08:16 2013 -0700

    intel/lynxpoint: xhci: Revert suspend/resume changes
    
    I have been attempting to work around USB3 issues that appear in the
    kernel with hacks in the firmware, but this is resulting in more
    headaches in the kernel.
    
    Instead remove all the work that was being done at resume time and undo
    the change that was issuing a warm reset to all ports at suspend time.
    
    The bad device behavior will be dealt with at the kernel level to
    handle devices that get stuck in polling state after enable/disable
    sequence.
    
    BUG=chrome-os-partner:22754
    BRANCH=falco,peppy,wolf,leon
    TEST=manual:
    
    suspend/resume with several misbehaving devices:
    Kingston USB3 Media Reader
    Transcend USB3 Media Reader
    Various ADATA USB3 drives
    Various Kingston USB3 sticks
    
    Original-Change-Id: I0894454af42d2ced456fe0da921d74c9e74902d0
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170107
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit c2abb4d0dad6ed00e1e230d604c4c0a76eb4eef7)
    
    Change-Id: Ib215d9c230f90a1c9f34bf29254bb9feec28c67e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170578
    [pm: rebase to master branch of coreboot upstream]
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6016
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7fc2da910766686d55d489d0e539a1586b98d5bb
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jun 27 12:17:17 2014 +0200

    kontron/ktqm77: Clean up int15 handler
    
    Worked out the purpose of more int15 calls and let them return
    appropriate values. Also remove handlers for copy-pasted calls never
    observed on this board.
    
    Change-Id: I3d8c4ec5542bd19baca1dca83badc9b568779e1b
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/6249
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 40f9ce93fa1d9e5206cd5c1081d22c60bfc6d3f3
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Oct 22 11:07:23 2013 +0200

    kontron/ktqm77: Improve W83627DHG's GPIO config
    
    Fix some outputs of the super i/o that should be GPIOs and make
    variables out of magic values that configure LVDS.
    
    Change-Id: Ib9eef065980cefff0046485549a68cf8f070d5b9
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/6248
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2b2f849b537db935453694e863f9b4f73efbbff5
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Jul 8 15:32:02 2014 +0200

    YABEL: Initialize global `biosmem` pointer for VBE
    
    The global pointer `biosmem` defined in vbe.c was never set. Thus, VBE
    calls didn't work within YABEL.
    
    Change-Id: I63c1c77755f9c442cfec227a495332595ce2b70c
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/6250
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f6e1cbec2a68211225c6281b1f451173de688f44
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Jun 28 22:47:22 2014 +1000

    southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes
    
    Remove some ASCII art past 80 columns.
    
    Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6155
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7116ac803736345cc7c7b73ac435efa50c4cd2b0
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jul 8 01:53:24 2014 +1000

    src: Make use of 'CEIL_DIV(a, b)' macro across tree
    
    The objective here is to tighten coreboot up a bit by not repeating
    common helpers. This makes the code base more consistent and
    unified/tight.
    
    Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6215
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit c805e62f9dd5e1b11906101845abd36b049e7dc3
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Jul 7 22:16:36 2014 +0200

    vendorcode/amd/agesa/f15tn: Fix erratum #712
    
    Implement the fix for the erratum #712. - Processor May Hang During Graphics Memory Controller
    Sequencing
    
    The processor may hang during a graphics memory controller (GMC) sleep state transitioning. The failure may
    be processor specific and may be sensitive to temperature.
    
    Potential Effect on System:
    System hang.
    
    Suggested Workaround:
    BIOS should set D18F2x408_dct[1:0] bit 31 = 1b.
    
    See Publication # 48931 Revision: 3.08
    
    Change-Id: I4346fd4ef3cf554ffdaaad5ab6fc84e73532e885
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/6216
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 533c119f5b4fd7725ab3f09a0f3af7b623cc501d
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jul 10 09:42:03 2014 +0200

    build system: avoid more race conditions
    
    In an abuild run, cbfstool is built in a shared directory
    using "make tools". Unfortunately the build system doesn't
    actually use that binary directly but creates a per-board
    copy (for convenience purposes when editing the image later)
    and uses that.
    
    With this change the build system uses the original file but
    still creates the copy for the user, avoiding the race while
    ensuring convenience.
    
    Change-Id: I38c603a7eca5ef859875ad3031bf7a850189645f
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/6242
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 5b9e6f175f7778b16ac988e2de4e271751ecc019
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jul 10 12:56:34 2014 +0200

    libpayload: Drop obsolete setting of reg_base in [oex]hci
    
    Setting of `controller->reg_base` is of no use here, as it is never read
    (in another function) later. Looks like this pattern originated from uhci.c
    where it makes sense.
    
    By removing the indirection through `reg_base` we also fix a possible
    truncation to u32.
    
    Change-Id: I5c99c5bf1f5b1d6c04bd84d87fd3e275fd7d0411
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/6251
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f4316f8c101b956af624b0c046c418b4489f6558
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Jul 7 17:11:53 2014 +0200

    libpayload: Catch null-pointer dereference in xHCI
    
    Fix a possible null-pointer dereference (hopefully) before anyone runs
    into this. Also don't switch ports to xHCI if initialization failed.
    
    Change-Id: I5dbaeb435a98ead0b50d27fde13c9f1433ea3e81
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/6245
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 8b8e96370dc709299da7a6393f6e190bb557685e
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Jul 7 17:20:53 2014 +0200

    libpayload: xHCI: Always initialize controller->pcidev
    
    As the controller structure is never fully cleared, this one wasn't
    initialized for non-pci controllers (but checked for non-null later).
    
    Change-Id: I852671c5f55650bdb6cd97f4ec74b1f95ee894c7
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/6246
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 6e23066d7ac31bd29b328824ec11e7d1252cf41c
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Jul 7 16:33:59 2014 +0200

    libpayload: Use unsigned long for BARs in *hci_init()
    
    Using void* for physical addresses leads to much casting and confuses
    developers when to convert from physical to virtual addresses or
    the other way around. When using plain integers for physical addresses
    and pointers for virtual addresses things become much cleaner and we
    won't ever end up dereferencing a physical address.
    
    Change-Id: I24cd53b81c7863b6d14f0cbb4ce8937728b37c1c
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/6244
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 322794243a98a47fe6e3b270277dd049e7d4f22e
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Jul 8 15:07:19 2014 +0200

    libpayload: Keep physical addresses in console drivers
    
    Like done in FILO, libpayload's console drivers might be initialized
    before a relocation. So keep physical pointers in there which won't
    break on relocation.
    
    Change-Id: I52e5d9d26801a53fd6a5f3c7ee03f61d6941d736
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/6247
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 6a058904d9fc55975689981cad3d65e84e0501d7
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Jul 4 18:17:39 2014 +0200

    libpayload: Remove redundant phys_to_virt() from xHCI driver
    
    Remove a redundant phys_to_virt() that sneaked in the initialization of
    PCI xHCI controllers. The use of casts from void* to u32 (and vice versa)
    prompts for things going wrong here. That will be addressed in a later
    commit.
    
    Change-Id: Ibc71ed6ee7016529c0e3a51559aaec07aaaba315
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/6243
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit fd570665ce9eb76e02d1fe5fb958e87ea017fd73
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 20:33:09 2014 +1000

    include/stdlib.h: Extend common macro collection
    
    Add the following useful macros:
    
     * Absolute Value Macro
     * Taking ceiling of (a / b)
     * Check if value x is a power of 2 or not
    
    Change-Id: I4e9a326aea3cdd963f13548d1fb63331a57d84b1
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6198
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4793328fbd00776046f43ef8d5f0775c54a7e572
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 10 20:27:27 2014 +0300

    AGESA Hudson: Fix build without HAVE_ACPI_RESUME
    
    If one commented out HAVE_ACPI_RESUME in Kconfig file for a board
    using agesa/hudson the build failed.
    
    Change-Id: Ifbad8f6e23ce4b5431e596bf67e6ab108fedb4ce
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6253
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)

commit 7e5494c549f1642cc9a98a8e59e87007572c8f88
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Jul 9 15:40:15 2014 -0600

    northbridge/amd: Fix the family15tn option rom mapping
    
    Family15tn video bioses internal have a PCI ID of 1002/9901.
    The vendor/device mapping in the family15tn/northbridge.c
    file needs to map to 1002/9901 and not to 1002/9900.
    This was tested on the amd/parmer mainboard.
    
    Change-Id: I0153e9b522e847099c6054d91bf73b50966ed838
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6252
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b2a14fb4f1656c9811f158140040f1157ccb5960
Author: Matt DeVillier <matt.devillier@gmail.com>
Date:   Mon Jul 7 18:48:16 2014 -0500

    intel/haswell: add vmx support w/Kconfig option
    
    patch based on VMX support in intel/fsp_model_206ax and intel/model_6fx
    tested/verified working on google/panther
    
    Change-Id: I61232fdc2a29c53aa3bea5ea78b2fdc41fd7396a
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Reviewed-on: http://review.coreboot.org/6223
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit e963b388ba552c0d4179425d55171775df3606e2
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jul 6 19:27:14 2014 +1000

    vendorcode/amd/agesa/f14: Trivial - drop whitespaces in .h
    
    Change-Id: Ic63c456e775ad0863ea773abd957d9399e8e2a13
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6191
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 1542a6fb8c9633f6a492078bab2e4f5d75564a3c
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jul 6 19:24:06 2014 +1000

    vendorcode/amd/agesa/f14: Trivial - drop trailing whitespaces
    
    Change-Id: I716253fe8532a4215e5770cd901ee3b3c4963d3d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6187
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 648c9548ba7dc14ac6879c9aa188a8ee6774df8b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jul 6 19:27:47 2014 +1000

    vendorcode/amd/agesa/f12: Trivial - drop whitespaces in .h
    
    Change-Id: Iace2ccfe95bd7f7e5dabbbc69ee4249d80d1cb84
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6190
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit f1323167a9a53873c84f556eab2aa4775519218c
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jul 6 19:23:33 2014 +1000

    vendorcode/amd/agesa/f12: Trivial - drop trailing whitespaces
    
    Change-Id: Ieca3358a2a459016b7a38dce7f717100b55baba5
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6186
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 692f522962bff55f362db82b054b9a605921c300
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jul 6 19:28:19 2014 +1000

    vendorcode/amd/agesa/f10: Trivial - drop whitespaces in .h
    
    Change-Id: Ie8d74970ef8969cf65b40970cb234399c3db8e56
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6189
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 8a6f21602e207b3cbed4a38baa12da8f0ded686e
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jul 6 19:22:55 2014 +1000

    vendorcode/amd/agesa/f10: Trivial - drop trailing whitespaces
    
    Change-Id: I8f4b2b555d71dd30f134e41ce998c946c4ac0280
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6185
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit b9a67008b9acc67a5e1009ed10e1650ca6bff869
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jul 6 19:29:03 2014 +1000

    vendorcode/amd/cimx: Trivial - drop trailing whitespaces in .h
    
    Change-Id: I3af50553191d7df9255be222eaf941b4232955d9
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6188
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ef5981b4aa5abe654e1579eb95e4c0403d5719ac
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jul 6 19:20:52 2014 +1000

    vendorcode/amd/cimx: Trivial - drop trailing whitespaces in .c
    
    Change-Id: I485f79ece481210f31b0b6d3c62d7269131e29ab
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6184
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit e1163c1782914c348a586b16321e09d81c371cbe
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 23:44:40 2014 +1000

    mainboard: Trivial - drop trailing blank lines at EOF in .h
    
    Change-Id: I4a4ee99468e5f1dae8412ae565a34290493db726
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6201
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7974471e379e3aaefc0ecd5524c408e69537444b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 23:42:58 2014 +1000

    mainboard: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I05d6d22664155ac8478e665733f816776e277c22
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6200
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 1f19d3494142bd12fa6d75f5761865346da5bcc5
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jul 8 00:29:53 2014 +1000

    vendorcode/google: Trivial - drop trailing blank lines at EOF
    
    Change-Id: Ib8d26d62566e42a78abc282dc9e351774b8e2faf
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6212
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 16a8206d52fa8aeb7ed2e59c6180b0d8c7355a1b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jul 8 00:18:27 2014 +1000

    vendorcode/intel: Trivial - drop trailing blank lines at EOF
    
    Change-Id: Iea9e95981e5e87f2890841e7a0cf45ba93ce84eb
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6211
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 234781e074919c6e6e5b78f6d323d214f1aed3a9
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 23:54:59 2014 +1000

    northbridge: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I9515778e97cc5ae0e366b888da90a651ae5994fe
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6210
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 264d265d9c0f9f6c157fcc12d28b238849d25293
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 23:54:15 2014 +1000

    southbridge: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I5484ebb665453777cc3b2561be6e50c787f1a257
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6209
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 730e3b02fb30b944664f69d9a73e69256bc9952f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 23:52:53 2014 +1000

    soc: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I1829c77f41cc809b590d00ef5522f368bd5fd814
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6208
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit f7c55148c02dcfd39f585aa90513a18d66815a97
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 23:52:18 2014 +1000

    cpu: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I9004f34ba0c13b4489b26ac8c1476d00a6c6d01d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6207
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 7e8d48372b8638fcba78c99b8ce0128bec4eaafc
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 23:51:09 2014 +1000

    arch: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I472f3b70226ea5236ba6fc231f0f257f0f0eed9d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6206
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 6beb1fe32512eb73c2e79f2ba7c1256d81fb74c6
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 23:50:25 2014 +1000

    lib: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I69a4a2ffb41eeae04529e527d68edc652f3638a5
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6205
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 64ea6dbe2e677e7b394d3c3aeb24b7f450a6a271
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 23:49:00 2014 +1000

    device: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I50a5177a8bad5dada862f30c5c9421f08b0e1686
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6204
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 1bd01663f51db9a9a801446fee697bf8c91952f3
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 23:47:29 2014 +1000

    drivers: Trivial - drop trailing blank lines at EOF
    
    Change-Id: Ie80c87c614a536cc6b0bdbf196c280b64547d3b7
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6203
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit f35353af55f6c954524c77c18d7282c260a8b8aa
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 23:45:39 2014 +1000

    superio: Trivial - drop trailing blank lines at EOF
    
    Change-Id: I8633d331d095fe9506a8f01969060ba9889c8eac
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6202
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit c2bc6fdc5b07d09545aa6be5312b4c1b841b6e26
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Jul 7 12:25:30 2014 +0200

    build system: prevent race on more tool binaries
    
    ifdfake is the newest tool addition that leads to build time
    races on highly parallel builds.
    
    Change-Id: I86289e50079da851dcc8e1c05c2536d5c03de87c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6197
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 96c801bfe94373741773244430485b4b694700dd
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 19:17:53 2014 +1000

    mainboard/hp/dl145_g3/get_bus_conf.c: Use ARRAY_SIZE macro
    
    Change-Id: Ie3287cba45bd6f4f8823ce03cd9983707c9ad0de
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6194
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 4b7910635de3ae31da83e9da03376d31f91df081
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jul 7 19:12:24 2014 +1000

    mainboard: Make use of ARRAY_SIZE macro in hda_verb.h
    
    We have the macro, let us be sure to make use of it.
    
    Change-Id: I8dc5ca580c7485e3cce7ebc29189a452de52b1b1
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6193
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 577573fd5ec7df094da09c92ae454b261173ecbe
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jun 27 12:16:17 2014 +0200

    YABEL: Drop IO stubs that are (by own admission) never used
    
    Change-Id: I90a120e64a5062493f64e3e8b48a75dae9342ec4
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/6178
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 501093d4fe993cfcca915c0d1fe2ab3a596d27b7
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Jun 16 17:40:11 2014 +0200

    Intel Lynx Point boards: Kconfig: Add `HAVE_ME_BIN`
    
    Change-Id: Ib7d2a5c14675427fe9556a6b81ed5397f17937d8
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6049
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cc53d5122505e3528a1f3d38004649bca8ff975e
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Jun 16 17:30:56 2014 +0200

    Intel Lynx Point boards: Kconfig: Add `HAVE_IFD_BIN`
    
    Change-Id: I0ea09d75cb05687407fb152642578e19824d1c4c
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6048
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 32d22988282c0696dd89312e41b4a9ef57886443
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 4 17:32:22 2014 +0300

    amd/dinar: Fix agesawrapper header
    
    Change-Id: I246cfb38aa47e67d62bcfcc37539e9593b8026ce
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6179
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 36abdc4017d93484577fe08fdb61d8ff22c6259c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon May 5 16:40:15 2014 +0300

    gizmosphere/gizmo: Move support of SPD data in CBFS
    
    This code is not specific to any board or AGESA family.
    
    Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5690
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 93d9f92cfbb214718e211aee71ac869c77f725ee
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Mar 27 21:52:43 2014 -0700

    spi: Change spi_xfer to work in units of bytes instead of bits.
    
    Whenever spi_xfer is called and whenver it's implemented, the natural unit for
    the amount of data being transfered is bytes. The API expected things to be
    expressed in bits, however, which led to a lot of multiplying and dividing by
    eight, and checkes to make sure things were multiples of eight. All of that
    can now be removed.
    
    BUG=None
    TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI
    errors in the firmware log. Built for rambi.
    BRANCH=None
    
    Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/192049
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    [km: cherry-pick from chromium]
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6175
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1e187356e831583830a22cf051c792470d0440f5
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Mar 27 20:37:03 2014 -0700

    spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.
    
    The spi_flash_probe and and spi_setup_slave functions each took a max_hz
    parameter and a spi_mode parameter which were never used.
    
    BUG=None
    TEST=Built for link, falco, rambi, nyan.
    BRANCH=None
    
    Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/192046
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    [km: cherry-pick from chromium]
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6174
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ab605108184e53964e6f6a2300a1983aa7166422
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jun 30 07:49:55 2014 +0300

    spi flash: Organise options list
    
    Change-Id: I21e4e2384d9b8bbd34f652e99af11dee993fb41c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6173
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c06af9eb8b662f23a7f93ff781f7a5b5edefbb9c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 3 12:11:05 2014 +0300

    Drop redundant select CACHE_AS_RAM
    
    The few remaining boards without CAR override this with
    select ROMCC.
    
    Change-Id: Ifd5223e67f6a2dadb47846bdaab40b1be763cf69
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6172
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8aeab56b102be493b7a592d45bb3646f8230e7be
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Jun 5 08:50:17 2014 +0200

    lenovo/x60/i915.c: Use define for `BSM`
    
    Although it builds without any further changes, including the header
    
    	src/northbridge/intel/i945/i945.h
    
    where `BSM` is defined, would be useful. Unfortunately that conflicts
    with the already included header `southbridge/intel/bd82x6x/pch.h`,
    so it is left as is.
    
    Change-Id: I7c0a795338c34038169e082446907987364a0e88
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5932
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 9238c11be4f8e0909b0ad1ecfdebf891337bb1a0
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Apr 19 11:03:40 2013 -0700

    intel/lynxpoint: Build intermediate step to add Lynx Point ME image
    
    This is needed to successfully build fox_wtm2 from external repo.
    
    BUG=chrome-os-partner:18638
    BRANCH=none
    TEST=manual: successfully compile coreboot for fox_wtm2 and
    create an image with chromeos-bootimage/cros_bundle_firmware
    
    Change-Id: Iaa4e9983faa1d86c2b29d8fd4f577be035497e38
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48676
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4132
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 88c873a07ecff2c6f5ec04d178251315cf01e06a
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Sep 16 13:51:08 2013 -0700

    intel/lynxpoint: xhci: Port reset changes on suspend/resume
    
    Some USB3 devices are not showing up after suspend/resume cycles.
    In particular if a device uses a lower power state like U2 it may
    take longer to come up and the firmware needs to wait after sending
    a warm port reset.
    
    In addition skipping port reset to connected ports in the way into
    suspend was causing problems so instead send all ports a reset
    before suspend.
    
    BUG=chrome-os-partner:22402
    BRANCH=falco,peppy,leon,wolf
    TEST=manual:
    
    Suspend/resume with ADATA HE720 HDD (and other devices) both
    connected at suspend and connecting while in suspend and ensure
    that the devices always show up in the kernel.
    
    Change-Id: Ib7b15dc65792742b4ceb7dcfc4b2c83192eafcc2
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/169548
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6015
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 779e178353a1adb6e6bee8fcad688bcbceb172cf
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 7 16:29:54 2013 -0700

    intel/lynxpoint: Export pch_enable_lpc() for Super I/O systems
    
    In order to enable a Super I/O in non Chrome EC systems we
    need to make pch_enable_lpc() available to the mainboard
    romstage.c
    
    BUG=none
    BRANCH=none
    TEST=boot ChromeOS on Beltino
    
    Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172180
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/6019
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c50c0ab4566a031a0420d762f2403126635bba93
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Jun 11 12:53:47 2014 -0600

    drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit()
    
    At the end of some SPI operations the SPI device needs to be polled
    to determine if it is done with the operation. For SPI data writes
    the predicted time of that operation could be less than 10us.
    The current per loop delay of 500us is adding too much delay.
    This change replaces the delay(x) in the do-while loop with a
    timer so that the actual timeout value won't be lengthened by the
    delay of reading the SPI device.
    
    Change-Id: Ia8b00879135f926c402bbd9d08953c77a2dcc84e
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5973
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ba92428514d8cac8045faa1dc573599424ef7231
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Jun 27 12:13:30 2014 +1000

    intel: Make monotonic timer a first class citizen
    
    The monotonic time now needs to be a first class citizen in Coreboot as
    it is a hard dependency of the drivers/spi flash command polling
    function.
    
    Change-Id: I4e43d2680bf84bc525138f71c2b813b0f6be5265
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6135
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit bda9a821142c0a105bc8892aef610ea43ce3400c
Author: Vladimir Berezniker <vmpn@vmpn.net>
Date:   Tue Jul 1 20:40:18 2014 -0400

    Documentation: Use correct file name for the build guide in the Makefile
    
    Change-Id: I19c456e8bcd2de19c5f9d963ea17dad84d300ab8
    Signed-off-by: Vladimir Berezniker <vmpn@vmpn.net>
    Reviewed-on: http://review.coreboot.org/6170
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit e05cba2c7225d43913fea3b0066f2e24990cee6f
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Wed Oct 30 23:56:26 2013 -0600

    intel/lynxpoint: Add SATA DEVSLP disable option
    
    Add the chip option to disable SATA DEVSLP. This disables
    the SDS bit in the SATA CAP2 register.
    
    BUG=chrome-os-partner:23186
    BRANCH=leon
    TEST=Manual: System runs without SATA failure for more than 10 hours
    
    Original-Change-Id: I8baa40935421769aeee341a78441fb19ecaa3206
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: https://chromium-review.googlesource.com/174648
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    (cherry picked from commit 49d25812b04a983d687a53a39530559ba99fd9b4)
    
    Change-Id: Iac0b32f80958f5ffb571733484dc931bee216f55
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: https://chromium-review.googlesource.com/176352
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/6013
    Tested-by: build bot (Jenkins)

commit 5a45b04ac0e4a296f1df1984200766151c66c42c
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Aug 22 09:56:42 2013 -0700

    intel/lynxpoint: Add CONFIG_LOCK_MANAGEMENT_ENGINE entry to Kconfig
    
    This was missing from lynxpoint.
    
    BUG=chrome-os-partner:21796
    BRANCH=falco,peppy
    TEST=emerge-falco chromeos-coreboot-falco
    
    Change-Id: Id1b261a5310ce1482f11c8c032c13f49046742fc
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66669
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6012
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 78145a56b4f0332804d3b843f0ca855821308d83
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Aug 21 13:16:21 2013 -0700

    intel/lynxpoint: Use separate SMI callback for USB XHCI routing
    
    This will allow the legacy mode boot path to leave USB
    ports routed to EHCI so they can be used by SeaBIOS.
    
    BUG=chrome-os-partner:22085
    BRANCH=falco,peppy
    TEST=manual: Build and boot from USB and SeaBIOS on falco
    
    Change-Id: I46870eccd1b846dc8a7f8d7948969c8e623e18cd
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66547
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6011
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7034b9ef77c8e3782eb920f602ef962a38f221a3
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Feb 11 16:18:07 2014 -0800

    intel/haswell: Allow overriding PRE_GRAPHICS_DELAY in config
    
    Without a prompt the config option will always stay 0
    due to the way Kconfig works.
    
    BUG=chrome-os-partner:25387
    BRANCH=panther
    TEST=Boot into dev mode with Mohammed's TV screen, see
         the dev mode screen appear.
    
    Change-Id: Ib7d9ec82b4a4a29daddc29aa7702fc420279017d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/185970
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/6010
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f1aabecaaccbac8ed575312f3801ec9de7e912a9
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jan 22 15:16:30 2014 -0800

    intel/haswell: Allow pre-graphics delay
    
    Some slow monitors/TVs can't wake up quickly enough for coreboot,
    so when the VBIOS is run it won't detect them. Hence, add an option
    to wait for a while before running the VBIOS.
    
    BUG=none
    BRANCH=panther
    TEST=Boot to dev mode on one of the systems that exposed the problem
         and see it go away.
    
    Change-Id: Ib9524f1c7ee08bedf96a6468da8b4ccf712fe0e2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/183545
    Reviewed-by: Mohammed Habibulla <moch@google.com>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/6009
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 0089c2418b252483120f72a47955f771b3993a28
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Jun 16 14:59:44 2014 +0200

    intel/lynxpoint: Make inclusion of Intel ME optional
    
    Current build configuration always wants to include an Intel Management Engine
    (ME) firmware (`me.bin`) on Intel Lynx Point systems.  However, we can have a
    working coreboot without it, as long as the factory delivered ME firmware is
    kept untouched in the flash ROM. So let the user decide if a ME firmware will
    be included in the build by introducing the Kconfig option `HAVE_ME_BIN`.
    
    The same was done in commit 99fd30e4 (sandybridge: Make inclusion of me.bin
    optional) [1] for Intel Sandy Bridge (BD82x6x).
    
    [1] http://review.coreboot.org/3522
    
    Change-Id: I7c6048fd0f56288769ad90acbfb67b908ac8d824
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6047
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5218e616517ff5118080b01ce2f4305699f8b319
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Jun 16 09:28:36 2014 +0200

    intel/lynxpoint: Allow building without IFD (descripter.bin)
    
    On newer Intel systems, like Intel Lynx Point, the flash ROM is shared
    between the host processor (BIOS), its Management Engine (ME) and an
    integrated Ethernet controller (GbE). The layout of the flash ROM (and
    other information) is kept in the so called Intel Firmware Descriptor
    (IFD).  If we only want to build coreboot to update the BIOS section,
    all we need is the flash layout.
    
    So add the option to specify the flash layout in the mainboard’s
    Kconfig, and thus, to build without the real IFD. However, with such a
    build, one has to make sure that the IFD section on the flash ROM will
    not be written over (nor any other section that has not been included
    by coreboot). A patch to write selected sections of a flash ROM with
    IFD has been sent to the flashrom mailing list [2].
    
    The same was done in commit a15cd66b [1] (sandybridge: Make build
    possible without descriptor.bin) for Intel Sandy Bridge (BD82x6x).
    
    [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
        [PATCH] Add option to read ROM layout from IFD
    [2] http://review.coreboot.org/3524
    
    Change-Id: I26a604446cdf37a6bbcee2b14a107b7ccf417d5c
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/6046
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6a089e3b18ebb5561ae7233d28ff53fff9fbe676
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 27 13:32:59 2014 +0300

    AGESA boards: Use acpi_is_wakeup_s3()
    
    Change-Id: Ib76ec433710b3a7c26360329a9403585d6f4fe4c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6143
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit db8693bde7ad2cc2f6b32bb9654685c1ddb502b2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 19 23:29:07 2014 +0300

    ACPI: Recover type of wakeup in acpi_is_wakeup()
    
    Update acpi_slp_type early in ramstage.
    
    Change-Id: I30ec2680d28b880171217e896f48606f8691b099
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6142
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ef40ca57ebd4de746eafaa1e5a1cae035337f285
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 19 22:19:20 2014 +0300

    AGESA: Call get_bus_conf() just once
    
    Instead of calling get_bus_conf() three times from write_tables()
    and executing it once, just make one call before entering write_tables().
    
    Change-Id: I818e37128cb0fb5eaded3c1e00b6b146c1267647
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6133
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 005028e0a952b00b6184cdddf5905a1637029585
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 19 23:12:15 2014 +0300

    AGESA: Add agesawrapper_post_device()
    
    NOTE: The procedure is moved across a collected timestamp
    TS_WRITE_TABLES, so the delay of SPI erase/write will be accounted
    for in an earlier entry in cbmem -t output.
    
    Change-Id: I0f082e7af1769c8d7d03cdd51fdb5dacbf3402b4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6132
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit e1b468e1a7cbea55108fb106105612e1f50c9487
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jun 18 09:10:53 2014 +0300

    AGESA boards: Use acpi_s3_resume_allowed()
    
    This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the
    build of romstage also for boards without HAVE_ACPI_RESUME.
    These symbols got exposed as the use of preprocessor directives was
    reduced.
    
    We expect the linker to do a fair job and optimize away function
    bodies that are on unreachable execution paths.
    
    Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6067
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit adf3d6ff52eb674267eacbf37f811c7144e857b3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 19 16:51:54 2014 +0300

    AGESA: Clean separation of SPI flash
    
    To be precise, wakeup from S3 does not involve SPI writing, while
    preparing for it on cold power-ons currently does.
    
    For S3DataTypeMtrr storage is changed such that the first 4 bytes
    is the length of data stored like with the other two S3DataType.
    
    Change-Id: Id920650474530d4191075da4ef70daa66c904c5b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6085
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 23b4f0c7344c199d5adb0aece8d3ca9a624f4a34
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jun 18 09:55:26 2014 +0300

    AGESA boards: Add prepare_for_resume()
    
    Use one common implementation for all AGESA platforms.
    
    Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6084
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 31eff28f4f47a38f6e25c93d76f52fe19a092545
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 20 12:52:06 2014 +0300

    AGESA S3: Refactor S3 backup store locations in SPI
    
    Prepare code to locate S3 backup from CBFS as a file. Follow-up will
    replace remaining use of CONFIG_S3_DATA_POS with cbfs_get_file_content().
    
    Change-Id: I693c41c90e61d1a7c7b10e43c9f264d099c9a400
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6083
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 2093c4f7c220068e630b756dd19b89ab1ddec88e
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Fri Jun 13 08:12:48 2014 -0600

    AMD/agesa: Add functions for AMD PCI IRQ routing
    
    Port the changes that were made in amd/cimx to amd/agesa
    as were done in:
       commit c93a75a5ab067f86104028b74d92fc54cb939cd5
       Author: Mike Loptien <mike.loptien@se-eng.com>
       Date:   Fri Jun 6 15:16:29 2014 -0600
    
          AMD/CIMx: Add functions for AMD PCI IRQ routing
    
    This change also moves the PCI INT functions to
    southbridge/amd so that they can be used by CIMX and
    AGESA. The amd/persimmon board is updated for this
    change.
    
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637
    Reviewed-on: http://review.coreboot.org/6065
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 931c1dcec043e6baac718a94f8731cc31461d4db
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jun 30 09:40:19 2014 +0300

    stdlib: Drop duplicates of min() and max()
    
    Change-Id: Ib2f6fad735e085d237a0d46e0586e123eef6e0e2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6161
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f41cb4ecd23c951e1c1c4fef0c99772983a3eba4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jun 30 13:15:42 2014 +0300

    ROMCC: Fix collision with token name max
    
    Even with !defined(__ROMCC__) in the file, romcc chokes on these
    parameter names after we declare common max() macro in stdlib.h.
    
    Change-Id: Id4f2aa61d9c5b19f428452cd475b1b2ed9a70f52
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6165
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 42b716f119ea994880364a7d423841ec97d99ac7
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 26 21:38:52 2014 +1000

    northbridge/intel/nehalem/raminit.c: Extraneous parenthese
    
    Equality comparison with extraneous parenthese, spotted by Clang.
    
    Change-Id: I8d532392a0365753583ed441958e06d5da784587
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6124
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit df3629b63cc840f089cfd645fc5cf992bbbffe16
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Jun 28 17:31:58 2014 +1000

    northbridge/amd/{gx2,lx}: Qualify pointer with `volatile`
    
    There is no guarantee reading a dereferenced null pointer will not be
    optimised away. Qualify the integer storage type with volatile. Clang
    enforces this explicitness.
    
    Change-Id: I31524141d70632cade0490c820936a3a8b570346
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6148
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 38a8fb0c1891bbe3b53965e04c1c7ebcc00654da
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jun 30 13:48:18 2014 +0300

    x86 MTRR: Drop unused return value
    
    It was never well-defined what value this function should return.
    
    Change-Id: If84aff86e0b556591d7ad557842910a2dfcd3b46
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6166
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 599cda82283294944883cb17e8c2a43d96f9d2e9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jun 25 01:22:17 2014 +0300

    Use MTRR defines
    
    Change-Id: I60ae6dcb8c3b280fe74f27f4d61de70cc1ba190b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6123
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 2c342f508065db05f31ac04a9dee934759d7c039
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Jun 27 18:22:53 2014 +1000

    Makefile.inc: Detect if a working clang binary exists before set
    
    Let us not assume the 'clang' binary exists and is working just because
    the user selected it in .config
    
    Change-Id: Iad3cbf4a7cda0e1c4d435fbe426b7247233973ea
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6141
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 480790b593607c5e5d472c1aa45813b08f580cf9
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Jun 27 18:14:47 2014 +1000

    Makefile: HOSTCC set too late in clang builds
    
    Currently we set HOSTCC=clang a little late meaning some minor bits
    (utils/kconfig) are built with GCC. Move the assignment up the Makefile.
    
    Change-Id: Ic72ad808eba0c0bf508bde34fb9bf0390c0b1d4d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6140
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit d2a7523cb18e804e71eee16656deab364dbf6603
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jun 29 02:27:19 2014 +1000

    northbridge/amd/gx2/raminit.c Halt func needs noreturn attrib
    
    Missing "__attribute__((noreturn))" on halt function. This sync's the
    implementation to be the same as that of amd/lx thereby avoiding
    compiler warnings.
    
    Change-Id: Iead16125805eb36ff875fba767cf8d4e5aa86715
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6157
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ec79d7a66ec18874f3f0ac6a8e6e84f4d23be1d9
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 26 18:14:04 2014 +1000

    drivers/pc80/mc146818rtc_early.c: Silence unused func complaints
    
    Clang complains these functions are unused since they find their way
    into the bootblock of ROMCC boards by #including the .c file. These
    static inlines should probably be moved into a header in reality.
    
    Change-Id: I9d82a6befb0ac99afab6265f9d3649e419f2887d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6122
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 78d33b649e96dcb5a49f33464e234d1227e88384
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 26 22:13:15 2014 +1000

    southbridge/intel/ibexpeak/me.c: Silence warns about unused func
    
    Move some __SMM__ functions under the #if preprocessor condition to
    avoid warnings about unused functions.
    
    Change-Id: I7f6fbc6a577032bc4e4635d91e8e94aecb517bd3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6127
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit caac5ef86d1164d3f12c0486d0a2e469d0ebb252
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Jun 28 17:52:34 2014 +1000

    northbridge/amd: Remove some extraneous parentheses from if-statements
    
    Spotted by Clang.
    
    Change-Id: I38832da7b93d4ee18b8de3e80dc39513a8910221
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6149
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4d7539eefdedc4297e1529ee94df7165e2076fa1
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Jun 28 15:33:30 2014 +1000

    cpu/x86/pae/pgtbl.c: Unsigned comparison < 0 always false
    
    Comparison of unsigned expression < 0 is always false.
    
    Change-Id: Idf4e7846b50f4376a5d33515681efbd773d1caca
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6146
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2f9b3afc84de76c75dd783adc3876da3c600e6d8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 26 05:30:54 2014 +0300

    AMD boards: Fix comment style and typos
    
    Change-Id: Id630cc46b79a39e1786d42adbc21f3b9c3a051aa
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6118
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 25b56c3af514faa8a730d56fe14cae4960ac83aa
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun May 25 00:11:35 2014 +0200

    build: remove -ccopts mechanism
    
    We now use the slightly more familiar CFLAGS_* and CPPFLAGS_*
    for the same purpose.
    
    Change-Id: Ifd2bd13f67f71fa0a15611a6d11a6a4c7994271b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5875
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit d638c2b34bae222ad16670c72ad7c9a8841a3ec9
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 26 18:11:07 2014 +1000

    include/pc80/mc146818rtc.h: Inconsequential, comment ifdef maze
    
    Change-Id: Ie1ec8dbcdbbe0f2b05fdb10b1dca43cfee2a58cb
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6120
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 95b0c3d75a40cea40a15e8f7d6f56af2ebe2db77
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 26 18:09:34 2014 +1000

    arch/x86/include/bootblock_common.h: Sanitize header inclusion
    
    Sanitize the inclusion of mc146818rtc.h in bootblock_common.h
    
    Change-Id: I37d9ffd1375aedbf1f3eaa4ddce27e16166ce0b9
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6119
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 44fd0a00318a6408f77ace75ed09628eba50c0a4
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Jun 27 18:07:05 2014 +1000

    utils/cbfstool: No need to pass -g flag twice
    
    Spotted by building with Clang.
    
    Change-Id: I7ab97278d8bd586a71e453c8cc9d26dd6938c8d2
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6139
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit efe2435fec15866d803579a2b84ec299e8b42fb5
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Jun 28 19:07:33 2014 +1000

    cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII art
    
    Embedding comments inside comments is illegal in the C specification,
    Clang enforces this.
    
    Change-Id: I0a468e4196034b00dfc5860fdbbab7788e4fef77
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6154
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 9c41063713c64994083a4baddb22d41a685a95b8
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Jun 25 17:54:54 2014 +0200

    Don't add .eh_frame sections to SMM image
    
    We don't need exception handlers and they waste space.
    
    Change-Id: I98a34d1c9638e8c4168edbfb4b1cddde8a64623f
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/6105
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 91d6fc8118d1b469ca8a9fa2da66e4819edf41c4
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun May 25 00:05:20 2014 +0200

    armv7: We don't use CPPFLAGS anymore
    
    CPPFLAGS is only used as qualified variant
    (like CPPFLAGS_armv7) now.
    
    Change-Id: If8b570ace4ac92d1fdb38ca3f7fef6c79d513a95
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5874
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit b0195a3325b838bc9bdaa62a76b5125e4b694169
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 23 01:32:44 2014 +1000

    build: Pass correct disassembly flags in Clang build
    
    On SVR4-derived platforms, the character `/' is treated as a comment
    character, which means that it cannot be used in expressions. The
    `--divide' option turns `/' into a normal character. This seems to be
    needed with our local build of binutils since we don't yet use the
    internal assembler/disassembler of the Clang tooling.
    
    Change-Id: I344fc8670fd5d994f3b63308a513dd367aefc7f9
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5813
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9b229858b2b0887511ae78e1535a422795e77736
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 26 18:12:11 2014 +1000

    lib/Makefile.inc: Stop gcc.c getting into SMM clang builds
    
    The libgcc runtime workarounds found in gcc.c are not needed for
    compiler-rt used by the Clang toolchain. Stop gcc.c from sneaking into
    Clang builds while processing boards that use SMM code.
    
    Change-Id: I51e8d517784721d28b4d951bd0bebc8b52682a8e
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6121
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 0ae068efdb23fa07293dcd55b48d25a095aa062c
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Jun 21 21:42:25 2014 +1000

    src/console/post.c: Sanitize headers from preprocessor abuse
    
    Continuing on from the rational given in:
    
    a173a62 Remove guarding #includes by CONFIG_FOO combinations
    
    Change-Id: I524713b21684f6fa99355614a1ab38aee9975790
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6091
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 5e196506860889c9ef19c048e20cd68e55edb885
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jun 24 17:35:02 2014 +1000

    include/device/device.h: Header is ROMCC tentative
    
    This header is incompatible with ROMCC and its inclusion leads to 'odd'
    build failures.
    
    Change-Id: If31d774385796dcafe2fd48151e424b4c872aec3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6103
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit faaa25366030e8a02c21e0eb0c96d839ad535232
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 26 07:11:22 2014 +0300

    amd/persimmon jetway/nf81-t56n-lf: Fix whitespace and alignment
    
    Change-Id: I76f017b0919e301eeb84e73eff21170bbc921ae2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6113
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 26c6543c351b6b03b77d6f262cca812b270ecdfc
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 26 05:30:54 2014 +0300

    AMD boards: Fix typos
    
    Change-Id: I5df80e6445f390060372be8760c9b5e960e4a6e5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6117
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 8f87c3f3970745ef1f5928d91c45711cd0fd6f36
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 26 05:30:54 2014 +0300

    AMD boards: Fix typos
    
    Change-Id: If1dc4fd2204a2e4b6f84c75f385b8ff958d2251d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6112
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit efa8a9dc214946ae0fdf285e6fb8849885117d9a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 26 05:30:54 2014 +0300

    AMD boards: Fix typos
    
    Change-Id: I22180c3c2987396717864f04c59560029d088d53
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6111
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit d874757a4f92bc30d1727de47617c9cce6dc6d0a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 26 05:30:54 2014 +0300

    AMD boards: Fix typos
    
    Change-Id: I92f3877b58d9acaa9578337e66107e9cd9f46043
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6110
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 6533b83c827c5a776668776d8cf9f7b99270adfa
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 26 05:30:54 2014 +0300

    AMD boards: Fix typos
    
    Change-Id: I090e98fbf28595d3917ef84e19bd6d6742f11b94
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6108
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 9533d836d77cf126ef3954eaf8f1e3acd0a1356a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 26 05:30:54 2014 +0300

    PIRQ tables: Fix typos
    
    Change-Id: I4d8abe3841378e06515e1b3a8f22d78425d08449
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6109
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 0b4b230163c82e74e7ac9b74c0c8f8e4abe9130e
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Wed Jun 25 10:13:22 2014 -0600

    bayleybay_fsp: Switch from EHCI controller to XHCI
    
    - Disable the EHCI controller and enable the XHCI controller.
    
    SeaBIOS has been tested on the board and boots an OS from a
    flashdrive at SuperSpeed.
    This also enables the top USB port on the 2-port stack, which goes
    through a High Speed Inter-Chip port.  The HSIC port is only enabled
    through the XHCI device.
    
    Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6106
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)

commit e3c65b97b4bdd9a5ba90f03e74c02d7d3c9e1856
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 13 11:07:34 2014 +0300

    gm45 boards: Switch to use DYNAMIC_CBMEM
    
    Change-Id: Id19d31a2d114bb796b31ad61802d40c8608e4020
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6038
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 502e1dc7cae2220fc0fbc176c9c7de2d8731dd46
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 13 11:07:34 2014 +0300

    nehalem boards: Switch to use DYNAMIC_CBMEM
    
    Change-Id: Ie4df2199e746de58c926f35bc9000752d399aa37
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6037
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 6455b01fe15b96d1306c10a1bd187871b30358f1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 13 11:07:34 2014 +0300

    i945 boards: Switch to use DYNAMIC_CBMEM
    
    Change-Id: I1bbcba086f841a90544b827ae807a3c351d19d21
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6036
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 56bd2005e64f449f78d94b3b0c8743eeedaef6b9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 13 11:17:36 2014 +0300

    emulation/qemu: Switch x86 to DYNAMIC_CBMEM
    
    Change-Id: I00055064003c814b86fd1400d50bfd02fdfdf475
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6035
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit d9cf38fdcb8b1ca9a8a30e3027bc85f91e1a8ffa
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 13 11:07:34 2014 +0300

    sandy/ivy boards: Switch to use DYNAMIC_CBMEM
    
    Like with other more recent boards already using DYNAMIC_CBMEM,
    the pointer to TOC is no longer stored in GNVS for ACPI.
    
    Change-Id: If2e11294202c40793ec985e2c0c006bbfcd03d3d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6034
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit c5fff75f681ca6307d180399cdfb6697fb2cbcf6
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jun 24 16:29:12 2014 +1000

    pc80/mc146818rtc.h: Has X86 specific inlines without guards
    
    PC80 header components are winding up in ARM builds with static inline
    X86 specific code.
    
    Change-Id: Ib23e70a34c478dc099b84b59a5234539cc2482e3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6101
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 743a218a6098fc2433c844214651d0c3624d08ad
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jun 15 15:59:44 2014 +0300

    nehalem sandy ivy: Check cbmem_add() result for MRC data
    
    In theory we could run out of CBMEM space so check the entry was added.
    There is no interest to support builds without EARLY_CBMEM_INIT.
    
    Change-Id: I68dd7c20e3d3692331aaafa2a692c5c0dfce95d5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6033
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit b0cbb2cd174a55098135f3419c50ad2a8f72a1eb
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jun 17 15:04:36 2014 +1000

    drivers/intel/gma: Uninitialized var before if condition
    
    The variable 'wait' is used uninitialized whenever 'if' condition is false
                    if (val & DDI_BUF_CTL_ENABLE) {
                        ^~~~~~~~~~~~~~~~~~~~~~~~
    
    Leading to an uninitialized use occurs here:
                    if (wait)
                        ^~~~
    
    Change-Id: I7d96bf1e33b9c4312d4a0ba8276e83d17d6cd070
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6052
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 502c3db939b8c3904008b85945520c7b0d044098
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Jun 21 23:02:46 2014 +1000

    include/pc80/mc146818rtc.h: Move include to top of file
    
    Change-Id: I7640186702abac6fe116e3c750be08c958bc6cad
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6092
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 8d77402d3fa66cf0f927cd83f26fcf28866cd040
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Oct 22 16:32:49 2013 -0700

    intel/haswell: Report x32 memory as "x8 or x32"
    
    There is only one bit for memory width reporting, either x16 or
    other.  With x32 memory this code is reporting it as x8 so instead
    report "x8 or x32" in this condition.
    
    BUG=chrome-os-partner:23449
    BRANCH=samus
    TEST=emerge-samus chromeos-coreboot-samus
    
    Change-Id: I2a7c49bcb8de19084947b9dc42b93140641886fc
    Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174120
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6008
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 527b03a4d7a8b881dc4a5d16cd70a47b13f88a48
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Aug 28 09:53:50 2013 -0700

    intel/lynxpoint: xhci: Update magic bits to new magic values
    
    BUG=chrome-os-partner:22254
    BRANCH=falco
    TEST=emerge-falco chromeos-coreboot-falco
    
    Original-Change-Id: I493a8cbbfdd958b855f6b4c01e03ee524be74c6e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/167050
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    (cherry picked from commit 226a66772768bf3c2f69e585984e52c0c270821f)
    
    Change-Id: I800b02b511f9d188dd7a8e8d83139a8181346916
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/167312
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/6014
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a3119e5835e4b8fd510d046c56a3bf2bf43a5c0d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Jun 18 14:28:03 2014 +1000

    drivers/elog: Unmangle header include out of pre-proc cond
    
    Change-Id: Ic4905d8a6908a30602382f5846f1dc2c0dbe2431
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6068
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b57fef9f3e2b3cb8d8c8c5a3552c94a28ff81d15
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jun 17 20:13:08 2014 +1000

    src/ec: Sanitize headers and comment #endif pairings
    
    Comment #endif /* FOO */ pairings.
    Alphabetise headers and remove any #if CONFIG_ guards around them.
    
    Background rational:
    Remove guarding the inclusion of headers based on CONFIG_ options. This
    *potentially* could hide issues such as functions being swapped from
    under our feet, since different runtime behaviour could be declared with
    the same function same name and type-signature. Hence, depending on the
    header we happen to get may change runtime behaviour.
    
    Change-Id: Ic61bdfb64d99f0e2998c6451ae6686915b7bb3d4
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6059
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0ddb82671cae52571e92b7b22cf088939d887d50
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jun 17 18:37:08 2014 +1000

    src/console: Sanitize headers and IS_ENABLED usage
    
    Alphabetise headers and remove any #if CONFIG_ guards around them.
    Use #if IS_ENABLED(CONFIG_FOO) over #if CONFIG_FOO where applicable.
    
    Change-Id: I2a616bcfb8470a1fa21c9e26271e81cca835272a
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6057
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6c99250c3fb97ccaa03d4f0c158caffdc53ff995
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Jun 20 21:19:06 2014 +1000

    device/pci_device.c: Sanitize headers
    
    Change-Id: I6254f4ab767952cc8ff31bb462c7037b027442ba
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6079
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 618ddfeea557f076fb38f21671dcabe34411f583
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Jun 20 21:49:39 2014 +1000

    device/{cardbus,agp}.h: Missing header for device_t type
    
    Missing header for the ramstage version of device_t which is a struct
    ptr.
    
    Change-Id: Ie2a30b75ee1d0513397276b81e8df1d995707f6f
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6080
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b393fa09e565af929474c442a62589ad1d73acbf
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jun 21 23:50:53 2014 +0300

    AGESA S3: Fix ACPISCRATCH in CBMEM
    
    After commit
    
      2ca2afe ACPI S3 support: Add acpi_s3_resume_allowed()
    
    ACPISCRATCH region in CBMEM was no longer allocated, causing
    AGESA platforms to fail S3 resume.
    
    IS_ENABLED() did not evaluate true here with non-zero parameter.
    
    Also avoid multiple defined defaults for HIGH_SCRATCH_MEMORY_SIZE.
    
    Change-Id: Id99e4bee91581b8ac3d1ec44763b2d792b721832
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6093
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit 4f7cb87df2a4b2d1da6c1e759a3a69bc36626850
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 19 03:48:42 2014 +0300

    AGESA: Move config parameters for non-volatile S3 data
    
    These parameters are not specific to the southbridge device, but
    the implementation of S3 storage defined by CPU code.
    
    Change-Id: Ic341cc2b7669cf8e3e920c48473826ec03fc7d8d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6081
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 207880cd1127acd6f5f0f2241d753aa6b1c39da0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Dec 10 09:03:17 2013 +0200

    Declare acpi_is_wakeup_early() only once
    
    Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4525
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 206f37043ed4c8581c7351399c267434653ec13b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jun 14 21:01:22 2014 +0300

    i945 boards: Drop disabled ram_check() calls
    
    This code would not get enabled just by flipping the options in menuconfig,
    also ramcheck() no longer test the range like the parameters would imply.
    
    We should add non-destructive ram_check() on S3 resume path to verify
    memory controller configuration has been properly recovered.
    
    Change-Id: Ie4675c4770146c4312cdfbc81afa19f243f90ee4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6027
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bd4553bb4c594ff5098fc7c4c85133aab163705e
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Mon Jun 16 10:46:56 2014 -0600

    MP Table: Change types to be consistent with the spec
    
    Update the elements in the MP Spec structures with
    appropriate types to more accurately reflect the
    real sizes of the bit fields in the MP Tables.
    
    Also add a function for PCI I/O interrupts since these are
    handled slightly differently than the other I/O interrupt
    entries.  The src_bus_irq field is defined where
     Bits 1-0: PIRQ pin: INT_A# = 0, INT_B# = 1, INT_C# = 2, INT_D# = 3
     Bits 2-6: Originating PCI Device Number
     Bit 7: Reserved
    
    Change-Id: I693407beaa0ee454f49464e43ed45d8cba3b18fc
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6050
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e96f4b1122fea74b8f9933fcefa1a2d5a616b39f
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sun Jun 22 22:05:24 2014 -0600

    baytrail_fsp: Fix the mmconf Kconfig
    
    The override value in the mainboard that was removed was correct.
    
    Change-Id: Ie820df0d6b7a713488173240f0c0ca4a9e108f71
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6095
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit fbd150383954671bdeeef9c8161cabd9bbe0627b
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Fri Jun 20 21:21:51 2014 -0600

    fsp_baytrail: Minor Kconfig updates
    
    - remove the Kconfig text when setting the default for the FSP location.
    The text was showing up twice in the config menu.
    
    - Remove an extra 'the' in the help text.
    
    Change-Id: I3777833bf32e19bbe5a8493578a9346d6ab062a4
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6090
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 2c28ee83cb00af16fe48d72133e668291b1d2a04
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Fri Jun 20 21:10:09 2014 -0600

    bayleybay_fsp: Add comments for the MMC/SD devices in devicetree
    
    This just adds some additional comments for the EMMC / SD / SDIO PCI
    devices in devicetree.
    
    The documentation states that the EMMC 4.1 device shouldn't be used,
    but it's available to enable in the FSP.  Because it can be enabled,
    I've included it in the devicetree even though its use is discouraged.
    
    Change-Id: I64633fe1908368f69a8d4031aa900b0bceb2189e
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6089
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a173a6255b5c3b7febea5cdf581fc3a57299954a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jun 17 17:05:36 2014 +1000

    Remove guarding #includes by CONFIG_FOO combinations
    
    First of many to remove guarding the inclusion of headers based on
    CONFIG_ options. This *potentially* could hide issues such as functions
    being swapped from under our feet, since different runtime behaviour
    could be declared with the function same name and type-signature. Hence,
    depending on the header we happen to get may change runtime behaviour.
    
    Change-Id: Ife56801c783c44e1882abef711e09b85b7f295a4
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6055
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9107e53756e158cf2b5803862b731577407265d5
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 19 20:52:39 2014 +0300

    cpu/amd/agesa: Use acpi_is_wakeup()
    
    Change test to return true on S2 wakeup too. In S2 CPU would
    have been powered down so MTRR recovery is required.
    
    Change-Id: I6ad5fb7e32c59be7d84f28461c238c3975e1e04e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6078
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c551caae56535b056be0440b08bd57e24459242c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 20 12:31:23 2014 +0300

    AMD cimx/sb800:  Use acpi_is_wakeup_s3()
    
    Change-Id: If237c2fcd52f50d5fa0cad5a02a941386b085f2e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6077
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8ae16a44a4a588c8ae81979634ddee681db4f804
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 19 20:44:34 2014 +0300

    northbridge/amd/agesa: Use acpi_is_wakeup_s3()
    
    Change-Id: Ia6f5b0454e7fbbf36baa2372dfeec51b5f5e8f67
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6076
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 58ceb00ea7a76040f9e4cada7073ee68a3b4455d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 20 06:21:01 2014 +0300

    PCI VGA ROM: Use acpi_is_wakeup_s3()
    
    Change-Id: I6f9c992f1a68025ed18de57c5856b3bf9a673bfb
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6075
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9d9eb1ec8d6f30fa000aa87246310757214337d5
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 20 05:38:07 2014 +0300

    PC80 RTC: Use acpi_is_wakeup_s3()
    
    Change-Id: Idc4c47f3802019c2853ec71f8e9c057c3ab8d3ee
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6074
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6202aea9220f6a423429cba625c0444f88f9bb58
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 20 05:41:21 2014 +0300

    PS2 keyboard: Use acpi_is_wakeup_s3()
    
    Change-Id: I812cc40e50a1e7e13caed48a1693feb8658b645c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6073
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c3c4a38c95b90fbf713e98f7b4d1e5be18bee633
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 20 05:21:30 2014 +0300

    Misc: Use acpi_is_wakeup_s3()
    
    Change-Id: I46906e6d68775edc5cfe199cfeb465db4da2691f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6072
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c3ed88636a3533b97cef5bcb445cbe61edbfae7f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 19 19:50:51 2014 +0300

    intel boards: Use acpi_is_wakeup_s3()
    
    Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6071
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 49380b87d114cf4c1bd6f0692f43e89e73f662b8
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jun 16 16:48:44 2014 +1000

    superio/smsc/fdc37n972: Trivial cleanup reorder headers
    
    Alphabetise headers and a few trivial cleanups.
    
    Change-Id: Ib8c8362962297cb59671d8274df8e4945373f94b
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6042
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 29179f0735e5a73b024008f218a79dfb04193c69
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Jun 12 16:28:21 2014 -0600

    superio/nuvoton: Add chip support for setting IRQs to edge/level
    
    Change-Id: I08b9eef9d6b0f120c17c3293f1f90b847742dc06
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/6064
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit da2daef4b43ac85657429fe9b3f4a6d18179d48d
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Mon Jun 9 12:33:24 2014 -0600

    superio/nuvoton: Adds a function to route pins 41-48 to UARTD
    
    Pins 41-48 default to being GPIs. This switches the internal
    mux to connect them to UARTD.
    
    Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5963
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7bf4f484c08e7256175e0db3024d3b76ba58613f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jun 17 15:12:09 2014 +1000

    southbridge/intel/lynxpoint/me_9.x.c: Use IS_ENABLED macro
    
    Silence unused function warnings, spotted by Clang.
    
    Change-Id: I5127893e9605ca490ff450faa92af5e9eafe8940
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6054
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 22e9e66cacafc4f403b3b51f42cfecaf1a4be63b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jun 16 14:09:10 2014 +1000

    superio/ite/it8772f: Remove prototypes for func with no body
    
    Change-Id: Iaf5db7153b08ac81b233f967c7a604ed08af91ca
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6040
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 114f0ee9d4bbcfc7fc4a68d2bf7f2eeabde45efb
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jun 16 13:27:57 2014 +1000

    src/mainboard/google/*/mainboard_smi.c: Remove #include .c's
    
    No need for these.
    
    Change-Id: I1df6e2ef06bd5546a66ee05a15fa2f7c3daf8853
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6039
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 4c960d4ebe2f5ef486cf31fdeb9b92033642d907
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Jun 5 22:12:06 2014 +0200

    google/link, lenovo/x60: i915io.c: Use define `ARRAY_SIZE`
    
    Change-Id: I8ddd46a573b61eba685efcc15456f288645d214d
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5936
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit d309eb145dbb0e79b0b678dc623949e12c15e02f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 30 11:35:33 2014 +1000

    mainboard/jetway/nf81-t56n-lf: Port recent Persimmon changes
    
    Port to recent reference board (AMD Persimmon) changes in commits:
    
    c93a75a AMD/CIMx: Add functions for AMD PCI IRQ routing
    
    Change-Id: I307709bfee554bc64788a973da6d9313ca7c0de2
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5882
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>

commit 4d9b77287e583c89fea4bac9f1c264b01dcab981
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 19 19:45:40 2014 +0300

    ACPI: Add acpi_is_wakeup_s3()
    
    Test explicitly for S3 resume.
    Also switch to use IS_ENABLED().
    
    Change-Id: I17ea729f51f99ea8d6135f2c7a807623f1286238
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6070
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6722f8da400ccb5553afe745ff71475c50d60f52
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jun 16 09:14:49 2014 +0300

    sandy/ivy boards: Use acpi_s3_resume_allowed()
    
    Change-Id: I8e0d43293e095c1c76c3cfef1f426737624ea37f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6063
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit bb805e156a6c464454ff1622a638e8ab768732bd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jun 16 09:14:49 2014 +0300

    nehalem boards: Use acpi_s3_resume_allowed()
    
    Also update packardbell/ms2290 to match lenovo/x201.
    
    Change-Id: I6bda740cadd81ebe47e57742c507bff322a9fb0e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6062
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 12d681b23f4c1e24cb31f5f253ec42290ca9c5ee
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jun 14 18:51:34 2014 +0300

    intel/i945 gm45: Use acpi_s3_resume_allowed()
    
    Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6061
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 2ca2afe760bf1f78ee410749332d85f9413a9f3a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jun 17 15:41:37 2014 +0300

    ACPI S3 support: Add acpi_s3_resume_allowed()
    
    Add this to reduce the amount of preprocessor conditionals used in the source,
    compiler currently resolves this to a constant.
    
    Once we have gone through all #if CONFIG_HAVE_ACPI_RESUME cases, we may change
    the implementation to enable/disable S3 support runtime.
    
    Change-Id: I0e2d9f81e2ab87c2376a04fab38a7c951cac7a07
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6060
    Tested-by: build bot (Jenkins)

commit b3594ab4899aebf3883694fabe469a414dd9a799
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jun 18 00:43:35 2014 +0300

    util/cbmem: Workaround for IS_ENABLED()
    
    Our include files reference CONFIG_xxx declarations, which we should
    ignore for utility build.
    
    We cannot include kconfig.h to get IS_ENABLED() as that file
    would require build/config.h and we do not want to enforce a build
    of the firmware to be able to build the utility.
    
    Since we do not include build/config.h each occurence of CONFIG_xxx
    in the included header files is undefined and will be treated as
    disabled.
    
    Change-Id: I74f1627fc3f294410db8ce486ab553dac9e967f4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6066
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8fac0b3e904138f0642d7ab29c5867002aebf686
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jun 17 18:53:36 2014 +1000

    src/lib/clog2.c: Fix style and clarity, remove some cruft
    
    Change-Id: I6b37cf945db12d2cf8096c9f49fff9e0bec139d6
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6058
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 669cb2f0c4af8f01ac1d83d854258287077bbe95
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Jun 17 15:09:51 2014 +1000

    drivers/intel/gma: Equality comparison with extraneous parentheses
    
    Spotted by Clang.
    
    Change-Id: I3e612c0fa050a09fa7e5b1cb643935b84eb2b957
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6053
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 3722f3c3f5e77763319ccd635405fff53139959f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 19 22:34:02 2014 +0300

    supermicro/h8scm: Fix Kconfig
    
    Change-Id: I0ecc3c5a26251f248234244bf305d3e13e41b9e9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6069
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 17290e4b6c80528baac1bcb5c2e33dbb5aa509be
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 13 11:21:13 2014 +0300

    intel/bayleybay_fsp: Drop redundant EARLY_CBMEM_INIT
    
    This is implied from DYNAMIC_CBMEM from soc/.
    
    Change-Id: I8cd8c2dff723950377998750377a3168f1f5fc5b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6029
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Martin Roth <gaumless@gmail.com>

commit de38eeaaa6d27b25efc5c7c8ea2b09090f9241f0
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jun 12 12:31:59 2014 -0600

    fsp_baytrail: Add the default FSP location
    
    The default FSP location needs to be in the chipset, not the mainboard.
    This was removed from the Bayley Bay mainboard in patch 41ea7230f7
    reviewed at http://review.coreboot.org/#/c/5982/
    
    Change-Id: Ia26ed34e1401cbd2303166628e7a4e357d79c874
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5985
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)

commit c0602d4cab34ee228465c2779dda400b367082b6
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jun 12 12:38:34 2014 -0600

    fsp_baytrail: Add Baytrail B0/B1 "Super SKU" microcode
    
    - Add the Bay Trail B0/B1 microcode.  These versions of the SOC were
    released as a "Super SKU" which had features of all the different
    SKUS (M/D/T/I), and identified as a Bay Trail T as noted by the
    number 2 in the third character from the left in the microcode name.
    
    - Update the size of the microcode blob.  We should be pushing a patch
    to eliminate the need for this shortly.
    
    Change-Id: I57ba51eabe9ea0609ab809f18b95e3bc9d5cb191
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5986
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit c94d73e0e6703369831fe6d489a20d71ab2bb974
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jun 16 17:24:14 2014 +1000

    mainboard: Clear up remaining SIO_PORT from Kconfig
    
    Push back any board specific values back into romstage.c #defines and
    drop any remaining fragments of CONFIG_SIO_PORT in-tree.
    
    Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6045
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 401b8accf8fdade02f40f528812ac081c7a0f432
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jun 16 17:09:27 2014 +1000

    mainboard/amd,lippert: Drop SIO_PORT from Kconfig
    
    CONFIG_SIO_PORT is not used anywhere and should not be here any way.
    
    Change-Id: I39eb2d668f1da9f89b7ff6eb219af1a48cb29232
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6044
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit dfc0c13b1ae1027743e80126855c615c72ffb609
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jun 16 17:02:24 2014 +1000

    mainboard/jetway/nf81-t56n-lf: Drop SIO_PORT from Kconfig
    
    CONFIG_SIO_PORT is not used anywhere and should not be here any way.
    
    Change-Id: I2e7be4337f7f46298b9ca5bd613c58deec2cb01a
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/6043
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit a0b4a8d8197421b6454d0614deeef1eef575bdd1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jun 15 14:28:23 2014 +0300

    ACPI: Remove CBMEM TOC from GNVS
    
    This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.
    
    Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6032
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit c862e441627468cd8b27436a26b0153010f491c5
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jun 14 15:25:33 2014 +0300

    northbridge/intel: Drop use of set_top_of_ram()
    
    We implement get_top_of_ram() on these chipset to resolve CBMEM
    location early in romstage. Call to set_top_ram() is not required.
    
    Change-Id: I492e436b0c32d2c24677265b35afd05f29dcd0f8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6031
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 191d221920143d47032997c48654f0d74e83e86e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jun 15 12:06:12 2014 +0300

    intel/nehalem: Add get_top_top_ram() in ramstage
    
    Needed to resolve CBMEM location early in ramstage. With DYNAMIC_CBMEM
    set_top_of_ram() will no longer be available.
    
    Change-Id: If50f1c5455a587b096348ffedadbe1dd2350a714
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6030
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit aac45febc78c2e3254fc6ed58ad8b81ce59bbf26
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jun 15 12:00:08 2014 +0300

    emulation/x86 : Drop HAVE_ACPI_RESUME
    
    S3 resume detection not implemented in romstage.c.
    
    Change-Id: I98277cb483825af2e6c5c8eefa4598b117613478
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/6028
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit a1e924ca6b5c8ce84625ac525db117391e5f872f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 6 08:32:42 2014 +0300

    mainboard/supermicro/h8dme: Drop unused code
    
    Clang complains about a unused debug function, so remove dead code.
    We have copy of dump_smbus_registers() in amdk8/debug.c.
    
    Change-Id: Ibf46deb1de1589d81760841b1d4ba319707915aa
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5942
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit f565ab0e2500090f9392d83c7b0e8b8bbab67ce4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat May 31 17:08:40 2014 +0300

    lenovo/x60: Fix build issue with DO_NATIVE_VGA_INIT
    
    Use the value from hardware for uma_memory_base.
    
    Change-Id: I70351166db6634ef3bca2bf12051ccc3730cab8e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5893
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit cc483aee964f26d064555c581db257202ec3e494
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Feb 4 21:19:51 2014 +0100

    intel/model_2065x: Add 20652 microcode.
    
    Change-Id: I2a46806a3f0a57497edebd49e69b97f90948adb9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5117
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit cbc783f3e1b31b03e163af928fee8d67dfd6678e
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Jun 6 15:21:28 2014 -0600

    Persimmon: Change MPTable to use mainboard IRQ routing
    
    With the addition of the mainboard PCI IRQ routing tables
    for AMD Persimmon, the MPTables can be set to use this
    information to accurately reflect the real hardware settings
    of the system.  Additionally, the IOAPIC gets defined before
    the MPTable gets generated so the settings can be read
    directly from the IOAPIC registers instead of 'guessing' at
    them as was done before.
    
    Change-Id: I96ec046a2208eddf4b5e442214ff43d2a349ca4d
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5878
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit d0167d3ae268e3fcdef5c02e381b47dbb04ab1a4
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Wed Jun 11 14:20:48 2014 -0600

    MP Spec: Correct the Virtual Wire assignment
    
    Virtual Wire mode is set by writing 0 to the the MPTable
    Feature2 bit field 'IMCR'.  The virtualwire variable was
    initially defined as writing a 1 to this bit field which
    would actually set PIC mode instead of Virtual Wire mode.
    However, nearly every mainboard called the MPTables with
    virtualwire = 0, which actually had the effect of setting
    Virtual Wire mode. I am correcting the definition but
    leaving the call to write the MPTables with virtualwire = 0,
    which is how most mainboards are already setting the tables
    up.
    
    See the MP Spec table 4-1 for more details:
    	Bit 7: IMCRP. When the IMCR presence bit is
    	set, the IMCR is present and PIC Mode is
    	implemented; otherwise, Virtual Wire Mode is
    	implemented.
    
    http://download.intel.com/design/archives/processors/pro/docs/24201606.pdf
    
    Change-Id: I039d88134aabd55166c2b68aa842bacbfcc0f42b
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5977
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 915973406544d1d6a60a539ad9fb8a33c3caf2c9
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Thu Jun 12 10:22:27 2014 -0600

    MP Spec: Add copyright header
    
    Adding the copyright header to the MP Spec files because
    they were not included before.
    
    Change-Id: Ifcd217a53bf8df19b28e251a7cac8b92be68d1fc
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5981
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit f7d8f09d7637915c98fca4832d4085aec949c7e0
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 31 13:57:52 2014 +1000

    amd/agesa,cimx: Rename ACPI OS detection methods
    
    Try to 'standardize' the otherwise peculiar method naming to be somewhat
    more in-line with other ACPI implementations. This makes it easier to
    compare with vendor DSDT dumps for example.
    
    Change-Id: I5ba54f7361796669ac0cab7ff91e7de43b22e846
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5888
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 7a22b0976c16d09eed5ab07beb28942fe70b8b43
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Jun 6 09:51:23 2014 +1000

    amd/agesa/f15tn: Invalid inline asm in gcc-intrin.h
    
    Forward port commit:
    db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm
    
    Change-Id: I87bf101b15bac7c06afa9cec10e2bd4e0cdfd6c7
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5941
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 3628f93cf5d671e4b63c6cda559f58d4721bdba1
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed May 21 07:00:48 2014 +1000

    mainboard/ibase/mb899: Break out superio hwm conf from mainboard
    
    Break out the PNP Super I/O HWM configuration from mainboard.c
    
    Change-Id: Ib4c7f26c7fa2a9845250a61a23c75cb9e440ab93
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5797
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit e93fe2344066e7471e82dacdaa53c9ed9a9b38e3
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 22 06:16:15 2014 +1000

    amd/agesa/f14: Backport f15tn fixes from DDR3 in mtspd3.c
    
    Change-Id: I710efc3171e1653241f2dba1217a9560d2d99a16
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5802
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit cd30951e3243b1d67c36408aa94760955d9e4503
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jun 12 14:29:27 2014 +1000

    mainboard/amd: De-ASCIIartify reference boards
    
    For anyone who knows the difference between a header and a variable in C
    these depictions are rather useless. Thus, these lines wast essential
    screen real estate while working on coreboot.
    
    Change-Id: I7fe55d936c035ef83832716c45bfc57d73c0edc7
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5979
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 0baaa2d5a71a2aae6e1b5a4a2fbe9a6abe0d359a
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jun 12 12:20:26 2014 -0600

    fsp_baytrail: remove version from default vbios path
    
    Intel requested that we remove the version number from the default
    vbios path.
    
    Change-Id: I2590fed0db157e3e430212336fc55eb099d28a72
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5984
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit d866e5872d5570fded81a4d392884725009a17dd
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Wed Jun 11 09:35:37 2014 -0600

    fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOT
    
    While pushing the fsp_baytrail code, it was requested that we change
    CONFIG_ENABLE_FAST_BOOT to CONFIG_ENABLE_FSP_FAST_BOOT.
    
    These were missed in the change.
    
    Change-Id: If8af3f90b0f5cc9154ff1d3a387f442430f42dee
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5972
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 4dfc50b8773a2ddc3f87f9e6d988de1d8751ba53
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Jun 13 08:47:32 2014 +0200

    mainboard.c: Fix typo in appro*p*riate in comment
    
    Use the following command to fix all occurences.
    
    	$ git grep -l approriate | xargs sed -i 's/approriate/appropriate/g'
    
    Change-Id: I4cbba972bb445c2407ef2e63ffb3068fc948f1c6
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5987
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 9b800ae9547ed5890773fd6e12781a49cf3fcfc4
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Jun 11 13:15:56 2014 -0600

    southbridge/amd: Change #if defined to #if IS_ENABLED
    
    The IMC functions were being called and timing out when the
    CONFIG_SB800_IMC_FWM/CONFIG_HUDSON_IMC_FWM were defined as 0.
    Changing to a IS_ENABLED will keep the IMC handshake from
    occuring if the IMC firmware isn't running.
    
    Tested on a Persimmon platform which makes three calls to
    spi_claim_bus() with each call timing out after 500ms.
    
    Change-Id: I5d4bbcecf003b93704553b495a16bcd15f66763b
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5974
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 41ea7230f7c8a94d20d8eefc908e250b359b7cf0
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jun 12 10:34:47 2014 -0600

    bayleybay_fsp Kconfig: Remove unnecessary overrides
    
    Use the default mmconf base address and fsp locations.
    
    Change-Id: Ia9116b0f0fc799592df2a10b10e086cfc88b394c
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5982
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 33eaf3a715e258597ca7924c94739433a343d1e6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 6 21:46:47 2014 +0300

    superio/smscsuperio: Fix chip detection
    
    There was dereference of NULL dev->ops in pnp_enter/exit_conf_mode()
    as those calls were made before pnp_enable_devices() was run.
    Since hardware did not enter configuration mode, detection failed with
    ID and REV read as 0xff.
    
    Change-Id: If13086707cd86e392890ccf4f717e13a87f3317f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5949
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.h@gmx.de>

commit afc8d987692ece2272ce902fbdcbddc303d0eca8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Jun 11 18:52:55 2014 +0000

    intel/bd82x6x: Skip unknown MBP.
    
    Allow skipping unknown MBP rather than bailing out.
    
    Change-Id: I9a54858c37d73e320de77aea5a05ab5dcf67cd69
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5976
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 209238755a0efaba26622c4160969391dfa5a39f
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Jun 7 13:31:29 2014 +0200

    device/device_util.c: Fix wording in comment of `new_resource()`
    
    Change-Id: Ieb0d5de37870a359f3a7ea1543640e26f86c1684
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5952
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ac1b875b554f45b0c98d375369119495b7ad2a2a
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Jun 5 14:30:22 2014 -0600

    amd/southbridge/lpc: SPI BAR has fixed size/location
    
    The CIMX sb700/sb800/sb900 and agesa/hudson code was treating
    the LPC SPI BAR as a normal PCI BAR. This will set the
    resources for a fixed size at a fixed address. This was tested
    on hp/abm, amd/persimmon, and gizmosphere/gizmo boards.
    
    Change-Id: I1367efe0bbb53b7727258585963f61f4bd02ea1d
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5947
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 61f902d4a7779d0ce30de79df7a71ad0c3788887
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jun 7 16:41:14 2014 +0200

    ibexpeak: Set number of USB ports.
    
    Change-Id: Ife3febcc88967386dfae624cd237562a34a68471
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5956
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 49c3045c2dc6852c80e6fa7fca8ecf2a9ecf3c06
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jun 7 16:30:35 2014 +0200

    ibexpeak: Remove some dead code.
    
    Change-Id: I68ae49d20a2524f03c4503f2b3be93f07b9cb6e3
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5955
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit c93a75a5ab067f86104028b74d92fc54cb939cd5
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Jun 6 15:16:29 2014 -0600

    AMD/CIMx: Add functions for AMD PCI IRQ routing
    
    The PCI_INTR table is an Index/Data pair of I/O ports
    0xC00 and 0xC01.  This table is responsible for physically
    routing IRQs to the PIC and IOAPIC.  The settings given
    in this table are chipset and mainboard dependent, so the
    table values will reside in the mainboard.c file. This
    allows for a system to uniquely set its IRQ routing.
    The function to write the PCI_INTR table resides in
    cimx_util.c because the indices into the table have
    the same definitions for all SBx00 FCH chipsets.
    
    The next piece is a function that will read the PCI_INTR
    table and program the INT_LINE and INT_PIN registers in
    PCI config space appropriately.  This function will read
    a devices' INT_PIN register, which is always hardcoded to
    a value if it uses hardware interrupts.  It then uses this
    value, along with the device and function numbers to
    determine an index into the PCI_INTR table.  It will read
    the table and program the corresponding value into the PCI
    config space register 0x3C, INT_LINE.  Finally, it will set
    this IRQ number to LEVEL_TRIGGERED on the PIC because it is
    a PCI device interrupt and the must be level triggered.
    
    For example, the SB800 USB EHCI device 0:18.2 has an INT_PIN
    value hardcoded to 2.  This corresponds to PIN B.  On the
    Persimmon mainboard, I want the USB device to use IRQ 11.  I
    will program the PCI_INTR table at index 0x31 (this USB device
    index) to 11.  This function will then read the INT_PIN register,
    read the PCI_INTR table, and then program the INT_LINE register
    with the value it read.  It will then set the IRQ on the PIC to
    LEVEL_TRIGGERED by writing a 1 to I/O port 0x4D1 at bit position 4.
    
    Also, the SB700 has slightly different register definitions than
    the newer SB800 and SB900 so it needs its own set of #defines for
    the pci_intr registers.
    
    Only the Persimmon mainboard is adapted to this change as an
    example for other mainboards.
    
    Change-Id: I6de858289a17fa1e1abacf6328ea5099be74b1d6
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5877
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit ce740c474c3590dcb0da184d7663adf1f1d78ea8
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Jan 3 16:54:56 2014 -0700

    PIC i8259: Move #defines and functions to i8259.h
    
    The PIC i8259.c file has a lot of #defines and function
    definitions in it.  I am moving these to the i8259.h file
    and also adding a few functions to update the PIC IRQ mask
    register.  The PIC default configuration has all of its
    interrupts masked off except for IRQ2.  IRQ2 is where
    the Slave PIC is cascaded from the Master PIC.
    
    Change-Id: I78d505358c29fadbc184137a09120863ea1d5c13
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5950
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f5a2d2607f2879067db761462aecb79c9c52b434
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 6 22:57:01 2014 +0300

    lippert/toucan-af: Fix comment on HAVE_ACPI_RESUME
    
    S3 resume is expected to work now, however the 3s delay and flash wear
    is still there.
    
    Change-Id: I7edbce7bcf9c2160099fd5e371562b1ec63d45d8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5971
    Tested-by: build bot (Jenkins)
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 1b6aef754e2bbc15755f6eb26835974775e600c6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 6 22:57:01 2014 +0300

    lippert/frontrunner-af: Fix comment on HAVE_ACPI_RESUME
    
    S3 resume now works, however the 3s delay and flash wear is still there.
    
    Change-Id: I9d2eda5454baf7704807cf67f3aca94a67de3406
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5970
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>

commit 8ef20cf9225b0af6b0b16aa71cccb65e434a3df1
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Jun 5 14:21:11 2014 -0600

    amd/hudson: Add the IOAPIC space to the fixed resources table
    
    Without this change the IOAPIC memory window would collide
    with PCI config space. This was tested on the hp/abm board.
    
    Change-Id: I5dd53463961f75bab80a41dc7beff8d0434b24ae
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5946
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit bccd408169b400e708248db317006da8b2332e2a
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Fri Jun 6 06:52:28 2014 -0600

    amd/family16kb: Move and resize the MMIO region
    
    The Kabini MMIO region was assigned a 256MB region at
    0xA0000000. That location is below TOP_MEM and is getting
    carved out of useable system memory which is not being
    reclaimed above 4GB. This changes its size to 64MB and
    moves it to 0xF8000000.
    
    This was tested on the hp/abm and asrock/imb-a180 boards.
    
    Change-Id: Ib226bc954311a3a2a15f182ab4618f4924e95a5b
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5945
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 601da481b5437c7a73f97a1bece5990a393037d8
Author: Damien Zammit <damien@zamaudio.com>
Date:   Mon May 26 23:00:23 2014 +1000

    util/inteltool: Add pci ids for 4 northbridge models instead of 1.
    
    This patch supports northbridges: 0x0150 0x0154 0x0158 0x015c as 3rd gen core.
    Tested on 0x0150 (0x0154 previously only model).
    
    Change-Id: I53a33d864494dd4ac1cb9e8330450f56001ed92c
    Signed-off-by: Damien Zammit <damien@zamaudio.com>
    Reviewed-on: http://review.coreboot.org/5873
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 0240f9492b79509c5b679190853405dc218244f0
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Jun 5 12:01:36 2014 -0600

    nuvoton/nct5104d: Update the #defined LDNs
    
    Change-Id: I4e4bc09a8f8fabe68519a29dc421af82c76c9873
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5944
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit da09d02c57ac4f48347087d9d1663a042a541e13
Author: Felix Held <felix-coreboot@felixheld.de>
Date:   Sun Jun 1 21:44:43 2014 +0200

    superio/nuvoton: factor out generic romstage components
    
    The romstage of Nuvoton Super I/O chips (but not Nuvoton BMC chips)
    is identical, so the early_serial.c file can be moved under
    nuvoton/common.
    The Nuvoton BMC chip WPCM450 is however left untouched.
    
    Change-Id: I4663176c1003b24a49a9fe5f9ebd27a1963b5565
    Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
    Reviewed-on: http://review.coreboot.org/5909
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit ef9343cac1917308c13c331d4fdef8d1eb799e9a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 11:42:55 2014 +0300

    AGESA: Use common heap allocator
    
    Change-Id: I5df1f0efdef2592b762fe391edaadbca4593e85a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5689
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6025efa3472f38d719d850d2143dae0b215db0f3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon May 5 13:20:56 2014 +0300

    AGESA: Use common GetBiosCallout()
    
    Change-Id: I9c8f7cc98c65102486e17ec49fa2246211dffc4f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5688
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 83cc3b0ed5f522e8ab23b9a9cab8f89bbb65c9c3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 23:13:08 2014 +0300

    AGESA fam15tn fam16kb: Use shared default callouts
    
    Change-Id: Ibbb07ef308c7e92a8a8dfe066f5e3866d5f8aee2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5687
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cb989f2c3c6763e03d90be06517b64dd03f1caf4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 23:13:08 2014 +0300

    AGESA fam15tn fam16kb: Use common handler for GNB_GFX_GET_VBIOS_IMAGE
    
    Change-Id: I158993bcb654ef27a9fc6b7e9dc3fc955fb740fa
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5686
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bc844500824fe415ab01bd3efa3d39b5047c823a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jun 3 12:04:37 2014 +0300

    Drop unused change_i2c_mux()
    
    Change-Id: I3ac39441746d739ac19e831bb67c76405c24ba27
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5925
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit f5bde44df2ff954c8af9fd6ab50453f491983dab
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jun 2 12:20:11 2014 +1000

    superio/smsc/kbc1100: Virtually rewrite support and fix mainboards
    
    1. Remove #include .c in romstage.
    2. Make romstage component symbols linker-time.
    3. Provide header guards and prototypes in superio romstage support.
    4. Correct function type-signatures to be static/non-static where
    appropriate, avoid 'pretend optimisations' by unnecessarily inlining
    functions.
    5. Separate out UART enable from various other PNP hard coding
    
    Change-Id: I9b8dad7c02d802e97db73ddf2913d5c6bb33a419
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5916
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 4ba8ba4654aef66283db5a69e40586fb9e186b5a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 23 01:29:00 2014 +1000

    build: Drop libgcc runtime wrapper in Clang builds
    
    This GCC specific workaround of wrapping of libgcc runtime symbols with
    gcc.c is not nessary with libcompiler-rt linkage.
    
    Change-Id: I50a2bc99d97f68a2ad2b51a92ea0e7086bab35fe
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5812
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit fdceb48b3623f8d342c9138feb8ee0db61a79f24
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Jun 2 07:58:14 2014 +1000

    superio/smsc/smscsuperio: Make romstage linkable with header
    
    Rewrite smsc/smscsuperio romstage component to be more consistent and
    provide header there-by removing #include's of early_serial.c's in
    mainboard's.
    
    Change-Id: I572e0c76422f09d4de88935a36c0a59e5350e6e0
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5915
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 8f45761a67347050058537f6a6cd75489af6c1d8
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 15 20:30:49 2014 +1000

    superio/ite/it8661f: Make early_serial into romstage sym
    
    Following similar reasoning as commit:
    d304331 superio/fintek/f81865f: Avoid .c includes
    
    Avoid any mistaken future inclusion of early_serial.c in mainboard.c
    code by providing symbols in romstage.
    
    Change-Id: I9e763a7ad9de090e35acdcf4d6a280d8227c6015
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5508
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 6fb379a1dbd60fcdd8ad30550b708ed1b9e3fa7d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jun 1 17:38:22 2014 +1000

    mainboard: Remove #include early_serial.c from w83977tf boards
    
    These non-ROMCC boards #include the model specific w83977tf Super I/O
    romstage component. The generic winbond_early_serial() function serves
    well here to further tighten integration into the new Super I/O
    framework and drop dependence on #include'ing .c files, leaving only
    ROMCC boards.
    
    Change-Id: Ib63c0f29f994c54e6112702506f288535799706c
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5898
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit aef5594f7409636cfbe2c7ebb23da041e36cd7f6
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jun 1 20:30:28 2014 +1000

    superio/ite/it8772f: Depreciate early wdt functions
    
    We have better written generic implementations of these functions
    introduced in commit:
    
     a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers
    
    Change-Id: Ic93d78fce18c68d1d1bf3b537e8985a2532a8fcf
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5901
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 1b3acb13e49753e53192d3e5b939713329d0d205
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jun 1 18:04:05 2014 +1000

    superio/ite/it8772f: Move towards removing #include .c
    
    Move samsung/stumpy board towards generic romstage component and away
    from poorly written hard-coded model specific Super I/O component. This
    is an incremental step towards getting obj-level abstraction between
    board and Super I/O.
    
    Change-Id: I358c5abef85c2ffa1b7178025cde8834a35b0a51
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5899
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit d235da108b38ad45f20c3e556e630b10fb16634e
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Jun 3 00:15:30 2014 +0200

    northbridge/intel/i945/gma.c: Add and use defines for `GMADR` and `GTTADR`
    
    Change-Id: I0f39b35fbf8e053ba21454a2847d6bb3ac5d2e1c
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5923
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 50684638bea678d6aec94c1345b45684a627fded
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Jun 3 00:26:03 2014 +0200

    northbridge/intel/i945/i945.h: Move define `BSM` to section D2F0
    
    The Base of Stolen Memory (BSM) register belongs to device 2,
    function 0.
    
    Change-Id: I2381f87ffaccb2f8034c160fc30c1d92f8b19402
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5922
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 12fcb86bba5004ce1b6f8172a08e6d89de2cfed8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Feb 23 00:09:48 2014 +0100

    sandybridge: Pass chip info to i915lightup.
    
    Change-Id: I280441aadb0575dc0b99584cdcd48cc76a0289a2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5284
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit fd2501b3f1af1d649484dcdae562cd0694eb61ee
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat May 31 16:36:29 2014 +0300

    i945: Fix TSEG size allocation for get_top_of_ram()
    
    Seems boards with i945 had TSEG disabled so this had gone unnoticed.
    
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Change-Id: I6a00ea9121847ce2fede22538e1b53a870d761f1
    Reviewed-on: http://review.coreboot.org/5892
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 15935ebe242bcdd6c84f5f2e9fb8a573e69a1c60
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat May 31 16:07:14 2014 +0300

    i945: Fix resource bases for UMA and TSEG
    
    TSEG appears in memory below graphics UMA region. Seems boards
    with i945 had TSEG disabled, so the incorrect order did not make
    a difference.
    
    Change-Id: Ie293aab17b60b5f06a871a773cd42577c7dc7c7b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5891
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 9c65978f3849098ad54970bde55a46a133bc8d5a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jun 1 16:31:48 2014 +1000

    mainboard/ibase/mb899: Trivial, Non-local header treated as local
    
    Change-Id: I5cb496d0d582d3dc5c0c0635f632561f8a3dd853
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5897
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit a34a1da44d9b16c0515325cecd5b23d15ab9c2cf
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jun 1 16:09:21 2014 +1000

    northbridge/intel/i945/i945.h: Trivial, fixup header guards
    
    Change-Id: Iff15ab436e5b7b4e189c7341e7c508faaef07a3a
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5896
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit ee62164bb2052b065e72c5202c221b600401e0bc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Feb 8 19:00:54 2014 +0100

    lenovo/x201: Fix order of SPI init.
    
    The lock bit for UVSVC/LVSVC was set before both registers were programmed.
    
    Change-Id: I000440db5c8dd2f260ebc1b69108b75621faf7b3
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5167
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 25b55f3d1ceb4fdf67ffb29ed4080dfd5f4e5916
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Mar 4 17:43:57 2014 +0100

    lenovo/t60: Implement intel VGA callbacks.
    
    Without it option ROM run results in just a black screen.
    
    Change-Id: Id203f55ca0f02c290a3f40ac1ec7c5f23c5580bf
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5344
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 63acd22dc5366c72a7165138f5030df9523824dc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jun 1 00:26:48 2014 +0200

    lenovo: Make version look like something thinkpad_acpi would accept
    
    thinkpad_acpi checks that BIOS version matches some pattern.
    Report version in this form.
    
    Not cleaned up as the idea of this patch seems to be met with resistance.
    Can make it Thinkpad-specific if the idea is accepted.
    
    Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4650
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 4c81a9e142f54f4d8fa3caa08e741c2ac09c296e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Mar 2 17:45:09 2014 +0100

    i915_reg: Declare LVDS register values.
    
    Change-Id: If8b3578c4fa31bf9f09c0053a5cac7ebc993b634
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5319
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 8ecdc9e877aec90cbc5126a4c82298a7eca89d83
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Feb 15 18:59:40 2014 +0100

    acpigen: Add acpigen_emit_eisaid.
    
    Change-Id: Ib92142a133445018cd152dabe299792ba5f36548
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5240
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 4b10bb7c807bf60674ff2d4c5494164d7869971a
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri May 30 09:26:46 2014 +0200

    util/board_status/board_status.sh: Move `cbfs.txt` to results directory
    
    Commit 40e936a1 [1]
    
        util/board_status/board_status.sh: Save ROM contents in `cbfs.txt`
    
    creates `cbfs.txt` in `${tmpdir}` but does not move it to the results
    directory `${tmpdir}/${results}`. So move it to the correct place.
    
    [1] http://review.coreboot.org/5867
    
    Change-Id: Ibca691ccf72b56b6271a611d92deaed7d377773b
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5883
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 32da8d900e2ca5fa9fe95d30dd064d593b26002f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 29 14:43:39 2014 +1000

    superio/nsc/pc87309: Avoid .c includes in mainboard
    
    Make superio romstage component link-time symbols.
    
    Change-Id: Icde27465a05946498ff7b8f1aaa7a9e8ba074272
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5880
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit beb0f2631fe6e49e86687cc3a7cf63ce41157a45
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 29 13:09:50 2014 +1000

    superio/winbond/w83627hf: Avoid .c includes in mainboards
    
    Move towards the removal of the superio model specific xxx_serial_enable
    implementation. Make remaining superio romstage parts link-time symbols
    and fix corresponding mainboards to match.
    
    The following mainboards remain unconverted as they are ROMCC:
     - mainboard/supermicro/x6dai_g
     - mainboard/supermicro/x6dhe_g
     - mainboard/supermicro/x6dhr_ig
     - mainboard/supermicro/x6dhr_ig2
    and so block the final removal of w83627hf_serial_enable().
    
    Special cases:
     - mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func
    Provide local superio pnp_ programming entry/exit functions as to avoid
    making superio implementation global symbols. Although this is not the
    proper/final solution, it does mitigate possible symbol collisions and
    allow for continued superio refactorisation.
    
    Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5601
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 9068788a8f0c96a5153fcd4e5ed80eac80b060c6
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon May 26 04:03:24 2014 +1000

    superio/winbond/w83627ehg: Depreciate romstage component
    
    Part 1/2: These are actually not necessary if Super I/O support is
    properly utilized.
    
    Change-Id: I39b621e582f8d0762276d29492c91dce500f0665
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5870
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 3c3e34d69fe4b185d4c0b698dfc6fcbf11b50dbb
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat May 31 11:32:54 2014 +0300

    i945: Use defines for DEVEN
    
    Change-Id: I32461449354155510c0e14e9d0ce396068ea50d4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5890
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 66f10b1a193b0c8cedbd32c2a83fc9e3b129648c
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun May 25 13:50:14 2014 +0200

    northbridge/intel/i945/northbridge.c: Use define `TOLUD` instead of hardcoded value
    
    Change-Id: I4739c5544aade105399347d239ba64f5115db397
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5869
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 355ce38dc2891c491387707ffe2e4e802ce4e864
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri May 30 13:58:59 2014 +0200

    northbridge/intel/i945: Add define for register `BSM` and use it
    
    Add a define for the register Base of Stolen Memory (BSM) and use it.
    
    Change-Id: I5b1df4e088d88344fac8cd8d218e76b08a885f58
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5884
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ae6e0c6bebc45f4c0b21a68e636a0d87b78db9cb
Author: Martin Roth <gaumless@gmail.com>
Date:   Mon May 19 15:28:00 2014 -0600

    cpu/intel/fsp_model_206ax: change realpath to readlink
    
    realpath and readlink can be used to do the same thing - in this case
    we're turning path1/path2/../path3/path4 into path1/path3/path4 so
    that the makefile's wildcard routine can evaluate it.
    
    Debian derivatives don't seem to include realpath. (and even when it's
    installed, it's not the gnu coreutils version.)
    
    Change-Id: I0a80a1d9b563810bdf96aea9d5de79ce1cea457a
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/5793
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Tested-by: build bot (Jenkins)

commit d75800c7f2476bee243cc22255acb54d6676d4bc
Author: Martin Roth <gaumless@gmail.com>
Date:   Mon May 12 21:56:27 2014 -0600

    intel/bayleybay: Add Intel's Bayley Bay mainboard
    
    Bay Trail-I Platform – Bayley Bay-I Customer Reference Board
    
    The Bayley Bay CRB-I is a dual-channel DDR3L SO-DIMM non-ECC platform.
    It is designed to support the Bay Trail-I SoC.
    
    This implementation uses the Intel FSP (Vist the Intel FSP
    website for details on FSP architecture and support).
    This code does not currently support S3. All other features and IO
    ports are functional. Booted on Ubuntu 14.04, Mint 16,
    Fedora 20 with SeaBIOS payload. Memtest86, FWTS, and
    other tests pass.
    
    Notes:
    - Generates a 2MB binary to be flashed to the upper 2MB of the ROM,
    to preserve the existing Intel Flash Descriptor & TXE binary.
    - Tested with B0 & B3 Baytrail I parts
    
    Board support page will be updated on acceptance.
    
    Change-Id: I80c836c7590f2dc25ec854e7a0bb939024cea600
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5792
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0f5cf5e45b78d2e6a91d978bb86de5a4ff07c4d5
Author: Mike Loptien <loptienm@gmail.com>
Date:   Mon May 12 21:46:31 2014 -0600

    PCI IRQs: Swizzle PCI IRQs for PCI bridges
    
    The PCI Specification states that devices that implement
    a bridge and a secondary bus must swizzle (rotate) the
    interrupt pins according to the table below:
    	Child Dev #     Child PIN       Parent PIN
    	0,4,8,12...     A/B/C/D         A/B/C/D
    	1,5,9,13...     A/B/C/D         B/C/D/A
    	2,6,10,14..     A/B/C/D         C/D/A/B
    	3,7,11,15..     A/B/C/D         D/A/B/C
    
    Which is also described by this equation:
    	PIN_parent = (Pin_child + Dev_child) % 4
    
    When a device is found and its bus number is greater than 0,
    it is on a bridge and needs to be swizzled.  Following the
    string of parents up to the root bus and swizzling as we go
    gives us the desired swizzling result.  When BIOS_SPEW is
    defined, it will print out each step of the swizzling process.
    
    Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/5734
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>

commit 433659ad1e864808ec30e90a62ecfd711559c5a9
Author: Martin Roth <gaumless@gmail.com>
Date:   Mon May 12 21:55:00 2014 -0600

    fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip
    
    While similar to the Bay Trail-M/D code based on the MRC, there are
    many differences as well:
    - Obviously, uses the FSP instead of the MRC binaries.
    - FSP does additional hardware setup, so coreboot doesn't need to.
    - Different microcode & microcode loading method
    - Uses the cache_as_ram.inc from the FSP Driver
    - Various other changes in support of the FSP
    Additional changes that don't have to to with the FSP vs MRC:
    - Updated IRQ Routing
    - Different FADT implementation.
    This was validated with FSP:
    BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
    SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
    MD5: 9360cd915f0d3e4116bbc782233d7b91
    
    Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5791
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2a9b2ed3ff5411d0efdbde3b9ba1d1de06ab09aa
Author: Martin Roth <gaumless@gmail.com>
Date:   Mon May 19 15:30:00 2014 -0600

    drivers/intel/fsp: update enable_mrc_cache with fast boot
    
    When going from a configuration with fast boot disabled to one with
    it enabled, ENABLE_MRC_CACHE was not being enabled properly.  This
    forces it on with ENABLE_FSP_FAST_BOOT.
    
    Change-Id: If7b6374e0c0a1d5403a50a1b0a958cea6f96cc88
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/5794
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7312c54dc684099a6d85ae13f3de097754ced0f0
Author: Martin Roth <gaumless@gmail.com>
Date:   Mon May 12 21:52:54 2014 -0600

    add rtc_init() to romstage
    
    The FSP clears the bit that tells us whether or not the RTC has lost
    power when it sets up memory.  Because of this, we need to initialize
    the RTC in romstage instead of ramstage.
    
    Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5735
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 2c55b70d1a9a52060708ee0cf44eac9c2764ddd4
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue May 13 23:29:22 2014 +1000

    superio/winbond/w83627thg: Depreciate romstage component
    
    Depreciate the model specific early_serial.c romstage component for this
    Super I/O in favor of the recent generic winbond romstage framework.
    
    Change-Id: I22775dc9b6341c8994d21591b7176abe4dd99911
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5724
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 92da206532598bd0cec91b2cddc7a1296400d728
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue May 13 23:52:30 2014 +1000

    superio/winbond/w83627uhg: Depreciate romstage component
    
    Depreciate the model specific early_serial.c romstage component for this
    Super I/O in favor of the recent generic winbond romstage framework.
    
    Convert dependent board to generic winbond serial init. Note the clock
    function is actually invalid since it never enters into PNP config mode
    to twiddle the register. Further, 48MHz is the default (page 9 of
    data-sheet) and so romstage.c need not do anything to the clock rate
    hence why it presumably works with this invalid function.
    
    Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5725
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit b918623f2e754d33226850958abd1a1fdc8c4889
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 09:18:26 2014 +1000

    superio/ite/it8712f: Depreciate model specific early_serial.c
    
    We now have common ite_*_*() functions for romstage and hence no longer
    require the model specific portion of this superio support.
    
    Change-Id: I30400abf27008a88072673075bba445f100d9ad3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5838
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 9bea0c1d146002f191bcfe1856abd39ab78ad9b3
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 09:11:31 2014 +1000

    superio/ite/it8712f: Drop model specific sio func for generic ver
    
    Drop it8712f_kill_watchdog() in favor of common ite_kill_watchdog()
    introduced in commit rev:
    
    a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers
    
    Change-Id: I9fc4d3ee7992618b5b14e35166e848d6e1cffa8b
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5837
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 40e936a1990a3dfd6fd2b8e2eab34643ecb7f470
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun May 25 12:20:51 2014 +0200

    util/board_status/board_status.sh: Save ROM contents in `cbfs.txt`
    
    The ROM content (CBFS content) captured with
    
    	cbfstool build/coreboot.rom print
    
    is useful for two reasons.
    
    1. With the used configuration for the build in `.config`, it can be
    compared how the size for romstage and ramstage change over time. To
    make that reproducible the used toolchain should also be stored
    somewhere in the future.
    
    2. With the CBFS content the time stamps can be better interpreted.
    For example, the size of the payload file is needed to interpret the
    time stamp for loading the payload.
    
    Change-Id: If77ca6412b1710e560f405f9a48df613c1819d36
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5867
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 18600aa1efb24ed9c60754a5d35f1794e7bafe6f
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Feb 2 11:23:26 2014 +0100

    payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4
    
    SeaBIOS 1.7.4 was released in December 2013 [1] and, besides other
    things, supports writing debug messages to CBMEM console.
    
    The new SeaBIOS Kconfig option `DEBUG_COREBOOT` has to be added to the
    SeaBIOS configuration file `.config` as otherwise the SeaBIOS build
    from within coreboot (`PAYLOAD_SEABIOS`) is interrupted as it is
    detected as a new option.
    
    This option was already added and enabled in commit 7c1a49bc [1]
    
    	SeaBIOS: have coreboot pass the choice to run optionroms in parallel
    
    so SeaBIOS messages are now written to the CBMEM console.
    
    Successfully tested on the Asus M2V-MX SE.
    
    [1] http://seabios.org/Releases
    [2] http://review.coreboot.org/5443
    
    Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5093
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 76d8fd6095edadbe12e2091eebfcb71dbcef798b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed May 14 19:15:08 2014 +1000

    mainboard/*: Convert to generic ITE superio romstage component
    
    Convert mainboard's that use model specific romstage functions of
    it8712f to the generic framework by following the reasoning of:
    
    a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers
    
    Change-Id: I1485306a951103c9a4bc0dbe87c416c91f46c36f
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5737
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 470c37c372b6b6a6961a3b287f609f55c15f6d4c
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Mar 16 00:15:57 2014 +0100

    util/cbfstool: Use `%zu` instead of `%ld` for size_t arguments
    
    cbfstool fails to built under 32-bit platforms since commit
    
        aa2f739a cbfs: fix issues with word size and endianness.
    
    due to the use of '%ld' format specifier on size_t, which on these
    platforms is only 32-bit.
    
    No error is seen though, when cbfstool is built, when building a coreboot
    image, where it is put in `build/cbfstool`.
    
    Use the length modifier `z` for size_t arguments, and cast to size_t where
    appropriate.
    
    Change-Id: Id84a20fbf237376a31f7e4816bd139463800c977
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5388
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit f2f7f03aff2df2471fce08f48bb0a6583263158e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Apr 4 15:05:28 2014 +0300

    console: Add console for GDB
    
    Connection of UARTs to GDB stub got lost in the console transition
    process, bring it back. In theory, GDB stub should work also over
    usbdebug, but that solution is not really tested at all yet.
    
    Change-Id: I90e05e8132889e788b92e055ee191f35add43bbc
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5343
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c009601f29847aa91ec2f5a89a02f46a2119c5a4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon May 5 18:56:33 2014 +0300

    AGESA fam12 fam14 fam15: Declare local callouts static
    
    Change-Id: I2ff70cafdd808a235ed4f0663e182d306f493c7e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5685
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f646f6d5822e648d9ba647a97981407c5c953b92
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue May 6 14:10:04 2014 +0300

    amd/dinar: Handle empty HOOKBEFORE_DRAM_INIT
    
    Removed function only read ACPI MMIO base address from a couple of
    registers in IO space.
    
    Change-Id: I25a31b7ac1706b9eebc5db0b9604039928328b0a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5683
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6b4b1513a5026b6c9f2883bf6687341405579689
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon May 5 12:05:53 2014 +0300

    AGESA fam12 fam14 fam15: Common handler for AGESA_RUNFUNC_ONAP
    
    Change-Id: I9f27e1e814a80864d8ca315fe816a083c55708c6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5682
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 838e211013d76cb8de86d8210bb52f396b9e369c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon May 5 12:21:04 2014 +0300

    AGESA fam12 fam15: Unify agesawrapper_amdlaterunaptask
    
    Pass parameter Func like fam14, fam15tn and fam16kb.
    
    Change-Id: I262bf88e431f7035e668ac8f3fb29ac0690b3e52
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5681
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5e19fa4c510a09abd9338fcc615be0c6cfbe3d6e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 23:13:54 2014 +0300

    AGESA fam12 fam14 fam15: Common handler for AGESA_DO_RESET
    
    This is x86 "standard" 0xcf9 reset mechanism.
    
    Change-Id: Ieb48290b21a7cb1425881fdd65c794e96da0248f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5680
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f1bb19abee7a81d5463c5885b57fe2cbc5d21715
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 17:23:49 2014 +0300

    AGESA fam14: Comment lack of PCI-e slot resets
    
    These boards return with AGESA_UNSUPPORTED, while other boards return
    AGESA_SUCCESS here when there is no hardware for external reset signalling.
    
    Change-Id: I5aed211b1812888af55a691cfbfa8d7b5aff91bc
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5679
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c459f9658b73ccb6a4300a00eafef90412fc4984
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 17:07:45 2014 +0300

    AGESA: Add common callouts
    
    Most of the callouts are not specific to board or even family.
    Start new file with default callouts doing nothing and returning
    either AGESA_SUCCESS or AGESA_UNSUPPORTED.
    
    Also add callout for returning empty IdsIdData. This feature is
    not used and could be easily overriden at board-level at later time.
    
    Change-Id: I65dbcdd80dddc89d47669ebe62c22caa63792f5c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5678
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cc84a001b8b71d457f30e5520c1583bbd297d691
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 14 21:05:35 2014 +0200

    build system: re-enable clang use
    
    Change-Id: I6e07fdec449d0b259d77986f65a60aa36d367cc8
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5747
    Tested-by: build bot (Jenkins)

commit 20ea04034dd1d2a1660e6d5fc9f5e8bc6c7859f4
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Feb 15 18:57:17 2014 +0100

    acpigen: Add acpigen_write_irq.
    
    Change-Id: Iba52dc2d52b7ac9a65d1d17b43e7204f5ede373e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5241
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit a31a838cdb22c827b8afe5b1620eedffa4ad4f0e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Feb 15 19:56:51 2014 +0100

    lenovo: Add lenovo_mainboard_partnumber.
    
    Change-Id: Ie10dcb742fe0884dd94ff5960e2e4b116f633243
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5246
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit dfdf001392c172738593149be21ad614839c30a3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Apr 28 23:25:01 2014 +0300

    ChromeOS: Rename chromeos.c in vendorcode
    
    Rename the file to vboot_handoff.c and compile it conditionally
    with VBOOT_VERIFY_FIRMWARE.
    
    Change-Id: I8b6fd91063b54cb8f5927c6483a398b75e1d262a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5645
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 604559c193af7decd7a4593ec1b4aa71d86b9531
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun May 25 06:34:06 2014 +1000

    northbridge/intel/i82810/raminit.c: Unused func spd_read_byte()
    
    Spotted by Clang
    
    Change-Id: Ib119f46fbbbd09a660bd6c4647b96a55d2c532a7
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5846
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 08280cb99ba415f453b9bc84cc65bfc874fa1f93
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun May 25 06:33:29 2014 +1000

    northbridge/intel/e7505/raminit.c: Silence warn of unused func
    
    Spotted by Clang.
    
    Change-Id: Iec34a23d0cf193ca6a4af0407b0763bf77ea03b3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5845
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 636cd6134639bff67dc7eb25e3279d588dd7742a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun May 25 06:30:35 2014 +1000

    northbridge/intel/i3100/raminit.c: Uninitialized variable
    
    Spotted by Clang
    
    Change-Id: If524a5cd984602a332c4ca28a8167a3597206b94
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5844
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 2f237c1859f29eaac6b10013a635a2d02a97780e
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun May 25 06:24:39 2014 +1000

    nb/intel/i945/raminit.c: duplicate 'const' declaration specifier
    
    Spotted by Clang
    
    Change-Id: I7e91f3edfa773560131e267a7776d8bf1ff7e295
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5843
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit a916b39e742b6d65e95a8e075de1aa3e9334e2ac
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun May 25 06:34:45 2014 +1000

    southbridge/amd/agesa/hudson: Unused func smbus_delay()
    
    Spotted by Clang
    
    Change-Id: Ic5b04f6f334bc9b1b014a7ada44e9656f7992063
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5847
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 33d664d9a1c5028ebf1ab30df6bf04e3c8c45cd6
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 04:03:39 2014 +1000

    southbridge/amd/cimx/sb900: Unused func smbus_delay()
    
    Spotted by Clang
    
    Change-Id: I14c099625db6f38fd0630b8864cf2a702b81d353
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5832
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 71714838a675e24e9e15da13bf70bfa3eae5a159
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri May 23 23:40:14 2014 +0300

    Drop PCI_BDF macro declaration
    
    Not used and did not have 12 bits reserved to address full PCIe
    configuration space per every function.
    
    Change-Id: Ib04a1eb2487735375b4ee738d48a5bebe41ba3c0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5835
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 8102a9afb87fd96470762f47a42ef9f344777bdb
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun May 25 09:50:26 2014 +1000

    mainboard/google/slippy: Fix usage of GNU field designator ext
    
    Following the reasoning in,
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: I219ae74d60fd7211de2edee96e74bbe13130bb94
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5849
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 6224c318606a27089cfcd832f4748bece818c377
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun May 25 09:49:37 2014 +1000

    mainboard/google/bolt: Fix usage of GNU field designator ext
    
    Following the reasoning in,
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: I31841e7bf578c77d08d452779936fcf5b3026d4f
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5848
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 511b383805a654d7a27c03d896d23d82ae902dd5
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 09:56:57 2014 +1000

    superio/ite/it8721f: Trivial drop redundant headers
    
    Change-Id: Ib086cd567c926dd659f67900195f93262ceb50c3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5839
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 8f9132fab10603abf75b8862418000669dfe9a27
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 04:01:38 2014 +1000

    mainboard/amd: Incorrect usage of logical vs. bitwise and
    
    Spotted by Clang
    
    Change-Id: I26201c7f5e421c38d3965d8e7e62c4a8e670e449
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5833
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 6cec824a28b7325337d251d87a5e47c92943cbed
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 04:16:57 2014 +1000

    mainboard/google/link: Fix usage of GNU field designator ext
    
    Following the reasoning in,
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: Id967f6057759cf0603c84514d32b067c3658306f
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5831
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 0f2355a0902285cb55e0802b7be66a9f08716700
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 04:15:16 2014 +1000

    mainboard/google/falco: Fix usage of GNU field designator ext
    
    Following the reasoning in,
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: I4e5f2d7e8e6b76703fccce38fc7e3165d763e97f
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5830
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 9492b9dab49336904167c19b161e6688dfe086e4
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed May 14 01:00:43 2014 +1000

    superio/winbond/w83697hf: Depreciate romstage component
    
    Depreciate the model specific early_serial.c romstage component for this
    Super I/O in favor of the recent generic winbond romstage framework.
    
    Change-Id: I529c9cd1d8d63db3035b4828b3c3fc43911f49ce
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5727
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 17046377191d14f46fd0af40be04899601a79768
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 22 00:16:39 2014 +1000

    mainboard/asus/k8v-x: Remove dubious SIO PNP programming in romstage
    
    Remove bogus attempt to double program the Super I/O. Remove also a
    questionable function that enters Super I/O LDN config space, does no
    actual LDN programming, rather multi-function register programming and
    then never leaves the config space. Further, we don't export pnp_
    symbols from the early_serial.c component into the global namespace.
    
    Change-Id: I7d6b97b174249ae16fe881728da5ca3dd069b696
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5800
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 80b627eb4d37fb503056d37b0910ad6afe9e63b5
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue May 13 16:36:56 2014 +0200

    Asus F2A85-M: Move to ther proper SIO
    
    The F2A85-M has IT8603E which is a strip down version of IT8728F.
    Change configuration from provisional IT8712F to the IT8728F.
    While at it also enable only needed LPC bridge decodes.
    As the side effect, this change also implements setup of environmental
    controller, thus it87 driver can detect the temperatures/fans.
    
    Change-Id: I22067b13ea27ee37e959a246718d9559c2a3215d
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/4499
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 290bed72589a36161c29debc67b7164dade5de3d
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue May 13 16:07:00 2014 +0200

    Implement proper IT8728F PNP ops
    
    The Asus F2A85-M has IT8306E which is a stripped down version
    of this SIO. Implement the PNP operations of the SIO.
    
    Change-Id: Ibc4f3fafc3ffb1cd799948e63be01e6924b45d6c
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/4498
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a7d14a170e9e36d4b8a0c73c112e5516f378c23a
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue May 13 15:57:47 2014 +0200

    ite/common: Introduce common watchdog and 3.3V VSB helpers
    
    Introduce the watchog and 3.3 VSB helper functions.
    The IT8712F can be migrated to use those too. To be used
    with IT8728F.
    
    Change-Id: If21e99b6069c7222f0bc8eb7c7121fe119b8dfe1
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/5728
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4405b06521c186a8b026cb3bc95837a3b605dd30
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue May 13 16:46:21 2014 +0200

    superio/ite/it8728f/it8728f_hwm.c: Small fixes
    
    Use proper include header in it8728f_hwm.c, fix format error.
    The base of HWM block starts at offset +5.
    
    Change-Id: I6855225b38bbcf5687d506bea9482c951d314684
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/5729
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit b27d3602e0faad60001debaa4572c23440114502
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 02:40:31 2014 +1000

    mainboard/samsung/stumpy: Fix usage of GNU field designator ext
    
    Following the reasoning in,
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: I6c5cc46385581d6b69d20f6bc9b016b799765d9e
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5829
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ea4ae2f02bde5f885ff8a2942478905416b15066
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 02:08:04 2014 +1000

    mainboard/intel/emeraldlake2 Fix usage of GNU field designator ext
    
    Following the reasoning in,
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: Idda1a49277c156670014fac27b9f1c378f8df0cd
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5827
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c686c95c9831d66e76cde6fe6f9d8c45abdb5970
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 02:07:18 2014 +1000

    mainboard/intel/baskingridge Fix usage of GNU field designator ext
    
    Following the reasoning in,
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: I61fe91e467c29f144323af9c4612420f322098b4
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5826
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6aa6509caee29342014721e5e6689e437e396aea
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 02:06:10 2014 +1000

    mainboard/intel/wtm2: Fix usage of GNU field designator extension
    
    Following the reasoning in,
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: I46fad8d236c620ee5dbeb24f4517f20f00db839f
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5825
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6f49f69ed0c46efd57c221c3e5ab163becb19897
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 24 02:04:52 2014 +1000

    mainboard/kontron/ktqm77: Fix usage of GNU field designator ext
    
    Following the reasoning in,
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: If948960abbd927aa6d2b471a42a2321a04d992f3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5824
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a0427cb84415d143db595b7b359a5edb55ebdb64
Author: Martin Roth <gaumless@gmail.com>
Date:   Wed May 21 15:03:08 2014 -0600

    vendorcode/intel/fsp/rangeley: remove extra file
    
    This is an extra file that is included in the Intel GSP release.
    It's got a coreboot header on it, isn't used, and looks very
    platform specific.
    I'm not sure where it belongs, but it doesn't belong in vendorcode.
    
    I've sent the contacts at Intel an email letting them know that this
    file should probably be removed from their FSP release and is getting
    removed here.
    
    Change-Id: I5ac6649235846ce5716bb180af29a5e422f4cce3
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5809
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit e9e99e976e18c21dcaccaeccbf5dc276d771446c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri May 2 15:19:21 2014 +0200

    drivers/pc80/Kconfig: Revert PS/2 initialization defaults
    
    Remove the inconsistent behaviour based on unrelated
    configuration: PS/2 init is now always enabled.
    This can change once we find a better approach.
    
    Change-Id: Ia8d55032f0e5eca0bf82d77df7dab95bcb2b353a
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5634
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 8084e5b6da38865bde976ae02563f83dad37c133
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 23 08:42:18 2014 +1000

    mainboard/google/peppy Fix usage of GNU field designator extension
    
    Following the reasoning in,
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: Idd7305cb34be77894ca4b6062bc0a2dc61126347
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5822
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f5037bd570a7cbd2b09fb6d34d3feb77553144f4
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 23 08:36:01 2014 +1000

    mainboard/google/parrot Fix usage of GNU field designator extension
    
    Following the reasoning in:
    
    8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: I5be77fe6670601e103260077fae07a5b9fd41f1d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5821
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 26c74fbd4f23223cb461dba9e35f5921fbc08534
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed May 14 04:13:16 2014 +1000

    payloads/coreinfo/multiboot_module.c: Trivial fix indents
    
    Stylistic fix-up's.
    
    Change-Id: I0cad7c860280d0d8dcb16d052846c72f690e2b65
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5731
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit aab0cce88891197510740ac5a663e003b7f99981
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Dec 19 20:43:29 2013 +0100

    abuild: make build directory configurable with a variable
    
    Allow overriding the build directly (default: coreboot-builds)
    using the COREBOOT_BUILD_DIR variable, in addition to setting
    it through the -o parameter.
    This helps with build nodes where jenkins wants to run the
    same command everywhere but allows different environment
    variables.
    
    Change-Id: If907897cf6ac01caa7d1e4b51aad4c005356bc5b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4543
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2d242797105c6905c69a64cac3f9cfa591bcb8a3
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 21 22:48:35 2014 +0200

    abuild: update version and copyright
    
    Enough changed to warrant a new version, date,
    and copyright.
    
    Change-Id: Ia099cd4fec3b05efc3f8bac09d38baede1c719e0
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5806
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ad27322702a0e31817d1a58aa4b8ceff004a4e56
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 21 23:00:32 2014 +0200

    abuild: allow build results outside the source tree
    
    A reasonable configuration that minimizes disk traffic
    could be
    
        $ abuild -o /tmp/abuild-$$ -z
    
    Change-Id: Ic91798af7e799a40a77025e09a6078ea6758cdac
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5805
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b0bc63b519d05cdf4b3aedaa683de09f410e9785
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 21 22:47:05 2014 +0200

    abuild: allow deleting the work directories immediately
    
    This is useful on pure build nodes that don't care for
    object files, just for a build log and success flag.
    
    Change-Id: Ida65d4e41652af0f1b7255309aec2eeb6ef5c9ef
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5804
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1f946706f119a7ec974170926165793f6f9ddd12
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 21 22:36:13 2014 +0200

    build: allow obj=/absolute/path
    
    This allows moving the build tree outside the source tree.
    
    Change-Id: I97882c4820d2c962c27bf8d50378e64016ce5790
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5803
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 68a56caf7e9bb0203de1d4d96861ba60885a401d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 23 07:11:14 2014 +1000

    northbridge/amd/amdmct: Incorrect usage of logical over bitwise and
    
    Small mix up of logical/bitwise logical and operation. Spotted by Clang.
    
    Change-Id: I2c2256b9b2f2b6ca627914118c745f579555acc9
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5820
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit ba363d3f185c30c51069cff711d8be8dccb3545f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 23 05:58:27 2014 +1000

    northbridge/amd/amdmct: Superfluous parenthesis in if-statements
    
    Remove superfluous parenthesis found in some if-statements, spotted by
    Clang.
    
    Change-Id: I98d2bf6b408caf320c5bcc8adb23d621b182976b
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5817
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit de6c3c846a448e1bdb6b9335510e0aa819371402
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 23 06:18:10 2014 +1000

    southbridge/amd/cimx/sb700: Unused func smbus_delay()
    
    Spotted by Clang.
    
    Change-Id: Ie4bed914ab694f4e96155140b8b54b6eb96d70d7
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5819
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 3a5ea48c0c7c2385b51b781f86147742844900ac
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 23 06:15:53 2014 +1000

    vendorcode/amd/agesa/f*: Fix typo in header guards
    
    _CPU_L3_FEATIRES_H -> _CPU_L3_FEATURES_H
    
    Spotted by Clang
    
    Change-Id: I1eabebffc7fd5e4f37b28dabcd28984bed64acd8
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5818
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 72ae4a3091046db366e7831b7361ea16a77672a0
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 23 05:55:04 2014 +1000

    northbridge/amd/amdmct/mct: Initialize variables at the eol
    
    Spotted by Clang
    
    Change-Id: Idada98b7863ef986021943cf3ddb92d2f035e3e1
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5816
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit f67395ee5b28f4d0a0694050089805d1b3395b63
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 23 05:51:21 2014 +1000

    southbridge/amd/sb700/smbus.c: Unused func smbus_delay()
    
    Spotted by Clang
    
    Change-Id: I0f04c380b5ada28fb900710facc293edd65ac177
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5815
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 351aff85ee0c694e791ac7647ed9f49d7d9e6e99
Author: Martin Roth <gaumless@gmail.com>
Date:   Wed May 21 15:07:26 2014 -0600

    device/pci_ids.h: defines for new Intel LPC devices
    
    Add defines for the Cave Creek and Rangeley LPC devices.  These
    chipsets will be added shortly.  This file is outside of any of
    the directories that will be touched by those additions, so it's
    getting changed in its own commit.
    
    Change-Id: Ia829282b2ad67eef09689858500bc7f93a1cd05b
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5810
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit efac717f3cf6daad582875657a1ef7db72ab59c8
Author: Martin Roth <gaumless@gmail.com>
Date:   Wed May 21 14:49:13 2014 -0600

    x86/include/arch/acpi.h: remove incorrect semicolon
    
    The semicolon really shouldn't be in the include...
    
    Change-Id: I90a0f516857365fddd21311cd703132af8d51007
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5808
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 16d953a46001e8852d63095e5310ed7869d109e7
Author: Martin Roth <gaumless@gmail.com>
Date:   Mon May 12 17:38:59 2014 -0600

    device_romstage: Add a way to move to the next device
    
    When trying to loop through all the devices in romstage, there was
    no function to just go from one to the next.
    
    This allows an easy way to go all the way down the chain of devices.
    
    Change-Id: Id205b24610d75de060b0d48fa283a2ab92d1df0a
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/5732
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit db0e0e2c54397dffa8b55bfbfb76a15d641e4235
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 15 21:13:33 2014 +1000

    amd/agesa/*/gcc-intrin.h: Invaild inline asm
    
    The 'm' (a memory reference) constraint makes little sense here since we
    are talking about a fs relative read, rather 'ir' (immediate or
    register) constraint is more sensible.
    
    N.B. The 'p' constraint allows anything which fits the form of an address
    calculation where the 'ir' constraint is just a register /xor/
    immediate. Hence would produce better code here however, unfortunately,
    clang does not currently support it properly.
    
    The %b and %w constraints are also redundant and only hide errors.
    
    The functions writefsword() and writefsdword() should use ir instead of
    iq. iq is unnecessarily restrictive (it is only required for writing
    bytes).
    
    The cld in stosb is redundant (and the constraints are unnecessarily
    complicated). Note that The ABI guarantees that the direction flag is
    cleared. i.e. eax, ecx, edx are caller-saved, returned value in eax,
    eax+edx, st0, yaddayadda, direction flag cleared. In fact bad things can
    happen if you set it in some asm and do not clear it until the end of
    the asm.
    
    Line wrap these extraneously long lines found with these particular functions.
    
    Many thanks to Christoph Mallon <christoph.mallon@gmx.de> from #llvm for
    helping me with this.
    
    Change-Id: Iaf3ad65791640e1060a2029e7ebb043f57b338a9
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5758
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 3312ed7e7a0b3269d6559207cdf9ed932ffecd31
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 22 03:36:22 2014 +1000

    amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop construct
    
    The semantics of this loop relies on an integer overflow in Index >=0
    that implies a return value of (UINT8)-1 which around wraps to 0xFF, or
    VOLT_UNSUPPORTED.
    
    Change-Id: I44d68973d0a80093350b2a8a4d3b46bfbb57917a
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5801
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 2c9e3706469e65629d6e74b5a43df9277f176933
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed May 21 06:51:15 2014 +1000

    mainboard/ibase/mb899: Sanitize headers
    
    These are not local headers.
    
    Change-Id: Ie0b0a682565a08dbfa089986dc7860fdb0846949
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5796
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 0deb355d0e7f042cbcf6d74937b39729c7eaac0f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 15 21:07:16 2014 +1000

    vendorcode/amd/agesa: unsigned enum is strictly positive
    
    The typedef'ed BIT_FIELD_NAME enum is type unsigned. The parameter
    'FieldName' is decleared with type BIT_FIELD_NAME and thus the redudant
    comparison of unsigned enum expression >= 0 is always true.
    
    BIT_FIELD_NAME is declared in vendorcode/amd/agesa/f14/Proc/Mem/mm.h
    
    Change-Id: Id2f03596c44b68e861e939f3528256d4b08c45ce
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5757
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 8a661ed788ff1373015a5c6b705e2e32b63ebe4a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed May 21 09:42:56 2014 +1000

    amd/cimx/sb?00/SATA.c: Integer overflow in loop condition
    
    The conditional comparison in the for-loop construct with the constant
    300000 has an index incrementor of type 'UINT16' (aka 'unsigned short')
    which is always true.
    
    Change-Id: I932c168742163be4038728fb40833231a447fa78
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5799
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 03b00e9675d08d01ff831f20e8e48d19e93494af
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue May 20 15:52:08 2014 -0700

    baytrail: Fix some minor errors in FSP
    
    - Duplicate declaration of GetFspReservedMemoryFromGuid
    - Corrupt line that was only compiled for a southbridge that no
      board in coreboot currently uses.
    
    (thanks for Mike Hibbett <mhibbett@ircona.com> for pointing this out)
    
    Change-Id: I847e807272acbaa93c87a89c0d2f94829c9121e6
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/5798
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 61113de9234f1b933a084c90097ec125fc12f55d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun May 18 10:33:31 2014 +1000

    mainboard/ibase/mb899: Indent devicetree.cb
    
    Change-Id: I29037c322dac5ed9ebc36b95bc1981acf21e5bd0
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5778
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit fb8df3240f5ac80a39b36ca8b5bad291156437a3
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun May 18 09:42:46 2014 +1000

    drivers: Drop GbE stub drivers
    
    These NIC stub drivers were to initialize the Gigabit Ethernet adapters
    just enough to keep coreboot from trying to execute an option ROM.
    However this is no longer required as non-VGA option roms are not ran;
    See:
    
    b32816e Remove PCI_ROM_RUN option
    
    Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5777
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 8dd407a878e8e4f86591ecde0af44400eb3fa098
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 15 19:37:24 2014 +1000

    vendorcode/amd/agesa: Logic typo in GfxPowerPlayLocateTdp
    
    The function GfxPowerPlayLocateTdp() sets MinDeltaSclk to a maximum
    sentinel value and checks DeltaSclk in a loop to minimize MinDeltaSclk.
    However, MinDeltaSclk incorrectly self-assigns.
    
    Change-Id: Id01c792057681516bba411adec268769a3549aa8
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5752
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit b2d68976c830c3b4eddf78ea788f02cfa6d25ffc
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 15 21:23:51 2014 +1000

    amd/agesa: Implicit assigment between enum without cast
    
    Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5760
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit e1845b38c7cd4c6e18b07d82d2ba6aebd9b8170f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue May 20 04:36:41 2014 +1000

    amd/agesa/f*: Strip tailing white-spaces from gcc-intrin.h
    
    Change-Id: I1d801b9d8387e267feeb95563e55910b30ebbc34
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5790
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 5cf88249236220ba4e1dc991e99b6bd823cf8de8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 18 11:02:56 2013 +0300

    via/vx900: Remove GFXUMA and use of related global variables
    
    Remove global variables uma_memory_base and uma_memory_size
    from builds with via/vx900 northbridge, as these variables can be kept
    within the chipset.
    
    Change-Id: I9f8aea4836d81e704eae6a0f2cefc7fd4586b8b8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5721
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f7bfc34942f5dda173c30f82323e13afb2045a21
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 18 11:02:46 2013 +0300

    intel: Remove GFXUMA and related global variables
    
    Remove use of global variables uma_memory_base and uma_memory_size
    from builds with Intel northbridges, as these variables can be kept
    within the chipset or even as stack locals.
    
    Intel platforms have no functional implemenation for option GFXUMA.
    If we did implement some choice between external and integrated graphics,
    it needs to be named in less obscure fashion.
    
    Change-Id: I12f18c4ee6bc89e65a561db6c2b514956f3e2d03
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5720
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5f098072295c1943e389bc6af7741eb2b8397b11
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 18 11:02:46 2013 +0300

    Add guard for UMA globals
    
    We no longer need these globally. Guard them so we get to declare
    static replacements at few locations until complete removal.
    
    Change-Id: Ie33e2a680fc9bbb7e28c8fbe17e5181e626736a5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5718
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5930774f57bad80eb4caf4469388665749d1064c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon May 19 09:23:57 2014 +0200

    build: use CFLAGS_* in more places where they're needed
    
    After moving out -m32 from CC_*, 64bit compilers need
    CFLAGS_* in more places to handle everything in 32bit
    as appropriate.
    
    Change-Id: I692a46836fc0ba29a3a9eb47b123e3712691b45d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5789
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 9f5af6a65a4d9de1e1b6ac9089a4feec29220148
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun May 18 23:30:56 2014 +0200

    vendorcode/amd: kill some intermediate variables in build system
    
    They don't exactly add clarity, but increase the risk
    they're used at some obscure place.
    
    Change-Id: Ic74f72dae3f9b7eb2343cb5c51bc44c888e1276c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5787
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit e3927436c64bcbdd17c5adaa24f86c584ecf1a68
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun May 18 23:04:27 2014 +0200

    build: move include paths where they belong
    
    They're _not_ part of the compiler binary, so they have
    no place in $(CC_*)
    
    Change-Id: I1e1c3c0be6f75629450a824ea834e1614d48ed9b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5785
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 2313c8bb65a90ab6341bcbe6230261f0fd0c5930
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun May 18 23:09:53 2014 +0200

    agesa: drop non-existing search paths
    
    With the upcoming CC/CFLAGS/CPPFLAGS split,
    romcc gets more CPPFLAGS, and it's picky about
    directories actually existing.
    
    Change-Id: Ib9c525296e5be0c8ace935ab8096bc98206cbcc1
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5784
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 6f7e4b21db604057311d24fd203bdba7cc7f8ee6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon May 19 09:18:11 2014 +0200

    fix printk types
    
    Some size_ts were considered long int and some compilers
    are picky about that.
    
    Change-Id: I671daa18eb3bfa2a7defc120e77bbb1ef72bd417
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5788
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit a6b6172ae30dc7a9f575c5b189a22e7b65464ff7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat May 10 16:57:40 2014 +0300

    Add aliases for Chromebooks in board_info
    
    This defines new board_info entry 'Vendor name' to be displayed in place of, or
    in addition to, the CONFIG_VENDOR string 'Google'.
    
    Also flag these as flashrom accessible SPI without socket. Instructions to
    disable flash write-protection can be found at Chromium developer documentation.
    
    Change-Id: I69791a091417a80d01e0ba2c6462417730a07be0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5750
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 49592da27fb365fc07621fe305fde2d6bf309bb0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu May 15 10:06:25 2014 +0300

    Board-status: Add second vendor line
    
    Change-Id: I8a962f323cbc6347f266a188a07f870ce174d339
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5751
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ee96c2ccbbc1d669ab9261cf871af377f118f62b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri May 9 10:28:15 2014 +0300

    LiPPERT: Add aliases for board_status wiki
    
    While at it, fix frontrunner-af board URL.
    
    Change-Id: I3b631830d679abc20f8a72411f2402689d9f9aac
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5706
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>

commit 246234fecb439cc7c9cee6616fe1b33c4d37a582
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 21:50:06 2014 +0200

    abuild: Only build boards with Kconfig
    
    We have dupes in the tree for aliases,
    board variants and the like,
    for board-status reporting purposes.
    But we don't need to build all of them.
    
    Change-Id: Ic1c6415568800350bdc0db97471e3875d9eac98c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5776
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit c86762657dc7013a56b1d281286789dae17ad936
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun May 18 11:28:43 2014 +1000

    device/oprom/yabel/vbe.c: Avoid unused func warn
    
    Change-Id: Idd74893c1fc3d0818d00c1f727c9fdc27168af0c
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5782
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 9c8532b350d00dbd1aa184f162ef0448c941c822
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun May 18 10:40:26 2014 +1000

    drivers/spi/sst.c: Remove unused func to_sst_spi_flash()
    
    Trips up clang builds with a warn treated as error.
    
    Change-Id: I9c0e2930ba8a60c7ad6063e9826b1b8638185505
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5779
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 40788c6a4e5e9b5172c3c8c5752b9c3cd50af78c
Author: Damien Zammit <damien@zamaudio.com>
Date:   Fri May 16 18:52:47 2014 +1000

    lenovo/t60: Enable dock serial port when undocked and redocked
    
    When the system is started with dock, the serial port works.
    As soon as the laptop is undocked and redocked, the serial port
    no longer works.  See below superiotool dump snippet:
    
    Upon bootup: SIO @ 0x2e
    LDN 0x03 (COM1)
    idx 30 60 61 70 71 74 75 f0
    val 01 03 f8 04 03 04 04 02
    
    Redocked:    SIO @ 0x2e
    LDN 0x03 (COM1)
    idx 30 60 61 70 71 74 75 f0
    val 00 03 f8 04 03 04 04 02
    
    Since the function dock_connect is executed every time the
    dock is reconnected, starting without a dock and then attaching
    it to a dock is now also fixed.
    
    Change-Id: Ibd97589a8c743673a55e382a5db2ba62656c595e
    Signed-off-by: Damien Zammit <damien@zamaudio.com>
    Reviewed-on: http://review.coreboot.org/5761
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit e47477e52ced46986c352a0ae6cf798c9a7aa560
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 18:38:10 2014 +0200

    build: re-enable ccache support
    
    The ccache support was mostly disabled because it
    didn't hook onto most compilers anymore.
    
    Caveat: ccache and scan-build don't work together since
    scan-build doesn't like arguments in its compiler command
    line (eg. "ccache gcc").
    
    Change-Id: I7c1c6e22cb662f2b08e774ea484ac1c412fdd2db
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5775
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit fadbe5f657147f5232b2e0ad2a2a8b654cbeb219
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 18:26:38 2014 +0200

    build: make scan-build work again
    
    This drops the scan-build related Kconfig options
    since it's now possible to simply run
    
        scan-build [-o outdir] make
    
    and get coreboot built with its report.
    
    There's also no inner make process anymore, and the way
    things work should be clearer now.
    
    Also adapt abuild to this new reality.
    
    Change-Id: I03e03334761ec83f718b3235ebf811834cd2e3e3
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5774
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit e24a119cceeef8ad62672fad2b92fd2f026621ab
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 19:05:56 2014 +0200

    build: allow romcc to be wrapped
    
    Allow ccache and scan-build to wrap romcc.
    This works a bit different from the other compilers
    because we only define it later.
    
    Change-Id: I3adce91d3dde9dd50aa6a2baad5b457744f35575
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5773
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 443fbcf6a322d34b5c69505823ef2c0e3a7ee06c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 18:24:45 2014 +0200

    abuild: replace hardcoded values by their variables
    
    Some coreboot-builds/ and makes made their way into
    abuild. Stop them.
    
    Change-Id: I5784e1fd623ada30e2fadcc74a7da3ee75c5ee96
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5772
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 262f31c3525f57f29310b5c7173b1a0f34efe792
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 15:13:40 2014 +0200

    build: remove call to missing function
    
    set_stage_libgcc never existed in our tree.
    
    Change-Id: I864fc683dd7b89a030daf05eafb9624ce828cb72
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5770
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit b145b8301fe973f588bcd637bb5eb070b1f472d3
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 15:08:47 2014 +0200

    build: break compiler flags out of $(CC)
    
    Having more than the executable in $(CC) only leads to
    trouble in a number of situations.
    
    Change-Id: I7642ca4068b3a3bd5798219d74de9e0eb85bb4e5
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5769
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 6bc44554b9df58465f6702828c4f663ab0e4d9ac
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 14:52:28 2014 +0200

    build: don't call $(CC) -print-libgcc-file-name twice
    
    Change-Id: Iaeeb8fc58e06c98273520e79999737da9ff3f872
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5768
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 4ebd3d9195731721e777186d6f78531bba29497e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 14:02:08 2014 +0200

    build: kill one indirection
    
    No need to first define X86_32 and then replace every
    single use of it with its lower cased equivalent.
    Just start out with the lower case versions in the first
    place.
    
    Change-Id: I1e771ef443db1b8d34018d19a64a9ee489cd8133
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5767
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit b83f7deb78fbc440a42db47eaa0605e116d9d28e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 14:20:11 2014 +0200

    build: get rid of a special case
    
    Don't call things in xcompile i386 and in the
    buildsystem x86_32 and then bridge things so
    they match. just call it the same everywhere.
    
    Change-Id: Ieef5f03f7aafb0b0a606fbe5a2386e310d2b0e94
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5766
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 58f73a69cd83c46604795d728f296779c1de162c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 14:00:12 2014 +0200

    build: separate CPPFLAGS from CFLAGS
    
    There are a couple of places where CPPFLAGS are
    pasted into CFLAGS, eliminate them.
    
    Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5765
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 98f49d28233f68aeb9dfccc6d7e633ae35449e00
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 13:53:11 2014 +0200

    build: CPPFLAGS is more common than INCLUDES
    
    Rename INCLUDES to CPPFLAGS since the latter is more
    commonly used for preprocessor options.
    
    Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5764
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit c2a0b7d990ff162504bbd1aef27c049ea885a38b
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 17 14:11:57 2014 +0200

    build: reduce duplication in payload adding rules
    
    They're all the same, so treat them that way.
    
    Change-Id: I8e3976df1e3a0f9dbcf1d5373611f6197bc9701b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5763
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 48e9eb89fa52eeb193f7e687bbb7f4e152235b79
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue May 13 12:57:26 2014 +0300

    libpayload: Fix to properly disable serial console
    
    With coreboot builds with serial console disabled, there is no
    CB_TAG_SERIAL entry in coreboot tables. We ended up with
    lib_sysinfo.serial == NULL and serial_hardware_is_present == 1.
    
    Change-Id: I9a2fc0b55bf77769f2f2bfbb2b5476bee8083f7d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5723
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 0890a825f3870f135447055c40b342bc6e3b0da7
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 14 14:48:31 2014 +0200

    xcompile: ABIs are really architecture specific
    
    no need to test for i386-eabi or armv7a-elf
    
    Change-Id: Icbef5a64f5b793092ca0f94ee8f54bc896bf39ad
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5746
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 1ec065bffae5233202ec1e64f3a2fb541da3784e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri May 2 15:08:46 2014 +0200

    drivers/pc80/Kconfig: simplify PS/2 selection rules
    
    There's no need to state the dependency twice.
    
    Change-Id: Ia241d441211c6f476d0a6ed7589b038f7a220265
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5633
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e0187df61bea98d506c8cddf5d7674d09cb50390
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 14 14:32:11 2014 +0200

    xcompile: break out big loop content into function
    
    Change-Id: Id98afa956a2af7113a6ef848b436d661a1fa39f2
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5745
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit adc241326c6b751911d4ef6763aa9bea0fa12934
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 14 14:30:08 2014 +0200

    xcompile: move tempfile cleanup closer together
    
    Change-Id: I4fb3041d505402de3cbcd7ec079dde5e168a90cf
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5744
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ee46712da0d02b2f11923e89bcddb7dc84c0939f
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 14 14:28:21 2014 +0200

    xcompile: actually use "special compile flags" idea
    
    xcompile used to test for special ARM flags - that were
    empty.
    Meanwhile, -Wa,--divide, which is only useful on i386-elf
    was tested for on arm and aarch64, too
    
    Change-Id: I1a5a1bc40fa1040d0939038b073aef31c72d0c6f
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5743
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 004295d86d7bbd6cfb0ce9767cbc1a2adbf61891
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 14 14:26:07 2014 +0200

    xcompile: fail earlier on missing host tools
    
    No need to test all the cross compiler things if
    there's no host compiler or iasl.
    Also test that the alternatives work, instead of
    assuming iasl or cc are in the path.
    
    Change-Id: I1d2293873f4bf1bb525d794851ec20adddb05ac6
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5742
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d387c63576098f63d18e11a45faf0fe5d1f57dee
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 14 14:23:28 2014 +0200

    xcompile: slightly refactor variable expansion magic
    
    Change-Id: Iebe071c863c6c7139128a2ec59acfb9da0f83512
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5741
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit aab174088199d7012b32e21753d75014d9c2aef5
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 14 14:14:38 2014 +0200

    xcompile: use bash
    
    I don't think all /bin/sh implement all features used
    in xcompile.
    
    Change-Id: Ida2a166242201ed0221316b123888127c83bf3c1
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5740
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e9fe6545cac2313cbee2b2bdd5c7518e41e9c833
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 14 13:43:58 2014 +0200

    abuild: add -L|--clang to enable clang builds
    
    Change-Id: I11053456fd90cda07143b76de49c2804e38f06e0
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5739
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9fd7c0f18ee8665f2e4dc311ae906412f2b0a0a1
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jan 16 09:47:39 2014 -0800

    baytrail: Add SOC thermal settings
    
    Apply the SOC thermal settings from DPTF reference code for
    SdpProfile=4 and adjust graphics PUNIT setting to match.
    
    BUG=chrome-os-partner:17279
    BRANCH=baytrail
    TEST=boot on rambi and check for valid GPU power values from DPTF
    
    Change-Id: I59fc4b75b52084ebcc4c0556563afca0585ea6b8
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182786
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5052
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit c6313db34f26bcb8bdbb5ff04ebc9c9e7193cf0f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jan 16 11:18:36 2014 -0800

    baytrail: Enable PCIe common clock and ASPM
    
    Enable the config options to have the device enumeration layer configure
    common clock and ASPM for endpoints.
    
    BUG=chrome-os-partner:23629
    BRANCH=baytrail
    TEST=build and boot on rambi, check PCIe for ASPM and common clock:
    
    lspci -vv -s 0:1c.0 | grep LnkCtl:
     LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
    
    lspci -vv -s 1:00.0 | grep LnkCtl:
     LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+
    
    Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182860
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5051
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3549462a95c5d7b9450924a1c0ca54b992c81211
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Jan 15 11:59:10 2014 -0600

    baytrail: enable graphics turbo
    
    Though the limited documentation indicates the default is
    0 for the gfx_turbo_disable bit, in practice that isn't
    true. Knock down the gfs_turbo_disable bit to enable
    graphics turbo mode.
    
    BUG=chrome-os-partner:25044
    BRANCH=baytrail
    TEST=Built and booted. Added debug code to output SB_BIOS_CONFIG.
         Noted that bit 7 was set to 0.
    
    Change-Id: I11210c6a0b29765cb709a54d6ebd94211538807b
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182640
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5050
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 469b5205c31eeb7f58e66aaec58ef824f2e090a5
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jan 13 16:37:51 2014 -0800

    rambi: Add ACPI devices and interrupts for codec and ALS
    
    The Codec and ALS both have interrupt sources that can be configured.
    The ALS kernel driver currently does not try to use it but the codec
    driver does for things like jack detect.
    
    ACPI Devices are added, but as with other ACPI devices the HID may
    need to be updated once more official strings are decided.
    
    BUG=chrome-os-partner:24380
    BRANCH=baytrail
    TEST=manual: build and boot on rambi and check for functional lightsensor
    
    Change-Id: Ib51a2aaf32d5597926fcbe9183947e9ac53e1468
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182366
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5049
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 59d1d87c86ff26142de23fd372fece3977a7330c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Jan 14 17:34:10 2014 -0600

    baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
    
    On baytrail, it appears that the turbo disable setting is
    actually building-block scoped. One can see this on quad
    core parts where if enable_turbo() is called only on the
    BSP then only cpus 0 and 1 have turbo enabled. Fix this
    by calling enable_turbo() on all non-bsp cpus.
    
    BUG=chrome-os-partner:25014
    BRANCH=baytrail
    TEST=Built and booted rambi. All cpus have bit 38 set to 0
         in msr 0x1a0.
    
    Change-Id: Id493e070c4a70bb236cdbd540d2321731a99aec2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182406
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5048
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3f94a74de29c660555d10fc3ddc18626668c618a
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jan 14 14:59:28 2014 -0800

    baytrail: Add ACPI Device for XHCI
    
    This will allow USB devices to wake the system (if 5V is not turned off)
    and the controller to enter D3 at runtime. (if autosuspend is enabled)
    
    BUG=chrome-os-partner:23629
    BRANCH=baytrail
    TEST=build and boot on baytrail
    
    1) with modified EC to leave 5V on in S3 ensure that waking from suspend
    with USB keyboard works.
    2) with laptop-mode-tools usb autosuepend config updated see that device
    enters D3 at runtime when no external devices attached.
    
    Change-Id: Ia396d42494e30105f06eb3bd65b4ba8b1372cf35
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182536
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5046
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5a45c9529a24a1be0a288fac2dab45b24e50c272
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jan 13 10:15:12 2014 -0800

    rambi: Add ACPI table support for I2C devices
    
    In order to support probing I2C devices when the controller is
    in ACPI mode the mainboard needs to decalre them in the proper
    scope with the address/interrupt information.  The touchpad devices
    are ATML0000/ELAN0000 and the touchscreen is ATML0001 so they can
    be distinguished in userland scripts based on ID.  There is also
    a special "ISTP" node that indicates whether the devices is a
    touchpad (=1) or touchscreen (=0) in case this is useful to drivers.
    
    These names may not be final but they are a starting point and can
    be easily changed.
    
    Atmel devices also have a bootloader mode which needs to be
    declared as a separate device.  Unfortunately it does not work as
    expected to have multiple I2cSerialBus() resources declared in a
    single device and have it select properly, even with the use of
    StartDependentFn(), so bootloader devices are declared separately.
    
    The original devices are left in \_SB scope and are only enabled
    if the I2C controllers are in PCI mode.  The new devices are only
    enabled if the I2C controllers are in ACPI mode.
    
    BUG=chrome-os-partner:24380
    BRANCH=baytrail
    TEST=manual
    
    1) Ensure there is no change in functionality by default and that
    the devices are still probed by chromeos_laptop in the kernel.
    2) Enable lpss_acpi_mode=1 in devicetree.cb and kernel changes to
    add _HID entries for devices in appropriate drivers.  Ensure that
    the devices are probed successfully.  Further changes are needed
    to the chromeos-touch-firmware scripts to load config and update
    firmware based on the new ACPI _HID entries.
    3) Put touchpad in bootloader mode (by flashing bad firmware) and
    ensure that it is detected at address 0x25 and the firmware is
    able to be updated.
    
    Change-Id: I5b9b47ddc94474a677497271e963f62cb09438e0
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182259
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5045
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b013fff5a3c036864c8f545f5cf645e27100209c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Jan 13 11:39:04 2014 -0600

    baytrail: nvm: use proper types for checking erase
    
    The current byte value was being converted to an int
    when checking against literal 0xff. As the type of
    the current pointer was char (signed) it was sign
    extending the value leading to 0xffffffff != 0xff.
    Fix this by using an unsigned type and using a
    constant type for expected erase value.
    
    BUG=chrome-os-partner:24916
    BRANCH=baytrail
    TEST=Booted after chromeos-firmwareupdate. Noted that MRC
         cache doesn't think the erased region isn't erased.
    
    Change-Id: If95425fe26da050acb25f52bea060e288ad3633c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182154
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5044
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 931e59074556988dfc4a2f32fe7fa7874a4e064e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Jan 13 11:34:51 2014 -0600

    baytrail: mrc_cache: check region erased before erasing
    
    On a firmware update the MRC cache is destroyed. On the
    subsequent boot the MRC region was attempted to be erased
    even if it was already erased. This led to spi part taking
    longer than it should have for an unnecessary erase
    operation. Therefore, check that the region is erased
    before issuing the erease command.
    
    BUG=chrome-os-partner:24916
    BRANCH=baytrail
    TEST=Booted after chromeos-firmeareupdate. Noted no
         error messages in this path.
    
    Change-Id: I6fadeb6bc5fc178abb0a7e3f0898855e481add2e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182153
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5043
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 58d6e18f0c963832ebfc3ad1aad48cfe1d65fd8a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Jan 10 11:48:45 2014 -0600

    rambi: disable SERIRQ native functionality
    
    Nothing can actually use this as the EC cannot speak
    using baytrail's SERIRQ protocol. Also, the voltage
    bridge is going away so nothing will be hooked up to it.
    Therefore disable this it.
    
    BUG=chrome-os-partner:24693
    BRANCH=rambi
    TEST=Built and booted.
    
    Change-Id: I406bb9c227578ec0a75eaf67143b3b27cb7880ae
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182082
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/5042
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f24318dfb631e05db83b2e676f34b2e3cfb3dd6d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 15 05:15:04 2014 +1000

    southbridge/amd/cimx/sb800: Unused func smbus_delay()
    
    Change-Id: Icc12aafc1462c08bca77a1798d4fae86b8250708
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5748
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit f6ba9f6a65cb737ed59d72cf2cdc6c942036fdb6
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed May 14 20:49:43 2014 +1000

    mainboard/lenovo/t520: too many arguments to pc_keyboard_init
    
    Fix build regression introduced in:
    a823f9b mainboard/lenovo: Add Lenovo Thinkpad T520 support
    
    Change-Id: I60d92f8cceda6427f43e6be9d78c2af82af4b061
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5738
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit a6130fc8f9c00e0c545389b4e407f0b745435a56
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon May 12 15:00:03 2014 +0300

    intel: Drop obsolete comments on MTRR usage
    
    Problem with UMA region allocation was fixed when MTRRs changed to use
    memrange implementation.
    
    Change-Id: I420dac30de2836a91596d81f88bb45b46f248532
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5719
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit a823f9b545b4a172c1c0f778b773f9ca13f0791e
Author: Zaolin <zaolin@das-labor.org>
Date:   Tue May 6 21:31:45 2014 +0200

    mainboard/lenovo: Add Lenovo Thinkpad T520 support
    
    Short list of known issues for this patchset:
    
    * Suspend/Resume - does not work
    * Combi pci card for SD/MMC card reader with IEEE1394 - not found
    * Shutdown - sometimes does not work as expected
    * At least mysterious harddrive i/o
    
    Change-Id: Iaba8d1f5e471cfeca20d82f4e1b416641e1f2ae9
    Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
    Reviewed-on: http://review.coreboot.org/5672
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 3d68b1a62af20894fc0137a9658587f12b84e004
Author: Zaolin <zaolin@das-labor.org>
Date:   Tue May 6 21:30:54 2014 +0200

    cpu/intel: Add CPU socket rPGA988B
    
    Used by the Lenovo ThinkPad T520
    
    Change-Id: I1009616cc4c18ebd0e3be7ceb50398617b49e3a3
    Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
    Reviewed-on: http://review.coreboot.org/5671
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Tested-by: build bot (Jenkins)

commit 580b1ad618315220d554b08db0cbafdebaf2114e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 9 15:29:49 2014 -0600

    baytrail: add C0 microcode update
    
    Include C0 microcode drop.
    
    BUG=None
    BRANCH=rambi,squawks
    TEST=Built. Booted B3 part.
    
    Change-Id: If454658235cd5a7b8640de0b3fa12dccddb0e9f6
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182080
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/5041
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 107b71c3a3101c307acadb75c1e1e2f7b96c5015
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 9 14:35:41 2014 -0600

    baytrail: reboot with EC in S0 with no MRC cache and EC in RW
    
    This improves boot time in 2 ways for a firmware upgrade:
    
    1. Normally MRC would detect the S0 state without an MRC cache
       even though it's told to the S5 path. When it observes this
       state a cold reset occurs. The cold reset stays in S5 for
       at least 4 seconds which is time observed by the end user.
    
    2. As the EC was running RW code before the reset after firmware
       upgrade it will still be running the older RW code. Vboot will
       then reboot the EC and the whole system to put the EC into RO
       mode so it can handle the RW update.
    
    The issues are mitigated by detecting the system is in S0 with
    no MRC cache and the EC isn't in RO mode. Therefore we can do the
    reboot without waiting the 4 secs and the EC is running RO so
    the 2nd reboot is not necessary.
    
    BUG=chrome-os-partner:24133
    BRANCH=rambi,squawks
    TEST=Booted. Updated firmware while in OS. Rebooted. Noted the
         EC reboot before MRC execution.
    
    Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182061
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5040
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 9f1a7cffabacdb6022e4579a6229eb5d29e9bcf4
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 9 14:28:05 2014 -0600

    chromeec: add function to reboot on unexpected image
    
    It's helpful to have a generic function that will tell
    the EC to reboot if the EC isn't running a specified
    image. Add that and implement google_chromeec_early_init()
    to utilize the new function still maintaing its semantics
    of if recvoery mode is enabled the EC should be running its
    RO image. There is a slight change in that no communication
    is done with the EC if not in recovery mode.
    
    BUG=chrome-os-partner:24133
    BRANCH=rambi,squawks
    TEST=Built and boot with recovery request. Noted EC reboot.
    
    Change-Id: I22240f6a11231e39c33fd79796a52ec76b119397
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182060
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5039
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit b376ea632f1498174d86fa8f8b78848607492055
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jan 9 10:10:15 2014 -0800

    baytrail: dptf: Add disable trip point methods
    
    Added a method in each temp sensor to disable the aux trip points
    and then a wrapper function to call this method for each enabled
    temperature sensor.
    
    The event handler function is changed to not use a switch statement
    so it does not need to be serialized.  This was causing issues
    with nested locking between the global lock and the EC PATM mutex.
    
    Some unused code in temp sensors that was added earlier is removed
    and instead a critical threshold is specified in _CRT.
    
    The top level DPTF device _OSC method is expanded to check for the
    passive policy UUID and initialize thermal devices.  This is done
    for both enable and disable steps to ensure that the EC thermal
    thresholds are reset in both cases.
    
    Additionally the priority based _TRT is specified with TRTR=1.
    
    BUG=chrome-os-partner:17279
    BRANCH=rambi
    TEST=build and boot on rambi, load esif_lf kernel drivers and start
    esif_uf application.  Observe that temperature thresholds are set
    properly when running 'appstart Dptf' and that they are disabled
    after running 'appstop Dptf'
    
    Change-Id: Ia15824ca42164dadae2011d4e364b70905e36f85
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182024
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5037
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit dec0148100cb05f5675c4f5127753cd32035930d
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jan 9 10:10:51 2014 -0800

    rambi: dptf: Set critical thresholds
    
    Set critical temperature thresdholds to 70C.  This will cause DPTF
    framework to shut down the system so it may need to be higher or
    lower but will need some testing.
    
    BUG=chrome-os-partner:17279
    BRANCH=rambi
    TEST=build and boot on rambi, start DPTF framework and observe it
    using specified critical thresholds.
    
    Change-Id: Ibbf6d814295eb5ff006cb879676b7613f5eb56a3
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182025
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5038
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 8be6759f79b033f4f87c49d340ee935e38b55f20
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jan 9 10:01:05 2014 -0800

    chrome ec: Fix temperature calcualtion in PATx methods
    
    The PATx methods will be passed a temperature in deci-kelvin,
    so it needs to be converted back to kelvin before being sent
    to the EC.
    
    The PAT disable method is changed to take the temperature ID
    as an argument so individual sensors can be disabled.
    
    BUG=chrome-os-partner:17279
    BRANCH=rambi
    TEST=build and boot on rambi, load esif_lf kernel drivers and
    esif_uf userspace application.  Start and stop DPTF and see
    that temperature thresholds are set to sane values.
    
    Change-Id: Ieeff5a5d2d833042923c059caf3e5abaf392da95
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182023
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5036
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit b3ce6586085f11412ab58852153c18678c330a3e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue May 13 09:23:10 2014 -0500

    chrome ec: call DPTF thermal threshold event handler
    
    When an EC thermal event occurs call the DPTF thermal threshold
    event handler to handle notifications.
    
    Change-Id: Ica928790bb478fccf8a46afef4eb7800589518b2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5726
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit a36d60af1ab93945bd216ec3b698f9358840cd96
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jan 6 12:33:59 2014 -0800

    baytrail: Updates for DPTF ACPI framework
    
    - Remove some unused functions from CPU participant that were
    confusing the userland component since the CPU does not have
    an ACPI managed sensor.
    
    - Guard the charger participant with an ifdef so it can be
    left out if not supported.
    
    - Use the EC methods for setting auxiliary trip points and for
    handling the event when those trip points are crossed.
    
    - Add _NTT _DTI _SCP methods for thermal sensors.  I'm not
    clear if these are required or not but they seem to be expected
    by the other DPTF framework components.
    
    BUG=chrome-os-partner:17279
    BRANCH=rambi
    TEST=build and boot on rambi and load ESIF framework
    
    Change-Id: I3c9d92d5c52e5a7ec890a377e65ebf118cdd7087
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181662
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5028
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 93e244433a510cd57012973192cffb3fa50d66e3
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jan 6 12:30:52 2014 -0800

    chrome ec: Update header and add functions to support DPTF
    
    The EC now supports two auxiliary programmable trip points for
    thermal monitoring.  These are expected to be used by DPTF and
    need to be exported.
    
    In order to support these the header was updated from the latest
    chrome ec source.
    
    BUG=chrome-os-partner:17279
    BRANCH=rambi
    TEST=build and boot on rambi
    
    Change-Id: I257d910daac4e36280c0cecf4129381a32ffcb9a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181661
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5027
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 063b2c4df71e54c674d729eae021da3e340bc110
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jan 6 12:35:36 2014 -0800

    rambi: Update the DPTF configuration
    
    - Add passive thresholds for thermal participants
    - Disable the charger participant and remove from _TRT
    
    BUG=chrome-os-partner:17279
    BRANCH=rambi
    TEST=build and boot on rambi and start ESIF framework
    
    Change-Id: Ie5917413aceadee6e39594257aaafb0bcb399d09
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181663
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5029
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 766482d320e5ec861e72fdb933d73bdfa72c1fb4
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 9 10:44:06 2014 -0600

    baytrail: don't SMI on tco timer firing
    
    The SMI on TCO timer timeout policy was copied from other
    chipsets. However, it's not very advantageous to have
    the TCO timer timeout trigger an SMI unless the firmware
    was the one responsible for setting up the timer.
    
    BUG=chromium:321832
    BRANCH=rambi,squawks
    TEST=Manually enabled TCO timer. TCO fires and logged in
         eventlog.
    
    Change-Id: I420b14d6aa778335a925784a64160fa885cba20f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181985
    Reviewed-on: http://review.coreboot.org/5035
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 19edc3a2e53eb54994a99ca8a868480badcbf227
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 9 11:17:37 2014 -0600

    baytrail: clear the pmc wake status registers
    
    The PMC in baytrail maintains an additional set
    wake status in memory-mapped registers. If these
    bits aren't cleared the device won't be able to
    go to S5 or S3 without being immediately woken up.
    Therefore clear these registers.
    
    BUG=chrome-os-partner:24913
    BRANCH=rambi,squawks
    TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work
         correctly.
    
    Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181984
    Reviewed-on: http://review.coreboot.org/5034
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 8f31ecf28b9788d007be746fc85160cb6e91c1ca
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 9 10:41:30 2014 -0600

    baytrail: log reset, power, and wake events in elog
    
    When CONFIG_ELOG is selected the reset, power, and wake
    events are logged in the eventlog.
    
    BUG=chrome-os-partner:24907
    BRANCH=rambi,squawks
    TEST=Various resets and wake sources. Interrogated eventlog
         to ensure results are expected.
    
    Change-Id: Ia68548562917be6c2a0d8d405a5b519102b8c563
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181983
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5033
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 00bf3dbf350b48e78aab413958ec83692d8fa263
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 9 10:33:23 2014 -0600

    baytrail: snapshot power state in romstage
    
    The memory reference code doesn't maintain some of
    the registers which contain valuable information in order
    to log correct reset and wake events in the eventlog. Therefore
    snapshot the registers which matter in this area so that
    they can be consumed by ramstage.
    
    BUG=chrome-os-partner:24907
    BRANCH=rambi,squawks
    TEST=Did various resets/wakes with logging patch which
         consumes this structure. Eventlog can pick up reset
         events and power failures.
    
    Change-Id: Id8d2d782dd4e1133113f5308c4ccfe79bc6d3e03
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181982
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5032
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 1ea9bde5af87fa786147773fcf2ee3faa7861945
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Jan 8 17:33:05 2014 -0600

    baytrail: add cpuid for C0
    
    The C0 part uses a new cpuid.
    
    BUG=None
    BRANCH=squawks,rambi
    TEST=None.
    
    Change-Id: Iddf1bc4d6f7bbec3ca92bff8edf613e00a4b4286
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181980
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/5031
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit b697eab9383b9ab23b7cdd2bc2a1969e6e135717
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Tue Jan 7 12:37:59 2014 -0800

    rambi: Move KBD_IRQ pin for Rambi 2.0 board
    
    KBD_IRQ# is moved to GPIO SC101, with SC50 going back to its original
    SERIRQ function.
    
    Note that this change breaks Rambi 1.5 keyboard functionality.
    
    BUG=chrome-os-partner:24424
    TEST=Manual on Rambi 2.0. Verify KB functions in OS with SC50 / SERIRQ KB
    interrupt toggling removed from EC code.
    BRANCH=Rambi, Glimmer, Clapper
    
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Change-Id: I3fa40441741ea9d52a6e2ff15925570510b5b82b
    Reviewed-on: https://chromium-review.googlesource.com/181757
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Randall Spangler <rspangler@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5030
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit e1fe688c9bf69781d40ef8568b35ea307eaa41a8
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Apr 30 20:41:41 2014 +1000

    src/*: Remove the last remnants of struct keyboard
    
    Change-Id: I7d0e8d2119a470428cfc01c0738b8988ab75ba2d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5624
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit f6f1ad6376fd3770c40c66b45ee89fe7029683de
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Apr 30 19:25:05 2014 +1000

    superio/*: Remove redundant chip.h header
    
    Change-Id: If7141112ea67071ee05c52f455c3b2496aa7e17e
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5622
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 0403c863e16a028bc4c55b0f6b7310f83d77e24c
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Apr 30 17:17:03 2014 +1000

    superio/*: Deal with some chip.h special cases
    
    While backing out the empty pc80 keyboard struct we encountered some
    special cases where chip.h is used for other purposes. Deal with these
    cases.
    
    Change-Id: Ib11a46cfd14d050d5daa213623b9d8a401c06410
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5621
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit def00be41db96971a92b78f3f23343c344d82c43
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Apr 30 05:01:52 2014 +1000

    src/drivers/pc80: Remove empty struct keyboard
    
    This is a empty struct that has propagated through the superio's & ec's
    but really does nothing. Time to get rid of it before it adds yet more
    cruft. However, since this touches many superio's at once we do this in
    stages by first changing the function type to be a pure procedure.
    
    Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5617
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit e61dd0f7a2be83ce5ba87d74f7384111576ffd49
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue May 6 23:53:09 2014 +1000

    southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
    
    We should configure i8254/i8259 down in to the southbridge rather than
    romstage of every AGESA/CIMx board much like Intel boards do.
    
    Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5669
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 216a619a74d61f66e3d3e1d668028d11a8868b4d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon May 12 23:16:18 2014 +0300

    Rambi: Enable 32k SUSCLK signal
    
    The SoC needs to provide a 32k clock signal SUSCLK for
    some modems to work properly, so this enables the signal.
    
    BUG=chrome-os-partner:24425
    TEST=Manual, check SUSCLK pin with a scope.
    
    Change-Id: Ibc0d5bb38a2c3e16f381dfc256097fdced67fd1c
    Reviewed-on: https://chromium-review.googlesource.com/180101
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
    Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
    Tested-by: Bernie Thompson <bhthompson@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5722
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>
    Tested-by: build bot (Jenkins)

commit 6a70258c696090bb10d65f2a57b91348c7382477
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Fri Dec 20 13:27:56 2013 -0800

    rambi: Make eMMC CLK pull-down and change pull strengths to 20K
    
    eMMC CLK was incorrectly configured as PULL_UP, but should have been
    PULL_DOWN. 2K pulls somehow masked this problem.
    
    BUG=chrome-os-partner:24353
    TEST=Verify eMMC is bootable on Rambi on boards that previously failed
    with an all-20K, all-PU eMMC pin configuration.
    BRANCH=None
    
    Change-Id: I0cbb6ebbb6818f83402b99330728266b09a0f5d6
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/181034
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5026
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 003931975f975145e25c0987aaa87344a30cb6af
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Dec 18 14:37:31 2013 -0600

    baytrail: align with intel recommendations
    
    The BISOC.EXIT_SELF_REFRESH_LATENCY field should
    not be updated from the default.
    
    BUG=chrome-os-partner:24345
    BRANCH=None
    TEST=Built and booted. S3 resumed.
    
    Change-Id: I6e701a520513372318258648e998dd8c7ab29ea4
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/180730
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/5025
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 68530cdb7c1b381a103256fd46e882c904dc47c2
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Dec 13 13:08:59 2013 -0800

    rambi: specify reference code index in vboot area
    
    Rambi's reference code will live at slot 3 in the
    verified firmware section.
    
    BUG=chrome-os-partner:22867
    BRANCH=None
    TEST=Built and booted. Verified correct area where
         reference code was loaded from.
    
    Change-Id: I8bee46600429ac8f732fe334852f69aff1324150
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/180027
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/5024
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7f17759e8228330cfde832a9384ec2990693d4c9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Dec 13 13:05:24 2013 -0800

    baytrail: add way to load reference code from vboot area
    
    When employing vboot firmware verification the reference
    code loading should load from the verified firmware
    section. Add this ability.
    
    BUG=chrome-os-partner:22867
    BRANCH=None
    TEST=Built and booted rambi. Noted firmware being loaded
         from rw verified area. Also noted S3 resume loading
         from cached area.
    
    Change-Id: I114de844f218b7573cf90107e174bf0962fdaa50
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/180026
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/5023
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 2e657964814b95de64406c50d08fc997f1c93887
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Dec 13 16:43:11 2013 -0800

    baytrail: Expose IOSF as ACPI object
    
    The kernel iosf driver uses HID INT33BD to probe and
    be provided the 12 bytes in PCI for access.
    
    BUG=chrome-os-partner:17279
    BRANCH=none
    TEST=build and boot on rambi, load iosf_mbi driver and
    verify that it gets address 0xe00000d0
    
    Change-Id: I865eafe664f00f21d1ebb967c291083830d895b9
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/180098
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5021
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 73c0a05bc704659fcd1c70cc5d97e134de54c8f3
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Dec 13 16:01:56 2013 -0800

    rambi: Disable HSUART2 and SPI interfaces
    
    Not used currently on rambi board.  Disable in case it
    saves power.
    
    BUG=chrome-os-partner:23862
    BRANCH=none
    TEST=build and boot on rambi
    
    Change-Id: Idb870c2cfa88cb6c3f1ada3caf0db566e33ec1eb
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/180084
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5020
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7e647f596c007567e421defd0d2963070daed497
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Dec 12 15:51:52 2013 -0800

    rambi: Enable SCC devices in ACPI mode
    
    With the ACPI GNVS exported and depthcharge changed to
    initialize eMMC in ACPI mode we can now put the SCC
    devices into ACPI mode.
    
    BUG=chrome-os-partner:24380
    BRANCH=none
    TEST=build and boot on rambi, test eMMC and SD card
    
    Change-Id: I39716198f8227c0c3293ac23eb09660792e2c51b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179901
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5018
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit c29d6b8ab2a963e51dafe17b45a826f4c1627795
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Dec 12 16:55:36 2013 -0800

    baytrail: Put devices in ACPI mode after setup
    
    Make sure reg_script is executed before the device is put into
    ACPI mode.
    
    BUG=chrome-os-partner:24380
    BRANCH=none
    TEST=build and boot rambi from eMMC in ACPI mode
    
    Change-Id: I4090babbfc7fb0f3be4da869386e998d87a513ba
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179896
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5017
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit d82caded48a7b2a3f0e8662e3e35a30aa7839743
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Dec 12 10:42:31 2013 -0800

    baytrail: Add header include wrapper and offset define
    
    Since this file will get added to payloads it is useful if it
    exports what offset in NVS it lives.
    
    BUG=chrome-os-partner:24380
    BRANCH=none
    TEST=build and boot rambi with emmc in ACPI mode
    
    Change-Id: I52860980c91dfe2525628e142b34ca192e69b258
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179848
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5014
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 2e4dea663ce9f23f8cd925803b045259219d927d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon May 12 05:02:58 2014 +1000

    superio/ite/it8718f: Remove hard coding from romstage
    
    Make use of the ITE common Super I/O framework and there-by removing any
    hard coding of Super I/O base address.
    
    Change-Id: I14af89d2727d7c6bac0f9840043c430726297429
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5717
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit f29200240e428761827ab8d179fa23068bfa9d59
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Apr 27 00:41:50 2014 +1000

    superio/ite/*: Factor out generic romstage component
    
    Following the reasoning of:
    cf7b498 superio/fintek/*: Factor out generic romstage component
    
    Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5585
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 946bee1c349db6bf88b4f6736dc910eb4890a74b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue May 6 18:00:07 2014 +1000

    superio/ite/it8728f: RAMstage PNP configuration component
    
    Provide devicetree.cb RAMstage configuration of this superio component.
    
    Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5668
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 31dbb536fae937f9201312f2c47213c65ca9d939
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 10 14:21:38 2014 +0200

    SeaBIOS: Fix cpp use
    
    No need to pass CPP down to SeaBIOS, it's not
    architecture specific and they define their own
    variable.
    
    Change-Id: I811aaf3929fa11cc01b7f168ccd310008e21e60c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5715
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit a3b06c99d066600c3462fe5fdebc5006cb9631ea
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue May 6 18:00:19 2014 -0700

    Arch-level Kconfig menu cleanup
    
    Remove arch-level Kconfig menu option as it shows all available architectures in
    make menuconfig. Instead pull the bootblock options for choice and update image
    to top-level Kconfig since it is already present for both x86 and arm.
    
    Change-Id: Iab9c4539f05cd54a7f751565fefcaf7b6f0edc86
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: http://review.coreboot.org/5673
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5c3f384f064f5c05945d561784fd7e8ef002a295
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu May 8 15:27:15 2014 +0300

    Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT
    
    Lines with 'select SERIAL_CPU_INIT' where redundant with the
    default being yes. Since there is no 'unselect SERIAL_CPU_INIT'
    possibility, invert the default and rename option.
    
    This squelches Kconfig warnings about unmet dependencies.
    
    Change-Id: Iae546c56006278489ebae10f2daa627af48abe94
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5700
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit a7e2cc507b520583fe2e727371e431d65924ee53
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 8 20:45:09 2014 +1000

    mainboard/jetway/nf81-t56n-lf: Toggle WDT and CIR in devicetree.cb
    
    Turn on WDT support in the devicetree. Turn off CIR support.
    Dispense with old commentary.
    
    Change-Id: Icf0c0e12a0ed7ce6c3b6176653e076ffc2ba937e
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5698
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit c848098b2fc1a93b777fa811c988ce2f9b732816
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 8 19:50:55 2014 +1000

    superio/fintek/f71869ad: Fix incorrect LDN's
    
    Turns out there are a few minor differences of the LDN's in the AD rev.
    of this Fintek chip. 0x07 is in fact the WDT so renaming and remove the
    now incorrect io mask. Add missing CIR LDN functionality and touch up
    src inline doc.
    
    Change-Id: I440aebad71d62d199d3283dd061933e76b21dda5
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5696
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 63fcb4a1f89f1b74f834249b1bc683da280221fa
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Dec 12 10:29:48 2013 -0800

    baytrail: cache reference code for S3 resume
    
    In order to use the same reference code on S3 resume
    that was booted the program needs to be cached. Piggy
    back on the ramstage cache to save the loaded reference
    code program.
    
    BUG=chrome-os-partner:22867
    BRANCH=None
    TEST=Built and booted. S3 resumed. Noted locations of reference
         code caching and load addresses in console.
    
    Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179777
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5013
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ce727e18f0992126b7a27b8a51b426834e804390
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Dec 12 10:27:11 2013 -0800

    baytrail: allow ramstage_cache_location() usage in ramstage
    
    To prepare for caching reference code for S3 resume the
    ramstage cache needs to be accesible in ramstage as well.
    
    BUG=chrome-os-partner:22867
    BRANCH=None
    TEST=Built and booted. S3 resumed.
    
    Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179776
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5012
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit be2512973d04f3da3cebfd3e7ee10809fbe4ae4a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Dec 12 10:10:52 2013 -0800

    ramstage_cache: allow ramstage usage add valid helper
    
    Allow ramstage cache to be used from ramstage proper. Also
    add a helper function for checking validity of ramstage
    cache structure.
    
    BUG=chrome-os-partner:22867
    BRANCH=None
    TEST=Built and booted. S3 resumed.
    
    Change-Id: If1f2ad1bcf64504b42e315be243a12432b50e3d5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179775
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5011
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 7d34c6070b8fc2e8dc2f5274794e2374a883d4ce
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Dec 12 10:07:00 2013 -0800

    baytrail: note S3 resume status earlier
    
    Certain code paths want to know if S3 resume is
    happening. However, the current baytrail code doesn't
    note S3 resume early enough. Therefore, mark S3
    resume just after pattr setup.
    
    BUG=chrome-os-partner:22867
    BRANCH=None
    TEST=Built and booted. S3 resumed.
    
    Change-Id: I5e5cc285940e4567521afb8483614ce6f813ddde
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179774
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5010
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 616f394d3656760deb1e048c0dde4fe3aaa6607f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Dec 10 17:12:44 2013 -0800

    baytrail: utilize reg_script_run_on_dev()
    
    The inclusion of reg_script_run_on_dev() allows
    for removing some of the chained reg_scripts just
    to set up the device context. Use the new reg_script
    function in those cases.
    
    BUG=None
    BRANCH=None
    TEST=Built and booted. Didn't see any bizarre dmesg or coreboot
         console output.
    
    Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438
    Signed-off-by: Aaron Durbin <adurbin@chromium.og>
    Reviewed-on: https://chromium-review.googlesource.com/179541
    Tested-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5009
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit cffe795dc1516607421bf770eab45076087fc461
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Dec 11 17:15:45 2013 -0800

    baytrail: initialize perf/power registers
    
    According to the reference code all these registers
    need to be set to their best known values.
    
    BUG=chrome-os-partner:24345
    BRANCH=None
    TEST=Built and booted. Suspend and wake. No idea about
         observable impact yet.
    
    Change-Id: I0e31505a165eee1d177e5d726edcfa6947430476
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179749
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5008
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit bc5b557a814be2790d4cea4267046dd8e3fdcb72
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Dec 11 17:13:10 2013 -0800

    baytrail: add more iosf access functions
    
    There's a slew of ports required to initialize baytrail's
    perf and power values. Therefore, add the necessary
    functionality in the iosf module as well as the reg_script
    library.
    
    BUG=chrome-os-partner:24345
    BRANCH=None
    TEST=Built and booted.
    
    Change-Id: Id45def82f9b173abeba0e67e4055f21853e62772
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179748
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5007
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 5cc3b401d8abc394540f9e8b0c8c33cf5a26b141
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Dec 11 17:10:58 2013 -0800

    baytrail: remove verbosity in iosf
    
    The iosf access functions already use some common code,
    however there is a duplication for setting up the proper
    control register for port and opcode. Introduce macros
    to remove this verbosity.
    
    BUG=chrome-os-partner:24345
    BRANCH=None
    TEST=Built and booted. Suspend and wake.
    
    Change-Id: I5bad7e2a11fa8e8bd4a3d7fa53d917b2565644f8
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179747
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5006
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit d86f0b743fba5d02cfc1500997f6c6f5e4250eb5
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Dec 10 17:09:40 2013 -0800

    reg_script: add reg_script_run_on_dev()
    
    The reg_script library has proven to be useful. It's
    also shown that many scripts operate on devices. However,
    certain code paths run the same script on multiple,
    but different, devices. In order to make that easier
    introduce reg_script_run_on_dev() which takes a device
    as a parameter. That way, chained reg_scripts are not
    scrictly needed to run the same script on multiple devices.
    
    BUG=None
    BRANCH=None
    TEST=Built.
    
    Change-Id: I273499af4d303ebd7dc19e9b635ca23cf9bb2225
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179540
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5005
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 430bf0d8a96bf9bb3c343c5cf63c6ae8482c532c
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Dec 10 14:37:42 2013 -0800

    baytrail: Add support for LPSS and SCC devices in ACPI mode
    
    This adds the option to put LPSS and SCC devices into ACPI mode
    by saving their BAR0 and BAR1 base addresses in a new device
    NVS structure that is placed at offset 0x1000 within the global
    NVS table.
    
    The Chrome NVS strcture is padded out to 0xf00 bytes so there
    is a clean offset to work with as it will need to be used by
    depthcharge to know what addresses devices live at.
    
    A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and
    the EMMC 4.5 IRQ is changed to 44.
    
    New ACPI code is provided to instantiate the LPSS and SCC devices
    with the magic HID values from Intel so the kernel drivers can
    locate and use them.
    
    The default is still for devices to be in PCI mode so this does
    not have any real effect without it being enabled in the mainboard
    devicetree.
    
    Note: this needs the updated IASL compiler which is in the CQ now
    because it uses the FixedDMA() ACPI operator.
    
    BUG=chrome-os-partner:23505,chrome-os-partner:24380
    CQ-DEPEND=CL:179459,CL:179364
    BRANCH=none
    TEST=manual tests on rambi device:
    
    1) build and boot with devices still in PCI mode and ensure that
    nothing is changed
    
    2) enable lpss_acpi_mode and see I2C devices detected by the kernel
    in ACPI mode.  Note that by itself this breaks trackpad probing so
    that will need to be implemented before it is enabled.
    
    3) enable scc_acpi_mode and see EMMC and SDCard devices detected by
    the kernel in ACPI mode.  Note that this breaks depthcharge use of
    the EMMC because it is not longer discoverable as a PCI device.
    
    Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179481
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5004
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 0e6be39f8b9411c356f1e10550ba0424c7caddd7
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 10 04:42:00 2014 +1000

    Makefile: Don't use llvm-mc for the moment
    
    The LLVM integrated assembler has some deficiencies in support for
    building AGESA. See:
    
    LLVM PR18918 - [RFE]: Missing altmacro support in integrated assembler
    
    Disable llvm-mc for the moment until these have been addressed fully
    upstream.
    
    Change-Id: Id4131d1de04d01c0bec284f976f0ba9662b950ab
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5711
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 868648c41de67f1794da5df275740be6fd30411f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat May 10 04:39:06 2014 +1000

    Makefile.inc: Make clang once again a valid toolchain
    
    'prove' that clang is supported (to some extent).
    
    Change-Id: I181f4910ba64ab9746e7ac94aa79da23cdd41dad
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5709
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 3ee43171ef4b2f5a3513fc785802a02afb4af4a9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri May 9 20:41:01 2014 +0200

    payloads: make build system integration work again
    
    Payloads using Kconfig get confused by coreboot Kconfig
    configuration in environment variables. Prune them.
    
    Change-Id: I63da2af0a15dca35d70cd65b2f74a1564aab9483
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5710
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 2dd3f877cc7926f5ac1cfd5a7e5d546c8be2121c
Author: Martin Roth <gaumless@gmail.com>
Date:   Fri Apr 25 15:09:27 2014 -0600

    cougar_canyon2: Switch CPU/NB/SB to the shared FSP code
    
    CPU - fsp_model_206ax:
    - Remove Kconfig options and mark this as using the FSP.
    - Use shared FSP cache_as_ram.inc file
    Mainboard - intel/cougar_canyon2:
    - Update to use the shared FSP header file.
    - Modify to call copy_and_run() directly instead of returning to
    cache_as_ram.inc.
    Northbridge - fsp_sandybridge:
    - remove mrccache, fsp_util.[ch]
    - add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits.
    - Update to use the shared FSP header file.
    
    These changes were validated with FSP:
    CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd
    SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801
    MD5: 24965382fbb832f7b184d3f24157abda
    
    Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5636
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit a6427161c20bfb8319208dbbd08697a530a3839e
Author: Martin Roth <gaumless@gmail.com>
Date:   Fri Apr 25 14:12:13 2014 -0600

    Intel FSP: add a shared set of functions for the FSP
    
    - Move the non chipset-specific fsp pieces out of the chipset into a
    shared area.  This is used by northbridge / southbrige / SOC code.  It
    pulls in pieces from Kconfig, Makefile and FSP specific code.
    - Enabled in the CPU code with a Kconfig "select PLATFORM_USES_FSP"
    
    Change-Id: I7ffa934c1df09b71d48a876a56e3b888685870b8
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/5635
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit f18abab20047a23d7b29705ce274920ad36cd18a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Mar 31 21:53:32 2014 +1100

    superio/serverengines/pilot: Avoid .c includes
    
    Following the same reasoning as commit
    d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid
    .c includes
    Clean up the early_serial #include directives in mainboard/romstage code.
    
    Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5439
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 618de689c348fa7aa4eaaa256eccc8efdf76d91c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu May 8 14:35:52 2014 +0300

    Squelch some warnings from Kconfig
    
    Overriding global config entries in mainboard directory Kconfig
    files often raise unnecessary warnings. Squelch some of those.
    
    Change-Id: Ib5127672ae068670028aa25c8ccb5366277622f2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5699
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b2757572121f503176ebdc311591536336811953
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu May 8 11:54:25 2014 -0500

    cbfstool: account for the trampoline code in bzImage payload
    
    For bzImages the trampoline segment is added unconditionally.
    However, that segment wasn't properly being accounted for.
    Explicitly add the trampoline segments like the other ones.
    
    Change-Id: I74f6fcc2a65615bb87578a8a3a76cecf858fe856
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5702
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 639f02b3bae1a7914501123c086491e442ea96f1
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu May 8 23:30:12 2014 +0200

    payloads/coreinfo/README: Use `It is` instead of `Its`
    
    Change-Id: Ic1a9f2f01c26ee97cd7183fcf1755cb916f1b02e
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5704
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4acd3c05d61562745321a9fe4d25a6ca98c66f05
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Dec 10 07:48:00 2013 -0800

    rambi: Enable DPTF
    
    This enables the DPTF framework, but it doesn't do much
    without some sort of kernel+user components to drive it.
    
    BUG=chrome-os-partner:17279
    BRANCH=none
    TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF
    
    Change-Id: Icb632a6e70c3912bbdfa6ef3f5c87cd79d2b8a3a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179480
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5003
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ad8d913f42b4dff80502456a08aac06e7fbcd0dd
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Dec 10 07:41:33 2013 -0800

    baytrail: Basic DPTF framework
    
    This is not complete yet but it compiles and doesn't cause
    any issues by itself.  It is tied into the EC pretty closely
    so that is part of the same commit.
    
    Once we have more of the EC support done it will need some
    more work to make use of those new interfaces properly.
    
    BUG=chrome-os-partner:17279
    BRANCH=none
    TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF
    
    Change-Id: I4b27e38baae18627a275488d77944208950b98bd
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179459
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5002
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 4cc4b04d8a5c5b2bdc5b0fcd34cf4ae6352b32c2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Dec 9 14:40:05 2013 -0800

    rambi: Set panel power timings
    
    These are the values that are seen with VBIOS and
    may need tweaked for derivative panels.
    
    BUG=chrome-os-partner:24367
    BRANCH=none
    TEST=boot on rambi in normal mode and see the panel come up
    
    Change-Id: Ie3120ab3c5298135626e8534d3954acd263dc74b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179365
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5001
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit b40e444aee50c4b9768b596f0d7cf726f8d2c10f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Dec 9 14:38:57 2013 -0800

    baytrail: Enable panel and set timings
    
    These need to be set before the kernel will work without
    running the VBIOS option rom.
    
    Also necessary is setting the PP_CONTROL register with
    the EDP_FORCE_VDD bit.
    
    BUG=chrome-os-partner:24367
    BRANCH=none
    TEST=boot on rambi in normal mode and see the panel come up
    
    Change-Id: I495f818d581d08b80db11785fe28b601ec956b3b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179364
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5000
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7b35706cf351675fc7b120a1d1d68baa9e2c717c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Dec 10 09:17:18 2013 -0800

    rambi: change SD card pulls to 20K
    
    Now that the SD card controller is limited to the SD card
    2.0 spec it's possible to use 20K pulls for the pads.
    
    BUG=chrome-os-partner:24423
    BUG=chrome-os-partner:24312
    BRANCH=None
    TEST=Built and booted. Able to dd to/from /dev/mmcblk1 without
         any errors.
    
    Change-Id: Id5396c55330a84bf7a09d227507d2bfcde66a1a4
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179423
    Reviewed-on: http://review.coreboot.org/4999
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 40b7455f9337605b0f3062a6feacb82f43099186
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Dec 10 09:01:41 2013 -0800

    rambi: limit SD card controller to 2.0 spec
    
    The rambi board can only meet the SD card 2.0 specification.
    Therefore, the controller capabilities need to be overridden
    to match.
    
    BUG=chrome-os-partner:24423
    BRANCH=None
    TEST=Built and booted. /sys/kernel/debug/mmc0/ios shows
         high speed as maximum timing as well as 3.3V signal voltage.
    
    Change-Id: Ib3824800852376e0f15a70584917d6692087ccfe
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179415
    Reviewed-on: http://review.coreboot.org/4998
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 8b120a87c37c3667e8d19689500a1641fd98143e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Dec 10 08:35:51 2013 -0800

    baytrail: allow SD card controller capabilities overrides
    
    The SD card controller can have the capabilities it supports
    to be overridden. Add two optional fields to the chip structure
    to allow the mainboard to override the SD card controller
    capabilities.
    
    BUG=chrome-os-partner:24423
    BRANCH=None
    TEST=Built and booted. Noted capabilities override console output.
    
    Change-Id: Ibfef8f765b35eeec6da969dd05f5484f8672a7b9
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179414
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4997
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 16cc9c9599262828407146129485590d90600ad7
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Dec 9 15:03:34 2013 -0800

    baytrail: fix nvs offsets
    
    The VDAT data was off by 2 bytes when reading it from the
    kernel. The reason is that the header did not line up
    correctly with actual ACPI code.
    
    BUG=chrome-os-partner:24440
    BRANCH=None
    TEST=crossystem devsw_cur now returns either 0 or 1 depending
         on state.
    
    Change-Id: Ie78599f29cd5daf7da98db5e37fa276d24339f6a
    Signed-off-by: Aaron durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179372
    Reviewed-on: http://review.coreboot.org/4996
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7538937d6e7c474dc7c17a1bc3c3591f0e6ef311
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Dec 9 13:41:32 2013 -0600

    rambi: export SPI write-protect GPIO correctly
    
    Bay Trail has 3 banks of gpios. Therefore, in order to
    properly identify a gpio the specific bank number as well
    as the GPIO within that bank is needed. The SPI
    write-protect GPIO is GPIO 6 within the SUS bank (offset
    0x2000).
    
    BUG=chrome-os-partner:24324
    BUG=chrome-os-partner:24408
    BRANCH=None
    TEST=Built and booted. Looked at GPIO sysfs in the
         chromeos_acpi directory.
    
    Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179195
    Reviewed-on: http://review.coreboot.org/4995
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit f4fe3c303ca5fe8124f48973eef2f798771be0fd
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Dec 9 12:52:37 2013 -0600

    baytrail: lpe audio device needs memory for its firmware
    
    The LPE audio device needs 1MiB of memory for its firmware.
    It also has a requirement that the memory needs to be on a
    512MiB boundary. Just take 1MiB @ 512MiB for the LPE device.
    
    BUG=chrome-os-partner:23791
    BRANCH=None
    TEST=Built and analyzed console logs for resources. Also interrogated
         registres within the kernel.
    
    Change-Id: I4d9ad5c7b5a2f3eb627b30528d738289278b3a7b
    Reviewed-on: https://chromium-review.googlesource.com/179192
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4994
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit c087a9e46988f1842ec5525607fa19953f9cbbad
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu May 8 11:14:41 2014 -0500

    toolchain: get rid of some bashisms
    
    On Ubuntu /bin/sh is symlinked to /bin/dash. The
    current toolchain.inc was doing some things that
    dash doesn't support. Make the shell callouts more
    conforming to the POSIX sh standard.
    
    Change-Id: I26b6b82b8d6158c9029e8be9e7c088ca9e207f21
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5701
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5c4b8483d2de976cb3957cc9ea23086041ed9625
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat May 3 13:29:06 2014 +0300

    ChromeOS boards: Always build code for bootmode straps
    
    Leave it under BOOTMODE_STRAPS to control whether these have
    any functional meaning on the build.
    
    Change-Id: Ieb59aa7ab4b1e8da6a1002e7a8e5462eb7988d35
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5643
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ab7280970a96eb5a604a37ffd913355a1f40fb88
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat May 3 16:47:52 2014 +0300

    ChromeOS boards: Fix includes
    
    Change-Id: Ib8448f3d36a23538cd9fea897f09da3ec4ad007a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5647
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1645589ce7c0312e71b6226b95b3fa888d55ddcd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Apr 28 23:41:06 2014 +0300

    Declare get_write_protect_state() without ChromeOS
    
    Change-Id: I72471ac68088cd26f8277b27b75b7d44ad72cfc4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5642
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit e3ddee0437bbae0f0059dfb13560be731ac86e9b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat May 3 10:45:28 2014 +0300

    Rename from save_chromeos_gpios() to init_bootmode_straps()
    
    This feature is no longer specific to ChromeOS builds.
    
    Change-Id: If27d4dc7caff8a551b5b325cdebdd05c079ec921
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5641
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit ff402e3aebcca0654753211cb1c46fd8aba390d0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Apr 28 23:41:06 2014 +0300

    ChromeOS boards: Use explicit include of chromeos.c
    
    Change-Id: I7b3d044fad1d6973910e9bef347478a45c149a4f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5640
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 63f28c00aa32662c432565fc417e1f9d1fde6122
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Apr 26 15:21:45 2014 +1000

    superio/fintek/f71869ad: Make hwm devicetree configurable
    
    Provision the configuration of the Fintek F71869AD Hardware Monitor's
    configuration by way of devicetree.cb. Make use of this in the
    jetway/nf81-t56n-lf board to properly control fan's.
    
    Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5580
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit dd2e8c35fb368316b51d969d046696a017f09d25
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Apr 24 02:58:11 2014 +1000

    superio/fintek/f71869ad: Configure multi-func reg in devicetree
    
    Facilitate for the configuration of so called "Multi-function Select
    Registers" with devicetree.cb in ramstage.
    
    Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to
    correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI
    mode. This allows the Fintek to correctly talk to the Southbridge over
    the SMBus for CPU temperature data as to control fans and so on.
    
    Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5576
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 708be1a45356b33eaf5f287e529a99fb856736af
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Apr 6 12:34:56 2014 +1000

    mainboard/jetway/nf81-t56n-lf: Improve diags in romstage
    
    romstage reports a completely unintelligible printf of "error level:",
    fix this and document meaning of the return values in source.
    
    Change-Id: Ia2fb9a6206e08822f6c2f62b69bf22cdae2ba819
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5465
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9928197c2678d6b19df40fe0d049f237bc924614
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Sat Dec 7 17:08:27 2013 -0800

    rambi: Make ec_in_rw a legacy GPIO
    
    ec_in_rw needs to be read by depthcharge, which only supports legacy
    GPIOs.
    
    BUG=chrome-os-partner:24408
    TEST=Manual on Rambi. Cold + warm boot device, verify that depthcharge
    detects the proper ec_in_ro state.
    BRANCH=None
    
    Change-Id: I25802b445c795eb85580c22d880efee8eeb21318
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179228
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4993
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 27351b93c07e62a1b23dd492b625f0eca6e9283a
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Fri Dec 6 16:58:10 2013 -0800

    baytrail: gpio: Make GPIO inputs MMIO by default
    
    The Linux kernel driver cannot handle Baytrail legacy GPIOs, so make the
    default input GPIO type MMIO.
    
    BUG=chrome-os-partner:24408
    TEST=Manual on Rambi. Run "echo 169 > /sys/class/gpio/export; cat
    /sys/class/gpio/gpio169/value", verify GPIO value changes based upon mic
    jack status.
    BRANCH=None
    
    Change-Id: I27870ce8b7ecae9228e06e48c8759409c824c2eb
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179169
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4992
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 70cc9084a51e7f276b20d146fdab5fda6884febb
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Thu Dec 5 14:57:08 2013 -0800

    rambi: Change eMMC pin PUs to 2K
    
    Strengthen PUs on all eMMC pins to fix problems with eMMC not coming up
    on certain boards.
    
    BUG=chrome-os-partner:24353
    TEST=Manual. Burn FW on board that previously failed to boot eMMC,
    verify chromeos can now install + boot from eMMC.
    BRANCH=none
    
    Change-Id: I7a9742968b8b8c2c42285ffc21de46aed9c87fb7
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178917
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4991
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit fad3703ce80011ccc0eaef03fb0575f591085d5f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Dec 5 12:40:08 2013 -0600

    rambi: configure SD card signals
    
    Rambi 1.5 boards use the native SD card controller on baytrail.
    Therefore, enable those signals. The CLK, D*, and CMD pins use
    2K pulls as these were shown to not exhibit any errors when
    doing reads or writes to a DDR50 sd card.
    
    Note that if a servo is connected on needs to enable the
    sd_vref_sel rail to pp1800 as this causes issues with card
    detect if it is not set to pp1800.
    
    BUG=chrome-os-partner:24312
    BRANCH=None
    TEST=Built and booted. Tested sd card read and write works in kernel.
         Also noted that write protect detection works as well.
    
    Change-Id: I520e2808acbd8494534fcb710411dbc0e12fc874
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178961
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4990
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 4334c876346fe6c4ab977ed93a65eed765e7b9bb
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Dec 5 11:12:15 2013 -0600

    baytrail: enable lpe resources assigned to device
    
    The enable_resources callback was accidentally populated
    with NULL. Make that callback be the generic
    pci_dev_enable_resources.
    
    BUG=chrome-os-partner:23791
    BRANCH=None
    TEST=Built and booted.
    
    Change-Id: I670b51bd9aff6764e9b549287a737b662572cdc7
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178960
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4989
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit b50566ef63b560ed149db6aeb19004d7c0345275
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Dec 4 18:34:11 2013 -0800

    baytrail: Fix _CRS to build with new IASL
    
    The new IASL is complaining about the PCI memory region not
    having consistent base/end/length values because they are
    placeholder that are fixed up in the method before returning.
    
    Put in some more valid placeholder values to make it happy.
    
    BUG=chromium:311294
    BRANCH=none
    TEST=build and boot with IASL 20130117 on rambi
    
    Change-Id: I0e21adcce43deb14d3c2c45787ff8c9efc357c2f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178864
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4988
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit ac9a905cf1e44570a27dea0afd9233b7418d9c1e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Dec 4 11:29:46 2013 -0600

    rambi: configure the LPE audio codec clock
    
    Rambi has the LPE audio codec connected to PMC_PLT_CLK[0].
    Configure it for 25MHz.
    
    BUG=chrome-os-partner:23791
    BRANCH=None
    TEST=Built and booted. Noted message in console output.
    
    Change-Id: I11297ba951149e5831c65ca70ac7bdbbed113098
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178781
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4987
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 8cbf47f12cfbf4ef8130b3e91bc1b29044238af5
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Dec 4 11:03:20 2013 -0600

    baytrail: add lpe codec clock configuration
    
    Add device tree option to determine if the LPE
    audio codec has a platform clock signal connected
    to it from the SoC. If a frequency is selected the
    platform clock number is used to enable the
    clock.
    
    BUG=chrome-os-partner:23791
    BRANCH=None
    TEST=Built and booted rambi with 25MHz option. Probed pin
         to audio codec. Noted 25MHz clock.
    
    Change-Id: I67d0d034f30ae1c7ee8269c0aea43e8c92ff868c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178780
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4986
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit bb0d1ea24736b96789c10823b1a194818943cc3c
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Dec 3 10:00:20 2013 -0800

    baytrail: Add ACPI code to describe GPIO controller
    
    There are 3 banks of GPIOs that need to be described
    with specific _UID and memory/interrupt values.
    
    BUG=chrome-os-partner:24314
    BRANCH=none
    TEST=build and boot on rambi, check for probed driver:
    
    gpiochip_find_base: found new base at 154
    gpiochip_add: registered GPIOs 154 to 255 on device: INT33FC:00
    gpiochip_find_base: found new base at 126
    gpiochip_add: registered GPIOs 126 to 153 on device: INT33FC:01
    gpiochip_find_base: found new base at 82
    gpiochip_add: registered GPIOs 82 to 125 on device: INT33FC:02
    
      fed0c000-fed0cfff : INT33FC:00
        fed0c000-fed0cfff : INT33FC:00
      fed0d000-fed0dfff : INT33FC:01
        fed0d000-fed0dfff : INT33FC:01
      fed0e000-fed0efff : INT33FC:02
        fed0e000-fed0efff : INT33FC:02
    
    Change-Id: I9619e2af4e1ccdf3d7b2e4ae280aadf22e278aeb
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178601
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4985
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 22f1dcdfc4f7e990e65a72ff9f34d74754208df6
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Dec 2 10:14:47 2013 -0800

    baytrail: Update to microcode 31E and fix C-state table
    
    With microcode 31E MWAIT 0x51 is now C6NS and 0x52 is now C6FS.
    
    BUG=chrome-os-partner:23505
    BRANCH=none
    TEST=build and boot on rambi, check that C1/C2/C3 are all used now
    
    Change-Id: I8528d808f4082c85d90e2b57747d9f2e2d982b85
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178461
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4984
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 5b33dc1ec922ca0025472d87a51bf1b7844b03e6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 7 20:20:10 2014 +0200

    baytrail: minor style
    
    use IS_ENABLED() over #if brackets
    
    Change-Id: I101f99971c0f7b5311ef19cc9832713ab0696935
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5692
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 802a8ece3f089ec38c6e1d141f618fc58bbc0791
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 7 20:19:50 2014 +0200

    rambi: Remove outdated comment
    
    Change-Id: Ic555d23a9112677a784dd814601f8202d4d17261
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5691
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 100b14d12bbf62ebaf81436ef6fd8c2c551d45ff
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Nov 27 16:51:26 2013 -0600

    rambi: handle single channel configs
    
    Some 1.5 boards have a single channel ram configuration.
    Accomodate such configs.
    
    BUG=chrome-os-partner:22865
    BRANCH=None
    TEST=Built and booted ChromeOS.
    
    Change-Id: I513327e47b9211d2dd1ea960d7da671a3773cb91
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178340
    Reviewed-by: Nick Sanders <nsanders@chromium.org>
    Tested-by: Bernie Thompson <bhthompson@chromium.org>
    Tested-by: Nick Sanders <nsanders@chromium.org>
    Reviewed-on: http://review.coreboot.org/4983
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 13d934166069de8f61a84ed111683703bdc7c78e
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Tue Nov 26 15:37:43 2013 -0800

    baytrail: romstage: Add config option to enable RMT
    
    Add config option to enable RMT in the MRC.
    
    BUG=chrome-os-partner:21807
    TEST=Manual. Build w/ "USE=rmt", verify RMT print seen on FW console.
    Build w/o USE flag, verify no RMT print.
    BRANCH=None.
    CQ-DEPEND=CL:*148655
    
    Change-Id: Ibd3da87317a3359e797d9b43bc437e7227a85048
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/178095
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4982
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ae31f7dcc4eb173ca4677d3a580c736dc088c5e5
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Nov 22 14:16:49 2013 -0600

    baytrail: pcie: Root port initialization
    
    Add PCIe driver to initialize root ports.
    
    BUG=chrome-os-partner:24111
    TEST=Manual on Rambi. Verify that PCIe Wifi card is detected and able to
    detect networks.
    BRANCH=None.
    
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    
    Change-Id: I3c68da5f27cd162e112add488bdf5ced192b7d12
    Reviewed-on: https://chromium-review.googlesource.com/177652
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4981
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5f5cd72a5589d68cb95d09eec1717577e0b782d3
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Thu Nov 21 11:00:53 2013 -0800

    baytrail: gpio: Fix NCORE gpio-to-pad LUT
    
    NCORE pad addresses were wildly wrong due to documentation bugs.
    
    BUG=chrome-os-partner:24179
    TEST=Manual on Rambi. Verify display isn't always on. Verify brightness
    control now works in Chrome OS.
    BRANCH=None.
    
    Change-Id: I464436a58baa4957329c11231c5a866dafd97ce8
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/177597
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4980
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 21565cac1b0b34c3e76c1bcd2bf933ac1313ecac
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Nov 20 15:21:40 2013 -0600

    rambi: use SERIRQ pad as keyboard irq in gpio mode
    
    The level shifting between 3.3V and 1.8V for the SERIRQ
    signal is not working. Instead use the SERIRQ pad as
    a gpio which is used as a direct IRQ signal for the
    keyboard interupt.
    
    BUG=chrome-os-partner:23965
    BRANCH=None
    TEST=Built and booted rambi. Keyboard works with associated EC change.
    CQ-DEPEND=CL:177189
    
    Change-Id: Ifc270ca38207828a6d4711551d4bde9121559cca
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/177223
    Tested-by: Bernie Thompson <bhthompson@chromium.org>
    Reviewed-on: http://review.coreboot.org/4979
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit baa1e382178ab6a45c5d584a88ac26c0767f8a12
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Nov 18 13:50:02 2013 -0600

    rambi: make ramids non-legacy gpio inputs
    
    The romstage code for rambi uses the mmio way of reading
    inputs. However, this is a problem is the GPIOs are set up
    as legacy mode. Subsequent warm resets mean the ram_id is
    read incorrectly. Ensure the ram_id is read consistently
    by keeping the GPIOs for ram_id in mmio mode.
    
    BUG=chrome-os-partner:24085
    BRANCH=None
    TEST=Built and booted. And rebooted. Now seeing consistent ram_id
         values on warm resets.
    
    Change-Id: Ieff98c000be80998854f325754f1e819975d2be5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/177230
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4977
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6f9947a3ec2cf481dbb233660a29f757a8707cf8
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Nov 18 11:16:20 2013 -0600

    baytrail: enable caching and prefetching in spi controller
    
    The default mode of the SPI controller has prefetching disabled.
    That obviously has a performance impact. Enable both caching
    and prefetching to make booting faster. This has a significant
    impact on streaming data out of SPI.
    
    BUG=chrome-os-partner:24085
    BRANCH=None
    TEST=Built and booted rambi. Payload loading step went from ~285ms
         to ~54ms.
    
    Change-Id: I065cf44e1de7dcefc49aa9ea9ad0204929ab26f4
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/177220
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4976
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bd4ea8cd4d34cdca6aef2914cf880a20bf3025fe
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 14 17:39:04 2013 -0600

    baytrail: fix direct irq pad configuration
    
    When a pad is configured for direct IRQ it needs to be in
    non-legacy. Additionally, the signal is passed directly to
    the APIC by setting the LEVEL and TPE bits in the pad config
    register. The APIC can then be configured for level, edge,
    and rising/falling.
    
    BUG=chrome-os-partner:24037
    BUG=chrome-os-partner:22863
    BRANCH=None
    TEST=Built and booted with this config. Trackpad is firing interrupts
         more than it should, but it appears to be a trackpad firmware
         and/or configuration issue.
    
    Change-Id: I00042b2ddba67d6bf23f0e7468d0719196e6f865
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176793
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4975
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ebf7ec5dab9198a0a84174e72b8eaf1af68d7b73
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 14 13:47:08 2013 -0600

    baytrail: ensure init_chromeos() is called in romstage
    
    The TPM needs to have the TPM_Startup command sent to it
    on all boot paths. The call init_chromeos() in romstage_common()
    fulfills this requirement.
    
    BUG=chrome-os-partner:24057
    BRANCH=None
    TEST=Built and booted. Was able to suspend to ram multiple times
         in a row.
    
    Change-Id: Id0339a9d82897249d20ff5f62d2dcb8b535310fa
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176803
    Reviewed-by: Todd Broch <tbroch@chromium.org>
    Tested-by: Todd Broch <tbroch@chromium.org>
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4974
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ee3ec728d86c83fbbaaa84bb72137dca7cd511a2
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 14 11:15:43 2013 -0600

    rambi: distribute IRQs away from PIRQA on pci devices
    
    Some of the drivers in the kernel were not so happy about
    having shared IRQs. Also, sharing IRQs means more code
    needs to be run in interrupt context to determine if the IRQ
    was meant for a particular device. Fix this.
    
    No more 'mmc1: got irq while runtime suspended' messages.
    
    BUG=chrome-os-partner:24056
    BRANCH=None
    TEST=Built and booted. Looked at /proc/interrupts and noted no
         more sharing between pci devices.
    
    Change-Id: Ie5da102204ffe3156dd55ab17af77df245a57c97
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176792
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4973
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bf9f24385739d29dd5ccea82dec06e1cdd2c10fe
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue May 6 17:24:59 2014 +1000

    superio/common/conf_mode: Provide another common pnp entry/exit
    
    ITE Super I/O's make use of this method to enter and exit in and out of
    their PNP configuration. Provide functions for use in ram stage
    component.
    
    Change-Id: I2b546c2b17eefc89aaab4982192f5e9a15a16c2f
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5666
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit d520840d4ca7d8fbd9c64946ee5f2d7ea44b8557
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Apr 11 20:24:06 2014 +0200

    kconfig: update to follow upstream more closely
    
    This might break a bunch of stuff (eg. win32 support),
    but otherwise introduces nconfig (ncurses based configuration
    frontend), partial configuration headers for improved dependency
    tracking (which requires some more build system support) and
    various bug fixes.
    
    Change-Id: I5d8a280810c6a26fc3fd056d5d94cb9e591a0ff5
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5487
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 99d8818af332f4db8ded058c7e5e59e2f56f7bc9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 14 11:06:17 2013 -0600

    baytrail: don't allow PCIE wake ups
    
    The PCIe subsystem was constantly waking up boards from
    S3 and S5. Completely disable PCIe wake ups. It can be made
    mainboard-configurable later if needed.
    
    BUG=chrome-os-partner:24004
    BRANCH=None
    TEST=Both S3 and EC RW->RW update (trip through S5) don't
         cause wakeups.
    
    Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176791
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4972
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 281abfb2dbf138bd732404f4412d8c6bee611bee
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Wed Nov 13 15:37:11 2013 -0800

    baytrail: gpio: Make pad input/output state mutually exclusive
    
    Previously pads were being configured as both input and output
    simultaneously due to the config bits being active low. Create new
    defines that only enable either input or output, and use them in our
    GPIO configs.
    
    BUG=chrome-os-partner:22863
    TEST=Manual on Rambi. Verify system boots and peripherals still
    function.
    BRANCH=None.
    
    Change-Id: If386682a3d810864b7b9f5d2aecdb2e6cfceea86
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176725
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4971
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit afaaa3a618ea677f20c9db75d09e311db0197906
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Nov 13 14:31:16 2013 -0600

    rambi: fixup settings so trackpad can be found in kernel
    
    The kernel chromeos_laptop driver nomenclature expects the
    board name to not be in all caps. Fix this as well as the i2c
    address for the trackpad.
    
    BUG=chrome-os-partner:24307
    BRANCH=None
    TEST=Built and booted. trackpad device is found. IRQs still not
         working yet.
    
    Change-Id: Id6be8ee4bce2835e303ea4fe63944be80d2d7ec2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176680
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4970
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit dc866cff31e26de7cf95bbd0675037d8066f7dc8
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Nov 12 20:21:53 2013 -0600

    baytrail: first pass at lpss device initialization
    
    This commit does the common parts for all LPSS devices
    that are enabled: enable snoop in IOSF and enable power
    management. Additionally, the i2c devices are taken out of
    reset.
    
    BUG=chrome-os-partner:23790
    BRANCH=None
    TEST=Built and booted with modified kernel-next. I2C bus devices
         show up and I see 0x10 on one of the buses.
    
    Change-Id: I540caea6a8666f5684dc5cee683a6b085dfac6de
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176424
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4969
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 64b902b57a035c31043cb0c6690e221a25287ff3
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Nov 12 20:20:10 2013 -0600

    reg_script: add iosf lpss port access
    
    Add the LPSS IOSF port access to reg_script. This is
    going to be used by baytrail.
    
    BUG=chrome-os-partner:23790
    BRANCH=None
    TEST=Buit.
    
    Change-Id: I0367acdb584f2de0bb871b136042b57fe6b7ec90
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176423
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4968
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 159216949597cb68a477af1b3723705f5e87cbb1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Nov 12 16:44:18 2013 -0600

    baytrail: initialize eMMC device
    
    The eMMC device is initialized as version 4.5 with HS200 speeds.
    
    BUG=chrome-os-partner:23966
    BRANCH=None
    TEST=Built and booted rambi to login screen off of eMMC device.
    
    Change-Id: I686c6136005fcb2587b939ddea293f4398df9868
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176536
    Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4967
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c626b74c1d5e1faaa6a23e3d658b0e097e6404f9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Nov 12 16:40:33 2013 -0600

    baytrail: initialize common SSC functionality
    
    The SSC (storage control cluster) houses the SD, SDIO, and eMMC
    interfaces. The scc cofniguration function, baytrail_init_scc(),
    is ran in the pre device stage to initialize the SCC. The eMMC
    is expected to be configured for version 4.5.
    
    BUG=chrome-os-partner:23966
    BRANCH=None
    TEST=Built and booted with some other eMMC changes into login screen off
         of eMMC device.
    
    Change-Id: I81cc755a790b7e43ad234a8201dae480277202c8
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176535
    Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4966
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e8f97d4f55816a298e672375ad39c37158acd61a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Nov 12 16:38:54 2013 -0600

    reg_script: add iosf paths for score, ccu, and ssc
    
    Handle SCORE, CCU, and SSC IOSF accesses.
    
    BUG=chrome-os-partner:23966
    BRANCH=None
    TEST=Built.
    
    Change-Id: I6e678eb79bd1451f156bdd14cf46d3378dc527c9
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176534
    Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4965
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d7f0f3de10bb2aa4e41c8d87b364feaab7c1f704
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Nov 12 16:37:05 2013 -0600

    baytrail: add score and ssc iosf access functions
    
    The SCORE allows controlling the pad configuration while
    the SSC handles the configuration for the storage control
    cluster.
    
    BUG=chrome-os-partner:23966
    BRANCH=None
    TEST=Built.
    
    Change-Id: Ifd9f67a4e88d5bb99faec6ceeb3e263001a87c41
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176533
    Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4964
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9547f8d799829ddab9196c4e0cad644a06db49e9
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Fri Nov 8 17:23:26 2013 -0800

    rambi: Add DIRQs for trackpad and touchscreen
    
    Also add the relevant info about these pins to the ASL tables + add
    SMBIOS type 41 data for these parts.
    
    BUG=chrome-os-partner:22863
    TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ
    regwrites w/ GPIO_DEBUG look correct.
    
    Change-Id: Id40655f9fb2ea7b10e1ff58d0b2a8b4cc6f05ff8
    Reviewed-on: https://chromium-review.googlesource.com/176299
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4963
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 99ac98f7e1fa30d3fb33cc5486e6af46b4bef56e
Author: Furquan Shaikh <furquan@google.com>
Date:   Wed Apr 23 10:18:48 2014 -0700

    Introduce stage-specific architecture for coreboot
    
    Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
    architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
    each of the three stages. This allows us to have an SOC with any combination of
    architectures and thus every stage can be made to run on a completely different
    architecture independent of others. Thus, bootblock can have an x86 arch whereas
    romstage and ramstage can have arm32 and arm64 arch respectively. These stage
    specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
    and compiler flags for every stage.
    
    These options can be considered as either arch or modes eg: x86 running in
    different modes or ARM having different arch types (v4, v7, v8). We have got rid
    of the original CONFIG_ARCH option completely as every stage can have any
    architecture of its own. Thus, almost all the components of coreboot are
    identified as being part of one of the three stages (bootblock, romstage or
    ramstage). The components which cannot be classified as such e.g. smm, rmodules
    can have their own compiler toolset which is for now set to *_i386. Hence, all
    special classes are treated in a similar way and the compiler toolset is defined
    using create_class_compiler defined in Makefile.
    
    In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
    and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
    Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
    toolsets are defined using create_class_compiler.
    
    Few additional macros have been introduced to identify the class to be used at
    various points, e.g.: CC_$(class) derives the $(class) part from the name of
    the stage being compiled.
    
    We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
    as they do not make any sense for coreboot as a whole. All these attributes are
    associated with each of the stages.
    
    Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: http://review.coreboot.org/5577
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit fb494d68ff92d036adf10fb7eacf97ed9f1a4391
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Fri Nov 8 16:43:34 2013 -0800

    baytrail: gpio: Add support for direct / dedicated IRQs
    
    Add support for DirectIRQ / dedicated IRQs. This consists of up to 16
    IRQs for both SCORE and SSUS banks.
    
    BUG=chrome-os-partner:22863
    TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ
    regwrites w/ GPIO_DEBUG look correct.
    
    Change-Id: I4b0dc6e7ae86c9f554b6e78792239234f702764c
    Reviewed-on: https://chromium-review.googlesource.com/176165
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4962
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 7e9634ffc0d48e471cb4c2ff521c6f4361207303
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Nov 11 15:01:39 2013 -0600

    rambi: disable HDA device
    
    For some reason HDA can now be disabled. It's unclear what changes
    in the baytrail code allowed this to happen, sadly.
    
    BUG=chrome-os-partner:22871
    BRANCH=None
    TEST=Noted hda is not in lspci.
    
    Change-Id: I64e2560533be6f701fa66cd53c906b62b09012ed
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176394
    Reviewed-on: http://review.coreboot.org/4961
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 59cd6216dd430db7488448b0c68aa7024690e179
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Nov 11 14:58:06 2013 -0600

    rambi: enable SCI and SMI gpios
    
    Rambi has 3 pins that need to be configured for SCI and SMI:
    
    1. GPIO_CORE[0] - runtime SCI pin
    2. GPIO_SUS[7] - SMI for firmware lid events
    3. GPIO_SUS[0] - wake pin for S3 wakes from EC.
    
    Configure these pins now that the rest of the infrastructure
    is in place. The one thing that is yet to work is runtime SCI
    for lid events once booted.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=built and booted. lid close at rec screen works. And wake
         from S3 with a keyboard press works.
    
    Change-Id: I5f8e38ec5f4cf1a8ef7aa7fcee9abc344d9b184f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176393
    Reviewed-on: http://review.coreboot.org/4960
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 3fbf671194a8f1469bf0e122fed8e8da23893ac9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Nov 11 14:55:47 2013 -0600

    rambi: mainboard EC - SCI and SMI fixes
    
    As rambi is a baytrail board it doesn't have a dedicated wake pin.
    Therefore, one needs to enable the proper GPIO to wake up the sytem
    before going into S3.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Put system into S3. Keyboard press created wake event. Also, typed
         'lidclose' on EC console while at recovery screen. Machine properly
         shutdown.
    
    Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176392
    Reviewed-on: http://review.coreboot.org/4959
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 9f83e873f4f0a06a68f68414720e837a69f54184
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Nov 11 14:45:27 2013 -0600

    baytrail: add GPIO SMI support
    
    GPIOs which trigger SMIs only set the status bits in the ALT_GPIO_SMI
    regier. No bits in the SMI_STS register are set. Therefore, the
    ALT_GPIO_SMI register needs to be read and cleared on every SMI.
    Additionally, the mainboard_gpi_smi() handler needs to be called as
    well on every SMI because of this property.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Built and booted to recovery screen. Typed 'lidclose' on EC
         console. SMI occurred which caused the board to be shutdown.
    
    Change-Id: Ic204d8b928a0cb4f51f108a649f374d9f94e4f47
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176391
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4958
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 59a4cd55782f1148d37f0c2408657ba93deefc86
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Nov 11 12:09:28 2013 -0600

    baytrail: add support for routing gpio pins to smi/sci
    
    In order for gpio pins to trigger an smi/sci the GPIO_ROUT
    register needs to be set accordingly. For SMI, the ALT_GPIO_SMI
    register needs to be enabled for each gpio as well.
    
    The first 8 gpios from the suspend and core well are the only gpios
    that can trigger an SMI or SCI. The settings for the GPIO_ROUT
    and ALT_GPIO_SMI register are not commited until the SMM settings
    are enabled in the southcluster.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Built and booted. Manually triggered SCI by changing GPE0a_EN
         and toggling PCH_WAKE_L on the EC console.
    
    Change-Id: Id79b70084edc39fc047475e984494c224bd75d6d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176390
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4957
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 997d25219b67704ba497a3d67f392a8a743a1782
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Nov 8 17:37:48 2013 -0600

    baytrail: fix fadt structure for gpe0 block
    
    The gpe0 block's size was being misreported. Correct
    the gpe0 size and use make the FADT fields be more
    robust instead instead of hand calculating fields that
    are the based on the same size.
    
    This change correctly enables GPE events in the kernel.
    Confirmed this by using iotools read the gpe_cnt register.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Built and booted. Confirmed EC's GPE event is enabled (but
         still not working).
    
    Change-Id: I415710f7fec2e95cecee3bf679ee673dacc27480
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176271
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4956
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ea7d4e0901e8ebfb2fe520ba3814c41138aaeb26
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Nov 8 23:02:20 2013 -0800

    baytrail: Add microcode/punit release 31a
    
    BUG=chrome-os-partner:23505
    BRANCH=none
    TEST=build and boot on rambi
    
    Change-Id: I89c25142245cd268f755210784fd9d0c60dc5661
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176305
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4955
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 8923be58b87cbf55f5765eca6ce29d7b6827be97
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Nov 5 13:02:30 2013 -0800

    baytrail: Add ACPI CPU entries
    
    - C-state table based on static config
    MWAIT values are from ref code for non-S0ix config
    C6 substate 8 is ignored by the kernel as it violates the CPUID
    but it is left in as the other substate may not work.
    - P-state table generated with proper ratio and VID values
    relies on having the package power msr set to magic value
    as the power-on default is wrong
    - T-state table uses static table
    
    BUG=chrome-os-partner:23505
    BRANCH=rambi
    TEST=build and boot on rambi
    
    Change-Id: I7c997e58cb3a71d0ec413b17f0c5467bef4bf62c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175742
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4954
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 6aa9f1f0eb97e315ab4db8e6da1d13db7ee7858f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Nov 7 12:47:35 2013 -0800

    baytrail: Add BCLK and IACORE to pattrs
    
    The bus clock speed is needed when building ACPI P-state tables
    so extract that function and have the value be saved in pattrs.
    
    The various IACORE values are also needed, but rather than have
    the ACPI code to the bit manipulation have the pattrs store an
    array of the possible values for it to use directly.
    
    BUG=chrome-os-partner:23505
    BRANCH=none
    TEST=build and boot on rambi
    
    Change-Id: I5ac06ccf66e9109186dd01342dbb6ccdd334ca69
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176140
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4953
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 05a3393a2c089d0c7ad7443e2298dacd129fadb3
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Nov 5 12:59:50 2013 -0800

    baytrail: Enable Turbo/Burst and set some magic MSRs
    
    As far as I can tell turbo enabling behaves like
    it did on haswell so use the standard code.
    
    There are also some magic values to set in some magic
    MSRs related to turbo and package power so they report
    correctly.
    
    The L2 cache shrink is enabled and a threshold is set
    that makes both dual and quad core happy.
    
    C1E is disabled to match the reference code.
    
    BUG=chrome-os-partner:23505
    BRANCH=rambi
    TEST=build and boot on rambi
    
    Change-Id: Ic6d4283d480a44d85a9b96571baf83928615665c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175743
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4952
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit fd461e396b482cd5d0cd81cb11c4973f4ebfa94c
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Nov 8 23:00:24 2013 -0800

    regscript: Add support for MSR type
    
    This required changing value/mask types to uint64_t.
    
    Another option would be to use id field to select low or high
    32 bits of the MSR and set them independently.
    
    BUG=chrome-os-partner:23505
    BRANCH=none
    TEST=build and boot on rambi
    
    Change-Id: Ied9998058a8035bf3f003185236f3be3e0df7fc9
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176304
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4951
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 9e68fe68ff272619ead17d8497fc6050e28caac6
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 7 08:13:58 2013 -0600

    rambi: include the EC devices normally on superio
    
    The superio.asl file allows for the mainboard to hang
    devices off of the LPC bus in ACPI. Include the keyboard
    controller, EC memory map, and host interface's resources.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Built and booted. Noted resource reservations in dmesg.
    
    Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176134
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4950
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ab7ed054bee3ede51c06053adf53d455fda6065a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 7 14:33:21 2013 -0600

    baytrail: include mainboard's superio.asl
    
    The mainboard needs an opportunity to hang devices off of
    the LPC device. Therefore, provide this opportunity for the
    mainboard.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Buit and booted with keyboard. Keys work.
    
    Change-Id: Ie2b660ad43e86d9237b0b0bb0720b069670bc537
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176133
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4949
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 84da959c691a1efa87ff47edd03d5427eaf6e093
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 7 11:19:34 2013 -0600

    rambi: update EC support
    
    Fix the SMI and SCI gpios for Rambi. Also, add in the
    EC callbacks for the SMI handler. Note that the handler
    for GPI SMIs has not been tested yet as baytrail chipset
    code  doesn't yet support setting up those configurations
    yet.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Noted that SCI was enabled in /sys/firmware/acpi/interrupts
         for the EC's SCI GPI. Also was able to see Chrome EC messages
         with CONFIG_DEBUG_SMI and powering down at the dev screen.
    
    Change-Id: I67b278fd38e1c09271d2c1e16e42f6e8c49e3a70
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176077
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4948
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit fa91e02a15ff45f70886b969a9587468afec10ac
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 7 10:47:01 2013 -0600

    baytrail: add more irq defintions
    
    The IRQs used for devices that are in acpi mode are added as well
    as the IRQ defitions for the dedicated GPIO IRQ routing.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Built.
    
    Change-Id: I2eed5a4584e2d908c32617c9289a2abeaa30bd44
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176120
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4947
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 1af366322e0330960d746e2875d61e202c8dd807
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 7 10:42:16 2013 -0600

    baytrail: configure acpi SCI irq
    
    Baytrail has a configurable SCI irq. Add support for
    properly configuring SCI irq. Note that it is currently
    fixed to IRQ9, but the code supports setting it to the
    other supported values. The current mainboards using
    baytrail defer the madt IRQ override information to the
    chipset.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Built and booted. Noted 'SCI is IRQ9' message.
    
    Change-Id: I7b307bd58f9de944f0cb4c116107a15345499f2e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176075
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4946
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 952d85e5f2d951850551572b756a6518c734e069
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 7 08:15:07 2013 -0600

    rambi: mirror bayleybay's eMMC gpio setup
    
    These changes to the eMMC pads allows the kernel to see the
    eMMC device. One is able to install onto the eMMC device, and
    the kernel is loaded and booted from eMMC device. Note, that
    it may not fully boot because of other issues such as
    not-completely working ACPI support.
    
    BUG=chrome-os-partner:22580
    BRANCH=None
    TEST=booted off of usb drive. can see eMMC device.
    
    Change-Id: I9c088398297a0b559383bdf4a389dd19a1110e0f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/176073
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4945
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 8de0ca435e7cee39cd5b7523aea4c7c59d1113d8
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Nov 6 10:58:46 2013 -0800

    rambi: Fix eDP panel functionality
    
    For some mysterious reason GPIO_S0_NC22 is making the eDP panel
    go entirely white when it is configured with internal pullup.
    Since these (supposedly XDP related) pins are unknown functionality
    lets set them to GPIO_DEFAULT instead of GPIO_NC.
    
    Additionally the VBIOS is being changed to issue int15 callback
    to determine the boot graphics device.  If we list both LFP and EFP
    then the dev/rec screens will show on the panel when HDMI is not
    attached and otherwise will display on HDMI.
    
    BUG=chrome-os-partner:23507
    BRANCH=rambi
    TEST=build and boot on rambi, see firmware/kernel screens on the panel
    when HDMI is not attached, and firmware screens on the panel and
    kernel screens on both when HDMI is attached.
    
    Change-Id: Ieb05a591d63c4f8e09fa154eeb76004d32579508
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175952
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4944
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 6e3289372c598e3e0702f44e52c04d689172b156
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Nov 6 12:04:50 2013 -0600

    baytrail: add support for S3 resume
    
    Previously the only path through memory init and coreboot was
    hardcoding S5. Therefore all S3 paths would not be taken. Allow
    for S3 resume to work by enabling the proper control paths in
    romstage.
    
    BUG=chrome-os-partner:22867
    BRANCH=None
    TEST=While in kernel 'echo mem > /sys/power/state'. Board went
         into S3. Power button press resumed back into kernel.
    
    Change-Id: I3cbae73223f0d71c74eb3d6b7c25d1b32318ab3e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175940
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4943
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 2237324e77a5e8ed30878609095c1592081f15e4
Author: Trevor Mosey <uberushaximus@gmail.com>
Date:   Fri May 2 20:07:03 2014 -0500

    lenovo/t60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String
    
    linux/drivers/platform/x86/thinkpad_acpi.c looks for an EC
    version string before loading, this code copies the vendor BIOS by
    exposing this string. This was originally part of x60's mainboard.c
    
    Change-Id: I5e54ea2833252bc4dbba46ceb67d78c435b34845
    Signed-off-by: Trevor Mosey <uberushaximus@gmail.com>
    Reviewed-on: http://review.coreboot.org/5638
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 69634c316ed1056e734a129e7c28580c2772c074
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue May 6 12:45:25 2014 +0200

    northbridge/intel/sandybridge/pei_data.h: Fix typo in hig*h*est in comment
    
    Change-Id: I0daf5d1d446de1f09b695f177b0491301613e278
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5667
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 303525b446469157ede480ca61aa6c14bb774eb9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Nov 5 11:42:32 2013 -0600

    baytrail: fix up FADT
    
    The FADT for baytrail had incorrect offsets leading to
    the kernel spewing a huge mess of ACPI errors. Fix these offsets
    to be initialized in the chipset code.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Built and booted into kernel on rambi. Login screen comes up.
    
    Change-Id: I89fc2a4fd800ff01cedf89b51cfb1369aceb9f03
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175663
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4941
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3bde3d74c5574d7855d1845130bdd357bd2cb7e4
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Nov 4 21:45:52 2013 -0600

    baytrail: interrupt routing support
    
    This provides the initial support for interrupt routing
    in bay trail. It includes both acpi changes and board changes
    to ensure the interdependencies are met with the current ASL
    code. The PIRQ routing is handled by the mainboard exporting
    an irqroute.h header that describes the per device and PIRQ
    PCI settings.
    
    There are still a lot of ACPI errors in the kernel with this
    change, though.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Built and booted rambi into kernel.
    
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e
    Reviewed-on: https://chromium-review.googlesource.com/175700
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4940
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 014baea1ceda67aa5df8bb4fbf20782893915f81
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 28 22:01:05 2014 -0500

    haswell: move to mp_init library
    
    The mp_init library was based off of haswell code, but baytrail
    was the first chipset to take advantage of it. Move haswell over
    to using it so that the code duplication can be removed.
    
    Change-Id: Id6e9464df028aa6ec138051f925817c85b4c13e5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5413
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 60ec2ff2f005cc3d361225ad24327dff14c7abf2
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat May 3 16:21:34 2014 +0200

    lib/hexdump: Use `size_t` for length parameter of `hexdump32()`
    
    In the signature of the function `hexdump32()` it does not make sense to
    represent a length, assumed to be positive, as a signed integer.
    With this change, it is no longer necessary to cast a pointer to
    unsigned long when passing it to `hexdump32()`.
    
    The same change for the function `hexdump()` was done in commit
    3dd0e72d [1].
    
    	lib/hexdump: Take const void * and size_t as arguments
    
    [1] http://review.coreboot.org/4575
    
    Change-Id: Id97f5daff95f94e862ee8b5be896a6629b125a13
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5646
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f0a59914d884ff74e392fe17c1edbe93557c0efa
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Dec 27 14:43:44 2013 +0100

    lib/hexdump.c: Indent with tabs instead of spaces and remove empty lines
    
    The coding style requires to use tabs for indentation and not spaces.
    Use GNU indent 2.2.11 with the switch `-linux` to indent the file,
    which also removes the empty lines at the end of the file.
    
    Change-Id: I874f178e50d7558d3299026aec2771ad45f88d8e
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/4576
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 08df7326e6bd39d14d32091fb773f701faf77bc3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 14:53:36 2014 +0300

    AGESA: Fix BiosCallouts table formatting
    
    Already done for fam15tn and fam16kb.
    
    Change-Id: I3da36bfe6fd1805867eee5aa1f017c4fda084349
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5660
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 088fd67a38c7030ef0e6434472d64a3607c29100
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri May 2 14:13:37 2014 +0300

    AGESA: Implement EmptyHeap()
    
    Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear
    the fields individually.
    
    Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5659
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8ef30253e3f117275306a1f977fd42e0470f4f5a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 07:24:43 2014 +0300

    AGESA fam14: Use common callouts
    
    Backported from fam15tn and fam16kb.
    
    This also implements GetHeapBase() to satisfy some requirements
    of HAVE_ACPI_RESUME for the following boards:
      amd/inagua
      amd/south_station
      amd/union_station
      asrock/e350m1
    
    Change-Id: I488d063d4eabf4bf45bcbabd1e8f13b88b2ef401
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5658
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5601922130485ee7af96189e843114f58a58b4fd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 07:22:20 2014 +0300

    AGESA fam14: Add fam14_callouts header
    
    Backported from fam15tn and fam16kb.
    
    Change-Id: I868352b32ff56a8386c615ab1a9f59e7e875292e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5657
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6711dce55275755d41920001890029c684145cb1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 08:53:51 2014 +0300

    jetway/nf81-t56n-lf: Revert change on function prototypes
    
    These function prototypes to remain identical across all
    AGESA families.
    
    Change-Id: If2a0a08fa7122e6becded37d032d3c40bde2d149
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5656
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f15e53a730940cbeaf8bf48a2bd12292ac49dc22
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri May 2 09:40:04 2014 +0300

    AGESA fam15: Add GetHeapBase()
    
    While fam15 boards do not select HAVE_ACPI_RESUME, backport this
    from fam14.
    
    Implementation of this function is common across different families.
    
    Change-Id: I222b418a0a79bbdf5f5cce6c876243ecb4912256
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5655
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4f998a07b51340dde499701fbff739f7df373059
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri May 2 09:40:04 2014 +0300

    AGESA fam12: Add GetHeapBase()
    
    While amd/torpedo does not select HAVE_ACPI_RESUME, backport this
    from fam14.
    
    Implementation of this function is common across different families.
    
    Change-Id: I0e5099a0991a2655ec2b6990929196900e842fc1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5654
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e3aef13933c36f8a12687d554e952d360fde0bdb
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri May 2 09:40:04 2014 +0300

    AGESA fam15tn: Use common GetHeapBase()
    
    Implementation of this function is common for all boards in family,
    and also across different families.
    
    Change-Id: I562a132fa6d3ade2700d9a375d7aa21fcf8ea890
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5653
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5caa9d9d81f0bcc90917d60b90f37f060dad48d3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri May 2 09:40:04 2014 +0300

    AGESA fam16kb: Use common GetHeapBase()
    
    Implementation of this function is common for all boards in family,
    and also across different families.
    
    Change-Id: I6aab710e76af9a361f0c0006922019a52feb3f6f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5652
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 575cf9df66e30cf00f9c58e263d83db5b3ca5dec
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 07:24:43 2014 +0300

    AGESA fam15: Use common callouts
    
    Backport from fam15tn and fam16kb.
    
    Change-Id: I6d8f9a88f0dc43c36efb168c0111a6e2bcdda5fd
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5651
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 05531a5f447a2b13ee35e8997251aa7f1fbaad07
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 07:21:25 2014 +0300

    AGESA fam15: Add fam15_callouts header
    
    Backported from fam15tn and fam16kb.
    
    Change-Id: I13ca70d141a46220a5d8ea7bb3898bc7d7258424
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5650
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5c96525b6a0161864fffc50f5d9e9ebc6a6dfa07
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri May 2 13:18:57 2014 +0300

    AGESA fam12: Move dimmSpd
    
    Implemented under northbridge/ on other families.
    
    Change-Id: I4d21af9d6c0f61eb1597e8e7095c08dd87ae2a84
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5649
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 328ce9a8b4ebeff40e3df38fca379343a3a0e8c3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun May 4 07:20:33 2014 +0300

    AGESA fam12: Add fam12_callouts
    
    Although amd/torpedo is only fam12 board at the moment,
    backported this from fam15tn and fam16kb.
    
    Change-Id: I72a856e2eb455a8428a886f0c4217ff80e60eb78
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5648
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 028dc1e1519d1043e114554918224389dda679d1
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu May 1 22:41:12 2014 +1000

    AMD F14h boards: Sanitise headers in agesawrapper.c
    
    Change-Id: Ic9c5e8abb3da020a642635ee74c9242091923619
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5628
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 8864e1c1499c019615411fa9a93cba840bc81549
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Apr 30 23:13:08 2014 +1000

    AMD F14h boards: Use std memset/memcpy func over AGESA
    
    In amd/{persimmon,inagua} and derived boards avoid using AGESA
    reimplementation of memcpy as following the reasoning in:
    e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
    
    Change-Id: I943b46103c3bf1c5fd88b25e9f9595b9adfcafeb
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5625
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 8e5435a74bfffb92bc2293e199d28e55494485d8
Author: Trevor Mosey <uberushaximus@gmail.com>
Date:   Fri May 2 16:11:50 2014 -0500

    lenovo/t60: Move mainboard_enable() code into a mainboard_init()
    
    mainboard_enable() is now modelled after google/parrot where the
    enable function only sets dev->ops->init for the root device to
    point to a mainboard_init() function, which in turn is called in a
    later pass over the device tree to do the actual initialization.
    
    Change-Id: I89a5192bd45ca8321b2b1ac49b073122e0f6ee2b
    Signed-off-by: Trevor Mosey <uberushaximus@gmail.com>
    Reviewed-on: http://review.coreboot.org/5637
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ae16d3dfbd2eb5bfd0cbaa8b63c16e35ee39261d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 30 01:37:58 2014 +0300

    AMD: Drop redundant test for CONFIG_RAMTOP
    
    Same test is already done in x86/mtrr.h.
    
    Change-Id: Ib0785d047567374294b9ee7afc4f4244f9ced926
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5620
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f771e569d72d6b7166ca0d92afaaf2e635a9ba1c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 3 09:12:55 2014 +0200

    Drop useless mainboard-romstage defines
    
    Some src/mainboard/*/*/romstage.c files use defines which later
    modify the behaviour of included .c files.
    Since it's a pain to work out what is affected by these, drop
    values that are only defined in the board but never used, or
    defined to identical values as in spd.h (and use that one instead).
    
    Change-Id: I8143b26fddc32a40ac4e611a6287bf7f144267dc
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5639
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit c38f3ae0dee4c413fc931bd1c294faeada807665
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Apr 26 15:29:10 2014 +0200

    build: allow building crossgcc when .config exists
    
    Under some circumstances the coreboot toolchain test prevented
    building crossgcc, which is counter-productive: If a .config file
    exists but no suitable .xcompile.
    
    Don't assume anything about the tree when building crossgcc or
    crosstools targets.
    
    Change-Id: I4d6e7a88908dc967342daf30df0fcbcc269ae63d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5584
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 88ca81a6d41f8f0b3491ce9f4b1ac553ed093ddf
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Apr 22 16:33:22 2014 -0700

    Move redundant Makefile rules from arch to top level.
    
    Remove all the common Makefile rules like coreboot.pre, coreboot.pre1 and others
    from arch level Makefile.inc to top level Makefile.inc.
    Also, organize Makefile.inc at arch level into per-stage rules and variables.
    
    Change-Id: I7dc5b2d31c959b55bb92d9c7811427c4dada1db5
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: http://review.coreboot.org/5571
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit fd33781fbf709c714b9287d69dbb63a09fad097e
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Apr 22 15:16:54 2014 -0700

    Move ARCH_* from board/Kconfig to cpu or soc Kconfig.
    
    CONFIG_ARCH is a property of the cpu or soc rather than a property of the
    board. Hence, move ARCH_* from every single board to respective cpu or soc
    Kconfigs. Also update abuild to ignore ARCH_ from mainboards.
    
    Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: http://review.coreboot.org/5570
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 2d9725e763c480f23a9e649df1424b1dc2fb3cfd
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Apr 26 10:28:19 2014 +0200

    drivers/pc80/Kconfig: Do not init PS/2 keyboard if GRUB 2 is chosen as payload
    
    If the user selects GRUB 2 as the payload in Kconfig, coreboot does
    not need to initialize the PS/2 keyboard as GRUB 2 is going to do it.
    
    Change-Id: Ia5d902e7c0fa34eaff26a31507751815bf2d2581
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5583
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4fdc680efc90e825cae83dccc99c9de1e5517215
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Apr 26 10:18:12 2014 +0200

    drivers/pc80/Kconfig: Do not init PS/2 keyboard if SeaBIOS is chosen as payload
    
    As the Kconfig description of `DRIVERS_PS2_KEYBOARD` says, SeaBIOS is
    able to initialize the PS/2 keyboard itself, so it is not necessary to
    let coreboot do it.
    
    SeaBIOS is also able to do it faster as discussed in a thread on the
    coreboot mailing list from October 2010 [1]. In that thread it was
    also proposed to not let coreboot initialize the PS/2 coreboot when
    SeaBIOS is used as a payload.
    
    [1] http://www.coreboot.org/pipermail/coreboot/2010-October/thread.html#61310
        subject: [coreboot] coreboot+seabios timings
    
    Change-Id: I1248cec3e2ca5b9311e46df8aabf67e14ffd4ea6
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5581
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7ac7627546d8d89d63abe06b7a0df1861f10eabf
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Apr 26 10:22:43 2014 +0200

    drivers/pc80/Kconfig: Mention that GRUB 2 is able to init PS/2 keyboard
    
    Change-Id: I0783ee123e0e1ecd5603bc6a40b53d3b0c23bf6d
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5582
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e93776579dcbbdc8f8a833590f21f9f33285d50b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 30 23:07:13 2014 +0300

    qemu-armv7: Kconfig cleanup
    
    RAMBASE, RAMTOP and XIP_ROM_SIZE are not used with ARCH_ARMV7.
    
    Change-Id: I072ed022e3279ed23716fdf78d0db8952b3fdb32
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5627
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b53b50b8c117015220556803e2147465c1e6ba9b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 29 20:26:02 2014 +1000

    asrock/e350m1: Sanitize #includes
    
    Following similar reasons as:
    5ff4b08 jetway/nf81-t56n-lf: Sanitize #includes
    
    Change-Id: Ie88b884bc2d4481bc2583d5be1f4d1376547f3c3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5614
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

commit dbadb0a8271974915f4c94113509277dd9cc10b2
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 2 03:41:56 2014 +1000

    jetway/nf81-t56n-lf: Set OEM to Jetway in DSDT and mptables
    
    Jetway builds this hardware, so let us be sure to set the truth in the
    DSDT Definition block and MPTables.
    
    Change-Id: I2dfb89152aa3b895ec6975293c5a5998ab6b52bd
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5630
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0bb0affede3e93a9dee09d04c0793abaa53d2f64
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 2 03:58:32 2014 +1000

    arch/x86/boot: Indent mpspec.c and make a loop more legible
    
    Fix some space->tab style and a for-for loop embedded to be more
    understandable/readable.
    
    Change-Id: I740c544e8c9330e6efbbd66a5c1e6a4a33d1a75e
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5631
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e72645a852a60610fc6419640d855d6c7e5409fb
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Apr 29 23:31:55 2014 +0200

    asrock/e350m1/devicetree.cb: Correctly indent device line
    
    Fix up commit dfa8a32f [1].
    
    	src/mainboard/asrock/e350m1: Properly indent devicetree.cb
    
    [1] http://review.coreboot.org/5612
    
    Change-Id: I59b3ec2f00d69951aa8a96c4a9c3de5b219acbfb
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5619
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bbe3e44310700a6c5c80647b5c1da21336d18364
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri May 2 03:11:42 2014 +1000

    mainboard/jetway/nf81-t56n-lf: Properly indent devicetree.cb
    
    Following the reasoning in,
    dfa8a32 src/mainboard/asrock/e350m1: Properly indent devicetree.cb
    
    Change-Id: I88ca01519c1c47a7eb0d564a55c945589f9d32af
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5629
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f12a2473c0aebc4cdf64811061f759bf694dfb57
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 29 14:05:02 2014 +1000

    superio/winbond/w83627thg: Remove w83627thg_enable_serial symbol
    
    Remove model specific implementation, w83627thg_enable_serial, from
    romstage component of sio support.
    
    Change-Id: I8ef1de5ccccae5f4dba69dbdb939e7070d3cecfc
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5604
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 0dd0669c5910273bfe82cd2b0c0a41984d564631
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 29 13:59:54 2014 +1000

    mainboard/*: Use generic winbond romstage in place of w83627thg
    
    Use the generic implementation of winbond in place of the model specific
    w83627thg_enable_serial() as so that it maybe removed later.
    
    Change-Id: Ice1a0dc428de9a3ddfb79e877fb03c7a8e09665f
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5603
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 04f5c4eca770641ec8e7090e0f0cd41906b94b07
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Oct 17 16:38:56 2013 +0300

    Build without ChromeOS
    
    Change-Id: I1da636573eed62ce693b984917084643787c094b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3978
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 6578475d93c2584942bf58601ee0b07fd925838b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Dec 22 03:12:38 2013 +0200

    ChromeOS: Use common fill_lb_gpio()
    
    Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5586
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 9ab1c106c3ec88adfefc0dfe237e538e33f2750d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Dec 22 00:22:49 2013 +0200

    device: Conditionally bypass oprom execution
    
    Builds with CHROMEOS can bypass VGA oprom when boot is not in
    developer or recovery modes. Have the same functionality available
    without CHROMEOS but with BOOTMODE_STRAPS.
    
    Change-Id: I97644364305dc05aad78a744599476ccc58db163
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5595
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit ab56b3b11c34b5315fadc2147f5d1a860dccc419
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Nov 28 16:44:51 2013 +0200

    ChromeOS: Remove oprom_is_loaded
    
    A global flag oprom_is_loaded was used to indicate to
    U-boot that VGA option ROM was loaded and run, or that
    native VGA init was completed on GMA device.
    
    Implement this feature without dependency to CHROMEOS option
    and replace use of global variable oprom_is_loaded with call
    to gfx_get_init_done().
    
    Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4309
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 926a8d1262c09fda9868f73cf0241140ccf09ec9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Apr 27 22:17:22 2014 +0300

    google/stout: Fix build without ChromeOS
    
    Currently we have no developer or recovery mode switches when
    building without ChromeOS.
    
    Change-Id: I49adfcd8408838cf581430970be5efcef11ba06b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5596
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 5687fc9d2120c01b929f24df07667f87089f9b5f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Nov 28 18:11:49 2013 +0200

    Declare recovery and developer modes outside ChromeOS
    
    Move the implementation for recovery and developer modes from
    vendorcode/google/chromes to lib/.
    
    Change-Id: I33335fb282de2c7bc613dc58d6912c47f3b5c06c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4308
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 580e5642a8d1db1bc85c5d55dc2227f3fda8eb34
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu May 1 16:31:34 2014 +0300

    device: provide option to always load PCI option roms
    
    Certain kernel drivers require the presence of option rom
    contents because the board's static configuration information
    is located within the blob. Therefore, allow a chipset/board to
    instruct the pci device handling code to always load but not
    necessarily run the option rom.
    
    BUG=chrome-os-partner:25885
    BRANCH=baytrail
    TEST=Both enabling and not enabling this option shows expected behavior.
    
    Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/188720
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5594
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit d5403773901d15e9c54a1a0241798a3ebc8612b9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu May 1 00:02:43 2014 +0300

    console: Fix UART selection prompt
    
    Without this change, removal of default UART_FOR_CONSOLE entries
    under mainboard/ Kconfig will remove this option entirely from
    created .config file.
    
    Change-Id: I11422ddb8c51abca177f999936c995ae0c91c459
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5626
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 93966e859234d4aca84a78b45933a74e973497c5
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Nov 4 17:28:19 2013 -0800

    baytrail: Add default _OSC method
    
    This is needed to let the kernel know it can control everything
    and not to disable features.
    
    BUG=chrome-os-partner:23505
    BRANCH=rambi
    TEST=build and boot on rambi
    
    Change-Id: I40ff15bb931a9be7c31509ec84489083b5af0a82
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175629
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4939
    Tested-by: build bot (Jenkins)

commit 053bd0753bc4433236ed21c1d4ce5bf5842bb434
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Nov 4 17:19:16 2013 -0800

    baytrail: Add root bus resource regions
    
    Populate the PCI mmio region from NVS TOLM variable.
    Other regions are fixed.
    
    BUG=chrome-os-partner:23505
    BRANCH=rambi
    TEST=build and boot on rambi
    
    Change-Id: Iec8352b0464ad850a76bd1706c028628c477731d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175628
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4938
    Tested-by: build bot (Jenkins)

commit 03ff2a242eac43636673183f11b710fc86b3b900
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Nov 4 17:15:20 2013 -0800

    baytrail: Add MCFG table to ACPI
    
    This adds the PCI configuration region table to baytrail.
    
    BUG=chrome-os-partner:23505
    BRANCH=rambi
    TEST=build and boot on rambi
    
    Change-Id: I0d975709a4a18d0f1c5e24581c9fd2190fe2996b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175627
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4937
    Tested-by: build bot (Jenkins)

commit abab05cb3cf5cb7a7579a839ea486bf61fc62e45
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Nov 4 17:12:30 2013 -0800

    baytrail: Clean up NVS region
    
    There is a lot of NVS allocated to things that are not really
    used.  Most of these are removed and some are moved around.
    Thermals are expected to be handled with DPTF so I've removed
    that bit of code but have not yet cleaned up the thermal zone.
    
    I left in the SIO BARs since I think we will need those still
    even though they may need work still.
    
    BUG=chrome-os-partner:23505
    BRANCH=rambi
    TEST=build and boot on rambi
    
    Change-Id: Id16ee67e6b3709a303c001afd72947147f938127
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175626
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4936
    Tested-by: build bot (Jenkins)

commit 1f52f51f4e6dd2c97faa46e3287460d8b2ad335b
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Nov 4 17:02:45 2013 -0800

    baytrail: Add function to read top of low memory
    
    The top of low memory is also the start of the region where
    PCIe resources are allocated.  This needs to be passed in
    ACPI but is only readable from IOSF.
    
    BUG=chrome-os-partner:23505
    BRANCH=rambi
    TEST=build and boot on rambi
    
    Change-Id: Iad95335f72dc3e35b837bedb8d52d388c861a330
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175625
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4935
    Tested-by: build bot (Jenkins)

commit 7fbe20bd2c3b8e0bcb667f5b1a07b80402fa8504
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Nov 4 17:00:22 2013 -0800

    baytrail: Add reserved MMIO regions to ACPI
    
    Add a length define for all the reserved MMIO regions and
    use them in the ACPI code to reserve the regions there.
    
    Add a region for the "abort page" documented in the EDS.
    
    BUG=chrome-os-partner:23505
    BRANCH=rambi
    TEST=build and boot on rambi
    
    Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175624
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4934
    Tested-by: build bot (Jenkins)

commit a90a59f5a3bfc22d6317186c004409469d1b031e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Nov 4 11:22:27 2013 -0800

    baytrail: Fix XHCI problems and re-enable
    
    - a few clock gating bits were set improperly and were preventing
    the system from transitioning out of S0 state.
    - the XHCC registers were not getting the top byte set properly
    which includes things like DMA write request size and request
    boundary crossing control.  This was causing memory corruption.
    
    BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=build and boot kernel from USB on rambi with XHCI driver
    
    Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175558
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4933
    Tested-by: build bot (Jenkins)

commit 81998090792ebc1a6e39455f5fcb4d2c9ec9c095
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Apr 28 18:07:33 2014 +1000

    mainboard/: Avoid including early_serial.c from w83627hf
    
    Following the reasoning of:
    dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c
    
    Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5597
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f385ba42e340863df18555bf3cfffe70a96e2d8c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Apr 29 23:27:32 2014 +0300

    console: Move UART port defaults to mainboard
    
    Correct selection of UART depends of board layout, not the CPU
    internals, so default setting should originate from mainboard.
    
    Change-Id: Ibf0ab0847ccce73c22704e86983dbe3d24ebc8a0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5618
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 48713a1bf7c2e55c34609a051b0dee7166c4a017
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Apr 15 18:19:48 2014 +0300

    console: Drop EARLY_CONSOLE option
    
    We have means to easily disable a specific console in romstage if
    necessary, so this global option makes little sense.
    
    The option was initially introduced as a work-around for build issues
    around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs.
    
    Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5607
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 28837c6b014dec37a3b4deeb8407469356b81e05
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Apr 4 20:32:59 2014 +0300

    allwinner/a10: Hide SoC specific UART functions
    
    If platform has a component coreboot has to communicate with using
    one of the UARTs, that device would not be part of the SoC and
    must not use functions specific to a10 UART.
    
    Change-Id: Ifacfc94dfde9979eae0b0cfb723a6eaa1fbcd659
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5469
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 70342a7f51a0069446966c42db4dbc44f6db16ee
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Mar 14 22:28:29 2014 +0200

    uart: Support multiple ports
    
    The port for console remains to be a compile time constant.
    The Kconfig option is changed to select an UART port with index
    to avoid putting map of UART base addresses in Kconfigs.
    
    With this change it is possible to have other than debug console
    on different UART port.
    
    Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5342
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit a8d089d3acc0c2254b3dbeb04c1e622ab01e6d98
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Apr 27 20:29:10 2014 +0200

    towiki.sh Move vendor link to the first column.
    
    It is not easy to see that there are two links,
    one to coreboot wiki and second to the vendor page.
    This change moves the vendor page link to the vendor
    column, separating it nicely.
    
    Change-Id: I3063be476231d04f833350043010a6e0001697e7
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/5593
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 68eff4fb1cc9e0d83a21e736143ad6ae8c41bc36
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Mar 3 09:18:18 2014 +0100

    lenovo/{t60,x60}/devicetree.cb: Fix typo in Controller in comment
    
    	$ git grep -l Cnotr | xargs sed -i 's/Cnotr/Contr/g'
    
    Change-Id: Iee826a8092dbf17f8a28b7eb7b6d183464c6e498
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5325
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b67e9a1acd82fec30235c69f717a0103f245667a
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Mon Apr 28 18:13:44 2014 +0800

    crossgcc: Support OSX 10.9 built-in tar utility program.
    
    Unlike OSX 10.8, OSX 10.9 doesn't provide GNU tar program, and built-in
    tar program is bsdtar 2.8.3. bsdtar can build crossgcc toolchain.
    Modify buildgcc to support tar in OSX 10.9 (uname = Darwin).
    
    Change-Id: I093898f8f99e29918387f9b275a30af461a7e1be
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/5598
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit dfa8a32f1f9603d852538de909ead732bc4f9b86
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 29 20:03:31 2014 +1000

    src/mainboard/asrock/e350m1: Properly indent devicetree.cb
    
    Trivial: clean up spaces to tabs to properly indent devicetree.cb
    
    Change-Id: Id5577139cfa039898af3b2158fdd6869ac9d2ec1
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5612
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 178a60b4b3c633c5c3311aaa134d0399e3d011d6
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 29 13:53:35 2014 +1000

    mainboard/kontron/986lcd-m: Remove a duplicate header
    
    Change-Id: I0dd50722c1ccbcb8a21b8fbab4d706d6b2f2b130
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5602
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 47a14b15cb2de20827fec741d24ebf32e64d273f
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Feb 9 10:20:02 2014 +0100

    util/board_status/board_status.sh: set its executable flag
    
    Change-Id: I58f6d356bf1625ee205a536ee95c08294891b123
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5171
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit bb6c2162d17bf6acf0ba874c12f5dc7cf3cdde05
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Apr 29 07:15:26 2014 +0300

    AGESA SPI: Fix Kconfig options
    
    Option AMD_SB_SPI_LEN leaked to non-AMD configs.
    Option SPI_FLASH is compulsory with HAVE_ACPI_RESUME.
    
    Change-Id: Ib84c4d9e4fdf670b32b0cae7280fcbb6d3aecaf5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5606
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 88e518f4bca789c81c866bddbce3f6e0015d7ad3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Apr 29 07:11:39 2014 +0300

    SPI: Use common dependency in Kconfig
    
    Change-Id: I11118a4fe1e05017349feae004f98a17bb02386b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5605
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 9e308b9955760ca768b35420d5373e59f398d174
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Apr 27 23:28:31 2014 +1000

    superio/winbond/w83627ehg: Convert romstage to generic component
    
    Convert the serial init to the generic romstage component and
    corresponding boards using this sio.
    
    Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5589
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 959adc3fcff5d2f943f9e064e1162cdb5e5f8ec3
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 29 03:31:10 2014 +1000

    mainboard/tyan/s8226: Remove redundant sio header
    
    Change-Id: I8d258c12d03e71fb525251104b4fa81596ad2187
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5599
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ffe460d77ab5bcbdbaeef095f807dd0fdbefd42c
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Apr 27 22:51:40 2014 +1000

    superio/winbond/w83627dhg: Convert romstage to generic component
    
    Convert the serial init to the generic romstage component and
    corresponding boards using this sio.
    
    Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5588
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit dbbc136c83d08db6f93f77ff897b64be2b90d078
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Apr 28 02:07:32 2014 +1000

    mainboard/asrock/e350m1: Avoid including early_serial.c
    
    Use generic winbond romstage serial init symbols instead of model
    specific implementation. We do this on a case by case basis as some
    boards are ROMCC and so need to #include .c files. This is a step to
    migrate non-romcc boards to a more generic superio framework.
    
    Change-Id: I56f6d9ec77cd21a612cbbdb48634543f34a2e72c
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5591
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 5a032c628b51e39fc160102f17f52ba0678db32d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Apr 27 22:41:31 2014 +1000

    superio/winbond/*: Provide common romstage component
    
    Following the reasoning of:
    cf7b498 superio/fintek/*: Factor out generic romstage component
    
    Change-Id: I3e889c0305c012e7556a5dd348e7f1e1ba629a9d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5587
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 2458f42b27e6525f4131899ef36f21d0f7dace1a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Apr 22 16:46:31 2014 +0300

    AMD: Add common header file for CAR setup
    
    Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4683
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cf7b4989083cb3fd1adf34dc5e07d4ac253e8f85
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Apr 23 21:52:25 2014 +1000

    superio/fintek/*: Factor out generic romstage component
    
    The romstage of Fintek Super I/O's is identical, leading to replication
    of essentially the same code prone to bitrot. Herein we consolidate the
    early pre-ram UART initialisation code into fintek/common, rather we
    leave the exceptions to be implemented under model/.
    
    More precisely we provide a well documented version of early_serial.c
    under fintek/common and select by way of Kconfig as a generic romstage
    component to Super I/O support. We leave future Super I/O's the option
    to implement `non-standard` initialisation code should such a (unlikely)
    need araise. A primary advantage is that new support for romstage serial
    is now trival to add. We also provide some Kconfig documentation while
    here.
    
    Change-Id: I3c62561558a62ece944a167ba302fb7076bba001
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5575
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4566d2e7cd32c1c2bdcc85a09c580e9f00f6b1dd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 23 10:28:59 2014 +0300

    uart8250io: Fix build with DEBUG_SMI
    
    Change-Id: I5110af348d22c0abc940f0922854fdd7e0c7e2e9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5574
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 6bedc274266b8b326860c2ab35ce8cb9ec7ccbb0
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Feb 12 21:53:44 2014 +1100

    libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.
    
    Alignment-agnostic encode/decode bytestream to/from little/big endian.
    
    The le16enc(), le16dec(), le32enc(), le32dec() functions encode and
    decode integers to/from byte strings on any alignment in big/little
    endian format. See BYTEORDER(9).
    
    Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5198
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f33782fb86ec2862a875843c19a923c19b90cd48
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Apr 18 15:07:56 2014 +0200

    lippert/hurricane-lx: Kconfig cleanup
    
    A Kconfig option defined instead of selected that really comes from
    somewhere else.
    
    Change-Id: I8730d12ed053520b794655e943c93583c441f3f1
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5542
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 6d51f6b2e8f4633a85d983b5bf8dcfc429df4c6c
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Apr 23 17:01:45 2014 +1000

    superio/fintek/*: Fix header style
    
    Remove some redundant includes. Fix repetitiveness in include guards and
    strip some misplaced tabs for whitespaces.
    
    Change-Id: I1f0bf6951cc6714f63e88b323754515fb02c089c
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5572
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 20f25dd5c8a513ee136e9f6d8c67959591298617
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Apr 22 10:41:05 2014 -0700

    Rename coreboot_ram stage to ramstage
    
    Rename coreboot_ram stage to ramstage. This is done in order to provide
    consistency with other stage names (bootblock, romstage) and to allow any
    Makefile rule generalization, required for patches to be submitted later.
    
    Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: http://review.coreboot.org/5567
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 817149643c27fca022cf526d6113a4aff898d511
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Apr 22 11:48:30 2014 -0700

    Get rid of HAVE_INIT_TIMER config option
    
    There is redundancy in terms of use of init_timer. We have a Kconfig option to
    decide whether a board has init_timer as well as we use a stub for init_timer in
    places where we do not have any init_timer defined. Thus, remove the Kconfig
    option. Henceforth, all boards that do not have init_timer functionality can
    include a stub_timer if required.
    
    Change-Id: I35d38ec686f4dc92861cf9248f9b540323cd98ae
    Signed-off-by: Furquan Shaikh <furquan@google.com>
    Reviewed-on: http://review.coreboot.org/5569
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ea2900bd6c260bb8b06a8b9e3fc93a21bd87d2e6
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Apr 23 04:21:53 2014 +1000

    superio/ite/it8673f: Remove poor implementation
    
    Following the reasoning of:
    HASH superio/ite/it8705f: Remove poor implementation
    
    Change-Id: Ic0722116b84acf4f3c3ef4b18b961a56f0f50718
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5568
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 45b7b5af763c6b3ab385690891641103b41e4816
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Apr 23 04:00:38 2014 +1000

    superio/ite/it8705f: Remove poor implementation
    
    This super io support is poorly implemented and would not work for all
    boards since it hardcodes values. Since there are no users of it, remove
    for now pending a fresh reimplementation from scratch.
    
    Change-Id: I818a9f4d2ab106b989824e49cee49d79acd6041a
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5566
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5c41ee69ef27575f93441f487b1d9f4c2d97f8e0
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Wed Apr 23 01:43:38 2014 +1000

    superio/ite/it8716f: Rewrite from hardcoded base addr
    
    Following the same reasoning as:
    HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr
    Removing hard coded magics and expose sio pnp api in romstage.
    
    Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5565
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 03ad2a26b07909a5c34a1ade30f905ae3de5b8a0
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Apr 21 17:34:38 2014 +1000

    superio/ite/it8721f: Rewrite from hardcoded base addr
    
    Rewrite early_serial.c implementation to honour a passed base address in
    device_t, removing any hard coding of values. We also expose early sio
    init functions as romstage symbols to avoid falsely #including
    "early_serial.c" in romstage.c of board support.
    
    Change-Id: I521b8f7cf85173345b90745c6f2ab66e25429f5d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5561
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 392de45ae2d9550c3b95078bff7a52c9e5eed563
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Apr 17 22:24:40 2014 +1000

    mainboard/*: Remove DUMP_ACPI_TABLES from amd boards
    
    Dumping the ACPI tables in this way has limited use, is not likely to be
    used and is poorly implemented. There are much more sophisticated tools
    available on Linux for debugging ACPI as such this code is outside the
    scope of coreboots 'bring up the hardware only' philosophy.
    
    A more generic implemention could be done with hexdump() in coreboot
    proper following on from this cleanup.
    
    Change-Id: Ifd3bfb76338609d18fcf7158d3c9a6d7c06c8847
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5530
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit d6060b7142310a7a5d3a4912bbd08d230cad90b1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Oct 17 18:50:13 2013 +0300

    usbdebug: Add BeagleBone Black
    
    Avoid some confusion as the selection of "BeagleBone" is not compatible
    with the product "BeagleBone Black".
    
    Change-Id: If73f80565cd26d2b41db972b4474ab85b609c1ad
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4289
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 147f703aa9296e7b08dfa3c38eaca5ab29ff817c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Dec 22 13:13:17 2013 +0200

    Drop drivers/generic/debug
    
    Not very popular nor useful nowadays.
    
    Change-Id: I3dc0f7aaf188950a43f5350d3a95669fbbdcfd94
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4554
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 86777e36b3238feaf91558b969c1794057c5ff47
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Apr 20 14:36:29 2014 -0500

    southbridge/hudson: Initialize ACPI IO ports separate of FADT
    
    The ACPI IO ports, and the respective SMI (for HAVE_SMI_HANDLER), were
    initialized when the FADT table was written. This works well on a cold
    boot, but the ACPI ports are not initialized on S3 resume, as ACPI
    tables are not written. This will not work on S3 resume if the default
    ports are not what we set them, or if AGESA sets them to some other
    value.
    
    To solve this, move the port configuration to southbridge chip init.
    
    Change-Id: Ib4043f0fa5e20f08d320acd12ce84d4d789cd035
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5559
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit cf38facbd2255562cfbf2a2bc528794fafa5891a
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Apr 19 16:22:53 2014 -0500

    hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18
    
    The PCIE PME pin from the APU is connected to GEVENT8, but the
    northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map
    accordingly.
    
    Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5556
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit 7efd5fda490dba79a30aeb83d966349eaf59baea
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Apr 19 13:36:49 2014 -0500

    hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11
    
    Hudson ASL files assume the USB power event notifications are mapped
    to GPE 0xb. Since that GPE is not used on this board, map these events
    to GPE11. This GPE is already handled in ACPI via Method(_L0B). We
    adjust this method to also notify the XHCI controller at PCI 10:0.
    
    Change-Id: If33dd4bb5830820227f7c8b34594886cfae37282
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5554
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit 44f2fab89a099b055e3ad7dc5cfe2fbeb82467e6
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Apr 18 01:42:19 2014 -0500

    AMD hudson and yangtze boards: Let mainboard declare power button
    
    The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and
    always had the wake source declared as GPE3. This is not the correct
    wake source for all boards. On some laptops declaring a wake source is
    not needed, as the wake mechanism is handled by the EC.
    
    Move the declaration of the power button to mainboard ASL files, and
    scope it as \_SB.PWRB . This also makes the naming consistent with the
    examples in the ACPI spec. The wake source for the PWRB of HP Pavilion
    M6 1035dx is removed, as it is incorrect.
    
    Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5546
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit ce7a8024ffa079590cbc841b7d2fd78770a59c3b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Apr 21 20:14:34 2014 +1000

    mainboard/asus/m5a88-v/devicetree.cb: Fix formatting
    
    Strip incorrect comments pretaining to the superio, and replace spaces
    with tabs.
    
    Change-Id: Ib3f6094c552777552d0ec06e3236210ee2e7b05d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5562
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 0a57e999b75d733669383bdc5d4c693b1d675a5d
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Apr 19 15:10:14 2014 -0500

    hp/pavilion_m6_1035dx: Do not re-init EC and lid SMI on S3 resume
    
    It's not needed, and puts the EC back into APM mode. The EC does not
    shut down during S3 sleep, so we don't need to re-initialize it.
    Lid SMI will have been disabled in the switch to ACPI mode, don't
    re-enable it.
    
    Change-Id: I2c06df140f63427dac32ae095d29e68f64135358
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5555
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit cf1f9b6a5bd1be169756dd1cd9568492a880651c
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Apr 20 13:24:42 2014 -0500

    southbridge/hudson: Remove redundant definitions of ACPI IO ports
    
    The ACPI IO ports were defined twice, and used inconsistently. Only
    keep one of the definitions for consistency.
    
    Change-Id: If5744f9375fdaa97ceb9ba03dca8aa825eecf159
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5558
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 991e951461bc57debc2df82bac76d0ab57682e66
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Apr 19 22:21:27 2014 -0500

    southbridge/amd/agesa/hudson: Refactor SPI controller driver
    
    The SPI controller driver used numerical offsets to access SPI
    registers, making it unreadable without the datasheet. Use less magic
    and more #defines to improve readability.
    
    Change-Id: I8a1f11645cfce027e5df7a41a98c70249695889e
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5557
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit c38d9913878019bbe476b8b8bc5631846ef2e58f
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Apr 18 21:29:59 2014 -0500

    hp/pavilion_m6_1035dx: Suspend/resume on lid close/open with ACPI
    
    This patch completes ACPI support for the lid switch. The lid SCI now
    notifies the OSPM of the status change when the lid is closed or
    opened, allowing system to suspend. The wake source is also declares,
    and the system wakes when the lid is opened.
    
    The system resumes successfully, but the display still does not come
    back on.
    
    Change-Id: I803c4fc64e15f8d1a90791ec246af66604646d8b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5549
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit c4e7db51fc83b99c43b25a8f698a9d007ed45dc6
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Apr 5 13:40:33 2014 -0500

    hp/pavilion_m6_1035dx: Add GEVENT to GPE SCI mapping table
    
    Each GEVENT pins can be mapped to a specific GPE via the SCI map.
    The default mapping is not appropriate for this laptop, so use the
    AGESA functionality to map currently known events.
    
    Change-Id: Ifa50bf000cfc8e77a6a4d84752f89838f165f7a0
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5548
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit a9a366171006aad3b928307c2dfb7b3e7793d4ef
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Apr 18 19:53:51 2014 -0500

    hp/pavilion_m6_1035dx: Move GEVENT/GPE definitions to common file
    
    These definitions were scattered in a couple of files, and we risk
    scattering them all over the place. Provide a common file for these
    definitions.
    
    Change-Id: I1fe99e5097cf10a349661f3b2ae2377f5cdd6103
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5547
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 46b0951182c07b7bcd86fd2b66ac162d99eee3f3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Apr 17 15:07:47 2014 +0300

    Move MAX_PHYSICAL_CPUS to AMD k8 and fam10
    
    This was always AMD-only and it was never properly used with AGESA.
    
    Change-Id: Ifb461ee845e442f6cf90aca52470cfb66e862bfc
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5540
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit a6c525a7d5ad0dedc31dcc9719be6bc5fbc743dd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 16 09:43:40 2014 +0300

    AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
    
    Following boards use cimx/sb700:
      amd/dinar
      supermicro/h8qgi
      supermicro/h8scm
      tyan/s8226
    
    Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0.
    There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1).
    
    Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0.
    Together with documented 4-bit restriction for APIC ID field, this APIC ID
    programming matches with MP tables and ACPI tables.
    
    I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which
    we do not have in the tree.
    
    Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5539
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 35546deba642d3bb341d329fc1b9711727a5c50e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Apr 17 15:07:32 2014 +0300

    AMD AGESA cimx/sb800: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
    
    All boards had APIC_ID_OFFSET=0 and MAX_PHYSICAL_CPUS=1.
    
    Change-Id: I6f08ea6de92a2af79fb3a99c5edd942b3a321c43
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5538
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 981639233766a95b9642f7268519eafeccc57464
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 16 09:43:40 2014 +0300

    amd/torpedo: Remove unused Kconfig options
    
    These are not used with cimx/sb900 vendorcode.
    
    Change-Id: I489ee80c739b31edac649491497162c65316996e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5537
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 29c3e367da8f80becacb66193d044f90b49bf0c5
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 16 16:30:00 2014 +0300

    AMD cimx sb700/sb800/sb900: Fix NODE_PCI and use of MAX_PHYSICAL_CPUS
    
    Match the definition of NODE_PCI() with get_node_pci(), so romstage
    and ramstage agree of the PCI BDFs for nodes.
    
    Note that all board have CONFIG_CDB = 0x18 and the maximum for
    nodes = 8, so we always have (CONFIG_CDB + x) < 32.
    
    Change-Id: I676ee53a65ef5b1243df2c5889577dd987c8fc9c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5536
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit b1ccccc2073c40f622f5c0b2e861c3e8453a94f9
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 19 22:20:14 2014 +0100

    mainboard: New port Packard Bell LM85.
    
    Change-Id: I8c1548470c605d06825fe35579879e806bf33542
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5271
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 5c97142419a7b7204786fea5b785c23a3bb41836
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 15 14:32:53 2014 +1000

    drivers/elog: Fix implicit function declaration issue
    
    Fix compilation. Relying on the pre-processor to condition an if
    statement will lead to warnings of implicitly defined functions. To
    solve this dilemma add symbols to resolve to at compile time.
    
    Change-Id: Id0117528c5579cc1dec750a8a17a76fab4314b3f
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5504
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 3bc6eb544ccfcd2f338652ca109442a8b8a01161
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 25 14:53:28 2014 -0500

    rmodule: add subsections to linker script
    
    Depending on the compiler options, subsections of the form
    of .section.subsection could be generated. Therefore, include
    those subsections for .bss, .sbss, and .data.
    
    Change-Id: I80dd64d8c62e7bc449ee2bbc0a22a941777e2ea6
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5407
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 7f09b754f982bc232a112a5593da08b3e24db509
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Apr 9 20:52:46 2014 -0500

    hp/pavilion_m6_1035dx: Implement MB.LIDS ACPI method
    
    Change-Id: I654ca745f7404b86aa25fb2e696751d616d0ca03
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5517
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 5db38a38c9e3dd50e2e513414a2a1b7ab80250a4
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Apr 9 20:51:41 2014 -0500

    hp/pavilion_m6_1035dx: Implement ACPI for wireless toggle hotkey
    
    Change-Id: I2e9ab68263648af8c9d46999e960f0a0711b61d7
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5516
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit fa840676f5f3bd92b63c352f0c8bf6f14bc2c314
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Apr 9 21:07:43 2014 -0500

    ec/compal/ene932: Update to use coreboot EC-mainboard API
    
    This patch implements a simple interface between the EC and mainboard
    ASL code. This interface does not rely on the preprocessor, and
    prevents name conflicts by scoping the interface methods. As this
    interface is documented on the coreboot wiki, an in-tree documentation
    is not provided.
    
    Change-Id: If0b09be4f5e17cc444539a30f0186590fa0b72b5
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5515
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit 91b6d3a6b9430c94989d37982a56ead948419e78
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Apr 18 01:01:10 2014 -0500

    hp/pavilion_m6_1035dx: Rename "LID0" ACPI object to "LID"
    
    There is only one lid switch, so it does not make sense to number it.
    This naming is also consistent with the examples in the ACPI spec.
    
    Change-Id: Ida0a4a89ca03b2aad4fc77e52996e86332d370cd
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5545
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 489ff7ef877abaa956e66e2c35e128f999570607
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Apr 17 23:41:19 2014 -0500

    hp/pavilion_m6_1035dx: Shutdown when lid is closed on non-ACPI OS
    
    This is handled by generating an SMI when GEVENT22 goes low. This pin
    is driven by the EC when the lid opens or closes. This SMI is
    disabled when switching to ACPI mode, so ACPI OSes are not affected.
    
    Change-Id: I38193572bf0416fd642002dba94c19257f0f6f5b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/171
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit 599d668cdd8438820d9ca8f54826163662b2a6f0
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Apr 17 23:33:50 2014 -0500

    southbridge/hudson: Compile refactored SMI setup utilities in SMM
    
    Refactor hudson_enable_gevent_smi() to allow configuring the interrupt
    mode and trigger level. Move the utilities which are useful in SMM to
    a separate file that is included in both ramstage and SMM. This is
    useful for SMI handlers which need to enable or disable GEVENT SMIs
    on-the-fly. A follow-up patch makes use of this infrastructure.
    
    Change-Id: Ifa4c300c00c178b18d7280690cfc4b8367c669b8
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/170
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit 2ad6ee97638e24db67a02fdb2431fe6a56d7c24d
Author: Wei Hu <wei@aristanetworks.com>
Date:   Wed Apr 16 22:52:59 2014 -0700

    util/cbfstool: Fix "Bad segment type 53534220 Could not load payload".
    
    The magic number mismatch was introduced by commit a8a133
    (Add section header parsing and use it in the mk-payload step).
    
    Change-Id: I73b0adb969816e9d130f19f48e175c57124e2f3a
    Signed-off-by: Wei Hu <wei@aristanetworks.com>
    Reviewed-on: http://review.coreboot.org/5528
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dbe6336f908800ec028dc1a1087d6782e5a38851
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Apr 17 00:47:47 2014 -0500

    hp/pavilion_m6_1035dx: Shutdown on low battery with non-ACPI OS
    
    Intercept the low battery SMI from the EC, and shut down the system
    immediately. The EC only sends this SMI when the OS did not enable
    ACPI mode, so ACPI OSes are not affected by this.
    On the other hand, payloads such as GRUB or SeaBIOS will experience
    the shutdown. This behavior is helpful for protecting the battery, for
    example, when the OS fails to boot and we are stuck in the payload.
    The low battery SMI is triggered at 10% charge, at which point the risk
    of cell degradation exists.
    
    Change-Id: I4c6c1a4feed8576cbdbb1945768de0805a1f5e42
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5527
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit f3390862653f9473359eb9a587842bb04671e6df
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Feb 26 15:19:04 2014 +0200

    console: Simplify the enable rules
    
    Consoles on CBMEM and USB have somewhat complex rules and dependencies
    when they can be active. Use simple variables to test which stage
    of boot is being built for each console.
    
    Change-Id: I2489e7731d07ca7d5dd2ea8b6501c73f05d6edd8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5341
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit e8792be223f5f0c5c6bafffa4056793f3c3bfab7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Feb 26 15:19:04 2014 +0200

    build rules: Identify build stage with simple variables
    
    Provide simple environment variables telling which stage of boot is
    being built. Also move this to arch-agnostic location.
    
    Change-Id: I8cbb5cf91f53e01c06e7d672b5be3f5c235f911d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5410
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit efb0b51e62667ade4d96f2a15eb6ed60bb29a9fe
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Apr 13 17:57:34 2014 +0300

    console: Split ROMCC helpers
    
    These are potentially useful with GDB or SerialICE too.
    Also it reduces the amount of actual code we put in romcc_console.
    
    Change-Id: Id8c56e979660ad9f4eef39c648f68c7ec60edfba
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5339
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 4076072b6c76debae0e328486d9bab71fe391db7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Feb 27 19:30:18 2014 +0200

    console: Use romstage code for ramstage and SMM
    
    Console is arch-agnostic and there is no need for separate
    implementations for romstage and ramstage.
    
    For SMM there is console only if DEBUG_SMI is selected.
    
    Change-Id: I7028eeeff8bfbb9c8552972436b29a7508834d87
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5338
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit fd95624dae22b00e00417dbfa1c0a4a4a40193c0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Feb 3 17:04:22 2014 +0200

    console: Drop driver list in ramstage
    
    This framework was only available in ramstage. So we had to define
    console output functions separately for bootblock, romstage and SMM.
    Follow-up patches will re-enable all the consoles removed here,
    in a more flexible fashion, and with less lines-of-code and copy-paste.
    
    Also the driver list is not in a well-defined order and some of the
    loops could exit without visiting all drivers.
    
    NOTE: This build has no console in ramstage.
    
    Change-Id: Iaddc495aaca37e2a6c2c3f802a0dba27bf227a3e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5337
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit aece3c931e5af19764624e2517a8aeaaa15a0a6f
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Apr 18 10:02:04 2014 +0200

    msi/ms9652_fam10: minor Kconfig cleanup
    
    SMP and IOAPIC shouldn't need to be redefined here, select is enough
    
    Change-Id: I8a66374205b671498ce21b3f174af14e98dbfe48
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5541
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit f951d66d313c8cb9cf838ca8ab2117eb3fd0fa50
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Apr 17 16:34:08 2014 +1000

    southbridge/sb800: Strip obsolete commentary
    
    Change-Id: I5cd9e1fcf197eae966be710b2ab24f49c6885eb0
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5529
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 43cb7ca9223b472b5ecf7f99070e0003e1a31619
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 16 16:29:03 2014 +0300

    AMD hudson yangtze: Drop MAX_PHYSICAL_CPUS in comments
    
    Change-Id: I81de291da7b3db8d04a127d5a304b558f1c75b34
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5535
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit fa4cb6d606a6017758ae1986fe57aea6ed9b0b2b
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Apr 17 11:49:42 2014 -0500

    southbridge/hudson: Remove unused function set_sm_enable_bits()
    
    This function isn't used on hudson, and seems to be copy-paste from
    older southbridges. It is used in sb700 to enable or disable certain
    PCI devices. On hudson, these configuration bits are moved to the PM
    space.
    
    Change-Id: I9b967a2d0a5dddc8341204dadeed90460251915c
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5513
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit 09fe3f83c545c162a4ac97e8c41198b8be915e2e
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Apr 16 18:44:37 2014 -0500

    hp/pavilion_m6_1035dx: Remove code which dumps ACPI tables
    
    Dumping ACPI tables in canonical form has very little value, and is
    of questionable use except when debugging acpigen. Remove the code
    which dumps the tables.
    
    Change-Id: Id13c88cee8674b13e5cf5b5ed32c26283e586fd9
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5526
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 73639e27170355a2bb9a54a340f5bcd2f3dac161
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Apr 9 12:24:39 2014 -0500

    hp/pavilion_m6_1035dx: Add SMI handler and handle EC requests
    
    The EC may disable some functionality, such as Caps Lock LED and
    battery charging if it never receives a command to go in APM mode. If
    we start it in APM mode, then immediately switch to ACPI mode, it will
    not get its SCIs serviced until an ACPI OS boots. If its SCIs are not
    serviced, it may assume the OS has hung.
    
    The way we solve this is to initalize the EC in APM mode, and only
    switch it to ACPI when an ACPI-capable OS issues the ACPI_ENABLE
    command. The switch has to be handled in SMM.
    
    Although we aren't yet processing SMIs from the EC, we are reading the
    status in order to satisfy the EC that the event is handled.
    
    Change-Id: Iffaeb9a6f57841f456c4bce8337dc09b287f8758
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5512
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit 62abbe909d27c7351107b0466acc9ea07b490930
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 16 18:32:07 2014 +0300

    roda/rk9: Drop MAX_PHYSICAL_CPUS
    
    Change-Id: I9c41cccf9058c48006b247aca705a3f869ae82a6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5524
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 288c95882d701bb09c77c8ad1a8904673503656c
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Apr 14 16:35:34 2014 -0500

    southbridge/hudson: Add support for ACPI enable/disable via SMI
    
    This enables the ACPI SMI command port in the FADT table, and sets up
    the hardware accordingly. If we have SMI enabled, then we don't set
    the SCI_EN bit at boot, causing the OS to send the ACPI_ENABLE
    command, as required by the ACPI spec. This gives us a chance to hook
    into the mainboard_smi_apmc() handler.
    
    Change-Id: Ib4c63d55b3132578dcae48bfe2092d4ea35821dd
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5511
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit 22d90e34f95307d143249b53f3bb48f0a674ecbd
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Apr 14 14:38:19 2014 -0500

    southbridge/hudson: Pass GEVENT SMIs to mainboard_smi_gpi()
    
    Change-Id: Ifc368974a7a0dc0756431654fb89668e3846801a
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5502
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 2dbd08faf4be1f2a156730f8857b4c6bb72909e3
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Apr 10 14:35:59 2014 -0500

    southbridge/amd/agesa/hudson: Add initial support for SMM
    
    This sets up the infrastructure to handle SMIs generated by the Hudson
    southbridge. An API for interfacing to mainboard handlers is not
    defined at this point. A few functions are defined to allow mainboard
    code to enable SMIs from GEVENT pins. These are the only functions which
    I expect to be needed anytime in the foreseeable future.
    
    SMIs are always acknowledged and cleared, as not clearing an SMI will
    cause us to re-enter the SMI, effectively bricking the machine if a
    southbridge-generated SMI without a handler occurs.
    
    Change-Id: Ibceb21ac5423eb134d3eb7d24800280b183f7619
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5494
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>
    Tested-by: build bot (Jenkins)

commit 065b7da298953feaec3563bf753f45cf00fba2c0
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Apr 15 15:41:38 2014 -0500

    cpu/amd/agesa/family15tn: Add udelay implementation for SMM
    
    This is a small implementation which uses only MSRs and rdtsc, without
    relying on northbridge or other system hardware. It's SMM safe in that
    it only reads registers, and doesn't modify the state of the hardware.
    
    Change-Id: Ifa02ca73455b382f830c9b30b80b4f1bb18706b4
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5501
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 53072d869ad9234781b5a479dfcc9a9288723da6
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Apr 12 21:57:18 2014 -0500

    cpu/amd/agesa/family15tn: Add initial support for SMM mode
    
    This is the minimal setup needed to be able to execute SMI handlers.
    Only support for ASEG handlers is added, which should be sufficient
    for Trinity (up to 4 cores).
    
    There are a few hacks which need to be introduced in generic code in
    order to make this work properly, but these hacks are self-contained.
    They are a not a result of any special needs of this CPU, but rather
    from a poorly designed infrastructure. Comments are added to explain
    how such code could be refactored in the future.
    
    Change-Id: Iefd4ae17cf0206cae8848cadba3a12cbe3b2f8b6
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5493
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit 342ac64a5d6f5ab639fb140ae69f9b3597878cba
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Apr 14 16:44:19 2014 -0500

    southbridge/hudson: Use MMIO instead of PIO to access PM space
    
    The MMIO region is set up by AGESA very early on, so we can use it to
    access the PM register space in ramstage. 16-bit accessors are also
    provided to simplify some setup tasks. 16-bit accesses are not
    possible via PIO.
    The pm2_iowrite/read accessors are removed, as they are not used.
    
    Change-Id: Ie7967b5086eb004525c39721338c6495aedc8165
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5503
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit f3e82f7969ac191f1b47864b6d5325bd6d8dd485
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 16 14:06:52 2014 +0300

    AMD AGESA fam15tn/fam16kb: Remove unused source files
    
    Change-Id: I45084ffe84fef4dd43acea843d7c93a81c255472
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5523
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 72a1768abab8c2101f833d801aed06c391eadda8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 16 09:43:40 2014 +0300

    AMD hudson yantgze: Drop MAX_PHYSICAL_CPUS
    
    Not used with AGESA vendorcode.
    
    Change-Id: I4de7e49d513a1bc8d6d4da1eea630b9eedf5de80
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5522
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit fd478f92a425f222a1218870a680ad026cd1d0e8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 16 09:43:40 2014 +0300

    AMD hudson yantgze: Drop APIC_ID_OFFSET
    
    Not used with AGESA vendorcode.
    
    Change-Id: I1c4e1dea8836143334d336f99afcee2ca326b0c9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5521
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 740862c7d3620e57b3e128c1230487c046d4b147
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 16 09:43:40 2014 +0300

    AMD AGESA: Drop SB_HT_CHAIN_UNITID_OFFSET_ONLY
    
    Not used with AGESA vendorcode.
    
    Change-Id: Ic9a0513641bf76d748bb106675bccc33c7abe21e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5520
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit aeb48934d4b8d0d8acfd8fa42f7fe3cbfd681ace
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 16 09:43:40 2014 +0300

    AMD AGESA: Drop LIFT_BSP_APIC_ID
    
    Not used with AGESA vendorcode.
    
    Change-Id: Ie99abf5bcffd740e2e7ed6d78937ab32935ef214
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5519
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)

commit ef5ce9a832d5f89d94411f0fb7ff58baad2b6526
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 16 09:43:40 2014 +0300

    AMD AGESA: Drop AMDMCT
    
    This config option is fam10 only.
    
    Change-Id: I7f4619d2d4e7e7695a8ee691d879df2748f1c0c7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5518
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 65f0dbc0647f25a7e067a0fe00c38e1c2cbe2d2a
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Mon Mar 10 17:28:33 2014 +0800

    AMD Thatcher: add IMC fan control
    
    There are 3 steps to enable the IMC fan control:
    1. Enable fan control related registers on Hudson using oem_fan_control().
    2. Set EcStruct.
    3. Enable thermal zone using enable_imc_thermal_zone().
    I have tested on Thatcher.
    
    Change-Id: I959721b4fd8787ac0824f9f873efd4788682eedb
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/5359
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 04eb2e89c6b606920f98db84311b579fd1743060
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Feb 9 10:24:22 2014 +0100

    util/board_status: Only pass switch `-a` once to `git commit`
    
    Change-Id: Iabcb26229401b03ad4ba2df0f78eee08f379aa03
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5172
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 2ac251bba9c5aa0dea0ef75bf9224c929aa26df2
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Jan 10 20:30:16 2014 +0100

    filo payload: Fix the build
    
    Also strip down the config that's set since these are actually
    SeaBIOS options, not FILO...
    
    Change-Id: I5dbe6255996f9e115699ff2a83fb3450533520ee
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4647
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit aeeafc08609bf2f28f603e641340946b5657f86e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Apr 15 20:14:21 2014 +0200

    sconfig: Fix build dependencies
    
    In some cases the build system tried to build main.c before
    copying the various "shipped" files (lex/yacc output) where
    the place the compiler expects them.
    
    Make the dependency explicit.
    
    Change-Id: Iacef5292aadb9fe7bc967aa4ab5ee6c9fe4df3d7
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5510
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9b0de7145927f0158de3fe526ff34e298fdae793
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Dec 29 18:45:23 2013 +0100

    buildsystem: check for coreboot toolchain by default
    
    Other toolchains just don't cut it.
    
    Change-Id: I7a0bdf60d89b5166c9a22c9e9f3f326b28f777b8
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4584
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 34195beed12dd91805c9e7beb1d49038ecf123b6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Jan 21 23:03:27 2014 +0100

    abuild: break early if building tools fails
    
    Change-Id: I8da04df024a31c780b924a586d056a5351845153
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4773
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7bd269e22505a158e9c77e18493c1e561f8dce0d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Apr 12 21:57:13 2014 +0200

    abuild: more verbose configuration step
    
    Also pass V=1 to the configuration step, if requested.
    
    Change-Id: If8b413d65d6bac34efab63614d039d74d920c8db
    Reviewed-on: http://review.coreboot.org/5492
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6ac7f5301ffa3b33cddfd6936b043bc9a6fbd222
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Mar 28 13:17:10 2014 -0500

    hp/pavilion_m6_1035dx: Add EC keyboard controller to devicetree
    
    This causes coreboot to call the keyboard initialization code for the
    KBC. This is only needed for payloads which do not initialize the
    keyboard.
    
    Change-Id: Id0bb77f2a8115fafc0cd6165a8431a7e07f0fac1
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5514
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit e07cb65c20bdbb7f51c8e617969a956ec0ac8363
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 1 04:13:26 2014 +1100

    vendorcode/amd/agesa/fam14: Build as a static library
    
    Following the same reasoning as commit
    ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library
    Since AGESA is stage-independent, we can build it just once, and use
    the resulting static library in both rom and ram stages.
    
    Change-Id: I8b78c462f4963fbb3a40d739196529fffedccb4c
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5441
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 00b61460301514ea44d847f6b6617e5f9091a8cb
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 15 19:43:05 2014 +1000

    hp/pavilion_m6_1035dx: Use hexdump() for dumping ACPI tables
    
    Following the rational of:
    5188d40 jetway/nf81-t56n-lf: Use hexdump() for dumping ACPI tables
    Use "Debugging -> Output verbose ACPI debug messages" in menuconfig to
    toggle.
    
    Change-Id: Ibf03ef916a789d0f049190755213ba93191d4662
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5507
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit ef4dcc09bbfbd7bb610ad51d6080fe01ace66dcc
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Apr 15 17:26:46 2014 +1000

    mainboard/jetway/nf81-t56n-lf: Make ACPI debug menuconfigable
    
    Turns out we have a CONFIG_DEBUG_ACPI definition under:
    Debugging -> Output verbose ACPI debug messages
    Hence, let us make use of this definition.
    
    Change-Id: I1b673feb6d9b2ee51c832a1cef159cd80e5c3517
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5506
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit feebd86ad2fe78955fda852103a8363a2da0cf59
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Apr 10 19:12:28 2014 +1000

    mainboard/jetway/nf81-t56n-lf: Documentation cosmetics
    
    Keep under 80 colums and Doxygen'ify inline documentation somewhat.
    Strip some whitespace bulk while here and refactor a little as to line
    wrap.
    
    Additionally, following the reasoning of:
    0b2fa34 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
    remove some fluff from buildOpts.c
    
    Change-Id: Icb38f087724d3e3511df1d554a620eb637ce286a
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5481
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit c12db59bced7b54dc9f55bbb06716a46875b211a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Apr 13 20:21:56 2014 +1000

    superio/ite/it8728f: Fix headers and prototype location
    
    Try to conform to some kind of standard/consensus for prototype
    location. Correct headers while here.
    
    Change-Id: Ie99b1801fa42ddefb9f25d54f326ba7131bd7089
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5499
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 01e0adf267dbe741e2c50137fbc8848c40ce0db9
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Mar 29 17:07:26 2014 -0500

    southbridge/amd/agesa/hudson: Clean up AGESA #includes
    
    Just like in commit
    * 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes
    
    Include AGESA headers specifying the path relative to AGESA_ROOT. The
    path is specified relative to AGESA_ROOT as opposed to src/ since this
    code may include headers from different AGESA families, depending on
    the board.
    
    Change-Id: Ide38cc34e207a8b617d1d319fd9c17a785f55833
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5423
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit ee905a8161a2cde891c6ce4dffbf99a89806658d
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Mar 29 13:15:18 2014 -0500

    vendorcode/amd/agesa/fam15tn: Build as a static library
    
    Up until now, we were building AGESA by specifying each AGESA source
    file and adding it to the list of romstage and ramstage source files.
    As a result, we were compiling each AGESA source twice, despite the
    fact that it does not depend on the stage we're in.
    
    Since AGESA is stage-independent, we can build it just once, and use
    the resulting static library in both rom and ram stages.
    
    We still keep the practice of specifying every single AGESA directory
    as an include dir and adding the AGESA CFLAGS to our global CFLAGS;
    this is needed due to the way AGESA builds.
    
    Change-Id: I9b23264129d1c08cb67cabc31d15a68d43ed7624
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5430
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 5405d3fe91ba9f218521c5f0a84561909d37ce5a
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Apr 9 16:14:25 2014 -0500

    hp/pavilion_m6_1035dx: Fix GPIO map and add WLAN pin
    
    Change-Id: I07725b71508c8b08451022307ae934c1b227f7f9
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5491
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 5188d4008b540f4dcda64ce3c7dabbfa0b26dbe7
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Apr 6 20:18:27 2014 +1000

    jetway/nf81-t56n-lf: Use hexdump() for dumping ACPI tables
    
    Use hexdump() instead of a local implementation for dumping ACPI_TABLES.
    
    Change-Id: I20354a4f9dff4105de5af696bb9da4a4f6cca788
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5466
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit cd96e829f1212e3736a23e81ae48bf0109da64cd
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Apr 5 10:21:57 2014 -0500

    hudson boards: Don't require ide.asl file on boards without IDE
    
    Not all boards which use the AMD Hudson southbridge have IDE. However,
    the southbridge's asl included an 'ide.asl' file which had to be
    present in $(mainboard_dir)/acpi.
    
    Address this issue by removing the inclusion of 'ide.asl' from the
    southbridge 'fch.asl' and remove 'ide.asl' from Hudson boards, none
    of which have IDE.
    
    If future hudosn board will come with IDE, the device can be declared
    in the PCIO scope of dsdt.asl, right below the inclusion of 'fch.asl'.
    
    Change-Id: Ie2efb7ebf8f5b527e26d7aaaeafbd3053a9a6b28
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5459
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 10b834374bbfaaeac5dbef21872c942da138f8b2
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Apr 13 16:45:12 2014 +1000

    cimx/sb800/cfg.c: Cut out purposeless ROM reading noise.
    
    Follow along hudson, cut out "SLP_TYP type was 0" excessively filling
    the buffer. We could make this conditional on non-zero?
    
    Change-Id: Iffd4c146b2ac4f57dbc3a011a683c92b6e132e39
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5495
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit b4417fb1390d627090ee1e838623ac73af1fc634
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Apr 6 23:57:57 2014 -0500

    hp/pavilion_m6_1035dx: Add basic EC initialization
    
    The EC is now set to ACPI mode, and properly generates SCIs on
    external events. This fixes the issue where battery notifications were
    not working.
    The keyboard matrix type is also explicitly set up.
    
    Change-Id: Ib6f0d23984d4ed1320340282469b8325c83547d1
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5471
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 99e2bf87ef9e91196bf19eaa9091c2a945352316
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Apr 6 02:53:49 2014 +1100

    cimx/sb800 boards: Don't require ide.asl on boards without IDE
    
    Not all boards which use the AMD cimx/sb800 southbridge have IDE.
    However, the southbridge's asl included an 'ide.asl' file which had to
    be present in $(mainboard_dir)/acpi.
    
    Address this issue by including ide.asl only in boards which have IDE,
    and remove it from all other cimx/sb800 boards.
    
    Change-Id: I57fcb4db9f85234b05ae1705ef81a576c478cee6
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5460
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0e3ca273151b9c13da7ae53923cb6387dd9d2cdf
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Apr 6 01:57:42 2014 +1100

    mainboard/*/acpi/ide.asl: Serialize ACPI methods to avoid races.
    
    Serialize methods against the construction of same (named) objects by
    competing threads. See ACPICA BZ 909 for further details.
    
    This change fixes issues that show up with the Ubuntu firmware test
    suite (fwts) ACPI table sanity checker.
    
    Change-Id: I49e3050a2a5aece6f031122b0211c056938d1a89
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5458
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 374251d9019ad0d99b8ea309e0e3eb2b55251a4c
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Mar 29 18:06:57 2014 -0500

    cpu/amd/agesa/s3_resume.c: Specify include paths from AGESA_ROOT
    
    Following the same reasoning as in commit
    * 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes
    include AGESA files with a path relative to AGESA_ROOT. We cannot
    with more than one generation of AGESA, hence the path being relative
    to AGESA_ROOT.
    
    Change-Id: If15c4cbfd42e0264264fdb3e8c426a47609ad41f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5426
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c21bd8839b68dbc46b11e50697b041ba2b20d59c
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Apr 12 04:12:14 2014 +1000

    jetway/nf81-t56n-lf: Replace AGESA types with stdint types
    
    Try to use void and uint*_t type specifiers in place of VOID and UINT*
    respectively. Use const in place of CONST type modifier. Remove some
    useless type casts.
    A few unneeded comments containing the AGESA redefenied types are also
    removed.
    
    Change-Id: I4bff96a222507fc35333488331c3f35ef1158132
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5486
    Tested-by: build bot (Jenkins)

commit e2f3bfc5b372227223c3ce869e2c82e1dffd469a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Apr 11 12:56:13 2014 +1000

    jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
    
    Replace usage of AGESA poor reinvention of memset/memcpy functions with
    the usual standard ones.
    
    Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5484
    Tested-by: build bot (Jenkins)

commit ac138976dfc15f3f6551bec806391700d909f3af
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Apr 5 19:26:56 2014 -0500

    hp/pavilion_m6_1035dx: Add ACPI support for lid switch
    
    This is sufficient to at least allow linux to recognize the lid switch
    and read its state correctly.
    
    Change-Id: Id5bd92466c72559f263c7ca8d23cbc741377a762
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5464
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 27bb6ad046c40b2c85649e0da0648376aa8a966e
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Apr 5 19:02:28 2014 -0500

    hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI
    
    Only the WLAN control pin and the lid switch input are declared, as
    those are the only pins whose function is known and tested.
    
    Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5463
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit f0504352b17a257776614c3b47fda12994134f68
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Mar 31 16:17:54 2014 -0500

    hp/pavilion_m6_1035dx: Add ACPI support for reading battery level
    
    Hook in the EC ASL code. This provides just enough information for the
    OS to be able to read the battery information.
    
    EC notifications (_Qxx) do not yet work, and it is unclear if the
    issue is in the ACPI code, or if the EC is not set up properly. Thus,
    the OS must boot with the battery inserted in order to be able to read
    its status.
    
    The _L03 ACPI method is also removed, as the EC SCI uses this event.
    
    Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5445
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 1a3872f7a48492b075ffa105a523cf133f651005
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Apr 1 16:02:08 2014 -0500

    ec/compal/ene932/acpi: Let mainboard define the ACPI lid object
    
    The GP15 ACPI object was used to get the state of the lid. However
    GP15 is specific to certain Intel chipsets, and will not always be in
    the ACPI namespace. Instead of hardcoding this object, let the
    mainboard define it.
    
    Also, document the ACPI interface for the EC.
    
    Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5444
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 5d41c1a7f9e3c4083856f6ae12605f752c32a249
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Apr 12 13:04:14 2014 +0200

    agesa: Always include family* Kconfig
    
    Otherwise we generate a recursive dependency because
    CPU_AMD_AGESA depends on the per-family configurations
    while those only exist if CPU_AMD_AGESA is selected.
    
    Change-Id: Ic08d517ff4ca8bb76afc1574b55c54b28ec3f1b0
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5490
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 4e6881f0ba917054405535ac922b9020a0eee4cd
Author: Martin Roth <gaumless@gmail.com>
Date:   Fri Apr 4 14:07:54 2014 -0600

    Add the Rangeley FSP include & srx directories
    
    These are the .h and .c files from Intel that support interaction
    with the FSP.  These have been modified from the FSP distribution
    only to strip trailing whitespace.
    
    Intel® Firmware Support Package for Intel® Atom™ Processor C2000
    Product Family (Formerly Rangeley)
    
    "Intel® Firmware Support Package (Intel® FSP) provides key
    programming information for initializing Intel® silicon and can be
    easily integrated into a boot loader of the developer’s choice.
    It is easy to adopt, scalable to design, reduces time-to-market, and
    is economical to build."
    
    http://www.intel.com/fsp
    
    Change-Id: I9ed94cb92909c3681cc88bf10b85a9ba25e8fc55
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/5457
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 954f3882f1ea8512de9a5a6a38569c36bffae405
Author: Martin Roth <gaumless@gmail.com>
Date:   Fri Apr 4 13:23:41 2014 -0600

    Add the Bay Trail FSP include & srx directories
    
    These are the .h and .c files from Intel that support interaction
    with the FSP.  These have been modified from the FSP distribution
    only to strip trailing whitespace.
    
    Intel® Atom™ processor E3800 product family (formerly Bay Trail)
    
    "Intel® Firmware Support Package (Intel® FSP) provides key
    programming information for initializing Intel® silicon and can be
    easily integrated into a boot loader of the developer’s choice.
    It is easy to adopt, scalable to design, reduces time-to-market, and
    is economical to build."
    
    http://www.intel.com/fsp
    
    Change-Id: I0fa64dbaf640493cdb5e670e8d213a49d9e7dcfb
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/5456
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit debd7657548ed7cdc67dcabe3f6e69b33093a43a
Author: Martin Roth <gaumless@gmail.com>
Date:   Fri Apr 4 13:53:07 2014 -0600

    Add the ivybridge i89xx FSP include & srx directories
    
    These are the .h and .c files from Intel that support interaction
    with the FSP.  These have been modified from the FSP distribution
    only to strip trailing whitespace.
    
    Intel® Firmware Support Package for Intel® Xeon® E3-1125C v2,
    E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™
    i3-3115C Processors for Communications Infrastructure with
    Intel® Communications Chipset 89xx Series Platform Controller Hub
    (formerly Crystal Forest Refresh: Ivy Bridge Gladden and Cave Creek
    
    "Intel® Firmware Support Package (Intel® FSP) provides key
    programming information for initializing Intel® silicon and can be
    easily integrated into a boot loader of the developer’s choice.
    It is easy to adopt, scalable to design, reduces time-to-market, and
    is economical to build."
    
    http://www.intel.com/fsp
    
    Change-Id: Ib76e89b2d2f6407cf55a5a664da989c7a7e0eb23
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/5455
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 18a40e05334b650d8104787416afd8ba87f03987
Author: Martin Roth <gaumless@gmail.com>
Date:   Fri Apr 4 11:59:48 2014 -0600

    Update vendorcode/intel/makefile for coming FSPs
    
    Other FSPs have more than just the initial fsphob.c source file.
    Add any .c files in the srx directory to the ramstage build.
    
    Change-Id: I5118bdcca44935b579809c4fc9566ab7914a6e4b
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Signed-off-by: Martin Roth <gaumless@gmail.com>
    Reviewed-on: http://review.coreboot.org/5454
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit eb4920df327fd7d3ac9e9f853768b15e9a02a9b1
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Apr 10 19:50:58 2014 +0200

    intel/*bd82x6x/acpi/pch.asl: Correct name of field unit to GP03
    
    GP0e does not fit into the naming scheme of the field units surrounding
    this field unit definition. Also the keys for e and 3 are close to each
    other supporting the theory that this is indeed a typo.
    
    Change-Id: I43cf288fe1e0240b33971073c1aa8a1db5762e31
    Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5483
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 6b583a454c24c0c8fb41da9eaef52a830e83b3e4
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Apr 6 15:19:56 2014 -0500

    vendorcode/amd/agesa: Do not hardcode ROM base address
    
    The ROM address range is set up in the LPC PCI device, register 0x6c.
    Coreboot already sets that up correctly in the bootblock, however
    AGESA overrides that to 0xffffff00, which will always map the ROM from
    0xff000000. This may conflict with other devices which are assigned
    address space in that range.
    
    If a device is assigned a range between 0xff000000 and the real ROM
    base, accesses to that device will be diverted to the system ROM,
    regardless of how other BARs are set up. Since we already need to set
    up the ROM address range in the bootblock, before calling AGESA, just
    remove the override from AGESA.
    
    Note that not all AGESA versions override this mapping.
    
    Change-Id: I592e5d087ed830c9604a04a356912c7654ce56d2
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5467
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 8395e90bc0a737f09ef5b5e2c94e37c66748b505
Author: Konstantin Aladyshev <aladyshev@nicevt.ru>
Date:   Sat Jul 12 02:36:32 2014 +0400

    supermicro/h8qgi/dsdt: Use PIC as default interrupt model
    
    According ACPI specification:
    
    """
    The \_PIC optional method is used to report to the BIOS the current
    interrupt model used by the OS. The argument passed into the method
    signifies the interrupt model OSPM has chosen, PIC mode, APIC mode,
    or SAPIC mode. Notice that calling this method is optional for OSPM.
    If the method is never called, the BIOS must assume PIC mode.
    
    Arguments: (1)
    Arg0 – An Integer containing a code for the current interrupt model:
    0 –PIC mode
    1 –APIC mode
    2 –SAPIC mode
    """
    
    In current configuration with default value of interrupt model
    PMOD equal 1 (APIC mode), Linux can't boot with "noapic" option.
    Kernel never call _PIC method and PMOD stays equal 1, indicatind
    that APIC routing objects should be evaluated. This mix of PIC
    and APIC leads to boot fail.
    
    Change default value of interrupt model PMOD to 0, for correct
    "noapic" boot.
    
    Change-Id: I7fa6f0c24802751202ed2e7f13411001a600e772
    Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/5473
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fe365ac7e8c01cff46c593e80ca20ae3cb3362e7
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Mar 16 17:24:18 2014 +1100

    mainboard/lenovo: [2/2] implement initial T530 support
    
    Step 2: change the Lenovo X230 code to adapt it to the new board's
    hardware with the great guidance from Vladimir (phcoder) to find the
    correct GPIO's.
    
    The machine has:
     - Chipset: Intel QM77
     - GPU's: Intel Integrated HD Graphics
            : Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology
    
    Change-Id: Iee12c3edc22df4a7935b7fb7ff4a320c21c4239b
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5391
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 956c29823328b37506fce7bfefe7e53e58706dd2
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Mar 16 17:09:58 2014 +1100

    mainboard/lenovo: [1/2] fork X230 to T530
    
    Step 1: copy all files unmodified from Lenovo X230.  This makes it much
    easier later to see how the two boards actually and deliberately differ
    when porting bugfixes from one to the other.
    
    Change-Id: I3151c7848440ea6c240b959379a8eb369d35f3de
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5390
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit a09dad0c77ff0365210f784b10d0516338a949b7
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Tue Mar 11 15:43:35 2014 +0000

    asus/f2a85-m: conditionally show POST codes
    
    Change-Id: I61e55601676c0825815d6520a874ccade8942379
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/5362
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1a25c9cdfd3fd391328133ba94c63ecd1083e4f8
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Feb 10 11:37:45 2014 -0800

    lynxpoint: Fix SerialIO ACPI compile issue with recent IASL
    
    The SerialIO DwordIo() definition is fixed up before returning
    it in the serialio device _CRS method, so the values that are set
    in the raw ASL are not actually used.
    
    However modern versions of IASL do not like that the RangeLength is
    set to zero and will fail to compile.  Set this value to 1 to make
    IASL stop complaining, but the real value is still fixed up in _CRS
    so this has no real effect on the end result.
    
    Change-Id: Iceb888e54dd4d627c12d078915108a11f45b1a2d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5182
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 69813febbc91571f9126f980b97fd7b37a45f125
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Mar 1 12:49:57 2014 +0100

    sb/amd/amd8111/acpi.c: Remove set but unused variable `dword`
    
    Removing `-Wno-unused-but-set-variable` from `CFLAGS` results in the error
    below, when building for example the HP DL145 GL1.
    
    	    CC         southbridge/amd/amd8111/acpi.ramstage.o
    	src/southbridge/amd/amd8111/acpi.c: In function 'acpi_init':
    	src/southbridge/amd/amd8111/acpi.c:100:11: error: variable 'dword' set but not used [-Werror=unused-but-set-variable]
    
    Removing the variable `dword` fixes this error.
    
    The read is left in the code, as I do not know if it has an effect or
    not.
    
    Change-Id: I9957cef3a996c5974c275423c9de63ccf230974e
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5315
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit dbc7bd9dce2d188dd48de7acd5754507ff0c87e5
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jan 28 11:34:38 2014 +0200

    console: Refactor uart8250/NE2K
    
    Do this for symmetry with romstage_console.c.
    
    Change-Id: If17acfc3da07b1dbefa87162c3c7168deb7b354a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5330
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 77f43e9b43894f6cdeaab29b2960796b1e3a219e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 4 19:50:07 2014 +0200

    console: Remove old fix for DEBUG_SMI
    
    No longer needed as wrap_putchar() survives SMM relocation to TSEG.
    
    Change-Id: I6143844b0b9902ef63baf3e5781a5dc4f54234be
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5335
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b04e0fff7da5547e2152dc8f6f23af247e9048ec
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 4 14:28:17 2014 +0200

    console: Simplify vtxprintf
    
    We do not need ROMCC support here and using wrappers for
    console_tx_byte we can simplify this code.
    
    Change-Id: I7f3b5acdfd0bde1d832b16418339dd5e232627e7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5334
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 657e0be46495bb54ddf5a0fbad786fe352c2847f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 4 19:03:57 2014 +0200

    console: Move newline translation outside console_tx_byte
    
    This gives us completely transparent low-level function to transmit
    data.
    
    Change-Id: I706791ff43d80a36a7252a4da0e6f3af92520db7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5336
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b3356bbff42148094ada671d3a0a803f195542e6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Mar 6 16:55:05 2014 +0200

    console: Add printk helper for ChromeOS
    
    Do not expose console_tx_flush() to ChromeOS as that function
    is part of lower-level implementation.
    
    Change-Id: I1e31662da88a60e83f8e5d307a4b53441c130aab
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5347
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 56ae13983bae2ba4214dd635c46afad7e7bc50c1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Feb 28 14:37:27 2014 +0200

    console: Hide global console_loglevel
    
    Change-Id: I7bdc468bc3f74516abb2c583bdb5b6d7555d987c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5333
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b2d25967142437a82da150d0134923e3fd783dbf
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jan 27 15:09:13 2014 +0200

    console: Unify do_printk()
    
    Change-Id: I6c50e47d9d2d0d1f42beee477e49b2a0054d1786
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5332
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 21333f96c78e6181c7a376538c48f3718b71d9ef
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Feb 14 10:04:31 2014 +0200

    console: Split console_init()
    
    Splitting the version prompt satisfies some requirements ROMCC
    sets for the order in which we include source files. Also GDB
    stub will need console hardware before entering main().
    
    Change-Id: Ibb445a2f8cfb440d9dd69cade5f0ea41fb606f50
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5331
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d53d96dddd1e8733b53519becda73288381d2396
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Feb 28 15:15:12 2014 +0200

    OxPCIe uart: Move under drivers/uart
    
    This driver is only a thin shell for uart8250mem and we could extend it
    with further compatible PCI IDs from other vendors/brands.
    
    Change-Id: Ic115b1baa0be0dbaa81e4a17a2e466019d3f4a67
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5329
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4c686f2106a33e7a452bec163c178724a0313616
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Feb 14 12:45:09 2014 +0200

    OxPCIe uart: Split PCI bridge control
    
    None of the PCI bridge management here is specific to the PCI UART
    device/function. Also the Kconfig variable defaults are not globally
    valid, fill samsung/lumpy with working values.
    
    Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5237
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit afa7b13b9355b3df3da7606d434cb8b450316ab9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Feb 13 17:16:22 2014 +0200

    uart: Redefine Kconfig options
    
    Option DRIVERS_UART builds with support for UART hardware.
    Option CONSOLE_SERIAL enables the console output for UART.
    
    Those x86 boards that do not have serial port on SuperIO should select
    NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration.
    
    Removes:
      CONSOLE_SERIAL_UART
      HAVE_UART_IO_MAPPED
      HAVE_UART_MEMORY_MAPPED
    
    Renames:
      CONSOLE_SERIAL8250     ->  DRIVERS_UART_8250IO
      CONSOLE_SERIAL8250MEM  ->  DRIVERS_UART_8250MEM
    
    Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5311
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit bbf6f3d384caf25efdfeca0fc5eaac13319a6a43
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Mar 15 01:32:55 2014 +0200

    console uart: Fill coreboot table entries
    
    Also fixes the reported baudrate to take get_option() into account.
    
    Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5310
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c2610a4a186c6e5a05f6518c2c7a734fde8f6cfd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Feb 24 20:51:30 2014 +0200

    uart: Prepare to support multiple base addresses
    
    Prepare low-level register access to take UART base address as a
    parameter. This is done to support a list of base addresses defined
    in the platform.
    
    Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5309
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit e5760af3980ea4c55afd7e759e8ca2a078a4a1dc
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Mar 30 18:53:12 2014 +0200

    cpu/amd/car: Use define MSR_MCFG_BASE rather than hardcoded value
    
    Change-Id: I0b40c9811115b204f1cae70546d236049c1b3d30
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5431
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 597cc45aa9fd89133c1e4d2f58df05dee9c45402
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Apr 7 14:59:42 2014 +1000

    jetway/nf81-t56n-lf: Simplify agesawrapper_amdinitcpuio()
    
    Follow same reasoning as:
    12fd779 hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio()
    Use coreboot variants for PCI and MSR access over AGESA's.
    
    Change-Id: Ic0d8bbd0faf6423605567564ad216b79e1331cc9
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5472
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit b1e63e42e7b5b7afb3ba51c87d055f9e82cceb24
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Apr 6 23:48:44 2014 -0500

    ec/compal/ene932/ec.h: Include stdint.h for definition of 'u8'
    
    Change-Id: I7ffa8e8f807e7d8a778eb80c12a0dc984bdb3f8b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5470
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 0b2fa34d316bd0035163aff7727cf764ef13b249
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Apr 5 18:51:33 2014 -0500

    hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
    
    Change-Id: I181da410490a92760ae1328a4286e805f5388886
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5462
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 05ba1bb6d45de0b1534cea2ac89d9bc2d275e7b0
Author: Konstantin Aladyshev <aladyshev@nicevt.ru>
Date:   Sat Jul 12 09:17:24 2014 +0400

    supermicro/h8qgi/dsdt: Move _PIC method to root scope
    
    _PIC method should be declared under root scope (\_PIC),
    otherwise Linux kernel doesn't use it.
    
    Change-Id: I29b6ca60191507ac8edf99fdf173617bd6446934
    Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/5478
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 12fd7791764314163e324cdf58a94ba14e97fc48
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Apr 6 17:10:31 2014 -0500

    hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio()
    
    TRIVIAL. Rather than using the AGESA functions for PCI and MSR access,
    use the coreboot variants, which are cleaner and more readable.
    
    Change-Id: I4f24820606900e16f0d159df019f4560f1592489
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5468
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit a0f9ece19c0998a3ecc859edb2f950cdeace47db
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Mar 9 00:05:18 2014 +1100

    util/cbfstool: Make cbfs_image_delete() NULL-tolerant.
    
    This fixes a double free crash that occurs when a call to
    cbfs_image_from_file() fails in cbfs_extract() and falls though to
    cbfs_image_delete() with a NULL-pointer.
    
    To reproduce the crash pass the following arguments where the files
    passed, in fact, do not exist. As follows:
    ./cbfstool build/coreboot.rom extract -n config -f /tmp/config.txt
    
    Change-Id: I2213ff175d0703705a0ec10271b30bb26b6f8d0a
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5353
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 7c1a49bcc0520de45ae57054baa86cfd56474c46
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Tue Apr 1 22:47:33 2014 +0000

    SeaBIOS: have coreboot pass the choice to run optionroms in parallel
    
    Introduce the tunable CONFIG_SEABIOS_THREAD_OPTIONROMS.
    
    Change-Id: Ifd4d9fca7316eb739ff184e54bdc1cdb0262f0c6
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/5443
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 011341d126fe1c97e8e817c718c2c827624d16b7
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Apr 5 11:11:14 2014 -0500

    hp/pavilion_m6_1035dx: Remove inexistent devices from devicetree
    
    This removes ominous "PCI: xx:xx.x not found" messages from coreboot
    console.
    
    Change-Id: I13a6f2497c04464e8dd0c4c5e7f40a1582f7f26c
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5461
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit fa02e16c7651a453702192e5a4c8f47f3d372b94
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Sat Mar 29 13:13:10 2014 +0100

    asus/f2a85-m: Sanitize #includes
    
    Based on the same reasoning as this commit:
    1d87dac hp/pavilion_m6_1035dx: Sanitize #includes
    
    Change-Id: I383f79b5392ee1ca244e403f755213fa7b32c0af
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/5420
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 6181e3dcd7202b2460aad91237f314b8dacf686a
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Dec 7 22:29:36 2013 +0100

    amd/agesa/hudson: Implement PNP resource setup in LPC bridge
    
    The previous SBxxx generations were setting up LPC bridge based
    on the PNP resources. Implement it also for AGESA Hudson.
    The AGESA itself opens one big region DFLT_SIO_PME_BASE_ADDRESS
    (512 bytes). Make the code smart enough to detect already used
    region and if any resource fits into AGESA defined region, do nothing.
    
    Change-Id: I718d034bc4c778697a7bd0506d4550c8f5a43159
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/4497
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4f5a5254c5ad0aa0227113c3fd31b12c0783c131
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Apr 3 14:40:24 2014 +1100

    superio/winbond/w83627thg: Avoid .c includes
    
    Following the same reasoning as commit
    d304331 superio/fintek/f81865f: Avoid .c includes
    Clean up the early_serial #include directives in mainboard/romstage
    code.
    
    Change-Id: I1f7c20ac7841874125b6bfcd9f9db25d96355881
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5449
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 5ff4b086ba1c1ff1e82ef5b7db1e776aeff3fcb7
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Mar 29 17:54:26 2014 +1100

    jetway/nf81-t56n-lf: Sanitize #includes
    
    Following the same reasoning as commit
    1d87dac hp/pavilion_m6_1035dx: Sanitize #includes
    Clean up the #include directives in this board support.
    
    Change-Id: I97b73a349ca7e49b413d7c04900f25076488dde4
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5414
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 3c04917a0023d383a06ed0d4215d7d50e7798059
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Apr 3 03:19:41 2014 +1100

    superio/nuvoton/nct5104d: Avoid .c includes
    
    Following the same reasoning as commit
    d304331 superio/fintek/f81865f: Avoid .c includes
    Clean up the early_serial #include directives in mainboard/romstage
    code.
    
    Change-Id: I14c438968bfed917977862efd8a393ec48cb04c9
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5446
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 793a429eb57d105ca7bdf8c25cb1066678c2721d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Apr 3 14:30:58 2014 +1100

    superio/winbond/w83627ehg: Avoid .c includes
    
    Following the same reasoning as commit
    d304331 superio/fintek/f81865f: Avoid .c includes
    Clean up the early_serial #include directives in mainboard/romstage
    code.
    
    Change-Id: Ib3a12fb8160729008bdaa8026365675a11325da0
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5448
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 59674d25be5b5090e01cae7000c2065d1a0c5abd
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 5 17:25:22 2014 -0600

    chromeos: fix build breakage when !CHROMEOS_RAMOOPS
    
    Needed types were being guarded by CONFIG_CHROMEOS_RAMOOPS.
    Expose those unconditionally.
    
    BUG=None
    BRANCH=None
    TEST=None
    
    Change-Id: Ie858c746307ad3669eab5c35bf219e1a58da2382
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/188714
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5453
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit eb3c9913dc3d010e9459054e2ce2cd6a93e22a21
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Mar 29 13:01:11 2014 -0500

    x86/Makefile: Allow addition of link libraries for rom/ramstage
    
    This is useful, for example, when using stage-independent code, as it
    allows us to compile that code only once. It's also useful for vendor
    code which needs wonky compiler definitions and include paths which
    we'd rather not include in the other files.
    
    Subsequent patches will make use of this when lib-izing AGESA.
    
    Change-Id: Ifb0c5d353bf09d23864270b9eefb6b75fd86e6cb
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5425
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 1d87dac4e478608a2605b3e983128d32df8526f3
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Mar 28 14:48:13 2014 -0500

    hp/pavilion_m6_1035dx: Sanitize #includes
    
    There were a number of things wrong with the includes. First, The
    includes did not use paths to AGESA files, thus relying on the
    compiler include paths to find the correct file. This made it unclear
    where the file included was located, and whether it was local, under
    vendorcode, or under a different directory. Instead, use full paths
    for each non-local include.
    
    Second, the local includes were mixed with the rest, making it unclear
    which file is local and which one is not. Keep the local includes at
    the top. This also prevents us from polluting the namespace of local
    headers, with library definitions, and allows us to catch if we missed
    an otherwise needed external header.
    
    Thirdly, alphabetize the order of includes where possible.
    
    Change-Id: I22c543291beabb83c16d912ea0a490be6ca4e03c
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5412
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit cb3ba5fdbc5cc9bd02b4aacf569cb455c34b81bc
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Mar 31 00:09:23 2014 +0300

    lenovo/x60: Remove duplicate console_init()
    
    For romstage, console_init() was called twice. The one in dock_connect()
    should have done only UART programming and not touch CBMEM console and/or
    USBDEBUG when those are enabled.
    
    Second case where dock_connect() is called is in SMI handler.
    If DEBUG_SMI is not enabled, console_init() does nothing in SMM.
    If DEBUG_SMI is enabled, console_init() is already called every time when
    enterining SMM.
    
    Change-Id: Ib3a842442cb7a5be9d6b71682cd6f368930af886
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5433
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit c814be415839920b11277db1f2c2754d8ed27887
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Mar 30 22:28:26 2014 +1100

    amd/agesa/s3_resume: Make compiler agnostic.
    
    Clang does not like inline functions defined in C files with prototypes
    in headers. Rather Clang expects inline function bodies to be in headers
    if they are to be used out of scope. Since inline is purely advisory to
    the compiler, drop its usage here.
    
    Change-Id: I08a7a3d2cdf841ffbab10c017c75917768aac209
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5429
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit ab180d85f76e8e8cc68ead2f0c89f29b9fe5fd53
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Mar 31 11:59:58 2014 -0500

    util/cbmem: handle larger than 1MiB mappings for console
    
    In some cases the cbmem console can be larger than the default
    mapping size of 1MiB. Therefore, add the ability to do a mapping
    that is larger than the default mapping using map_memory_size().
    The console printing code will unconditionally map the console based
    on the size it finds in the cbmem entry.
    
    Change-Id: I016420576b9523ce81195160ae86ad16952b761c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5440
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit a270586d4b077149ab1eb1823ccb17c90f840ec7
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Mar 29 20:42:58 2014 +1100

    superio/fintek/f71859: Avoid .c includes
    
    Following the same reasoning as commit
    d304331 superio/fintek/f81865f: Avoid .c includes
    Clean up the early_serial #include directives in mainboard/romstage code.
    
    Change-Id: I3577ca3f761fb699dc51141a02e1f853bf1f1a21
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5417
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit b5a49ad9d782698f1a845953729eb489456d803d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Mar 31 15:14:14 2014 +1100

    superio/fintek/f71889: Avoid .c includes
    
    Following the same reasoning as commit
    d304331 superio/fintek/f81865f: Avoid .c includes
    Clean up the early_serial #include directives in mainboard/romstage code.
    
    Change-Id: Id8a1a2e8c87add636af1506598c2669d72dc3238
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5437
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 880e5248dc625f00fe3bc83d13b88730020d577a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Mar 31 15:13:07 2014 +1100

    superio/fintek/f71872: Avoid .c includes
    
    Following the same reasoning as commit
    d304331 superio/fintek/f81865f: Avoid .c includes
    Clean up the early_serial #include directives in mainboard/romstage code.
    
    Change-Id: Ia021229154dc90b830a314f3adc2a0dd444bd68d
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5436
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit ade70a0482fa4ed36d8d2d75f190876ccd7cbad5
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Mar 31 15:08:35 2014 +1100

    superio/fintek/f71863fg: Avoid .c includes
    
    Following the same reasoning as commit
    d304331 superio/fintek/f81865f: Avoid .c includes
    Clean up the early_serial #include directives in mainboard/romstage code.
    
    Change-Id: I863c16634873224c17e43100271e9b91419724d0
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5435
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit fbdc3ef7d9df3b68efafffa1c2d50352d25dfb60
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Mar 31 15:01:16 2014 +1100

    superio/fintek/f71805f: Avoid .c includes
    
    Following the same reasoning as commit
    d304331 superio/fintek/f81865f: Avoid .c includes
    Clean up the early_serial #include directives in mainboard/romstage code.
    
    Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5434
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 905bfb05dc3f6063c396d4665cc95dcde91a8ced
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 28 08:40:59 2014 -0500

    x86: use car_(get|set)_var accessors for apic timer
    
    The timer_fsb variable was not correctly being accessed in the
    presence of cache-as-ram. The cache-as-ram backing store could
    be torn down but then udelay() could be called causing hangs from
    accessing variables that have unknown values.
    
    Instead change the timer_fsb variable to g_timer_fsb and obtain
    the value through a local access method that does the correct things
    to obtain the correct value.
    
    Change-Id: Ia3e30808498cbe4a7f6f116c17a8cf1240a807a3
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5411
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit deb2cb27e9bade18c4d186899edfaeabfc1131bd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Mar 28 23:46:45 2014 +0200

    Static CBMEM / CAR: Flag boards with BROKEN_CAR_MIGRATE
    
    Use of CAR_GLOBAL is not safe after CAR is torn down, unless the
    board properly implements EARLY_CBMEM_INIT.
    
    Flag vulnerable boards that only do cbmem_recovery() in romstage on S3
    resume and implementation with Intel FSP that invalidates cache before
    we have a chance to copy the contents.
    
    Change-Id: Iecd10dee9b73ab3f1f66826950fa0945675ff39f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5419
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 0ec3f493a332a7e779600406732141573fafd526
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Mar 30 18:55:05 2014 +0200

    git-ignore site-local
    
    It's _local_
    
    Change-Id: I5624e240ffe486763b25b14b218e69362c488f50
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/5432
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit d3043313a91dff3bc2f879ffb3b4bf23a364d711
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Mar 29 20:28:03 2014 +1100

    superio/fintek/f81865f: Avoid .c includes
    
    We should not be #include .c files, instead link early_serial into
    romstage and provide a prototype.
    
    Change-Id: Ia9277169ce1592e1fc72f8849f0982741daec567
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5416
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 01c44000bedc571b10bdae7d0acfba079a131e42
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Dec 28 15:10:28 2013 -0500

    cubieboard: Enable the SD controller and mux SD pins
    
    This step needs to be done before calling any MMC functionality.
    
    Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4745
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit fccfee3bce901dfe78af8c36656f09973c2f3846
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Mar 26 18:51:08 2014 -0500

    mainboard/hp: Add initial support for Pavilion m6-1035dx
    
    This was a pathetically easy port, where all the components are
    already supported. This is basically a verbatim copy of amd/parmer.
    The EC is an ENE KB932, which is a part that does surprisingly little
    for an EC. This also means we need almost no code to get it working.
    I've "select"ed the EC in Kconfig, which is the only difference from
    parmer, although the keyboard worked fine without it.
    
    I haven't coupled in the ACPI code from the EC yet, so battery level
    is not readable from the OS. Hotkeys work except for brightness
    control, and the CapsLock LED blinks at regular intervals instead of
    following the CapsLock key.
    
    Change-Id: Idfec6f848b99a52e73eac22d516f3550477ad822
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5409
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 35a4901d3a90813514994d709cd473b4a58aa9ef
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Mar 23 00:09:32 2014 +0100

    mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h`
    
    It's not needed and causes build failures without CONFIG_CHROMEOS.
    
    Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd
    Reported-by: Idwer Vollering <vidwer@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5398
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 4f3bb801edffb27e7e52c297cf6cf5dc4ad22a95
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 26 22:57:55 2014 -0500

    cbfstool: provide structure to linux payload builder
    
    This change started with tracking down a bug where the trampoline
    size was not being taken into account for sizing the output buffer
    leading to a heap corruption.  I was having a hard time keeping
    track of what num_segments actually tracked as well as what parts
    were being placed in the output buffer. Here's my attempt at
    hopefully providing more clarity.
    
    This change doesn't crash when adding a bzImage:
    $ dd if=/dev/zero of=bb.bin bs=64 count=1
    $ ./cbfstool tmp.rom create -s 4M -B bb.bin -m x86 -a 64
    $ ./cbfstool tmp.rom add-payload -f ~/Downloads/bzImage -C "1" -n
    "fallback"/payload
    
    Change-Id: Ib1de1ddfec3c7102facffc5815c52b340fcdc628
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5408
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 2164831671aab4181bc7ba1d57237c4f782864e8
Author: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde@gmail.com>
Date:   Wed Mar 12 11:19:31 2014 +0100

    util/superiotool: Add initial support for Fintek F71869ED.
    
    Datasheet: http://www.fintek.com.tw/files/productfiles/F71869_V1.1.pdf
    Practically the same as F71869AD, just another ID (0x1408).
    Tested on actual hardware, Jetway NC9C-550-LF.
    
    Update:
    Fixed F71869ED based on the proper datasheet:
    http://www.alldatasheet.com/datasheet-pdf/pdf/459075/FINTEK/F71869ED.html
    
    Change-Id: I5da858565ca16ba4d73b47b42fadd31dabbc290b
    Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde@gmail.com>
    Reviewed-on: http://review.coreboot.org/5380
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 024822f26d1f5d7cda64d42cd181c6fd8745ff7f
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Mar 25 19:23:00 2014 +1100

    mainboard/jetway/nf81-t56n-lf: Enable ACPI S3 support in Kconfig
    
    Switch on ACPI suspend/resume support which now works after many cycles.
    
    Change-Id: I94a9bc9f23c2b4482d940018d542ab89e6c76f09
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5406
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ffdf2e1acfb85326a9dbe4de1f455c9275569b99
Author: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde@gmail.com>
Date:   Mon Mar 24 10:02:42 2014 +0100

    util/superiotool: Register fix for Fintek F71869AD
    
    Fixed F71869AD based on the proper datasheet:
    http://www.alldatasheet.com/datasheet-pdf/pdf/459074/FINTEK/F71869AD.html
    
    Change-Id: If22341551c6a1a9bbae088801a6194f7b5b6bf4d
    Signed-off-by: Wilbert Duijvenvoorde <w.a.n.duijvenvoorde@gmail.com>
    Reviewed-on: http://review.coreboot.org/5405
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 1547ef23624fe3748ba8aa1130e48fdf6bc1207b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Mar 23 20:42:02 2014 +1100

    mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cb
    
    Change-Id: Ia58994d14ebf488a9200b02ec7af9c71ef4de9e6
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5401
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 3eb8eb7eba55cdfd64c8d50181ea066526ff6485
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Mar 10 16:13:58 2014 -0500

    rmodules: use rmodtool to create rmodules
    
    Start using the rmodtool for generating rmodules.
    rmodule_link() has been changed to create 2 rules:
    one for the passed in <name>, the other for creating
    <name>.rmod which is an ELF file in the format of
    an rmodule.
    
    Since the header is not compiled and linked together
    with an rmodule there needs to be a way of marking
    which symbol is the entry point. __rmodule_entry is
    the symbol used for knowing the entry point. There
    was a little churn in SMM modules to ensure an
    rmodule entry point symbol takes a single argument.
    
    Change-Id: Ie452ed866f6596bf13f137f5b832faa39f48d26e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5379
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 4fde5a66b4a2b4117a45519ab0f63a9fd6bff835
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 7 15:11:53 2014 -0600

    util: add rmodtool for parsing ELF files to rmodules
    
    The current implementation of creating rmodules relies
    on invoking the linker in a certain manner with the
    relocations overlaid on the BSS section. It's not really
    surprising that the linker doesn't always behave the way
    one wants depending on the linker used and the architecture.
    Instead, introduce rmodtool which takes an ELF file as an
    input, parses it, and creates a new ELF file in the format
    the rmodule loader expects.
    
    Change-Id: I31ac2d327d450ef841c3a7d9740b787278382bef
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5378
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 36be8135d74964fa2eb03af44079d845c199486b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 11 11:48:56 2014 -0500

    cbfstool: add ELF writing support
    
    In order to generate rmodules in the format of ELF files
    there needs to be support for writing out ELF files. The
    ELF writer is fairly simple. It accpets sections that can
    be associated with an optional buffer (file data). For each
    section flagged with SHF_ALLOC a PT_LOAD segment is generated.
    There isn't smart merging of the sections into a single PT_LOAD
    segment.
    
    Change-Id: I4d1a11f2e65be2369fb3f8bff350cbb28e14c89d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5377
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8089f1780635daae24ded0ac7fb9dc2d2f2a01bb
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Mar 16 20:42:40 2014 +1100

    mainboard/lenovo/x230 Fix usage of GNU field designator extension
    
    In C99 we defined a syntax for this. GCC's old syntax was deprecated.
    
    Change-Id: If8c53b5370be9101b9e5f2dfa88a6229f500a0f6
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5392
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 38608937b658ae2031b78d274463f3d8712fd95b
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Feb 20 19:37:42 2014 +1100

    romcc.c: Fixes warning about unused function from unused macros.
    
    GCC suppresses warnings about unused static functions if they are
    inline, however Clang only does this for header files. None of these
    MASK_ declarations are used, so just remove them.
    
    Change-Id: Ia230beba3f6367237838d9b3d90536459e1d52cb
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5273
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 5809a7395d49122757a0ebdfa120e023ebe876ba
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Tue Mar 11 15:36:21 2014 +0000

    Make POST device configurable.
    
    Change-Id: If92b50ab3888518228d2d3b76f5c50c4aef968dd
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/4561
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit c078094f39d8683b9a1087dc7f60e8605733ed99
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 5 16:41:27 2014 -0600

    cbfstool: add symbol table parsing to the ELF parser
    
    Optionally parse the symbol table contained within an ELF
    file. It currently assumes there is only one symbol table present,
    and it errors out if more than one is found.
    
    Change-Id: I4ac4ad03184a319562576d8ab24fa620e701672a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5376
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit c3e6e14a1227421c3e520a2a62f279bc4408ee3a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 5 14:33:42 2014 -0600

    cbfstool: add string table parsing to ELF parser
    
    Optionally parse the string tables within an ELF file.
    
    Change-Id: I89f9da50b4fcf1fed7ac44f00c60b495c35555ef
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5375
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit ccb5ad8d3c8eeb992c2ede12c24c5fabc36aad95
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 5 13:57:30 2014 -0600

    cbfstool: add relocation parsing to ELF parser
    
    Optionally parse the relocation entries found within an ELF
    file.
    
    Change-Id: I343647f104901eb8a6a997ddf44aa5d36c31b44b
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5374
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit d0f61659238c3ed79fecf841c58cabedbf936ac8
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 5 13:09:55 2014 -0600

    cbfstool: introduce struct parsed_elf and parse_elf()
    
    In order to make the ELF parsing more flexible introduce
    a parse_elf() function which takes a struct parsed_elf
    parameter. In addition take a flags parameter which instructs
    the ELF parser as to what data within the ELF file should be
    parsed.
    
    Change-Id: I3e30e84bf8043c3df96a6ab56cd077eef2632173
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5373
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 19a11d6fe9593e585aff8a5787d25e38faa3d88c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Mar 13 08:52:17 2014 -0500

    cbfstool: remove incorrect section size check
    
    I was overzealous in checking the section size with respect
    to the file size. That check makes no sense as the section only
    deals with link sizes -- not on-disk sizes. Remove the check as
    it doesn't make any sense.
    
    Change-Id: I348e7847ae3a50badc22693439614f813462445a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5384
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit ed2bcaa7310840073ac20f2087bd786d5874bd81
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Mar 13 03:33:35 2014 +1100

    mainboard/jetway/nf81-t56n-lf: Fix HWM base addr.
    
    The target board has a different base addr. for its hardware
    monitor (fans, temp, etc) from the Fintek Super I/O datasheet.
    
    Change-Id: Ifc025cb92d0fc4e8f813091d00a6c87deae05863
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5383
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 236cf4751345da3748cfcaa9f8c8a73889415ab3
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Mar 13 01:08:31 2014 +1100

    mainboard/jetway/nf81-t56n-lf: Remove hard-coded IMC fan craft.
    
    Fan controls in 0x400-0x4ff are not programmed here. Thus fan
    control from amd/persimmon in the devicetree.cb does not apply
    to this board.
    
    Change-Id: I9156143476df0a7b44c7af90fa2107e8a8ba851e
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5381
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit a31ff73e8de60ca6ac61a724f8c7649a1034176f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 7 15:23:05 2014 -0600

    cbfstool: elfparsing: check segment and section regions
    
    While parsing the section and program headers ensure the
    locations of their contents are within the elf file proper.
    
    Change-Id: I856f7de45f82ac15977abc06e51bedb51c58dde1
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5372
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit b1b5118c717d673506292dced272a0837612fc17
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 5 14:54:13 2014 -0600

    cbfstool: elfheaders: use proper parameters to calloc()
    
    Though the result doesn't matter much, the callers of calloc()
    should order the parameters correctly. i.e. the first paramter
    is the number of elements in an array and the second is the
    size of each element.
    
    Change-Id: Ic7c2910d623d96f380feb4e5f6fa432376f49e9b
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5371
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 54ef306377024bea83ffe0622c9a53ab4f4f5ec1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 5 12:12:09 2014 -0600

    cbfstool: add eflparsing.h
    
    elfparsing.h serves as the header to working with the elf
    parser. Additionally, only include what is needed by the other
    files. Many had no reason to be including elf.h aside from fixing
    compilation problems when including cbfs.h.
    
    Change-Id: I9eb5f09f3122aa18beeca52d2e4dc2102d70fb9d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5370
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit aa8784c2d140c373b6edaf20192a9ed0669f0956
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 5 12:01:36 2014 -0600

    cbfstool: move iself() to eflheaders.c
    
    The only user of iself() was in elfheaders.c. Move it there,
    and make it local to the compilation unit.
    
    Change-Id: I0d919ce372f6e2fce75885fb4fcba20d985979b3
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5369
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit a983cea5b99686b9281893b980d701dd2f1bf35e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 4 22:08:05 2014 -0600

    cbfstool: elfheaders: use common checks and buffer helpers
    
    The elfheaders code was manipulating struct buffers. Use
    the introduced buffer helper functions. Additionally fix
    up offset and size checks for the program headers and section
    headers by using common code paths.
    
    Change-Id: I279c77f77aaa1860a0be43fb111df890dd1d84d5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5368
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 0c54bfa0eeda1a84540e95e7dd5c3b4d8b7b5e6e
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Feb 9 14:50:50 2014 -0600

    Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs"
    
    This reverts commit b845636ce67f6e7c96bf3fb3008738f596a5d5ce.
    This commit changed the board status script to describe all boards in
    terms of x86 terminology, such as CPU->southbridge->northbridge.
    
    This terminology does not apply to a number of SoCs, in which the
    buses are not connected via successive bridges, and as such it is
    misleading and misguided to describe ideas of southbridge and
    northbridge for these devices.
    
    Change-Id: I98ba24ee00b816bf20d507c6d313ec2946acaedf
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5177
    Tested-by: build bot (Jenkins)

commit b34739b4b05cc87258097e0fbf3db1f7c93ec16c
Author: Chris Douglass <cdouglass.orion@gmail.com>
Date:   Fri Feb 14 13:51:26 2014 -0500

    drivers/spi: Add support for adesto SPI flash parts
    
    Adds support for the following Adesto Technologies
    SPI Flash parts.
    
    AT25DF081
    AT25DF321
    AT25DF641
    
    It has been tested on an Orion VPX7654 board populated
    with an AT25DF321A part. The "08" and "64" densities have not
    been tested.
    
    These parts are the successors of the Atmel AT26DF line that
    was spun out or purchased by Adesto.
    
    In this patch, adesto.c is identical to winbond.c with part
    entries for the Adesto parts. The datasheet for the AT25DF parts
    includes a "100MHz" programming command in addition to the "85MHz"
    command that is currently used but this patch does not add support
    for that enhanced programming mode.
    
    Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439
    Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
    Reviewed-on: http://review.coreboot.org/5225
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 06ece7de93a6e0820fa21a86d2312c6fd9209aea
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 14 00:30:04 2014 -0600

    chromeos: provide option to dynamically allocate ram oops buffer
    
    Fixing the location of the ram oops buffer can lead to certain
    kernel and boot loaders being confused when there is a ram
    reservation low in the address space. Alternatively provide
    a mechanism to allocate the ram oops buffer in cbmem. As cbmem
    is usually high in the address space it avoids low reservation
    confusion.
    
    The patch uncondtionally provides a GOOG9999 ACPI device with
    a single memory resource describing the memory region used for
    the ramoops region.
    
    BUG=None
    BRANCH=baytrail,haswell
    TEST=Built and booted with and w/o dynamic ram oops. With
         the corresponding kernel change things behave correctly.
    
    Change-Id: Ide2bb4434768c9f9b90e125adae4324cb1d2d073
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5257
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e7e78d61a96072ba619f95eba9762a0ca50abe15
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sun Nov 3 19:38:12 2013 -0800

    baytrail: Reserve memory between ASEG and 1MB and for ramoops
    
    Low system tables are in this region, and it is probably safer
    to keep ASEG reserved.
    
    Also keep the region used by ramoops from being used by the OS
    and from being cleared by developer mode boots.
    
    Lots more work needed to make the ACPI tables fully functional.
    
    BUG=chrome-os-partner:23505
    BRANCH=rambi
    TEST=boot on rambi and see that the kernel finds RSDP and uses ACPI
    
    Change-Id: I4f7064d3cff14a3ecf15b194a1f20c1fa9d5e134
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175554
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4932
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 714b1e8b6ca00f43f920e7a3f3db8f039356ce50
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Nov 1 13:35:32 2013 -0700

    rambi: Enable USB boot with EHCI controller
    
    This adds the EHCI driver back to libpayload and configures
    the devicetree to route ports to EHCI.
    
    This is hopefully just temporary until the issues with XHCI
    can be worked out.
    
    BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=build and boot from USB on rambi
    
    Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175513
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4931
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 3c9f17462a618d4fc848fac852a0f2bfca50c8d3
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Nov 1 13:34:00 2013 -0700

    baytrail: Add EHCI initialization
    
    This adds required steps to initialize the EHCI controller
    on the baytrail platform.
    
    BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=build and boot from USB on rambi
    
    Change-Id: I3a5487791e2305616036d4550e260a178c0e1c4d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175512
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4930
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit f81a91a768f54ef25aa6019fb40d3b98a3cb18c2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Nov 1 13:32:53 2013 -0700

    baytrail: Add XHCI initialization
    
    This adds required steps to initialize the XHCI controller
    on the baytrail platform.
    
    Actually using XHCI is causing lots of bad behavior including
    apparent memory corruption.
    
    BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=build and boot on rambi
    
    Change-Id: Ic43e04f4b47e107ec3bb0c387a9fc72c3cae0271
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175511
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4929
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 97651c55a3058bfedacdeb6de6243087d1dc5b7a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Nov 1 14:36:03 2013 -0500

    baytrail: add audio clock workaround for LPE
    
    Apparently the LPE device needs a 25MHz clock. Provide
    the work around to enable this clock.
    
    BUG=chrome-os-partner:23791
    BRANCH=None
    TEST=Built and booted. Confirmed setting being applied.
    
    Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175493
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4928
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 65ad521f8a19ec42c1bafa6777eb927fa55261a2
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Nov 1 14:19:24 2013 -0500

    baytrail: add ccu iosf access functions
    
    The clock control unit needs to be accessed to configure
    some of the devices properly. Therefore. provide a way
    to access the CCU.
    
    BUG=chrome-os-partner:23791
    BRANCH=None
    TEST=Built.
    
    Change-Id: I30ed06e6aef81ee99c6d7ab3cbe8f83818b8dee5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175492
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4927
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 46ab8cdc680cdafe37532b9ee15d38efa4912c98
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Oct 30 17:07:46 2013 -0500

    baytrail: HDA function disable workaround
    
    Parts of the audio path are common between the HDA and LPE.
    However, those parts are power-controlled by the D-state of
    the HDA device. Therefore, one cannot put the HDA into D3Hot
    because those audio paths will be shutdown.
    
    BUG=chrome-os-partner:22871
    BRANCH=None
    TEST=Built and booted through depthcharge. Disabling HDA still
         causes a shutdown when performing warm reset, however I
         was able to verify the magic sequence was being performed.
    
    Change-Id: I3b01356d85a4b7b902bd896b8eb9e7bc509fcc42
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175491
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4926
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 1eae3eed293b0e781efec68840eb80749baa5ede
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Oct 30 17:08:59 2013 -0500

    baytrail: allow function disable on TXE
    
    Previously it was not known how to put the TXE pci device
    into D3Hot. It's been disseminated that this is not a requirement
    for disabling the TXE pci device in the function disable register.
    Therefore, allow this by returning 0 from place_device_in_d3hot().
    
    BUG=chrome-os-partner:22871
    BRANCH=None
    TEST=Temporarily set TXE to be disabled. Noted FUNC_DIS was being
         set accordingly.
    
    Change-Id: Ibf537bf8ba718859591dc89bdf41e57c1ea9d836
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175490
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4925
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 223d4a4ff67ab6212c2dced57b29a078ba82375b
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Oct 31 08:27:29 2013 -0700

    baytrail: Switch graphics init to use reg_script
    
    This is an example consumer of the register script handler.
    
    BUG=chrome-os-partner:23507
    BRANCH=rambi
    TEST=build and boot on rambi and see recovery screen
    
    Change-Id: I4954a5defd0a345b179819b9f6bb15ea340a6715
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175214
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4924
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 6e8c2790bbc9190cf8b7ff83787b5328a2b8828e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 4 22:01:12 2014 -0600

    cbfstool: add struct buffer helper routines
    
    There are some open-coded manipulation of the struct buffer
    innards in the elf parsing code. Add helper functions to avoid
    reaching into the struct itself.
    
    Change-Id: I0d5300afa1a3549f87f588f976184e880d071682
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5367
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1240d29209c1e1bac556113485a894f6ef4ae0af
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Mar 10 14:13:27 2014 -0500

    cbfstool: add bputs() to store a byte stream to a buffer
    
    There was already a bgets() function which operates on a buffer to
    copy a byte stream. Provide bputs() to store a byte stream to a
    buffer, thus making the API symmetrical.
    
    Change-Id: I6166f6b68eacb822da38c9da61a3e44f4c67136d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5366
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 01650045f471bbe7ca1ca36868c82a47df8decd3
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 5 16:38:26 2014 -0600

    cbfstool: add get8/put8 variants to xdr structures
    
    In order to provide consistent usage provide the get8()
    and put8() callbacks to xdr operations. That way no futzing
    needs to be done to handle 8-bit reads and writes.
    
    Change-Id: I1233d25df67134dc5c3bbd1a84206be77f0da417
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5365
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fae75172d1976edb4a7f375d221a2042ec286b0c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 5 15:02:21 2014 -0600

    cbfstool: move verbose to common.c
    
    In order for multiple tools to use the common code found
    in common.c place the verbose variable within common.c's
    compilation unit.
    
    Change-Id: I71660a5fd4d186ddee81b0da8b57ce2abddf178a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5364
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4e6ad1bcaf63b746236d56dec39ff8ac3348c7be
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Mar 10 09:53:34 2014 -0500

    rmodule: allow rmodule header structure to be used by userland
    
    In order for userland to create rmodules the common code should be
    shareable.  Therefore, convert the short u<width> name types to the
    posix uint<width>_t types. Additionally, move the definition of the
    header structure to a new rmodule-defs.h header file so that userland
    can include that without pulling in the coreboot state.
    
    Change-Id: I54acd3bfd8c207b9efd50a3b6d89efd5fcbfc1d9
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5363
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 62a3f6f6656012c6c0bc4f95f8773fc9c1811cd5
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Mon Dec 2 10:39:44 2013 +0800

    AMD Olive Hill: add IMC fan control
    
    There are 3 steps to enable the IMC fan control:
    1. Enable fan control related registers on Hudson using oem_fan_control().
    2. Set EcStruct.
    3. Enable thermal zone using enable_imc_thermal_zone().
    I have tested on Olive Hill.
    
    Change-Id: I1748e8c92fb72a82bac0506ecdf98304a5bd8239
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/4301
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit d5813530fa4d6d217c3e797ee4042a4b841da72c
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Mon Dec 2 10:48:26 2013 +0800

    AMD Parmer: add IMC fan control
    
    There are 3 steps to enable the IMC fan control:
    1. Enable fan control related registers on Hudson using oem_fan_control().
    2. Set EcStruct.
    3. Enable thermal zone using enable_imc_thermal_zone().
    I have tested on Parmer.
    
    Change-Id: Id11d5c5da30346c034d155a73749e7f4c9c980eb
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/4302
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 7841ece730ea42e9c432fad788b8c35f8ff716e2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Mar 9 13:46:48 2014 +0200

    CBMEM console: Fix build for ARM
    
    This preprocessor guard was used to disable CBMEM console from
    romstage of ROMCC boards. It unintentionally disabled it for ARM
    too as they do not have CACHE_AS_RAM selected.
    
    Option EARLY_CBMEM_INIT implies CAR migration which is required
    to have CBMEM console in romstage. This change should have been
    done in commit f8bf5a10 already, but we missed it.
    
    Change-Id: I03e95183be0e78bc7dd439d5fef5b10e54966dc3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5356
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit afc62a7631b92ab43774555552eb6a5ec0c4a7cb
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Mar 2 17:31:42 2014 +0100

    intel/gma: Remove MCH register declarations.
    
    i915_reg.h re-declares some of MCH registers as seen through MCHBAR mirror.
    It's not currently used and we don't want any MCH registers in GFX.
    
    Change-Id: I5fa4711fee60d64316696b7ed713013de8759b54
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5318
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 47089f29f0cf368e7c951158af61d5c040c7c8b9
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Mar 2 19:14:44 2014 +0100

    smbios: Supply tag type 2 (base board information)
    
    Information really contained in it is mostly the same as in type 1 tag.
    However Linux uses type 2 to match hardware. Duplicate the info.
    
    Change-Id: I75e13d764464053ecab4a833fbb83836cedf26e6
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5322
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 7d48f04bb4ba13e583a6fbc172eed9c8b5455dad
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Jan 27 00:16:51 2014 +0100

    lbtdump: Dump forwarded tables.
    
    Recent coreboot puts real tables in high memory and only pointer
    is remaining at traditional location.
    
    This patch makes lbtdump work with recent coreboot.
    
    Change-Id: I1c4945909da16c0ec81e59c2d94d9a7d27e2aba5
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4830
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit b66d53ac1086fbe26180a98af9b464a7abebd9d5
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Mar 10 01:58:37 2014 +1100

    mainboard/jetway/nf81-t56n-lf: Turn PS/2 driver on by default.
    
    This board has a working PS/2 port for a keyboard. Thus, it
    makes for a good option to have on by default.
    
    Change-Id: Ifcde0474d7be26152f1b5e19fe4906e87732b9a4
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5357
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit bfa29dc021f34f96bfe1f995e90834b0042a9784
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Mar 9 17:46:39 2014 +1100

    mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
    
    The platform dependent mainboard.c was incorrectly disabling the
    second clock signal feeding the GPP ports. This results in
    spurious hangs by calling the set_pcie_dereset() SB CIMx callback
    many times. This also stops coreboot from finding the second NIC
    behind the pci 15.0 bridge.
    
    Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5355
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 8340666cb18322cbf39110b82d83bf02bfa8c856
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Mar 6 16:32:18 2014 +0200

    intel/jarrell: Apply ROMCC workaround
    
    Taken from intel/xe7501devkit, maybe it had same symptoms once.
    
    The call to ich5_watchdog_on() has side-effect of exploding the
    requirements for ROMCC internal arrays at compile-time. The hard-coded
    limit in question is MAX_RHS in util/romcc.c, the default of 127 comes
    from the rhs field defined with 7 bits.
    
    Before this patch intel/jarrell builds were using upto MAX_RHS=102, while
    other ROMCC boards built even with MAX_RHS=10. This workaround brings
    intel/jarrell to the same level.
    
    Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5348
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 233f5b3b0ed27348b68fbaa453184d4fdb7fa0dc
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Mar 7 10:40:21 2014 +0200

    ROMCC: Trigger internal compiler failure and apply the workaround
    
    These boards first failed when attempting to change print_err() from
    direct function call to console_tx_XX() to a code block in the form of
    
     do { if (y) console_tx_XX(x); } while(0)
    
    Removing the label dummy_romcc_workaround_label added here will
    trigger the following compiler error for the two boards:
    
      Internal compiler error: no edge to block->last->next
    
    Change-Id: I997adfaf586d7fa2096401dd574b07ce676d0ac6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5349
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 2cf9715c9a766234ccf8a514bdf23af72c90b507
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Feb 20 20:06:42 2014 +1100

    utils/romcc.c: Fix spurious unsigned integer comparisons.
    
    Clang warns about comparisons of unsigned integers with being below
    zero. Remove spurious logic checks that are always false.
    
    Change-Id: I70c4d5331df81e48bf7ef27ff98400c4218f7edc
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5275
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 946923b0fbeba89e56f78e8266cf7f623ee78a87
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jan 18 18:28:58 2014 +0100

    qemu-i440fx: add a prototype for main()
    
    This probably belongs elsewhere, but I haven't found a nice place yet.
    
    Change-Id: I9ca52db33905cf4ee229d7ff44012105915271a8
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4720
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 1386d5ccb0fd4f4de45059dc4646ca2c9d5100f5
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Mar 8 11:37:46 2014 +0100

    lib/dynamic_cbmem.c: Include `cbmem_console.h`
    
    Broken with commit 1d7541fe (console: Fix includes).
    
    Change-Id: If41f9e08df98d79b7bbf740b1a5634d0140207be
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5351
    Tested-by: build bot (Jenkins)

commit c34713d33e088095acb6dd61527a26117d9c368e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Feb 25 20:36:56 2014 -0600

    x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING option
    
    Boot speeds can be sped up by mirroring the payload into
    main memory before doing the actual loading. Systems that
    would benefit from this are typically Intel ones whose SPI
    are memory mapped. Without the SPI being cached all accesses
    to the payload in SPI while being loaded result in uncacheable
    accesses. Instead take advantage of the on-board SPI controller
    which has an internal cache and prefetcher by copying 64-byte
    cachelines using 32-bit word copies.
    
    Change-Id: I4aac856b1b5130fa2d68a6c45a96cfeead472a52
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5305
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 7274800ea37edf41cb50e899d03baa02bdeecade
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Oct 31 08:26:23 2013 -0700

    Add a generic register script handler
    
    This is based on the RCBA configuration setup from haswell.
    It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF.
    I did not extend it to handle MSR yet but that would be another
    potential register type.
    
    There are a number of approaches to this kind of thing, but in the
    end they have a lot of switch statements and a mass of #defines.
    I'm not particularly set on any of the details so comments welcome.
    
    BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=emerge-rambi chromeos-coreboot-rambi
    
    Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175206
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4923
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 0567c91b22e36eb07e7c7b8a67cbf6b41778db30
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Feb 14 10:31:38 2014 +0200

    console: Use single driver entry for UARTs
    
    UARTs now have unified prototypes and can use a single entry
    in the list of drivers for ramstage.
    
    Change-Id: I315daaf9a83cfa60f1a270146c729907a1d6d45b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5308
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ab94bbf07221483ec52d072940a8b6206b69dc62
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 25 12:06:14 2014 +0200

    usbdebug: Move Kconfig under drivers/usb
    
    This menu may become a bit more complicated with addition of
    new USB hardware so move it out of console/.
    
    Change-Id: Ieb330675b9227a3e53d093f7c2b5a65e3842dc82
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5307
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 9c479c9a3e3353d3a73e62d4b593bbe4129af4fd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jan 26 11:32:51 2014 +0200

    SMM: Only have console with DEBUG_SMI
    
    Existing code compiled serial communication and printk() for SMM
    even when DEBUG_SMI was not selected.
    
    Change-Id: Ic5e25cd7453cb2243f7ac592b093fba752a299f7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5142
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit bea6bf07dfd9b97ad81fb7433464a9f61ff02105
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jan 30 15:45:16 2014 +0200

    uart8250: Move under drivers/uart
    
    Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5236
    Tested-by: build bot (Jenkins)

commit 2b95da01e6bbdd8b001fa1ff2830dbaa70f14c3e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Feb 15 10:19:23 2014 +0200

    uart8250mem: Unify calls with generic UART
    
    NOTE: UART base for SMM continues to be broken, as it does not use
    the address resource allocator has assigned.
    
    Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5235
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4770749edca1e54c9a04b48ca6909d786139fa1b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Feb 15 07:53:18 2014 +0200

    uart8250io: Unify calls with generic UART
    
    Change-Id: I6d56648e56f2177e1d5332497321e718df18300c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5234
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1d7541feeba372ec3d1d441442238e1c65972bd7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Feb 17 21:34:42 2014 +0200

    console: Fix includes
    
    Do not pull in console hw-specific prototypes everywhere
    with console.h as those are not needed for higher levels.
    
    Move prototypes for UARTs next to other consoles.
    
    Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5232
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7e75f20477511c48f47416caed7301e852165a7f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Feb 10 23:21:14 2014 +0200

    pl011 UART: Move under drivers/uart
    
    Currently this is only a minimal stub to get console on qemu-armv7.
    
    Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5162
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2cbcd2b7103f61a0a5b5f755aa92e3da8ec527f5
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Feb 19 08:58:12 2014 +0200

    ti/am335x: Fix baudrate calculation
    
    UART input clock is platform dependent. Also account for possible
    use of get_option() where baudrate is not compile-time constant.
    
    The hardware reference on BeagleBone is from a 48 MHz oscillator input.
    With pre-divisor of 16 we get same register values as in table 19-25.
    
    Change-Id: I89aee27c958f8618ce79a968ae7520a867e7e8a2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5290
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 65ba20e17bd91e4b92e34b495f64a51a0313f6a9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Feb 19 08:58:12 2014 +0200

    allwinner/a10: Fix baudrate calculation
    
    UART input clock is platform dependent. Also account for possible
    use of get_option() where baudrate is not compile-time constant.
    
    Change-Id: Ie1c8789ef72430e43fc33bfa9ffb9f5346762439
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5289
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c5332e30da4c314c1d44d6d3f9df6d2ae6417e0f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Feb 19 08:58:12 2014 +0200

    samsung/exynos5: Fix baudrate calculation
    
    Account for possible use of get_option() when baudrate is no longer
    compile-time constant.
    
    Change-Id: Ib45acd98e55c5892dbce9903830665aefeda5be0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5288
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 919923def3d76a95665c60e7ff3dd033c2d65d84
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jan 28 10:02:53 2014 +0200

    option: Add arch-agnostic get_option()
    
    We should not have pc80/ includes in console/.
    
    Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5157
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3ee1668ab4fbf75b256ac8eef4273b1ea445c998
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Feb 17 19:37:52 2014 +0200

    uart8250: Fix and unify baudrate divisor calculation
    
    Divisor is a function of requested baudrate, platform-specific
    reference clock and amount of oversampling done on the UART reference.
    Calculate this parameter with divisor rounded to nearest integer.
    
    When building without option_table or when there is no entry for
    baud_rate, CONFIG_TTYS0_BAUD is used for default baudrate.
    
    For OxPCIe use of 4 MHz for reference was arbitrary giving correct
    divisor for 115200 but somewhat inaccurate for lower baudrates.
    Actual hardware is 62500000 with 16 times oversampling.
    
    FIXME: Field for baudrate in lb_tables is still incorrect.
    
    Change-Id: I68539738469af780fadd3392263dd9b3d5964d2d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5229
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c76b3d6cca4a6135e5a7d7f3c2d9aa5128ef23f0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 18 06:46:19 2014 +0200

    uart: Drop HAVE_UART_MEMORY_MAPPED
    
    This option is used to make uart8250mem option visible in menuconfig.
    Showing it for these ARMs is incorrect.
    
    Change-Id: I2c28e1c3781df41c09c365355a5105c9fe4945ed
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5259
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a172ea546992c3f6f6a99b4dbaabbdae4c959707
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Feb 17 11:36:29 2014 +0200

    uart: Do not guard entire include file by config options
    
    Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or
    CONFIG_CONSOLE_SERIAL8250MEM or CONFIG_CONSOLE_SERIAL.
    
    Don't do indirect includes for <uart8250.h>.
    
    The config-specific options are already properly guarded, and there
    is no need to guard the register and bit definitions.
    
    Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4585
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 93fa422dea31f20bef6ceda43daa2e51a6d01ed5
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Mar 4 23:54:16 2014 +1100

    jetway/nf81-t56n-lf: Minor corrections to devicetree.cb
    
    The miniPCIe ports hanging off 15.0 are infact x1, as are the two
    onboard NIC's on 6.0 and 15.0.
    
    Change-Id: I6247838f6b5823369543e338975a4c5c6fd00d7c
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5328
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit ba885068120ec31de6191d2e89c2605830e7faab
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Tue Mar 4 17:07:22 2014 +1100

    jetway/nf81-t56n-lf: Fix PS/2 ACPI for KBC & Mouse.
    
    Provide ACPI table node so that the PS/2 keyboard/mouse port works
    in GNU/Linux.
    
    Change-Id: If73b8d37a81bb9066cbcc650b518d25e243b84e7
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5327
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 2e18978a97dc87a1b8713e45d33b7a226efdcece
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Mar 3 02:23:18 2014 +1100

    .gitignore: Don't track .ccwrap from scan-build.
    
    Change-Id: I5757023b844e965d797e6b1a7e6955940f6d3363
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5317
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 131573056fc12a629f7db0da14d8c50d8d156247
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 19 22:18:08 2014 +0100

    nehalem: Replace video init.
    
    Old video init just replayed the sequence.
    This one actually computes the values.
    
    Change-Id: Ic1fe7a2e90dc2cc36ac0d8bcea5cfabc583f09a3
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5270
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1b12ef1ac3bb45a315622dd82d16d3397a74d56f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Feb 21 07:21:00 2014 +0100

    drivers/intel/gma: Add EDID retrieving functions.
    
    Change-Id: I64f2fcc5ad52d6a0188d02b28769001ada718c4f
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5278
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 42c4a9df29528ab456da4c0a643816cb81d10610
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Feb 16 17:13:19 2014 +0100

    bd82x6x, ibexpeak, lynxpoint: Unify SPI.
    
    SPI registers didnt change since ICH8. No need to have separate
    files for them. Unify.
    
    Change-Id: I4e2ac3221b419c007e135c9ee615fc3b84424cbc
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5254
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 83ef74992a991023999b8ce2361e2b9bb1fb188f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Mar 3 23:21:12 2014 +0100

    ibexpeak/ehci: Set .enable_resources properly.
    
    Without this memory decoding isn't activated which, in turn,
    makes SeaBIOS crash.
    
    Change-Id: I3dcc721b500ab7468e1082157eeeed38044462d0
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5326
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 3f7ad7b216b4021c7cb93201a94b0fae46f5e19e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Feb 18 19:36:05 2014 -0600

    coreboot: don't return struct lb_memory * from write_tables()
    
    No one is interrogating the write_tables() return value. Therefore,
    drop it.
    
    Change-Id: I97e707f071942239c9a0fa0914af3679ee7a9c3c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5301
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit b013c279a93627c7edeb10cb5b976483e61166d9
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 19 22:10:03 2014 +0100

    nehalem: Remove SSKPD.
    
    Not really used and conflicts with SSKPD from i915_regs.h
    
    Change-Id: I1462457f656310df99e78aee8cbfe0206f6e2a1e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5268
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit db7d04d1b753eee52448e48ca55b28564d998bf5
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Feb 22 10:35:45 2014 +0100

    qemu: Support textmode gfx init.
    
    Change-Id: I8b6b14b4fcf8df21d8bbf988d640b1efa013bd7f
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5283
    Tested-by: build bot (Jenkins)
    Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 160e9a0224890219199f4af7cc79934cfcf45155
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Feb 22 10:34:47 2014 +0100

    devices: Allow to configure textmode in native gfx init.
    
    Usefull to select between text mode which offers best compatibility with
    payloads and gfx mode which makes the best-looking screen.
    
    Also right now we have an unfortunate situation when qemu is in gfx mode
    while most real systems use text mode.
    
    Change-Id: Ifad7ba197875edfdd06eb932afeb5800229ef055
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5282
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4bab5824e1551c7b0284e7155ef704b0b5359342
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Mar 1 09:27:37 2014 +1100

    lib/selfboot: s_srcaddr is uninitialized.
    
    s_srcaddr is uninitialized in the BSS section, leading to a
    garbage valued operand on the LHS of a '<' on line 383.
    
    Change-Id: Ie4fec91b09c70fb1d91ad3918ac3f60653fa1d83
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5314
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 2d5cec640132616b8336c60fdc426391ed800ef8
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Feb 25 00:24:22 2014 -0600

    coreboot: remove unused get_lb_mem() function
    
    The get_lb_mem() is no longer used. Therefore, remove it.
    
    Change-Id: I2d8427c460cfbb2b7a9870dfd54f4a75738cfb88
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5304
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit ceebc0503f15788604d31e16ac391ce8f99ca32e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Feb 25 00:21:10 2014 -0600

    selfboot: use bootmem infrastructure
    
    Instead of packing and unpacking entries in lb_mem use
    the bootmem infrastructure for performing sanity checks
    during payload loading.
    
    Change-Id: Ica2bee7ebb0f6bf9ded31deac8cb700aa387bc7a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5303
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 4904802efc8eee37f95163f60823509e2a208af4
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Feb 18 21:55:02 2014 -0600

    coreboot: introduce notion of bootmem for memory map at boot
    
    The write_coreboot_table() in coreboot_table.c was already using
    struct memrange for managing and building up the entries that
    eventually go into the lb_memory table. Abstract that concept
    out to a bootmem memory map. The bootmem concept can then be
    used as a basis for loading payloads, for example.
    
    Change-Id: I7edbbca6bbd0568f658fde39ca93b126cab88367
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5302
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit c7db28c580785b62b9fc67b7526c87d4f0073883
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 19 22:09:33 2014 +0100

    intel/nehalem: Fix soft reset detection.
    
    Change-Id: I4575cddc35dc8309372beafec441d194bc145242
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5267
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit e1eef694ea6a055ab5f6dc792847702aced5a2ad
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 19 22:08:51 2014 +0100

    intel/nehalem: Use non-powercycle reset.
    
    Change-Id: Ibc2421a50e272a580461e4eacec6cfcd38654fe8
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5266
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 9817a37416468cc8a00990e3f431b8d3634f5fcc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 19 22:07:12 2014 +0100

    nehalem/raminit: Don't touch clock generator in raminit.
    
    Clock generator is mobo-specific. Don't touch it in raminit.
    
    Change-Id: Ie114696b7fb13b8daee8dd1393d43bc609e149b3
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5265
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7d1996cc4af563f614455db23fe91a6feccd2560
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Feb 24 22:27:39 2014 -0600

    coreboot: introduce arch_payload_run()
    
    The selfboot() function relied on global variables
    within the selfboot.c compilation unit. Now that the
    bounce buffer is a part of struct payload use a new
    architecture-specific arch_payload_run() function
    for jumping to the payload. selfboot() can then be
    removed.
    
    Change-Id: Icec74942e94599542148561b3311ce5096ac5ea5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5300
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit e58a24b1b598383eab918dac03be4d7122bf0ac5
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Feb 24 22:11:45 2014 -0600

    selfboot: store bounce buffer in struct payload
    
    In order to break the dependency on selfboot for jumping to
    payload the bounce buffer location needs to be communicated.
    Therefore, add the bounce buffer to struct payload.
    
    Change-Id: I9d9396e5c5bfba7a63940227ee0bdce6cba39578
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5299
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 6086e63a79576a1c7d8d06c2413fef34a65c94ba
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Feb 24 21:50:24 2014 -0600

    coreboot: use struct payload for selfload()
    
    In order to encapsulate more data for self loading use struct
    payload as the type. That way modifications to what is needed
    for payload loading does not introduce more global variables.
    
    Change-Id: I5b8facd7881e397ca7de1c04cec747fc1dce2d5f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5298
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 1322d7f9d58f355f469ab7b993f7da5b6117edb6
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Feb 24 21:24:28 2014 -0600

    coreboot: move common code to payload_run() from selfboot()
    
    The selfboot() routine was perfoming most of the common teardown
    and stack checking infrastructure. Move that code into
    payload_run() to prepare removal of the selfboot() function.
    
    Change-Id: I29f2a5cfcc692f7a0fe2656cb1cda18158c49c6e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5297
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit bdf913ab010c99db8e64845f5b5837c9008609dc
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Feb 24 14:56:34 2014 -0600

    coreboot: unify infrastructure for loading payloads
    
    A payload can be loaded either from a vboot region or from cbfs.
    Provide a common place for choosing where the payload is loaded
    from. Additionally, place the logic in the 'loaders' directory
    similarly to the ramstage loader infrastructure.
    
    Change-Id: I6b0034ea5ebd04a3d058151819ac77a126a6bfe2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5296
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 9cd96b409646418040f5c046a1366cfc38251d70
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Fri Feb 21 12:43:07 2014 +1100

    vendorcode/amd/agesa/f*: Improve gcccar.inc assembler compatibility.
    
    A comparison with a two's complement in gcccar.inc has dubious
    GAS/AT&T notation. Clang miss-parses 0x-1 as an invalid hexadecimal
    number.
    
    Change-Id: I88baa5c2513f062ff309df05916a3832b9bd9bb1
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5277
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5edfa3779dd3fc18ec182bc4f0085c0aa1e1474e
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Jan 29 16:50:40 2014 -0600

    cbfstool/lzma: Remove dead code under #ifdefs
    
    Remove a bunch of dead code which depends either on commented out
    #defines, or compiler definitions. Use this opportunity to remove the
    need for "-D_7ZIP_ST" in the compiler flags.
    
    Change-Id: Ib6629002be7bf4cee6d95d7baa724893b5e8ba32
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5083
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 5ca914bc64829f097629661c2f48492c81cfd77e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Feb 2 18:44:42 2014 +0100

    lenovo/x60: Unify volume button handling with common code.
    
    Change-Id: I45fe44a91f9f83a510b204e01dbaff9e8a9696ca
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5099
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e92155fbe6f40f92dcb4001c62804d64463e28f7
Author: Chris Douglass <cdouglass.orion@gmail.com>
Date:   Fri Feb 14 13:51:52 2014 -0500

    intel/sandybridge: add PCI IDs for 6-Series PCH
    
    The PCI ids are taken from:
    	Intel® 6 Series Chipset and
    	Intel® C200 Series Chipset
    	Specification Update – NDA
    	October 2013
    	CDI / IBP#: 440377
    
    Change-Id: Ib8418173fd36fd4109b3c4ec0d5543ca8e39ffa6
    Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
    Reviewed-on: http://review.coreboot.org/5226
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 770c71f3ec6a002c83f4a6fd9d1ee20096aa9acb
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Jan 28 00:05:29 2014 +0100

    lenovo/x201: Move mainboard init to mainboard_init.
    
    Rather than having it inside mainboard_enable.
    
    Change-Id: Ie8bd25eb49b919b4e25c4628e3557fc66b2ba4d9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4840
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit f0e025a386ab79166c2711a022a813fda874da63
Author: Chris Douglass <cdouglass.orion@gmail.com>
Date:   Tue Feb 18 11:21:02 2014 -0500

    drivers/spi: Sort SPI flash files
    
    Change-Id: Id7e65065556ca7225969ca0afdb21eda24aeb967
    Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
    Reviewed-on: http://review.coreboot.org/5260
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e2718656ec9ca7cb3c6f94453b9e76b0ae132abd
Author: Chris Douglass <cdouglass.orion@gmail.com>
Date:   Fri Feb 28 08:54:41 2014 -0500

    util/ifdtool: cleanup some magic numbers
    
    There are five firmware regions that are (currently) defined. This
    was assumed throughout the ifdtool code with many literal 4s and
    5s. This patch changes them to refer to a new #define NUM_REGIONS.
    
    Change-Id: I523d3763942f875025ebc4b9ba8b2ccf1db5b2f5
    Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
    Reviewed-on: http://review.coreboot.org/5313
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4eabe1e4e1e4aa7ffa5a147a609a8782f48f0791
Author: Chris Douglass <cdouglass.orion@gmail.com>
Date:   Thu Feb 27 09:25:19 2014 -0500

    util/ifdtool: add option to change flash layout
    
    The new option "--newlayout <file>" will read <file> in flashrom's
    layout format and copy flash regions from the current flash image
    file to a new flash image file.
    
    If a region grows, the padding is added at the beginning of the target
    region in the new file so that the data is "right-aligned" to the
    end of the region.
    
    If a region shrinks, a warning is given and the tail end of existing
    data is copied to the target region in the new file.
    
    Regions of zero or negative size are ignored. (In the example below
    00fff000:00000fff regions are an artifact of the address encoding
    in the register fields.)
    
    Example Usage:
    
    Given a flash image for a board with a Sandy Bridge processor and
    Intel 6-Series chipset in the file vpx7654.bin
    
    ifdtool --layout layout.txt vpx7564.bin
    will yield the file layout.txt:
    	00000000:00000fff fd
    	00180000:003fffff bios
    	00001000:0017ffff me
    	00fff000:00000fff gbe
    	00fff000:00000fff pd
    
    Notice that the "bios" portion extends to the end of the 4MB flash.
    It may be edited to extend the bios portion to consume to the extent
    of an 8MB flash. like layout2.txt:
    	00000000:00000fff fd
    	00180000:007fffff bios
    	00001000:0017ffff me
    	00fff000:00000fff gbe
    	00fff000:00000fff pd
    
    ifdtool --newlayout layout.txt vpx7654.bin
    will create a file vpx7654.bin.new that is 8MB.
    
    Change-Id: I0e0925a725c40fa44d8c4b6e86552028779d0523
    Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
    Reviewed-on: http://review.coreboot.org/5312
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 03ce014cfc35a1c51eadec46d30169b2c641e011
Author: Chris Douglass <cdouglass.orion@gmail.com>
Date:   Wed Feb 26 13:30:13 2014 -0500

    util/ifdtool: add option to dump flashrom layout
    
    Dump the Intel Flash Descriptor map in the format expected
    by flashrom's "layout" option.
    
    Example usage:
    
    Given a 4MB flash image vpx7654.bin that was generated by Intel's
    FITC tool for a 6-Series chipset...
    
    ./ifdtool --layout l.txt vpx7654.bin
    cat l.txt
    	00000000:00000fff fd
    	00180000:003fffff bios
    	00001000:0017ffff me
    	00fff000:00000fff gbe
    	00fff000:00000fff pd
    
    Change-Id: Ib740178ed6935b5f6e1dba1be674303f9f980429
    Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
    Reviewed-on: http://review.coreboot.org/5306
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 970dd9c46672bd194189296977ac8bbf098c139e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 12:20:58 2014 +0100

    boardstatus/towiki: Skip OVERRIDE_FANCTL
    
    Change-Id: I4c5f69db198c8aa4757c82856fb04aa5ee16879f
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5123
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 50d9752e7f881da20bb4623a7a2460e65c9931ba
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 12:20:24 2014 +0100

    boardstatus/towiki: Skip comments after options.
    
    Change-Id: Id1213f4a44cd3a7a698b761d4942707d7dc1dee6
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5122
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 7035b85f52682a5225d985cb4bee8753cf4760ab
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Jan 28 04:16:41 2014 +0100

    boardstatus/to-wiki.sh: Accept Kconfig with non-tab separators.
    
    Change-Id: I3812c6bd6fb11d9e98ef60afb205782f2b1f0e44
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5069
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 4a082c669c50e5ccca51069b47a928be20d0f8c0
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 31 11:58:32 2013 -0500

    baytrail: use common code for iosf accessors
    
    The same sequence is used regardless of the port
    being read or written. Therefore, use the same
    implementation for reading or writing to a port.
    
    BUG=None
    BRANCH=None
    TEST=Built and booted through depthcharge. Dev and recovery
         screens still work. Nothing bizarre in console output.
    
    Change-Id: I1a64b54b50472fa7d601e199653eb4a76accf910
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175441
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4922
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit bc69ae9823e9260bee6f2db557a6d26c683f4ad2
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 31 10:46:56 2013 -0500

    baytrail: add lpss iosf functions and regs
    
    The low power subsystem devices have a lot of their
    configuration done in the IOSF sideband message space.
    Add support for these access methods.
    
    BUG=chrome-os-partner:23790
    BRANCH=None
    TEST=Built and booted through depthcharge.
    
    Change-Id: I0dd52b952a16ef1280c29301164db041ee87f636
    Signed-off-by: Aaron Durbin <adurbin@chromum.org>
    Reviewed-on: https://chromium-review.googlesource.com/175440
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Tested-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4921
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 92fce495a7fa4331b7f1d49d8f8fe6bcb33761d4
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Nov 1 07:55:07 2013 -0700

    baytrail: Fix EHCI function number and XHCI typo
    
    BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=successfully disable EHCI controller in devicetree.cb
    
    Change-Id: I8a22e25a9f7c263d2a6debf0cd1606cb0f6f7645
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175403
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4920
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit a8e9b63166876941d1d8e54b732d824a8ef38a76
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Oct 30 15:46:07 2013 -0500

    baytrail: increment boot count for elog
    
    The elog boot counter in cmos was not being initialized
    nor incremented. Start doing that in romstage. Since S3
    resume is not detected yet the increment is unconditional.
    
    BUG=None
    BRANCH=None
    TEST=Built and booted through depthcharge multiple times. Noted
         output such as 'Boot Count incremented to 4'.
    
    Change-Id: Ic585d4ad4b3af086e0067e28fe0f35c02979bbd2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174717
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4919
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 6e77beec96b538f26c63f2623c72a7e5d24fb5e1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Oct 30 15:25:42 2013 -0500

    baytrail: add GNVS to cbmem and set acpi_slp_type
    
    The ACPI code was previously complaining about not being able
    to find the GNVS area: 'ACPI: Could not find CBMEM GNVS'. Fix
    this by adding GNVS area early in start up. This is also the
    appropriate place to set the acpi_slp_type variable to indicate
    an S3 resume or not.
    
    BUG=chrome-os-partner:22867
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Built and booted through depthcharge. Noted cbmem has 'ACPI GNVS'
         entry.
    
    Change-Id: Ifbca3dd390ebe573730ee204ca4c2f19626dd6b1
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174647
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4918
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 61cd57ba36cc69aba2d6feb3be6398e4d4f46f68
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Oct 30 14:36:11 2013 -0500

    baytrail: fix uninitialized acpi structures
    
    The callers of the following functions assume the storage
    area provided by the pointers is initialized. That's not the
    case as these were just place holders.
    - void acpi_create_intel_hpet(acpi_hpet_t * hpet);
    - void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
    
    To fix this properly initialize the hpet entry, and just remove
    the serialio_ssdt function entirely.
    
    BUG=chrome-os-partner:23505
    BRANCH=None
    TEST=Built and booted through depthcharge on rambi. Noted no more
         ACPI errors relating to invalid length.
    
    Change-Id: If56ab033562ef2d755e9c9de42f507c95d291aba
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174716
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4917
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 0854c84735175ea29c8df74dd9d7124a0c1a415b
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Oct 31 08:20:48 2013 -0700

    baytrail: Add IOSF functions for USBPHY and USHPHY
    
    These are needed for USB2 and USB3 PHY init sequences.
    
    BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=emerge-rambi chromeos-coreboot-rambi
    
    Change-Id: Id284d882034e15eceeaa910b8b73bc0d8d895199
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175227
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4916
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 5d53554d41873993a17b75acaf2c5a2581ee90dd
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Oct 31 10:10:20 2013 -0700

    rambi: Enable internal keyboard
    
    The EC LPC init function needs to run to enable the internal keyboard.
    
    I needed this to confirm that it is just USB keyboards that are causing
    all sorts of issues.
    
    BUG=chrome-os-partner:23635
    BRANCH=rambi
    TEST=boot to recovery screen and hit tab
    
    Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175207
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4915
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit a6151f4bfb59ace5b59f255ca06bb9299ad11efe
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Mon Oct 28 16:43:17 2013 -0700

    rambi: Enable SATA port
    
    Enable first SATA port in Rambi device tree.
    
    BUG=chrome-os-partner:23643
    TEST=TEST=Manual, in dev mode. Verify on rambi that SATA disk is
    detected, and kernel is found + booted.
    
    Change-Id: Ic0cb5f9ff17ca0f6cc7941f203b9338df200811d
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174916
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4914
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 1dbd0e224ec96bc4024be2ba7176d95f31282f3d
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Mon Oct 28 16:15:02 2013 -0700

    baytrail: Add SATA driver
    
    Add SATA driver for baytrail platform.
    
    BUG=chrome-os-partner:23643
    TEST=Manual, in dev mode. Verify on rambi that SATA disk is detected, and
    kernel is found + booted.
    
    Change-Id: I5c13e03203c8f26d233c7d10af8ff6812c460578
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174914
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4913
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 4477050e223450e42f7b55bdef10153004c216d6
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Oct 29 17:00:07 2013 -0500

    rambi: add all on-board devices
    
    Add the on-board devices in the SoC to the device tree.
    Also, disable the unused devices aside from TXE and HDA.
    Those particular devices cause the system to shut down
    when they are disabled.
    
    BUG=chrome-os-partner:22871
    BRANCH=None
    TEST=Built and booted through depthcharge. Noted the calls to the
         southcluster disable function.
    
    Change-Id: I482c1c9609833054aeb2948144af54b57d3df086
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174645
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4912
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit d7bc23ac8e034de2bf33c50a1f209d7d23250e6b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Oct 29 16:37:10 2013 -0500

    baytrail: add support for disabling south cluster pci devices
    
    When the southcluster pci devices are listed in the devicetree add
    the ability to perform the proper disabling sequence for turning
    off devices. This only turns off the pci device interface as well
    as put the device into D3Hot. It is not yet known how to put the TXE
    device into D3Hot so it's currently not possible to disable that
    device.
    
    Also, expose the southcluster_enable_dev() function so that other
    devices can call this if they require doing specific things before
    disabling the device. The southcluster_enable_dev() is only called
    on devices found in the devicetree and if they currently have no
    ops associated with them.
    
    BUG=chrome-os-partner:22871
    BRANCH=None
    TEST=Built and booted through depthcharge. Interrogated
         output to ensure devices were being properly disabled.
    
    Change-Id: I537ddcb9379907af2fe012948542b6150a8bf7c5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174644
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4911
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 67633a558a2cc55215565ee8e9079c97acc87171
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Oct 29 10:57:31 2013 -0500

    baytrail: use MCRX in iosf access functions
    
    While most registers accesses don't need the use of the MCRX
    register (upper 24 bits of address) the MCRX register should
    be protected. The reference code could be doing accesses to
    registers that initialized the MCRX register. Thus, any access
    after that should ensure the MCRX register is initialized
    appropriately.
    
    BUG=None
    BRANCH=None
    TEST=Verified assembly output. Also, built and booted through
         depthcharge.
    
    Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174643
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4909
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit cf6c9cc29cedfd533da8cfaa8481560bce739097
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 14:27:22 2014 +0100

    Kill ALT_CBFS_LOAD_PAYLOAD
    
    Not used anymore.
    
    Change-Id: Icf3a4a7f932776981048b805478582ad2b784182
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5132
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 58fdb4fe15f949745b31f1d8136226ab88f7271d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 14:23:56 2014 +0100

    lynxpoint: Kill alternative cbfs_load_payload.
    
    With generic load using 32-bit accesses this is no longer has a
    huge impact it previously did. It's also unnecessarily
    component-speficific.
    
    Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5131
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 4337020b950454815204eed4e43a894be0b125ca
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 19:46:45 2014 +0100

    Remove CACHE_ROM.
    
    With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82,
    speedup by CACHE_ROM is reduced a lot.
    On the other hand this makes coreboot run out of MTRRs depending on
    system configuration, hence screwing up I/O access and cache
    coherency in worst cases.
    
    CACHE_ROM requires the user to sanity check their boot output because
    the feature is brittle. The working configuration is dependent on I/O
    hole size, ram size, and chipset. Because of this the current
    implementation can leave a system configured in an inconsistent state
    leading to unexpected results such as poor performance and/or
    inconsistent cache-coherency
    
    Remove this as a buggy feature until we figure out how to do it properly
    if necessary.
    
    Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5146
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 20f83d56561879045ecade24d51e79dfb151baf6
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Feb 11 10:38:27 2014 +0100

    intel/*/acpi: Increase range length of MCHBAR buffer to 32 kB
    
    Linux kernel 2.6.31 reports the warning below on Intel Ivy Bridge (with
    FSP).
    
    	resource map sanity check conflict: 0xfed10000 0xfed17fff 0xfed10000 0xfed13fff pnp 00:01
    
    Since Sandy Bridge the length of the MCHBAR is 32 kB and it is already
    used that way in other places.
    
    	$ more src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
    	[…]
    	OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
    	[…]
    
    So instead of 16 kB specify that 32 kB are decoded in that memory
    range for Intel Sandy Bridge, Ivy Bridge and Haswell.
    
    (Linux kernel 3.10 does not warn about that.)
    
    Change-Id: Ie7a9356d9051c807833df85e4a806e5a9498473f
    Reported-by: Norwich in #coreboot on <irc.freenode.org>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5192
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Werner Zeh
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit e3f75f8ecaf1aab1bee1f1f79caa35c526c124a5
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Oct 28 15:49:34 2013 -0700

    baytrail: Enable GFX device
    
    - Ungate display in PUNIT
    - Set GSM to 64MB since 32MB is not supported in <C0 stepping
    - Initialize power management registers in GTT
    - Execute VBIOS if found
    
    BUG=chrome-os-partner:23507
    BRANCH=rambi
    TEST=build and boot to dev screen via HDMI on rambi
    
    Change-Id: Idb032c7ea7f16b651b4c921e3429a652fe663a5d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174922
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4907
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e549e94d03305ce142d973ebb1f8383d37d3a491
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Oct 28 14:18:38 2013 -0700

    baytrail: IOSF write functions need to set data before control
    
    The data needs to be available in the register before the control
    bits are set to make the write happen.
    
    BUG=chrome-os-partner:23507
    BRANCH=rambi
    TEST=successfully ungate power on PUNIT on rambi
    
    Change-Id: I8fae60d5385ce9a401c1dec9cbb39b70d157a6c2
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174898
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4906
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 063c87358880ac911764b5a8fe4cdf09003278e1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Oct 28 11:24:53 2013 -0500

    rambi: add chromeos EC support
    
    As rambi has the ChromeOS EC on it the EC needs to
    be configured properly. Do this along with updating the
    ChromeOS support for passing on write protect state, recovery
    mode and developer mode.
    
    BUG=chrome-os-partner:23387
    BRANCH=None
    TEST=Built and booted to depthcharge. EC software sync appears to
         work correctly. Additionaly, 'mainboard_ec_init' appears in
         the console output.
    
    Change-Id: I40c5c9410b4acaba662c2b18b261dd4514a7410a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174714
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4905
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3e0eea1f93655c43f84c6223ed1ae843666c7863
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Oct 28 11:20:35 2013 -0500

    baytrail: initialize chromeos EC if present in romstage
    
    The EC needs to be initialized early in romstage. Therefore
    perform the call after console has been initialized in order to
    view any messages that the code may spit out.
    
    BUG=chrome-os-partner:23387
    BRANCH=None
    TEST=Built and booted with recovery mode and EC in RW. Noted that
         system reboots the EC.
    
    Change-Id: I35aa3ea4aa3dbd9bd806b6498e227f45ceebd7a1
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174713
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4904
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8fa6283b8dcf6abe740d60dc1450c07fcf1265de
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Oct 28 09:54:22 2013 -0500

    baytrail: use version 2 of efi wrapper
    
    Version 2 of the efi wrapper wants the speed of the TSC
    timer initialized in the parameter structure.
    
    BUG=chrome-os-partner:22866
    BRANCH=None
    TEST=Built and booted through depthcharge. No errors spit out by
         wrapper.
    CQ-DEPEND=CL:*147256
    
    Change-Id: I9cd265ea6bde93be85fc6fbc905d83af57fc2773
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174712
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4903
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit eb2eedf6f7d6ac1cff65ed8672701f6efd3b19dd
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Oct 25 09:12:45 2013 -0500

    baytrail: remove gfx read_resources() work around
    
    Before the special PUNIT settings the GFX pci device
    had the same device id as the transaction router. This
    required a special case in the transaction router's
    driver to do the proper thing for read_resources().
    However, that requirement is no longer needed as the
    PUNIT special message is now being done. Therefore,
    remove the work around.
    
    BUG=None
    BRANCH=None
    TEST=Built and looked at resource allocation logs to confirm
         work around is no longer needed.
    
    Change-Id: I90b155cb5560ca3291f146c2f586456e5529f6b2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174652
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4902
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 315bb30cd764a3f57cc6ce36a481e7361ac3a0c0
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 24 14:55:42 2013 -0500

    baytrail: get rid of global microcode_ptr
    
    A global microcode_ptr was added when doing the MP
    development work. However, this is unnecessary as the
    pattrs structure already contains the pointer. Use
    that instead.
    
    BUG=chrome-os-partner:22862
    BRANCH=None
    TEST=Built and booted. Microcode still being loaded correctly.
    
    Change-Id: I0abba66fc7741699411d14bd3e1bb28cf1618028
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174552
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4901
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 049e9bd2dca2b4bb962c25e18ba29f0c0d777517
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 24 14:54:04 2013 -0500

    baytrail: add microcode version 319
    
    Update microcode version to 319.
    
    BUG=None
    BRANCH=None
    TEST=Built and booted. Noted 319 being used.
    
    Change-Id: I008f90a1c6b542d979e34da22e9f375224c0ffeb
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174551
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4900
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8b22feb1cf3afb63d5d9d7d34f0787de88a851a8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Feb 23 14:06:58 2014 +0100

    jetway/nf81-t56n-lf: Use proper category.
    
    "Mini-ITX" was a pure inventional name for category called "mini".
    
    Change-Id: I6450fd27c1a7679f252ce7f46f409b7dc459c50d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5286
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit d47c08affd4548b766da4a026573b43e577f3182
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 11 14:58:04 2014 +0200

    TI am335x: Apply Kconfig use conventions
    
    Change-Id: Ic3c26fd7b1dd8a6731abc9a63b9ca17e084074b2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5291
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit d777d86ab2afc03c0a1d98f136e05ef9c64aa5ed
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Feb 20 05:10:09 2014 +1100

    CAR_GLOBAL: enforce compiler to check if _start != _end
    
    There are some fun rules C compilers can use to optimize their code.
    One of them is the assumption that two symbols point to two different
    addresses.
    In this case this wasn't true, resulting in unintended code execution
    (and later, a crash) with a clang build.
    
    Change-Id: I1496b22e1d1869ed0610e321b6ec6a83252e9d8b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/4719
    Tested-by: build bot (Jenkins)

commit fb6d25faa05c43a46da5a2f5307c35b97e08e7cb
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Feb 21 08:38:27 2014 +0100

    device: Do not show "framebuffer graphics resolution" with native init.
    
    No native init uses this.
    Real hardware ones use mode specified in EDID.
    Qemu one uses CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_[XY]RES.
    
    Change-Id: I0845fec10b9811e2be44b5be30b9dc4f1c9719a6
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5281
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1a37b265a40c68aee027e1d0919ef5792d1b34d9
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 19 22:12:02 2014 +0100

    lib/edid: Don't set vbe_valid in decode_edid.
    
    Decoding EDID doesn't yet mean that gfx mode is used.
    
    Change-Id: Icedd36f26877754f34dd59233cce72271d7f0b19
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5269
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit ea6736a2d0b4f30e564eab25128d9c67058330da
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Feb 10 00:00:44 2014 +0200

    usbdebug: Unify console API
    
    Struct dbgp_pipe would not be suitable for use with xHCI.
    Just use an index, it is easy to setup in Kconfig if our
    future debug setup has separate pipes for console
    output and debugging/traceings.
    
    Change-Id: Icbbd28f03113b208016f80217ab801d598d443a8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5227
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 902626c23c5b56765900a7c8e3dded109f4044fa
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Feb 16 17:22:26 2014 +0100

    nehalem: Make SPD address map into parameter.
    
    It's mobo dependent.
    
    Change-Id: I7a9ba0fb7374a61178e9282acd8f10098435f1fd
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5253
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 2ab8ec7cfb1c930fc188d6ac13040b3fd753c476
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Feb 20 14:34:56 2014 +0100

    nehalem/raminit: Fix typo of NUM_CHANNELS instead of NUM_SLOTS.
    
    Change-Id: I0fbfa8cb39881782bec3af5e43ff3c63dd2e4919
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5276
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2bebc8016630b2db5c0740041bf1cfc80e2706cd
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 19 22:02:51 2014 +0100

    ibexpeak/thermal: set temperature target in early init.
    
    Properly determine temperature target and set it in early
    init rather than hardcoding it in late init.
    
    Change-Id: Ie763f205890674a9dd1d9c5974caaccdd67cea14
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5264
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 10b3974811b7e851856f71f8e09e8c5c682326f6
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 19 22:00:00 2014 +0100

    intel/model_2065x: Fix APICID generation.
    
    APIC IDs always step by 4 on 2065x independently of number of threads.
    
    Change-Id: I5abd4005c8ce1740bb0862d952af66236b609aa8
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5262
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e7f7d990df2da664a42d8bbb6f3a4f5c71731261
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Feb 17 22:32:02 2014 +0200

    SMM: Fixes for DEBUG_SMI
    
    Get the required UART includes directly.
    The ne2k part is old copy-paste leftover.
    
    Change-Id: Ifd9253abb5a50b515887459faf06b63f907eeda9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5258
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit b7d87888801325dc77cd9113011d08efd330e101
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 19 22:01:35 2014 +0100

    ibexpeak/lpc: Fix PCIIDs.
    
    Add PCIID from Easynote LM85. Remove unrelated IDs inherited from
    BD82x6x.
    
    Change-Id: I03b6e0b2e08a4a6014aa1ef1f8d9a3a567f03ad9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5263
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit d01ed75066fffe3fb73c98ece628f34120e6e029
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jan 18 16:56:36 2014 +0100

    printk: support and use %hh prefix
    
    clang complains otherwise.
    
    Change-Id: I2ac98d7147ecd3d7064f17f8c9d214d44baedf97
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4717
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 327a86603c861ece294f1c9db5875a178bcbcc76
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jan 18 16:26:11 2014 +0100

    x86: only build disassembly with gcc
    
    The assembler options are specific to the gnu toolchain.
    
    Change-Id: I8424767ef186ef2d4c18bfbcae1f54e0da2e4f47
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4715
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 938ef9fb8d69f8ce28dfc4948e05fe3768b020df
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jan 18 16:24:24 2014 +0100

    x86 bootblock: improve clang compatibility
    
    Its linker doesn't like "." arithmetics, so use .org,
    while its assembler doesn't like data32 prefixes.
    
    Change-Id: I3f5bbb350493d6510b8013df15d44c44c5db63c7
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4714
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

commit 0d0b3c5467192a101faaaebcace4ca390c2a5646
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Feb 10 11:34:27 2014 -0800

    lynxpoint: Finalize chipset before playload if not CONFIG_CHROMEOS
    
    The Chrome OS environment sends an SMI to finalize the chipset/board
    at the end of the "depthcharge" payload, but there is no facility to
    send this command if not using the full ChromeOS firmware stack.
    
    This commit adds a callback before booting the payload that will
    issue this SMI which will lock down the chipset and route USB devices
    to the XHCI controller.
    
    Change-Id: I2db9c44d61ebf8fa28a8a2b260a63d4aa4d75842
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5181
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 970ad7076388b3ef98988121170df86196d493b4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Feb 15 13:58:01 2014 +0200

    console: Add drivers/uart
    
    Also move UART related Kconfig options from top-level file.
    
    Change-Id: I4e407977cff6f6506f991600c98d6d264676d3f8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5230
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 7040d7dfad8f62bbcbe5f92c653fb0c962e868ec
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Thu Oct 24 09:59:00 2013 -0700

    rambi: Set VBOOT_RAMSTAGE_INDEX to point to ramstage image
    
    The ramstage image is the third image in the partition (after ECRW hash
    and depthcharge image).
    
    TEST=Manual. Boot rambi, verify that ramstage image is correctly found:
    "RW ramstage image at 0xffb1dc70, 0x0000f391 bytes"
    BUG=None.
    
    Change-Id: I628db3daf0b109106c51693960487a0c83b4e9f4
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174540
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4899
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit ae5d83ef84b1cd51e426d9e812ec40a7bc744e55
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 24 10:21:43 2013 -0500

    baytrail: add support to run reference code blob
    
    The reference code blob is needed to bootstrap
    certain pieces of hardware in bay trail. Provide
    the ability to run reference code by loading
    the reference code as an rmodule.
    
    Note that support for vboot verification and S3
    resume is omitted from this commit.
    
    BUG=chrome-os-partner:22866
    BRANCH=None
    TEST=Built and booted with refcode loading.
    
    Change-Id: I30334db441a57f4d87b4de6fca0a9a48e1c05c05
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174426
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4898
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit e18d68fbaccf9e0f9bafed7f7dc60dbe95d2f4fd
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 24 00:05:31 2013 -0500

    baytrail: add south cluster fixed resources
    
    The PCU (platform controller unit) contains the
    resources and IP blocks that used to reside in the
    south bridge. Bay Trail has since renamed it south
    cluster. There are quite a few fixed MMIO and I/O
    resources. If these aren't added the resource allocator
    will freely assign these addresses which causes conflicts
    and other subtle bugs.
    
    BUG=chrome-os-partner:23544
    BUG=chrome-os-partner:23545
    BRANCH=None
    TEST=Built and booted through depthcharge. Verified
         resource allocation not weird. And no more depthcharge
         crashes.
    
    Change-Id: I697fbda4538c03fded293bcb63a5823b1ed150ec
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174421
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4893
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 6c3413ab5f2edb417efe8b91b49f38795699f73e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Feb 16 18:03:45 2014 +0100

    lenovo/x201: Fix wrong declaration in devicetree.cb
    
    Change-Id: I90c6ff14ab819368ccc874008a7fb1410a543984
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5255
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit ce7ecf9cc7cd7370c8f5779ea5e12c67928ad6e1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 24 08:42:10 2013 -0500

    baytrail: enable monotonic timer
    
    Enabling the monotonic timer allows for collecting
    boot stage times as well as each device initialization
    time.
    
    BUG=chrome-os-partner:23166
    BRANCH=None
    TEST=Built and booted. Noted timings in console output.
    
    Change-Id: I5fdc703ea21710fd26de352f367c6fc0c767ab6a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174422
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4894
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 73a1018ce33a85c0b55633410225162e1bf3fe2c
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Sun Feb 16 00:32:13 2014 +0000

    src/drivers/spi: introduce AMIC support
    
    Add support for the AMIC A25L032 flash chip.
    
    Change-Id: Ie8d441a923c6fbd18c16440b4571321652d934d5
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/5252
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit a4c7b7a46b16de7dfa2c3f2fe1e1ce071328fa77
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Feb 16 06:55:41 2014 +0200

    vortex86ex: Drop baudrate programming for 10 UARTs
    
    This is responsibility of end-user application. When coreboot does
    it, it is only for the purpose of debug console.
    
    Change-Id: Idbbf9528c60b9b819b7bea9dfe84078a3f055bc9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5251
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Andrew Wu <arw@dmp.com.tw>

commit 591031f4deb9d44cef0de8501b482c6a32872581
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Feb 13 00:33:40 2014 +0200

    sandy/ivy: Fix mrc.cache file in CBFS
    
    The file was not recreated when configuration changed. One would
    hit this bug when turning CHROMEOS on/off.
    
    Also do not create mrc.cache with CHROMEOS at all.
    
    Change-Id: I5b0ecde66589396b24967ce289bf65e20bb08825
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5211
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit d262a71957dcbe42e84e23aa4d3ca1c64bc10176
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Jan 28 14:28:49 2014 +0100

    ibexpeak/azalia: Remove C4-register extended init.
    
    This sequence was derived from BD82X6X and on ibexpeak it inadvertently
    disables interrupts. In older kernels it wasn't a problem but in new kernel
    it makes codec probe fail.
    
    Change-Id: I40184ae8c4cfe758869af1a1565b88f0a238150e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5074
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 56ffa7268cb6b2cb43b6ca2a285bf13a292b4792
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Feb 16 18:04:05 2014 +0100

    ibexpeak/sata: Add PCI ID from Easynote LM.
    
    Change-Id: I979a40ad3692cd474920f3ee5c6b10c41f75bfdb
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5256
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 7837be6cbb9dfacf66d0981e281c3d9a0a35767d
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Oct 21 22:32:00 2013 -0500

    baytrail: SMM support
    
    Initialize SMM on all CPUs by relocating the SMM region
    and setting SMRR on all the cores. Additionally SMI
    is enabled in the south cluster.
    
    BUG=chrome-os-partner:22862
    BRANCH=None
    TEST=Built and booted rambi. Tested with DEBUG_SMI and noted
         power button turns off board while in firmware.
    
    Change-Id: I92e3460572feeb67d4a3d4d26af5f0ecaf7d3dd5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/173983
    Reviewed-on: http://review.coreboot.org/4892
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 6a360048a1a4f8eaebbf9c4ec75fe4a9543421b2
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Feb 13 10:30:42 2014 -0600

    haswell: backup the default SMM region on resume
    
    Haswell CPUs need to use the default SMM region for
    relocating to the desired SMM location. Back up that
    memory on resume instead of reserving the default
    region. This makes the haswell support more forgiving
    to software which expects PC-compatible memory layouts.
    
    Change-Id: I9ae74f1f14fe07ba9a0027260d6e65faa6ea2aed
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5217
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit b4b9eb399ef2f5539afce6e43b49d4cf1613ae9e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Feb 13 10:26:18 2014 -0600

    x86: provide infrastructure to backup default SMM region
    
    Certain CPUs require the default SMM region to be backed up
    on resume after a suspend. The reason is that in order to
    relocate the SMM region the default SMM region has to be used.
    As coreboot is unaware of how that memory is used it needs to
    be backed up. Therefore provide a common method for doing this.
    
    Change-Id: I65fe1317dc0b2203cb29118564fdba995770ffea
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5216
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit af5ca44784618aec5474991ac50adc3c73020f45
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Feb 13 07:20:13 2014 +0200

    intel/jarrell: Fix missing include
    
    To unconditionally get cmos_read().
    
    Change-Id: I0af0e85c8a1f42113bd32b51c4e29e86b3c28112
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5228
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 302cbd6c2e0859619c3ee668bc47362845faaccf
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Oct 21 12:36:17 2013 -0500

    baytrail: bring up APs
    
    Bring up the APs using x86 MP infrastructure.
    
    BUG=chrome-os-partner:22862
    BRANCH=None
    TEST=Built and booted rambi. Noted all cores are brought up.
    
    Change-Id: I9231eff5494444e8eb17ecdc5a0af72a2e5208b5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/173704
    Reviewed-on: http://review.coreboot.org/4889
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 70400284b94e1a4f21be0b97df361af71f363870
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Oct 21 12:11:17 2013 -0500

    rambi: add BSP lapic device
    
    There's some baked in assumptions internal to coreboot
    that the BSP's cpu device exists in the device tree. Therefore
    provide one in the device tree.
    
    BUG=chrome-os-partner:22862
    BRANCH=None
    TEST=Compiled and booted with other changes.
    
    Change-Id: I22ba10964760ee8efbc5bbd5d4ce65daf31b3839
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/173702
    Reviewed-on: http://review.coreboot.org/4887
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9956b72d567268dec936238f8da5e3e8451bfb8c
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Fri Oct 18 17:13:18 2013 -0700

    baytrail: Modify GPIO pull-up specification method
    
    Minor style changes to the way GPIO pull-ups are specified in
    board-specific GPIO maps. Intent is to allow calls to GPIO_FUNC macro
    from such maps.
    
    BUG=chrome-os-partner:22863
    TEST=Manual. Build + boot on bayleybay.
    
    Change-Id: I80134b65d22d3ad8a049837dccc0985e321645da
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/173748
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: David James <davidjames@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4886
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6c52ba77797c2ac62dcdb74e1bdd898003b9bc3b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Oct 16 09:21:55 2013 -0700

    rambi: disable internal pullups on ram_id[2:0]
    
    The ram_id[2:0] signals have stuffing options for pull up/down
    with values of 10K. However, the default pulldown values for these
    pads are 20K. Therefore, one can't read a high value because of
    the high voltage threshold is 0.65 * Vref. Therefore the high
    signals are marginal at best.
    
    Fix this issue by disabling the internal pull for the pads connected
    to ram_id[2:0].
    
    BUG=chrome-os-partner:23350
    BRANCH=None
    TEST=Built and checked that ram_id[2:0] is properly read now.
    
    Change-Id: Ib414d5798b472574337d1b71b87a4cf92f40c762
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/173211
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
    Reviewed-on: http://review.coreboot.org/4885
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f3f409bf5592dc093dc7f2dc1448ad21879c466e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Oct 11 08:39:54 2013 -0500

    baytrail: correct MMC pci location
    
    The original documentation was incorrect. Fix the pci
    device for the MMC port to reflect reality.
    
    MMC is at 00:17.0 with a device id of 0x0f50.
    
    BUG=None
    BRANCH=None
    TEST=Built.
    
    Change-Id: Ic18665b7dda5f386e72d1a5255e4e57d5b631eb0
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172772
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4884
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9d9d7f04296e2c6de5bd10ee4bff1a496006f9e1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Oct 11 00:44:06 2013 -0500

    baytrail: fix tsc rate
    
    Despite some references to a fixed bclk in some of the
    docs the bclk is variable per sku. Therefore, perform
    the calculation according to the BSEL_CR_OVERCLOCK_CONTROL
    msr which provides the bclk for the cpu cores in Bay Trail.
    
    BUG=chrome-os-partner:23166
    BRANCH=None
    TEST=Built and booted B3. correctly says: clocks_per_usec: 2133
    
    Change-Id: I55da45d42e7672fdb3b821c8aed7340a6f73dd08
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172771
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4883
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6f6a249a75927476ba5e06bb2b0a0138e0cf63ea
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Feb 9 19:21:30 2014 +0200

    usbdebug: Remove EHCI_DEBUG_OFFSET
    
    Read this variable from PCI configuration capabilities list instead.
    
    Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5176
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 6e56de3d202c2175a13c91ab2c1bc1eb0d7f652a
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Jan 25 21:46:10 2014 +1100

    Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.
    
    Step 2: change the Persimmon code to adapt it to the new board's hardware.
    
    The NF81-T56N-LF is a IPC form factor embedded board:
    - AMD Fusion G-T56N (1.65 GHz dual core) APU
      - 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V)
      - VGA and LVDS (via Analogix ANX3110)
    - AMD A55E (Hudson-E1) southbridge
      - 6x USB 2.0/1.1 ports
      - 5x SATA3 6Gb/s, 1x mSATA socket
      - 6-Channel HD Audio (via VIA VT1705)
      - PCI and ISA (via ITE IT8888)??
      - NEC uPD78F0532 microcontroller on I2C ("SEMA")??
    - 2x RJ45 GbE (via Realtek RTL8111E x2)
    - Fintek F71869AD Super I/O
      - PS/2 KB/MS port
      - RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
      - GPIO header
      - CIR header
    - 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)
    
    Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies*
    claiming the SPI flash is 16MB. They also use red pen over the chip
    so you wont see this deceit.
    
    Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/4801
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4726a87c9a615dc26733cd799f8c4b78670f9ae7
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Jan 25 07:40:39 2014 +1100

    Jetway NF81-T56N-LF [1/2]: create board by forking AMD Persimmon
    
    Step 1: copy all files unmodified from Persimmon.  This makes it much
    easier later to see how the two boards actually and deliberately differ
    when porting bugfixes from one to the other.
    
    Change-Id: I23e223049ed1c69e320e6b31efe4266bfeb97207
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/4800
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 80865c961915dd2ca866c8e59874098a6af3dbcb
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Feb 15 14:05:29 2014 +0100

    lenovo/x60: Change to common EDID framework.
    
    Currently lenovo/x60 gfx init provides vbe_mode_info_valid in
    incompatible way. Use EDID framework as do other inits.
    
    Change-Id: I887abd5a09064f26f473a2bf9caa2eb33e269c07
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5238
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7b54ca228e99c4ae86e74c33715cc33fc283d346
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Feb 15 23:42:43 2014 +0100

    lenovo/x60: Fix EDID byte-swapping.
    
    Change-Id: I75305ff7c5a8ba6142ef460e813acc014d9992bb
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5249
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit ffa839d3106e316cfe0c75539efbc8009c5cf2fe
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Dec 29 18:27:56 2013 -0500

    console/uart8250*: Remove inclusion of mc146818rtc.h
    
    The RTC functionality provided by the include is specific to x86, but
    is not used in these files.
    
    Change-Id: I82d0dfdb6e8b67bc81291a7a5d63ced91e095772
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4586
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 0f333071ef9151b89de3fcf6dc5c14dba596941a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 30 17:19:46 2014 -0600

    coreboot: infrastructure for different ramstage loaders
    
    There are 2 methods currently available in coreboot to load
    ramstage from romstage: cbfs and vboot. The vboot path had
    to be explicitly enabled and code needed to be added to
    each chipset to support both. Additionally, many of the paths
    were duplicated between the two. An additional complication
    is the presence of having a relocatable ramstage which creates
    another path with duplication.
    
    To rectify this situation provide a common API through the
    use of a callback to load the ramstage. The rest of the
    existing logic to handle all the various cases is put in
    a common place.
    
    Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5087
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e9aaa71fb1e05c4432d768d87071ef842c536cb4
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 30 15:48:29 2014 -0600

    x86: provide stage_exit() like arm
    
    The arm architectures have a stage_exit() function
    which takes a void * pointer as an entry point. Provide
    the same API for x86. This can make the booting paths
    less architecture-specific.
    
    Change-Id: I4ecfbf32f38f2e3817381b63e1f97e92654c5f97
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5086
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit efc5841ab404aa615306a233dcbcda225b9380b5
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jan 23 08:30:42 2014 +1100

    libpayload/ahci: Fix a warning by decompartmentalise the AHCI driver.
    
    Decompartmentalise AHCI driver into two parts, ATA and ATAPI. Add a few
    superficial comments while here. This also fixes a compiler warning.
    
    Change-Id: Ia1fd545b39868a81cbc311f6ffc786f9f1f61415
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/4783
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 09af15e09eed91c98d4b97446b6b5c445b90517d
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Feb 13 14:33:08 2014 -0600

    google/rambi: Do not select CHROMEOS in Kconfig
    
    CHROMEOS is the meant to be selected by the user. The correct variable
    for a mainboard to select is MAINBOARD_HAS_CHROMEOS. This will then
    default to a CHROMEOS build, but when the mainboard selects CHROMEOS,
    the user can no longer disable CHROMEOS.
    
    Change-Id: I78fb15a0a9fef733e2de064d6c09cf774b7bce78
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5218
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 87cc49bc5b2208d0a5e33786cd6be314fb9053ea
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Feb 4 10:46:51 2014 -0600

    crossgcc: Update IASL to latest version (20140114)
    
    Change-Id: I2450cad4a43907b8ca6d8f4d35932d7f451f71ea
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5116
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit b5fc67ab0216e3d3e0da0baa2e5e389a6f841958
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Mon Feb 10 12:08:36 2014 +1100

    superio/fintek: Document Fintek F71869AD code.
    
    Change-Id: I156077bf5571764d0e4bc044be80c8ab94556de4
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/5178
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 6d51f5dfe91139928572a2e18722a049b5543b38
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Jan 3 04:24:35 2014 -0500

    cpu/allwinner/a10: Add minimal ramstage driver
    
    Change-Id: I857755976b17b0e492c086162f395a77933eeed8
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4698
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3ccb3ce4157df2cdab6d9a2a02cc609ae2814567
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Oct 11 00:26:04 2013 -0500

    baytrail: print dram configuration
    
    After running the MRC blob print out some information
    on the training: MRC version, number channels, DDR3
    type, and DRAM frequency.
    
    Example output:
    MRC v0.90
    2 channels of DDR3 @ 1066MHz
    
    Apparently there are two dunit IOSF ports -- 1 for each
    channel. However, certain registers really on live in
    channel 0. Thus, there was some changes to dunit support
    in the iosf area.
    
    BUG=chrome-os-partner:22875
    BRANCH=None
    TEST=Built and booted bayleybay in different configs.
    
    Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172770
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4882
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1ce0b3022c723ca7c9f00cc884e8e3282cb0dcdb
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 10 12:47:47 2013 -0500

    baytrail: allow downstream use of SSE instructions
    
    If a payload is compiled to use SSE instructions it will
    fault with an undefined opcode because SSE instructions weren't
    enabled. Therefore enable SSE instructions at runtime.
    
    BUG=chrome-os-partner:22991
    BRANCH=None
    TEST=Built and booted with SSE enabled payload. No exceptions seen.
    
    Change-Id: I919c1ad319c6ce8befec5b4b1fd8c6343d51ccc1
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172642
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4881
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit dc249f690a46f00ae11bedd080a749d6f1e8df3e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 10 21:03:50 2013 -0500

    baytrail: add vboot ramstage verification
    
    Add suport for verifying the ramstage with vboot
    during romstage execution. Along with this support
    select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to
    cache the relocated ramstage 1MiB below the
    top end of the TSEG region.
    
    BUG=chrome-os-partner:23249
    BRANCH=None
    TEST=Built and booted with CONFIG_VBOOT_VERIFY_FIRMWARE=y
         selected.
    
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Change-Id: I355f62469bdcca62b0a4468100effab0342dc8fc
    Reviewed-on: https://chromium-review.googlesource.com/172712
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4880
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 42283e7994b6519c4d1786b840d439fb90be4fb0
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Tue Feb 11 23:19:02 2014 +0100

    Eliminate some ASL warnings
    
    The ASL compiler warned about "Control Method should be made Serialized
    (due to creation of named objects within)". This commit eliminates the
    warnings by changing those NonSerialized into Serialized.
    
    Change-Id: I639e769cf7a9428c34268e0c555a30c7dee1e04c
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Reviewed-on: http://review.coreboot.org/5189
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 76e25b66ae1975212b7863eb91437f92443bfef6
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Feb 12 15:54:47 2014 -0600

    google boards: Do not hardcode location of spd.bin
    
    spd.bin can reside anywhere in CBFS, and we only use CBFS APIs to
    access and read it. As such, there is no need to hardcode it, and it
    can collide with mrc.bin or mrc.cache on some boards. Do not use a
    specific position for spd.bin, but instead let cbfstool find the
    optimal placement.
    
    Change-Id: I496094d3c0de708813494095b7ac4be8addb4112
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5210
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 82e7d956efc6c860dbec2c6a66857a43e5c14504
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Fri Oct 11 12:39:48 2013 -0700

    baytrail: gpio: add configs for PU/PD functional pins
    
    Pull-ups and pull-downs can be active on functional pins. Add configs
    for these options so they can be specified on board GPIO maps.
    
    TEST=Manual on bayleybay. Verify that platform boots to payload load.
    BUG=chrome-os-partner:22863
    
    Change-Id: Ie4f77d8ce812f086cc8fe5a6bfcac59669f56f92
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172766
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5209
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit b3b008a9b6f3d50901e7b7cb68a8ad210dd74100
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Feb 11 10:43:21 2014 -0800

    falco: Add ACPI code to describe the I2C touchpad device
    
    If the SerialIO devices are put into ACPI mode then it is possible
    to use ACPI to instantiate the touchpad in the kernel without
    needing to have a platform level driver to do the binding.
    
    This is the "new way" of describing on-board I2C devices and the
    upstream kernel is starting to add ACPI IDs to drivers so they can
    be used in this fashion.  For the Cypress touchpad use a generic
    ACPI ID of "CYPA0000" to describe it.
    
    In order to support the proper scoping of the touchpad device under
    the appropriate I2C controller device the mainboard.asl file needs
    to be included after pch.asl so the I2C device exists.
    
    Change-Id: I81e053d27be478f3a19b6f9b13cd2b4fabcb88c0
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5194
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6c03160d48f9b2d1dfaf5a193893b011e71ac30e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Feb 11 10:34:06 2014 -0800

    lynxpoint: Do not put SerialIO devices into D3Hot in ACPI mode
    
    Remove the bit of code that was putting the SerialIO devices into
    D3Hot state when they are switched from PCI to ACPI mode.  Instead,
    add the appropriate ACPI Methods to allow the kernel to control the
    power state of the device.
    
    The problem seems to be that if the device is put in D3Hot state
    before it is switched from PCI to ACPI mode then it does not properly
    export its PCI configuration space and cannot be woken back up.
    
    Adding the ACPI Methods for _PS0/_PS3 allows the kernel to transition
    the device into D0 state only when it is necessary to communicate with
    the device, then put it back into D3Hot state.
    
    Change-Id: I2384ba10bf47750d1c1a35216169ddeee26881df
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5193
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2161c1d792fedecfad32587b6fde657c19d647d0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 11 19:56:57 2014 +0200

    PCI: Add capability list parser to romstage
    
    These are almost one-to-one copies from pci_device.c. However,
    devicetree has not been enumerated yet and we have no console.
    
    Change-Id: Ic80c781626521d03adde05bdb1916acce31290ea
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5196
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 2c78726897055553c362de37cf0aad25bd67cba3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Feb 12 14:45:02 2014 +0200

    PCI: Drop includes under cpu
    
    The files affected do not make any PCI configuration calls.
    If they did, the more correct includes would be pci_ops.h,
    pci_defs.h and pci_ids.h.
    
    Change-Id: I3e7f009371be6ea50318eaabf0c15500cb3f1210
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5200
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 318066fbc1c53d0686bde6626a406c039ec0b8f3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Feb 12 14:18:50 2014 +0200

    PCI: Guard pci.h with CONFIG_PCI
    
    Adding PCI functions for romstage in pci.h breaks ARMv7 build without
    this. Also fix two related includes to use pci_def.h instead.
    
    Change-Id: I5291eaf6ddf5a584f50af29cf791d2ca4d9caa71
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5199
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 8cde852ecf4dced16b342a2da31990e0caf8b92b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Feb 9 23:35:39 2014 +0200

    usbdebug: Split to USB host/device
    
    Top-level interface to console over USB mut not require low-level
    details of ECHI debug port internals.
    
    Change-Id: If3ca3b1f479e3f20976cd4abd8f5e682a58d5650
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5197
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 411bf97c22dde9943b892a0969470d8b07b23e27
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Tue Feb 11 23:20:14 2014 +0100

    winbond/w83627hf/acpi: Fix some ASL warnings
    
    There were ASL compiler warnings about "Size mismatch". This commit
    eliminates the warnings by changing the ASL declarations of those
    fields.
    
    Change-Id: If851ed4892ef6c96acbff861abd7001ab67d9d66
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Reviewed-on: http://review.coreboot.org/5190
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 3a7227852b87fb4963baa31e8c36bc504a007f4d
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sat Nov 2 03:40:39 2013 +1100

    utils/crossgcc: Refactor Makefiles for separate arm/i386.
    
    Refactor Makefile build system as decompartmentalise armv7a and i386
    targets from crossgcc.
    
    Change-Id: If93f62050810ba594c9925a9eb8ba9d04bc76459
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/4008
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit adc0a6352d315b105caf71bd676b0a3f168af1e0
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Tue Feb 11 22:19:35 2014 +0100

    hp/dl145_g1: Add missing copyright notes
    
    Missing copyright notes added.
    
    Change-Id: I55b320a169b1125017c63b7a2384078465e7ce6e
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Reviewed-on: http://review.coreboot.org/5188
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 3298eb2123a8f90f70821fd8f79dd29c9707523b
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Tue Feb 11 22:15:18 2014 +0100

    hp/dl145_g1: Fix some commented out code
    
    Some out-commented code contained variables which changed name.
    This commit fixes the "problem".
    
    Change-Id: I8d9168c9f4b2cb6810b3e4dfeff2155f3c08357d
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Reviewed-on: http://review.coreboot.org/5187
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 592d5277cce849fa354afea65c3898ddd9fb0f5d
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Tue Feb 11 22:13:06 2014 +0100

    hp/dl145_g1: Add HAVE_HARD_RESET
    
    This platform has a hard reset button
    
    Change-Id: Ic4d2f9382b6770654eea8842a37ad38cf12de459
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Reviewed-on: http://review.coreboot.org/5097
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit aaedecaea4748ca656c5fdf0fae529b9e7b5408d
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Tue Feb 11 22:51:03 2014 +0100

    hp/dl145_g1: Adding FID/VID and Powernow ACPI
    
    Add cool-n-quiet functionality which allows the OS to dynamic
    alter CPU voltage and frequency change in order to save power
    e.g. when the CPU load is low.
    
    Change-Id: I4c895a56bcf571d4276af192aeef87d120143063
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Reviewed-on: http://review.coreboot.org/5186
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit d907a3402e347633bac09013050a3d290c27d1f8
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 30 22:20:01 2014 -0600

    amd/cimx: fix sb(8|9)00 NULL type redefine
    
    It is inappropriate for chipset code to be redefining
    types -- especially NULL to a non-pointer type. There's
    only one non-straight forward change. A condition
    being checked was '!ptr_type == NULL' (0 as int). That
    check is actually 'ptr_type != NULL'.
    
    Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5088
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6ecdb68562989aec1362e3a99f3ed2e0012e1191
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 10 20:54:57 2013 -0500

    baytrail: add reset support
    
    Bay Trail has the following types of resets it supports:
     - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
     - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
     - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
     - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9
     - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to
       0xcf9 but with ETR[20] set.
    
    While these are documented this support currently provides support
    for 2nd soft reset as well as cold and warm reset.
    
    BUG=chrome-os-partner:23249
    BRANCH=None
    TEST=Built and booted.
    
    Change-Id: I9746e7c8aed0ffc29e7afa137798e38c5da9c888
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172710
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4878
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f92271db84d5f3e5fe4765213bfb9d6f1af241fb
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Thu Oct 10 13:41:19 2013 -0700

    rambi: Add platform GPIO configuration tables
    
    Configure GPIOs according to function on board.
    
    TEST=compile only.
    BUG=chrome-os-partner:22863
    
    Change-Id: Ic38eeb64149606f2d7a19cc7a0144cc7e24807b8
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172657
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4875
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8561460d6839e89a113525492beba485dbc0d2ea
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Wed Oct 9 15:29:46 2013 -0700

    rambi: Add ncore GPIO config tables
    
    gpncore config tables were previously missing -- add them.
    
    Also, make the baytrail GPIO/PAD LUTs easier to read.
    
    TEST=Manual. Build + boot on bayleybay.
    BUG=chrome-os-partner:22865
    
    Change-Id: I49a1b23c7ad4fb5f4c86618e8c78ea9a1a42f79d
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172510
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4874
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1f5eb1f78e839a5dc1454c20060ccca14a74deb5
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Oct 8 15:33:39 2013 -0500

    rambi: add per-sku SPD support
    
    There are currently 4 SKUs:
    0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
    0b001 - 4GiB total - 2 x 2GiB Hynix  H5TC4G63AFR-PBA 1600MHz
    0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
    0b011 - 2GiB total - 2 x 1GiB Hynix  H5TC2G63FFR-PBA 1600MHz
    
    Add each of the 4 spds to the build, and use the proper
    parameters to MRC to use the in-memory SPD information.
    
    BUG=chrome-os-partner:22865
    BRANCH=None
    TEST=Built. Noted 1024 bytes of SPD content.
    
    Change-Id: Ife96650f9b0032b6bd0d1bdd63b8970e29868365
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172280
    Reviewed-on: http://review.coreboot.org/4872
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5f8ad56358b04ba0b0752944d2ed643d4df9c480
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Oct 8 16:54:18 2013 -0500

    baytrail: move early init to before mainboard
    
    It's helpful to have a lot of the early init happen
    before the handoff to mainboard. One example of this
    need is having the BARs programmed so that the mainboard
    can read board-specific gpios.
    
    BUG=chrome-os-partner:22865
    BRANCH=None
    TEST=Built. Booted and saw console outout in bayleybay
         mainboard.
    
    Signed-off-by; Aaron Durbin <adurbin@chromium.org>
    
    Change-Id: I030d7b4f9061ad7501049e8e204ea12255061fbe
    Reviewed-on: https://chromium-review.googlesource.com/172290
    Tested-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4871
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 3b036f71075cb5860d41a8fb83cd885d2044181c
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Tue Oct 8 11:31:21 2013 -0700

    baytrail: Add functions to peek at GPIO input values
    
    - Add functions to peek at GPIO input pad values (need to be used from
      romstage for board ram_id GPIOs)
    - Modify UART GPIOs to use existing fn-assignment function
    
    TEST=Manual. Add debug print and verify that GPIO functions return input
    values. Also, verify UART still functions in romstage.
    BUG=chrome-os-partner:22865
    
    Change-Id: Ib2e57631c127a592cfa20ab6e2184822424e9d77
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172189
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4870
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit bb3ee8371160e7ffc4d2f4e6de870b7fa3e01d70
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Oct 7 17:12:20 2013 -0500

    baytrail: set max frequency early in romstage
    
    Set the BSP to operate at max frequency early in romstage.
    The call to punit_init() is when the frequency actually ramps as
    that makes the punit actually start working.
    
    BUG=chrome-os-partner:22857
    BRANCH=None
    TEST=Built and booted. Noted operating frequency status is max.
    
    Change-Id: Icfd9e5c7682aa21fc740bd687607ca6a66597d5e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172131
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4869
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 08a4613219f5a26a2bcf1216deeb08284cb5269a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Oct 7 16:24:44 2013 -0500

    baytrail: adjust cache policy during romstage
    
    The caching policy for romstage was previously using a 32KiB
    of cache-as-ram for both the MRC wrapper and the romstage stack/data.
    It also used a 32KiB code cache region. The BWG's limitations for
    the code and data region before memory is up was wrong. It consists
    of a 16-way set associative 1MiB cache. As long as enough addresses
    are not read there isn't a risk of evicting the data/stack.
    
    Now create a 64KiB cache-as-ram region split evenly between romstage
    and the MRC wrapper. Additionally cache the memory just below
    4GiB in CBFS size. This will cover any code and read-only data needed.
    
    BUG=chrome-os-partner:22858
    BRANCH=None
    TEST=Built and booted quickly with corresponding changes to MRC warpper.
    CQ-DEPEND=CL:*146175
    
    Change-Id: I021cecb886a9c0622005edc389136d22905d4520
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172150
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4868
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 3f5a1ffb83895b325ec54ba0a6d0147f0af5fca8
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Oct 4 15:23:31 2013 -0500

    baytrail: add punit access functions
    
    Like the bunit and dunit, add the punit accessor functions.
    
    BUG=chrome-os-partner:23085
    BRANCH=None
    TEST=Built.
    
    Change-Id: Ifd7184dfca8c0491c107bc1c562ea1ded444e372
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171931
    Reviewed-on: http://review.coreboot.org/4867
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0b132c3ae3e36a94c594e171b6d17a06d8c759cf
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Fri Oct 4 11:47:21 2013 -0700

    baytrail: make default GPIO configs closer to power-on defaults
    
    - Set config0 defaults for hysteresis disable, pad bypass, etc.
    - Set config1 power-on defaults.
    - Set pad_val for input as default.
    
    BUG=chrome-os-partner:22863
    TEST=Manual. Enable GPIO_DEBUG and verify pad registers are set
    according to expectation. Also verify bayleybay still boots to payload
    loading.
    
    Change-Id: I0f1c9e4d4f39c5c56d7e14a82eb4825612e19420
    Reviewed-on: https://chromium-review.googlesource.com/171903
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4866
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 5a5c886b8d7b191f6d2842af84e3dcfa3e3a6e39
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jan 26 14:41:54 2014 +0200

    SMP: Add arch-agnostic boot_cpu()
    
    We should not have x86 specific includes in lib/.
    
    Change-Id: I18fa9c8017d65c166ffd465038d71f35b30d6f3d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5156
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 972d5cf040aebbb8052767a4a88ad99a961ad2bf
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jan 26 14:44:18 2014 +0200

    Move hexdump32() to lib/hexdump.
    
    Needs printk and is not a console core function.
    
    Change-Id: Id90a363eca133af4469663c1e8b504baa70471e0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5155
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 4d77ed9d99af5442d9fce889ce2199de773c4f08
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Feb 7 03:58:24 2014 +0100

    Kconfig: Move vendorcode menu up from the bottom to above Chipset menu
    
    Change-Id: Ic97a497a634533f44d94df297ca6e35d94c34565
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/5160
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 7c9bb41817988287c74f83512541355e7818c57f
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Jan 29 16:55:48 2014 -0600

    cbfstool/lzma: Remove code which depends on commented out defines
    
    These options seem to control the behavior of the encoder/decoder,
    with comments citing a trade-off between memory usage and performance.
    I removed these in a separate patch to make reverting in the future
    easier, if we find these options are useful.
    
    Change-Id: I24cb7101b89e60f4fb96777e3681c03d2a62e3d5
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5084
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c1d1fd850ee7b8e52bd2ea5064fab68ac0c27098
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Feb 5 01:10:08 2014 -0600

    cbfstool: Deserialize CBFS master header when reading image
    
    Rather than  using [hn]to[nh] whenever accessing a member of the CBFS
    header, deserialize the header when opening the CBFS image. The header
    is no longer a pointer inside the CBFS buffer, but a separate struct,
    a copy of the original header in a host-friendly format. This kills
    more of the ntohl usage.
    
    Change-Id: I5f8a5818b9d5a2d1152b1906249c4a5847d02bac
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5121
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2516f2e467afcb263aa0ea2a18ea7c289e7bf10f
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Sat Feb 8 00:17:21 2014 +0100

    hp/dl145_g1: Adding ACPI support
    
    Basic ACPI support for this old platform. Created by copying and
    tweaking similar motherboard ACPI implementations in coreboot.
    Works reasonably well under Linux, providing HPET-timers
    and more under linux (tested under OpenSUSE 12.2 kernel 3.4.63-2.44).
    Not tested under Windows.
    
    Change-Id: I69431be962a0d272db398ecf4ac9f0249de8ebab
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Reviewed-on: http://review.coreboot.org/5185
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit cb141bce35d6b0ee08a14c1097fa19bc10e4d9e7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Feb 7 19:24:23 2014 +0200

    usbdebug: Split PCI EHCI part
    
    There are EHCI compatible host controllers on ARM without PCI bus
    architecture. Currently we have not come across one with the debug
    capability though.
    
    Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5175
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 48e899d2d5d7adfccecbde5b75b7d8e7a1394af4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jan 21 10:44:08 2014 +0200

    usbdebug: Fix data toggle on receive
    
    USB device end toggles data PID when we ACK'd the zero-length data
    packet. As USB host we need to toggle data PID too or the next data
    received would get discarded.
    
    Change-Id: I3203bc874c7ded9244c7548a666d7041a0fbb379
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4775
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 089b88c165468367e176d5bcc022b3702f499234
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jan 18 12:26:13 2014 +0200

    usbdebug: Remove duplicate port claim
    
    This claim is useless when done before EHCI controller reset. Code in
    usbdebug_init_() already sets this properly after reset, see use of
    DBGP_OWNER.
    
    Change-Id: Ic17493fe4edbbbed6ebcbef35a264fbf188f1fba
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4709
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 0108bf5157de24619f644721a82775d578087573
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jan 15 22:26:03 2014 +0200

    usbdebug: Improve receive speed
    
    Read from USB endpoint_in 8 bytes at a time, the maximum what
    EHCI debug port capability has to offer.
    
    Change-Id: I3d012d758a24b24f894e587b301f620933331407
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4700
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit ed87ebc3259abea8f952a7ffd785f670a779bde2
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Jan 29 17:02:55 2014 -0600

    cbfstool/lzma: Remove LITTLE_ENDIAN_AND_UNALIGNED_ACCESS_OK
    
    This was designed as a micro-optimization for x86, but it is only used
    once. Let the compiler decide if optimizing this is worth the effort.
    
    Change-Id: I5939efa34f0e9d16643893ca04675247842e7db5
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5085
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b63b75b0f7262a4a28b6c1e147f81edcfebf37d2
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Jan 29 14:56:20 2014 -0600

    cbfstool: Fix LzmaEnc.c and build with -Wshadow
    
    LzmaEnc.c was full of shadow definitions. Luckily, shadow definitions
    were not used after the scope in which they were redefined, so it is
    possible to just remove them.
    
    Tested by successfully booting qemu i440fx to grub2 payload.
    
    Change-Id: I01d44db59882114ffe64434b655b931f3beec8e2
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5082
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ae45a9884b82c2e2bfcf87afeb45260706a27adc
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Jan 29 14:27:52 2014 -0600

    cbfstool: Fix build errors when building with clang
    
    Now that we can set CC to an arbitrary compiler, fix issues that clang
    finds. Luckily, there were only two trivial errors.
    
    Change-Id: I0fd1f0f263a8ab7004f39cd36ed42d1a1cba5c04
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5081
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b33384a03c903d4a12a4e4f2805bfb53ff96ff3d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Feb 8 18:58:39 2014 +0100

    device_util: Make device in dev_find_slot_pnp u16.
    
    LDN is 8-bit but coreboot squeezes unrelated info: VLDN in this field.
    Increase to 16-bit to handle this.
    
    Change-Id: I97af1b32dcfaed84980fa3aa4c317dfab6fad6d8
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5165
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit ca4f4b8c9eef77fbcad0af3b21885a337a1f2c83
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Sat Feb 8 15:41:52 2014 -0600

    mtrr: only add prefetchable resources as WRCOMB for VGA devices
    
    Be more conservative and only add VGA devices' prefetchable
    resources as write-combining in the address space. Previously
    all prefetchable memory was added as a write-combining memory
    type. Some hardware incorrectly advertises its BAR as
    prefetchable when it shouldn't be.
    
    A new memranges_add_resources_filter() function is added
    to provide additional filtering on device and resource.
    
    Change-Id: I3fc55b90d8c5b694c5aa9e2f34db1b4ef845ce10
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5169
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Tested-by: build bot (Jenkins)

commit 892728c65fcd82cab43e334396b86fc257ecf256
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 13:01:47 2014 +0100

    boardstatus/towiki: Fix 1st gen i3/i5/i7 codename
    
    It was a typo.
    
    Change-Id: I82964b5ed7e7749ba141aeb3ee8dc4c107bcd7a9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5127
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit b845636ce67f6e7c96bf3fb3008738f596a5d5ce
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 12:21:40 2014 +0100

    boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs
    
    Change-Id: I3a38ca834606bb53e6f82cbe79c3a99288429aee
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5124
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 400c05cf25b50701d39cbd90b94420b80b3a4748
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Feb 4 14:34:11 2014 +0100

    device_util: Add dev_find_slot_pnp.
    
    Change-Id: I5223c54c8ddbc60a176e4d718730e99decc772a3
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5112
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 732cee31a6ab9b796043cb2455f4a19765a95c5a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Dec 23 12:14:13 2013 +0200

    ARMv7: Remove static CBMEM allocation
    
    The calculations for static allocation are no longer valid.
    
    Change-Id: I6740cdcec789abddf78485a0edaf24882ef8c2a5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4569
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit c79dfdb9910ba368e3473f758c84b0f24064833f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Feb 3 19:43:08 2014 +0200

    console: Drop IO and Oxford (PCI) UARTs on armv7
    
    Change-Id: Ia410b61c4babdfa3c984539527a9739462d3ad80
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5141
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 9a3acf6900e9ab22743f75a2a4ee4623e257f165
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Feb 3 13:07:59 2014 +0200

    console: Drop extra uart_init()
    
    This call is already in console_init().
    
    Change-Id: Ie0cb3595af514e37efac5ac5d474f52ba551bf22
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5140
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit e2f4c2a72f99c5069d4653bcb4c0589c44641268
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jan 30 16:45:29 2014 +0200

    uart8250: Drop includes in superio
    
    Change-Id: If723896cc31da75dbb3a63d5dc959764e96fded1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5139
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit d0281f15eb352ca8efca6f32c727a1f73f307f11
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 4 20:28:23 2014 +0200

    uart8250: Drop unused declarations
    
    Change-Id: Ie915ef9dbc45604bd5ca1b610acb12af634fdebe
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5138
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 2113099e49dff8c985763521b7ad9f1d1c6bb89c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jan 30 10:51:32 2014 +0200

    uart8250: Drop xmodem support
    
    Unused and hard-coded to use uart8250 on IO.
    
    Change-Id: I3f84c50039a450a2ae97a5fd2af89992f8567e6c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5137
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 03731d776ccfff69ba5380dbf7ae136ed8d5b30c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Feb 2 19:12:14 2014 +0200

    QEMU debugcon: Move under drivers/emulation/qemu
    
    Also prepare this console for use in romstage.
    
    Change-Id: I26a4d4b5db1e44a261396a21bb0f0574d72aa86d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5136
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>

commit 207379db12875b6b94956ef689f12789c805c2b8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jan 31 07:38:21 2014 +0200

    ne2k: Move under drivers/net
    
    Change-Id: I978b6009c09c31be4429f57be40ef82f438f7574
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5135
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5148642c56eaa66c1680963099e8460aea84dcae
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jan 31 07:38:21 2014 +0200

    spkmodem: Move under drivers/pc80
    
    Change-Id: I46eb17ab19cea8759b3e4822019285cbe907e83a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5134
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit e2227a23a73f2d68cd5d339559813eefc6942837
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Feb 5 13:02:55 2014 +0200

    usbdebug: Move under drivers/usb
    
    Also relocate and split header files, there is some interest
    for EHCI debug support without PCI.
    
    Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5129
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 9db1c4e51a24ca1d81cd0d764c01ddd612aab775
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 4 19:18:59 2014 +0200

    usbdebug: Drop obsolete code
    
    Change-Id: I918ca1d0d0d7bcb7e16d41a12830a0357f15b8ed
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5130
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 30fe6120ca8d7211f0055e47d3ecd569a628f2aa
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 23:25:28 2014 +0100

    MTRR: Mark all prefetchable resources as WRCOMB.
    
    Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5149
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 7a4fa0a32cf11a0686804afffbcd02827c846fcf
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 23:38:29 2014 +0100

    lib/memrange: Skip 0-sized resources.
    
    Change-Id: I44194153817b8e6b641e407fc4a9e0fd5bc3f318
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5152
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 5b9e3b60516d5255962604db7530089103f83ec1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Feb 5 16:00:43 2014 -0600

    mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocation
    
    If the MTRR usage exceeds the BIOS allocation for MTRR usage
    re-try without the WRCOMB type.
    
    Change-Id: Ie70ce84994428ff6700c36310264c3c44d9ed128
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5151
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Tested-by: build bot (Jenkins)

commit ed9307db13671ee347a3f1288e87da508139feea
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Feb 5 15:44:30 2014 -0600

    memranges: add memranges_update_tag() functionality
    
    The memranges_update_tag() function replaces all instances
    that are tagged with old_tag and update to new_tag. This
    can be helpful in the MTRR code by adjusting the address
    space if certain memory types cause the MTRR usage to
    become too large.
    
    Change-Id: Ie5c405204de2fdd9fd1dd5d6190b223925d6d318
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5150
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 17:00:40 2014 +0100

    load_payload: Use 32-bit accesses to speed up decompression.
    
    Flash prefers 32-bit sequential access. On some platforms ROM is
    not cached due to i.a. MTRR shortage. Moreover ROM caching is not
    currently enabled by default. With this patch payload decompression
    is sped up by theoretical factor of 4.
    
    Test on X201, with caching disabled:
    
    Before:
      90:load payload                  4,470,841 (24,505)
      99:selfboot jump                 6,073,812 (1,602,971)
    
    After:
      90:load payload                  4,530,979 (17,728)
      99:selfboot jump                 5,103,408 (572,429)
    
    Change-Id: Id17e61316dbbf73f4a837bf173f88bf26c01c62b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5144
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 79c712cb9e35ea9c0f383c047b4aa9590b64496d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Feb 5 19:10:03 2014 +0100

    lenovo/x201: Enable flash prefetching.
    
    Speeds up coreboot and especially payload load.
    
    Before:
      90:load payload                  4,530,979 (17,728)
      99:selfboot jump                 5,103,408 (572,429)
    
    After:
      90:load payload                  4,390,051 (14,849)
      99:selfboot jump                 4,505,966 (115,915)
    
    Change-Id: I45c3042594cda16ab3adde6472e00ec1b2d2a688
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5145
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 3fcde22a30fc26fa299d4e26a9cc0bde7eb0356d
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Feb 4 17:35:44 2014 -0800

    Add an xdr function for the cbfs_file header
    
    And use it in fit.c and remove one more use of htonl.
    
    Change-Id: Ibf18dcc0a7f08d75c2374115de0db7a4bf64ec1e
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/5120
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c625d0983c6427277c3f6ebd9911def76d6351c9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Oct 4 16:00:07 2013 -0500

    mainboard/google: add initial rambi mainboard support
    
    BUG=chrome-os-partner:23121
    BRANCH=None
    TEST=None
    
    Change-Id: I283415be326e2d92e1e1bf7866954f17a7266edb
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171940
    Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
    Reviewed-on: http://review.coreboot.org/4865
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 189aa3e2aec9ca6446d8425a3ec3a11cb4b5c696
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Oct 4 11:17:45 2013 -0500

    baytrail: initialize punit
    
    The punit is responsible for a number of things. Without
    performing the sequence included it won't change processor
    frequency when requested and apparently there are some bizarre
    hangs introduced if this sequence isn't included either. Lastly,
    this needs to come after microcode has been loaded. As that is
    done in bootblock the ordering is correct.
    
    One other side effect is that this fixes the graphics devices'
    device id. Before it was showing up as the same device id of the
    SoC transaction router.
    
    BUG=chrome-os-partner:22880
    BUG=chrome-os-partner:23085
    BUG=chrome-os-partner:22876
    BRANCH=None
    TEST=Built and booted.
    
    Change-Id: Ib7be1d4b365e9a45647c778ee5f91de497c55bf1
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171862
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4864
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c0270aa6d0e183ceb04566b6e9e3939bd9215d35
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Oct 4 11:15:48 2013 -0500

    baytrail: load microcode in bootblock
    
    Start loading microcode in the bootblock. This way
    no caching has been set up and cache-as-ram mode
    will be running in a validated configruation (with ucode
    patch).
    
    BUG=chrome-os-partner:22858
    BRANCH=None
    TEST=Built and booted. Confirmed microcode is loaded.
    
    Change-Id: I6fd1d8e55bcc9d799b11d9faed771ac50dc120a2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171861
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4863
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fd039f7f4d84b1c04dba81874068f8ea94620f87
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Oct 4 11:11:52 2013 -0500

    baytrail: disable tco timer
    
    The TCO timer always starts ticking out of reset.
    However, depending on microcode loading and punit
    initialization the TCO timing out has a different
    impact on the sytem. Without loading microcode
    or initializing the punit the tco times out and
    nothing happens. However, when microcode is loaded
    a timeout will reset the system. Lastly, if the
    punit is initialized but the microcode isn't loaded
    the TCO timeout will shut down the system.
    
    To fix all the weird symptoms disable the TCO.
    
    BUG=chrome-os-partner:22858
    BRANCH=None
    TEST=Built and booted with microcode loading. Reset doesn't
         occur.
    
    Change-Id: I49cd62f510726a96bf734ae728a352c671d1561e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171860
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4862
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a64ef62ca4da18f0b6c8f6949c659c81fb68c418
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 3 12:56:37 2013 -0500

    baytrail: program PUNIT memory-mapped base address
    
    Apparently there was another BAR living at 0x5c in the LPC
    bridge that mapped the PUNIT registers. EDS 2.0 released
    and this register is now documented.
    
    BUG=chrome-os-partner:23085
    BRANCH=None
    TEST=Built and booted.
    
    Change-Id: I5892c2a14923b57826060e92b4335cb1952ea057
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171612
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4861
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 51ca694a970705cd06925b508f3e6244331fa841
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 3 09:01:45 2013 -0500

    baytrail: add 316 microcode
    
    The 316 microcode is the newest version. Include that in the build.
    
    BUG=chrome-os-partner:22858
    BRANCH=None
    TEST=Built and partially booted with microcode loading. Noted 316
         loaded.
    
    Change-Id: Iba01dd58688737ae38bc58a84014ee9526540db1
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171611
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4860
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3f00d29800c52ad8ccef51cb65b96c01be95362a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 3 08:57:17 2013 -0500

    baytrail: additional iosf changes
    
    Allow for one to write an individual byte of a 32-bit register
    when sending a read/write through the IOSF messaging system.
    Add PUNIT registers and fields for early sequencing.
    
    BUG=chrome-os-partner:23085
    BRANCH=None
    TEST=Built and partially booted with changes that use PUNIT
         registers and individual byte en fields.
    
    Change-Id: I929fb5c51d805c55c478cab884e3572254987fc7
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171710
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4859
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 833ff353b71c6d473b7fdfa75e464599dd03d976
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Oct 2 11:06:31 2013 -0500

    baytrail: import and use updated mrc_wrapper.h
    
    The mrc_wrapper.h was changed to protect against ABI differences
    between the two sets of compilers and flags used. This requires
    a prope shim for the console output funciton.
    
    BUG=chrome-os-partner:23048
    BRANCH=None
    TEST=Built and booted successfully.
    
    Change-Id: I976e692e66dcfc0eacadae6173abfd9b81e31137
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171580
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4858
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c04e171467c61668d9ffefebf363858937c3e477
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Fri Sep 27 16:21:04 2013 -0700

    baytrail: Rearrange config options alphanumerically
    
    This is a no-op change for easier maintenance.
    
    BUG=none
    TEST=manual
        . baitrail coreboot still builds and runs
    
    Change-Id: I0c0bd78c6f361e8f81979f19cce148e7f51865ee
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/171002
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4857
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 794bddf97c1c07f5fd12f073f4f5da3f476a1f07
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Sep 27 11:38:36 2013 -0500

    baytrail: start collecting timestamps
    
    This commit always selects COLLECT_TIMESTAMPS and starts
    tracking TSC values from the early stages of bootblock.
    The initial timestamp value is saved in mm0 and mm1 while
    in bootlbock. This approach works because romcc is not configured
    to use mmx registers for its compilation.
    
    Additionally, the romstage api with the mainboard was changed to
    always pass around a pointer to a romstage_params structure as the
    timestamps are saved in there until ram is up.
    
    BUG=chrome-os-partner:22873
    BRANCH=None
    TEST=Built and booted with added code to print out timestamps at
         end of ramstage. Everything looks legit.
    
    Change-Id: Iba8d5fff1654afa6471088c46a357474ba533236
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170950
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4856
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 818f369da2b0c0df553fd41aad966869653a1d91
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Feb 4 08:29:35 2014 -0800

    Change the linux payload generator to use the standard header generator
    
    When I changed mkpayload, I did not realize we had a duplicate
    block of code in the linux payload code. Have it use the same
    header generator as the standard payload code does.
    
    Change-Id: Ie39540089ce89b704290c89127da4c7b051ecb0e
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/5115
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 35850ae88e0be8d05ab672d5badcd89ab8006389
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Feb 2 22:37:28 2014 -0600

    cbfstool: Eliminate global variable "arch"
    
    Now that unused functions have been removed, the global "arch" is only
    used in very few places. We can pack "arch" in the "param" structure
    and pass it down to where it is actually used.
    
    Change-Id: I255d1e2bc6b5ead91b6b4e94a0202523c4ab53dc
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5105
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 2bdc0d0bd6de826588d5ceda139d021922db5e48
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Feb 2 22:13:31 2014 -0600

    cbfstool: Remove more unused functions from common.c
    
    A lot of the early functions have been re-implemented in a context-
    centric mode, rather than relying on global variables. Removing these
    has the nice side-effect of allowing us to remove more global
    variables.
    
    Change-Id: Iee716ef38729705432dd10d12758c886d38701a8
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5104
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit c677c7d6e43c1f88ddfbd86ff32c81425f665596
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Feb 2 21:34:15 2014 -0600

    cbfstool: Hide cbfstool_offset from the global namespace
    
    This is part of a larger effort to reduce global variable usage in
    cbfstool. cbfstool_offset is particularly easy to hide since it's only
    used in common.c .
    
    Change-Id: Ic45349b5148d4407f31e12682ea0ad4b68136711
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5102
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit f592c08b68f78bf3c7feef9ea8a420a10e28338d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Feb 4 15:11:45 2014 +0100

    pcengines/alix2c: Add ALIX.2C as a clone of ALIX.2D.
    
    According to vendor (Pascal Dornier) they're the same from coreboot
    perspective.
    
    Change-Id: I43aeb77f21c251b3d9c5c2dcfa01d4d1de0bc87b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5114
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fbdbcb713f1f1f184604a3a63e34904ee37a58d9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jan 31 20:32:54 2014 +0200

    AMD cimx/sb800: Set SPI frequency and prefetch
    
    Broken with/since commit d1cb0eec.
    
    Original intention was to set the frequency for 'Fast Read' command
    in bits 15..14, and enable 'Fast Read' command.
    
    Modified register contains SPI frequency for 'Normal Read' command
    in bits 13..12. Default for this is 11b for 16.5 MHz. Existing code
    unintentionally clears these bits, increasing SPI frequency to 66MHz
    for 'Normal Read' command.
    
    This is above specifications for many common SPI flash components
    and also makes flashrom older than 0.9.7-r1750 to operate unreliably
    on read/write/erase for these platforms.
    
    Change-Id: I30109e2a0410c0bb0bdc968ea71787396b32e761
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/5089
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit d9b5d897d7f05d0ee8f9411628b757beea990b4b
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Sun Feb 2 12:23:52 2014 +0100

    cpu/amd/model_fxx: Add coolnquiet for two new (old) AMD K8 models
    
    The added CPU's are OSA248CEP5AU and a OSP280 processors.
    The OSP280 VID/FID numbers have been found by experimentation
    and extrapolation/guesses from similar models. It has been
    verified to work fine under Linux (OpenSuse 12.2, kernel
    3.4.63-2.44) with four different test-processors.
    Windows is untested.
    
    Change-Id: I3afa1cba5f55c8a78917b3636382af7706a80fee
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Reviewed-on: http://review.coreboot.org/5095
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit bc06691a3bcb799954074bbff8846db5fd31afe6
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Feb 2 21:48:18 2014 -0600

    cbfstool: remove unused function create_cbfs_image()
    
    It's not used anymore. Instead, we have the better replacements
    cbfs_image_create() and cbfs_image_from_file().
    
    Change-Id: I7835f339805f6b41527fe3550028b29f79e35d13
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5103
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ebe3b3cfe212a2e985e12f1ab93bdef4487733f5
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Thu Sep 26 16:44:14 2013 -0700

    baytrail: Add GPIO initial configuration infrastructure.
    
    During ramstage, call mainboard_get_gpios to get initial GPIO configuration
    from the mainboard code, then initialize GPIOs as requested.
    
    BUG=chrome-os-partner:22863
    TEST=Manual. Using bayleybay GPIO table, set UART GPIOs to 'function 1',
    and verify UART still works after GPIO configuration. Also, verify
    legacy GPIO config is functional by toggling test pin.
    
    Change-Id: Ic58d8ddd15c4dc48a751a83f6d26c7809c1efc42
    Reviewed-on: https://chromium-review.googlesource.com/170306
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4855
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Jan 24 14:38:10 2014 +0100

    lenovo/x230: Enable msata port.
    
    Port 2 is used by msata. Enable it.
    
    Change-Id: Ib75227f64c9d77f6cfca1902a78d63b5cdd23d76
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4789
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit b5adeee1cc961da60fe72e3226d3a0aeb60306e4
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Mon Jan 6 08:38:15 2014 -0800

    cbfstool: add code to serialize the header using the new xdr functions
    
    This change adds a header serialization function. Programmers can thus just
    set up a header as needed, without worrying about forgetting if and how to
    use the [hn]to[hn]* functions.
    
    In the long term, we will work to remove swab.h, i.e. we need to get to the
    point where programmers don't have to try to remember [hn]to[nh]* and where
    it goes. To date, even the best programmers we have have made an error with
    those functions, and those errors have persisted for 6 or 7 years now. It's
    very easy to make that mistake.
    
    BUG=None
    TEST=Build a peppy image and verify that it's bit for bit the same. All
         chromebooks use this code and build and boot correctly.
    BRANCH=None
    
    Change-Id: I0f9b8e7cac5f52d0ea330ba948650fa0803aa0d5
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/181552
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/5100
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a8a133ded34d82a7baa9a439969eae780a501992
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Mon Dec 30 13:16:18 2013 -0800

    Add section header parsing and use it in the mk-payload step
    
    This completes the improvements to the ELF file parsing code.  We can
    now parse section headers too, across all 4 combinations of word size
    and endianness. I had hoped to completely remove the use of htonl
    until I found it in cbfs_image.c. That's a battle for another day.
    
    There's now a handy macro to create magic numbers in host byte order.
    I'm using it for all the PAYLOAD_SEGMENT_* constants and maybe
    we can use it for the others too, but this is sensitive code and
    I'd rather change one thing at a time.
    
    To maximize the ease of use for users, elf parsing is accomplished with
    just one function:
    
    int
    elf_headers(const struct buffer *pinput,
    	    Elf64_Ehdr *ehdr,
    	    Elf64_Phdr **pphdr,
    	    Elf64_Shdr **pshdr)
    
    which requires the ehdr and pphdr pointers to be non-NULL, but allows
    the pshdr to be NULL. If pshdr is NULL, the code will not try to read
    in section headers.
    
    To satisfy our powerful scripts, I had to remove the ^M from an unrelated
    microcode file.
    
    BUG=None
    TEST=Build a peppy image (known to boot) with old and new versions and verify they are bit-for-bit the same. This was also fully tested across all chromebooks for building and booting and running chromeos.
    BRANCH=None
    
    Change-Id: I54dad887d922428b6175fdb6a9cdfadd8a6bb889
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/181272
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/5098
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 25fc8d181fde674fb35ad56c841ffb3b4b0489e9
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Feb 2 11:48:48 2014 +0100

    drivers/i2c/at24rf08c/lenovo_serials.c: Remove trailing whitespace
    
    The trailing whitespace breaks the Git commit hook
    `util/lint/lint-stable-003-wihitespace`. So remove it.
    
    Change-Id: I70e4ac71529884a9a4fabf2aa9a4ea6e0323b9d4
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/5092
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 566b4f008f51a5ea3eee9356ed80322f34c36017
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Jan 12 00:23:30 2014 +0100

    AGESA f15tn: Fix GPP ports resume
    
    The AGESA resumes the GPP ports in the romstage using FchInitResetGpp(),
    which does FchGppPortInitS3Phase() for S3 resume. The PreInitGppLink()
    looks into CMOS to figure out what ports to just force to Gen1 or
    Gen2 PCIe. Then boot continues and in the ramstage the rest of GPP
    init is executed. There is a problem that nobody sets properly the
    PortDetected flags in the S3 path. As the consequence FchGppDynamicPowerSaving()
    thinks the GPP port is not enabled and shut downs it.
    
    The best fix would be also to remove the CMOS dependency which
    might be some left over, because AGESA does not use CMOS much for
    anything else. There could be also some way how to pass the GPP state
    structure from romstage to ramstage possibly via hudson/resume.c
    but I don't know how to do that. Similar problem is that the "late"
    stage of init again "forgets" the PortDetected state.
    
    This fix fixes the resume issue on Asus F2A85-M. With this patch applied
    both GPP ports (used as PCIe x1 and internal ethernet) are working again
    after resume.
    
    Change-Id: Idaf609043abb09441c6790504d66d23e0637588f
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/4671
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d69757bd4ed9f39deae15d08d3f0988e068480be
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Jan 21 09:45:15 2014 +0100

    lenovo/x201: Skip AT24RF08 detection.
    
    AT24RF08 was inherited from RE of original BIOS. As we don't really care
    if the chip in question is really AT24RF08 or a generic replacement,
    we can skip this check.
    
    Change-Id: I862dd66b2332314beb835f215f1c1cd838aa07b9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4769
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 707b35bcddf798674adb85efe63499d2ebfa48fc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Jan 20 03:03:38 2014 +0100

    pcengines/alix6: Make clone declaration in line with other clones.
    
    Change-Id: I4e56f6b37314bff569728b732b4115fb940f70dd
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4756
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 55f9a731b8c6bec598871943bd613187c8546ac3
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Mon Dec 2 10:18:04 2013 +0800

    AMD hudson and yangtze: add IMC fan control support
    
    imc_reg_init: init fan control related registers.
    enable_imc_thermal_zone: AGESA does not enable thermal zone. We enable
    it here.
    
    Change-Id: I93c729982d78b6d2c7c20bcb1a3e27a7dd0eba91
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/4300
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 62adc4c6101749d59bdcc36135556fc2d2482131
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 23 09:06:08 2014 +0100

    lenovo: Handle EEPROM/RFID chip.
    
    EEPROM/RFID chip present in thinkpad should be locked in a way to avoid
    any potential RFID access.
    
    Read serial number, UUID and P/N from EEPROM.
    
    This info is stored on AT24RF08 chip acessible through SMBUS.
    
    Change-Id: Ia3e766d90a094f63c8c854cd37e165221ccd8acd
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4774
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 5f20dbfbe38c6a7797b578f46006299a73d1bd90
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Jan 27 23:57:44 2014 +0100

    ibexpeak: add smbus_write_byte
    
    Change-Id: I045f1cff794d3c965c502fff98dd2442af2143bd
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4839
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit e57718f522d3324bf9343200fabeb316700f49ed
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Jan 27 23:48:27 2014 +0100

    bd82x6x: Add smbus_write_byte
    
    Change-Id: Iaab076cc014a1ee463866c243636f4f71798ddc4
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4838
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit dec919890e2073d83679b0b0fcafa2114f33b826
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Jan 27 23:46:46 2014 +0100

    smbus: Add guards to avoid calling NULL.
    
    Many of SMBus functions are unavailable on many controllers.
    While calling unavailable function is bad, it shouldn't lead
    to spectacular crash.
    
    Change-Id: I7912f3bbbb438603893223a586dcedf57e8a7e28
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4837
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 5ef4220693aa727094b7cd9cadfaab51a13ed3e9
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Feb 1 16:24:22 2014 +0100

    cpu/intel/model_2065x: Add model 20652
    
    Found in some X201t.
    Tested on X201t.
    
    Change-Id: I3fc4c3f5b1abf9fe61746ab8f401d1b6ee67f3ea
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/5090
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 452d31ad752cff53776b1780e2dac76c67575997
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Sep 24 16:47:49 2013 -0500

    baytrail: introduce pattrs
    
    The pattrs structure is intended for the supporting coreboot
    code to reference instead of going back to the source of
    the values (msrs, cpuid, etc). It essentially serves as a global
    structure for collecting attributes about the platform/processor.
    
    Additionally, the implementation provides a point during boot to
    hoook work before device enumeration/initialization by providing
    a init() function to soc_intel_baytrail_ops that is called before
    device work in the boot state machine.
    
    BUG=chrome-os-partner:22862
    BUG=chrome-os-partner:22863
    BRANCH=None
    TEST=Built and booted. Noted pattrs output.
    
    Change-Id: I073da8aca29635146fb0d4a2625b2b7564fd8414
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170403
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4854
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4c53df47302968fd6f90261d84c9d3c0f8e7bbc2
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Sep 23 14:17:35 2013 -0500

    baytrail: add dunit access and registers
    
    The dunit on baytrail is the dram unit. Provide a means
    to access the configuration registers there using the
    proper IOSF mechanisms.
    
    BUG=chrome-os-partner:22875
    BRANCH=none
    TEST=Built and booted. Able to read dram registers.
    
    Change-Id: I4d5c019720a7883fe93f3e1860bcd57ce2ea6542
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170490
    Reviewed-on: http://review.coreboot.org/4853
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 191570ded853521ed2e54414ba33074ba7909a7d
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Sep 24 12:41:08 2013 -0500

    baytrail: set host memory map
    
    Prior to this commit the coreboot resource allocator
    was not using proper addresses. That's not surprising there
    wasn't any code to initialize the resources properly. This
    commit initializes the memory map accoring to the BUNIT
    registers.
    
    BUG=chrome-os-partner:22860
    BUG=chrome-os-partner:22862
    BRANCH=None
    TEST=Built and booted. Noted output for resource assignments
         is sane.
    
    Change-Id: Ice8d067d8b993736de5c5b273a0f642fa034a024
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170429
    Reviewed-on: http://review.coreboot.org/4852
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fda56a6bfdee8a1b0afea3618e466f2813368aeb
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Sep 24 12:29:57 2013 -0500

    baytrail: add common pci_operations
    
    The coreboot device modeling for pci devices wants
    a pci_operations structure for all devices. This structure
    just sets the subsystem vendor and device id. Add a common
    one that all the other pci drivers can use for Bay Trail.
    
    BUG=chrome-os-partner:22860
    BRANCH=None
    TEST=Built and booted while utilizing this new structure.
    
    Change-Id: I39949cbdb83b3acb93fe4034eb4278d45369e321
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170428
    Reviewed-on: http://review.coreboot.org/4851
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ecf90863898469c9fa8251eedb62ec8e064f25c9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Sep 24 12:36:14 2013 -0500

    baytrail: initialize graphics before MRC
    
    The graphics device needs to have its resource contraints
    initialized before running the reference code. Right now just
    use a 256MiB aperture, 32MiB of stolen memory data, and 2MiB
    GTT memory.
    
    BUG=chrome-os-partner:22869
    BRANCH=None
    TEST=Built and booted. Noted amount of stolen memory matches
         configuration as well as BAR size within the graphics
         device.
    
    Change-Id: I328bf858f288363187cf705d6340947393b5ff10
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170427
    Reviewed-on: http://review.coreboot.org/4850
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ba170b477514239daf92dc7f4333318c96f275bc
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Sep 23 14:15:42 2013 -0500

    baytrail: cache ROM space early in bootblock
    
    Take advantage of the cache early in bootblock. The
    intent is to speed up cbfs walking when trying to locate
    romstage.
    
    BUG=chrome-os-partner:22857
    BRANCH=None
    TEST=Built and booted.
    
    Change-Id: If03210103c9782390230915db3b4a9759d172dce
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170426
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4849
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 81d3a2277c002e8744e34773442dc239e1c217e9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Sep 23 13:18:16 2013 -0500

    baytrail: update microcode to version 313
    
    B2 and B3 steppings are now bumped to version 313.
    
    BUG=chrome-os-partner:22858
    BRANCH=None
    TEST=Built.
    
    Change-Id: I09ae5110b66c725e959e95fc15bc85ccf371495d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170425
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4848
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ba1f9aaa9e05b40b55235dbe981880f9aa5c5136
Author: Lubomir Rintel <lkundrak@v3.sk>
Date:   Tue Jan 28 16:52:48 2014 +0000

    utils: Install man pages as non-executable (chmod 644)
    
    This bothers rpmlint.
    
    Change-Id: I27d9cfac3ef6834ff87acc5a5ccbf332e59eeb1a
    Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
    Reviewed-on: http://review.coreboot.org/5075
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 9a7d7bcea5c3a7bbf956c0909af121a870af515e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Sat Sep 7 00:41:48 2013 -0500

    baytrail: add initial support
    
    The initial Bay Trail code is intended to support
    the mobile and desktop version of Bay Trail. This support
    can train memory and execute through ramstage. However,
    the resource allocation is not curently handled correctly.
    The MRC cache parameters are successfully saved and reused
    after the initial cold boot.
    
    BUG=chrome-os-partner:22292
    BRANCH=None
    TEST=Built and booted on a reference board through ramstage.
    
    Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/168387
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4847
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit ba6b07e88884c62b4075b4e7156fc205e7f7971e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Jan 14 17:28:33 2014 -0600

    cpu/intel: allow non-packaged scoped turbo setting
    
    In the past the turbo disable setting (bit 38) of the
    IA32_MISC_ENABLES msr has been package scoped. That means
    knocking the turbo disable bit down enabled turbo for the
    entire package. Sadly, that's no longer true on all Intel
    processors. Therefore, allow non-packaged scoped turbo
    setting by introducing the CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
    Kconfig option. It defaults to false which was the original
    assumption.
    
    BUG=chrome-os-partner:25014
    BRANCH=baytrail
    TEST=Built and ran both ways successfully.
    
    Change-Id: I71a31e76ff47878023081fc47da643187517b597
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/182405
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5047
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit cd3f8ad235b9fbcb21950004f9f31b019e43c08a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Oct 21 22:24:40 2013 -0500

    x86: Add SMM helper functions to MP infrastructure
    
    In order for the cpu code to start SMM relocation 2 new
    functions are added to be shared:
    - void smm_initiate_relocation_parallel()
    - void smm_initiate_relocation()
    The both initiate an SMI on the currently running cpu.
    The 2 variants allow for parallel relocation or serialized
    relocation.
    
    BUG=chrome-os-partner:22862
    BRANCH=None
    TEST=Built and booted rambi using these functions.
    
    Change-Id: I325777bac27e9a0efc3f54f7223c38310604c5a2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/173982
    Reviewed-on: http://review.coreboot.org/4891
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit d0520406ed3f7dc6a36d1b49b2623eafd0b498fb
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Oct 21 22:21:12 2013 -0500

    x86: add SMM save state for 0x0100 revision
    
    The Bay Trail SMM save state revision is 0x0100.
    Add support for this save state area using the
    type named em64t100_smm_state_save_area_t.
    
    BUG=chrome-os-partner:22862
    BRANCH=None
    TEST=Built and booted using this structure with forthcoming CLs.
    
    Change-Id: Iddd9498ab9fffcd865dae062526bda2ffcdccbce
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/173981
    Reviewed-on: http://review.coreboot.org/4890
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit e0785c03310574dcd96d5bbe878a1bae8c0f2a8c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Oct 21 12:15:29 2013 -0500

    x86: parallel MP initialization
    
    Provide a common entry point for bringing up the APs
    in parallel. This work is based off of the Haswell one
    which can be moved over to this in the future. The APs
    are brought up and have the BSP's MTRRs duplicated in
    their own MTRRs. Additionally, Microcode is loaded before
    enabling caching. However, the current microcode loading
    support assumes Intel's mechanism.
    
    The infrastructure provides a notion of a flight plan
    for the BSP and APs. This allows for flexibility in the
    order of operations for a given architecture/chip without
    providing any specific policy. Therefore, the chipset
    caller can provide the order that is required.
    
    BUG=chrome-os-partner:22862
    BRANCH=None
    TEST=Built and booted on rambi with baytrail specific patches.
    
    Change-Id: I0539047a1b24c13ef278695737cdba3b9344c820
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/173703
    Reviewed-on: http://review.coreboot.org/4888
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 75e297428f6a88406fa3e1c0b54ab3d4f411db5c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 10 20:37:04 2013 -0500

    coreboot: config to cache ramstage outside CBMEM
    
    Haswell was the original chipset to store the cache
    in another area besides CBMEM. However, it was specific
    to the implementation. Instead, provide a generic way
    to obtain the location of the ramstage cache. This option
    is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
    Kconfig option.
    
    BUG=chrome-os-partner:23249
    BRANCH=None
    TEST=Built and booted with baytrail support. Also built for
         falco successfully.
    
    Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172602
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4876
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 6ac3405fdff9277d73db9b03cf88ca8dcc9d4455
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 24 08:55:51 2013 -0500

    x86: include optional reference code blob in cbfs
    
    In order to incorporate external blobs into
    CBFS besides MRC have a notion of a reference code
    blob. By selecting HAVE_REFCODE_BLOB and providing
    the file name the refcode blob will be added to
    cbfs as a stage file.
    
    BUG=chrome-os-partner:22866
    BRANCH=None
    TEST=Using this option and other patches able to build,
         boot, and run blob code.
    
    Change-Id: I472604d77f4cb48f286b5a76b25d8b5bfb0c7780
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174423
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4895
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit f517c448a5b297662d061c03a5a89f5fd2e248e2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Dec 12 10:43:58 2013 -0800

    libpayload: Parse CBMEM ACPI GNVS pointer
    
    Pull the ACPI GNVS pointer from CBMEM and expose it in
    the sysinfo structure for use by payloads.
    
    BUG=chrome-os-partner:24380
    BRANCH=none
    TEST=build and boot rambi with emmc in ACPI mode
    
    Change-Id: I47c358f33c464a4a01080268fb553705218c940c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179900
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5016
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 2f6402c7a66acb7fd51794b190fbecfb852bcab4
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Nov 20 15:18:24 2013 -0600

    chromeec: allow override of i8042 interrupt
    
    Some boards need to override which IRQ the i8042 keyboard
    controller has its interrupt on instead of the default
    IRQ#1. The SIO_EC_PS2K_IRQ macro provides the mainboard
    an ability to override the interrupt location.
    
    BUG=chrome-os-partner:23965
    BRANCH=None
    TEST=Built and booted rambi using this option. New IRQ is correctly
         picked up by kernel allowing keyboard support.
    
    Change-Id: Ic2b222018dfc3aa30e24a31009e832ae0fb7e9cf
    Reviewed-on: https://chromium-review.googlesource.com/177222
    Tested-by: Bernie Thompson <bhthompson@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4978
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 58867b10028e97a323498d0be284243f769e7845
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Oct 24 12:37:48 2013 -0700

    chrome ec: Fix ASL to use IO() instead of FixedIO()
    
    FixedIO seems like a nice short version of IO but in reality
    it is limited to 10-bit ISA addresses and so should not really
    be used in most situations.
    
    Change all the references to use IO() directly instead.
    
    BUG=chromium:311294
    BRANCH=none
    TEST=emerge-samus chromeos-coreboot-samus and check for iasl
    warnings using updated iasl compiler revision 20130117.
    Boot the imge and ensure that EC regions are still exported
    in /proc/ioports.
    
    Change-Id: I54de65892bed9e43dbba916990cf2b70c370843c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174810
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4910
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 3a499c3a42e2d079c6c0c9600a3a8de928c30b6e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Dec 13 13:02:46 2013 -0800

    chromeos: provide option to identify reference code blob
    
    Certain platforms need to have reference code
    packaged and verified through vboot. Therefore,
    add this option.
    
    BUG=chrome-os-partner:22867
    BRANCH=None
    TEST=Built.
    
    Change-Id: Iea4b96bcf334289edbc872a253614bb1bebe196a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/180025
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/5022
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 16e899ba943f45b8506c3e75752adfc7dc2b52ba
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Dec 12 10:43:21 2013 -0800

    cbmem: Export ACPI GNVS cbmem pointer in coreboot table
    
    This will make it possible for payloads to find the ACPI
    NVS region which is needed to get base addresses for devices
    that are in ACPI mode.
    
    BUG=chrome-os-partner:24380
    BRANCH=none
    TEST=build and boot rambi with emmc in ACPI mode
    
    Change-Id: Ia67b66ee8bd45ab8270444bbb2802080d31d14eb
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/179849
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5015
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit d37705c3b0ead5f0ff715bd27959114cd273fb6c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 10 20:58:57 2013 -0500

    vboot: provide empty vboot_verify_firmware()
    
    In the case of CONFIG_VBOOT_VERIFY_FIRMWARE not being
    selected allow for calling vboot_verify_firmware()
    with an empty implementation. This allows for one not to
    clutter the source with ifdefs.
    
    BUG=chrome-os-partner:23249
    BRANCH=None
    TEST=Built with a !CONFIG_VBOOT_VERIFY_FIRMWARE and non-guarded
         call to vboot_verify_firmware().
    
    Change-Id: I72af717ede3c5d1db2a1f8e586fefcca82b191d5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172711
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4879
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit d4322565ed95266f12b3444772d81f406c53d0bb
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jan 23 08:34:54 2014 -0800

    VBOOT: Set virtual recovery switch based on EC Software Sync
    
    The Virtual Recovery switch flag needs to be set in coreboot since
    it is passed through directly to VBOOT layer by depthcharge.
    
    Rather than add a new config option we can assume that devices with
    EC Software Sync also have a virtual recovery switch and set the
    flag appropriately.
    
    BUG=chrome-os-partner:25250
    BRANCH=all
    TEST=build and boot on rambi, successfully enter developer mode
    
    Change-Id: Id067eacbc48bc25a86887bce8395fa3a9b85e9f2
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/183672
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/5061
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 5760e197b3cfc5718740bc5aea4861ea521b9e01
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jan 26 11:45:30 2014 +1100

    AGESA boards: Clean up definition of BIOS_SIZE in platform_cfg
    
    Clean up vendor code from hard coded #define if-def chain with a
    pre-processor shift and subtract.
    
    Change-Id: Ibce34ab576d7db8586a6ec8f9b2460268e0e1878
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/4811
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 9ad52fe56e8fbb1cd2e37795741773708b72eef3
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Jan 27 20:57:54 2014 -0600

    cbfstool/lzma: Avoid use of typedef with structs and enums
    
    When typedef is used with structs, enums, and to create new typenames,
    readability suffers. As such, restrict use of typedefs only to
    creating new data types.
    
    The 80 character limit is intentionally ignored in this patch in order
    to make reviewing easier.
    
    Change-Id: I62660b19bccf234128930a047c754bce3ebb6cf8
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/5070
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4a7b1152115e866cd3164bdd90d8b0ffa26a863b
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Jan 27 17:17:29 2014 -0600

    cbfstool: Don't assume compiler is gcc, and use $(CC)
    
    Change-Id: I49feb5be885369fca10c8db31329e51d87031641
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4841
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e20f27a0982d1955568d4596543890bc51e1932b
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Jan 27 16:16:47 2014 -0600

    cbfstool/lzma: Remove windows-specific remnants
    
    Remove checks for MSVC version and references to windows types and
    calling conventions. Calling conventions are not needed as functions
    are not exported, like in a library.
    
    Change-Id: I884a1502cf56b193de254f017a97275c8612c670
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4836
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5719bdc81ce87a0a511561ee2d98eb6ef8dbf6f8
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Jan 27 14:25:19 2014 -0600

    cbfstool/lzma: Remove C++ remnants
    
    The original lzma code was probably designed as a library, and had
    tons of checks for __cplusplus and extern "C". They were not removed
    when imported, but remove them now.
    
    Change-Id: I4ae6e7739d191093c57130de8ae40da835e81bd1
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4835
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 91e9f27973aba1988b32e694add144ab852dfece
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Jan 26 22:55:01 2014 -0600

    cbfstool/lzma: Use stdint and stdbool types
    
    This is the first patch on a long road to refactor and fix the lzma
    code in cbfstool. I want to submit it in small atomic patches, so that
    any potential errors are easy to spot before it's too late.
    
    Change-Id: Ib557f8c83f49f18488639f38bf98d3ce849e61af
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4834
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit aa2f739ae87386b8a29068ecfdc2b25bcf4a19ca
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Dec 3 11:13:35 2013 -0800

    cbfs: fix issues with word size and endianness.
    
    Add XDR functions and use them to convert the ELF headers
    to native headers, using the Elf64 structs to ensure we accomodate
    all word sizes. Also, use these XDR functions for output.
    
    This may seem overly complex but it turned out to be much the easiest
    way to do this. Note that the basic elf parsing function
    in cbfs-mkstage.c now works over all ELF files, for all architectures,
    endian, and word size combinations. At the same time, the basic elf
    parsing in cbfs-mkstage.c is a loop that has no architecture-specific
    conditionals.
    
    Add -g to the LDFLAGS while we're here. It's on the CFLAGS so there is
    no harm done.
    
    This code has been tested on all chromebooks that use coreboot to date.
    
    I added most of the extra checks from ChromeOS and they triggered a
    lot of warnings, hence the other changes. I had to take -Wshadow back
    out due to the many errors it triggers in LZMA.
    
    BUG=None
    TEST=Build and boot for Peppy; works fine. Build and boot for nyan,
         works fine. Build for qemu targets and armv8 targets.
    BRANCH=None
    
    Change-Id: I5a4cee9854799189115ac701e22efc406a8d902f
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/178606
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Ronald Minnich <rminnich@chromium.org>
    Tested-by: Ronald Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4817
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8449b5e0a9e5eca3c91c1d9351d5f21eaa0ba582
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Nov 5 17:07:44 2013 -0600

    libpayload: adjust max number of memranges
    
    Rambi currently has more than 16 memory ranges. Because of
    this libpayload is silently dropping them and the full amount
    of memory is not being properly wiped. Correct this by bumping
    the number of ranges to 32.
    
    BUG=None
    BRANCH=None
    TEST=Built and booted rambi. Noted that the full amount of memory
         was being properly wiped.
    
    Change-Id: Ida456decf2498cb1547c0ceef23df446a975606b
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/175792
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4942
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 029aaf627c381a70b365e8b29797425785eb6788
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 10 12:41:49 2013 -0500

    x86: add common definitions for control registers
    
    The access to control registers were scattered about.
    Provide a single header file to provide the correct
    access function and definitions.
    
    BUG=chrome-os-partner:22991
    BRANCH=None
    TEST=Built and booted using this infrastructure. Also objdump'd the
         assembly to ensure consistency (objdump -d -r -S | grep xmm).
    
    Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/172641
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4873
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit f545abfd22a594ecb9c0678efa5278bb38a37a70
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 24 10:14:06 2013 -0500

    rmodule: consolidate rmodule stage loading
    
    There are 3 places rmodule stages are loaded in the
    existing code: cbfs and 2 in vboot_wrapper. Much of the
    code is the same except for a few different cbmem entry
    ids. Instead provide a common implementation in the
    rmodule library itself.
    
    A structure named rmod_stage_load is introduced to manage
    the inputs and outputs from the new API.
    
    BUG=chrome-os-partner:22866
    BRANCH=None
    TEST=Built and booted successfully.
    
    Change-Id: I146055005557e04164e95de4aae8a2bde8713131
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174425
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4897
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 16000c883ee121b82b943c613ab1ae6a5ed7e01c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Sep 19 12:19:51 2013 -0500

    spi: Add support for Winbod W25Q64DW
    
    The W25Q64DW spi part is programatically equivalent
    to the other W25Q64 parts except it operates at 1.8V.
    Just add a new entry with the appropriate ID.
    
    BUG=chrome-os-partner:22292
    BRANCH=None
    TEST=SPI controller can program the part.
    
    Change-Id: I65b0261223a9fefcb07477a43b6a3edb8228dd03
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/170011
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/5077
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit bf18b17cf3dc5957de0356a82bffd395504447fc
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Oct 24 10:11:08 2013 -0500

    cbmem: add reference code ids
    
    In order to identify the ram used in cbmem for
    reference code blobs add common ids to be consumed
    by downstream users.
    
    BUG=chrome-os-partner:22866
    BRANCH=None
    TEST=Built and booted with ref code support. Noted reference
         code entries in cbmem.
    
    Change-Id: Iae3f0c2c1ffdb2eb0e82a52ee459d25db44c1904
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174424
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4896
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 3674ccfa3ef9fe9317bc9f9b7231e3b55452f1c4
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Jan 27 16:39:17 2014 -0600

    x86/mtrr: don't assume size of ROM cached during CAR mode
    
    Romstage and ramstage can use 2 different values for the
    amount of ROM to cache just under 4GiB in the address
    space. Don't assume a cpu's romstage caching policy
    for the ROM.
    
    Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4846
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit e6767674af95c7b5e9b508839b3aaf8b477921c4
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Jan 27 15:52:47 2014 -0600

    intel: fix microcode compilation failure in bootblock
    
    When not building with CONFIG_SSE there are not enough
    registers for ROMCC to use for spilling. The previous
    changes to this file had too many local variables that
    needed to be tracked -- thus causing romcc compilation
    issues.
    
    Change-Id: I3dd4b48be707f41ce273285e98ebd397c32a6a25
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4845
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit ffa81bf29d0e1e98207aa7bb763f78a1e61e91bd
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 25 14:38:51 2014 +0100

    bachmann/ot200: Fix cmos.layout.
    
    In current cmos.layout baud_rate overlaps with hardcoded reboot byte.
    Fix the layout and provide the default for upgrade.
    
    Change-Id: I979b8743c4aab6f17b3acf61b92a74a333203379
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4804
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

commit 790e3adc7079bfa40c4932e4633096bff2863b03
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Jan 27 15:08:27 2014 -0600

    chromeos: include stddef to fix compilation error
    
    As some of the standard definitions were shuffled around
    chromeos started failing to build. Correct this.
    
    Change-Id: I9927441ccb2d646e8b3395e6e9f8e8166de74ab0
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4844
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit a86e81d472fd80dd5f33d36a02d41c14cb7eb1bd
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Jan 27 15:07:26 2014 -0600

    x86: include header to define types in use
    
    The tsc header is using u32 w/o including the file
    with defines it.
    
    Change-Id: I9fcad882d25e93b4c0032b32abd2432b0169a068
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4843
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit e6606518243d9beda31693d40493b5f7a1a3e2e0
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 26 23:53:00 2014 +0100

    coreboot_table: don't add CMOS checksum twice.
    
    Checksum is already in cmos_layout.bin. No need to add it twice
    
    Change-Id: I6d12f35fd8ff12eee9a17365bbfab38845c09574
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4829
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit a60a3020d9611de3ac9333d0c8791c401a6a70a0
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Jan 27 04:07:32 2014 +0100

    siemens/sitemp-g1p1: Add missing boot_option option.
    
    Unlike other additions this doesn't require versionning first since
    the bootblock reads it anyway from this hardcoded offset.
    
    Change-Id: I3e3f65602bb1b92b91097692ee13e6948a748061
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4832
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 3572f5c6f0876f055bb4d4567a9ba89a0fd05976
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 26 21:57:43 2014 +0100

    sitemp-g1p1: Migrate to new cmos.default approach
    
    Current code just prints warning, defaults match the behaviour of
    current code when checksum is incorrect and look sane.
    
    Change-Id: Icda0d3cb3517fc15e6a0ee787b00276d2d435776
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4827
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 5b5f834e8475fc89af85d2d706b8c31f32e6f4f3
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Sun Jan 26 00:19:58 2014 +1100

    util/superiotool: Add initial support for Fintek F71869AD.
    
    Change-Id: Ia2ce8214d8b419d0ca0186e6f6b2241097b0847b
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/4802
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 962b6c0a5e844e919ef0c28fee102f63fa8d5de9
Author: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Date:   Thu Jan 23 22:12:25 2014 +1100

    superio/fintek: Add initial support for Fintek F71869AD.
    
    Change-Id: I41f1ee20517dd179a4dee914ab7f6332739e326e
    Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
    Reviewed-on: http://review.coreboot.org/4784
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 28684171f07b6adce0031108bb799457970f433a
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Jan 26 11:23:17 2014 -0600

    google/stout: Provide cmos.default
    
    Change-Id: Ief0d08e0cd3dc469d700acf8567435894651171e
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4822
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit ded4e1266d8bed8537039c926400bc32f9380e42
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Jan 26 11:02:40 2014 -0600

    google/butterfly: Provide cmos.default
    
    Change-Id: I0ec0d80f6c6682a0d3656a0c0743d166b1bc85c2
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4820
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 0bf998e34f0ceb30893d15154fc5324dbfab514c
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sun Jun 23 19:39:03 2013 +0200

    lenovo/t60: Add CMOS defaults.
    
    The code for handling the invalid CMOS space in mainboard.c
    is now useless and so it was removed.
    
    Change-Id: I86ec6a7f73e32948adff9087d4af5372a49a46a5
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3520
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 63e35f207c1dd80d9293b42a761e548d282a5260
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 26 03:55:01 2014 +0100

    pc80/keyboard: Ignore interface test failure.
    
    On Asus A8N-E this test fails but if failure is ignored keyboard works.
    
    Change-Id: Ifeeff2f41537b35bc90a679f956fea830b94292c
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4816
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit e0553b436bb63858556abc1e85d68f8aad059f44
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 26 14:49:26 2014 +0100

    asus/a8n-e: Implement basic ACPI.
    
    Change-Id: I3c8fa1fbec2175787666697f2239abb70020019e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4819
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 8540a8b80fae8c4faff734503d5d36cae3519506
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 26 14:11:35 2014 +0100

    asus/a8n-e: Add IRQ for onboard audio.
    
    Now onboard audio works.
    
    Change-Id: I1a598390c980287744689011b40210cec0145c6a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4818
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1bddb02f05dda2261999fab30764e47ac68b0f82
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 26 02:36:55 2014 +0100

    asus/a8n-e: Fix GPIO resources.
    
    Allocator can't currently handle both PnP and PCI resources together.
    Only 2 resources in PnP are not fixed. So fix them.
    
    Change-Id: Iad695d1d991d110b726ec429fff87c616af5ac8b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4815
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit bb6956ad13d2a65aa78b1eb3baeffe4379929bcc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 25 18:14:52 2014 +0100

    asus/a8n-e: supply cmos.default
    
    Change-Id: Ib54cda60c9d8c57885c2b62f978222e01c1c3347
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4814
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 4fe9813adb44b369c84a097b4be3101eddf6b19d
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Jan 25 15:55:28 2014 +0100

    src/cpu: Fix spelling of MTTR to MTRR
    
    Change-Id: Ia4718ac31a5b2bd12f8cda5e107aa878d74d2a03
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/4805
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit f927df68e491e3bb7bad02a405aae5fd91545155
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Jan 25 23:17:32 2014 -0600

    Revert "Makefile: Check $CC variable returned from xcompile is not empty."
    
    This reverts commit 1287d1cc80c52ff2598f2bae235fc42d8456f44a.
    This commit has the side-effect of making abuild fail, and as such is
    reverted until a safe solution can be found.
    
    Change-Id: Ib8cb78468c2922322b490e0b52c0bd24f3de7ef9
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3269
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit b92f5e884d9d9d73ea4b3c5b583f6a1391f7605e
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Jan 20 18:04:14 2014 -0600

    nb/sandybridge: Move MRC cache above mrc.bin
    
    This small change greatly reduces CBFS fragmentation. There is now a
    small gap of only 728 bytes between mrc.bin and mrc.cache, with the
    64 KiB alignment maintained for mrc.cache -- assuming systemagent-r6
    is used. The gap was just under 64 KiB before.
    
    With this change, it is easier to accommodate fallback and normal
    boot stages without having to manually place the stages in the highly
    fragmented CBFS.
    
    Change-Id: Ia2340c1928ed6e232949e053d1943c2f5737f741
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4763
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit b66b0438c03407999402d927202fcb2b061a0054
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Jan 21 03:09:14 2014 +0100

    asrock/e350m1/board_info.txt: Specify ROM socket and Flashrom support.
    
    Based on info by Kevin O'Connor.
    
    Change-Id: I21d447fec976e0ee967ba64b0f506c97c22917a3
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4765
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 487984e7f3fbe20f9015c913300644fd3e8bb27e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Jan 20 20:43:25 2014 +0100

    asus/a8n-e/board_info.txt: Set ROM Protocol.
    
    Change-Id: I65f2faee672d4d7dea50b67cf6426f503034b380
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4760
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1ebc7e943b1e48ed0b2c385d64cbe1c88693ac37
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Jan 21 15:28:38 2014 -0600

    cbfstool: correct size left calculation for "empty" entries
    
    After removing a file sandwiched between two other files, that file
    could no longer be re-added at the same location. cbfstool tried to
    add the file, and a new "empty" entry, which, together, would no
    longer fit, so it continued checking for the next available space.
    
    Change the behavior to add the file if there is enough space for the
    file alone, then only add the "empty" entry if there is enough space
    for it.
    
    Change-Id: Iad3897dd28cf12f12ae877cfd83e1990fa7d2f0f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4772
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 9c70adf26d810405f22ea9f07a10d4f56fee3cb8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 23 20:37:22 2014 +0100

    intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.
    
    Not used anymore since microcode was moved.
    
    Change-Id: Id666c80cb20e90e3664c4dcfcc0c41a4aeb4864c
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4788
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1287d1cc80c52ff2598f2bae235fc42d8456f44a
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Thu Sep 5 00:21:11 2013 +0800

    Makefile: Check $CC variable returned from xcompile is not empty.
    
    If xcompile can't find out suitable GCC compiler for i386/armv7, it
    will not set $CC_i386/$CC_armv7 variable. Makefile sets $CC variable
    from xcompile, and will print strange error messages when executing
    $CC program if $CC is empty.
    
    Add checking to avoid this problem. If $CC is empty, also delete
    invalid .xcompile file, so Make can recreate this file next time.
    
    Change-Id: Ia8d481d76ca52f3351cb99f05779d06947161c5d
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3905
    Tested-by: build bot (Jenkins)
    Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f3c7a9cf9dd275fa597abf4e40552b3645e1cb23
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 4 21:00:38 2014 +0100

    sandy/ivy SPI: Support hardware sequencing and use with multiple chips
    
    When 2 chips are present to get to the second one you have to use hardware
    sequencing. Also use it as the fallback if chip is unknown.
    
    Based on code in flashrom by Stefan Tauner and Carl-Daniel Hailfinger
    distributed under compatible license.
    
    Tested on Lenovo X230 which has EN25QH64 (8M) + N25Q032..3E (4M)
    
    Change-Id: I56f3cf0406b5f09fa327ed052c8e8b1df1d8a11f
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4613
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e23bd0e3c4e4ec8fddf8b2bc6aa6fa398781fcd1
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 18 17:45:32 2014 +0100

    SPI: Add API for programmer-specific flashing.
    
    Change-Id: I7a2f5b9ae74458b5ed6271b1c27842c61546dcd2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4712
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e33d6cac96a3cc0fce313a6a19d20cb2561d057f
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Wed Oct 23 20:47:20 2013 +0800

    keyboard.c: fix coding style with indent
    
    Change-Id: Ie8efa9fb9bdc65bf8015eec197f44c432e87d907
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3986
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a4ae3107cae800c1fa13a97c78827ef2608684bd
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Mon Dec 23 19:54:26 2013 +0800

    dmp/vortex86ex: Initialize I2C controller base address/IRQ
    
    Change-Id: Iefd6852f2300f703ebed8b52aee627107a024f85
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/4570
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 77c70a06e1cdb6781857a2f488f13432bbcf18ec
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 23 16:41:35 2014 +0100

    lenovo/x230: Enable wacom USB port
    
    Based on lsusb -t info from David Schissler.
    
    Change-Id: I061881f531b11dc6f5f7719269cf9f3c9b0b99e1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4786
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2657e841097b33bc6f50470f852d2e54fb35f5f6
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Jan 6 20:40:27 2014 +0100

    Multiboot: remove multiboot tables generation.
    
    GRUB2-as-payload doesn't use them. Libpayload can live with just coreboot tables
    if loaded as payload. memtest86+ can use them but is buggy with them. Solaris
    needs a huge boot archive not supported by coreboot and too big to fit in
    flash (dozens of megabytes). All-in-all looks like no users are left for this.
    
    Change-Id: Id92f73be5a397db80f5b0132ee57c37ee6eeb563
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4628
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b2939f7486b80a3f7fc5fc7fd5723dd58984d31d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Jan 22 17:12:35 2014 +0100

    lenovo/x230: Add missing copyright line.
    
    Change-Id: I5ecd25e23cebf83d4ae9300307aaac527e05c377
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4778
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4c8b1ee14a0a293289fe90e4c25032979b35adbb
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Jan 10 19:30:54 2014 +0100

    X201: Enable expresscard hotplug.
    
    Change-Id: Ieefc2ad775c16de9aa974b2602d55ee047c9f568
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4643
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 786c0f5fca4735f4d4b8d680749f6ef8b6198a3f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 2 10:16:46 2014 +0100

    nehalem: Fix SMRAM register address
    
    Change-Id: If6646853039d15d6ba0fcf2b9b9b0658004be6e6
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4787
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 969f8617e9ff4e71a11a8fc4567e8c8de33585a0
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Jan 22 21:41:34 2014 +0100

    lenovo/x201: Reinit CBMEM only on S3 resume.
    
    Change-Id: I0643cdab10cda3f19ab56223f5fa77376a8046ac
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4782
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bca985557e3a7dc94c954d7295a963f654886a08
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 9 11:13:18 2014 +0100

    X201: Move early nehalem S3 magic to right place.
    
    This MCH magic needs to be done before GPIO.
    
    Now S3 (Suspend-to-RAM) works on X201.
    
    Change-Id: I319e57af52ff01083bfbffbcd883ac5f453320a1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4632
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f7a42de725b2e5a2a7e3af7cee61291c56cd6518
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 9 11:10:04 2014 +0100

    nehalem: Restore frequency ratio registers on S3 resume
    
    Previously registers 274/265 and 6dc/6e8 were recomputed
    which lead to a slightly different values. On
    S3 resume it needs to be a perfect match.
    
    Change-Id: I14f42c7659dde5f327979831fcb1f84ea0c78dee
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4634
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f62669c966bb52701005477198e35302e611b3d8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 9 10:59:38 2014 +0100

    nehalem: Small cleanup to raminit RE bindings
    
    Change-Id: Ifd3f172a1c8a108909d1a7dae94f926b2778c2b1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4633
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1cd937b48c652206e0c62bba81afe5a2a829742a
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 9 23:41:48 2014 +0100

    Ibexpeak: add missing thermal init.
    
    Without it ME doesn't always start correctly and no temperature is reported,
    no fan management and so on.
    
    Change-Id: Iff71f3afbc35a1453a20d182890ae2d196c556bd
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4636
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 82926e1d16ff2fd78d6dd3d2d65f35ed45145774
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 18 02:05:17 2014 +0100

    nehalem: Move mrc.cache to 0xfffe0000.
    
    On nehalem there is no MRC.bin. To avoid excessively fragment the CBFS,
    put MRC.bin as high as possible.
    
    Change-Id: Ia3f7aef5a1e62a42c9fa9ea0f6eec2b29eb6722d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4708
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cc16ffc7cb96a3d36813bc83f5e343003ea30fc5
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 05:48:17 2014 +0100

    X201: Add missing LPC registers
    
    Without them PMH7 is inaccessible from running system.
    
    Change-Id: Ib5a524325040e253a9d914906f90263fc208c313
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4655
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 24356dd5c1edc64eeea4f1f15806ffb53a86911f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 2 11:08:29 2014 +0100

    X201: Add missing CPU counter.
    
    Change-Id: If9f10ef40193fc84ab1849429b5af678ffe831b2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4624
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bd89699516a26f698b967167f72d6bf2d84280be
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 2 10:10:14 2014 +0100

    nehalem: Simplify acpi.c by using __SIMPLE_DEVICE__
    
    Change-Id: I93351a2716cd58c2006400cecca1390b1704e94b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4603
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 517406aac7d9c7efb12f5e419213cd1b2d8f01a5
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Jan 10 01:01:42 2014 +0100

    X201: Add azalia verb.
    
    Adds missing sound codec configuration.
    
    Change-Id: I3a7097ab0a7c85524f2400471323f5d2d15569ed
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4641
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0dbea2322a6cd02568d3fbe296183c4a6032a8f2
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Jan 20 20:22:19 2014 -0600

    board_info.txt: Add ROM information for google butterfly
    
    Change-Id: I7d973ef41c4f2973e71015ec292ae88faaeb5840
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4766
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 4737b0c2ccc481af04406507d6ad738a3b8c5e7f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Jan 22 17:12:56 2014 +0100

    lenovo/x230/dsdt.asl: Change space to tab.
    
    Change-Id: I9e6d39a5a08fe9fd27daeca0e8393ff019b722d4
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4779
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 52884ad1615965dcf4bd1835805b41922720d2af
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Jan 20 04:26:38 2014 +0100

    board_info.txt: Classify almost all remaining boards.
    
    Based on info from commit messages (most devel/eval boards are mentioned
    as such in commit message) and information from vendor sites (mostly based
    on form factor).
    
    Classification for siemens/sitemp_g1p1 is based on info by Nico Huber.
    
    For Google boards based on info from ML posted by Aaron Durbin.
    
    Remaining unclassified board is:
    google/pit
    
    For which very little info is available publically.
    
    Change-Id: I12dfff4c629811a48cfc77be27bdc5081530b8f6
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4759
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit d1443aa60bfab1e00523731f20608f4cae04193b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jan 4 08:46:32 2014 +0200

    CBMEM: Rename cbmem_reinit()
    
    This function does not really initialize anything, but only
    checks for the TOC.
    
    Change-Id: I9d100d1823a0b630f5d1175e42a6a15f45266de4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4669
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 6f1d26e25839ffddd89843ac631b1e2a892bc72f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jan 22 22:03:31 2014 +0200

    lenovo/x230: Fix CBMEM
    
    Fix build. Changes to static CBMEM functions were written before
    this board was in tree.
    
    Change-Id: I6b20d0c2815337edc330d384a409f1f939727c2b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4781
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit fa8cedae2ac12917d38ad07430de0ce60dcb8604
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jan 12 14:38:33 2014 +0200

    AMD K8/fam10: Fix CBMEM on S3 resume
    
    Change to use cbmem_recovery() to wipe CBMEM region and reset
    ACPI wakeup if CBMEM TOC was not found.
    
    Change-Id: Ic362253eaa00bd442d4cc0514632f9096e20bfa6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4673
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 47770c07692e28cd66d74da9d94c6c1ca3e76056
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jan 12 14:38:24 2014 +0200

    AMD AGESA: Fix CBMEM on S3 resume
    
    Change to use cbmem_recovery() to wipe CBMEM region and reset
    ACPI wakeup if CBMEM TOC was not found.
    
    Change-Id: I6648570d76b5c137f50addcc5bce9c126d179c65
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4672
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 2d8520b275d47e0670e7f9e166e0f63c32855548
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jan 6 17:20:31 2014 +0200

    CBMEM: Replace cbmem_initialize() with cbmem_recovery()
    
    The replacement function confirms CBMEM TOC is wiped clean on power
    cycles and resets. It also introduces compatibility interface to ease
    up transition to DYNAMIC_CBMEM.
    
    Change-Id: Ic5445c5bff4aff22a43821f3064f2df458b9f250
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4668
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 97e1b11f416aa23787e71b6133702b82daf1552e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jan 6 17:18:58 2014 +0200

    lenovo/x201: Really do EARLY_CBMEM_INIT
    
    The board was missing cbmem_initialize() call in romstage. Selecting
    EARLY_CBMEM_INIT implies this is done in romstage.
    
    Change-Id: I9ec93f89fe4cbb9e729532be36db601b6e62bca6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4667
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 886a543d60c528fd349b0b0aebf7338ec8350a88
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Oct 13 20:41:57 2013 +0300

    roda/rk9: Add EARLY_CBMEM_INIT
    
    Change-Id: I450f78cce7172fd2dee66dc81b4f33e07c1aff09
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4664
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit a7c9611712efc04c0c73a8a8621eabd5c869af89
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Oct 13 20:41:57 2013 +0300

    intel/i945 boards: Add EARLY_CBMEM_INIT
    
    Inspired by commits ac6ea04b and 4560ca50 that enabled this feature
    for lenovo/x60 and lenovo/t60 with i945 chipset.
    
    Change-Id: Ia04f58b8c3769b5734708c6a338bb80c13c5aeba
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3994
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit 66fd775168a46e5f7ee0c121735d3be98bbcab1c
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 17:02:11 2014 +0100

    emulation/qemu-armv7: Fix wrong stack parameters.
    
    Now it boots up to message "Could not find payload".
    
    Change-Id: I07ddca7046492f7e0dec15a8ea00c2870b09ee67
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4754
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit e7e9502d46735e4f1aafd9b362d912070b9bb29d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 12 15:26:15 2014 +0100

    Lenovo X230: new port
    
    probably a problem in MRC:
    - EHCI output failure after sysagent
    - no S3
    - no MRC cache
    - MRC needs watchdog
    - less MTRR could be used by some memory map optimisations
    
    Not tested:
    - dock (probably doesn't work)
    - msata (probably works)
    - wwan (probably works)
    - mini displayport (probably works)
    
    Blobs:
    MRC
    VGA Oprom
    
    Change-Id: I5bdb9372971f48e048848d57b6c924b79782dbde
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4679
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 2a1d5b061db4e0019fa4a7f0a8c0fdca2c5c2242
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Nov 11 15:20:56 2013 +0100

    cbfstool: cleaner filling fields
    
    The LARCHIVE header isn't a string (not null terminated).
    It confused coverity, and while it should be obvious that
    we're not aiming for any null bytes after the header, we
    can also just not pretend it's a string.
    
    Change-Id: Ibd5333a27d8920b8a97de554f1cd27e28f4f7d0a
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4088
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit df29f1ba6f4f81dbae704f1ab97c9f3044d3b930
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jan 18 16:38:12 2014 +0100

    CAR_GLOBAL: Define section details once
    
    Improve clang compatibility by dropping an opaque hack
    
    The section attribute was only ever meant for specifying
    section names, not their properties - otherwise they would
    have provided section(name,attribute,class) instead of only
    section(name).
    
    The hack to add attribute and class to the name, and commenting
    out the "real" definitions inserted by the compiler (see the
    terminating "#"), is refused by clang developers.
    
    This is a cleaner implementation in that the section is first
    declared with its properties, then used later-on, expecting that
    later conflicting declarations are ignored.
    
    It can still break in two ways:
    1. The assembler or linker could complain about a section declared
    in two different ways.
    2. The assembler could just use the latest declaration, not the first,
    to determine the section's properties.
    
    I won't sort these out unless they actually happen.
    
    
    Change-Id: I4640b0fc397b301102dde6dc3ea1a078ce9edf1c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4716
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 9609823ed8776f63594c7ff700c13779712b80e9
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 5 06:52:11 2014 +0100

    sandybridge/igd: Add brightness register descriptions
    
    Needed for brightness control for Lenovo X230
    
    Change-Id: Ib6d127d2e050671dd402c31af06ff4726f65156c
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4618
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

commit 77005b47688b6b18bca27350a0b1f399b31f71f6
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Jan 21 02:39:46 2014 +0100

    board_status.sh: Replace [[ with [.
    
    [[ is a bashism.
    
    Change-Id: Ief7c43fc1740db32ed97850a415b0c256b5bb35a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4764
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 74230c32ced71c1c56691f95c82860096b63366d
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Jan 15 23:28:02 2014 -0600

    google/butterfly: Remove unused cmos.layout options
    
    Do not expose options that are unsupported by the board. I tried for
    a couple of days to see why hyperthreading wasn't working. It's not
    supported by the CPU. The same applies to the baud_rate option. It
    makes no sense to expose it to userspace via nvramtool.
    
    Change-Id: I89b91820616d92fb4db20bf77f4b7f48a70353d5
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4697
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7358643e0af6c436906972c0b6a193effafc4f8c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jan 18 16:23:32 2014 +0100

    sconfig: don't "const" structs twice
    
    It's useless and makes clang unhappy.
    
    Change-Id: If256b99aebabd87df30a3a078c5804330b82989b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4713
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 484a5bfffeed234f998ededbc3a7ec927bc2569b
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Jan 10 19:43:33 2014 +0100

    X201: Fix SMI bindings.
    
    Doesn't have a visible effect currently but it's better if those
    bindings are correct.
    
    Change-Id: I0f1a468e59429b14db139cc48e1e68c0e1841300
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4645
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit df7d5c9e0671486004c42f4f57b79bf9beafba51
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Jan 20 03:18:20 2014 +0100

    boardstatus: Fix creation of links to configs.
    
    The unusual construction ls + grep + while read fails
    for unknown reason. Use standard for x in * consruction
    instead.
    
    Change-Id: Ibcdf5e18543587f71a605bae2d0df72b6a286a5b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4757
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 51634d25bcbc969a546819341fd901d4359ec7bd
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 23:24:02 2014 +0100

    google/falco/board_info.txt: Declare as a laptop.
    
    Change-Id: I42c77d03b6a5f8ef88f1276de543bb3fc55467af
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4755
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 14813b3241af145590c005799c542bfd6ad0a8c1
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 12:47:20 2014 +0100

    board_info.txt: Add mentions of thin client names.
    
    Based on info from old page
    
    Change-Id: Ibd07b5904569e510de249e4216875438a855ff57
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4746
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 3e51837f9a85a5bc1ce08322756fb0631a18dd36
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 03:50:06 2014 +0100

    boardstatus: Add useful info from old page header to foreword.
    
    Change-Id: Ie3d1be1e51df458cd8b55230c888f032ab705ef8
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4743
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 39268299c00efbc63b684d0da8ed86eb77b78111
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 13:37:16 2014 +0100

    linutop: Add Linutop-1 as a clone of artecgroup/dbe61
    
    Change-Id: I69e99e2a1bf9b890281caaf0633f91850d923241
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4747
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 08c372f460292434926af7651c91759af9df428a
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 14:44:04 2014 +0100

    boardstatus: Do not error out on unknown CPU/northbridge
    
    On bot, stderr is unmonitored, so it make no sense to stop with an error.
    Instead use some sensible guesses.
    
    Change-Id: I6292e9fbf446b751471b95f86e7515c6680bddf3
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4748
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit c9babb278f2de86022979db04628e99f333b73c8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Jan 15 22:07:52 2014 +0100

    nvramcui: Trim values when setting.
    
    Values get space-padded by curses and then enum search fails to match them.
    Rtrim to compensate for curses.
    
    Change-Id: Iecf095f21cfade9425eaa039b67625615eb80481
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4692
    Reviewed-by: Nico Huber <nico.h@gmx.de>
    Tested-by: build bot (Jenkins)

commit 571bec726c4c5fe0d95ae4ad3604e49e859f8861
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Jan 15 22:04:12 2014 +0100

    libpayload/lpgcc: Add curses include path.
    
    Without it payloads that need curses fail to build.
    
    Change-Id: I4533238b547e4c2d9e0778fb7d314db35a9559df
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4689
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.h@gmx.de>

commit 2a0fc9fbb40a4db06910c31c39cbfd36e3bb58ad
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 03:49:30 2014 +0100

    boardstatus: Drop v4 mention of coreboot version.
    
    Change-Id: I5cf34e14f6e11c03822a6ce6226365c76e0f6875
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4742
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 7ea00155b20db923833b8d3564c897b8ecf3fcc1
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Jan 15 22:06:56 2014 +0100

    libpayload/options: Fix out of array read.
    
    It resulted in garbage in upper bytes of numeric options.
    
    Change-Id: I5e5d8b770ed93c7e8a1756a5ce32444b6a045bac
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4691
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Nico Huber <nico.h@gmx.de>

commit fd5b3704374c9ca7d57627f9d449536d02b9baf0
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Jan 10 20:40:59 2014 +0100

    libpayload: Bring keyboard_wait_write() back
    
    Code is using it...
    
    Change-Id: I6894b45cbbf70c8e7ce37ce18d93cadf0ea9fbfc
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4649
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Nico Huber <nico.h@gmx.de>

commit 5fb48a85dc9f3fdb28779b92eb19870615d32322
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 03:19:16 2014 +0100

    boardstatus: Accept only hex digits for AMD family number.
    
    Change-Id: Ia13e54f35215d07d93f93887eef5aeb91ffb874d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4741
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit aa998bb4806358d32dcec09c1866cd0d620b6826
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 03:18:25 2014 +0100

    boardstatus: Skip SKI_ISA_DMA_INIT configs.
    
    Change-Id: I10872c31baa0d73ce55d1738a0643fda2555c62e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4740
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 047c10c0f8537bbae5749292a5036ac71314a312
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 02:56:48 2014 +0100

    boardstatus: Add new category "sbc".
    
    Change-Id: I8a7bf265ebb30dd5997f93729a0329e74f463a23
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4739
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 14a703045dc4930158e9b0535c30424c51491825
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 02:54:25 2014 +0100

    boardstatus: Add category "emulation".
    
    Change-Id: If9d26b9e4cb1895452316c9cf2e8c75a01cfd7c2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4738
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 13cd4907f29e9f3221ed80a20543c735dc76d74d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 01:36:02 2014 +0100

    board_info.txt: Remove some needless name overrides.
    
    Overrides were to have names in line with wiki but names derived from the
    tree are better in some cases.
    
    Change-Id: Ic805ba9a3b9c7f926dc9ef27f8673f2c18e9af34
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4737
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 2e71e55d338f8b9cc629c3c5e2e35fda73e7f56d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 01:37:01 2014 +0100

    board_info.txt: Change iei/kino's link to web.archive.org.
    
    Original link is dead.
    
    Change-Id: I56e975ee411f7290c12aad501f490ccc5dedaf05
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4736
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1af25246a971da02bc50000e19c1b07a39145e21
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 01:18:04 2014 +0100

    board_info.txt: declare chromebooks as laptops.
    
    Change-Id: I4a3ed7e9b6aaec8aba8ffc47eafdbcca31e4c700
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4734
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 9514f5a90165c6fac44f5e54e2bf53d7dbb64f83
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 01:00:03 2014 +0100

    board_info.txt: Categorize various boards
    
    Info supplied by: idwer
    
    Change-Id: I3086e8118a721ded33c578c6c82e20642ef9d776
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4733
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 0fc8ed6318e15699bd7f1b8464fe0882b3a4cdc1
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 01:36:02 2014 +0100

    boardstatus: Remove some needless name overrides.
    
    Overrides were to have names in line with wiki but names derived from the
    tree are better in some cases.
    
    Change-Id: Iff3c27db1a4936b03f976c82d872589e41df0c90
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4735
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 2eaf3b4e3adbf95d358c83eb41378aabff193de5
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 00:37:23 2014 +0100

    boardstatus: Handle clones.
    
    Change-Id: I7bfe19eb800729713a549dc0396765a9785e11b1
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4732
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 03cd8e5fa4a6667352e293b2673551e62a09ed11
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 00:21:19 2014 +0100

    boardstatus: Use Board:$vendor/$board for board pages.
    
    Change-Id: I5249d86188845e1104d25163faa5010b943e707a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4731
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit acca285973cdabca3c64c9c85d090202bfee4afc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 19 00:26:05 2014 +0100

    board-status: Add board_info.txt manually for irregular wiki entries
    
    Based on info from wiki.
    
    Change-Id: Iebd799abe48550c4df55632b8177d845df7d9a7d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4706
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 4333071e2359add4edbae3a8c1063f1bfbb031bb
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Jan 17 21:22:32 2014 +0100

    board-status: Add board_info.txt extracted from wiki.
    
    board_info.txt is a file to be used by board-status to add
    some useful info to the generated table like flash chip type.
    This series is autogenerated from wiki page Supported_Motherboards.
    
    Change-Id: Ie2bda900713ef4883134477163320936c84c34f5
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4701
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit af771885a5a02f365a1408a06fc38519c31c621d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 18 23:33:50 2014 +0100

    jetway/j7f4k1g2e and jetway/j7f4k1g5d: Add as clones of jetway/j7f2.
    
    Change-Id: I16e027b78dc65538d8f0cd6f5e57bbdfc10b7169
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4729
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 21a2707ea92521bee3d6d213793b47645c313dfd
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 18 23:37:13 2014 +0100

    boardstatus: Remove support for multiname mobos.
    
    It's ugly and not needed anymore.
    
    Change-Id: I98301c75684813a217c3ca0435a15b6e4ffef558
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4730
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 2cb9685860d634c66988c4d45b7a696e6e2b42a8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 18 23:29:55 2014 +0100

    jetway/j7f24: Rename to jetway/j7f2.
    
    Original actually meant j7f[24] which without square brackets
    became confusing.  There is no such board as j7f24.
    
    This is a prerequisite to adding j7f4* as cloned boards
    
    Change-Id: Ia7708b13ac4141ef788183c7817fce1366919936
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4728
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit fb0710889491fc814d4d2b3a5ef0413fbc5f960d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 18 23:24:36 2014 +0100

    via/epia-mii and via/epia-ml: Add as clones of epia-m.
    
    Change-Id: I4f297e7a7332acc6ceda6a99981599e3a372b696
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4727
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit f16d9c6bcc6341829b47ad138249e916ccdc8549
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 18 22:59:15 2014 +0100

    iei/rocky-512: Add it as an explicit clone of juki-511p.
    
    Change-Id: I87e2768de6728658a87729998648514824d79fd6
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4726
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit e66548d010d70c70d9894a24d4fb14f29c781f14
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 18 22:56:08 2014 +0100

    A8N-SLI: Add it explicitly as a clone of A8N-E
    
    Change-Id: Ieab7d46177eb92393914f8cb055675df00a9a375
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4723
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 49fef4b6cbed18d2514b681ed46d3c57559f0f99
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 18 22:18:01 2014 +0100

    boardstatus: Take default board name from MAINBOARD_PART_NUMBER.
    
    Change-Id: I2f775e8919cfd35bbcf5910a8b25776e833ee100
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4722
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 22210dd95ba6a31c169e1fc94f52b04fa5ee773f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Jan 17 16:04:25 2014 +0100

    boardstatus: generate table of all boards with links to latest run
    
    Change-Id: I78f94238d7931c8b41e63174220ec4392108f4ce
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4699
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 07d881a02dce014a3218fa3824390f7683c3031f
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Dec 8 16:41:18 2013 -0600

    cpu/intel: Remove dummy terminators from microcode blobs
    
    Now that CBFS microcode no longer requires a NULL termination, remove the
    dummy terminators from all microcode blobs. This also enables microcode
    blobs from different CPU models to be linked in the same
    cpu_microcode_blob.bin without the terminators getting in the way.
    
    Change-Id: I25a6454780fd5d56ae7660b0733ac4f8c4d90096
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4506
    Tested-by: build bot (Jenkins)

commit 2c38f50b4ad8850676a70427bf1e2e9e9aab82a4
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Dec 6 23:14:54 2013 -0600

    cpu/intel: Make all Intel CPUs load microcode from CBFS
    
    The sequence to inject microcode updates is virtually the same for all
    Intel CPUs. The same function is used to inject the update in both CBFS
    and hardcoded cases, and in both of these cases, the microcode resides in
    the ROM. This should be a safe change across the board.
    
    The function which loaded compiled-in microcode is also removed here in
    order to prevent it from being used in the future.
    
    The dummy terminators from microcode need to be removed if this change is
    to work when generating microcode from several microcode_blob.c files, as
    is the case for older socketed CPUs. Removal of dummy terminators is done
    in a subsequent patch.
    
    Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4495
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@gmail.com>

commit b4c39902edbba61827c60a75fe84e748e217b8be
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 16 02:14:39 2014 +0100

    butterfly: fix compilation with !CHROMEOS
    
    One of arguments to cbfs_get_file_content was missing.
    
    Change-Id: Icb4ef26f18d63c133bc32f1c62a524edee0621ea
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4696
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit c18e52122d6080ea8378c54b759089286736c478
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Mon Jan 6 21:57:56 2014 +0000

    AMD Hudson: show POST codes on a PCI device
    
    Show POST codes on a PCI device: implement hudson_pci_port80().
    Remove the comments that use pci_locate_device():
    using the code found in the comment seems to break booting.
    
    This shares much code with sb600/sb700/sb800,
    however the deduplication work needs to be discusses somewhere else
    than in this review board.
    
    Tested on an Asus F2A85-M.
    The contribution is (C) by Rudolf Marek.
    
    Change-Id: I54fb1dcb0614452c775ed70d867ab44ff263a61a
    Author: Rudolf Marek <r.marek@assembler.cz>
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/4559
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit be8d23a3b5f07886edd0d263b75628b75533e6d5
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Oct 29 20:41:50 2013 +0100

    cpu/amd/model_fxx/powernow_acpi.c: Comment out set but unused variable `Start_vid`
    
    When adding support for PSS object generation for AMD pre Family Fh CPUs
    (199c694f) the function `pstates_algorithm` was copied and adapted, but
    `Start_vid` is not needed anymore as a static table is used. I’d remove
    the variable, but Ron Minnich requested to leave it there for
    documentation purposes. So just comment it out.
    
    Change-Id: I3002951d168cade6461941c16d78373c47792e13
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/4036
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 01d06dc67b3d4fdce450bb738eef6c17450c5fb8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Jan 15 15:52:31 2014 +0100

    ROMSIZE: Add option for 12M chips.
    
    On X230 2 real chips (8 + 4) are merged into one virtual 12M chip.
    
    Change-Id: I49c251b1777fc9edccebc4a204b9c4a087bf2a8e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4688
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 78938481eb3b4a11950d7c37627bf4704eb6e7da
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jan 4 11:02:45 2014 +0200

    Intel (sandy/ivy): Avoid calling cbmem_initialize() twice
    
    Delay the copying of MRC cache data from CAR to CBMEM until after
    sdram_initialize() returns and cbmem_initialize() completes.
    Calling cbmem_initialize() twice would complicate the decision logic
    of when CBMEM area needs to be wiped clean.
    
    Change-Id: Ic59e94cb2436293efc47b52f7418f5dbf76c714a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4666
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 1e5cacc8f81666818450ec2ca783367af2fdf56c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Oct 15 20:16:26 2013 +0300

    google/stout: Add EARLY_CBMEM_INIT
    
    Required for MRC cache and for HAVE_ACPI_RESUME to work.
    
    Change-Id: I7d48b167bd581d7c14ca50bd46e74be0133cecfb
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4665
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit cb08e169cf959333206ef69d8aa82808ef797eb7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Oct 15 17:19:41 2013 +0300

    CBMEM intel: Define get_top_of_ram() once per chipset
    
    Only have one definition of get_top_of_ram() function and compile
    it using __SIMPLE_DEVICE__ for both romstage and ramstage.
    
    Implemented like this on intel/northbridge/gm45 already.
    This also adds get_top_of_ram() to i945 ramstage.
    
    Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3993
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit bbf013c38fe76cf9cc107c41c17e4ac432847d28
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jan 6 11:08:01 2014 +0200

    nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash
    
    CBFS could start from below 4MB, and should be cacheable for the
    purpose of early microcode update and CBFS search for romstage file.
    
    Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4626
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 107f72e674a3fbe2cadb24d98bba53f432bc2e0c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jan 6 11:06:26 2014 +0200

    Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR
    
    This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
    set with values that are not power of 2. The region programmed
    as WB cacheable will include all of ROM_SIZE.
    
    Side-effects to consider:
    
    Memory region below flash may be tagged WRPROT cacheable. As an
    example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
    Since this can overlap CAR, we add an explicit test and fail
    on compile should this happen. To work around this problem, one
    needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
    define a smaller region for WB cache.
    
    With this change flash regions outside CBFS are also tagged WRPROT
    cacheable. This covers IFD and ME and sections ChromeOS may use.
    
    Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4625
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

commit 5e73be2a7a6d69cf860afba82b38803c2a792006
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 12 19:25:00 2014 +0100

    sandybridge: Allow skipping mrc.cache
    
    On X230 MRC fails if cache is passed to it. Until better solution is found
    do not create mrc.cache
    
    Change-Id: I7e70ebe3c4879e7ab33a9c95a0c9e40408ff5ca4
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4680
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1b4cbafe1d88a2ae4a4e8a3cfe71adca563f755d
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Dec 28 15:42:31 2013 -0500

    cpu/allwinner/a10: Clarify positioning of boot stages
    
    This fixes a number of potential issues, such as generating a build
    failure if the bootblock is too large, and making sure romstage and
    ramstage cannot overlap in memory.
    
    Change-Id: I4ca9ad097b145445316bcd962e007731b08a7fda
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4687
    Tested-by: build bot (Jenkins)

commit 93b600ded7aa847649a175b2a56f154e434fb10c
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Jan 3 01:27:23 2014 -0500

    cubieboard: Setup CPU clock in romstage and load ramstage
    
    This completes the romstage for the cubieboard.
    
    Change-Id: If3272d8a9e414f782892bc41b34b5e2dece5d7e1
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4686
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 601b5b530206d7d920036a4274954cc7a8beacd7
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Dec 28 19:29:36 2013 -0500

    cpu/allwinner/a10: Add helper to configure CPU clock
    
    Change-Id: I5a3bb3220aeefdd6822a7dbecf210ff77095dad6
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4685
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 594ef813266053a7d6777b91be7724ee5b62ff7a
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Jan 13 00:49:49 2014 -0600

    lib: Add log2 ceiling function
    
    Change-Id: Ifb41050e729a0ce314e4d4918e46f82bc7e16bed
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4684
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3dd0e72d3b9ad5fb6593db6c81c9ad712711e330
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Dec 26 22:53:52 2013 -0500

    lib/hexdump: Take const void * and size_t as arguments
    
    Representing a memory location as an unsigned long is specific to
    32-bit architectures. It also doesn't make sense to represent a length
    assumed to be positive as a signed integer. With this change, it is no
    longer necessary to cast a pointer to unsigned long when passing it to
    hexdump.
    
    Change-Id: I641777d940ceac6f37c363051f1e9c1b3ec3ed95
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4575
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8e053afa860e254d099b7c2e530cfbbe185ca098
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Jan 9 20:45:21 2014 -0600

    cubieboard: Configure system voltages from devicetree
    
    Change-Id: I93bac9bf94f5bafcd3ff0c3d5763b31d3ee9959b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4640
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit abe9b81e838bcf85e60671989815dfab669002ee
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Jan 9 20:17:18 2014 -0600

    xpowers/axp209: Add helper to set voltages from devicetree config
    
    Change-Id: I3ffe225b78f88c3c2d3a15292c43009e69413afb
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4638
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit af4bd599ca84478c9109a4bdba43a790ec5bbc2f
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Jan 12 15:42:58 2014 -0600

    lib: Make log2() available in romstage on ARM, not just x86
    
    On x86, log2() is defined as an inline function in arch/io.h. This is
    a remnant of ROMCC, and forced us to not include clog2.c in romstage.
    As a result, romstage on ARM has no log2().
    Use the inline log2 only with ROMCC, but otherwise, use the one in
    clog2.c.
    
    Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4681
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 910ce017571b85f2139c9ab1fcd94a8a88dd4f48
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Jan 10 23:06:03 2014 -0600

    cpu/allwinner/a10: Provide utility to make a bootable image
    
    Up until now, we relied on mksunxiboot to prepend the header which
    makes coreboot.rom bootable on Allwinner SoCs. If that tool was not
    present, the build silently failed.
    
    Integrate this tool into our util/ package, so that we do not have to
    rely on mksunxiboot being in PATH.
    Our version of mksunxiboot also eliminates some limitations of the
    original tool, so we no longer have to use 'dd' to limit the file
    size.
    
    Change-Id: Id5a4b1e2a3cb00cd1d6c70e6cbc3cfd8587e8a24
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4656
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d7b07af621627bbc40fb8481702b1fe7ab9b9c3c
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Jan 9 20:42:13 2014 -0600

    cpu/allwinner/a10: Clean up include order in Makefile.inc
    
    Alphabetize the sources for each stage (bootblock, rom, ram), and
    include twi.c in both romstage and ramstage.
    
    Change-Id: I5526f5a66f6600560005731a3ee536eb858f4ff0
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4639
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4d3a89d72a9def26c9d44d0bbdb40165d24a9417
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Jan 9 20:07:10 2014 -0600

    xpowers/axp209: Allow voltages to be sepecified in devicetree.cb
    
    This allows system voltages to be specified uniformly, rather than
    hardcoding them for each board. This will be used by cubieboard in an
    upcoming patch.
    
    Change-Id: I9dc2d3281d076c359c3fad13688649f7d36c0001
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4637
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 428eeff923f8b4e18f4df093f8e8e389311cce3a
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Dec 30 01:21:55 2013 -0500

    drivers: Add support for X-Powers AXP209 PMU
    
    Change-Id: I1de0e656a38527b172af1d0b5bcd97acbfc03bf0
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4591
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 066dcec2fe3137bba049cbec669f57860ee21bbd
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 5 06:46:19 2014 +0100

    drivers/spi/eon: Add EN25Q64
    
    chip found in X230 if not using hardware sequencing.
    
    Change-Id: I6ded10d35bfdbbe3d54c4170dd7846c7833f5ff7
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4616
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 09b65e63916749dc4cfbcd89decf2fdb1312c683
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 21:17:37 2014 +0100

    X60: Enable WWAN by default.
    
    Change-Id: I8e51a8fc03c1d7dbbdc11b121b3ea3ec18f65a5a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4670
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ea9181c76aaf4b07cb3de304ef8d8cdf9879b33e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 5 06:50:10 2014 +0100

    acpi/ec: Add missing delays
    
    Without these delays on fast systems like X230 the port is read before it's
    updated.
    
    Change-Id: I3e01fc348cc5170cec108a05095ba301055ed6b0
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4617
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c2ee6801e89b3d4f346e075a034e04716b91d0b7
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 12 14:28:56 2014 +0100

    sandybridge: Use calls rather than asm to call to MRC.
    
    Using asm as it's done currently is unsafe because caller-saved registers
    are not declared as clobbered.
    
    Using real call is nicer.
    
    regparm((1)) ensures that argument is passed in %eax as expected.
    
    Change-Id: I7449182582eaa53d4e473bc834b472edd8ee0d30
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4675
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f3c3dae580d92feba8fe07f407c89843ea9721cc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 12 15:19:50 2014 +0100

    ec/lenovo/h8: Add backlight control.
    
    Change-Id: I773793bf53d91ae787bd0d0ae7bd882243196d56
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4678
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit eada34faaa19766ed9e1584130b1a99491f47487
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 04:22:35 2014 +0100

    ec/lenovo/h8: Make trackpoint enable a CMOS option.
    
    To be consistent with touchpad counterpart.
    
    Change-Id: I72d09b41b964f80a81fbf409ef69dd368834a3e2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4654
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1eda31c0a754aa2973104f25a7f3c2a2b897b90a
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 04:18:52 2014 +0100

    ec/lenovo/h8: Remove trackpoint_enable from device tree.
    
    Change-Id: I6652e0ad4e0179950f775bbd0200484907bfc976
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4653
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8e7e5254e4088d78f03b2a413721ba687e09b19c
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 03:45:53 2014 +0100

    ec/lenovo/h8: make wlan config a CMOS option
    
    To stay in line with wwan and bluetooth.
    
    Change-Id: Iafe2dc97fc2aec5c2ad1834659b796a6b079c1bc
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4652
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit add3f7fda27eb93636b473471d17f985f14cbb8d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 20:58:20 2014 +0100

    ec/lenovo/h8: Allow control of low-battery beep.
    
    Change-Id: I2f422e83f2afcf0cc3f3ecbace01a8f4f39e87d4
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4663
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9a3b9c42d3063b03bf0028a3cbca0f2465f8f609
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 20:56:47 2014 +0100

    ec/lenovo/h8: Allow user to disable powermanagement beeps.
    
    They're pretty annoying.
    
    Change-Id: I44d26dc168927a9cedfd6ecc4c9a51a3a7b362c7
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4662
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6d6298dddc4147e7a1df6c51cb97b3d94e9c4584
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 07:46:50 2014 +0100

    ibexpeak / bd82x6x: Make SATA mode user-visible option.
    
    Ability to choose compatibility mode is interesting for testing payloads and
    OS for compatibility with older systems.
    
    As per comments
    "ide_legacy_combined # TODO: Does nothing since
    		      generations, remove from sb code?"
    The "combined" mode was removed. It wasn't used by any mobo and the code for
    it is almost identical to IDE one other than few bits relating to interrupt
    handling and ISA mode.
    
    Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4658
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2dd601efafb54433e1bbf60f3936eeba7ef353e2
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 03:40:08 2014 +0100

    ibexpeak: Fix timings for IDE mode.
    
    Change-Id: I3c89bb633c32a2c2db349cb4fcbe1ed1c8deb5af
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4657
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 11a7c84f858812c2a02d9a2b96415f2cad93447e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 10:55:31 2014 +0100

    ec/lenovo/h8: Implement sticky Fn option.
    
    Useful for accessibility.
    
    Sticky modifier (sticky Fn) is a behaviour of modifier key when
    you don't have to hold it pressed to achieve the result. E.g.
    with normal Fn brightness up is:
    <Press Fn> <Press Home> <Despress Home> <Depress Fn>
    With sticky Fn you can do:
    <Press Fn> <Depress Fn> <Press Home> <Despress Home>
    
    Change-Id: I4da5adcea02428d936023891de08684cae77c44e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4661
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fc7090b249ddfc7d5332ca8bee0f322607643960
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 10:29:14 2014 +0100

    ec/lenovo/h8: Add an option to swap ctrl and fn.
    
    Tested on my X201 and X230.
    
    Change-Id: I3c7ec65681157d15c6e87eea64779a08e03ae5a8
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4660
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 128741682250e196ccc9ff0bf9e7a5db5dfcdbd3
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 12 14:12:15 2014 +0100

    CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file
    
    Number one reason to use cbfs_get_file was to get file length.
    With previous patch no more need for this.
    
    Change-Id: I330dda914d800c991757c5967b11963276ba9e00
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4674
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 0af61b6c82d7ff02426a26bf435b7c6ee768a602
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 12 13:45:52 2014 +0100

    lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content
    
    Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4659
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit e4ac9c043a9bb0a6601bbdca1a99a3811f7c94d8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 11 03:42:09 2014 +0100

    ec/lenovo/h8: Remove wlan_enable and wwan_enable from device tree.
    
    wwan_enable was never used.
    wlan_enable isn't something for device tree but for CMOS config if at all.
    
    Change-Id: I765d9d6f0b73b7dc5a57c0c630a53b4b7a0b48cb
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4651
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cd4774084469ab44f2f6c3f195537e618e965db4
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Nov 18 11:57:45 2013 +0100

    arch/x86/acpi/globutil.asl: Make control method `S2BF` serialized
    
    This changes eliminates a warning from the ASL compiler.
    
    Change-Id: I502cca731b6b4cd3e17c57fc191f1eed10a5a1fe
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/4093
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 8ebc72cddae96aac8728f8ffc6882637ea073cec
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Jan 4 12:19:18 2014 +0100

    util/cbmem/Makfile: Add rule `junit.xml` for Jenkins
    
    The rule has the target `junit.xml` and runs `make clean` and `make` and
    logs the result in the file `junit.xml` suitable for consumption by
    Jenkins.
    
    Change-Id: I42a31f6c7a45fa9c3773969d78f745fcc4e09dbd
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/4611
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a151c1232988bb62612bd4000b0fd9ec297893b9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Jan 10 19:28:18 2014 +0100

    3rdparty: update to current HEAD
    
    It includes a sandybridge fix.
    
    Change-Id: I84ff1ac1622b10a4a4aa42517bac0c024c386998
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4642
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 08fec4605830b1a525e7cacab7d31f18f455d4c3
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Jan 10 19:41:54 2014 +0100

    lint: check label style only on changed files
    
    This should probably propagate to the other lint checks.
    The idea: only enforce style on files that were at least touched
    by the developer.
    
    Change-Id: I5ac690ee726e27e80e790fa9a41cd14b84ad2161
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4644
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 5d1ada0f6431962bef812844c79e01ba5048e6fa
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Jan 10 20:01:26 2014 +0100

    intel/fsp: Fix microcode including
    
    IS_ENABLED() requires the full define (incl. CONFIG_ prefix)
    but isn't needed here.
    
    Change-Id: I91d504367c75ce3fcecc6fa2499afaa0896595d3
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4646
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 54124d3e5689f7ca8d27090c5ef0512876f8ec2d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 26 02:42:52 2013 +0100

    Remove sprintf
    
    Remove sprintf as if you can't easily use snprintf then you probably
    have buffer overflow.
    
    Change-Id: Ic4570e099a52d743aca938a2bfadb95981adc503
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4280
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a37383db8081b66eafc3860ede23edbfd39ac8ad
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 26 02:41:26 2013 +0100

    Replace all occurences of sprintf with snprintf
    
    THis reduces risks of bufer overflows.
    
    Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4279
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4b5012a4a2bf804d395ae3a72c76f50c4a9189db
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 26 22:07:47 2013 +0100

    console/vsprintf: Implement snprintf
    
    snprintf is a safe variant of sprintf. To avoid buffer overflows
    we shouldn't use sprintf at all. But for now let's start by
    implementing snprintf in first place.
    
    Change-Id: Ic17d94b8cd91b72f66b84b0589a06b8abef5e5c9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4278
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 697c1ed1ff93c3da040dd4bff0cbd1886bd5bf05
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 9 11:06:37 2014 +0100

    X201: set default USB debug controller to 2.
    
    The other port is not easily accessible.
    
    Change-Id: I6ea31346a375debcd5fc1c27e4078e3a436715e3
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4635
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 6a7aeb3b35bc119286c83355af67812b4871467e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Jan 5 11:37:32 2014 +0100

    bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurable
    
    DRAM reset gate GPIO is different on different mobos move it to hidden config
    with 60 (current value) as default.
    
    Set it to 10 for Lenovo X201.
    
    Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4622
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit ffd4a610ba5d1ec00d166f221485e99ffe12d909
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Dec 25 03:00:39 2013 -0500

    cpu/allwinner/a10: Import raminit code from uboot
    
    The memory initialization code is a work in progress for uboot, so we
    only import the bits needed to get RAM up and running. Any refactoring
    is cosmetic, and any functional refactoring should be done in separate
    patches, and preferably, in coordination with the sunxi team.
    Since it's not yet determined if we should initialize memory during
    the bootblock or romstage, we don't add raminit to the build just yet.
    
    Change-Id: I2ec1821942c6970150a02fa3806a257da649e1c9
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4597
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit cce6c1c92ae521bd0f661af2ad30a7cada8fa949
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Dec 31 13:20:27 2013 -0500

    cpu/allwinner/a10: Add low-level helpers for DRAM clock control
    
    PLL5 is special in that it controls the DRAM clock, and requires a
    fine-grained low-level control which will be needed by raminit code.
    This change also brings functionality which will be needed by
    raminit.
    
    Change-Id: I25ecc91aa2154e504ceebb9003a5e5728d47f4a3
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4593
    Tested-by: build bot (Jenkins)

commit 5d8b0a9fb31ff5d595aab08165ce686dd1a65dfc
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Dec 31 00:57:30 2013 -0500

    cubieboard: Initialize memory in bootblock
    
    Even though the Allwinner A10 is limited to a 24KiB bootblock, the
    memory initialization takes only about 3KiB and leaves enough room for
    an MMC or NAND driver, so init the memory early on. The advantage is
    that we can eliminate complicated logistics of where to cache CBFS and
    where to load the ramstage in SRAM.
    
    Change-Id: Id549552ed509434e831db60deaef28e04d62417f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4630
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 391622ae30d36ff6a666892d2da7eba67120a400
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Dec 26 02:02:00 2013 -0500

    cubieboard: Keep AHB clock within specs
    
    The CPU was clocked at 384MHz in the bootblock, but the AHB bus has a
    maximum rated frequency of 250MHz. Its clock needs to be divided to
    keep it within spec. Overclocking the AHB bus hung the CPU when
    memory was accessed.
    
    Change-Id: I7cb9cdd1f126b3d5b0446fc68af79b54946bc2d3
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4629
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 30c20e92a28c8a993baf41415c8a36410ca97c2d
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Jan 2 04:01:52 2014 -0500

    cubieboard: Turn on green LED during bootblock
    
    Change-Id: I807060bde374e4a42abe306cecf838ab157c9515
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4600
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 919e499a364bebd0032f2f7b92051fb4f301f66f
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Jan 2 03:59:24 2014 -0500

    cpu/allwinner/a10: Add functions for driving GPIO pins
    
    Change-Id: I9473a6e574c3af02d154a7e30245f0dc0b238300
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4599
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 6ed574a661dcf85dea9d093fdcd4c060d51d08d2
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Jan 2 03:22:03 2014 -0500

    cpu/allwinner/a10: Add definitions for in/output GPIO functions
    
    Change-Id: I2b857d3b4c01e39c62e54f753e400e6049f1dbc9
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4598
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit a94bed01165b7571ac186d55a45f6d53d45c48ba
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Jan 2 01:57:53 2014 -0500

    cpu/allwinner/a10: Add function for reading chip revision
    
    Change-Id: Iafbd253235db3914b9382fdb41de2622ef83c6d8
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4596
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit bd09dbe3300eca302b84a8fe64cb302889089ab2
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Dec 31 00:17:19 2013 -0500

    cpu/allwinner/a10: Implement udelay using timer 0
    
    Change-Id: I4825f0d57696cd28751c59ae133b7e3315fb78e5
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4595
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit b70a140bd02ef5320c094f555b42dc1875dab2d5
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Dec 31 15:34:43 2013 -0500

    cpu/allwinner/a10: Add definition for gating GPIO S clock
    
    This bit is not documented in the datasheet, but is used in the
    upcoming RAM init code.
    
    Change-Id: I697ec222496236ac7690460ee62313ab8b1a2f0b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4592
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 5c4bde70ae92626fc92ee51249912961a668bba1
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Dec 28 21:50:54 2013 -0500

    cpu/allwinner/a10: Add basic TWI (I²C) driver
    
    Change-Id: I11b10301199e5ff1a45d9b7d2958cc7b6667a29c
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4588
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bc30b2b225a31f7fcf4e25014a73739641a8df71
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Dec 24 16:48:03 2013 -0500

    cpu/allwinner/a10: Refactor API for gating clocks to peripherals
    
    Rather than having to track which bit in which register should be
    cleared or set to gate or ungate the clock to a certain peripheral,
    provide a simplified enum which encodes the register and bit. This
    change comes with a function which decodes the enum and gates/ungates
    the clock.
    
    This also removes the register-dependent bitmasks for APB0 and APB1
    gating registers.
    
    Change-Id: Ib3ca16e54eb37eadc3ceb88f4ccc497829ac34bc
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4571
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8226dbbf1d85be662ab6d427ca80c305cf0b719d
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Dec 22 21:30:21 2013 -0500

    cpu/allwinner/a10: Refactor and document pinmux API
    
    Include a function to multiplex more than one pin at a time. This
    is useful for peripherals that have the same function number for
    all their pins.
    Since we now have two functions for muxing pins, also document
    them.
    
    Change-Id: I53997cc3a2586e3cf749cd672f69fb427659c67f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4565
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit be32f51aa180bd132caa790452b8c0e7920c3afb
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Dec 22 18:51:29 2013 -0500

    cpu/allwinner/a10: Clarify the usage of SRAM during bootblock
    
    We have 32KiB of usable SRAM right when we boot. The first 24KiB can
    be loaded with our bootblock, while the other 8KiB can be used as
    stack during the bootblock stage.
    
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Change-Id: I48d3a37869031c3c1dbc1fab71204d473d64deeb
    Reviewed-on: http://review.coreboot.org/4563
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 14964dd3726971e47c2df6eff49d23a62e07963b
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Dec 13 20:25:04 2013 -0600

    mainboard: Add preliminary support for A10-based Cubieboard
    
    Add a minimal infrastructure which initializes the system clocks
    and serial console.
    
    Change-Id: I768ede6ccf8674ffe9fecd8925cec89768209cab
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4553
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f64111b4865d611821950b25dc1ea235d8d9ca79
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Dec 13 20:44:48 2013 -0600

    cpu: Add initial support for Allwinner A10 SoC
    
    Add minimal support needed to get a bootblock capable of initialising
    a serial console.
    
    Change-Id: I50dd85544549baf9c5ea0aa3b4296972136c02a4
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4549
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 34286b861a9427520f3f3afb8bf64bfa7de37c24
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Dec 21 21:08:53 2013 +0100

    libpayload: add junit.xml build target
    
    It builds all defconfigs/* and logs the results
    in junit.xml, suitable for consumption by jenkins
    
    Change-Id: I86c4022851b47820c95359b2ea9b735a77b1bc2c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4551
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 25cd678d22e236716c23d6d115139a29f86f7fae
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Dec 21 12:47:49 2013 +0100

    libpayload: update defconfig
    
    Just clean out stuff we don't even have anymore
    
    Change-Id: I2b4128c6496b4400d52d87680bedc3cece3d444c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4550
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fdb348a1d12965b8f6566b217466d50b8c015020
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Dec 21 11:41:22 2013 +0100

    libpayload: reintroduce optional PCI in XHCI driver
    
    being a good citizen on the box, libpayload tries to return to EHCI
    mode on shutdown, so a non-XHCI capable USB driver after it (eg. in
    the OS) finds something to work with.
    
    Change-Id: Id227d646e08a258b841c644263112f0815dd486c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4547
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4dba06a827af7962c9441a5f6a08f8f9b95224e0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jan 4 09:42:02 2014 +0200

    CBMEM: Fix allocation for static CBMEM
    
    CBMEM console buffer size is adjustable in menuconfig, but this would
    not correctly adjust the overall allocation made for CBMEM.
    
    HIGH_MEMORY_SIZE is aligned to 64kB and definitions are moved down in
    the header file as HIGH_MEMORY_SIZE is not used with DYNAMIC_CBMEM.
    
    Try to continue boot even if CBMEM cannot be created. This error would
    only occur during development of new ports anyways and more log output
    is better.
    
    Change-Id: I4ee2df601b12ab6532ffcae8897775ecaa2fc05f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4621
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 5b353002a96f1cad9be96b14781f391c6d3faeff
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jan 5 08:49:29 2014 +0200

    CBMEM: Drop cbmem_base_check()
    
    This function was for logging only, but we have both base and size
    already logged elsewhere.
    
    Change-Id: Ie6ac71fc859b8fd42fcf851c316a5f888f828dc2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4620
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit cb28f3f8ed13cdd9ae17441dacf6409eaf390105
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jan 3 15:15:22 2014 +0200

    CBMEM ACPI: Move resume handler
    
    Handler is ACPI/x86 specific so move details out of cbmem code.
    
    With static CBMEM initialisation, ramstage will need to test for
    S3 wakeup condition so publish also acpi_is_wakeup().
    
    Change-Id: If591535448cdd24a54262b534c1a828fc13da759
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4619
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 8526c3a4035c61e65814ef1fbe69b26311440d0c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jan 3 08:20:50 2014 +0200

    usbdebug: Fix hidden menuconfig options
    
    Options for selecting the USB port and controller for usbdebug
    were unintentionally hidden with commit 8232bc2c on AGESA platforms
    using cimx/sb700 or cimx/sb800.
    
    Change-Id: Ibacc81a580519fe7fa86f08374046625327340b4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4607
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit e51210dbaeafb91d9eb03eddcd061cfc94a48eab
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Jan 4 20:58:55 2014 +0100

    MRC cache: determine flash size on runtime
    
    It should be possible to put coreboot compiled for smaller chip by
    putting it at the end of bigger chip. We already have chip size in
    flash->size. Use it.
    
    Tested on Lenovo X230.
    
    Change-Id: If8ff03ed72671a9f2745ed4e759a04e83aa7cc37
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4612
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 00ea28ecf9a9524824c652cd834428bf61fa62e8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 2 10:12:21 2014 +0100

    nehalem: Simplify smi.c by using __SIMPLE_DEVICE__
    
    Change-Id: Ib5bac45ee7aa5492c10fa97cd75b828b6192250d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4604
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 98dda06e7ae3dba0a53f13a5436675deeceff733
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jan 2 10:08:19 2014 +0100

    cpu/cpu.h: Allow compiling with __SIMPLE_DEVICE__
    
    Change-Id: I14a2ac47198be6359b4f10b38f1cf86c9917d67e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4602
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 503e4fef17666b1145aba21313f471ddb727a074
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Jan 3 04:27:39 2014 +0100

    X201: Fix native video init
    
    Due to recent restructuring X201 native video init has disappeared from
    config options. Put it back and fix compilation with it.
    
    Change-Id: I6d9ba5da196c093abd2df89a6fe5efefece1fb3c
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4606
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 47777569d234ff4ed0703ac176586bd09d3ed992
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Jan 2 09:19:21 2014 +0100

    board-status: fix weekly format
    
    The last few days of the year might belong to the first
    week of the new year in the ISO week numbering scheme.
    
    GNU date accounts for that with different-than-usual
    notation.
    
    Change-Id: I8047c197971077a845d6c1fdc9da6eb9f3741539
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4610
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fd3451d72d49cc08a2c2ad6fd5f9a4174b42b0e4
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Jan 3 09:45:57 2014 +0100

    device/Kconfig: Add third person singular s to lacks
    
    Change-Id: I74be0dbbf8d99f58ac28bfac281ccd27d1500078
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/4608
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 812d624fd0384a5603c03a5055e9d0f7dd446dd4
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Dec 26 08:24:16 2013 -0700

    asrock/imb-a180: Configure the 6 COM ports and the keyboard
    
    Change-Id: I66d0715f3be201f8068acd7097e2be49185bee00
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4574
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 6c6acd79a0f8a1f6aa639d8cf3a0ac1dc90ba07e
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Dec 26 08:17:16 2013 -0700

    superio: Uncomment the w83627uhg UART clock source initialization
    
    The asrock/imb-a180 mainboard is the first mainboard to use this
    w83627uhg/nct6627UD sio. The default h/w clock setting is 0. Adding
    the SIO in the mainboard Kconfig made the builder complain that the
    set_uart_clock_source() wasn't being used. So the calls to that function
    were uncommented.
    
    Change-Id: Iedba035237c5c0fa230b02ff4799bb8c1b7bbd4a
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4573
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 892d12922064e962be976a36d94b600804aeb6cc
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Dec 11 12:38:40 2013 -0700

    Add the gizmosphere/gizmo mainboard
    
    Gizmo is a AMD-Family14 based board. More information can
    be found at www.gizmosphere.org
    
    Change-Id: I5cfd161b4f408be1f65cf332b083ed7c79a99cfd
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4536
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit ea8d4607ce496b48fe5946ec309663261558f634
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Dec 23 09:55:33 2013 +0200

    AMD K8 (rev F): Move rev F0/F1 workaround to header
    
    Place this in header so it works also when raminit_f.c and
    raminit_f_dqs.c are not #included in romstage.c build.
    
    The workaround remains to be disabled for all boards.
    
    Change-Id: Iff0271ceb21ee1e28a1a31d6bbdb97e29d76461e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4568
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 5c62375222997d62a796a521b9c8af521882dbe2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Dec 22 23:14:27 2013 +0200

    AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge
    
    Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all
    K8 rev F boards do the same things here.
    
    Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4567
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 7d3045b517907d0827d5800b1bfb399a3df5ada7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Dec 22 20:48:40 2013 +0200

    AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT
    
    Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4558
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit b316585eaf3dbaa14c3f8ccb704dd2e0d37ed5ea
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Dec 23 09:56:36 2013 +0200

    AMD K8 (pre-F): Clean platforms without K8_REV_F_SUPPORT
    
    Change-Id: Ie109f58bd8ce54754b8d0b00118e75ace8717df0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4566
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 0946190e15f7aed3fdad5a60ef76cb1c6051c69c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Dec 29 08:25:47 2013 +0200

    AMD K8 (rev-F): Always have RAMINIT_SYSINFO
    
    K8 Rev F raminit code cannot be built without RAMINIT_SYSINFO,
    so have the option enabled together with K8_REV_F_SUPPORT.
    Also move the option under AMD K8.
    
    Change-Id: I91fa0b4ae7e3e54fbcb4a4f91eb043956cd0fb60
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4582
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 239c3d32f0e83685940cf1e15f1fb31747016e55
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Dec 27 14:46:32 2013 +0200

    AMD fam10: Drop RAMINIT_SYSINFO
    
    AMD fam10 raminit cannot be built without RAMINIT_SYSINFO, this
    is not a true option but copy-paste remainder from AMD K8.
    
    Change-Id: Id8edc112f3bacebd1732304ac9ee6e77cc6263b7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4581
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1709453bad5560b03e6d46aedc834e476074b658
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Dec 27 14:46:13 2013 +0200

    via/epia-m700: Drop RAMINIT_SYSINFO
    
    Option is for AMD K8 only.
    
    Change-Id: Ic55288b3cae2c9bf4f347037e7bf5d9bfcf16689
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4580
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 2e77461051ffd600d37a820130537b681514c410
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Dec 22 20:42:58 2013 +0200

    AMD K8: Socket implies K8_REV_F_SUPPORT
    
    K8_REV_F_SUPPORT is already set by all affected sockets, (AM2, F, S1G1).
    
    Change-Id: If42a4178263d90a4e195fae0c78943ac9eda1ad6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4557
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 475e1b9095d15c02daa6bf41a88d5e1245ed10be
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Dec 27 15:21:58 2013 +0100

    via: Write »access« without »m« at end
    
    The comment was copied around so fix all occurrences using the following
    command.
    
    	$ git grep -l accessm | xargs sed -i 's/accessm/access/g'
    
    Change-Id: I46e117c126c0f851cd5e95cf9e42a77ca5f80996
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/4577
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ba6c2663ed45b6bd82e324ede4e903176181dcfa
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Dec 22 18:00:22 2013 +0200

    AMD AGESA: Drop MEM_TRAIN_SEQ
    
    This config was for AMD K8 only.
    
    Change-Id: Ic1ce60041fef6ddee2dae0e3559fb78f088740af
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4556
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 6c57f64e58c80d9d5d9213dc4a0f3131b6aecd77
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Dec 22 18:00:22 2013 +0200

    AMD fam10: Drop MEM_TRAIN_SEQ
    
    This config was for AMD K8 only.
    
    Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4555
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 142b52cd322ff69afe974f90a446f62b193d120c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Dec 10 07:33:36 2013 +0200

    AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includes
    
    Change-Id: Ib3a69e3364418426438f88ba14e5cf744e2414fa
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4524
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 88a67f0cc9d0bec08a6cfa5b1c3f4198fd98ab4f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Dec 12 12:27:53 2013 +0200

    AMD boards (non-AGESA): Cleanup earlymtrr.c includes
    
    Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4523
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit 1c434ff2d6200777ec0f6f806ebe8bb45f939dc8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Dec 12 12:27:53 2013 +0200

    vortex86ex: Cleanup earlymtrr.c include
    
    No MTRRs on this platform.
    
    Change-Id: Iaef57c8013ae9d40f3b063aae284b3faeeaa43dd
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4572
    Tested-by: build bot (Jenkins)
    Reviewed-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit b32816e9a5564e3604c3829b92727b54356f4777
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Dec 20 17:47:19 2013 +0100

    Remove PCI_ROM_RUN option
    
    The main purpose of option rom is to supply int* handlers.
    But supplying those is outside of coreboot scope and if someone needs those
    they should run SeaBIOS anyway which runs the option roms wonderfully.
    
    Running VGA oprom is kept because they're needed to init graphics.
    
    This patch still keeps the options to include the option roms to make them
    available to SeaBIOS.
    
    Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4545
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Kevin O'Connor <kevin@koconnor.net>

commit 50ecb9c11131a31bc6f0d0e0b5fcbd5aab36e5e0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Dec 6 21:50:55 2013 +0200

    usbdebug: Add option to disable console for romstage
    
    If there is trouble setting up usbdebug, it may be useful to delay
    usbdebug init to run in ramstage.
    
    Change-Id: I31de5a06d3f9ce19f71c422cce0c8cb0fd50f396
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4488
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit d26da9c8f0794f473f476a69821abffb52996237
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Sun Dec 22 21:38:18 2013 +0000

    Coding style: punctuation cleanup [1/2].
    
    Clean up superfluous line terminators.
    
    Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/4562
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit c6c8cb7f799f81a55b94c1e64ee13773dfc7f631
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Dec 7 18:57:02 2013 -0600

    Fix linking microcode with more than one microcode file
    
    When assembling microcode , the rule to link individual object files into
    one larger file only passed the first dependency to the linker. As a results
    only microcode from one object file would actually get linked. This is fixed
     by replacing $^ with $+ inside the make rule.
    
    Change-Id: I65c0565f2e03777af23e530c08d1241804ca19b1
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4500
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fea5b50febb1d0cb37f8f77a44e5a0d6634c539d
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Thu Oct 31 20:12:09 2013 +0800

    vortex86ex: Change PCI S/B resource reservation functions for more I/O devices.
    
    Originally, Vortex86EX PCI S/B internal resource reservation functions can
    only support one big legacy I/O device space (0-0xfff).
    
    Change function signature to support other non-legacy I/O device space in
    the future.
    
    Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3976
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 44af57a78bcb478f70f3047fcf950424f8e8e01c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Dec 19 22:06:22 2013 +0100

    buildgcc: defer cleaning up the tree a bit
    
    cleanup() uses BUILDDIRPREFIX, which is set after the
    getopt loop.
    
    Change-Id: I8a904781ee4fefc42681d31e94b64008cf03750a
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4544
    Tested-by: build bot (Jenkins)
    Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>

commit 9d1d7409686465f51bf6d940fc17f595e8d51f0e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Aug 8 14:12:20 2013 -0700

    lynxpoint: XHCI: Don't put device in D3 in _PS0 Method
    
    The end of the _PS0 method that is supposed to transition the
    XHCI device to D0 state is instead putting it in D3 state.
    
    This triggers a PME_B0 GPE which causes a Notify to the XHCI
    ACPI Device in the kernel and that increments the wakeup counter
    and causes aborted suspends.
    
    Instead if we just leave the device in D0 where it should be
    after executing this function then the PME_B0 is not generated
    and the kernel does not see a wakeup on XHCI.
    
    Similarly I changed the _PS3 method to always put the device in
    D3 at the end of the method, rather than depending on the state
    to be D3 at the start.
    
    Before this change the kernel would see the following sequence
    when trying to suspend when the XHCI controller is in D3cold:
    
    kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28)
    kernel:   evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [XHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802bc30
    kernel:   evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [EHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802b8e8
    kernel:   evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [HDEF] (Device) Value 0x02 (Device Wake) Node ffff88017802b1b8
    kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0
    kernel: xhci_hcd 0000:00:14.0: PME# disabled
    kernel: xhci_hcd 0000:00:14.0: enabling bus mastering
    kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64
    kernel: PM: Wakeup pending, aborting suspend
    kernel: last active wakeup source: 0000:00:14.0
    
    Now it does not get a notification (due to PME_B0) when going to D0
    on the way into suspend.  XHCI goes from D3cold to D0 (in order to
    be able to read mmio) and then back to D3hot before suspend.
    
    kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28)
    kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0
    kernel: xhci_hcd 0000:00:14.0: PME# disabled
    kernel: xhci_hcd 0000:00:14.0: enabling bus mastering
    kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64
    kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._S3D] (Node ffff88017802c000)
    kernel: xhci_hcd 0000:00:14.0: PME# enabled
    kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
    kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff88017802bf50)
    kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D3hot
    
    Change-Id: Id5cd28eede2b27d97640047feb17349ae4ab79b7
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65236
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4448
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0bf1dea8d82efff46847d3a6b0f5dac5667b40fe
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Aug 13 13:32:28 2013 -0700

    lynxpoint: Fix an issue clearing port change status bits
    
    The coreboot and ACPI code that clears USB3 PORTSC change status
    bits was not properly preserving the state of the PED (port enabled
    or disabled) status bit, and it could write 0 back to this field
    which would disable the port.
    
    Additionally add back the code that resets disconnected USB3 ports
    on the way into suspend (as stated in the BWG) but take care to
    clear the PME status bit so we don't immediately wake.
    
    suspend/resume with USB3 devices
    
    1) suspend with no devices, plug in while suspended, then resume
    and verify that the devices are detected
    2) suspend with USB3 devices inserted, then suspend and resume
    and verify that the devices are detected
    3) suspend with USB3 devices inserted, then remove the devices
    while suspended, resume and ensure they can be detected again
    when inserted after resume
    
    Change-Id: Ic7e8d375dfe645cf0dc1f041c3a3d09d0ead1a51
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65733
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4473
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 568ce5ce1318e2e5e50af0e1207eff3d90f29b1d
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 30 16:15:14 2013 -0700

    lynxpoint: XHCI: Advertise D3 as lowest wake state
    
    The recommended value in docs is D2, but lynxpoint XHCI does not even
    support D2 state which causes the kernel to think this device cannot
    be used as a wake source:
    
    kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
    kernel: ACPI: Device does not support D2
    kernel: xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
    
    Additionally this means the kernel will never put the device into D3
    state by itself.  There is SMI code that will put the device into D3
    before suspend so advertising D3 here should be correct.
    
    With this change the kernel will put the controller into D3 on suspend
    and back to D0 on resume, including executing the ACPI methods
    for _PS0/_PS3 that contain chipset specific workarounds.
    
    In addition add a _PSC method to directly return the D state from the
    device registers.  With ALL USB devices removed the XHCI controller
    goes into D3 state and the kernel can have a hard time determining
    the state of the device at boot.
    
    A kernel compiled with CONFIG_ACPI_DEBUG=y and module parameters
    acpi.debug_layer=0x7f acpi.debug_level=0x2f can be used to see
    what ACPI methods are executed:
    
    kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
    kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff8801000a7f50)
    kernel: ACPI: Preparing to enter system sleep state S3
    ...
    kernel: ACPI: Waking up from system sleep state S3
    kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff8801000a7f28)
    kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0
    
    Change-Id: Ic64040eb4dd1947a1e2f0ee253a64be683e0ec70
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    
    meld with s3d
    
    Change-Id: Ic6789720c4efe661dcb03a4afce8d88115854472
    Reviewed-on: https://gerrit.chromium.org/gerrit/63916
    Tested-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4409
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0dcb577652026dea116b87b0c3dd0fb16ec0aed3
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 30 15:58:18 2013 -0700

    lynxpoint: Fix issues with XHCI init
    
    - Put the device into D0 and not D3 so memory bar is available
    and the subsequent commands actually do something useful
    - Remove set of 818Ch[7:0]=FFh (gone in ref code)
    - Fix reg 0x40/0x44 mixup
    
    Verify that expected bits are set:
    localhost ~ # pci_read32 0 0x14 0 0x10
    0xe0500004
    localhost ~ # mmio_read32 0xe0508144
    0x000003ff
    localhost ~ # mmio_read32 0xe050816c
    0x000f0038
    
    Change-Id: I388398e8c7d11e538ca18dab55d8bbd9b88f17df
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63801
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4408
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 911cedff97c45f0794f014ceb16a83edafd028c0
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 30 16:05:55 2013 -0700

    lynxpoint: Route all USB ports to XHCI in finalize step
    
    This commit adds a new Kconfig option for the LynxPoint
    southbridge that will have coreboot route all of the USB
    ports to the XHCI controller in the finalize step (i.e.
    after the bootloader) and disable the EHCI controller(s).
    
    Additionally when doing this the XHCI USB3 ports need
    to be put into an expected state on resume in order to make
    the kernel state machine happy.
    
    Part of this could also be done in depthcharge but there
    are also some resume-time steps required so it makes sense
    to keep it all together in coreboot.
    
    This can theoretically save ~100mW at runtime.
    
    Verify that the EHCI controller is not found in Linux and
    that booting from USB still works.
    
    Change-Id: I3ddfecc0ab12a4302e6034ea8d13ccd8ea2a655d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63802
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4407
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1f529083fca3e7a39d3cfacc0f6bb02c2d232362
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 30 15:53:45 2013 -0700

    lynxpoint: Move USB SMI sleep code to separate USB files
    
    Move this to the existing USB source files so they can share some
    helper functions and keep the main smihandler code cleaner.
    
    The XHCI sleep prepare code now implements the actual sleep
    preparation steps from the ref code instead of the docs.
    
    Change-Id: Ic90adbdaba947a6b53824e548c785b4fb3990ab5
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63800
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4406
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c81187f2312ef3487fa6bd534dcc689317f9423e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 1 19:09:21 2013 -0700

    pit: disable LCD FETs before doing any graphics init
    
    This ensures that the LCD FETs are off before we do graphics init.
    
    FIXME: The location of the code is sub-optimal and should probably be
    done in romstage, but there are __PRE_RAM__ considerations to take
    into account.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I0844030d0a0e51eee1d29f1762f0b495777268df
    Reviewed-on: https://gerrit.chromium.org/gerrit/64305
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4470
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1ad77de62dabe68edd3792f2f6538224cb27773c
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Aug 12 14:52:45 2013 -0700

    exynos5420: Assign corect parent PLLs
    
    Assign correct parent PLL's for the following clocks:
    ACLK_400_WCORE (MPLL->CPLL) (400 -> 333MHz)
    PCLK_200_FSYS (MPLL->DPLL) (200 -> 200MHz)
    MUX_ACLK_100_NOC_SEL (MPLL -> DPLL) (100 -> 100MHz)
    ACLK_266 (DPLL->MPLL) (300 -> 266MHz)
    ACLK_200_DISP1(MPLL->DPLL) (200 -> 200MHz)
    ACLK_400_MSCL(MPLL->CPLL) (400 -> 333MHz)
    ACLK_66 (MPLL->CPLL) (66.666 -> 66.6MHz)
    MUX_ACLK_400_DISP1_SEL (CPLL->DPLL) (666 -> 300MHz)
    MUX_MPHY_REFCLK (MPLL->OSC)
    MUX_UNIPRO (MPLL->OSC)
    MUX_MIPI1 (EPLL->OSC)
    MUX_DP1_EXT_VID (EPLL->OSC)
    MUX_FIMD1_OPT (EPLL->OSC)
    MUX_IPLL(IPLL->OSC)
    This also corrects the clock dividers for few of the clocks,
    as the clock parent changes affect the final frequency of the
    clocks.
    
    This is ported from: https://gerrit.chromium.org/gerrit/#/c/62437/
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: Ie833c01913d0961a6190446bd573511de8dee5f8
    Reviewed-on: https://gerrit.chromium.org/gerrit/65620
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4469
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7f35bbb0d4c2993f227b83250c5c5df0d02139e3
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Aug 12 13:24:24 2013 -0700

    exynos5420: don't assume MPLL for i2c parent clock
    
    This reads the clock select field for MUX_ACLK_66_SEL in the
    CLK_SRC_TOP1 register in order to obtain the source clock rate
    for I2C peripherals. Before we were always assuming that the source
    was the MPLL.
    
    Unfortunately not all fields in the CLK_SRC_TOPn registers are
    enumerated the same with regard to clock select. So this is just
    a one-off for now.
    
    This is basically ported from https://gerrit.chromium.org/gerrit/#/c/62443.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I9fa85194ae1a1fadab79695f059efdc2e2f1f75f
    Reviewed-on: https://gerrit.chromium.org/gerrit/65611
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4468
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b783d4585ff6c229ec76619c3f9666070e19359e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Aug 9 18:59:02 2013 -0700

    exynos5420: Set SPLL to 400MHz
    
    Increase SPLL to 400MHz from 300MHz as we set SPLL as the
    switching parent for ARM and KFC. This value is as per
    recommendation of the hardware team.
    
    This is ported from https://gerrit.chromium.org/gerrit/62618
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I8a5a5b957083b0b1f3e3e318fe5753cf7ae19223
    Reviewed-on: https://gerrit.chromium.org/gerrit/65432
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4464
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 401da258275aa630fba30576602e1dfeecc955dc
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 8 20:45:53 2013 -0700

    exynos5420: re-factor clock_get_periph_rate()
    
    This re-factors clock_get_periph_rate() to be a simpler and also
    make a few corrections along the way. To summarize:
    
    - clk_bit_info is no longer used. It had numerous errors and was
      really painful anyway since it was just a bunch of opaque magic
      numbers that made bugs non-obvious.
    
    - Clock source bitfields for peripherals handled in the switch
      statement are 3 bits, not 4. Some divider values are 3 bits,
      some are 4. The earlier code always assumed 4 bits for both
      which included reserved bits in many cases.
    
    - UART source clock and divider shift values were wrong.
    
    - PWM clock divider was being read from the wrong register.
    
    - SPI3 divider value was being read from the wrong register.
    
    - There was a really confusing calculation for SDMMC0 and SDMMC2
      clock rates, but it was never actually used since the switch
      statement never handled PERIPH_ID_SDMMC{0,2} and would thus
      return if they were ever passed into this function.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I0a03a64d8b42fbe83dbf377292597ce681b22f4b
    Reviewed-on: https://gerrit.chromium.org/gerrit/65284
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4463
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit efd4b9e936d11816cec3f4ab1aa3d897c8cfd0e5
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 8 19:03:03 2013 -0700

    exynos5420: add a peripheral clock select --> PLL decoder
    
    This adds a helper function to translate between peripheral clock
    select fields in clock source registers and PLLs. Some of this was
    already done to handle a few special cases, this generalizes the
    earlier work so that follow-up patches can do further clean-up.
    
    Unfortunately, the PLLs represented by clock select fields in
    various modules are not uniformly ordered. So for now we focus on
    peripheral clock sources only.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: Id58a3e488650d09e6a35c22d5394fcbf0ee9ddff
    Reviewed-on: https://gerrit.chromium.org/gerrit/65283
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4462
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5f6ffbab1b67ed34aac4b85ae9e64dbd08e373f2
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 8 16:16:40 2013 -0700

    exynos5420: add CPLL and DPLL to the known list of PLLs
    
    This patch adds CPLL and DPLL to the known list of PLLs.
    
    This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af
    Reviewed-on: https://gerrit.chromium.org/gerrit/65282
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4461
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bd56bf0dcff59d38066715438a9350f50136fcc3
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 8 16:04:07 2013 -0700

    exynos5420: correct the PMS value for CPLL
    
    This patch matches the User Manual Table 7-2 about the PMS value for
    CPLL. This doesn't change the PLL frequency (before and after both make
    666MHz) but this is the suggested PMSK values for obtaining 666.
    (Suggested as per user manual).
    
    This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: Ia33e1971ab88da761000d443792560476514626b
    Reviewed-on: https://gerrit.chromium.org/gerrit/65281
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4460
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 136e7090152d91ad0e1efcf4869e23fbaa6f453c
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Aug 9 00:31:09 2013 -0700

    exynos5420: Configure the UART pins unconditionally
    
    Configure the pins for the UART unconditionally in the mainboard code (when we
    know which UART to configure) instead of in the UART driver. This also means
    the UART will work if later software wants to use it without setting up the
    pins.
    
    Built and booted on pit with the serial turned off and some serial init
    in the kernel decompression stub fixed.
    
    Change-Id: Icab5755e4f935f52d44b9cb3b43d1cb62acce08f
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65299
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4457
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ce011ec1317eebdcec91f29d206869ac0a71c23a
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Aug 6 16:00:37 2013 -0700

    exynos5250: Implement support to boot with USB A-A firmware upload
    
    This patch implements the basic infrastructure required to use the USB
    A-A firmware upload feature on Exynos5 processors with Coreboot. It will
    require a corresponding host-side script that activates the feature and
    uploads the correct image parts in the correct order to harcoded target
    addresses, as described in the comments of alternate_cbfs.c.
    
    Also fixes a bug in the Google Snow mainboard where it would not
    correctly initialize the pinmux configuration for the SPI flash bus.
    During a normal SPI boot the IROM would already do that for you, but
    when booting from USB you have to do it yourself.
    
    Change-Id: I40a39f8f5d1d70b58dbf258015c1653a27097d67
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64875
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4456
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 20316321fbf4cab423961f73df31795ec6dea670
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Aug 8 11:07:40 2013 +0800

    armv7: Allow accessing ACTLR (Auxiliary Control Register)
    
    The ACTLR provides implementation defined configuration and control options for
    the processor.
    
    Change-Id: I74df1ed7887eb3f16a1b8297db998ec2f8b18311
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65107
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4447
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e0cfad2b563a26365041dcf75fe7b8302fcab5a4
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 8 14:09:46 2013 -0700

    exynos5420: re-factor the SDMMC GPIO config routines
    
    The existing GPIO config routines for SDMMC0-2 are over-generalized
    and somewhat confusing as a result. It would work nicely if all SDMMC
    ports were configured in the same fashion, but there are a few
    exceptions.
    
    For example, the inner function runs differently if we're using 8 bits
    of data instead of 4, so a big chunk is skipped for SDMMC2. SDMMC0
    requires SD_0_CDn to be an output rather than alternate function and
    must have a value set.
    
    This patch trades some verbosity for simplicy. Now the SDMMC GPIO
    configuration a straight-forward sequence of GPIO operations
    without any exceptions.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: If75075b24c6588c4c1b3be3fb9b1aa95e2fac2d1
    Reviewed-on: https://gerrit.chromium.org/gerrit/65248
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4446
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b9f267ce231635029d37d42d31702ab979784da5
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 8 14:51:07 2013 -0700

    exynos5420: configure SD_0_CDn as VDDEN for eMMC
    
    On Exynos5420 the MMC channel 0 is connected to eMMC
    Which does not have a card detection pin. Also this pin
    is connected as VDDEN to PMIC.
    
    This is ported from https://gerrit.chromium.org/gerrit/#/c/60732/
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I19048d22b7dd00df1716b6b5b332a7eb70fe0836
    Reviewed-on: https://gerrit.chromium.org/gerrit/65247
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4445
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 93951f4ed8b15c7140961a24d7fa756e3ec204ff
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Aug 8 11:27:27 2013 +0800

    armv7: Add CPU & MP primitive instructions
    
    To configure multi-processors, we need the intrinsic functions to get core ID,
    put core into idle state, and to wake up cores.
    
    Change-Id: I87a62dab6efd6c8bb0c8e46373da7c7eb7b16b35
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65112
    Reviewed-on: http://review.coreboot.org/4444
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 792b621ac03cb0d0eab065374f912a103a7b4080
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Aug 5 21:09:32 2013 -0700

    exynos5420: init APLL at 1800MHz
    
    This initializes the APLL at 1800MHz.
    
    Change-Id: I366bf4e75510847ab93d9c9f214a49c731cca08a
    Reviewed-on: https://gerrit.chromium.org/gerrit/64745
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4443
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f05e8713007fa61f20dfa39a5176f8d5427cd673
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Aug 6 15:17:37 2013 -0700

    exynos5xxx: use oscillator clock when changing ARM frequency
    
    Switch ARM clock source when changing the APLL frequency to avoid
    stability issues.
    
    This is ported from https://gerrit.chromium.org/gerrit/#/c/64189/5
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I923107555e6d3287b3694cbf9e4bb548d3e5f4a8
    Reviewed-on: https://gerrit.chromium.org/gerrit/64838
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4442
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 49c1be95d32f7106da2aef2c8f94709457081e7a
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Aug 6 18:05:55 2013 -0700

    exynos5420: set L2ACTLR parameters for A15 cores
    
    This patch does the following for the A15 cores:
    - Disable clean/evict push to external
    - Enable hazard detect timout
    - Prevent gating the L2 logic clock
    
    This is ported from https://gerrit.chromium.org/gerrit/#/c/60154
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I7ac9f40acecfa7daee6fb81772676bf5119d0536
    Reviewed-on: https://gerrit.chromium.org/gerrit/64862
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4441
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e6789c139b3f2a098188ba48547dad46d0302e22
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Aug 5 22:19:36 2013 -0700

    snow: Set up the i2s0 pins during boot
    
    Change-Id: I6729a139091b40d8fd9ba2aa7a8c4e14216d95c5
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64879
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4440
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4e195afdf70f2a2daaa628d4e449a841f09d1b5c
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Aug 5 22:15:21 2013 -0700

    exynos5250: Add a pinmux function to set up i2s bus 0
    
    This bus is hooked up on snow and, as it's the only bus hooked up on some
    other boards, having it available in firmware to test is handy.
    
    Change-Id: Icb48b9af4a67d382bd6fbce1e4c6a320d811d365
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64877
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4438
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 36e62c2516ef46e726af79da3d14dfa416e468ab
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Aug 6 17:32:41 2013 -0700

    armv7: add wrappers to read/write L2ACTLR
    
    This adds inline wrappers to read the L2 cache auxiliary control
    register (L2ACTLR).
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: Iec603d7c738426232f7ce3a4a474d01c85fa3f2f
    Reviewed-on: https://gerrit.chromium.org/gerrit/64861
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4437
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 49832975c3c0ea152873f868d829f6ed819bb915
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Aug 6 15:36:44 2013 -0700

    ARM: Don't inject nobits since we actually want to load these bits
    
    Change-Id: I128e3ecc3773fe7c28616e93ef60b48c5862f302
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64839
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4436
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c1471396a48d2620c9f51b3fdd85f0a71ced8635
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Aug 6 04:30:13 2013 -0700

    ARM: Remove (NOLOAD) from the .car section
    
    On ARM, if the .car section is marked as NOLOAD, there's nothing that sets it
    to zero. Some code in the cbmem console depends on a global variable being
    zero initially, and if that's not true bad things happen.
    
    Change-Id: Ic72a9fb0ee0c5a608190be6f24d0d7de7c34fc1f
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64769
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4435
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 56a7cff7f665e5ac6859bad384a6fcff19f117d3
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Aug 5 18:53:15 2013 -0700

    exynos5420: minor correction to CPU frequency print
    
    This divides the CPU frequency by 1,000,000 instead of 2^20.
    
    serial console shows "CPU:   S5P5420 @ 800MHz" instead of
    claiming 762MHz.
    
    Change-Id: I70cc5b62f689c5553b57c82be61233fb9f733f6e
    Reviewed-on: https://gerrit.chromium.org/gerrit/64743
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4434
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c0491d4fb55eaa7a18cb46dfab886eeb195b9323
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Aug 6 10:48:48 2013 +0800

    armv7/exynos: Fix and remove memory reset workarounds
    
    The memory corruption problem in Exynos suspend/resume process is caused by two
    things together: PHY_RESET and MRS command.
    
    After stop sending MRS on resume, we can now remove the workaround of skipping
    PHY_RESET.
    
    Change-Id: I64acc27c1d2bb549ae6ad7d32ecda94b0355972c
    Reviewed-on: https://gerrit.chromium.org/gerrit/64736
    Tested-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/4433
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c0d5eb2a332a7db1311517032e6f9ce1d5b91551
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Thu Aug 1 11:38:05 2013 -0700

    Pit: graphics
    
    This includes the new dp code, which is better, and the fimd code,
    which is changed and improved. We took the chance to remove un-needed
    files, and also to remove some foolish u-boot habits, but not all of
    them. That will take time.
    
    With these changes we get graphics.
    
    Since the only mainboards we have with 16 bit graphics are 5:6:5,
    adjust edid.c to just use that format. If at some future time we need
    4:4:4, which seems unlikely, we'll need to add a function to adjust
    the lb_framebuffer. Note that you can't just divine this from the EDID,
    as the graphics pipe format need not match the actual final format used.
    
    The EDID reading works. We've been requested to support hard-coded
    EDIDs and that will come in the next revision. Currently the hard-coded
    EDID is ignored for testing.
    
    Change-Id: Ib4d06dc3388ab90c834f94808a51133e5b515a4d
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64240
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4432
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 052bf4ba2108ecc354c08f64dc57290c9509fd22
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Nov 6 16:38:21 2013 -0800

    kirby is dead. long live the arm pit.
    
    Remove kirby from our tree. It's dead.
    
    BUG=none
    BRANCH=none
    TEST=none
    
    Change-Id: I0768a9ea40be5d70d845a46f6e28036a133b7aa6
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/176030
    Reviewed-by: Ronald Minnich <rminnich@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4548
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 01b438367c18573a57cf2d374b47d3f04dcc67ef
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Mon Aug 5 17:18:44 2013 -0700

    Snow: correctly disable trust zone hardware
    
    The kernel assumes that trust zone is disabled.
    
    Change-Id: Ia8d6fa69adcb812a747d8b89eb77e57144423eaa
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64722
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4431
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b0efbd39108928a790a346cac46d1b2364147198
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Aug 5 15:56:37 2013 -0700

    Pit: correctly initialize trust zone
    
    This ensures that various trust zone things are reset,
    which is important because the kernel assumes they are.
    
    Change-Id: Ie02ea89885621f58a3ccc4f1729617208a264153
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64697
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4430
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fffbda5897059d642dd3d8facd2a14ada6da416b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jul 31 16:28:44 2013 -0700

    ARMv7: Fix location of CBMEM console in romstage
    
    The CBMEM console pointer in romstage is actually a zero byte array.
    This means CBMEM area has to live at the end of the allocations or
    else CBMEM console will overwrite whatever comes after it.
    
    Change-Id: Icc59e982b724a2d396370c3a5abd8898e08baf26
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63997
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4428
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1f9f04e57117aea8e06be4fc49f3d7fa8b096389
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 1 18:57:52 2013 -0700

    pit: update PMIC write sequence in romstage
    
    This update the PMIC write sequence to be correct for newer board
    revisions.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I2210b0d1945fb19c96a674c8fad1b0ff5a4a381e
    Reviewed-on: https://gerrit.chromium.org/gerrit/64304
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4427
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d598cac656d214bbdfdfa11426cca4bee6aed216
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 1 18:17:55 2013 -0700

    exynos5420: update set_cpu_id()
    
    The current function seems to be outdated...
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    built and booted. Now we see "CPU:   S5P5420 @ 762MHz"
    instead of "CPU:   S5PC420 @ 762MHz"
    
    Change-Id: Ieb103a5fa62bda9a6b2cbd9a82fb4f72c5dd6466
    Reviewed-on: https://gerrit.chromium.org/gerrit/64302
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4425
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8ccabb6877c443d7905b02c9d9e5bafdc3994d82
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 1 19:12:56 2013 -0700

    snow: TPS69050 -> TPS65090
    
    This corrects a minor typo used for a part number.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I8583cbfc3b4a6c3ad06419f5aab3ba7a8f685575
    Reviewed-on: https://gerrit.chromium.org/gerrit/64301
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4424
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit aa6061a0d0032065e210789c52af5d9b0a375ba9
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jul 31 23:40:55 2013 -0700

    kirby: pit: Fix up wakeup_need_reset
    
    In a previous commit the contents of wakeup_need_reset were removed because
    the GPIO it referred to wasn't connected to anything on pit. I didn't realize
    at that time that that could have been because we hadn't tried getting
    suspend/resume working on pit and hadn't updated that file. On snow, the GPIO
    is the recovery mode pin. This change updates pit to have the right GPIO,
    kirby to read that GPIO, and makes the comments for both pit and kirby more
    explicit and spells out the fact that this is the recovery mode GPIO.
    
    Having a check here at all may still be a holdover from snow that isn't
    applicable to pit or kirby, but since there is a parallel as far as the
    recovery mode GPIO we might as well make them match while waiting for more
    information.
    
    Change-Id: Ic1f3f605a0fddf89e8f5668c7a8df30bdfb91d94
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64164
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4421
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 925ad2efad9743e402d88fbc6344731e3f2c2ba3
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jul 31 23:21:34 2013 -0700

    pit: Get rid of the mostly unnecessary exynos5420.h
    
    Like on kirby, this header had a single constant in it that was actually used.
    This change moves that constant inline and gets rid of the header file.
    
    Change-Id: Ibe380396f72fddb121fb6ceb3cee24f1b9a85738
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64163
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4420
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 88fdd930ac91e21887545911acbbd08b68707d0f
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jul 31 22:50:21 2013 -0700

    exynos5250: Add mct_start to the timer init blob in timer_monotonic_get
    
    A previous change removed init_timer from timer_monotonic_get because its old
    implementation set up the PWM based timer which was going away. It would still
    be a good idea to initialize the timer at that point, just not the pwm.
    
    Change-Id: I4816710ec2c9d5ca53b704c6b9397bcfac183fdc
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64160
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4419
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 61cd11187d17db572069f0af8434aeac38f19448
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Jul 30 22:43:47 2013 -0700

    kirby: Clean some cruft from mainboard.c
    
    1. Kirby doesn't have a backlight enable GPIO on the AP since that's handled
    entirely by the DP-to-LVDS bridge.
    2. There is no tps65090 on the other side of the EC who's settings need to be
    adjusted. If we need to turn on the LCD or backlight power manually, it will
    have to be done in a different way.
    3. The PMIC doesn't provide a 32KHz output for the audio codec.
    
    Change-Id: Iadc5f3aec4818805edf3f2517da9e6fee87085dc
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63883
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4413
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 318cb10eb9fad5b33d2326c4cd2a9b6788fbd68f
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Jul 30 22:41:13 2013 -0700

    kirby: Neutralize wakeup.c and delete the mostly unused exynos5420.h
    
    The function in wakeup.c isn't applicable on kirby. The only constant in
    exynos5420.h that was used was the speed of the 4th i2c bus. Instead of having
    a whole header file for that one constant used in one place, the constant is
    just moved inline along with the comment it had in the header.
    
    Change-Id: I5ad50c5eeaecbbf7865d76afb31a12d36c3371ee
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63882
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4412
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9245440eaf6d77175a76b68162917997a3152d24
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Jul 30 21:35:31 2013 -0700

    Add a kirby board which is mostly a copy of pit
    
    Change-Id: Ic78c65486816015f7574a13affc6e54acbbea73e
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63875
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4411
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 74dbfc252ff07a9c9b7fcf4511e561991d5bd46d
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Jul 30 13:46:58 2013 -0700

    arm: Remove __image_copy_end from the ARM linker script
    
    That symbol isn't used by anything and doesn't appear in other linker scripts.
    
    Change-Id: Iab54ecb3be2e262d7674ef8ee7ed13ea2e5b56f3
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63776
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4399
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 80e6293a89fd3e0dc564b2ac04063aa4aa7cafab
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jul 29 15:52:23 2013 -0700

    Exynos 5420: Enable dynamic CBMEM
    
    ...  In order to do this, the graphics memory has to move into
    the resource allocator and out of CBMEM.
    
    Change-Id: I565c3d6dea747822fbabf6f3845232d4adfbf333
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63657
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4391
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 662874446a55356ed74ebf7acdcfa276752214bf
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 19 15:54:19 2013 -0700

    Exynos 5250: Enable dynamic CBMEM
    
    ...  In order to do this, the graphics memory has to move into
    the resource allocator and out of CBMEM.
    
    Change-Id: I7396da4a7068404b0d2e4d308becab4dd6ea59bb
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59326
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4390
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d9a98581ce5f94b2c8278aafcbb845f630ad7d71
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Dec 21 11:02:14 2013 +0100

    armv7: Prepare tables code for dynamic CBMEM
    
    The CBMEM API is different for dynamic CBMEM,
    so hide the functions that get in the way (but
    our compiler complains about)
    
    Change-Id: I7634a202059548e56c74fe3fe6eff57bc60f1a1b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4546
    Tested-by: build bot (Jenkins)

commit 88750cb3b60fa1d351a69b35ff10c739f4f4e8ce
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Jul 16 17:30:16 2013 -0700

    google/pit: disable SYSMMU for graphics
    
    It's not needed and it's a potential problem source.
    
    Change-Id: Ic4cafe74e7fc3a9031d852895ad7fd5e5cd64d11
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/62279
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4410
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ea3a463460fcc679a25fd8d028fa01515164abae
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Aug 1 18:48:26 2013 -0700

    max77802: update header
    
    This adds #defines for BUCK2DVS1_1_2625V and BOOSTCTRL_OFF.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I363c73ff4a645da53973767fa4bfa2c120394af6
    Reviewed-on: https://gerrit.chromium.org/gerrit/64303
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4426
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 997be3d2eef923024907a2b8ff37e6cb23394b9d
Author: Furquan Shaikh <furquan@google.com>
Date:   Wed Jul 31 13:17:30 2013 -0700

    Refactor code containing aux calls
    
    Moved a lot of code from i915io.c to intel_dp.c with specific function calls
    
    Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc
    Reviewed-on: https://gerrit.chromium.org/gerrit/63950
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Reviewed-on: http://review.coreboot.org/4429
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 771c3aca70e6fa8eb0b3ad5f6b6478578bfb5e85
Author: Furquan Shaikh <furquan@google.com>
Date:   Thu Aug 1 13:58:17 2013 -0700

    Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flags
    
    Depending upon the values decoded from edid, the function decides the appropriate bits to
    be set in flags parameter (Important for fastboot to work correctly in kernel)
    
    Change-Id: I3b0f914dc2b0fd887eb6a1f706f87b87c86ff856
    Reviewed-on: https://gerrit.chromium.org/gerrit/64265
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    Reviewed-on: http://review.coreboot.org/4423
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit db3157cfee6881d8095c4f96cd1fa5d5da9a5c68
Author: Furquan Shaikh <furquan@google.com>
Date:   Wed Jul 31 16:47:31 2013 -0700

    Add cpu transcoder attribute to intel dp
    
    Also, used this attribute in the calculation of htotal and other registers
    Added intel_dp_* functions for m,n registers and dimension register calculations
    
    Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a
    Reviewed-on: https://gerrit.chromium.org/gerrit/64001
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    Reviewed-on: http://review.coreboot.org/4422
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d0a81f75342508449d13fd05305864413470e0c9
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Jul 30 12:41:08 2013 -0700

    Calculate transcoder flags based on pipe config
    
    Works fine with all three panels with the change of 6 bits per color.
    
    Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e
    Reviewed-on: https://gerrit.chromium.org/gerrit/63762
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    Reviewed-on: http://review.coreboot.org/4402
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 10bd772db854c62528c67b9d0e5e329c525d83f9
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 16 11:03:27 2013 -0700

    Enable CAR migration on Exynos 5250 and 5420
    
    Despite calling romstage memory CAR in this case, the variables actually
    do live in SRAM on the Exynos CPUs. However, in order to share as much
    generic code as possible, we're using the same infrastructure here.
    
    Change-Id: I85173c37099a25f3e55980e88120401826cdf29c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/62188
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4394
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c59fda321697974d467dc7ae8f7b22b43a1899af
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Tue Aug 13 10:50:15 2013 -0700

    peppy: Set optimal DTLE register values
    
    Empirical testing shows that 0x5 is the optimal setting for DTLE DATA /
    EDGE on Peppy.
    
    Change-Id: I273a3a68be97b3eb7c2ee2071e5de1ef7bf7f2d9
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65717
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4476
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 287522749ececda35b52dc9b9e8e704e305ec888
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Tue Aug 13 10:45:21 2013 -0700

    lynxpoint: Add configuration option for SATA gen3 DTLE registers
    
    Allow DTLE DATA / EDGE registers to be configured in board-specific
    devicetree.
    
    Change-Id: I82307d08c9cf73461db3ac7fb875a4fe70d6f9ea
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65716
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4475
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 190688c65f7c128f2dace3b600d1c0f2e56723ee
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Aug 13 11:18:42 2013 -0700

    haswell: add option to change DqPinsInterleaved
    
    Some mainboards will need to have this set.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0
    Reviewed-on: https://gerrit.chromium.org/gerrit/65722
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4474
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8818b9d0d416b42f6d88307a93cf98825f1413da
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Aug 12 14:11:39 2013 -0700

    wtm2: disable SDcard USB port
    
    This is causing hangs in depthcharge (again?) so for now
    turn that port off so the resulting coreboot images are
    at least useful.
    
    Change-Id: I32c7774a95b0020b97105e0fa42c21ccb617c718
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65615
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4467
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3106d0ffce85fe07feefb5c488802aab8e9b42f6
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Aug 12 13:51:22 2013 -0700

    haswell: Misc updates from 1.6.1 ref code
    
    These programming sequences were changed in the latest code.
    
    Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65612
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4466
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4fb3a61fc6e11686a95c09f63e194fba0cb899f6
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Aug 9 10:12:51 2013 -0700

    slippy/falco/peppy: Fix EC wake events in S5
    
    The SMI handler code was setting S3 wake events when going
    into S5 and enabling a key press to wake the system.
    
    Change-Id: I6413ef1341e0149187df9f4f7e0c314d4c9e9c6e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65323
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4459
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 727b5455fbdd3003005da83039f92c96354b53a2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Aug 8 16:28:41 2013 -0700

    Add a specific post code for S3 resume failures
    
    If the firwmare is flashed and the MRC cache is blown away
    then it is not possible to resume.
    
    Right now this can be inferred from the event log but it can
    be made very clear by adding a unique post code for this event.
    
    1) boot falco
    2) flash firmware
    3) suspend and then resume
    4) check for post code 0xef in log
    
    0 | 2013-08-08 16:27:47 | Log area cleared | 4096
    1 | 2013-08-08 16:27:47 | ACPI Enter | S3
    2 | 2013-08-08 16:27:55 | System boot | 48
    3 | 2013-08-08 16:27:55 | Last post code in previous boot | 0xef | Resume Failure
    4 | 2013-08-08 16:27:55 | System Reset
    5 | 2013-08-08 16:27:55 | ACPI Wake | S5
    
    Change-Id: I7602d9eef85d3b764781990249ae32b84fe84134
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65259
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4458
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7e1c83e31bdd4b0aeebb2ed0916959a472c2369f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Aug 9 07:55:10 2013 -0700

    Add Kconfig options to override Subsystem Vendor and Device ID
    
    These can typically be set in the devicetree but we need a way to
    override those values with a Kconfig setting so as not to expose
    the Vendor ID before the product has launched.
    
    Change-Id: Ib382e6d9359d24b128c693a657ffde52604efad3
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65310
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4455
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d538e8fb0006c4ea2d689f2d99e28f9786a6fc2e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Aug 9 09:11:29 2013 -0700

    falco: Force enable ASPM on PCIe Root Port 1
    
    Boot on falco and look in /sys/firmware/log for
    the string "PCIe Root Port 1 ASPM is enabled"
    
    Change-Id: Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65315
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4454
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 249a03b080be30cccecf37354b19fc8b918be447
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Aug 9 09:06:41 2013 -0700

    lynxpoint: Add devicetree config option to force enable ASPM
    
    The PCIe root port has ASPM settings/workarounds that are only applied
    based on the value of an undocumented bit in PCI config register 0x32C.
    
    If that bit is not set for some reason then the settings are not applied.
    This devicetree config option will force the ASPM settings for each port
    based on the bit map.
    
    Change-Id: I40b08ca9a0ef52742609bac72fb821454a373799
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65314
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4453
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0b3cd36061d853a470f38415f71ca78bb3f9d331
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Aug 8 15:40:01 2013 -0700

    lynxpoint: me: Disable some verbose messages
    
    The default ME output is quite verbose and not all that useful
    unless you are actively debugging the ME and then you can enable
    the CONFIG_DEBUG_INTEL_ME option.
    
    This commit silences the firmware capabilities and the MBP output.
    
    Change-Id: I2b8abcb34ae0d00d9a38d029979e84ee0d0ca287
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65252
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4452
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c45dc1c08131dfaf5f8a26927b40006660c1ebf6
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Aug 8 15:33:34 2013 -0700

    falco: Disable unused clocks
    
    CLKOUT for PCIE ports 1-5 and CLKOUT_XDP are not used
    and can be disabled.
    
    I couldn't test this directly without a scope so instead I
    used a modified commit that also disabled PCIe Port 0 and
    saw that that correctly disabled the WLAN port.
    
    Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65251
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4451
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0dc0d1383df258bbb18dec18e0bf7e00dfda1651
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Aug 8 15:31:51 2013 -0700

    lynxpoint: me: Support ICC clock enables message
    
    This message allows unused clocks to be disabled based on a
    devicetree setting in each mainboard.
    
    Change-Id: Ib1988cab3748490cf24028752562c64ccbce2054
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65250
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4450
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2017b4a44fcb8dcf01852d00391d71be5c041523
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Aug 8 15:07:12 2013 -0700

    lynxpoint: me: Allow for more than MKHI MEI messages
    
    The original ME code was assuming that the only type of messages
    it would send were MKHI type and so it had some embedded checks
    for that header and that type of message.
    
    In order to support ICC messages this needs to change to handle
    different header types, so now the header will be sent first
    and then the data will follow, rather than the two both being
    sent in the same low-level function.
    
    This change has no real affect on the system, subsequent commit
    will add new ICC messages.
    
    Change-Id: I52848581e49b88c0a79e8bb6bda2a179419808a3
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65249
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4449
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5fcfece7568f55b205f095aaa310e4ea95054bad
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Jul 31 15:35:55 2013 -0700

    falco: Enable EC controlled throttling
    
    When the EC requests the host to throttle (for charging or thermal
    related reasons) the package power consumption will be limited.
    
    Right now this is set at 12W but that is somewhat arbitrary and may
    need tuning.
    
    1) define the THRT method in \_TZ scope for EC to call
    2) enable SCI events for throttle start and stop
    3) define the power limit at 12W and set it in NVS
    
    1) Enable CONFIG_ACPI_DEBUG=y in the kernel
    
    2) Enable the Debug object event in acpi module
    acpi.debug_layer=0x7f acpi.debug_level=0x2f
    
    3) Using EC console generate host event for throttle start
    > hostevent set 0x20000
    
    4) Check dmesg for throttle start events
    ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q12] (Node ffff8801002c5988)
    [ACPI Debug]  String [0x12] "EC: THROTTLE START"
    [ACPI Debug]  String [0x10] "Enable PL1 Limit"
    
    5) Using EC console generate host event for throttle stop
    > hostevent set 0x40000
    
    6) Check dmesg for throttle stop events
    ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q13] (Node ffff8801002c59b0)
    [ACPI Debug]  String [0x11] "EC: THROTTLE STOP"
    [ACPI Debug]  String [0x11] "Disable PL1 Limit"
    
    Change-Id: I39b53a5e8abc2892846bcd214a333fe204c6da9b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63989
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4416
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d338b46504bde900a18fc32eff7cda14ba3711b4
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Jul 31 15:30:41 2013 -0700

    chromeec: Add event methods for EC requested throttle
    
    Two new events possible from the EC for starting and stopping throttle.
    
    These are handled in a per-board method that is defined under the
    thermal zone.  This is not quite where I wanted it but the scoping
    rules in ACPI don't let me have a defined external object in the
    same scope.
    
    Change-Id: I766f07b4365b29df3daa8e45e88f7c38c645c287
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63988
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4415
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7ad61f6262c3056232c414ed9482b7d6f8719948
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Jul 31 14:08:59 2013 -0700

    falco: Drive GPIO59/LTE_DISABLE_L low on S3/S5
    
    Try to prevent WWAN from causing spurious wakes.
    
    Change-Id: Ifcc44063de0eb1634cab9dd244737071568e3455
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63987
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4414
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7b4c4325e92ba39265a3ed32a6b2aec6a8864985
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Jul 25 09:23:00 2013 -0700

    pit: Add missing elements to the edid data structure
    
    When the edid data structure changed a while ago, it caused hangs on snow
    which were fixed by adding those missing members. Unfortunately we didn't
    realize that pit needed the same fix.
    
    Change-Id: I81780b8135b99b2e24af723e703b9befff7b5ef0
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63646
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4389
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c422002b5f819de97d12dfec16cc55488f28642e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Jul 24 16:02:14 2013 -0500

    tpm: provide explicit tpm register access
    
    An issue was observed using a specific vendor's TPM in that it
    chokes on access to registers that are not explicitly defined in the
    PC client specification. The previous driver used generic access
    functions for reading and writing registers. However, issues come
    to play when reading from the status register. It read it as a 32-bit
    value, but that read address 0x1b which is not defined in the spec.
    
    Instead of using generic access functions for the tpm registers
    provide explicit ones. To that end provide more high level wrapper
    functions to perform the semantic access required.
    
    Change-Id: I781b31723f819e1387d7aa25512c83780ea0877f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63243
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4388
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 980180962a1855220de08779fa4697c78757614a
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jul 24 06:18:20 2013 -0700

    pit: Bump the EC SPI bus speed up to 5 MHz
    
    That speed is used with U-Boot instead of the more conservative 500 KHz.
    
    Change-Id: Ie9d79db3b52b88c1f3bfec1745634ae6bdc9f4ee
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63193
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4386
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e13680bdd04f4d2128f024123784a9131f76faad
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jul 24 03:57:49 2013 -0700

    exynos5420: Fix some clock settings
    
    Some registers and bit fields were wrong, but the difference is mostly
    academic since the code that uses them are never called.
    
    Change-Id: I0ce5e1529cdda1a4973765af8c31b79130b1111c
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63189
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4385
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ad88fda1cf8ad21db47be4a212e1d6e6239d058b
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jul 24 04:06:37 2013 -0700

    exynos5420: Fix the clock divisor mask
    
    The divisor mask had been set to 0xff, but the bitfield is 4 bits wide.
    
    Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63188
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4384
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit dd8f60363a007b43714fa8c0a6044fb6c7fb9866
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Jul 30 13:52:27 2013 -0700

    arm: Don't use const pointers with the write functions
    
    This functions are by definition changing the data pointed to by their
    arguments, so they shouldn't by const.
    
    Change-Id: Id29b3f76526aba463f8bb744f53101327f9c7bde
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63777
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4400
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 713853a9c8fca493567548fe3cf0b8107b7fc138
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jul 31 22:48:20 2013 -0700

    exynos5420: Get rid of the PWM code like on the 5250
    
    The timer code was supposed to be using the mct, and also using the monotonic
    timer infrastructure instead of the get_timer function. This change had been
    made for the 5250 but not yet for the 5420.
    
    Change-Id: I03a4fbb434f2346761f28fb6bd2218b526f2a4a2
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64159
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4418
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9b764a0dcc67a7bbf6e74b35cdd9e3e7c6d59c83
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Jul 30 15:11:35 2013 -0700

    exynos5250: Get rid of the PWM timer code we shouldn't be using anymore
    
    This code was left over from U-Boot and was superceded by the MCT.
    
    Change-Id: Ia85e3b7281dcdd4740238dddd0dfc6f0ba2c94da
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63778
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4401
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2c116febabe3619933d361ca4289df899ec83e3d
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jul 31 22:13:24 2013 -0700

    exynos5420: Apply pwm const fix to the 5420 as well
    
    When the const was removed from write function arguments, a related bug in the
    5250 code was fixed so that it would still compile. Unfortunately, that same
    change needed to be made to the 5420.
    
    Change-Id: If15057c92422de91dc8e35dbd8b5c978bfae122a
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64154
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4417
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9a9d7e8ad049041bec21b29180e2dc94d8ef37e2
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Jul 30 13:38:13 2013 -0700

    exynos5250: Fix consts in the pwm code
    
    The code generally intended to make the pointer const instead of the thing it
    pointed at, but it had const backwards. Sometimes both the pointer and the
    data could be const, but sometimes there were writes where only the pointer
    should be.
    
    Change-Id: Ifcd5495769b86b47d7b583cce63ed5c2158bec4e
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63775
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4397
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit c0f82d222294b339582a5b15aadccab2933364c4
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jul 24 03:50:18 2013 -0700

    arm: libpayload: Include stdint.h in cache.h
    
    The cache.h header uses standard int types but doesn't include stdint.h itself.
    
    Change-Id: If470978164b0cd1f05c27c2c8eda365133cc47ff
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63190
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4387
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7b6cc0403fb00d8795894bb27e9b7faff3fbe130
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Aug 14 11:31:39 2013 -0500

    falco: add rtd2132 settings to device tree
    
    Now that the rtd2132 device has the full settings the
    panel timings need to be implemented. Sadly, the Tx timings
    in the rtd2132 aren't 1:1 with the panel's Tx timings. Below
    is the table equivalent:
    
      RTD2132 | Falco Panel
      --------+------------
         T1   |    T2
      --------+------------
         T2   | T8+T10+T12
      --------+------------
         T3   |    T14
      --------+------------
         T4   |    T15
      --------+------------
         T5   | T9+T11+T13
      --------+------------
         T6   |    T3
      --------+------------
         T7   |    T4
      --------+------------
    
    Change-Id: I10a3ad475d6b9485a707eb49e31afd197fc8d24d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65858
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4472
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ebad1765542d63fd873d62fb52ca9e150c9b6291
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Aug 14 11:27:40 2013 -0500

    rtd2132: implement full configuration
    
    It has been disseminated that the RTD2132 chip
    needs to be fully programmed for settings to take affect.
    Most of the settings are note documented very well and
    present themselves as magic values. Also, the wait time
    for starting the sequence needs to be bumped from 2ms to 60ms.
    Lastly, expose all the known settings through devicetree.
    
    Change-Id: I9eeea9c4a13ec20b8ce1c5297e43c4dd793d90e5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65857
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4471
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 08637d3c9e408161cfed33bec381a632e2283d79
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Jul 29 16:39:00 2013 -0600

    Remove PS/2 keyboard initialization on resume from S3
    
    When we go through the resume path, there shouldn't ever be a need to
    initialize the PS/2 keyboard.  The OS is going to reinitialize it
    anyway, and it just slows the resume.
    
    Verified Code flow in normal boot/S3 resume with print statements.
    Verified Keyboard was correctly disabled and flushed by booting
    to recovery mode screen while pressing keys on the integrated
    keyboard.
    
    Change-Id: I48bdca2fa2cc0c965401d10fef75cadb09d2e1e9
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63648
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4396
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3ee59f7b313e41b8379c54f00bba2526f0d0d43b
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Fri Jul 26 16:31:21 2013 -0600

    Libpayload: Add keyboard-disable function.
    
    Add a function to disable and clear the keyboard controller.
    
    Verified Code flow in normal boot/S3 resume with print statements.
    Verified Keyboard was correctly disabled and flushed by booting
    to recovery mode screen while pressing keys on the integrated
    keyboard.
    
    Change-Id: I3e1f011c3436fee5ce10993c6c26a3c8597c6fca
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63627
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4395
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2f38b07570d504b82878efa55e55a144a81d54ee
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jul 18 16:24:08 2013 -0700

    Add simple hexdump function
    
     - prints hex and ascii
     - detects duplicate all zero lines
    
    Change-Id: I557fed34f0f50ae256a019cf893004a0d6cbff7c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/62655
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4392
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 063c7c5bf61b07afdebec0b4a079aa69a18ae42d
Author: Yunlian Jiang <yunlian@google.com>
Date:   Fri Aug 9 11:24:00 2013 -0700

    nvramtool: add -MG to makefile to make it pass clang
    
    Change-Id: I7878d2639946c6c2222022a72ba54e4df0fce976
    Reviewed-on: https://gerrit.chromium.org/gerrit/65335
    Tested-by: Yunlian Jiang <yunlian@chromium.org>
    Reviewed-by: Yunlian Jiang <yunlian@chromium.org>
    Commit-Queue: Yunlian Jiang <yunlian@chromium.org>
    Reviewed-on: http://review.coreboot.org/4465
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit dcac1628bcec7d1f566fb2f877438df87f5593d3
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Aug 5 22:16:49 2013 -0700

    libpayload: Include hexdump.c in the Makefile so it gets built
    
    The hexdump function was added to libpayload recently, but its source file was
    never added to the Makefile so it wasn't compiled or linked in.
    
    Change-Id: Ic3c12a5b8a6ea631b83c10a6e4210544ff00b5bf
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/64878
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4439
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0d0b6e20f52ccc6315adc2f4f02bc9eb8b631d68
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Jul 10 17:27:45 2013 -0700

    Pit: set PWM to external on Parade
    
    The PWM is controlled externally from the APU.
    
    Change-Id: Ia5130d7616991a78dfde44043a60a32cee4f145c
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61513
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4363
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c0872f26d7fc4b8a30679ebdc7002ae8c072a0fb
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Jul 10 15:22:17 2013 -0700

    Pit: move parade writes to mainboard.c
    
    What gets written into the parade is highly mainboard-dependent.
    So the parade_writes array needs to be there.
    
    Change-Id: Ia382d9bf1929e67b7c14d7a09f5461b71866a16b
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61486
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4362
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3f1791536159953729cc928b1f03a3236905428c
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Wed Jul 24 11:01:08 2013 -0700

    peppy: Drive WLAN_DISABLE_L / BT_ON low in S3 and S5.
    
    When the board is in S3 and S5 the WLAN_DISABLE_L signal
    can leak power into the WLAN power well since the GPIO
    controlling WLAN_DISABLE_L is in the suspend well. Therefore,
    drive WLAN_DISABLE_L low to avoid the power leak.
    
    This is a clone of a Falco change:
    I1a0df80dd47fdbd535aca7a9d49253794c480606.
    
    Change-Id: I625dfbb228d1f293b880a52dfe552842d55a17d1
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63220
    Reviewed-by: Dave Parker <dparker@chromium.org>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4383
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit aa04ed649442296366bc2bad1936ec5184235069
Author: Furquan Shaikh <furquan@google.com>
Date:   Tue Jul 23 15:53:02 2013 -0700

    Added structure members x_mm and y_mm to edid decoding
    
    Change-Id: I9a628cec4da127a3f072d9611259dad99dfa9d29
    Reviewed-on: https://gerrit.chromium.org/gerrit/63125
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    Reviewed-on: http://review.coreboot.org/4382
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6b19071ffb89dbb68196b7f3b088d87d4fad9e80
Author: Furquan Shaikh <furquan@google.com>
Date:   Mon Jul 22 16:18:31 2013 -0700

    FUI: Fill in link_m and link_n values
    
    ... based on the EDID detailed timing values for
    pixel_clock and link_clock.
    
    Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n
    respectively.  Other two undocumented registers 0x6f030 and 0x6f034 correspond
    to data_m and data_n respectively.
    
    Calculations are based on the intel_link_compute_m_n from linux kernel.
    
    Currently, the value for 0x6f030 does not come up right with our calculations.
    Hence, set to hard-coded value.
    
    Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e
    Reviewed-on: https://gerrit.chromium.org/gerrit/62915
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Reviewed-on: http://review.coreboot.org/4381
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3d9b5a29317b9df63698abbcf743ff4d15b2892a
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Jul 16 17:56:20 2013 -0700

    Slippy: remove unneeded code in i915io.c
    
    This code is left over from what the VBIOS did; It is redundant.
    
    Change-Id: I321c867c81ec8b4d5e10f8b51b872cecb3082d97
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/62290
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Furquan Shaikh <furquan@chromium.org>
    Tested-by: Furquan Shaikh <furquan@chromium.org>
    Reviewed-on: http://review.coreboot.org/4380
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f47c4bcd01ffb1c1279eb94481ca0143608a0983
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 30 15:43:43 2013 -0700

    slippy/falco/peppy: Route USB to XHCI on resume
    
    Turn on the pei_data flag that will instruct the reference code
    binary to route all USB ports to the XHCI controller on resume and
    disable the EHCI controller(s).
    
    Change-Id: I2f2ed853a6d17f90ea524bc516f3e78079222739
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63798
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4404
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 289bac6a04f5cb16a9297c31e7a11013b0b51eb4
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 30 15:41:42 2013 -0700

    haswell: Add pei_data field for USB routing
    
    The linux kernel will unconditionally route all USB
    ports to the XCHI controller at boot.  The EHCI controller
    can then be disabled, and it should be left disabled
    by the reference code when this is done.
    
    However not all OS may do this unconditional route,
    so provide an option to the reference code binary to
    enable this behavior.
    
    Change-Id: Iedf5af54182bf109cd1119c1999e46300665d41e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63797
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4403
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d3c5e50506337a36039fcc42f71de50aadd6f076
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 30 15:33:57 2013 -0700

    haswell boards: fix SATA interrupt in ACPI
    
    SATA is routed to PIRQG which should be interrupt 22
    and not interrupt 21.  The kernel uses MSI with this
    device so this is only seen when booting with pci=nomsi
    
    Change-Id: Ic90ca2c561fc4c53ec1d395c05872222c65ff98a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63796
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4398
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 52e3f449ac06e1f3e8a40647649fa2f94dea1c0b
Author: Julius Werner <jwerner@chromium.org>
Date:   Tue Jul 23 12:45:18 2013 -0700

    libpayload: Increase USB EHCI transfer timeout
    
    The EHCI driver defines a maximum transfer timeout of two seconds. The
    comments state that during tests the maximum amount of required transfer
    time was for the SCSI TEST_UNIT_READY command on certain devices. We
    have now observed a USB device (Patriot Memory 13fe:3100) that can NAK
    this command for slightly more than two seconds. It will also completely
    fail if the timeout hits, since it gets confused by the subsequent CSW
    retry/recovery mechanism and starts producing babble errors. This patch
    increases the timeout to three seconds to circumvent this problem.
    
    To test, boot a Falco from a red-black RageXT USB stick.
    
    Change-Id: I3c4fef468fb16eacc5a487d76d025a78fb450e27
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63095
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Sameer Nanda <snanda@chromium.org>
    Reviewed-on: http://review.coreboot.org/4379
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 68a8431fcf8ce1fdf390f800b311120f37a5598d
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 23 09:13:42 2013 -0700

    haswell: Update microcode revision
    
    CPUID 306C3 Haswell MOB C-0 microcode to 12h
    CPUID 40651 Haswell ULT C-0 microcode to 15h
    
    localhost ~ # grep microcode /proc/cpuinfo
    microcode       : 0x15
    microcode       : 0x15
    
    Change-Id: Ibdfe2b8ef0969b1ccc6dd1642a9fc352b5d11f27
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63045
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4378
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8d716b98d0b0498123f7afc68188f60c9f0c0b6b
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 22 15:33:10 2013 -0700

    slippy/falco/peppy: update ACPI C-state settings
    
    Since these boards do not support C10 we should not bother
    advertising that state in the ACPI _CST.
    
    Instead use this map:
    
    ACPI(C1) = MWAIT(C1E)
    ACPI(C2) = MWAIT(C3)
    ACPI(C3) = MWAIT(C7S)
    
    Change-Id: I37eb02bf9555c74e957316a1ba9778eb2b6ee128
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/62898
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4377
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8056dc657410ee2b82e136548f9ebd00ba98fe30
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 22 08:47:43 2013 -0700

    lynxpoint: Avoid any ME device communication in S3 path
    
    The management engine is occasionally hanging the system on resume
    when it is accessed.  Since we actually don't need to do anything
    with it on resume it can be disabled early in the resume path and
    avoid assigning resources just to remove them later.
    
    suspend/resume on falco and check /sys/firmware/log
    to ensure that device 00:16.0 is disabled early and that no
    resources are probed or assigned and that the device init path
    does not execute.
    
    Change-Id: I35573681e3a1d43d816d24954842cbe9c61f3484
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/62897
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4376
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3d299c4b092d3464ea90ddc338f62b04a61e0c46
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Jul 19 08:48:05 2013 -0700

    lynxpoint me: add support for mbp clear wait in finalize step
    
    The management engine is slow, requiring at least 500ms between
    when the Dram Init Done message is sent (right after memory training)
    to when the MBP will report that it is successfully cleared and
    that the ME can finally be sent the EOP message.
    
    Currently this is adding 100-150ms to the boot time.  If we defer
    waiting for the MBP Clear indicator until the finalize step we
    can gain back that lost time.
    
    boot on falco with SMI debugging enabled to
    ensure that the ME is locked down in the finalize step:
    
    Finalizing Coreboot
    SMI# #0
    SMI_STS: PM1 APM
    ME: MBP cleared
    ME: mkhi_end_of_post
    ME: END OF POST message successful (0)
    
    Change-Id: Icab4c8c8e00eea67bed5e8154d91a1eb48a492d1
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/62633
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4375
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 80fd5c4461041508a9579d698ab89dd97ec2ae15
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Jul 19 08:41:38 2013 -0700

    lynxpoint xhci: Add ACPI D0/D3 workarounds
    
    There are specific programming requirements for the usb3 ports
    on all LynxPoint chipsets when transitioning to D0 or D3.
    
    LynxPoint-LP has additional workaround steps needed involving
    resetting the disconnected ports when transitioning to D0.
    
    The workarounds are implemented in ACPI code so the controller
    can transition properly into D3 at runtime.
    
    Change-Id: I3b428562f48c9cb250b97779a3b2753ed4f81509
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/62632
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4374
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit af98062817e61f4dafd509fd768696a4250f1aa3
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jul 18 23:02:18 2013 -0700

    Revert "lynxpoint: Move ME lock down to ramstage"
    
    This reverts commit ff81f50f0e4c068b64c4a5c7f5244196ecd24965.
    
    Deferring this step until the finalize stage will allow us
    to defer waiting for the MBP clear indicator and speeding
    up the boot.
    
    Change-Id: Ib8edffd06689e72875830cd68b5aedb7ac3b0559
    Reviewed-on: https://gerrit.chromium.org/gerrit/62631
    Tested-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4373
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d8c7d73283676306e383fde4f42547d0ee3b0209
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 16 09:01:43 2013 -0700

    lynxpoint: power management setup tweak
    
    Updated from 161 ref code
    
    Change-Id: I3e07935fec1df21f14d97d165792fe54bf9e474c
    Reviewed-on: https://gerrit.chromium.org/gerrit/62128
    Tested-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4372
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 45df5962c7044713f4631f9483426d9241e36bde
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Mon Jul 8 14:02:57 2013 -0700

    SLIPPY: final changes for FUI
    
    The intel_ddi.c change I thought should be in but I don't see it. It just adds two functions back
    that we need.
    
    There are two new files for slippy annotated with comments about how it needs to evolve.
    
    That said, this code has been tested on 3 different panels. Both dev and non-dev usages work.
    
    physbase initialization to static value removed.
    
    Moved spin calls to intel_dp_*
    
    Change-Id: I0480af45c21c7dedcaff7e8be729f0eb554ec78a
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61136
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4370
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit ebb8a1a819b335525871edabe9dba304c5ef5250
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Sun Jul 14 16:32:42 2013 -0700

    peppy: Duplicate SPD data for 2GB configurations.
    
    Peppy SPD table has 4GB configurations followed by 2GB configurations.
    Current implementation does remapping to point 2GB configuration to the
    same SPD index as the 4GB. This is different than Falco, which simply
    duplicates the SPD data for all configurations. To simplify probing in
    mosys, copy the Falco implementation of duplicating SPD data.
    
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    
    Change-Id: Idb185a437f3cf4f40d2dae1ae59c30235df8f489
    Reviewed-on: https://gerrit.chromium.org/gerrit/61847
    Reviewed-by: Dave Parker <dparker@chromium.org>
    Reviewed-by: Jay Kim <yongjaek@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4369
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 21d4a85042ced5574333e94083d9ee58480b52a9
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 15 10:38:12 2013 -0700

    chromeos: Check for recovery reason code in shared data
    
    When using RW firmware path the proper recovery reason can
    be retrieved from the shared data region.  This will result
    in the actual reason being logged instead of the default
    "recovery button pressed" reason.
    
    1) build and boot on falco
    2) crossystem recovery_request=193
    3) reboot into recovery mode, check reason with <TAB>
    4) reboot back into chromeos
    5) check event log entry for previous recovery mode:
    
    25 | 2013-07-15 10:34:23 | Chrome OS Recovery Mode | Test from User Mode
    
    Change-Id: I6f9dfed501f06881e9cf4392724ad28b97521305
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61906
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4368
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 29f76884092dbd8de492437e9656e48671a12530
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 15 09:17:09 2013 -0700

    haswell boards: Use PECI temp sensor id 0
    
    The EC temperature sensors were renumbered and now PECI
    is at index 0.
    
    1) boot on falco
    2) check /sys/class/thermal/thermal_zone0/temp
    3) check 'temps' on ec console
    
    Change-Id: Idde1457c42c80850b5b8ac22781060ed9b224d13
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61896
    Reviewed-on: http://review.coreboot.org/4367
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit a9dc05130e1a13cb9f6bf55f46071f4977029273
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 15 09:13:04 2013 -0700

    falco: Enable RTD2132 spread spectrum at 1.0%
    
    This may need further tuning but will start at 1.0%.
    
    boot on falco and check /sys/firmware/log
    
    localhost ~ # grep RTD2132 /sys/firmware/log
    RTD2132: Enable 1.0% Spread Spectrum
    I2C: 01:35 (Realtek RTD2132 LVDS Bridge)
    
    Change-Id: I96e1c14dbc6a7bfaf1c8deb1806c48bf2fd3e32a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61895
    Reviewed-on: http://review.coreboot.org/4366
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 0cf0d1499ab4fb86a6c85f83ab4097a62e2e3642
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 15 09:11:21 2013 -0700

    rtd2132: Add driver for Realtek RTD2132 LVDS bridge
    
    This driver allows the mainboard to enable spread spectrum
    clocking at 0.5%, 1.0%, and 1.5% with devicetree settings.
    
    Change-Id: I59c61e67aa8e951fd9904ad951deb6d0ba29669e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61894
    Reviewed-on: http://review.coreboot.org/4365
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 8870733b591834c7d20c4227c95d76e757a76883
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 15 09:07:20 2013 -0700

    lynxpoint: Add LPT-LP device id and smbus_write_byte
    
    This is needed for SMBUS drivers to write to devices.
    It was copied from existing intel southbridge driver.
    
    Change-Id: Id0ce2393b2946a9c741413bca563a1a4dc0a4f5e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61893
    Reviewed-on: http://review.coreboot.org/4364
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 05d065cff5fe7a83cb7e5776dc9c6610032ac412
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Jul 12 12:46:11 2013 -0500

    bolt: make the gpio interrupts edge sensitive
    
    The drivers in the kernel expect the devices using gpios
    to generate interrupts to be edge sensitive. Make it so.
    
    Change-Id: I920ef621682d33ba081f737e97f0239f903db2f7
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61678
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4361
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit f584218544e7537623f8db5ce351c384f48f7450
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jul 15 12:34:28 2013 +0800

    armv7: Remove SYS_TEXT_BASE config.
    
    SYS_TEXT_BASE is not used by any one. To prevent confusion when changing memory
    layout, remove it from current configurations.
    
    Change-Id: I15012b864bbb9c12003843b9b24ea64c91f4578b
    Reviewed-on: https://gerrit.chromium.org/gerrit/61853
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Hung-Te Lin <hungte@chromium.org>
    Tested-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/4371
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d03d69bf18b6989e9a87b30ead3283becf21885c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Dec 19 20:13:23 2013 +0100

    abuild: improve --remove
    
    Make abuild -r work in more sitations (eg. xargs parallelization),
    and make it not break junit output.
    
    Also tell Kconfig to just overwrite the config file, instead of
    atomically updating it, which help if coreboot-builds is on a
    different filesystem (eg. tmpfs).
    
    Change-Id: I2f4eedfd34ea6771732a60b38f1856056089be23
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4542
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit f422a443d7c540a4cec17f6314553d8eb23f4478
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Nov 13 21:53:23 2013 +0100

    ec/lenovo/h8: Enable 3G modem
    
    Just like bluetooth and wlan it need to be enabled in EC.
    Set the appropriate bit in EC if CMOS config says so.
    
    Change-Id: Ia48ca3201f013d3b4c4153f32ff536e06b6a2f6d
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4516
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 7d14e89c54e89901e7196e7a5da9583515576128
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 30 15:45:25 2013 -0700

    lynxpoint: Don't write to non-existent EHCI
    
    The LynxPoint-LP chipset only has one EHCI controller so we should
    not attempt to write into the second one that only exists on LynxPoint-H.
    
    Change-Id: I1eae060c7f0a5873c9684e5abfeea5cb5895ab62
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63799
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4405
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b1ae0303ce1ae3cb7f5b4f9ded32fac424be5bcb
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Dec 8 16:30:07 2013 -0600

    cpu/intel: Do not rely on CBFS microcode having a terminator
    
    Up until now, a dummy terminator was required for CBFS microcode files.
    This was a coreboot only requirement in order to terminate the loop which
    searches for updates.
    
    Figure out where the microcode file ends, and exit the loop if we pass the
    end of the CBFS without finding any updates.
    
    Change-Id: Ib61247e83ae6b67b27fcd61bd40241d4cd7bd246
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4505
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 4c37e58ea5afcda9779ac5ea410e84c168461f21
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Dec 17 13:08:01 2013 -0500

    device/dram/ddr3: Move CRC calculation in a separate function
    
    Calculating the CRC of a SPD may be useful by itself, so split that
    part of the code in a separate function.
    
    Change-Id: I6c20d3db380551865126fd890e89de6b06359207
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4537
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d7813436b325551604b13f8cefc30a6f92be4534
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Dec 7 12:19:08 2013 +0100

    X60/T60: Implement "next display output" button.
    
    Most of the code needed for this is already in the tree with X201
    patch series but code didn't know where to send the next screen
    notification and so was disabled. Define right video device.
    
    Tested by: Sam Noble
    
    Change-Id: I4ff0d220afdca342617ce43c6e5d0164ad8eba27
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4494
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit dd9945bdc7d221e58c1212092d315e1f13b66f85
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Dec 16 23:19:01 2013 +0100

    qemu/videoinit: Set required fields in fake EDID
    
    x_resolution, y_resolution and bytes_per_line were not inited. Without them
    coreboot sweared that screen is 1108630x1142817 and payload tried to draw on
    such a big screen.
    
    Change-Id: I0d0277a20c7e1976c27af4a57651ab2be0f9c5d7
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4535
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 86545f7978eac21d925f1b0ce874ca03fbd24c5c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Dec 16 06:46:00 2013 +0100

    libpayload: Add simple hexdump function
    
     - prints hex and ascii
     - detects duplicate all zero lines
    
    Change-Id: I084b3072bc05725b23c5c3ca0dbf1533f164a08c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63660
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Author:  Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/4393
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 9bf05de5ab2842fc83cea8da5e9058417fc4bc24
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Nov 14 19:11:19 2013 +0100

    lenovo/x201: Add support for Lenovo X201 (Calpella-based laptop)
    
    Was extensively tested on my X201.
    More info on the wiki
    
    Change-Id: I503d77749780422e446b48224ca98a1f22a2c180
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4514
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 2c8766891444eb49db2ec54146c7e83c0c1f8304
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Nov 13 18:31:24 2013 +0100

    ec/lenovo/h8: Fix peripheral init without CMOS config
    
    Currently H8 skips important init if unable to access CMOS config.
    Change default to enable all features to have a sane system without
    using CMOS config.
    
    Change-Id: I4448ccd21beae8ad23eb22391770c6fe3b83e3b4
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4515
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit cc2f3452e4bd191aef8436863628685f30c925ea
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Dec 7 12:03:11 2013 +0100

    intel/cougar_canyon2/Kconfig: Remove HAVE_ACPI_RESUME as S3 is unsupported
    
    According to the commit message for the board Cougar Canyon 2 (48a749a8)
    resuming from S3 is currently unsupported.
    
        The FSP does not support S3 at this time. S3 may be added
        when it is available in the FSP.
    
    Mirror that in the configuration by not selecting the Kconfig option
    `HAVE_ACPI_RESUME`.
    
    Change-Id: I894f103ffa7d8db6342f99fff0867b02bc750752
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/4519
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit ad3bd9d5f24abac6e9296dbbaa2b36f23ddfaab6
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Dec 10 01:28:04 2013 +0100

    drivers/pc80: Add ACPI description.
    
    AT controller needs an ACPI node, otherwise FreeBSD doesn't detect keyboard
    and mouse. Currently each SuperIO adds its own description. This one should
    be used in the future instead.
    
    Change-Id: Iaad5ed3846c6d9f467a02a286a1e6f60a3607af5
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4518
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 75b68d8f5b60c62060eda1761b7a10c70b9ed8a5
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Dec 12 06:53:05 2013 +0200

    cpu/amd: Remove error messages on non-matching microcode patches
    
    Microcode update file contains patches for various processor
    revisions, it is not an error to have those.
    
    Change-Id: Ifbca26276b66f17092afe249a2cfc229713a9fec
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4520
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit f95bb2d7bb6b38fba4f2c5af702e0b43da0c77ae
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Dec 13 12:30:46 2013 +0800

    crossgcc: Fix a typo.
    
    Change-Id: I8b88957a93e6369c59e9eb17f4ba48954fbc3c02
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/4526
    Tested-by: build bot (Jenkins)

commit 66e0c4c8c46eec6063a7bb8933990cc5c203ec2e
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Dec 4 22:21:15 2013 -0600

    cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS
    
    CPU_MICROCODE_IN_CBFS was designed to mean that loading microcode updates
    from a CBFS file is supported, however, the name implies that microcode is
    present in CBFS. This has recently caused confusion both with contributions
    from Google, as well as SAGE. Rename this option to
    SUPPORT_CPU_UCODE_IN_CBFS in order to make it clearer that what is meant is
    "hey, the code we have for this CPU supports loading microcode updates from
    CBFS", and prevent further confusion.
    
    Change-Id: I394555f690b5ab4cac6fbd3ddbcb740ab1138339
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4482
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Tested-by: build bot (Jenkins)

commit 580d11f1f1448a618c339d60b83b52f3bd259b8d
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri May 24 13:40:51 2013 -0500

    libpayload: expose cbfs ram functions
    
    The ram_media.c file is being compiled, however the
    global functions were not exposed through a header.
    
    Change-Id: I4588fbe320c29051566cef277bf4d20a83abf853
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56642
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4194
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4c5b161e3f0a2daa7d37bb9d77b5dba468dd3c0e
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Fri Jun 28 14:33:30 2013 -0700

    EDID: add fields specialized to the needs of framebuffers
    
    Now that we have horizontal display areas that are not multiples of 32  bytes,
    things are more complex. We add three struct members (x, y resolution and
    bytes per line) which are to be filled in by the mainboard as it sets the mode.
    
    In future, the EDID code may take a stab at initializing these but the values are
    context-dependent.
    
    Change-Id: Ib9102d6bbf8c66931f5adb1029a04b881a982cfe
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60514
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4336
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3ece50d9db35eecef557fc6ad8cc404224cfc9ac
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 24 14:57:40 2013 -0700

    bolt: Initial mainboard commit
    
    BUG=chrome-os-partner:20448
    BRANCH=none
    TEST=emerge-bolt chromeos-coreboot-bolt
    
    Change-Id: I634a755ac7659e7a977b51bcc061f69eb8263810
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59843
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4330
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0a7c49efa02b770f9f4f723633f82784be7ae6b8
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jun 20 12:40:55 2013 -0700

    HDA: Enable Mini-HDA and fix up PCH-HDA init
    
    The SystemAgent contains a mini-hd audio controller at PCI 0:3.0
    which uses the same verb table init sequence as the southbridge.
    
    In order to avoid two copies of the verb table loading code I
    separated out the HDA verb table functions into a file that can
    be re-used and then added a minihd driver to the haswell northbridge.
    
    The minihd verb table is the same across devices so it can live
    within the minihd driver rather than needing to be specified in
    each separate mainboard.
    
    I also fixed up the driver for lynxpoint HDA by following the
    reference code.
    
    Without HDMI cable plugged in driver does not find any codec,
    and it does not seem to re-probe when HDMI is connected.  We may
    be missing kernel patches for this.
    
    hda-intel 0000:00:03.0: no codecs found!
    
    With a basic kernel patch to add 0x0a0c device ID to HDA driver
    and with HDMI cable connected it is much happier:
    
    snd_hda_intel 0000:00:03.0: irq 60 for MSI/MSI-X
    input: HDA Intel MID HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input9
    snd_hda_intel 0000:00:1b.0: irq 61 for MSI/MSI-X
    input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input10
    input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input11
    
    Change-Id: Ifa587984be4fc2801704a0368b9cdf8379c2450e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59336
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4318
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4e3b345d163b1fb7a0ed309f4cf9c24d49bb48aa
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Jul 12 08:55:57 2013 -0700

    slippy/falco/peppy: make GPIO interrupts be edge triggered
    
    The drivers are designed to work with an edge triggered interrupt.
    
    Change-Id: I35a121ecfb6409bb9049f4d1e034185bb3bb7557
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61664
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4360
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6da7046f731d22202049cdc5d35e37db9f2a0540
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Jun 26 09:51:21 2013 -0700

    EXYNOS5250: be less chatty at critical moments
    
    The 5250 DRAM code is *really* chatty. That's not a great
    idea in time critical code, and DRAM init is generally
    very sensitive about such things.
    
    Finally, for those things that are errors, print them
    at an error level, not a debug level.
    
    Change-Id: Ifa86b019dfd5f8ae6c8a1da2a35b5d0808dc3623
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60100
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4359
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3641cb1d66e20f3d267a595945ec177c3715cdff
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Jul 10 09:04:47 2013 -0500

    falco: drive WLAN_DISABLE_L low in S3 and S5
    
    When the board is in S3 and S5 the WLAN_DISABLE_L signal
    can leak power into the WLAN power well since the GPIO
    controlling WLAN_DISABLE_L is in the suspend well. Therefore,
    drive WLAN_DISABLE_L low to avoid the power leak.
    
    Change-Id: I1a0df80dd47fdbd535aca7a9d49253794c480606
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61421
    Reviewed-on: http://review.coreboot.org/4358
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit c5aac958ae99bd556d077a49618e4a5daf0e65f3
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jul 8 18:41:02 2013 +0800

    exynos5250: Correct DDR3 Phy-reset value names.
    
    The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real
    phy-reset is a low-active pin, so "off(0)" will trigger "start to reset".
    
    To prevent confusion, we should rename the constants to "RESET_ENABLE" and
    "RESET_DISABLE".
    
    Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9
    Reviewed-on: https://gerrit.chromium.org/gerrit/61081
    Tested-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/4357
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 356833d0b5379de6d960b479b6a9eb7d6b971b86
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 9 15:40:27 2013 -0700

    haswell: Fix up GPU power management setup
    
    New/more magic values from latest ref code.
    
    Change-Id: Ia2655333b4daca86c2f2a76f5edcd55cdaf3f851
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61334
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4356
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 118d105a375618a8ee8309cd9dcdc17ea6d31f30
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 9 15:34:25 2013 -0700

    haswell: Export functions for CPU family+model and stepping
    
    These are needed to enable workarounds/features on specific
    CPU types and stepping.  The older northbridge function and
    defines from sandybridge/ivybridge are removed.
    
    Change-Id: I80370f53590a5caa914ec8cf0095c3177a8b5c89
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61333
    Commit-Queue: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4355
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f6d6e62aaf76ba4bef5e0dcdfc73975c25f5337b
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jul 3 19:07:21 2013 +0800

    exynos5420: Setup clocks for MMC bus controller.
    
    To configure source clocks on Exynos 5420 for MMC drivers.
    Some registers are different from the 5250. FSYS now has two parts
    and MMC uses FSYS2. The MMC block uses MPLL as the clock source.
    The "high-speed" MMC interface runs as 52MHz, so divider is set
    accordingly.
    
    Also, the MMC driver has changed from MSHCI (Mobile Storage Host Controller
    Interface) to DWMCI (DesignWare MMC Controller Interface).
    
    Change-Id: I9ba9cf43e2f2dcd9da747888c0c7676bd545177b
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60858
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4354
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 865912cec083afba64f9ada0a438da8a10daea78
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Mon Jul 8 14:26:35 2013 -0700

    peppy: Add backward-compatible RAM_ID table.
    
    Make use of google_chromeec_get_board_version to determine board
    version, and apply proper RAM_ID table to load correct SPD.
    
    Change-Id: I6a2d54759cf2ce98bf53df0db396c6e09368c714
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61192
    Reviewed-by: Dave Parker <dparker@chromium.org>
    Reviewed-on: http://review.coreboot.org/4353
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit aa1b10617d3a06c37e8294aa45dbb8bea5857651
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jun 13 14:24:35 2013 +0800

    Peppy: Update Realtek ALC283 verb table
    
    Update peppy's verb tables for the Realtek ALC283 Audio Codec.
    
    ALC283 Configuration:
    Digital Mic - NID 12h: Disabled
    Speakers    - NID 14h: Enabled
    Mono out    - NID 17h: Disabled
    Mic 1       - NID 18h: Disabled
    Mic 2       - NID 19h: Headphone Jack
    Line1       - NID 1Ah: Internal Mic
    Line2       - NID 1Bh: Disabled
    PCBEEP      - NID 1Dh: Enabled
    SPDIF       - NID 1Eh: Disabled
    HP-OUT      - NID 21h: Headphone Jack
    
    Mic 1 doesn't seem to really be available, but the documentation
    refers to NID 18h as MIC1, so it's being disabled as it's not
    being used.  The onboard microphone has been moved to line 1.
    
    I had my peppy modified to attach the mic to line1 and mic1 now
    works with this patch.  Mic2 looks harder to rework, so I think
    that will have to wait for the DVT boards.
    
    Change-Id: I7d6ce6b428806b6aed1d36e7e25302fa5ae14b21
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/58880
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4352
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit d0a6a38bb7902324f87fd3111b48ba30d1817cb6
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Mon Jul 8 14:18:01 2013 -0700

    chromeec: Allow get_board_version to be called from romstage.
    
    We will soon need to call google_chromeec_get_board_version to determine
    correct DDR SPD. We must do so before DDR is initialized, so allow this
    function to be called from romstage.
    
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    
    Change-Id: I882d84e38d11bf66067193a6f408f941f2cf8a81
    Reviewed-on: https://gerrit.chromium.org/gerrit/61191
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4351
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a367892c98a8ae84470a28ab2d9e4dd8a09596b4
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 9 11:08:52 2013 -0700

    falco: fix usb port settings
    
    USB2 Port A set to 6.4" and Back Panel
    USB2 Port B set to 5.2" and Back Panel
    USB2 Port C set to 12.3" and Internal
    
    Other devices all set to Internal.
    
    build and boot on falco and check settings.
    
    Based on the config settings all ports end up with
    tuning param 1 == 5 and param 2 == 2
    
    U2ECR[0] = 0x00059501
    U2ECR[1] = 0x00059501
    U2ECR[2] = 0x00059501
    U2ECR[3] = 0x00059501
    U2ECR[4] = 0x00059501
    U2ECR[5] = 0x00059501
    U2ECR[6] = 0x00059501
    U2ECR[7] = 0x00059e01
    
    Change-Id: I6b9e6df2679036a501355e6b389a486a6f178f99
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61297
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4350
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 7ed39767048c535217bb741e1d0f0f365f598f10
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 9 10:46:52 2013 -0700

    Log device path during resource allocation
    
    Systems are hanging in dev_configure() without a log to
    indicate which device is being processed.  Add some logging
    points to save the device path before talking to the device
    so we can narrow in on which device is the problem.
    
    Change-Id: I3751c19a1ea68cdccbc33e4f6b2eeddd1bd9f2e4
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61296
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4349
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 768903eac919f66362354f8141ca9a37b8ceb79f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 1 08:59:43 2013 -0700

    haswell: Update ULT microcode to rev 14h
    
    localhost ~ # grep ^microcode /proc/cpuinfo
    microcode       : 0x14
    microcode       : 0x14
    
    Change-Id: I839f29cff61abf798a619b30ad945e25c79f548f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60658
    Reviewed-on: http://review.coreboot.org/4348
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 46cbcf6354ebfbe921a8160fbe0eba7029605beb
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 1 08:50:16 2013 -0700

    falco: Remove thermal thresholds that use CTDP
    
    This CPU does not support Configurable TDP and so far does
    not need to use Controllable TDP.
    
    Change-Id: I15599cd4e6890dd5c9d9f99bc4e95307a8dcc827
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60657
    Reviewed-on: http://review.coreboot.org/4347
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c083d2e3470222a6a4130a322d133f7404a06bc6
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Jul 6 22:11:19 2013 -0700

    libpayload: Get rid of a compiler warning
    
    Change-Id: I7252925ef5c4efb69cad6b6fa179031162cf8e74
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61058
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4346
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cb0aeef0a9ef58049a093eb42b8c7f06c9e1b271
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jul 8 12:27:13 2013 +0800

    libpayload: armv7: Add cache control function to invalidate range.
    
    When dealing with DMA, we need a function to invalidate cache without corrupting
    contents on main memory (clean).
    
    Change-Id: I28e632ae57a7b7ed1accee74e76045b92f92a699
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61078
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4345
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d0fa1d1a616ce4fd08ca2348700b6e0201761da3
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jul 8 12:25:34 2013 +0800

    payload: armv7: Fix dcache_clean_by_mva.
    
    The OP assigned by dcache_clean_by_mva must be handled in
    dcache_op_mva.
    
    Change-Id: Ib32262f0419453b2690d7c1a1c6602380b46a37f
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61077
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4344
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 86148a6219887fe22acc414c37db8f15bfd403ed
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jul 8 12:17:25 2013 +0800

    armv7: Fix dcache_clean_by_mva.
    
    The OP assigned by dcache_clean_by_mva must be handled in dcache_op_mva.
    
    Change-Id: Ia7631a08be6afacb13dfff406ac4db20efc98926
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61076
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4343
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c55131cdbf2481b4e580dc3859dc682844617a42
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Jun 26 10:29:02 2013 -0700

    PIT: remove a comment that is incorrect.
    
    The is_resume comment is wrong for this board. It only applies
    to the older 5250 cpu. In fact, the is_resume parameter
    is not needed for ddr init and will likely be removed soon.
    
    Change-Id: I4e3c92fcaaa75d3c9223d90acccf053f61406307
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60103
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4342
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dcaaba44b62ebec7fa3d490f5dbf35931360cfa1
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jul 7 04:05:51 2013 -0700

    snow: Fix the edid data structure definition so depthcharge works again.
    
    Some new fields were added to the edid data structure, and the edid code was
    changed to put estimated values into those fields which were ultimately passed
    into depthcharge or other payloads. On snow we do things different and just
    declare an edid structure statically which didn't have those members. The rows
    and columns of the graphics console were 0, and that confused the framebuffer
    driver and made it loop forever.
    
    Change-Id: I6ca3bd948482b347a6a981e83b82b10dca995e5e
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61057
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4341
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d6ff9e7deb0680b7d54958377834bc3c7606ba0c
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Wed Jun 26 18:11:23 2013 -0700

    peppy: RAM_ID + storage changes for next build.
    
    - Update RAM_ID table.
    - Add DEVSLP0 signal to NGFF SATA port.
    
    Note: After this change, old Micron 2GB boards will no longer boot.
    
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    
    Change-Id: Id68a1d6ace2702cca9c37305726cd55a0bde5005
    Reviewed-on: https://gerrit.chromium.org/gerrit/60167
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-by: Dave Parker <dparker@chromium.org>
    Commit-Queue: Dave Parker <dparker@chromium.org>
    Reviewed-on: http://review.coreboot.org/4340
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ccb12fbb58c13af46e2275fd50cd8b171fdd169a
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Wed Jul 3 17:55:38 2013 -0700

    peppy: Disable audio codec enable GPIO in S3 + S5.
    
    To save power, disable audio codec in S3 + S5.
    
    Also, refactor Lynxpoint GPIO code slightly to allow usage in SMM
    binary.
    
    Change-Id: I55c4248c89a258b5e4cecf8579eb58f1c15430c0
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60950
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4339
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 041dae191409ef715e0100a5c63bff7f7feb2aaa
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Dec 7 10:40:19 2013 +0100

    board-status: extend wiki foreword
    
    Change-Id: I9791beff44535a0a130292414fcd9875b497b1ca
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4492
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f0a13ceb639f7a7d5a6e84a2c89f3deab0de757a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Dec 8 07:20:48 2013 +0200

    AMD boards: Fix includes for microcode updates
    
    No ROMCC involved, no need to include .c files in romstage.c.
    
    Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4501
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 299c26510202faa3cf7383040f330d502d224fdf
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Dec 8 01:13:43 2013 -0600

    Refactor usage of walkcbfs to permit access to CBFS headers
    
    walkcbfs() is used only with ROMCC. Besides finding stages during the
    bootblock, it's also used when applying microcode updates during the
    bootblock phase. The function used to return only a pointer to the data of
    the CBFS file, while making the header completely inaccessible. Since the
    header contains the length of the CBFS file, the caller did not have a way
    to know how long the data was. Then, other conventions had to be used to
    determine the EOF, which might present problems if the user replaces the
    CBFS file. This is not an issue when jumping to a stage (romstage), but can
    present problems when accessing a microcode file which has not been
    NULL-terminated.
    
    Refactor walkcbfs_asm to return a pointer to the CBFS file header rather
    than the data. Rename walkcbfs() to walkcbfs_head(), and reimplement a new
    walkcbfs() based on walkcbfs_head(). Thus current usage of walkcbfs()
    remains unaffected.
    The code has been verified to run successfully under qemu.
    
    Subsequent patches will change usage of walkcbfs() to walkcbfs_head where
    knowing the length of the data is needed.
    
    Change-Id: I21cbf19e130e1480e2749754e5d5130d36036f8e
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4504
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f87c20a00dca412ad8fa255ef38fd954762afa4b
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Dec 8 17:46:40 2013 -0600

    cbfstool: Properly handle EOF in update_fit step
    
    During the update_fit step, 'file_length' is used to determine how many
    bytes are left in the CBFS file. It was decremented in a loop from an
    array 'mcus[num_mcus].size', but 'num_mcus' was incremented right before.
    Since 'mcus' is memset(0) externally, 'file_length' was never decremented.
    
    The loop exited when it reached a dummy terminator, usually 48 bytes of 0
    which are internationally added to microcode blobs in coreboot. However,
    if that terminator is removed, the loop doesn't stop and continues until
    it segfaults.
    
    Change-Id: I840727add69379ffef75b694d90402ed89769e3b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4508
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 691b313c2807a5e9d293e9a520f951ea1319bb8f
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Dec 9 14:09:07 2013 +0800

    crossgcc: Continue to unpack archive if it was incomplete
    
    If the unpacking was interrupt by Ctrl-C, probably part of
    an archive is unpacked. If we run buildgcc again, the
    incomplete folder would be and skipped.
    
    We can create a file to tell the script the unpacking is done.
    
    Change-Id: Id9eb74d119e22b62c70dca9b38a92c3dbdf0f64c
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/4512
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 19803e7cb04b6b411f3c8e58c69cbf12c7fc07b9
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Dec 9 14:11:04 2013 +0800

    gitignore: ignore the crossgcc/build-{arch}-{archive}
    
    The architecture information has been added to the folders to
    build archives for crossgcc. We need to change the .gitignore
    to keep ignoring them.
    
    Change-Id: Ic18685e507f1b09088120eee6047d49141e29906
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/4513
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7afd2bbf84635519ded76b49ab5779be5ad439dc
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Dec 9 10:27:56 2013 +0800

    documentation: Change the file name of document for building Coreboot
    
    I am planning to write a document for new man, helping them to build a
    working image from knowing nothing about Coreboot. The previous
    LinuxBIOS-AMD64.tex was a good script.
    
    LinuxBIOS was a out-of-date name. It needs to be changed it to Coreboot.
    And the new document is not specific to AMD, so we get rid of the AMD64 from
    the file name.
    
    This is a separate patch for the renaming.
    
    LinuxBIOS-AMD64.tex was still about SVN and buildtarget. Later patch
    will come up for updating those old thing. And this new document,
    CorebootBuildingGuide.tex, is planning to be only about building.
    Navigating the source code is moved to later advanced document.
    
    Change-Id: Ia8a2fd9db51e9870c1d645067bcfdc91ae1bf90a
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/4487
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4eb4a1f6bea1307badd174d4729281fb0516ad41
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Dec 7 20:10:41 2013 +0100

    board-status: update foreword
    
    Change-Id: I6acafee948b1224b88fd640e02c18168c1f90e39
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4496
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 87932c027ea41685ae8304c2ed406a47bbebe584
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Dec 7 10:44:52 2013 +0100

    board-status: one-line reports, with links to per-board pages
    
    Make boards take less vertical space, and link to board pages
    
    Change-Id: Ifdd062a15191809b75422416c874161d9114363d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4493
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 2267658db44f7ffade5fd15cd1b8a4019a380f7e
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 26 21:48:57 2013 +0100

    snprintf: lockless operation
    
    Instead of having global variables put them on the stack.
    
    Change-Id: I462e3b245612ff2dfb077da1cbcc5ac88f8b8e48
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4288
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit f421b33edb78890f8721de49c1dd1e086f1d25fc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 26 21:43:05 2013 +0100

    vtxprintf: Introduce vtxdprintf for the ease of closures
    
    It was suggested to eliminate the lock for sprintf. One way to do it is
    to make the fake tx_byte into a closure. This patch allows it.
    
    It's a bit tricky since we need to preserve compatibility with romcc.
    
    Change-Id: I877ef0cef54dcbb0589fe858c485f76f3dd27ece
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4287
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7f68dfd6e8d90516a25d0b7523387ea1b8704355
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Dec 7 10:38:42 2013 +0100

    board-status: document the wiki scripts
    
    These were terribly under-documented
    
    Change-Id: I285ea083110d87076281e81065f5f38d0c688358
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4491
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 16cbf8983c2481a31357f25c44a09b670edcf870
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Jul 3 16:21:28 2013 -0500

    haswell: VR controller configuration
    
    Configure the VR controller. This enables the PSIx levels
    as well as C-state ramping. PSIx thresholds are:
     - PSI3: 1A.
     - PSI2: 5A.
     - PSI1: 15A.
    
    Before:
    0x601 0x0000000000000100
    0x603 0x0036000000262626
    0x636 0x000000000000006f
    After:
    0x601 0x4010140f00000100
    0x603 0x0036000000262626
    0x636 0x000000000000006f
    
    Change-Id: I6958845ac4164ebd0f1bb2d6d9be55ba63ed9344
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60931
    Reviewed-by: Sameer Nanda <snanda@chromium.org>
    Reviewed-on: http://review.coreboot.org/4338
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 01ab2d14be086bd6fda82eaad000a34e6abb9047
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Sun Jun 30 20:30:58 2013 -0700

    Add kernel-derived support functions for DDI.
    
    Newer mainboards that use haswell -- and, presumably, chipsets to come -- need
    some support functions. Add them in the drivers/intel/gma directory.
    Currently, this is one file: intel_ddi.c, but more may come.
    
    Compilation of this file is controlled by INTEL_DDI, defined
    in the Kconfig as default n and used in the Makefile.inc
    
    Change-Id: I501ee291c0d4589925ed3e478f67106337fcad31
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60612
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4337
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 6f0e160459aa7d1de34da85978df5f3282c973ce
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Dec 5 19:36:31 2013 +0100

    abuild: drop xml mode
    
    We use junit style output these days.
    
    Change-Id: I4110ec10bf0e9f4354ee08e7e1c5a81ae605fee0
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4484
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit b17117904d1c233bc0798022f17b4ef38393fffc
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Jun 28 16:01:53 2013 -0700

    haswell: Add ACPI support for Controllable TDP
    
    Add ACPI Methods to enable and disable power limiting with PL1.
    This can be used in ACPI Thermal Zone or in EC ACPI _QXX events.
    
    This commit adds new unused methods and is fully tested with the
    subsequent commit that makes use of these methods.
    
    Change-Id: I9d8d23bfe9cf7c756ff8ab0412e5a010826b12db
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60546
    Reviewed-on: http://review.coreboot.org/4334
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit c70353f1eb26b9239ba7704111c9b471463ce42e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Jun 28 14:40:38 2013 -0700

    haswell: Misc power management setup and fixes
    
    1) fix enable of power aware interrupt routing
    2) set BIOS_RESET_CPL to 3 instead of 1
    3) mirror PKG power limit values from MSR to MMIO on all SKUs
    4) mirror DDR power limit values from MMIO to MSR
    5) remove DMI settings that were from snb/ivb as they do
    not apply to haswell
    
    1) verify power aware interrupt routing is working by looking
    in /proc/interrupts to see interrupts routed to both cores
    instead of always to core0
    
    BEFORE: 58:       4943          0   PCI-MSI-edge      ahci
    AFTER:  58:       4766        334   PCI-MSI-edge      ahci
    
    2) read back BIOS_RESET_CPL to verify it is == 3
    
    localhost ~ # iotools mmio_read32 0xfed15da8
    0x00000003
    
    3) read PKG power limit from MMIO and verify it is the same
    as the MSR value
    
    localhost ~ # rdmsr 0 0x610
    0x0000809600dc8078
    localhost ~ # iotools mmio_read32 0xfed159a0
    0x00dc8078
    localhost ~ # iotools mmio_read32 0xfed159a4
    0x00008096
    
    4) read DDR power limit from MSR and verify it is the same
    as the MMIO value (note this is zero based on current MRC input)
    
    localhost ~ # rdmsr 0 0x618
    0x0000000000000000
    localhost ~ # iotools mmio_read32 0xfed158e0
    0x00000000
    localhost ~ # iotools mmio_read32 0xfed158e4
    0x00000000
    
    Change-Id: I6cc4c5b2a81304e9deaad8cffcaf604ebad60b29
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60544
    Reviewed-on: http://review.coreboot.org/4333
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit ddf68901f7640aa3789e2c04159804142ca26812
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Jun 28 15:59:19 2013 -0700

    peppy: Enable power limiting for thermal control
    
    Limit power to 12W at 73C and remove limit at 68C.
    
    To have the CPU consume maximum power it is necessary to stress
    both the CPU and the GPU.  Bastion (chrome.supergiantgames.com)
    and/or webglsamples.googlecode.com can be useful for this.
    
    Testing this properly requires a script to report the running
    average power readings.  The watch_power.sh script is attached
    to this issue in the partner tracker.
    
    1) Run watch_power.sh continuously:
    localhost ~ # watch -n 0 bash -e /tmp/watch_power.sh
    2) Start Bastion (or other stress apps).  The power draw should
    be close to 15W if under enough load.
    3) Watch until temperature climbs above 73C and is caught by
    the thermal zone 10 second poll, this can be sped up by blocking
    or removing the fan.
    4) The ACPI thermal zone states should change to reflect that
    active[2] is now enabled and power consumption should drop to 12W.
    5) Stop the stress apps and wait until the CPU cools off again,
    enable the fan again if it was removed.
    6) The ACPI thermal zone state should switch back to active[3].
    
    Change-Id: Ie6714a8543d4f06edf8513086fc9c968273bdb23
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60545
    Reviewed-on: http://review.coreboot.org/4335
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 10a070b447c2b847352b3fc9b8e23cb51a080309
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Jun 28 12:30:53 2013 -0700

    elog: handle ROM_SIZE differences from detected flash size
    
    The elog code calculates flash offsets and their equivalent
    addresses in the memory address space. However, it assumes
    the detected flash size is entirely mapped into the address
    space. This can lead to incorrect calculations. Add code
    to allow ROM_SIZE to be less than detected flash size. The
    underlying assumption is that the first ROM_SIZE bytes are
    programmed into the larger device.
    
    Change-Id: Id848f136515289b40594b7d3762e26e3e55da62f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60501
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4332
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 8c0cb8ae3b3945a1f61a8eab3b9f41af9a0bb10b
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Fri Dec 6 22:02:47 2013 +0000

    Correct file permissions.
    
    Some files have incorrect/odd permissions,
    correct them: remove unnecessary +x flags.
    
    Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/4490
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit 6e6d719d827403af1504584b1b4281f8dbdbf2b4
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Fri Dec 6 21:48:38 2013 +0000

    src/vendorcode/amd: remove Visual Studio remnants.
    
    Delete files that (were overlooked and) are probably needed to
    build with Visual Studio.
    Remove doxygen helper files as well.
    
    Change-Id: I6b6cece178917ad9da1081eb6b1bb9be33066a77
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/4489
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit a406119e9b6908a59eed4d1d9cba417642b13e73
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Dec 4 21:57:15 2013 -0600

    arch/x86: Do not run UPDATE-FIT if we don't include microcode
    
    The original intention was to only run UPDATE_FIT when a microcode file was
    included in CBFS. This happens when either CPU_MICROCODE_CBFS_GENERATE or
    CPU_MICROCODE_CBFS_EXTERNAL is selected, however, the makefile checked that
    CPU_MICROCODE_IN_CBFS was selected instead. The end result was that on
    hasswell, the UPDATE-FIT step was always run, even when no microcode was
    included, generating a build error.
    
    Instead, introduce a new variable which tells if a microcode update is
    added in CBFS during the build.
    
    Change-Id: I28638912ed6f77761ef8a584f7636dc907b7a9b7
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4480
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 8232bc2cdd47666a51cd3bc5beea608f13b8e9fa
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Sep 24 21:04:12 2013 +0300

    usbdebug: Hide irrelevent options from menuconfig
    
    No need to show the choice of USB port or controller in case of older
    hardware where location for usbdebug was hardwired.
    
    Change-Id: Ia186bf2c6ed60be2834cf6fd0a1965c8bf81ed4d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4290
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit fab0c9f35db584ed0fb597fa99719a965e2fbd9a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Nov 28 18:10:03 2013 +0200

    butterfly: Fix build without ChromeOS
    
    Use a file in CBFS for keyboard layout and ethernet MAC instead
    of scanning FMAP.
    
    Change-Id: I7658c7c4e389deb20d7d8f57cce8b568efdc575d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4307
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit e4c657c4afe968c86efe30766a1d14a29c782093
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Dec 3 18:22:44 2013 +0100

    Do not export variables to GRUB build
    
    Variables in coreboot and not in line with GRUB ones. E.g. HOSTCC is both
    HOST_CC and BUILD_CC for GRUB (consult INSTALL for more details) and
    what coreboot calls CC is TARGET_CC for GRUB.
    
    Current code plugs this by defining variables explicitly but it has a nasty
    effect that make stops caring about flags added in makefile itself. Undef
    as many variables as possible but still pass them to configure for them to
    have correct effect and keep CC assignment as my make version doesn't undefine
    it even when instructed to do so.
    
    Tested with qemu.
    
    Change-Id: I9d18f557138a20ae3918d698dee8f5b5c5738f75
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4310
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 590e8d45581730a210eb32d58a87305ea6edb706
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Tue Dec 3 09:40:39 2013 +0100

    qemu: fix GENERATE_ACPI_TABLES=n in fw_cfg.c
    
    Change-Id: Ib8dc069c9e503747c349e96a466feb42279afd08
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/4305
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4623b20e5a14e5d4b0fa040807f7ecc02051204b
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Fri Jun 28 09:21:16 2013 -0700

    Add in the Makefile bits for the new intel gma driver
    
    The Intel GMA driver is in, this CL splices in the Makefile bits.
    
    Change-Id: Icf42a537575b8cc90a679ec1fc15b09294630611
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60346
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4331
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 589555109c95914d5162978c83ae93ba8c9f5a0e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Dec 5 19:53:04 2013 +0100

    abuild: fix and enable USE_XARGS configuration
    
    USE_XARGS mode builds n boards in parallel (with 1 CPU each) instead of
    building 1 board with n CPUs.
    This requires the main build system to work under such circumstances.
    
    Change-Id: Ib4571a78dfe78fd61ae5b26c18be9745bd8b3d52
    Reviewed-on: http://review.coreboot.org/4485
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d935f039382a32cd49722235d4186db652f1b56b
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Dec 5 20:17:36 2013 +0100

    sconfig: avoid regenerating the binary all the time
    
    This makes USE_XARGS-abuild unhappy due to races
    
    Change-Id: I1237468366c7f8af7eacd572c2bd32df9a3d58ca
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4486
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 99451b174a841f62b0e5fbbf157ba9161f3a661b
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Thu Jun 27 10:42:59 2013 -0700

    FUI: add intel_dp driver derived from kernel functions
    
    These functions are not all used yet, but do compile and are partially used
    in the FUI testing.
    
    They were extracted from the 3.4 kernel using coccinnelle filters. The .c files
    are only compiled in if CONFIG_INTEL_DP is set.
    
    Change-Id: Id95622a75aa02b496c9ea4717cb143394a8332e3
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/60245
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4329
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5bcca7e98215d95190274f14d34284f16a6fe194
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Jun 25 15:56:46 2013 -0700

    haswell: pull in the init code for FUI
    
    Removed two unnecessary register sets, and did the power well a bit
    more correctly. Also, added a register definition include file so we can
    used constants instead of magic numbers.
    
    We also set registers to common initialized values that are
    needed for FUI, VBIOS, and kernel. This set of registers
    appears to be an absolute bare minimum. Since we're hoping to use
    FUI for all chipsets from this one forward, we unconditionally do the
    setting here.
    
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    
    Change-Id: Ife3f661ba010214d92b646b336f2b06645119f17
    Reviewed-on: https://gerrit.chromium.org/gerrit/59988
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4328
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7982de165e87c59df98f8334afc1728e7cc90e7f
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Jun 5 08:35:52 2013 -0700

    google/link: use the new edid functions when in FUI mode
    
    The new edid functions support converting the edid to an lb_framebuffer.
    Use them. Also, since panels seem to set bits per color instead of bits
    per pixel, just force the right value in the edid struct.
    
    Add helpful comment because people don't always believe we need to set
    the pallette.
    
    While we're at it, fix a problem that caused it to not compile.
    
    Change-Id: I645edc4e442d9b96303d9e17f175458dc7ef28b6
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57619
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
    Tested-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/4327
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4bc107bc02529cb1c9288435de2f2e86497f76b3
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 24 13:14:44 2013 -0700

    lynxpoint: Update LPT-LP PM settings
    
    - updates from 1.6.0 ref code
    - remove the step comments as they are no longer even close
    - add constants for LPT revisions
    
    build and boot on Falco
    
    Check that RCBA+2300[1] is set:
    > mmio_read32 0xfed1e300
    0x00000002
    
    Change-Id: I8b3c5fda3f3170455699a7834239cb991603e7a8
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59821
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4326
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1c4289dfd537d1d46319f016a27c004098dbae97
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Jun 21 14:06:11 2013 -0500

    lynxpoint: enable clock gating
    
    Implement the LynxPoint BIOS Spec for clock gating.
    
    Change-Id: Iaa84cb447bd29b0d13cdda481a1661ea40499de1
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59590
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4325
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 550bcca6021f475d4ad7dd2c73d6bc4b5a93f94a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Jun 21 13:37:23 2013 -0500

    lynxpoint: provide gpio_is_native()
    
    There's a need to determine if a specific gpio pin is
    is set up to be a native function or not. Implement this.
    
    Change-Id: I91d57a549e0f4fddc0b1849e5f74320fc839642c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59589
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4324
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ab365af0a05e391d1e20e39e8bfb61c023b0a678
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 3 12:13:26 2013 -0800

    lynxpoint: implement additional programming steps
    
    The BIOS spec for LynxPoint calls out additional
    programming steps for the PCIe Root Ports. Implement those
    steps from the BIOS spec. These steps are completed before
    deeper PCIe probing. The "late" programming was removed as
    that was applicable to Cougar/Panther point where this
    code was originally copied, though there was some overlap.
    
    Change-Id: I64f25e4451e035d98ca6b66b0335bd280b70b074
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59558
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4323
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c0254e6b6fbe7268fa47b2d4bd0a203423b2eec2
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jun 20 01:20:30 2013 -0500

    lynxpoint: disable pcie devices based on config
    
    PCIe Root Ports should be disabled based on pin ownership
    and the strapping configuration. Implement this logic
    for LynxPoint. The chip_ops->enable_dev() path is no
    longer used. Instead the PCIe driver handles the enabling
    and disabling of devices. This allows for having an empty
    or incomplete device tree since those "allocated" devices
    do not travel through the chip_ops->enable_dev() path.
    The coalescing was tested to be working properly, however
    not all configurations were tested.
    
    Change-Id: I1e8bfe5e447b72ff8a4b04b650982d8c1ae0823c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59424
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4322
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6e764ff1f1919f64cc76e699d875d50c8c22759c
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Thu Jun 20 15:26:57 2013 -0700

    peppy: Disable forced dev mode.
    
    Don't force dev mode. Allow users to enter / exit dev mode as normal.
    
    Change-Id: I168eb04a8ac102a8c4a1ca8936f78f62b001e0eb
    Reviewed-on: https://gerrit.chromium.org/gerrit/59492
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-by: Dave Parker <dparker@chromium.org>
    Reviewed-on: http://review.coreboot.org/4321
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b86062959b8fbd0276f3455539badd86ac0ae867
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 21 12:43:09 2013 -0700

    libpayload: Have similar cache api on ARM and x86
    
    So far this is used by the USB driver, and instead of
    having ifdefs all throughout that code, implement the same
    API on x86 and ARM.
    
    Change-Id: I8093ad818ad2e38a0901787aa8674faf591d580c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56105
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4320
    Tested-by: build bot (Jenkins)

commit 414cd436c9f0f9606778890e1cbc88131732f3d2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jun 20 14:53:35 2013 -0700

    Fix Makefile to include all copies of the SPD sources
    
    On some systems there may be 2GB SKU that is the same as the
    4GB SKU but just one channel of memory.  In that case we need
    to ensure that both copies of the same SPD source end up
    populated by ensuring that repeated entries are included by
    using $+ instead of $^.
    
    Alternatively we could do the check inside romstage, but it
    is already set to behave this way if the SPD gets populated
    correctly.
    
    I changed spd_index to 3 in falco romstage to force it to
    pretend it was a 2GB config of the same memory, then booted
    to ensure it was indeed limited to 2GB.
    
    memcfg channel[0] config (00780008):
       ECC inactive
       enhanced interleave mode on
       rank interleave on
       DIMMA 2048 MB width x16 single rank, selected
       DIMMB 0 MB width x16 single rank
    memcfg channel[1] config (00600000):
       ECC inactive
       enhanced interleave mode on
       rank interleave on
       DIMMA 0 MB width x8 single rank, selected
       DIMMB 0 MB width x8 single rank
    
    Change-Id: Ibfe5051ccda2fe69e8caff3f3c264116e3411c65
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59483
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Tested-by: Jay Kim <yongjaek@chromium.org>
    Reviewed-on: http://review.coreboot.org/4319
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0db924d74cfec0e85ed4f9a01e519888d9f309b3
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Aug 9 11:06:11 2013 -0700

    cbmem: print timestamp names
    
    The numbers alone are hard to parse, so add
    some timestamp names to make it easier to read.
    
    Change-Id: Ie32d3e7ca759bd15e7c160bdd829dec19943e6cb
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65333
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4314
    Tested-by: build bot (Jenkins)

commit d8ef9e9e9b8f7e4685fc1cbad0b1f6d82799712c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jul 31 15:44:37 2013 -0700

    Fix timestamp output in cbmem utility on ARM
    
    On ARM the timestamps are already in micro seconds, so
    no need to convert them.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: If7363b0703e144bde62d9dab4ba845e1ace5bd18
    Reviewed-on: https://gerrit.chromium.org/gerrit/63991
    Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4313
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 274c6c2177979ba471f61f03d2ea76df673ff925
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Dec 5 18:11:33 2013 +0100

    Add scripts to export board status data to wiki
    
    It's a start...
    
    Change-Id: Ibdb0b64ab0349df58bcad5ce553bf0dbec636925
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4483
    Tested-by: build bot (Jenkins)

commit 08c4150ec4f9fde303205802d646f96a54fd5a59
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 21 14:45:28 2013 -0700

    libpayload: Clean up CFLAGS
    
    - Add -ffreestanding and -fomit-frame-pointer for all
      platforms.
    - Add ARMv7 specific flags to the armv7 Makefile
    
    Change-Id: I71ab1b096e505940cc20c266bccd43917bcfad3a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56104
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4317
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1defc861d064ab9fbad68e33824b2fc9af8f240e
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Thu Nov 21 16:12:27 2013 +0800

    AMD Kabini: fix issue 'S3 fails to suspend after wake up from USB keyboard'
    
    Propagated from
    http://review.coreboot.org/3347
    http://review.coreboot.org/3374
    
    The cause of this issue is:
    USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event,
    but this bit is not clear after wake up. So OS thinks there is a
    wake up signal and wake up immediately.
    
    Both amd/olivehill and asrock/imb-a180 have been validated.
    
    Change-Id: I7c26cb07bcd2e62bb792809b67314e5155c6adf6
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/4261
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit ddf58ef844e06f338f40397d42f07657f021949f
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Thu Nov 21 16:11:40 2013 +0800

    AMD Kabini: Add ACPI sleep/wakeup calls for southbridge
    
    The AML code of PTS and WAK for southbridge are in
    UINT8  AlibSsdtKB[], Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h.
    It was integrated into SSDT even it was called by nobody.
    The source ASL was provided by AGESA for reference, but it
    has been scrubbed when it was ported to Coreboot.
    
    Without the calls, Olive Hill can not wake up if it boots Windows.
    Both amd/olivehill and asrock/imb-a180 have been validated.
    
    Change-Id: Ia7bba29904dbd6f33fdb08bf88bb499005ef561b
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/4260
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit abd119d28fae43a98b75824c974519bec9100299
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Wed Dec 4 10:22:25 2013 +0800

    AMD IMC AGESA: Access the data in stack by correct length
    
    The bug is hard to find. We were adding the feature of fan control. We
    met some strange things which could not be explained. Like, sometimes
    adding printk let the error disappear. Then we traced the code by hardware
    debug tool (HDT). It turned out the data in stack was overwritten.
    
    The values of AccessWidthxx are
    { AccessWidth8 = 1,
      AccessWidth16,
      AccessWidth32,}
    For the case of AccessWidth8, we only need to access the index/data
    once. But ReadECmsg and WriteECmsg did the loop twice, 1 more time
    than they are supposed to do. The data in stack next to "Value" would
    be overwritten.
    
    For all the cases, the code should be
     OpFlag = OpFlag & 0x7f;
     switch (OpFlag) {
        case 1:              /* AccessWidth8 */
             OpFlag = 0;break;
        case 2:              /* AccessWidth16 */
             OpFlag = 1;break;
        case 3:              /* AccessWidth32 */
             OpFlag = 3;break;
        case 4:              /* AccessWidth64 */
             OpFlag = 7;break;
        default:
             error;
     }
    
    Actually, the caller only takes AccessWidth8 as the parameter. We can ignore other
    cases for now.
    
    That is an AGESA bug. AMD's AGESA team own this code. They have given the
    response that they are going to update this in next release. I presume let them
    decide the proper way to fix that. Before that, I change the code as little
    as possible to make it run without crash.
    
    Change-Id: I566f74c242ce93f4569eedf69ca07d2fb7fb368d
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/4297
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit f589909b91e30cb826b18cf7a46299649edc53d6
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Dec 4 16:57:52 2013 -0600

    cpu: Remove BOARD_MICROCODE_CBFS_GENERATE Kconfig option
    
    Commit * bdafcfa Add the Intel FSP 206ax CPU core support
    Introduced this option. This option was meant to have a board generate
    a CBFS file containing microcode. However, microcode generation used to be
    enabled by default when CPU_MICROCODE_IN_CBFS was selected.
    
    The introduction of BOARD_MICROCODE_CBFS_GENERATE killed that automatic
    default, which is not what we want. This option is misguided in the sense
    that it tends to introduce a non-default which had been intentionally a
    default. We now have to select two Kconfig options in order to generate
    microcode in CBFS, meaning one option is redundant.
    
    Change-Id: I3034833df1a9afa7d6d9d537484cb4ac89d30183
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4478
    Tested-by: build bot (Jenkins)

commit 55fa7f5c5f3f57779b3ba08ad6b33ddfb93bdd4d
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Dec 4 19:32:23 2013 -0600

    intel/fsp_bd82x6x: Use correct type pointer for mainboard_smi_gpi
    
    mainboard_smi_gpi has recently been updated to take a u32 argument from a
    u16, but the patch introducing the fsp_bd82x6x support has been verified
    on a master before this change, thus resulting in a 'cast from incompatible
    type' error. Update the pointer to the correct size argument.
    
    Change-Id: I9d62ee43f7c8ed774898f54d29a87cf463b76e91
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4479
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 6a7dd08b1666758de339ff8096d542a3f4499053
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 19 12:39:52 2013 -0700

    libpayload: sync ARMv7 arch/io.h with coreboot
    
    On ARMv7 we need to carefully add memory barriers to
    all memory read and write operations. This change
    brings libpayload in sync with what coreboot is doing.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: Ie9c30b0f0d30531c5f9d99c2729246a86b8cec26
    Reviewed-on: https://gerrit.chromium.org/gerrit/59294
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4316
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9531692ee18553098b951d8bf5a2eaf46e4d76f5
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 19 15:47:05 2013 -0700

    qemu-armv7 CPU: Move Kconfig code into CPU directory
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: Icae8042add5f4dd5c707369ffc4587c613d69d29
    Reviewed-on: https://gerrit.chromium.org/gerrit/59324
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4315
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a9c8361c02474f66c398fc292c6c5129b48578de
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 16 17:47:35 2013 -0700

    cbmem: fix userspace utility to work with dynamic CBMEM
    
    This also adds an option -x/--hexdump to dump the whole
    CBMEM area for debugging.
    
    Change-Id: I244955394c6a2199acf7af78ae4b8b0a6f3bfe33
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/62287
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4312
    Tested-by: build bot (Jenkins)

commit 7f68150f1e148528169680438ee5047bfb46cfe1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 19 15:39:09 2013 -0700

    cbmem: Implement ARM support
    
    on ARM the CBMEM utility requires the procfs entry
    /proc/device-tree/firmware/coreboot/coreboot-table
    provided by the FDT (dynamically created by depthcharge
    at the moment)
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: If5f961afb23791af6f32dd4fc9a837a1aa41b70e
    Reviewed-on: https://gerrit.chromium.org/gerrit/59322
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4311
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e02a8330e89019bd2123e279291b7386f5e672b2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Dec 2 17:12:47 2013 +0200

    lenovo/x60: Drop global oprom_is_loaded
    
    Variable use is specific to ChromeOS.
    
    Change-Id: I5b61a038e6b08e3b2408c4d990749d45fdf2148d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4306
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit b67d99c01a9f57b338cd73b94c3a7c069d15e2e8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Aug 18 18:08:40 2013 +0300

    lumpy: Fix build without ChromeOS
    
    Change-Id: I1a59405499deceed7df01a03834be72830e6578f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4291
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 48a749a89844ba76ff1564d5009e81d4d8e06db8
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Oct 29 22:13:38 2013 -0600

    intel/cougar_canyon2: Intel CRB FSP based mainboard
    
    Cougar Canyon 2 is a Ivybridge/PantherPoint reference board.
    This implementation uses the Intel FSP (Vist the Intel FSP
    website for details on FSP architecture and support).
    The FSP does not support s3 at this time. S3 may be added
    when it is available in the FSP. All other features and IO
    ports are functional. Booted on Ubuntu 12.04 and 13.04,
    Fedora 18 with SeaBIOS payload. Memtest86, FWTS, and
    other tests pass.
    
    Board support page will be updated on acceptance.
    
    Change-Id: I26c0b82d7ac295498376ad4c3517a9d6660d1c01
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4018
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0da082b62542fae0f6882a90dcff7ddcf672d96d
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Oct 29 22:20:45 2013 -0600

    Update SMM for FSP systems
    
    Add the FSP northbridge and southbridge includes.
    
    Change-Id: I5c7f395dc033caa8d0bf0313382769595d77f2a5
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4019
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 73a9b503f00675753f97227d967bb0adddb3ca00
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Oct 29 22:12:32 2013 -0600

    Add Intel FSP bd82x6x southbridge support
    
    Add support for the bd82x6x using the Intel FSP.
    The FSP is different enough to warrant its own source files
    for now. The mrc/system agent chromebook solution does much more
    southbridge initialization and configuration than the FSP version.
    It may be combined in the future.
    
    Change-Id: Ie493945f3d321d854728d231979a0c172d2b36de
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4017
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bdafcfa55509d0cf2cbbb686411f569d56d3916c
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Oct 29 17:46:54 2013 -0600

    Add the Intel FSP 206ax CPU core support
    
    Add support for 206ax using the Intel FSP.
    The FSP is different enough to warrant its own source files
    for now. It has different CAR code, micorcode, and FSP inclusion.
    It may be possible to combine this code with the mrc based
    solution used by the chromebooks in the future.
    
    Change-Id: I5105631af34e9c3a804ace908c4205f073abb9b4
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4016
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 54b8e7a0bba7787eca737506cb5d85bf408344d2
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Oct 29 17:57:30 2013 -0600

    Add Intel FSP northbridge support Sandybridge and Ivybridge
    
    Add support for Sandybridge and Ivybridge using the Intel FSP.
    The FSP is different enough to warrant its own source files.
    This source handle the majority of FSP interaction.
    
    "Intel® Firmware Support Package (Intel® FSP) provides key
    programming information for initializing Intel® silicon and can be
    easily integrated into a boot loader of the developer’s choice.
    It is easy to adopt, scalable to design, reduces time-to-market, and
    is economical to build."
    http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html
    
    Change-Id: Ib879c6b0fbf2eb1cbf929a87f592df29ac48bcc5
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4015
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a5adfed6e33c1cb43971f7fe3f5cfc90e4f42846
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 12 17:18:03 2013 -0700

    qemu-armv7: Drop additional console_init()
    
    It's done in bootblock_simple.c just after returning from
    the mainboard specific bootblock function.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I96cab5e406132a9f7dc30d48ff99f524773a1a14
    Reviewed-on: https://gerrit.chromium.org/gerrit/58473
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4257
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 46957056c0cf56ff08b9c841bbde444cb51baacd
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 26 01:16:20 2013 +0100

    ibexpeak: ensure config compatibility with bd82x6x
    
    Ibexpeak shares few files with bd82x6x. In order for it to work correctly
    their config structures from chip.h must match, so include bd82x6x/chip.h
    in ibexpeak/chip.h
    
    Change-Id: Ib56b311b8af04f4e4803d1834724680f604901cd
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4277
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 5ae3175218bd1970938683c6759ded4addbc0b0d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 19 13:47:46 2013 -0700

    Drop obsolete CONSOLE_LOGBUF
    
    This was used by Ron 13ys ago and was never used again
    ever since.
    
    Change-Id: I8ae8a570d67fa0b34b17c9e3709845687f73c724
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59320
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4256
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 6149776e7312b6c2417aa8c3621f864b36cea7cd
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jun 19 20:48:06 2013 -0700

    libpayload: ARM: Don't leave alignment checking on after the exception test
    
    Currently, the exception handling code on ARM in libpayload turns on alignment
    checks as an easy way to generate an exception for testing purposes. It was
    leaving it on which disabled unaligned accesses for other, unlreated code
    running later. This change adjusts the code so the original value of the
    alignment bit is restored after the test exception.
    
    Built and booted into depthcharge on pit with an unaligned accesses added
    after the call to exception_init in the depthcharge's main. Before this
    change, the access caused an exception. After this change, the access
    completed successfully.
    
    Change-Id: If92cab3cc8eabca7c5b0560ce88a8796a27fe3b2
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59372
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4255
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit cfe77beea4bb2ec501a14ab822e4773f64dfb21b
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jun 19 04:54:38 2013 -0700

    libpayload: Make the region to scan for the cb tables configurable.
    
    The address range to scan for the coreboot tables varies from machine to
    machine based on the range memory occupies on the SOC being booted and on the
    amount of memory installed on the machine. To make libpayload work on
    different ARM systems with different needs, this change makes the region to
    scan configurable. In the future, we might want to come up with a more
    automatic mechanism like on x86, although there's less consistency on ARM as
    far as what ranges are even memory in the first place.
    
    Change-Id: Ib50efe25a6152171b0fbd0e324dbc5e89c527d6e
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59242
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4254
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 4bdc4aa297150f4b8913f43df8286671886aca3e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Jun 19 10:49:29 2013 -0700

    lynxpoint: Fix LPT-LP PME_B0 bit offset in ACPI _PRW objects
    
    LynxPoint-LP has a lot of GPEs and the "default" set has been
    moved to register 4 starting at bit offset 96.  This means
    that PME_B0 bit in GPE0_EN/GPE0_STS is now bit 109 in LPT-LP
    but still bit 13 in LPT-H.
    
    suspend on falco and wake from usb
    
    4 | 2013-06-19 10:49:17 | ACPI Enter | S3
    5 | 2013-06-19 10:49:22 | ACPI Wake | S3
    6 | 2013-06-19 10:49:22 | Wake Source | Internal PME | 0
    
    Change-Id: I443cd4d17796888debed70c0bda27ae09accd09b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59265
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4253
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit a392d477c10d587a1c3de29c3c3e6c56a7fcafdd
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 19 12:06:50 2013 -0700

    libpayload: Add missing break statement in coreboot table parsing
    
    Otherwise the code would try to parse GPIOs when encountering
    a mainboard entry in the coreboot table. This never caused any
    problems because the mainboard entry is parsed before the GPIO
    entry.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I1443bda8585a990a39115743d48304ec4b54bccb
    Reviewed-on: https://gerrit.chromium.org/gerrit/59292
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4252
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 199e196005eddfe669e0ce653f6f7da1c595c380
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jun 4 10:14:42 2013 -0700

    vboot: use out_flags to indicate recovery mode
    
    In order to make the proper decision on loading the
    option rom or not the recovery mode setting needs to be
    known.  Normally this is detected by asking the EC,
    but if recovery is requested with crossystem then the EC
    does not know about it.  Instead we need to check the
    output flags from VbInit().
    
    Change-Id: I09358e6fd979b4af6b37a13115ac34db3d98b09d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57474
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4223
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit eec8e33ecd31caf7e2df7209dfee0abaf97b0be2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jun 4 10:08:54 2013 -0700

    vboot: Do not pass OPROM_MATTERS flag to VbInit
    
    Since we are using VBNV to determine if developer mode is
    active we do not need the messy OPROM hook magic any longer.
    
    Change-Id: I1b9effef3ef2aa84e916060d8e61ee42515a2b7c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57473
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4222
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f9da70618e8d6d05aa6e8ae92479e5fc3764d7bd
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jun 4 10:06:25 2013 -0700

    slippy/falco/peppy: Fix Chrome OS GPIO export in ACPI
    
    The OIPG package needs to have >1 member to make the chromeos_acpi
    kernel driver do the right automagic sysfs topology creation.
    
    Additionally an "unimplemented" GPIO should be reported as 0xFF
    because 0 is a valid GPIO number.
    
    verify crossystem on slippy
    
    $ sudo crossystem | grep -e recoverysw_cur -e wpsw_cur
    recoverysw_cur         = (error)
    wpsw_cur               = 1
    
    Change-Id: I06dff09152bde30a3ffe58b1defe9d299155472c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57471
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4221
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6a805905cb5737108260174d422b52a5641fc2ff
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 3 10:45:08 2013 -0700

    haswell boards: Enable VIRTUAL_DEV_SWITCH
    
    This config option was not enabled which was preventing
    the user from enabling developer mode from recovery mode.
    
    With this enabled we can disable the "dev mode by default"
    behavior and let people enable it by entering recovery mode.
    
    This will make the firmware behave like a typical chromeos
    device.
    
    Peppy is left in "default dev mode" until after bringup.
    
    1) boot slippy in normal mode by default
    2) enter recovery mode with servo button
    3) Ctrl+D on USB keyboard to enter developer mode
    4) boot slippy in developer mode
    
    Change-Id: I414c0d10dd0489e3c89798f75a2872a43297c8d8
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57350
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4220
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b1b9c93f7c4deb1db7eccfe001d8ef146052d3eb
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Oct 17 16:38:25 2013 +0300

    Add option to disable ChromeOS
    
    Those building Chromebook firmware from coreboot git might be more
    interested in building without ChromeOS extras.
    
    Change-Id: I2f176d059fd45bf4eb02cc0f3f1dcc353095d0ce
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3977
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 161e9cc56b6009068a2b690f0d5d073bbb228acc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Nov 27 21:36:25 2013 +0100

    Introduce a config whether dock is inited in romstage or not
    
    Instead of depending on exact mobo configure general characteristic whether
    dock is configured in romstage or ramstage.
    
    X60 and T60 have superio in dock so it needs to be inited to get serial, so
    it should be inited in romstage.
    
    On X201 there is nothing useful that early in boot but it's needed to init more
    to get dock working, in particular EC init needs to be done first.
    Change-Id: If5072e3dec883a94cd2d5643a92f7f6c3c9feee9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4294
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dfc0881272ebb7d865fefbb037f7545b37bf2be3
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 26 16:37:45 2013 +0100

    EC H8: remove dependence on IS_X201
    
    Instead define brightness up/down function and gfx device and use
    preprocessor magic to glue it together.
    
    Change-Id: I03074ae07b33c1546d229efc3e80606ddbee6300
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4282
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 72dccce0c9a7cf59ca51a3174fc11eb8899e1761
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Nov 23 19:22:53 2013 -0600

    global: Fix usage of get_option() to make use of CB_CMOS_ codes
    
    Do not directly check the return value of get_option, but instead compare
    the returned value against a CB_CMOS_ error code, or against CB_SUCCESS.
    
    Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4266
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bcfcfa4473357eb6272bc8bcc5e03f4ba517bcd2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 3 10:41:12 2013 -0700

    haswell: Update pei_data to match ref code
    
    - Add a new USB location field
    - Add a new "ddr_refresh_2x" field, enabled on Falco only
    - Fix copy+paste bug in baskingridge
    
    Checked that tREFI is halved during memory setup in the memory
    training log:
    tREFImin = 6240       << DEFAULT
      C(0).tREFI = 0xc30  << MODIFIED (=3120)
      C(0).tREFI = 0xc30  << MODIFIED (=3120)
    
    Also ensure that the SD card is detected properly again.
    
    Change-Id: Ie3a82c08df06ada9af56282b5255caefa56487f2
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57349
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4219
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit a6c29fe6841ad5e03ddb35803943bed3bc83dfd2
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 26 17:49:29 2013 +0100

    amd/car/post_cache_as_ram: Switch stack in assembly rather than in C
    
    Compiler may do loads of optimisations around stack switch and so it's allowed
    to break stack switch as it sees fit. Do it in assembly instead.
    
    Not tested.
    
    Change-Id: I277a62a9052e8fe9b04e7c65d149e087282ac2a2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4286
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 77a5abe78052ac8f65c005272700d82c2b014da7
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jul 6 19:44:47 2013 +0200

    ec/lenovo/h8: Add h8_build_id_and_function_spec_version()
    
    The function reads the Build ID and the supported function specification
    version from the running EC firmware, and stores a text representation
    in the provided output buffer.
    
    Change-Id: I3b647d7f315c9b4922fa9a9c5167a80f6d82e753
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3617
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3d06488dbf86763d87980dbf66f384d430eff4fd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Nov 30 21:04:40 2013 +0200

    Makefile: Drop obsolete rules
    
    The source files were removed with commit 3e4e3038.
    
    Change-Id: I2df9d8cce0ec1462dcba4790a6c62abade0d223c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4298
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 39536e955a93d025f941dcb51bff640815212d15
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jun 11 16:17:56 2013 -0700

    falco: Update panel power sequence timings
    
    These are based on the datasheet and I included the timing
    values I used from the docs.
    
    Change-Id: Ib75b2c5e50ac09d1e4cf9dd22229bb0f0a8965a4
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/58540
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4234
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit ccd2f28fc46793381d1f628a94baf25f784cf8ed
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jun 11 08:49:55 2013 -0700

    peppy: Port updates from slippy/falco boards
    
    - Add HDA verb table
    - Add on-board device table
    - Add panel power sequencing values
    
    Change-Id: I1b3450c2740ec1d930f157a9b23550e1efc8668f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/58197
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4233
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 9c660993cd5d1dfc25c31daa4215289eadb63884
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Jun 4 08:57:54 2013 -0500

    vboot: use out_flags to indicate dev mode
    
    In order to make the proper decision on loading the
    option rom or not the developer mode setting needs to be
    known. Under early firmware selection it is possible to know
    the state of developer mode by a flag in out flags. Use this
    flag when early firmware selection is being employed to determine
    if developer mode is enabled or not.
    
    Change-Id: I9c226d368e92ddf8f14ce4dcde00da144de2a5f3
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57380
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4218
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit b6b3f79db8af6f4ed4fa5aca79ca159a638ac00a
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jul 6 20:10:36 2013 +0200

    lenovo/x60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String
    
    The Linux thinkpad_acpi.c driver looks for this string while
    reading information about the system it is running on.
    
    This commit does not make the module load but it is one of
    several things that the module looks for on a ThinkPad.
    
    Change-Id: Ia48bbd85ba4d528063695345b0f968d264573341
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3779
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 9a6ca071e006b46ec4472e781d177271e2e02a45
Author: Shawn Nematbakhsh <shawnn@google.com>
Date:   Thu Jun 13 19:47:47 2013 -0700

    peppy: Add 2GB DRAM configuration.
    
    Currently, all Peppy boards w/ '000' SPD GPIOs have 2GB DRAM. Disable
    the second DRAM channel based upon the GPIOs.
    
    Need to change / confirm this for upcoming builds.
    
    Change-Id: I7085ddecb80626cc0bed99ba7b174c6b80350696
    Reviewed-on: https://gerrit.chromium.org/gerrit/58620
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4238
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d9e298961f96e89a831a2993686b89b13089c76a
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Fri May 31 18:57:20 2013 -0700

    peppy: Re-enable EC software sync
    
    The EC was disabling flash commands and sysjump was not working
    properly. With those two fixed software sync works properly.
    (Taken from I63ca00d6c94854f2b395eb736ce20792da5f8de2).
    
    Change-Id: I9c7d1d1f1aaf7de33d0cec5f6daf648576ba8900
    Reviewed-on: https://gerrit.chromium.org/gerrit/57289
    Reviewed-by: Dave Parker <dparker@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4212
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6fb41dcad7e5030530f307b1ed86ffecd5e6eb89
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Tue May 28 17:46:49 2013 -0700

    peppy: Update GPIO table + USB port map.
    
    - Update GPIO table to match board.
    - Update USB port map.
    - Remove iSSD power sequencing code.
    
    Change-Id: Iaa8e5921ed9db6bcfd18b5a888c7f80b2c93a710
    Reviewed-on: https://gerrit.chromium.org/gerrit/56869
    Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4211
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 0bf1febed82c8433686978c74a0c851d85189f91
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Apr 26 03:34:00 2013 -0700

    elog: Get rid of the descriptor type and some unnecessary wrappers
    
    There was always exactly one elog descriptor declared and initialized, but its
    contents were being accessed through a pointer that was passed back and forth
    between functions instead of being accessed directly. This made the code more
    verbose than it needed to be and harder to follow. To address this the
    descriptor type was eliminated, its contents were turned into individual
    global variables, and various functions were adjusted to no longer take the
    descriptor as an argument.
    
    Similarly, the code was more verbose and complicated than it needed to be
    because of several wrapper functions which wrapped a single line of code which
    called an underlying function with particular arguments and were only used
    once. This makes it harder to tell what the code is doing because the call to
    the real function you may already be familiar with is obscured behind a
    new function you've never seen before. It also adds one more text to the file
    as a whole while providing at best a marginal benefit. Those functions were
    removed and their callers now call their contents directly.
    
    Built and booted on Link. Ran mosys eventlog list. Cleared the event log
    and ran mosys eventlog list again. Added 2000 events and ran mosys eventlog
    list. Cleared the log again and ran mosys eventlog list.
    
    Change-Id: I4f5f6b9f4f508548077b7f5a92f4322db99e01ca
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49310
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4245
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 84a93d1bc34287f2208e40a704fa48c091182cd5
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Apr 24 23:31:41 2013 -0700

    elog: Stream line the elog driver.
    
    The elog driver's design was a bit more elaborate than it really needed to be
    since it no longer had to keep track of multiple copies of the log in flash
    and also in memory. This change streamlines it by removing unnecessary
    compartmentalization of some bits of code, and some variables which tracked
    the last entry added which were never used.
    
    Built and booted on Link. Ran mosys eventlog list. Added 2000 events to
    the event log and ran mosys eventlog list again. Cleared the log by echoing 1
    into /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list.
    
    Change-Id: I7d4cdebf2f5b1f6bb1fc70e65eca18f71b124b18
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49309
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4244
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 455c68ed0dca6cc5c8df4131c2fcf314e3002f56
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Apr 24 17:54:37 2013 -0700

    elog: Merge elog_validate_and_fill into elog_init_descriptor.
    
    elog_validate_and_fill was called in exactly one place, in
    elog_init_descriptor. It didn't actually do what its name implied since the
    data in the event log was already "filled" by elog_init_descriptor. Likewise
    elog_init_descriptor was delegating an important part of its own job, scanning
    through the list of events, to elog_validate_and_fill.
    
    Since one function was basically just a displaced part of the other which
    couldn't really stand on its own, this change merges them together.
    
    Built and booted on Link. Ran mosys eventlog list. Added 2000 events with
    the SMI handler and ran mosys eventlog list again.
    
    Change-Id: Ic899eeb18146d0f127d0dded207d37d63cbc716f
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49308
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4243
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 42cb7090c5c88e8b191908df191de3bbaf888ffe
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Apr 24 17:36:53 2013 -0700

    elog: Get rid of elog_reinit_descriptor.
    
    This function was just a wrapper around elog_init_descriptor, and all it did
    was pass the current backing store location and size back in so it would be
    reused. Those values, which never change, are now set in
    elog_setup_descriptors, eliminating those parameters to init and eliminating
    the need for _reinit_.
    
    Built and booted on Link. Ran mosys eventlog list. Added 2000 events to
    the log and ran mosys eventlog list again.
    
    Change-Id: I133768aa798dfc10f32e14db95235a88666890c3
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49307
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4242
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 331eb084bb76cdbd3b13dc6661bb70a58abd35e1
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Apr 24 04:11:40 2013 -0700

    elog: Eliminate the second in memory copy of the event log.
    
    The event log driver keeps two copies of the event log in memory, one to
    take the place of the historically memory mapped image of flash which is now
    read and written manually, and one originally intended to be an in memory
    cache of flash. Since both are now just copies in memory, there's no value in
    having them both and keeping them in sync.
    
    Built and booted on Link. Ran mosys eventlog list. Added 2000 events to
    the log and ran mosys eventlog list again. Cleared the log by echoing a 1 into
    /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list again.
    
    Change-Id: Ibed62a10c78884849726aa15ec795ab2914afc35
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49306
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4241
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bfae4aa768ca376e2b5b216b57b33600e2a8a094
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Apr 24 03:16:21 2013 -0700

    Make elog_shrink not depend on having seperate memory/flash descriptors.
    
    The way elog_shrink currently works is that it completely clears the data in
    the flash/flash descriptor and then recreates it using the part of the log
    it's going to keep as stored in the memory descriptor. That scheme depends on
    there being to independent copies of the log.
    
    This change reworks elog_shrink so that it moves the data it wants to keep
    within a single descriptor and then propogates it to the other and to flash
    intact. This way, when one of the descriptors goes away, all we have to do is
    remove the code that would update it.
    
    Built and booted into ChromeOS on Link. Ran mosys eventlog list. Added
    2000 events to the log and ran mosys eventlog list again. Echoed a 1 into
    /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list.
    BRANCH=None
    
    Change-Id: I50d77a4f00ea3c6b3e0ec8996dab1a3b31580205
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49305
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4240
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e62e0369d503ac4088b13ef09b15dbe50479855e
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Apr 23 19:36:01 2013 -0700

    elog: Get rid of the staging_header variable.
    
    The header is at the start of the log. There's no reason to either keep a
    seperate pointer to it, or to keep a copy of it in some other bit of memory.
    
    Built and booted on Link and used 'mosys eventlog list' to list the
    contents of the log. Ran
    
    for x in $(seq 1 2000); do
      cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog;
    done
    
    And ran mosys eventlog list again to verify that the log had been shrunk
    correctly.
    
    Change-Id: I2afcd52c0ce5bbb662ac56f2895cdbea28d5c2ce
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49304
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4239
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 60f820835f66ad4eb63f2fdecb7ebce3411077a8
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Jun 19 13:28:04 2013 -0500

    lynxpoint: move all pcie device handling to pcie.c
    
    Some of the pcie logic was located in pch.c as well
    as pcie.c. Move all pcie logic to the same pcie.c
    file. This is a straight cut-and-paste (no logic changes)
    except for a rename from pch_pcie_enable() ->
    pch_pcie_enable_dev().
    
    Change-Id: I338c53039b95f255ab9ced313c51193a9d34b404
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59277
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4251
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 3fcd356464bd65e8aafa0aae01e7fa6a2f4bc67d
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Jun 19 13:20:37 2013 -0500

    lynxpoint: expose pch_disable_devfn()
    
    The function to disable devices was formerly named
    pch_hide_devfn(). This routine was doing more than hiding
    devices. It was disabling them, i.e. turning them off.
    Therefore, rename it to pch_disable_devfn(). Also, allow
    external callers to this function.
    
    Change-Id: Id5bb319d4e67892c02a39dff49e45b2811a2f016
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59276
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4250
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit c17aac32f27f6ab18faaabc8a5667bc2a0a10120
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Jun 19 13:12:48 2013 -0500

    lynxpoint: expose iobp functions
    
    The iobp functions are useful to may of the southbridge
    devices as certain values need to be updated to properly
    initialize the devices. Therefore expose read, write, and
    updated iobp functions.
    
    Change-Id: Id7fdd8d0d9f022f92d6285ecd8f85a52024ec2bb
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59275
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4249
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 91bd0b8419d4949fd2aa447432f0d68352f20965
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jun 18 13:19:26 2013 -0700

    Add description to MAINBOARD_VENDOR string so it can be overridden
    
    A quirk of the Kconfig used in coreboot is that config options
    cannot be overriden by local config changes unless they have
    a description string.
    
    1) Add CONFIG_MAINBOARD_VENDOR="Custom" to local config
    2) Build and flash coreboot
    3) cat /sys/class/dmi/id/sys_vendor and look for "Custom"
    
    Change-Id: I1b5f2124cd4a22c056c025143ae5bcaafa6b03f0
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/59088
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4248
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 12a41d8f8ef2fc7cc93d0a1ff7eed162950994e0
Author: Shawn Nematbakhsh <shawnn@google.com>
Date:   Tue Jun 11 20:30:09 2013 -0700

    peppy: Add an inverted input GPIO type
    
    The wake device input pins are active low and the
    GPIOs need to be set as inverted when they are marked
    as an input so they are not spuriously logged.
    
    Also sync pin states from Falco initial commit.
    
    Reference change: I15d38dcc9b2fb4b2b0eb27da358fa3c343e22323
    Change-Id: I66e136d389d53a367436d816fa84dacdc8e86bad
    Reviewed-on: https://gerrit.chromium.org/gerrit/58334
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-by: Dave Parker <dparker@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Signed-off-by: Shawn Nematbakhsh <shawnn@google.com>
    Reviewed-on: http://review.coreboot.org/4247
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 38ad4911f60fed70b703782b2b40324bed121f38
Author: Dylan Reid <dgreid@chromium.org>
Date:   Fri Jun 14 11:50:35 2013 -0700

    falco/slippy: Fix DMIC nid verb.
    
    Set nid 0x12 instead of nid 0x05.  The DMIC is on NIC 0x12.
    
    Change-Id: Ifc883b65a50aeec6a6d3ad02fe8418f124e6241d
    Signed-off-by: Dylan Reid <dgreid@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/58711
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
    Tested-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Jay Kim <yongjaek@chromium.org>
    Tested-by: Jay Kim <yongjaek@chromium.org>
    Reviewed-on: http://review.coreboot.org/4246
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c7633f4f5e3693c005791006e6cc788b218770c7
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jun 13 17:29:36 2013 -0700

    slippy/falco/peppy: Fix SPD GPIO initialization.
    
    SPD GPIOs were being read prior to initialization in romstage_common. To
    fix, pass the copy_spd function to romstage_common, to be called at the
    appropriate time (after PCH init, before DRAM init).
    
    Change-Id: I2554813e56a58c8c81456f1a53cc8ce9c2030a73
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/58608
    Reviewed-on: http://review.coreboot.org/4237
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 752b1e6d5d341e9c328d596a6f00bd8071274a48
Author: Shawn Nematbakhsh <shawnn@google.com>
Date:   Wed May 8 11:45:23 2013 -0700

    Butterfly: Force DDR refresh rate to 2x.
    
    Due to OEM request, always set DDR refresh rate at 2x.
    
    Change-Id: I81a4f57aca6388551dca6effbd9a4ac1a97e4f5a
    Reviewed-on: https://gerrit.chromium.org/gerrit/50477
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4214
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 932fbd659ac7bea41e977f5fb5315fcfc93d36dd
Author: Shawn Nematbakhsh <shawnn@google.com>
Date:   Wed May 8 11:41:04 2013 -0700

    Add DDR refresh config to pei data structure.
    
    Allow platform customized DDR config, including forcing refresh rate to
    2x.
    
    Change-Id: I311ae7ddf25142153c94a3fc3fb0a36e03f50ab2
    Reviewed-on: https://gerrit.chromium.org/gerrit/50476
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4213
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ce22cd066bfa1c3c2c24ef6c6759620c52aeba22
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Nov 30 21:06:18 2013 +0200

    Fix build with USE_OPTION_TABLE
    
    Parallelized build might try to build SMM before option_table.h is
    created. Remove related redundant explicit rules.
    
    Change-Id: Ida8b5c408af05adcf3210ce7bfc8a1e5959194c7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4299
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit eb13b6f3e886d6f97105464cc2292e775ac83778
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 26 10:13:28 2013 +0100

    H8: Move EC GPE declaration to mainboard
    
    Change-Id: Iefc481f09268dd15bbc3cbfa8bdd110d44383f6a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4281
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit a522cf0c9c348ca75d8a758857c180db88c0f691
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 29 07:49:55 2013 -0700

    lynxpoint: Do not clear ACPI NVS region on resume
    
    There are useful values in NVS that are set at boot
    and runtime and they should not be cleared on resume.
    
    suspend/resume twice on slippy and ensure
    that the USB ports are still powered on the second suspend.
    
    Change-Id: I4bce60b02b6637f6683120ae9c4a5c64563aacf7
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56941
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4210
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 44c0e4e11a9a5a7cb087bf42f0f6c47abc2b0aa5
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Nov 27 22:54:11 2013 +0200

    CBMEM console: increase temporary buffer size for non-dynamic CBMEM
    
    Make temporary buffer allocation equal with the allocation in CBMEM and
    let copy_console_buffer() handle possible truncation.
    
    When not using dynamic CBMEM the CBMEM area is initialized late in the
    ramstage and should be able to hold almost as many characters as the
    CBMEM can hold. We have seen 40000 was not always enough with logging
    level set to spew, new default size is 0x10000.
    
    Change-Id: If4b143fdf807e28b6766b8b99db5216b767948d5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4295
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 19d06b2f891a47bdaa02a5b8e60cef85313aae83
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Sep 9 11:22:18 2013 -0700

    cbmem console: reduce temporary buffer size for dynamic CBMEM
    
    When using dynamic CBMEM the CBMEM area is initialized before
    entering ram stage, and so we need a way smaller temporary buffer
    for the CBMEM console during early bits of ram stage. In practice
    around 256 bytes are needed, but keep the buffer at 1k so we make
    sure we don't run out.
    
    TEST=Boot tested on pit
    BRANCH=none
    BUG=none
    
    Change-Id: I462810b7bafbcc57f8e5f9b1d1f38cfdf85fa630
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://chromium-review.googlesource.com/168575
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    [km: cherry-pick 7fd1bbc0 from chromium git]
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4293
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit a3c5ba3ca71c6c6a72a4ab1ef244d3b4acfb83a9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Nov 27 17:51:31 2013 +0200

    CBMEM console: Prevent buffer overrun
    
    Make sure memcpy target and a possible message telling log was truncated
    stay within the allocated region for CBMEM console.
    
    This fixes observed CBMEM corruption on platforms that do not use CBMEM
    console during romstage. Those platforms will need an additional fix to
    reset cursor position to zero on s3 resume.
    
    Change-Id: I76501ca3afc716545ca76ebca1119995126a43f8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4292
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 1fefa84405090ef659e561809a043febbef997a9
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Thu Oct 24 20:37:48 2013 +0800

    dmp/vortex86ex: Add timeout for keyboard system flag checking.
    
    If Vortex86EX PS/2 keyboard controller system flag bit times out,
    reload controller firmware code and try again.
    
    Abort and die after 11 tries as this means the CPU is defect. Also
    inform the user by printing a message.
    
    Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3988
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit f55f51a5606ece66676da0423cb2c61081a28f62
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Nov 25 23:40:01 2013 +0100

    ibexpeak: set HAVE_USBDEBUG_OPTIONS
    
    Previously, I've set this config in mobo config, yet according to
    Kyösti Mälkki this parameter is southbridge-specific and not
    mobo-specific.
    
    Change-Id: I92428aed5a69d88a371f5d7267bc54ba7530766c
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4276
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 994611a6377cac10e7cc372450018ac625a7cd32
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 29 07:48:47 2013 -0700

    lynxpoint: Add an inverted input GPIO type
    
    The wake device input pins are active low and the
    GPIOs need to be set as inverted when they are marked
    as an input so they are not spuriously logged.
    
    suspend/resume on slippy with trackpad wake:
    
    8 | 2013-05-29 07:43:14 | ACPI Enter | S3
    9 | 2013-05-29 07:43:18 | ACPI Wake | S3
    10 | 2013-05-29 07:43:18 | Wake Source | GPIO | 12
    
    and with power button wake:
    
    11 | 2013-05-29 07:43:35 | ACPI Enter | S3
    12 | 2013-05-29 07:43:40 | EC Event | Power Button
    13 | 2013-05-29 07:43:40 | ACPI Wake | S3
    14 | 2013-05-29 07:43:40 | Wake Source | Power Button | 0
    
    Change-Id: I15d38dcc9b2fb4b2b0eb27da358fa3c343e22323
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56940
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4209
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5679e5a4b6ddf32a3a5291913a353037938473ae
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Oct 21 20:23:35 2013 +0200

    google/parrot/smihandler.c: Use `battery_critical_logged` only with `ELOG_GSMI`
    
    Make the declaration and use of it conditional on the ELOG_GSMI Kconfig variable.
    
    Change-Id: I2ef291d2f3e7d35545014e03ba8e0045da6050e5
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3987
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4aab71aae4e9a30fa61aab10947869f3430be4ee
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 28 11:35:43 2013 -0700

    slippy/falco: Re-enable EC software sync
    
    The EC was disabling flash commands and sysjump was not working
    properly.  With those two fixed software sync works properly.
    
    Google Chrome EC MKBP driver ready, id 'slippy_no_version'
    Clearing the recovery request.
    EC hash:7fea29992ef72e3e64d8ffe522aa1dfa68dcb44a2da96a4c19530ea1a0bd22c4
    EC-RW hash address, size are 0xffa1cfe8, 32.
    Hash = 727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde
    Expected hash:727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde
    EC-RW firmware address, size are 0xffad000c, 57180.
    VbEcSoftwareSync() - expected len = 57180
    Computed hash of expected image:727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde
    VbEcSoftwareSync() updating EC-RW...
    VbEcSoftwareSync() jumping to EC-RW
    VbEcSoftwareSync() in RW; done
    
    Change-Id: I63ca00d6c94854f2b395eb736ce20792da5f8de2
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56821
    Reviewed-on: http://review.coreboot.org/4208
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit cb73a8410cb80c8ff86e3d860ac3c8ae458b19ac
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 10 10:41:04 2013 -0700

    Clean up POST codes for Boot State machine
    
    Now that there is a clearly defined boot state machine
    we can add some useful post codes to indicate the current
    point in the state machine by having it log a post code
    before the execution of each state.
    
    This removes the currently defined POST codes that were
    used by hardwaremain in favor of a new contiguous range
    that are defined for each boot state.
    
    The reason for this is that the existing codes are mostly
    used to indicate when something is done, which is confusing
    for actual debug because POST code debugging relies on knowing
    what is about to happen (to know what may be at fault) rather
    than what has just finished.
    
    One additonal change is added during device init step as this
    step often does the bulk of the work, and frequently logs POST
    codes itself.  Therefore in order to keep better track of what
    device is being initialized POST_BS_DEV_INIT is logged before
    each device is initialized.
    
    interrupted boot with reset button and
    gathered the eventlog.  Mosys has been extended to
    decode the well-known POST codes:
    
    26 | 2013-06-10 10:32:48 | System boot | 120
    27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize
    28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0
    29 | 2013-06-10 10:32:48 | Reset Button
    30 | 2013-06-10 10:32:48 | System Reset
    
    Change-Id: Ida1e1129d274d28cbe8e49e4a01483e335a03d96
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/58106
    Reviewed-on: http://review.coreboot.org/4231
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 8adf7a2c50dcb3a7f09b66c1f3918ab195d8c5ec
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 10 10:34:20 2013 -0700

    Log device path into CMOS during probe stages
    
    One of the most common hangs during coreboot execution
    is during ramstage device init steps.  Currently there
    are a set of (somewhat misleading) post codes during this
    phase which give some indication as to where execution
    stopped, but it provides no information on what device
    was actually being initialized at that point.
    
    This uses the new CMOS "extra" log banks to store the
    encoded device path of the device that is about to be
    touched by coreboot.  This way if the system hangs when
    talking to the device there will be some indication where
    to investigate next.
    
    interrupted boot with reset button and
    gathered the eventlog after several test runs:
    
    26 | 2013-06-10 10:32:48 | System boot | 120
    27 | 2013-06-10 10:32:48 | Last post code in previous boot | 0x75 | Device Initialize
    28 | 2013-06-10 10:32:48 | Extra info from previous boot | PCI | 00:16.0
    29 | 2013-06-10 10:32:48 | Reset Button
    30 | 2013-06-10 10:32:48 | System Reset
    
    Change-Id: I6045bd4c384358b8a4e464eb03ccad639283939c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/58105
    Reviewed-on: http://review.coreboot.org/4230
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit d5686fe23b1341ca2c72b2941cf80577e6198f23
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 10 10:21:41 2013 -0700

    Extend CMOS POST code logging to store extra data
    
    This can be used to indicate sub-state within a POST
    code range which can assist in debugging BIOS hangs.
    
    For example this can be used to indicate which device
    is about to be initialized so if the system hangs
    while talking to that device it can be identified.
    
    Change-Id: I2f8155155f09fe9e242ebb7204f0b5cba3a1fa1e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/58104
    Reviewed-on: http://review.coreboot.org/4229
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit e807c34a5e34e8dd7cb959458de593ea1070fde4
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 10 09:53:33 2013 -0700

    cmos post: Guard with spinlock
    
    The CMOS post code storage mechanism does back-to-back
    CMOS reads and writes that may be interleaved during
    CPU bringup, leading to corruption of the log or of other
    parts of CMOS.
    
    Change-Id: I704813cc917a659fe034b71c2ff9eb9b80f7c949
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/58102
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4227
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 35bd3fedfeafe96b5fb938c1b47e2b0380fdbfb7
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Mon Sep 24 22:14:24 2012 -0600

    Extend the ELOG errors for EC fan.
    
    Change-Id: Ida98f81b1ac1f6b3ba16c0b98e5c64756606fd58
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48318
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4126
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 748a6b10680bccaa890e9db388c1a9a6e284a227
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Mon Nov 25 17:12:07 2013 +0100

    qemu: minor bochs cleanups
    
    Add a comment, tweak spacing a bit, addr variable
    doesn't need to be global any more.
    
    Change-Id: Id8d8a7babce671243351074f7ac52a5c8c264de5
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/4274
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit bd7e8d8d2b1d65e59dd45db6529c89f9173b7b20
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Thu Jun 6 14:37:49 2013 +0200

    AMD Northbridge LX: simplify get_top_of_ram()
    
    Get rid of not needed dependency to gliu0table. This change is
    needed to move get_top_of_ram() to raminit.c - as needed for
    EARLY_CBMEM_INIT.
    
    Boot tested on a Bachmann OT200.
    
    Change-Id: I0bfe40c366a3537775d5c1ff8e0b1f5ac94320b7
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3380
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit b82a74c7ffc2da70012b47d76b055285469886bb
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 21 10:29:50 2013 -0700

    libpayload: Drop PowerPC architecture
    
    This was never completed / working and we have the working
    ARMv7 port for an architecture template, so get rid of this
    dead code.
    
    Change-Id: Ic2c1267ee5546dd6e1b63220c263b2fa86c8ae33
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56065
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4235
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5f5d914876218b106917a12c181b5b3f79264955
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 10 09:59:17 2013 -0700

    Add function to encode device path into integer
    
    This function will encode the device path into 3
    bytes of a dword which can be saved for debug.
    
    It will be used by subsequent commit to store the
    current device into CMOS for debugging BIOS hangs.
    
    Change-Id: I3a5155ea53c8d280806e610a0f8998dbabe15f3c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/58103
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4228
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 28080e451039bb14bdf2ab03a26f2819ed4991bf
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jun 11 08:43:12 2013 -0700

    falco: update verbs for ALC283
    
    Set verbs to reflect the layout used for ALC283 in Falco,
    which ends up being the same as Slippy.
    
    Change-Id: I3dce4effefaa91ee5bdcbe2a8a3750ebc41376ad
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/58196
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4232
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d7134e06b1b1ac21108b23438604b7385e4a43fa
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Nov 23 18:54:44 2013 -0600

    pc80/mc146818rtc: Return an error code rather than an integer
    
    Do not return hardcoded numerical values to communicate succes/failure, but
    instead use an enumeration.
    
    Change-Id: I742b08796adf136dce5984b702533f91640846dd
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4265
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fe9e30d6b74e340f9a97b9e358e20ec8a2785954
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Nov 23 17:46:04 2013 -0600

    include/types.h: Add generic enum for error codes
    
    The idea is that instead of:
     if (do_something()) do_something_else();
    It is more readable to write:
     if (do_something() != CB_SUCCESS) handle_error();
    
    Change-Id: I4fa5a6f2d2960cd747fda6602bdfff6aef08f8e2
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4264
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 85263b06bb423fdeb703f85c8e3378d989e854a3
Author: Dylan Reid <dgreid@chromium.org>
Date:   Tue Jun 4 20:01:32 2013 -0700

    slippy: update verbs for ALC283
    
    Set verbs to reflect the layout used for the ALC283 in slippy.
    
    install on slippy and check that headphone switch works
    as does external mic.
    
    Change-Id: I2d6bcda9cf8bbf49cbb6d2dbbe7f1a5adf315d8a
    Signed-off-by: Dylan Reid <dgreid@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57560
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4224
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1c20e385a09fcbbf83c03b3a2d3713f4403debea
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Jun 7 12:31:21 2013 -0500

    libpayload: usb mass storage card hot plug
    
    Mass storage devices such as card readers show up as
    as USB devices. However the media not be inserted. In those
    situations the previous code would just fake a disk and
    call usbcreate_disk. This is inappropriate because it forms
    a 1:1 mapping of USB device to disk leading to the inability
    to remove the disk and/or handle "hot plug" card insertion
    and removals.
    
    To alleviate this issue introduce the notion of ready to the
    usbmsc structure. It tracks detached, not ready, and ready
    states. The polling routine is then used to track not ready
    to ready transitions thereby creating and removing disks
    appropriately. This handles the case of inserting and removing
    a card that shows up as a new disk.
    
    Booted recovery mode. Able to observe inerstion and removal
    of sdcard. Also able to insert valid USB flash drive to boot
    as well.
    
    Change-Id: I3eefbe537ec1b9c975744b8984b06c17ae236f40
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57948
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4226
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a967f414dfb1f85097ba7ca2f00fdc7f415da776
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jun 6 16:14:21 2013 -0500

    libpayload: usb mass storage detect empty media
    
    There is currently a hard-coded 30 sec delay in the mass storage
    driver while waiting for each device to become ready. However, mass
    storage card readers that are empty return an error code on the
    TEST UNIT READY command. A REQUEST SENSE command then needs to be
    issued and interrogate the data to determine if no media is present.
    If no media determination is found to be true the USB device is no
    longer considered a candidate to be a disk.
    
    This code does lead to the fact that the media card reader needs to be
    populated at enumeration time. I suspect this is not an issue as it
    appears the storage stack in libpayload can't handle removable media
    coming online later.
    
    Booted recovery and dev modes. Noted that removable mass storage
    devices with no media were ignored without any boot delay.
    
    Change-Id: Ida7a45614d97c6e6fbfc9bb099765aad4df550fd
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57828
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4225
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2d9d39a7041cf531246845194f76cb9f65eaa08d
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 29 15:27:55 2013 -0700

    lynxpoint: Enable USB clock gating, late setup, and sleep prep
    
    Both EHCI and XHCI controllers have additional setup steps
    that are not part of the PEI reference code so they need to
    be done later.
    
    Both controllers also have specific clock gating setup
    requirements that are now implemented.
    
    Additionally they both have specific requirements when entering
    sleep states.  XHCI needs something in S3/S4/S5 and EHCI only
    has steps for S4/S5 entry.
    
    Change-Id: Ic62cbc8b6255455e56b72dd5d52e27a311999330
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57033
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4217
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5afca1357fdaebc5c4ad2b2a963f3c239648ba76
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu May 30 10:40:54 2013 -0500

    haswell: check for clean reset
    
    When an INIT# is delivered to the CPU the CPU starts
    executing from the reset vector. However, the internal state
    is maintained. Therefore, check for such a condition and
    reset the system.
    
    Issues 'apreset warm' on the EC console. INIT# is sent and
    CPU notices it's not a clean reset and forces one. No hangs.
    
    Change-Id: I71229e0e5015ba8c60f5989c533268604ecc1ecc
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/57111
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4216
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e9b50628d1c7f0cc8046903188562eebec8107bb
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Sat May 25 09:38:16 2013 -0700

    peppy: Add Elipda DIMM SPD
    
    Peppy RAM ID table is as follows:
    
    000 41K256M16HA
    001 H5TC4G63AFR
    010 EDJ4216EFBG
    
    Elpida SPD taken from Ib1e430cd390b4dbc013fc0802f1a59c1a0412577 by
    dlaurie.
    
    Change-Id: Iac156a2d25435514f28e2e73bef617d0fe2d90a1
    Reviewed-on: https://gerrit.chromium.org/gerrit/56687
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-by: Dave Parker <dparker@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4201
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e9d060d42c7ae3552962804cdab282738c4eeffa
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Thu May 23 15:13:46 2013 -0700

    peppy: Initial mainboard commit
    
    Taken directly from slippy with only constant + string changes.
    (Peppy port of I4172460d3b075bfd5bb22013a6225cf0e8f95b9c by dlaurie)
    
    The following changes are required in a subsequent commit:
    
    - Add Elpida SPD data.
    - Update GPIO map.
    - Remove iSSD power sequencing.
    - Update USB port map.
    
    Change-Id: I01dfb841f0e9186cf8a0a23f72e7be986a83be42
    Reviewed-on: https://gerrit.chromium.org/gerrit/56513
    Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-by: Dave Parker <dparker@chromium.org>
    Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/4200
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ae1ef60dfa304450bacc475cd767ac4a610a76e0
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 28 08:32:21 2013 -0700

    falco: Update DIMM SPD table
    
    RAM_ID indices have been changed and settled on a 2GB config
    that will be the same DRAM chips but only used in one channel.
    
    Change-Id: I444e655883ae045622ab3dfb964da4d7f86e1c0d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56810
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4198
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 116aa3a1900dae2beb56f381e91c9890c1e8ca30
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 28 07:55:02 2013 -0700

    falco: Add panel power sequence timings
    
    These are placeholder values until we can configure for
    the exact panel.
    
    Change-Id: If40367c0e5f80d46d085c89b0edae60f1ccacdaf
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56808
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4197
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c7f2ab742b2589281efa852309e29c8da5270fbe
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 28 07:49:09 2013 -0700

    haswell: Add magic to turn on grahpics in normal mode
    
    The haswell i915 kernel driver apparently expects the VBIOS
    to set a few specific registers.  This sequence is enough to
    make the driver happy without executing the VBIOS.
    
    This also makes graphics work after suspend/resume.
    
    Change-Id: I34937d55ffff8a9445442e6e6ca1bfc49869da63
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56806
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4195
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 22419e045616c344c7a2a308c5ef086a221ad006
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri May 24 12:37:02 2013 -0700

    falco: Add on-board devices and configure GPIO irq/wake
    
    Add the onboard I2C devices for Falco trackpad/lightsensor
    and generate SMBIOS Type41 tables for them.
    
    Add ACPI device for the trackpad to expose the interrupt map
    to the OS so it can be used.
    
    Configure interrupt GPIOs as PIRQ type and wake GPIOs as
    just standard input type.  The wake GPIO is reconfigured as
    ACPI SCI in the specific device _DSW method.  This prevents
    the wake GPIO from generating a flood of SCI at runtime.
    
    LTE_WAKE_L_Q and WLAN_WAKE_L_Q are left as ACPI SCI as these
    are not repurposed interrupt pins so they are not generated
    at runtime.
    
    SIM_DET and ALS_INT_L are set as input since we don't have an
    interrupt handler for them.
    
    Change-Id: Ibe9687b2f7f41ead18353c3f650219fe6e94ae2f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56632
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4191
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d67c5dbf06f009b705bc0c2b7278504bb538d36e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri May 24 11:27:12 2013 -0700

    slippy: Add on-board devices and configure GPIO irq/wake
    
    Add the onboard I2C devices for Slippy trackpad/lightsensor
    and generate SMBIOS Type41 tables for them.
    
    Add ACPI device for the trackpad to expose the interrupt map
    to the OS so it can be used.
    
    Configure interrupt GPIOs as PIRQ type and wake GPIOs as
    just standard input type.  The wake GPIO is reconfigured as
    ACPI SCI in the specific device _DSW method.  This prevents
    the wake GPIO from generating a flood of SCI at runtime.
    
    LTE_WAKE_L_Q and WLAN_WAKE_L_Q are left as ACPI SCI as these
    are not repurposed interrupt pins so they are not generated
    at runtime.
    
    SIM_DET and ALS_INT_L are set as input since we don't have an
    interrupt handler for them.
    
    tested on slippy with trackpad with additional
    kernel changes to chromeos_laptop.c to initialize devices.
    
    1) Ensure trackpad interrupt is functional and that there
    is not a flood of ACPI SCI when trackpad does interrupt:
      9:          1          0          0          0   IO-APIC-fasteoi   acpi
     37:        421          0          0          0   IO-APIC-fasteoi   cyapa
    
    2) Ensure that devices are exposed as wake capable:
    Device  S-state   Status   Sysfs node
    TPAD      S3    *enabled   pnp:00:00
    TSCR      S3    *disabled  pnp:00:01
    
    3) Ensure that trackpad can wake from S3 by default, but
    that it does not cause an immediate wake when entering suspend.
    
    4) Ensure that trackpad can be disabled as a wake source with
    echo TPAD > /proc/acpi/wakeup
    
    Change-Id: Id562d20b54eeefec56040b8f70ef238911312628
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56622
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4190
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 14031db21f3a41966a30bfc27bc97ddf03f40458
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri May 24 11:10:31 2013 -0700

    lynxpoint: Add ACPI Method to enable GPIO as wake source
    
    This is an LPT-LP specific method that will enable a specific
    GPIO as an ACPI SCI wake source.
    
    It can be used by a device _DSW method to enable a pin that is
    otherwise not configured to generate SCI at runtime.
    
    It will set:
    - GPIO owner to ACPI
    - GPIO route to SCI
    - GPIO config to GPIO, Input, Inverted
    
    Also clean up and remove ACPI field definitions that are unused
    and/or incorrect.
    
    Change-Id: I14acc2de50e6200f61c2898a7bd1252400e0f0be
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56621
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4189
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 96f77bd0d9436eb4259d2a132670735ac20e8b95
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri May 24 12:43:24 2013 -0700

    falco: Add Elpida DIMM SPD
    
    This was provided by the vendor but I added the part number at
    byte 128-143 so it can be identified when extracted by mosys.
    
    Change-Id: Ib1e430cd390b4dbc013fc0802f1a59c1a0412577
    Reviewed-on: https://gerrit.chromium.org/gerrit/56634
    Tested-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4192
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 86ce7f92735d4e0a3c6938cf7695b2805f5f48b4
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 28 12:37:08 2013 -0700

    RTC: Skip rtc_init() in S3 resume path
    
    In addition to not clearing the pending interrupts, we also
    don't want to reset the RTC control register when booting
    with an S3 resume.
    
    On most new systems, when the RTC well is losing power, we
    will also lose state that is required to perform a resume,
    so we end up in a normal boot anyways. Hence don't do any
    RTC initialization in the S3 resume path.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I73b486082faa741e9dccd15f2b8e3a8399c98f80
    Reviewed-on: https://gerrit.chromium.org/gerrit/56826
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Derek Basehore <dbasehore@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4206
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7ae7fc081b3832f1f6ba80eac8c92f788cbdd554
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue May 28 16:15:01 2013 -0500

    x86: fix compile error for !CONFIG_MULTIBOOT
    
    Some code was previously removed regarding elf notes. However,
    that code left a dangling comma under !CONFIG_MULTIBOOT
    configs for inline assembly constraints. Instead, place the comma
    within the #ifdef stanza.
    
    Change-Id: I805453ef57d34fbfb904b4d145d8874921d8d660
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56844
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: David James <davidjames@chromium.org>
    Reviewed-on: http://review.coreboot.org/4207
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 680b0ab72a1db04d4ce5be52131869e3d5d0135f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 19 16:07:46 2013 -0800

    baskingridge: drop incorrect USB handling code
    
    These GPIO accesses were copied by accident and don't
    make sense for the baskingridge board.
    
    Change-Id: I03bfc2cf97b6056a746a6c1a27308823ecaa9637
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4204
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c593999a0ad9b9f19c8171f6229faa191d055491
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri May 24 11:06:49 2013 -0700

    lynxpoint: Enable extra 16 IOAPIC entries for GPIO PIRQ
    
    LynxPoint-LP has an additional 16 entries in the IOAPIC that
    can be assigned to specific GPIOs when they are configured
    as PIRQ.
    
    The maximum redirection entries field in the IOAPIC needs to
    be set to 0x27 when this is enabled.
    
    Additionally specific GPIOs need to be routed to PIRQ so they
    interrupt via the IOAPIC instead of the GPIO IRQ 14/15.
    
    Change-Id: Ie587e1d203422ff6fb7fc5056d20a5ae66720991
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56620
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4203
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7820c77f2c118d604d0acfce8deb40536cae3121
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri May 24 11:02:06 2013 -0500

    wtm2: add ssdt2 table
    
    The LynxPoint southbridge ACPI code needs the SSDT2 table to function
    properly. Otherwise the ACPI evaluator in the kernel spews errors.
    
    Change-Id: I73918545a07e43f4a281ff34d8537340d601b102
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56601
    Reviewed-on: http://review.coreboot.org/4188
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 21a78706addd15fcc682f556566c303a463fcda1
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu May 23 14:17:05 2013 -0700

    smbios: Add generic type41 write function
    
    Mainboards were defining their own SMBIOS type41
    write function.  Instead pull this into the generic
    SMBIOS code and change the existing mainboards to
    make use of it.
    
    Change-Id: I3c8a95ca51fe2a3118dc8d1154011ccfed5fbcbc
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56619
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4187
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 032be82a11a9cee6cc45df7a5ea94778ea4280d7
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu May 23 07:23:09 2013 -0700

    elog: Check for successful flash erase in elog_shrink
    
    A parrot device with a bad flash part has been seen to hang
    in the elog_shrink code becuase the flash was not successfully
    erased and it gets stuck in a loop trying to shrink the log
    and then add an event.
    
    Change-Id: I8bb13dbadd293f9d892f322e213c9255c8e9acb3
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56405
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4186
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b1c25e74af0a7b1cb4aae0fc9ab8147ee9d14907
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu May 23 15:57:46 2013 -0500

    haswell: update pei_data data structure
    
    Update and use the new pei_data data structure. Now that the
    reference code is fixed it's possible to properly disable/enable
    the USB2 and USB3 ports correctly.
    
    Change-Id: I075c646e7574be354420b6e59507e8917a97d0f0
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56594
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4185
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5290f71569d1bf8b6fa80d34f4b176407082fec8
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 22 16:31:09 2013 -0700

    falco: Initial mainboard commit
    
    - Only the first two DIMM SPDs are specified so far
    - GPIO map is updated
    - iSSD power sequencing removed
    - USB port map updated
    
    Change-Id: I4172460d3b075bfd5bb22013a6225cf0e8f95b9c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56329
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4184
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 619eca0685ef2c7777ff0d741730a29af5db05a0
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed May 22 15:28:20 2013 -0500

    lynxpoint: fix mem corruption during ssdt2 gen
    
    The ssdt2 generation code was calling acpigen_patch_len().
    However, none of the entries had AML object lengths that
    needed patching. That resulted in the following message:
    
    ASSERTION FAILED: file 'src/arch/x86/boot/acpigen.c',  line 52
    
    Additionally, this caused an errant write to a memory address
    whose value was in the variable ltop. This was the 0 address.
    
    Change-Id: I44abf5a4e4225220575aee6b5c9bb6b0be093a28
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56299
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4182
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7fab00c8976bae54ed32617dd1e4c9b0ace249ab
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 22 09:51:11 2013 -0700

    lynxpoint: Fix XHCI controller device in ACPI
    
    The ACPI code was defining two EHCI controllers and ignoring
    the XHCI controller.  This changes the second EHCI controller
    to be XHCI instead and changes the wake resource to indicate
    S3 and not S4.
    
    cat /proc/acpi/wakeup
    
    Device  S-state   Status   Sysfs node
    HDEF      S4    *disabled  pci:0000:00:1b.0
    EHCI      S3    *enabled   pci:0000:00:1d.0
    XHCI      S3    *enabled   pci:0000:00:14.0
    
    Change-Id: If28775e6ef8608c22c85ca91d91d1f598ec7755d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56263
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4181
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 98c40622feeaf1d8f211501e8f337d5bde544d13
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 21 16:37:40 2013 -0700

    lynxpoint: Enable SerialIO clock in PCI mode
    
    The clock gating register at offset 0x800 is managed by the
    clock driver in the kernel when the devices are in ACPI mode.
    When in PCI mode we should force enable the clock here.
    
    When in ACPI mode or the device is disabled it should be put
    in D3Hot state.
    
    > i2cdetect -y -r 10
         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
    00:          -- -- -- -- -- -- -- -- -- -- -- -- --
    10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
    20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
    30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
    40: -- -- -- -- 44 -- -- -- -- -- -- -- -- -- -- --
    50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
    60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
    70: -- -- -- -- -- -- -- --
    
    Change-Id: Ib93ffd41bf36386d5ce63bfc0ae6597f3e23bc48
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56122
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4180
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8d1b132733ab82b689e9a7fd6677e317b1535c92
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 21 12:15:50 2013 -0700

    libpayload: Fix xcompile
    
    The architecture name for our ARM port is armv7, not arm.
    Hence, none of those flags were ever actually used.
    
    Fix the architecture name and remove the flags, they should
    not be set in xcompile, but in the Makefile, like in coreboot.
    
    Change-Id: Id9c5db7ebceafddb58a1ce1988417f09c074ba6c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56084
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4179
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cd7bb2faab769a16bacac8bcbfa20fec970dce16
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 21 09:28:28 2013 -0700

    slippy: Enable EC SMI
    
    Enable GPIO SMI for GPIO34 and set it as inverted so it
    is only generated when it is raised by the EC.
    
    1) ec console command: lidopen
    2) wait until booted to developer screen
    3) ec console command: lidclose
    4) ensure system turns off
    
    Change-Id: I7d50f171f3f4539c7c264103d1ffc7c5d0f1c7ba
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56052
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4177
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 8992e53c23cb088efbdafbf3e2ba77e7d8778d71
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 2 16:16:41 2013 -0700

    libpayload: Add USB support for non-PCI controllers
    
    Restructure USB stack to not depend on PCI, and
    make PCI stub available on x86, but provide fixed
    BARs for ARM (Exynos 5)
    
    Change-Id: Iee7c8b134c22b661a9a515e24943470c9dbadd1f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49970
    Reviewed-on: http://review.coreboot.org/4175
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 441a4baf87ada2608a109a203a5d8040f6dc2b0d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri May 17 11:56:09 2013 -0700

    libpayload (EHCI): correctly align PORTSC
    
    Two structures in the USB EHCI stack were pointing
    to hardware but not marked attribute((packed)) hence
    leaving it to GCC to correctly align the data structures.
    
    Next, the number of reserved bytes in hc_op_t was wrong
    (but implicitly aligned to the correct values on x86)
    
    It seems this worked fine on x86, but on ARM it was doing
    the wrong thing.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I94bed4850ded7d3f7bbc7ff3079c103c6054c22d
    Reviewed-on: https://gerrit.chromium.org/gerrit/55555
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4174
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ed095ca39a99d7dcc94856612cfff5695bd87ae6
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon May 20 15:57:16 2013 -0500

    lynxpoint: update azalia device ids
    
    The vendor ids were never updated to reflect LynxPoint's device
    ids. Therefore, none of the initialization was being ran. Fix
    this.
    
    Change-Id: Ic6ec00c9fb1cbcb6087fd89b0acff3d83294ac6a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/55821
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4173
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d7cb8d074f4a9e437ed897ac596ca794698b38c9
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 15 15:03:57 2013 -0700

    lynxpoint: Change SerialIO device enable reporting to ACPI
    
    In order to report whether coreboot enabled a SerialIO device
    in ACPI mode we had been relying on reading NVS in the _STA
    method for the SerialIO device.
    
    The ACPI _STA method has restrictions on what it can access
    and is unable to access OperationRegions outside its scope
    which means it should not be trying to read NVS.
    
    This change adds a new SSDT to the ACPI tables and fills it
    with constants that indicate whether or not a device is enabled
    in ACPI mode.
    
    The ACPI code is changed to read these variables from the
    SSDT and use that instead of trying to query a variable in NVS.
    
    Attempt to use lpt-clk driver to probe the
    device clocks for SerialIO devices and see that the kernel
    does not complain about accessing the GNVS region.
    
    Change-Id: I8538bee4390daed4ecca679496ab0cb313f174ce
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/51369
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4170
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8d783b84930e2e14e4f70234ea6589acd06557e7
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 14 11:16:34 2013 -0700

    slippy: Minor vboot related fixes
    
    - Disable EC software sync for now
    - Report correct EC active firmware mode
    - Force enable developer mode by default
    - Set up PCH generic decode regions in romstage
    - Pass the oprom_is_loaded flag into vboot handoff data
    
    Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/51155
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4169
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1c0540000dc4705cee44857293285382f4ae8bad
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri May 10 13:50:09 2013 -0700

    Fix int15 return value for mainboard oprom handlers
    
    These boards were returning 0 to indicate success when
    the realmode handler expects it to return 1 to indicate
    that it handled the interrupt.
    
    Change-Id: I2baeaf8c2774fa7668a8b2f2d9ad698302eefb21
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50881
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4168
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0e939155a332c884b2a068da6a9fc89246c34cb7
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 7 13:28:56 2013 -0700

    wtm2: Set SerialIO I2C ports to 3.3V
    
    These are both pulled up to 3.3V in the schematic.
    
    Change-Id: I12e055a39ff6100300c3d285899b8d6239e3773d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50356
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4164
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8a0cb8de65572d6cb40cd36f06fa2567953eb390
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue May 7 11:14:01 2013 -0500

    cbfstool: check potential microcode update earlier
    
    The update-fit command takes in a parameter for number of slots
    in the FIT table. It then processes the microcobe blob in cbfs
    adding those entries to the FIT table. However, the tracking of
    the number of mircocode updates was incremented before validating
    the update. Therefore, move the sanity checking before an increment
    of the number of updates.
    
    Change-Id: Ie8290f53316b251e500b88829fdcf9b5735c1b0e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50319
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4161
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 71b81bb64c44bc4150a1a19565a8732a361ae1f7
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue May 7 10:56:16 2013 -0500

    x86: call cbfstool update-fit when fit selected
    
    In order for the FIT entries to be populated in the table the
    update-fit command needs to be done on the coreboot image. That
    way the microcode entries are added to the table properly.
    
    Change-Id: I44595aee1ca710f4f04d482d8900cf95fbc1797f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50317
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4159
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 92e1f15175b3ab6fc50e3614c735d5e9cb3f3a22
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon May 6 14:02:27 2013 -0700

    lynxpoint: Expose ACPI Device for LP GPIO controller
    
    In order to probe the gpio-lynxpoint kernel driver the
    LP GPIO controller needs to be exposed as a specific
    ACPI device.
    
    This also allows the resources to be exposed to the OS via
    this device instead of the catch-all LPC device.
    
    Ensure the driver loads at boot:
    gpiochip_find_base: found new base at 162
    gpiochip_add: registered GPIOs 162 to 255 on device: INT33C7:00
    
    Also ensure the driver is visible in sysfs:
    $ cat /sys/devices/platform/INT33C7:00/gpio/gpiochip162/label
    INT33C7:00
    
    Change-Id: I9f79c008f88da9b67ed1cdfdb9d3a581ce8f05ff
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50215
    Reviewed-on: http://review.coreboot.org/4158
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f8b36501fd3f70569b15cc8dcaa9bcd8f76870af
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 2 14:02:28 2013 -0700

    Make ssize_t an actual ssize_t
    
    In the process of getting rid of compiler includes during in coreboot
    and libpayload, we defined size_t and ssize_t ourselves, using a GCC
    macro for size_t: __SIZE_TYPE__. Unfortunately, there is no
    __SSIZE_TYPE__, so we temporarily redefine unsigned to signed to make
    __SIZE_TYPE__ __SSIZE_TYPE__.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I4cf4eb0fdaa4db64277c2585fe2c1bdc0acdf02b
    Reviewed-on: https://gerrit.chromium.org/gerrit/49947
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4156
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 118b382e7d3d126da3ea4adff375cf3065df8734
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu May 2 18:23:24 2013 -0700

    call fill_lb_framebuffer() earlier
    
    fill_lb_framebuffer() now sets the framebuffer pointer according to
    the EDID information, so it must be called before setting the tag
    and size.
    
    (credit to rminnich for this, I'm just uploading it)
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    
    Change-Id: I5ac783fa3a776eee504d39889284041d1dc2c92a
    Reviewed-on: https://gerrit.chromium.org/gerrit/50012
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: David Hendricks <dhendrix@chromium.org>
    Tested-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4155
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1d048ca56080488b525077c99f94cf478efa43ed
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 1 11:30:24 2013 -0700

    lynxpoint: Move ME lock down to ramstage
    
    Now that we have RW ramstage we don't need to have the
    management engine lock down step done in a final SMM.
    
    ME: mkhi_end_of_post
    ME: END OF POST message successful (0)
    PCI: 00:16.0: Disabling device
    
    Change-Id: I9db4e72e38be58cc875c1622a966d8fcacc83280
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49757
    Reviewed-on: http://review.coreboot.org/4153
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 144f7b29ad995da897ec6c6ee4f87bed2ec7d28e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 1 11:27:58 2013 -0700

    lynxpoint: Add missing ME MBP entries
    
    There were two undefined MBP types that are now defined.
    These include NFC status and some interesting timing data.
    
    ME: Wake Event to ME Reset:      6 ms
    ME: ME Reset to Platform Reset:  7 ms
    ME: Platform Reset to CPU Reset: 51 ms
    
    Change-Id: I67bf1f303f3c32497041e64c40eb9ccb6a63d88a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49756
    Reviewed-on: http://review.coreboot.org/4152
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 764d009a615a3c1bdc42aef5506fc9b199bf5047
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed May 1 13:41:44 2013 -0500

    lynxpoint: export mem console pointer in ACPI
    
    Instead of having an OS re-parse cbmem book-keeping records
    for the cbmem allocator just to get the console buffer export
    the pointer to the memory console directly in a field named 'CBMC'.
    This field lives in the GNVS table.
    
    Change-Id: Ief0c4da7b18df66feb9c816c9f4abdf5a72bd3a4
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49764
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4149
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8f4baece7acc3e0ee2e3f04a181ce51b59ec4667
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Apr 25 17:21:58 2013 -0700

    elog: Make sure the elog data structures are initialized in elog_clear.
    
    If elog_clear is called before other elog functions, for instance if it's
    called through an SMI immediately after the system boots, then the elog data
    structures won't have been set up and the system will go off the deep end.
    This change adds a call to elog_init to elog_clear to make sure things things
    are always initialized before we start using them.
    
    Before this change, this command would cause
    the system to lock up if run immediately after boot:
    
    echo 1 > /sys/firmware/gsmi/clear_eventlog
    
    After this change, that results in the log being cleared correctly.
    
    Change-Id: I45027f0dbfa40ca8c581954a93b14b4fedce91ed
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49303
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4144
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5cf34ce02a73d7a455626eaa8a6b7aa69127cca7
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Apr 26 10:41:33 2013 -0700

    lynxpoint: Updates to power management and clock gating
    
    Slight tweaks found when looking at latest ref code when
    investigating package C-state issues.
    
    A few bits in the clock gating register don't match the
    documentation and are also cleaned up.
    
    Change-Id: I36ced7280c160b114c70b2eeafc8b24813ff2f6a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49330
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4142
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4d7a4c59dea4cc5f31d9bdd8163f3e0c925b1e90
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Apr 23 10:25:34 2013 -0500

    x86: use proper types for interrupt callbacks
    
    The mainboard_interrupt_handlers() argument for the function
    pointer was using void * as the type. This does not allow the compiler
    to catch type differences for the arguments. Thus, some code has been
    committed which violates the new interrupt callbacks not taking any
    arguments. Make sure the compiler provides a type checking benefit.
    
    Change-Id: Ie20699a368e70c33a9a9912e0fcd63f1e6bb4f18
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48970
    Reviewed-on: http://review.coreboot.org/4141
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 454744fd8665eba8721adcd6d84e74c17f8b2b42
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Apr 23 15:23:15 2013 -0700

    Unify and clean up remaining INT15 handlers
    
    Some handlers still had 2 variants, others were
    incorrectly guarded by CONFIG_ variables. This
    patch straightens them out.
    
    This does not touch the siemens/sitemp_g1p1 which
    provides an interestingly complex solution for the
    int15 handler.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I5d74fdf7c2ab1faa96ebc2b5ca5c69398449b069
    Reviewed-on: https://gerrit.chromium.org/gerrit/48979
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4140
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 98e4d8aabb7c42115682b18ef5740e944e9a03a1
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Apr 11 22:44:37 2013 -0700

    ARM: Update the size/location of the coreboot tables so we can boot again
    
    Change-Id: I3235f42c7faaf28a63455162ea55dc1a6bebd1f5
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-by: Hung-Te Lin <hungte@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48290
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Tested-by: Gabe Black <gabeblack@chromium.org>
    Commit-Queue: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/4128
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 19afe8de6d6f2e5e3140a4a21fb450c9867fbe97
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Nov 26 14:53:42 2012 -0800

    butterfly: Log EC shutdown reason in ELOG
    
    The EC saves its last "shutdown reason" for the system in EC RAM
    that we can read back and log on boot.
    
    The decode for the "reason" field will be added to mosys.
    
    Change-Id: I834d39122e45262ef8e7ba59201accbee5857aac
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48323
    Reviewed-by: David James <davidjames@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4127
    Tested-by: build bot (Jenkins)

commit 8c5947709a1d9e72d6ce17c48068b38afcb81967
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Apr 19 14:22:29 2013 -0700

    cbmem utility: compatibility with older coreboot versions
    
    Commit b8ad224 changed the memory address in lb_cbmem_ref coreboot
    table entries from a pointer to a uint64_t. This change was introduced
    to make the cbmem utility work on both 32bit and 64bit userland.
    Unfortunately, this broke the cbmem utility running on older versions
    of coreboot because they were still providing a 32bit only field for
    the address while the cbmem utility would now take the following 4
    bytes as upper 32bits of a pointer that can obviously not be
    mmapped. This change checks if the size of the lb_cbmem_ref structure
    provided by coreboot is smaller than expected, and if so, ignore the
    upper 32bit of the address read.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: If4c8e9b72b2a38c961c11d7071b728e61e5f1d18
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4139
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fe8290de22562251ef94fdd09c6577ae3ede1c44
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Apr 23 15:00:02 2013 -0700

    Fix VGA option rom INT15 handler
    
    The format of this function changed but was not updated in
    all mainboards.  This fixes all Sandybridge/Ivybridge boards.
    The int15 handler no longer takes a regs structure as an
    argument and instead uses global variables.  The yabel interface
    is now similar enough that we can drop the duplicate handler.
    
    Change-Id: Icdaae4d6d50884f6d7bce7a167d48cb1d4807010
    Reviewed-on: https://gerrit.chromium.org/gerrit/48969
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4135
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 6119bea233a29d806ae77b44177feeba7010bfdd
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Mar 29 13:24:29 2013 -0700

    armv7: import updated cache/MMU stuff from coreboot
    
    This imports the cache/MMU code from coreboot as of 1877cee.
    
    Change-Id: I97ec8b9640921a94a4b27d89e4ae6185e9f96f18
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48288
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4134
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7905f9254ebc865cbd78e4ade3e5d795957be4a6
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Mon Nov 25 11:20:20 2013 +0100

    qemu: cirrus native video init
    
    Recent commit proposal by Ron Minnich proposes to move to native gfx init for
    qemu. Unfortunately we didn't have native init for default qemu video (cirrus)
    Here is one extracted from GRUB one which I wrote couple of years ago.
    
    Change-Id: Icb89cf918ef5d276bcc703c48c568e7b9c1be756
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4270
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c6f6be0929ccef4c551f9640300972e7bc8600ec
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 12 22:32:08 2013 +0100

    Support for nehalem northbridge
    
    Including raminit
    
    Change-Id: If1dd3855181481b8b928adf0fdb40b29d15897db
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4044
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 888d559b0373cb956314b8087439378c14a16918
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Nov 13 17:53:38 2013 +0100

    Support for Ibexpeak southbridge
    
    Part of X201 port.
    
    Change-Id: If17d707004aba9f08459dbd8f3a146fa3c076aa9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4052
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit cae09e0bbe61417667685c93cccc761c7d727daf
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Nov 19 17:42:41 2013 -0800

    bochs: add support for native graphics
    
    Per our discussions with Gerd, qemu will now always do native graphics
    on coreboot. The VGA BIOS capability is not needed and will no longer
    be supported. Attempts to build without native graphics will result in
    an error.
    
    This code builds for both x86 emulation targets. I'm hitting an issue
    testing that is unrelated to coreboot; if someone can test, that
    would be helpful. Be sure to start qemu with -vga std.
    
    We also add a test for the PCI BAR being zero and return silently if it
    is.
    
    Change-Id: I66188f61e1bac7ad93c989cc10f3e0b55140e148
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/4258
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>

commit 969553e574310beadc836fb1eb0c139585ddb8ce
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Nov 14 19:08:38 2013 +0100

    Add declaration of dock registers 1, 2 and 3.
    
    Needed to make dock work on X201.
    
    Change-Id: Id0b32266cacf04bb48530bedf50818c268f947ec
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4081
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 655ac2420d9d844b2c58269daf04e2c1dd60cb39
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Nov 24 19:56:21 2013 -0600

    google/butterfly: Declare mrc_scrambler_seed_chk in cmos.layout
    
    SandyBridge raminit uses this CMOS option. If it is not declared, the build
    fails when USE_OPTION_TABLE is selected.
    
    Change-Id: I1ba1f994d4ea3824dc66e8f35d0b5b24b88d4dd6
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4269
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a0ca7d045871acef0649d7b74e29eb70008a2326
Author: mrnuke <mrnuke@nukelap.gtech>
Date:   Sun Nov 24 18:29:58 2013 -0600

    .gitignore: Properly ignore KDevelop files
    
    Change-Id: I1410242e4d1995baedd5d3a001f86619e729db98
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/4268
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 5183ab64b5896133b1e02ed4687e27aaa41877e7
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Nov 24 09:41:32 2013 +0100

    no-car/cbmemc: Fix compilation
    
    the part !CAR && PRE_RAM is obviously meant as dummies. Unfortunately
    cbmemc_tx_byte has wrong number of arguments and hence causes compilation
    failure.
    
    Found out when compiling for vexpress-a9.
    
    Change-Id: Ic84d142bac5c455c2371fbc9439c898de04a974e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4267
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 990555b0efafa2860888eeb335477720f464acb2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri May 10 11:00:07 2013 -0700

    haswell: Update GT PM register value
    
    This was changed to 0x80000000 in SA BWG 1.5.0.
    
    Change-Id: Ic6773f45057f3eb93b2d93ee543e3db77fccf805
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50852
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4166
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit fd0bc14844d7ef96781404e4d0a14e522e4f5827
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu May 9 07:41:58 2013 -0700

    haswell: Update ULT microcode to 0x10
    
    [    1.503741] microcode: CPU0 sig=0x40651, pf=0x40, revision=0x10
    [    1.510483] microcode: CPU1 sig=0x40651, pf=0x40, revision=0x10
    [    1.517213] microcode: CPU2 sig=0x40651, pf=0x40, revision=0x10
    [    1.523947] microcode: CPU3 sig=0x40651, pf=0x40, revision=0x10
    
    Change-Id: I19ef40b636eebeb8cc29cc0404abbe263ec8eaa7
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50655
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4165
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1c097107099201e60be5745b839268752878dc34
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 7 13:19:56 2013 -0700

    haswell: Remove limit on package C-state
    
    With the XHCI controller enabled we no longer hang the
    system when dropping into a package C-state so remove
    the code that was disabling it.
    
    Change-Id: Icd60488fd2506dac04fb6ec96a77bec265b10d8c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50355
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4163
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 58181124f656af4362395765933ab7747aaba8b4
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 7 11:31:33 2013 -0700

    haswell: Update ChromeOS ACPI GPIO package
    
    The chromeos_acpi driver sysfs naming is not what
    crossystem expects if there is just one entry in the package
    because it does not add a ".#" suffix in that case.
    
    Specify all the expected GPIOs on wtm2 as undefined, which
    should be 0xFF and not 0x00 becuase 0 is a valid GPIO.
    
    Change-Id: I9b17e9bab94219695e65b17914c84acf02a0983b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50337
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4162
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 5b4178575f65715c168989bf3e0719d99fccd366
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue May 7 11:05:06 2013 -0500

    haswell: split microcode between ULT and non-ULT
    
    The current microcode blobs contain both ULT and non-ULT
    revisions. Only include one or the other based off of the
    CONFIG_INTEL_LYNXPOINT_LP Kconfig option.
    
    Change-Id: I3e4e41d4cd727b1a974361fb469267e6f6022d5a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50318
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4160
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 8e0cd496a15b1e20571806468e7d2a9a5b1c9890
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed May 1 13:29:45 2013 -0500

    haswell: enable monotonic timer
    
    For all the current haswell boards enable the monotonic timer.
    The ULT boards use the 24MHz MSR while the non-ULT boards use the
    local apic.
    
    Change-Id: I8b19f526a5a49e8467f296c566a2c4263bc5a863
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49763
    Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/4148
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 3e996a55cd7b6a3ff9a1b5f16fd3c2247ff6bda8
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Apr 30 11:09:57 2013 -0700

    haswell: Update ULT microcode to rev 'a'
    
    Change-Id: I714208da23bf7cbd1232874c05ad3100551f5f7c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49647
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4146
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit e1e87e0ed6280f168abd92edcd692aec4ead8fe8
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Apr 26 10:35:19 2013 -0700

    haswell: Configure PCH power sharing for ULT
    
    This reads PCH power levels via PCODE mailbox and writes the
    values into the PMSYNC registers as indicated in the BWG.
    
    Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49329
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4143
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit f24262d01822bd8634e44b5aab19dafe7e04ae72
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 10 14:59:21 2013 -0500

    haswell: calibrate 24MHz clock against BCLK
    
    On haswell ULT systems there is a 24MHz clock that continuously runs
    when deep package c-states are entered. The 100MHz BCLK is shut down
    in the lower c-states. When the package wakes back up a conversion
    formula needs to be applied. The 24MHz calibration is done using the
    internal PCODE unit.
    
    Change-Id: I6be7702fb1de1429273724536f5af9125b98da64
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48292
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4136
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 7c351316429f8b991df7ea233a5528f4efb3b8e0
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 10 14:46:25 2013 -0500

    haswell: configure c-states
    
    The c-states are configured according to the BWG, however the
    package c-states are disabled as they currently cause platform
    instability. The exposed ACPI c-state to processor c-state mapping
    are as follows for ULT boards:
    	ACPI(C1) = MWAIT(C1E)
    	ACPI(C2) = MWAIT(C7S long latency)
    	ACPI(C3) = MWAIT(C10)
    The non-ULT boards have an expoed c-state mapping:
    	ACPI(C1) = MWAIT(C1E)
    	ACPI(C2) = MWAIT(C3)
    	ACPI(C3) = MWAIT(C7S)
    
    Included in this patch is removing the updating of current limit
    registers as some of the MSRs are different and the proper values
    are currently unknown. Lastly, some of the MSRs were renamed to
    match the BWG.
    
    Booted 3.8 kernel and used powertop to note package, core, and acpi
    c-state residency.
    
    Change-Id: Ia428d4a4979ba3cba44eb9faa96f74b7d3f22dfe
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48291
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4133
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 15de7cb4224b6add9a65d083e9a2e8484ae511b8
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Apr 23 13:44:37 2013 -0700

    lynxpoint: Add a function to set an individual GPIO
    
    This will be used in a later commit to do some specific
    power sequencing.
    
    Change-Id: Id7f033bb80aed915c2498ea910cb3ac7290da37f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48947
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4137
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 55ad9724322739a862745a71806af8d9a870601b
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Apr 23 13:43:23 2013 -0700

    lynxpoint: Rework LP GPIO handling
    
    This adds some macros for the common GPIO defines and drops
    the gpio number definition from each entry.  The end result
    is much easier to read.  The wtm2 mainboard gpio list is modified
    to use this.
    
    Also fix a bug in the LP version of get_gpio() that was always
    returning zero due to a miscompare.
    
    Change-Id: I143e5aee412af1eda84e35f8026f31cf13df508e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48946
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4138
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 0edc22490a643c4b4c6181c42eed375485f9e0e4
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Apr 29 15:04:30 2013 -0700

    smi: Update mainboard_smi_gpi() to have 32bit argument
    
    With the LynxPoint chipset there are more than 16
    possible GPIOs that can trigger an SMI so we need
    a mainboard handler that can support this.
    
    There are only a handful of users of this function
    so just change them all to use the new prototype.
    
    Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49530
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4145
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit a7e9a9b75f806b290ea4fbe22a03e3489b1931f1
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 28 07:54:15 2013 -0700

    slippy: Add panel power sequence timings
    
    These are placeholder values until we can configure for
    the exact panel.
    
    Change-Id: Ibe88cc3588947366eb1728e5b3e1ab8c8be6dfe8
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56807
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4196
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit d80cd2ad80b2b9debfce1fce5f94c773cb51c8cc
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 22 16:13:49 2013 -0700

    slippy: Clean up for easier porting
    
    Minor tweaks to variable names in the slippy mainboard
    that make it easier to base a new board from without
    as much renaming.
    
    Also properly set up the thermal variables for the
    thermal zone that is defined in ACPI instead of using
    the generic setup from WTM2.
    
    Change-Id: I752c1a50bfdc06b6ddad95bd1331c6870b9f9df2
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56328
    Reviewed-on: http://review.coreboot.org/4183
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit cfe0235c6fb5574b54139c6e7bd31da974e4ef23
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 21 10:11:07 2013 -0700

    slippy: Run EC init as part of mainboard init step
    
    This will log and clear EC events so they do not take effect
    when the SMI handler is enabled.
    
    Change-Id: I5ef563f7cedc8977410cc3f69e2655fc4e14c9eb
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56055
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4178
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 90bfbfa9bae901d006b5933d26fad3c7185170fc
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 21 08:05:39 2013 -0700

    slippy: Update interrupt routing
    
    The SerialIO devices have specific requirements for PCI
    interrupt mode to use PIRQ{E,F,G,H} that are not being met.
    
    D21:F0 uses PIRQE, which must not be shared with other PCH
    D21:F1-F6 share PIRQF, which must not be shared with other PCH
    D23:F0 uses PIRQH, which must not be shared with other PCH
    
    - Fix D20IR -> D20IP typo
    - Remove D25/EHCI2 as it does not exist
    - Reorder other interrupts to clear PIRQE/PIRQF/PIRQH
    
    Check device interrupts in the kernel
    
    0:      IO-APIC-edge    timer
    1:      IO-APIC-edge    i8042
    8:      IO-APIC-edge    rtc0
    9:      IO-APIC-fasteoi acpi
    16:     IO-APIC-fasteoi ath9k
    18:     IO-APIC-fasteoi i801_smbus
    19:     IO-APIC-fasteoi ehci_hcd:usb1
    21:     IO-APIC-fasteoi i2c-designware-pci--1, i2c-designware-pci--1
    40:     PCI-MSI-edge    PCIe PME
    41:     PCI-MSI-edge    i915
    42:     PCI-MSI-edge    ahci
    43:     PCI-MSI-edge    xhci_hcd
    44:     PCI-MSI-edge    snd_hda_intel
    
    Change-Id: Id4c08d11d2860f270c6387138acdc7d3d83a85b5
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56028
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4176
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit a54adc1bc78a4caa814be8e5a69d48e1f181952a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed May 15 17:02:23 2013 -0700

    slippy: set PWM values
    
    The dev screen was not displaying properly. With the
    PWM values programmed the screen displays correctly.
    
    Change-Id: I82b56a92e4168022082a2e519026977ee2ae0c9e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/51472
    Reviewed-on: http://review.coreboot.org/4172
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 270881af741eaeae29a084bad351c7182bfde275
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 15 15:05:38 2013 -0700

    slippy: Put SerialIO devices in PCI mode
    
    The device at function 0 also needs to be enabled
    or the kernel will ignore all other functions.
    
    00:15.0 DMA controller: Intel Corporation Lynx Point-LP Low Power Sub-System DMA (rev 03)
    00:15.1 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #0 (rev 03)
    00:15.2 Serial bus controller [0c80]: Intel Corporation Lynx Point-LP I2C Controller #1 (rev 03)
    
    Change-Id: I0e1bc7bb719756496c46664d66dc1b1cf2f4d1ba
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/51370
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4171
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit ffa0fa4660c8c9e605773ce9ad21d5bef209613d
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri May 10 11:00:56 2013 -0700

    slippy: Add EC to the device tree
    
    This lets the keyboard init get called properly.
    
    Change-Id: I11ffb459907188a58149d28a6ade0b7de7d15d08
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50853
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4167
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 4d019c9ee2d5d25cc8eac2b97586f761b79e49b2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri May 3 15:59:59 2013 -0700

    slippy: Update SPD
    
    Change-Id: Iae0258ceb0424df0937d2cec7dd885060f5b4e48
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50082
    Reviewed-on: http://review.coreboot.org/4157
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit f31fcbc832c45294f11541cd96a973d43108b1fa
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu May 2 10:40:49 2013 -0700

    slippy: Add SPD data for on-board memory
    
    Change-Id: I7a617fe06d23b906f718ed30f1378f7d220b2799
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49911
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4154
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit a103d0715c178d9f68720dfc24d1ba880c39590c
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 1 11:12:53 2013 -0700

    slippy: Prepare LPC IO decode ranges for EC
    
    - 0x200-0x208 for host command window
    - 0x800-0x8ff for host command arguments and parameters
    - 0x900-0x9ff for exported EC memory map
    
    Change-Id: I064b969843ef0d3c602793d1cb3d82715775c05e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49755
    Reviewed-on: http://review.coreboot.org/4151
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit e820a6ce833aacb0cf9500809b03493a01dcf9c0
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed May 1 11:11:10 2013 -0700

    slippy: Add iSSD power sequencing
    
    Without an LM10506-A the power sequencing for this
    part needs to be done manually using GPIOs.
    
    Change-Id: I842152e5f7c30c8dbe37df0c344935a659eb2887
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49648
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4150
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cf72d91613eef7a2ff7ed2145cd8baefff35eb16
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Apr 29 15:10:31 2013 -0700

    slippy: Initial mainboard commit
    
    Change-Id: I33876b90902d4a08d760eb482b08ba41be6e3695
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/49531
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4147
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 7797ffa1bebfefde0076383a12f620897e5ef81a
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Wed Nov 20 15:09:23 2013 +0800

    amd/olivehill: Fix the double spaces in copyright header
    
    Change-Id: I1bdc52efc827c331c53b97d2b96edafc518d05bf
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/4259
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 6a89cf3ef305a82dbc097d73693a58f687c4b19a
Author: Bill Richardson <wfrichar@chromium.org>
Date:   Tue Jul 10 17:54:59 2012 -0700

    Honor vboot's request to load the VGA option ROM
    
    This removes an earlier patch that caused the VGA option ROM to be loaded by
    coreboot even in normal mode when it isn't needed.
    
    Change-Id: Ie0a331a10fff212a2394e7234a0dbb37570607b7
    Signed-off-by: Bill Richardson <wfrichar@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48173
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/4125
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 047c98a2c1b9a9dfc4568b1b1471aab7cfcae606
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 21 10:46:28 2013 -0700

    libpayload: fix wrong endian assumption in sha1.c
    
    Not all platforms !x86 are big endian, hence actually look
    at the CONFIG_LITTLE_ENDIAN flag instead of CONFIG_ARCH_X86.
    
    Change-Id: Ibbd8f48b377a1121dd1e045834a94a2d67eda2ab
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/56066
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
    Tested-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/4236
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c6f0997ffcfc5c622c2901e95efb4ca97974aadd
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 8 01:31:44 2013 +0200

    Northbridge: i945: Native VGA init: print the GMA and GTT addresses
    
    The patch was made by Peter Stuge, I just split it
      and added a commit message.
    
    Change-Id: Ieaaaa2611f7bb8968f01b16daefe7e2afe870f72
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/4001
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 03e4ac6671e91a0180f6eec3db9f55a7c2adbba1
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 8 01:25:43 2013 +0200

    Northbridge: i945: Native VGA init: use UMA address
    
    The patch was made by Peter Stuge, I just split it
      and added a commit message.
    
    Change-Id: I4e88c26b70ea8cb249d7613c749b3edc5e3b5e7f
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/4000
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c882d93054f17439569bf64f9d13c9059e6a471e
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Oct 27 16:07:28 2013 +0100

    Lenovo X60: Native VGA init: Get rid of the memory corruptions.
    
    Without that fix the GTT points at 0x00000000.
    
    The patch was made by Peter Stuge, I just split it
      and added a commit message.
    
    Change-Id: Ia378b600ba2faf00d42635c6503b94ff0cb1bc8c
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/4002
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2186b6538ede48fbbf8a250b96e58780bfdae082
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sun Oct 27 15:50:02 2013 +0100

    lenovo/x60: native vga init: fix code style issues.
    
    Change-Id: I054edffbb38b13559da10180fc2c6cd9929ba162
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3999
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 33b09567d291d3e07429c94e38ec6210435c42c1
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Fri Oct 25 16:22:57 2013 +0800

    dmp/vortex86ex: Move DMP specific POST code defines into one file
    
    Move into src/cpu/dmp/dmp_post_code.h
    
    Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3989
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 099b914dcd63cb8c177fa1e981046cd25f4565f7
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sat Oct 26 22:35:46 2013 +0200

    lenovo/x60: export reboot_bits nvram configuration.
    
    This permits any software running after the ramstage to tell coreboot that the
      boot was successfull.
    
    Change-Id: I6b19160dcf1ea1948360db71d02e344a3bcb44ef
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3992
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f3c1c9b6ac73c7b5346d36ac06e5bf08244e1d82
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Nov 18 11:20:30 2013 +0100

    payloads/external/SeaBIOS/Makefile.inc: Remove empty lines at file beginning
    
    Change-Id: I3e6eba62b6790836edf9813c2a45c77390d8c078
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/4094
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 25b8b7b8813f849c132db597510c4d61c47566fa
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Apr 19 10:02:23 2013 -0700

    haswell: Put each logical processor in its own P-state domain
    
    The recommendation from Intel is to report each core as a
    separate logical domain in the _PSD table.
    
    This goes against the recommendation in the ACPI specification
    because all of these cores are on the same package and share a
    VR so they will do voltage transitions together.
    
    The reasoning is that with a larger number of logical processors
    the P-state often ramps too quickly resulting in higher power
    consumption.  By exposing each core as a separate domain the OS
    can manage them individually allowing the socket to select the
    optimum frequency.
    
    $ cat /sys/firmware/acpi/tables/SSDT > /tmp/SSDT
    $ iasl -d /tmp/SSDT
    
    Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00)
    {
      Name (_PSD, Package (0x01)
      {
        Package (0x05)
        {
          0x05,
          0x00,
          0x00000000,
          0x000000FE,
          0x00000001
        }
      })
    }
    
    Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00)
    {
      Name (_PSD, Package (0x01)
      {
        Package (0x05)
        {
          0x05,
          0x00,
          0x00000001,
          0x000000FE,
          0x00000001
        }
      })
    }
    
    Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00)
    {
      Name (_PSD, Package (0x01)
      {
        Package (0x05)
        {
          0x05,
          0x00,
          0x00000002,
          0x000000FE,
          0x00000001
        }
      })
    }
    
    Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00)
    {
      Name (_PSD, Package (0x01)
      {
        Package (0x05)
        {
          0x05,
          0x00,
          0x00000003,
          0x000000FE,
          0x00000001
        }
      })
    }
    
    Change-Id: I5ef41b6ead4d88e9ba117003293dbc629c376803
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48662
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4130
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 77647b33cf33e882a0a21f7d46c42b54945e8045
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Apr 19 09:47:58 2013 -0700

    haswell: Update microcode for ULT/40651 to rev 8
    
    $ cat /sys/devices/system/cpu/cpu*/microcode/version
    0x8
    0x8
    0x8
    0x8
    
    Change-Id: Id6491ae96c516ae0b55471e53f79f0407cf3ffdb
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48661
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/4129
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7a91816bdbccd488361356eb309e9afb0f02db22
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Apr 8 09:32:12 2013 -0700

    Fix compile error in chromeos by adding stddef.h
    
    Compile was failing with the following error:
    
    In file included from src/vendorcode/google/chromeos/vboot_handoff.h:22:0,
                     from src/vendorcode/google/chromeos/chromeos.c:22:
    vboot_reference/firmware/include/vboot_api.h:388:18: error: unknown type name 'size_t'
    src/vendorcode/google/chromeos/chromeos.c: In function 'vboot_get_payload':
    src/vendorcode/google/chromeos/chromeos.c:50:23: error: 'NULL' undeclared (first use in this function)
    
    Change-Id: I13f9e41ef6a4151dc65a49eacfa0574083f72978
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48289
    Reviewed-on: http://review.coreboot.org/4131
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d26558cf5b03074687b604937efa2ecdb0b1ac81
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Nov 14 18:56:45 2013 +0100

    Lenovo hotkeys support
    
    Implement proprietary lenovo ACPI hotkeys
    
    Change-Id: I36a6d3a280b0ac76d9ea063cdc10197a57e306f9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4055
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 219f068ae3522f52dfb09b1b2bc93cfbf21d5357
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Nov 13 18:24:04 2013 +0100

    Change EC GPE on X201
    
    X201 has GPE at 0x11 (17) instead of 28.
    
    Tested on X201.
    
    Change-Id: Ib6306e6f085c4f6811df0789aa402a0d6901ed13
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4053
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 617f853ae43ce1c15fbec1ecba2aa5624f6b4c7d
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Nov 23 14:46:34 2013 +0100

    lib/coreboot_table: set type and size of framebuffer tag after fill_lb_framebuffer
    
    When testing Ron's patch on qemu I found out that fill_lb_framebuffer
    overwrites size and tag fields. We need either to fix/check all
    fill_lb_framebuffer implementations or write tag/size after fill_lb_framebuffer.
    I prefer later as it's more robust.
    
    Change-Id: I98f5bac14f65fb4d990cb21426d402b27f2e8a48
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4263
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 71f35ebdaab56e4ff1d4d882d2cd4f29bda1aacc
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 12 23:32:52 2013 +0100

    Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.
    
    2065x is with nehalem and not sandybridge.
    
    I don't care much eitherway but it clears some confusion.
    
    Change-Id: Ib2b8e570b830a12ed8d0d313ee4eb56755796d4b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4046
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit e2b6795e046894487863e4bc9e29aa075dfcc3f6
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Nov 14 19:09:42 2013 +0100

    Call X201 dock hooks in EC code
    
    Unlike on X60/T60 dock has to be inited at the same time as EC.
    
    Change-Id: If6eb3140c871859ce99027a50908f72bcc560243
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4082
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 75b90a1f50f15b8ccb814d005c840d189d512f26
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Nov 14 18:49:26 2013 +0100

    Remove MRC variables from 2065x CAR init.
    
    2065x boards don't use MRC. And the space in question isn't used either.
    
    Read number of variable range MTRRs from MSR rather than hardcoding it.
    
    2ff is still zeroed out as unless you zero-out undocumented bits as well
    boot fails.
    
    Tested on Lenovo X201.
    
    Change-Id: Ic574193094e7d27c2d6a4d7d3e387d989578532e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4080
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 533ad1058363a14f0ad2f4c7b0a30b940b757ef5
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Nov 14 19:23:30 2013 +0100

    Don't wait on 2065x
    
    The mdelay is not necessarry on 2065x.
    
    Tested on X201 that it works without delay.
    
    Change-Id: Ida9e85be7c214f3ba4c9476b5d8a0351e7980e5e
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4083
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 87bdd86fe0ac0dfb687ca42ff25c95c40f7bf8c4
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Mon Nov 18 10:34:06 2013 +0800

    AMD f15tn, f16kb: Remove CDIT table and DMI table
    
    On AMD Trinity and Kabini boards errors similar to the following are
    shown.
    
    	ASSERTION FAILED: file 'src/mainboard/asrock/imb-a180/agesawrapper.c',line 431
    	DmiTable:100123f7, AcpiPstatein: 10010129,AcpiSrat:0,AcpiSlit:0, Mce:10010de9,Cmc:10010eab,Alib:1002111c, AcpiIvrs:0 in
    	agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5
    
    The reason is that on f16kb boards, the CDIT and DMI table are not
    created. On f15tn boards, only the DMI table is not created.
    
    Until the root cause is found, disable the table generation to remove
    the errors.
    
    Thanks to Wei Hu for debugging and reporting this issue on the list [1].
    
    [1] http://www.coreboot.org/pipermail/coreboot/2013-November/076607.html
        CDIT table is not created
    
    Change-Id: I837e3c322bb5331a9b950a72397796a60642c3f3
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/4092
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit fe6bdd96d892c2c7c3c9047259dfd38fa9bfe60f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 19 18:01:03 2013 +0100

    Fix error message on wrong compiles of 2065x
    
    Current error message refers to sandybridge chipset. Instead error
    should be that 2065x needs Ibex Peak.
    
    Change-Id: I8cc8a34f496aec7af0ce95b4b65fd25e165f43fb
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4202
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 38c78889c5dfeda842e3dd8b8698549cd5e71021
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Nov 12 16:46:47 2013 +0100

    Asus F2A85-M: Fix S3 memory power cut-off
    
    The power to memory is lost during the the suspend, activate
    the 3VSBSW# which switches the power during S3 suspend sequence.
    
    As a result resuming from suspend to RAM works now, but now the
    GPP ports of the Hudson southbridge are gone after resume from S3.
    The devices 15.0 and 15.1 are disabled (decode as ffff) and
    therefore anything behind them too [1].
    
    [1] http://www.coreboot.org/pipermail/coreboot/2013-November/076620.html
        fam15tn hudson PCIe GPP ports off after resume
    
    Change-Id: Id953313ee4400a03a2ad8ca09e39a5e0d5f92524
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/4041
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 113a3668489507f5b14ccea4daae0216021bf228
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Nov 14 12:10:08 2013 +0100

    Add GRUB2 payload to build system
    
    Since a long time GRUB 2 is a viable payload alternative to SeaBIOS and
    FILO. So make it easy for coreboot users to use GRUB 2 as a payload by
    integrating it into coreboot’s build system, so it can be selected in
    Kconfig.
    
    As the last GRUB 2 release 2.00 is too old and has several bugs when
    used as a coreboot payload only allow to build GRUB 2 master until a new
    GRUB release is done. The downside is, that accidental breakage in
    GRUB’s upstream does not affect coreboot users.
    
    Currently the GRUB 2 payload is built with the default modules which
    results in an uncompressed size of around 730 kB. Compressed it has a
    size of 340 kB, so it should be useable with 512 kB flash ROMs.
    
    Tested with QEMU.
    
    Change-Id: Ie75d5a2cb230390cd5a063d5f6a5d5e3fab6b354
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4058
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c37b05c41339acbeee00bd65c13b8a97b16854ce
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Nov 11 15:16:53 2013 +0100

    nvramtool: write size field more obviously
    
    The field wasn't initialized in RAM first and later overwritten in a somewhat
    twisted way (that relied on the size field coming after the tag field in the
    struct).
    
    Change-Id: Ibe931b297df51e3c46ae163e059338781f5a27e2
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4087
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit ef4020957e009f2861522549927069d6e9d39959
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Mon Nov 11 10:36:28 2013 -0800

    cbfs: 64-bit cleanups
    
    cbfs used u32 in a number of cases where uintptr_t was
    correct. This change builds for both 64-bit and 32-bit
    boards.
    
    Change-Id: If42c722a8a9e8d565d3827f65ed6c2cb8e90ba60
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/4037
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 7fda0e8e61682e66c956d3759a0ce39486dad747
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Sun Nov 17 11:07:25 2013 -0800

    cbfs: remove unused code and prototype
    
    The code is wrong (it's calling ntohl on an entry point that is actually
    already le due to an old cbfs bug) and nothing calls it any more anyway.
    
    Change-Id: Ief2c33faf99e3d2fc410524a5aae7bde378f088b
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/4090
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 72f15bd2be37f5c28dae044aeec04aabb0db7326
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Sun Nov 17 13:49:42 2013 -0800

    cbfstool: add a constant for the aarch64
    
    Change-Id: Ide2c8b778447de66d95bd8c55b378aa2051ac2a0
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/4091
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit e851a685ef9d6280982465b319971e4252859227
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Wed Nov 13 12:56:30 2013 +0100

    qemu: set smbios entries from fw_cfg
    
    Qemu makes the guest uuid (qemu -uuid $uuid) available
    to the guest via fw_cfg.  Other smbios fields can be
    configured in qemu using the -smbios command line
    switch (check the qemu manpage for details).
    
    This patch adds coreboot support for this, so the
    values provided by qemu will actually show up in the
    smbios table.
    
    Change-Id: Ifd9ae0d02749af4e7070a65eadbd1a9585a8a8e6
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/4086
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 06262743c76102083287f5085380138164117bc7
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Wed Nov 13 13:37:23 2013 +0100

    smbios: make manufacturer, product_name and uuid runtime settable
    
    Make manufacturer, product_name and uuid smbios fields (type 1)
    configurable at runtime, simliar to version and serial number.
    
    Change-Id: Ibc826225e31fa42aa944fa43632dd6a406d5c85d
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/4085
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit a4affe17f1a31946841b6fa425d0ef4b3ea00855
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Nov 12 18:17:19 2013 -0800

    board_status.sh: trivial cosmetic changes toward the end
    
    This moves an ugly comment closer to where it is applicable and also
    adds a visual break between the commands which gather data and the
    part of the script that finishes up. I'm usually not fan of banner
    comments, but it seemed to help in my totally subjective opinion.
    
    I was thinking about how to break the part that uploads results into
    a separate function, but there are enough variables that are re-used
    from earlier parts that the tradeoff probably isn't worth it.
    
    Change-Id: If888329911c4de3b907cdf5973695c707bbb02fe
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4051
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 406ce8a06e82dc17c7153c02585aa3e8f885561f
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Nov 12 18:10:23 2013 -0800

    board_status.sh: pass filename as an arg to command wrappers
    
    This allows the command wrappers to delete files if the command
    fails. In particular, it delets empty or otherwise useless files
    that are generated if a non-fatal command fails.
    
    Change-Id: If26d7b4d7500f160edd1cc2a8b6218792fefae8b
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4050
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f8b90e4622533947dbc21c55b21ea932eb7420c7
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Nov 12 17:24:42 2013 -0800

    board_status.sh: add support for non-fatal commands
    
    This adds cmd_nonfatal() for commands which are considered
    non-essential and can be expected to fail safely. This can be used,
    for example, to gather data that is generated when using non-standard
    utilities or coreboot config options.
    
    Change-Id: Ie43944d2eb73f9aae1c30c3a204cfc413e11d286
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4049
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1fc65f76f46c4ebef3bfd716908855f3cfb98d89
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Nov 12 16:49:45 2013 -0800

    board_status.sh: move show_help()
    
    This is really only a cosmetic change, but is intended to make it
    slightly easier to remember to update the help menu whenever
    options change.
    
    Change-Id: I58b5012309229d08da138a01c7cd1c5096423179
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4048
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 16955fd6654cc50ce8776c6c176bacd9316585f5
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Nov 12 16:45:37 2013 -0800

    board_status.sh: Make clobber option use 'C' instead of 'c'
    
    Clobbering output is only really useful when debugging the script.
    Since we're only using short options, let's save 'c' for something
    more important.
    
    Change-Id: If87a70fdc0cd006818d1736c40f9984dfec663a9
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4047
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1b6e7a67489138848edfc641522297b0263b739c
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Nov 11 18:44:05 2013 -0800

    Updates to the board status script
    
    This is the first major re-work for the board status script.
    Summary:
    - Added a command to the getrevision.sh script to retrieve tagged
      revision.
    
    - Results are placed in a dynamically generated temporary location.
      This makes it easy to do multiple trial runs and avoids polluting
      the coreboot directory.
    
    - Results are stored in a directory with the following form:
      <vendor>/<mainboard>/<tagged_revision>/<timestamp>/
      Vendor and mainboard are obtained from CONFIG_MAINBOARD_DIR so that
      hierarchy is consistent between coreboot and board-status.
    
    - The results directory is used as the commit message.
    
    - board-status repository is checked out automatically if results are
      to be uploaded.
    
    TODO:
    - Add ability to run commands which may fail. Currently we assume
      any failure should terminate the script, but some commands can be
      made optional.
    
    Successfully uploaded first result to board-status repository. See
    http://review.coreboot.org/gitweb?p=board-status.git;a=summary .
    
    Change-Id: Icba41ccad4e6e6ee829b8092a2459c2d72a3365b
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4039
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0dde01cad1c0b1422c845fc201733be559004fb7
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Nov 11 15:57:09 2013 +0100

    romcc: Fix off-by-one
    
    Arrays are indexed 0..(number_of_element-1).
    
    Change-Id: I2157e74340568636d588113d1d2d8cae50082da2
    Found-by: Coverity Scan
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/4089
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit d69da8475e9794cfd8580457c63dafb8f5d240ed
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Thu Jul 25 15:59:07 2013 +0200

    qemu: load acpi tables from fw_cfg.
    
    Starting with release 1.7 qemu provides acpi tables via fw_cfg.  Main
    advantage is that new (virtual) hardware which needs acpi support
    JustWorks[tm] without having to patch & update the firmware (seabios,
    coreboot, ...) accordingly.
    
    So if we find acpi tables in fw_cfg try loading them, otherwise fallback
    to the builtin acpi tables.
    
    Change-Id: I792232829b870ff6ed8414a3007e0af17f6c4223
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/4040
    Tested-by: build bot (Jenkins)

commit 55b059385a2158d14ad01621c7b5eb8091455eb0
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Nov 13 23:05:23 2013 +0100

    Lenovo T60/X60: cmos.layout: Replace tabulators with spaces for consistency
    
    Change-Id: Iec0abae8a4b18ac737e9ebb3eac219182729be0f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/4057
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d8cfd23f6ab37ae68366625e144136392384638f
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Nov 12 21:59:10 2013 +0100

    intel/2065x: Use TSC for udelay()
    
    For the ram init of Intel Nehalem ram init we need a udelay implementation.
    Use common TSC framework for it as Intel Haswell already does.
    
    Change-Id: I360a6db1ec1ba32c92698a7d6f6968c93ead5c52
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/4043
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit c5e947ef17d98722d27a67d65a84a28fd5861dbd
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Nov 11 18:43:39 2013 -0800

    rename status-related stuff to board_status
    
    This just moves stuff to be more clear about the purpose of
    the script. Other suggestions are welcome.
    
    Change-Id: Ic6095fd4eb347daa5a03eff21b5952d2d42a6bfd
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4038
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 7b4a99c66569c74243f44ec7c09f0fd6e5f6802e
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Tue Nov 5 13:58:50 2013 +0800

    AMD Hudson: Move function s3_resume_init_data to southbridge
    
    Besides the AGESA static settings, the settings in mainboard/buildOpt.c also
    change the final configuration. We need to make sure the settings in FchParam
    in resume stage are the same as they were in cold boot stage, otherwise the
    board can not wake up more than once.
    
    Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180.
    
    (USB keyboard doesn't work when board wakes up. It is not introduced by this
    patch. It needs more debugging.)
    
    Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/3932
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit baa782020e9d2d0ce7b6fd1c7c43411c9aa2b900
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Wed Nov 6 14:36:17 2013 +0100

    qemu: load e820 from fw_cfg
    
    qemu 1.7+ provides a fw_cfg file named "etc/e820" with e820-like entries
    for reservations and ram regions.  Use it for ram detection if present,
    otherwise fallback to the traditional cmos method.
    
    Change-Id: Icac6c99d2a053e59dfdd28e48d1ceb3d56a61bdc
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/4030
    Tested-by: build bot (Jenkins)

commit 289b45fdffa42db85fa4ad63338677ab8f15e9a2
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Wed Jun 12 10:18:58 2013 +0200

    qemu: add fw_cfg files support
    
    Qemu can provide files using the firmware config interface.
    This is used to pass config options, virtual machine config
    info and option roms into the guest.
    
    This patch adds support for reading the file index and loading
    files from qemu.
    
    Change-Id: I57d4a734527c4117239f355121cf1fb8a390ab0d
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/4029
    Tested-by: build bot (Jenkins)

commit a91daa5ba15260fc5551ff54fb926d6e2b093711
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Thu Nov 7 16:51:24 2013 +0100

    add memory clobber to ins{b,w,l}
    
    Change-Id: Ia710eb59f23a52afba2a8ef6e0ff2b2306107245
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/4033
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e1539ba93185931f970f0fdf7d008cbaaf9d234f
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Fri Nov 8 10:46:57 2013 +0100

    libpayload: add memory clobber to ins{b,w,l}
    
    Change-Id: I3c4b8a9eeb6c4b2bcc58ccff091b4c997b2da923
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/4034
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 04134a52b2077d0a77819ea12ee9646050e8edc0
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Wed Oct 30 16:18:07 2013 -0600

    sio1007: Properly build '.c' files
    
    Properly build the super i/o .c files.  This prevents including
    the .c file directly in romstage, which is generally bad practice.
    Adding a Makefile and a .h file to include.
    
    Change-Id: I0be66e94d3062a2c4a445cee2f12ec249598dc8b
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4014
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit c4b6f3bacb7a2ac139f8b85c85388ef6fbda96d9
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Nov 5 17:47:37 2013 -0700

    emeraldlake2: Clean up COM port enable
    
    Remove the COM port enable loop. There is no need to
    search for the port when it is needed and known by the
    GPIO function.
    
    Change-Id: Ie4e533fd9e49ed9ae62b209317b4b9853ff9926a
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4027
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit af0cd0921a277e0724d75e73271c8dd9ce70c0f9
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Wed Oct 30 16:25:23 2013 -0600

    console: Add hexdump32 function
    
    Add a function to display memory locations in the console
    logfile.
    
    Change-Id: Iddb8d2e7a24357075f32c2fdf7916ae7a732247d
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4013
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 12785d9601d8fdfe6f12289b4fd7001f304862f5
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Fri Nov 8 10:13:50 2013 -0800

    util/xcompile/xcompile: set up for aarch64
    
    The tools for aarch64 on ubuntu are called
    aarch64-linux-gnu-*
    The type is
    elf64-littleaarch64
    
    This now finds the right files for building on aarch64
    
    This has only been tested on ubuntu saucy; the aarch64 toolchain
    is in a very ill-defined state on most distros.
    
    Change-Id: Ic1bbd40f0d72384d6e80287b850686292a252918
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/4035
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 2a58ecde78350902ac47145a3f2dba063bce3375
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Oct 29 17:32:00 2013 -0600

    Add new finalize functions for devices and chips
    
    Many chipset devices require additional configuration after
    device init. It is not uncommmon for a device early in the devicetree
    list to need to change a setting after a device later in the tree does
    PCI init. A final function call has been added to device ops to handle
    this case. It is called prior to coreboot table setup.
    
    Another problem that is often seen is that the chipset or mainboard
    need to do some final cleanup just before loading the OS. The chip
    finalize has been added for this case. It is call after all coreboot
    tables are setup and the payload is ready to be called.
    
    Similar functionality could be implemented with the hardwaremain
    states, but those don't fit well in the device tree function pointer
    structure and should be used sparingly.
    
    Change-Id: Ib37cce104ae41ec225a8502942d85e54d99ea75f
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/4012
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 86655cf835900d54569a867de05e56ccd71db879
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Thu Nov 7 18:03:05 2013 +0800

    Trivial: Remove trailing whitespaces in status.sh
    
    The whitespaces make "git commit" failed.
    
    lint-stable-003-whitespace
    Check for superfluous whitespace in the tree
    ========
    test failed:
    File util/status/status.sh has lines ending with whitespace.
    ========
    
    Change-Id: I52fc5ae3e5aa81dac098b36d2479e4d10325a09b
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/4032
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 0ce5ebf0a09bfdc7f93737d441cf46899ed1cc79
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Oct 21 21:22:09 2013 +0200

    northbridge/intel/i945/raminit.c: Remove set but unused variable `reg16`
    
    
    Change-Id: Id4a758644a7b799e7662113c07d395e053525934
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3984
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bf22338a0957bb7af765e112dc0c892b119ee525
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Oct 20 00:41:28 2013 +0200

    southbridge/via/vt8237r/ctrl.c: Remove set but unused variable `regm3`
    
    Change-Id: I6bb652419a54b7b7190e417346581f38335425ae
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3985
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b0aec8f070053284a750f07d0fe6f1b37bac83d1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Oct 30 15:03:25 2013 +0200

    usbdebug: Fix build for ROMCC boards
    
    Header file is not compatible with romcc, just drop it as a romstage
    built with romcc cannot use usbdebug anyway.
    
    Change-Id: If7f8f22d6a8fa1f02157df281f82f02b72b6a609
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/4006
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6583a8108ca2cbcb2f363d50bd234e60bc3f4f3e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Nov 1 19:37:44 2013 -0700

    Another pass at board status script
    
    This reports relevant bits of information about a machine which is
    running coreboot. This also includes a script to get revision info
    from git, which we may want to split out into another patch.
    
    A remote target can be specified since it is likely that the machine
    used to develop the code is not the same machine being developed for.
    The remote host must be set up for non-interactive root login.
    
    Example: sh util/status/status.sh -r gizmoboard -u
    
    Change-Id: Ief0a85faca2ec9ce2d270e1e5b09e74836ab0c97
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/4021
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d0299e4b5178ce8f8b986674cece3e07519f2dff
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Oct 21 09:28:19 2013 +0200

    southbridge/intel/i82801ix/lpc.c: Remove unused variable `dummy`
    
    Removing `-Wno-unused-but-set-variable` from `CFLAGS` the build for
    QEMU Q35 and Roda RK9, both using the Intel 82801Ix southbridge, fail
    with the following error.
    
    	src/southbridge/intel/i82801ix/lpc.c: In function 'i82801ix_enable_apic':
    	src/southbridge/intel/i82801ix/lpc.c:45:5: error: variable 'dummy' set but not used [-Werror=unused-but-set-variable]
    	cc1: all warnings being treated as errors
    
    Removing `dummy` should be safe as GCC probably optimizes it away before
    anyway. That no dummy variable is used for an RCBA [1] access in Intel
    Lynx Point supports that this can be dropped safely.
    
    [1] root complex base address
    [2] src/southbridge/intel/lynxpoint/early_pch.c
    
    Change-Id: I1c138a3498228dbd025f68d5e6af0acc29ed3460
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3982
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 1ce4860405d995585d08350481932238ee2f8c4a
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Sat Oct 19 01:33:08 2013 +0800

    vortex86ex: Defer checking PS/2 keyboard controller system flag
    
    Don't check keyboard controller system flag until before calling
    pc_keyboard_init(). This makes waiting time shorter.
    
    Change-Id: I2cdb533a5b25575e1717434533a60decf748f6d8
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3958
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ac164057993e9edbfe78537efbbc9ef5f75cd67c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 11 21:14:59 2013 +0300

    usbdebug: Fix boards without EARLY_CBMEM_INIT
    
    The main usbdebug file lib/usbdebug.c was removed from romstage
    build with commit f8bf5a10 but the chipset-specific parts were not,
    leading to unresolved symbol errors for AMD platforms.
    
    Add a silent Kconfig variable USBDEBUG_IN_ROMSTAGE for convenient
    use of this feature.
    
    Change-Id: I0cd3fccf2612cf08497aa5c3750c89bf43ff69be
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3983
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 569ad760cc4d7e3595bd9d4f569d08b021a64663
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Oct 2 22:10:11 2013 +0200

    util/lint/lint-stable-003-whitespace: Ignore temporary files ending with a tilde
    
    Some editors like gedit create auxiliary files ending with a
    tilde '~'. As these are not checked into the Git repository, do
    not check these for whitespace errors.
    
    Change-Id: I2c4cf00f9d623be73ea3bbb7b2da4f1e1900c8e9
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3952
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>

commit 553fe1cbc72c849504041fb65dbbb1afacd3914b
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 15 16:45:51 2013 -0500

    winent-mb6047: initial WIN Enterprises MB-60470 board port
    
    What works:
     - ACPI interrupt routing for onboard devices
     - onboard devices including USBs, ATAs, NICs, COM1
    
    What almost works:
     - SMI720 VGA BIOS needs forthcoming VGA BIOS hooks in SeaBIOS to work
    
    Untested:
     - Interrupt Line Register interrupt routing
     - PIRQ interrupt routing
     - MPBIOS/MPTABLE interrupt routing
     - unpopulated on board revision 1A AC97 audio
     - unpopulated PCI-E x16 slot
     - unpopulated ExpressCard slot
     - HT expansion board
    
    Thanks to WIN Enterprises for providing boards.
    
    Change-Id: I7787f89b3ab454b668c3b75d0d1cde55b8d53c48
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/3975
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit e1ffd9ef7a04b5a3d167b0767afce08a04721fe8
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 15 14:26:34 2013 -0500

    winent-mb6047: copy tyan/s2891 mainboard directory
    
    Change-Id: I382e30c92a4c428ec53dd959a5fda4927797fb9b
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/3974
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6a4e9b547a0e73fb48ee228357820fb3ba85cec2
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Oct 18 09:42:55 2013 +0200

    get_bus_conf.c: reindent with indent
    
    Change-Id: Ia0c37339aa69b92a1b518fa5e49adc4a7628ae5d
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3979
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit cd9abf95e7fe3d67f02e5e0197efa2688db83d22
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Tue Sep 3 20:39:48 2013 +0800

    arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS
    
    SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify
    the xcompile script to search for cpp program path, and pass it to
    SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler).
    
    This is needed, so the crossgcc toolchain to build the SeaBIOS payload
    under Mac OSX. OSX ships a cpp program, but it works differently
    from GNU CPP, so we need to override it.
    
    Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3896
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>

commit c2a8031a5eb8ed22ab6f906e44445af1c9487361
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Mon Oct 7 16:27:01 2013 +0800

    libpayload/sample: Use settings from .xcompile file to build.
    
    It is for crossgcc.
    
    Change-Id: Ia1d676adfea340b6b80858215459491c9338d614
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3955
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>

commit 697927cc35c80ddbe91d868ba1e41fb68dda815d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Oct 13 04:15:40 2013 +0300

    CBMEM: Define cbmem_top() just once for x86
    
    It is expected this will always be a casted get_top_of_ram() call
    on x86, no reason to do that under chipset.
    
    Change-Id: I3a49abe13ca44bf4ca1e26d1b3baf954bc5a29b7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3972
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 2644793ef486881f3af36bec69d5f9abf82123ac
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 11 21:14:59 2013 +0300

    Have option of timestamps, CBMEM console and usbdebug for most boards
    
    As boards without EARLY_CBMEM_INIT do not initialize CBMEM in romstage,
    and have no CAR migration, these features are available for ramstage only.
    
    Change-Id: Ic3f77ccdedd4e71ba693619c02c9b98b328a0882
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3970
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 082c19ea89a24216aafd4ef728f9983b93f6b486
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Oct 12 00:22:57 2013 +0300

    CBMEM: Fail builds on missing get_top_of_ram()
    
    Dummy get_top_of_ram() is removed from romstage to fail already at
    build-time for cases where cbmem_initialize() would not complete.
    
    The mechanisms behind CAR_GLOBAL migration only work correctly when
    romstage can succesfully make the cbmem_initialize() call.
    
    Change-Id: I359820fb196ef187b9aa2e8a3e8f658a0550f237
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3969
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 1a279046cd5b347c4c9d5b7bb4227417acdb2950
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Oct 13 23:06:09 2013 +0300

    intel/i82371: Remove HAVE_ACPI_RESUME
    
    This is needed to apply a rule that get_top_of_ram() in romstage is
    required to select HAVE_ACPI_RESUME, otherwise chipset/board has no
    means to backup low memory to CBMEM on s3 resume.
    
    Only board affected is asus/p2b.
    
    Change-Id: Ia5cbf4e5e40af25f52a19de584d8bc5370487154
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3971
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 29e9c22eb71f0a7dcbeaa6fbf2a049dbc56b7c05
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Oct 13 13:27:56 2013 +0300

    timestamps: Fix some lost timestamps for romstage
    
    Timestamps from cbfs_and_run, TS_START_COPYRAM and TS_END_COPYRAM,
    were lost with commit b766b1c7.
    
    Reason is variable ts_table was referencing CAR storage after CAR
    is torn doesn. Add use of car_get_var() / car_set_var() so the
    references go to migrated storage in CBMEM.
    
    Change-Id: I5a942ad7fd59a04e3a5255f4a3636d37dcfc1591
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3967
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 4ca721399cdb8012f9ac81e20129afe5ddda84cc
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Sun Sep 22 15:20:37 2013 +0800

    AMD Olive Hill: Disable NoSnoopEnable to fix HDMI audio corruptions with Ubuntu
    
    Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can
    resolve this issue.
    I have tested on Ubuntu 13.04 with AMD Catalyst 13.4 Proprietary
    Linux Display Driver[1].
    
    [1]. http://support.amd.com/us/gpudownload/linux/Pages/radeon_linux.aspx
    
    Change-Id: I5d2dddb1b7469d56cd64e3c1e0f4c6c6f095b4ab
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3934
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 2c86fc434383838c593c38feb5c28de78f18ea8d
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Mon Sep 23 15:12:56 2013 +0800

    ASRock IMB_A180: fix Ubuntu HDMI audio issue
    
    Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can
    resolve this issue.
    I have tested on Ubuntu 13.04 with latest graphic driver.
    
    Change-Id: I09c19b8925eedee03cfb1d8c0831a84e8aeeba4f
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3937
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit f38145e81c7ddc0c9a652d0fd833714264c2c6de
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Sun Sep 22 15:13:57 2013 +0800

    AMD Olive Hill: fix Windows 7 HDMI audio issue
    
    Windows 7 cannot find HDMI audio device because of acpi setting.
    I have tested on Windows 7. I can play music.
    
    Change-Id: I90ade7e7be79f65783922333c2cbb2d3cc6557ea
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3933
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7b6d412dbc4e5c11d3dd7890abf0edf279b3f504
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Wed Jul 31 16:55:26 2013 +0800

    vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7
    
    The platform initialization (PI) code v1.0.0.7 for Kabini has some
    enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH
    bug fix (RTC) and so on.
    
    Use the name Kabini instead of Kerala everywhere.
    
    Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0
    as used in `AGESA_VERSION_STRING`.
    
    Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3935
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit f8bf5a10c599ef071998bbc3f16e9e3d7fcdb6eb
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 11 22:08:02 2013 +0300

    Revert "CBMEM: Always have early initialisation"
    
    This reverts commit de1fe7f655c549e8dce5b34218221890fa5ccc34.
    
    While things appeared to work, there were actually invalid references
    to CAR storage after CAR was torn down on boards without
    EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be
    restricted to boards that handle CAR migration properly.
    
    Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3968
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit cf18c856aafaaa2a7e5eaebf64a2d5c647e590e8
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Fri Oct 11 16:14:18 2013 -0500

    ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1
    
    Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is
    0xfec00000 (that is, outside the range of bus 0 address space).  This
    causes IOAPIC interrupts to fail to work under Linux.  This issue was
    originally unnoticed by me when testing as sanity checking such as
    this is not done by NetBSD.
    
    Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've
    checked.
    
    Change-Id: I736db163750f709d68c988fac075597a50b29ab7
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/3963
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 948dede9c5a3d67295c4b9528fd11e741459c116
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Fri Oct 11 15:52:30 2013 -0500

    ck804: obtain stored IOAPIC address from allocator instead of register
    
    Change-Id: Ibdd438455a545aa9266b0fd893d5ff27124ab22c
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/3961
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b6795255389ffd2320307dc6848919049016dfbd
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Fri Oct 11 14:58:39 2013 -0500

    ck804: obtain I/O APIC base address for ACPI MADT from allocator
    
    Change-Id: I67192c8ae99e396ea4b17e03c658f31dbb5c1800
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/3960
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3fa1a13f62fe805a4592eaa551cd9d5713613f91
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Wed Oct 9 18:57:20 2013 +0800

    dmp/vortex86ex: Initialize PS/2 keyboard.
    
    Call pc_keyboard_init function in southbridge. It makes PS/2
    keyboard work in coreinfo payload.
    
    Change-Id: Idb79f87b09eeeade94e966fb8769dec7578e2cf5
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3957
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7a00ca75d70ceb336e189851dca06b363139ed96
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Oct 12 21:29:26 2013 +0200

    northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable `reg` in `setup_mtrr_dqs()`
    
    Change-Id: I7fc7819c329c058472031e82237be5c170b277f4
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3965
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>

commit 772d026076d7c19755aa9dcc592a372e3c5ba980
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Fri Oct 11 16:09:37 2013 -0500

    ck804 lpc: use PCI_BASE_ADDRESS_1 instead of 0x14
    
    Change-Id: I752a4a890e1f610651a2c688cf42350ce8e9deaa
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/3962
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit fd4f4136e8b6dd6f743b2a3bfd02c735b6b25131
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 19 12:25:44 2013 -0700

    Rename cpu/x86/car.h to arch/early_variables.h
    
    and add an ARMv7 version.
    
    Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    [km: rebased fa004acf8 from chromium git]
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3939
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 8ad6e78778b036cf2c9bc455376a8599e0bcb759
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Fri Oct 11 13:50:04 2013 -0500

    Nvidia boards: acpi_tables.c: Remove intermediate variable in ACPI interrupt routing initialization
    
    Change-Id: I6cb4ad5ea5ad40284f8e88ff440f2605d3b83359
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/3959
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 4f9bf7e2fb7035725c2899db0d00d77007d9113c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Sep 9 09:23:19 2013 +0300

    AMD hudson yangtze: Fix corruption of a global ramstage variable
    
    A late for loop may reference over the current array allocation
    and corrupt an unrelated global variable. As a quick fix bumb the
    size of the array allocation uniformly to 6.
    
    We missed these boards for commit 9c7d73ca because the arrays
    had been renamed.
    
    Change-Id: Iff2f2a0090d9302576bc72195d2a3f6fa37ce29a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3954
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit 11b47801b2c3abc3bb8c523b722fafa1103bff45
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Oct 2 21:59:38 2013 +0200

    cpu/x86/mtrr/mtrr.c: Remove superfluous assignment to `type_index`
    
    When building coreboot with the Clang static analyzer scan-build,
    it reports »Value stored to 'type_index' is never read«. Indeed,
    in `memranges_each_entry()` `type_index` is assigned a value
    before being read. So remove that line.
    
    Change-Id: I6da2fb8be7157bb98c57281babd4a08ca0d9f7a7
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3953
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit b142a5154280c00a3e4bc9d162b31bfe4b665f60
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Tue Sep 17 09:49:02 2013 +0200

    qemu: q35: avoid address conflict
    
    Qemu has the fw_cfg interface at 0x510, which conflicts with
    power management base address in coreboot.  Move the pmbase to a
    non-conflicting address.  No need to worry about speedstep, it
    is not supported by qemu and isn't enabled in the qemu config.
    
    Change-Id: I3e87d8301988028ca0ea7d96c08b4e26ac15a7c2
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3938
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c371442a2925e9bfc9ddc045bfd446db53f0a145
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Jul 19 14:03:47 2013 +0200

    libpayload: Switch xHCI shared ports back to EHCI on shutdown
    
    On Intel's Panther Point the xHCI ports are shared with an EHCI
    controller. Our xHCI driver switches them to xHCI, naturally. But
    we forgot to switch them back on shutdown, which left them
    unusable by a non-xHCI aware operating system.
    
    Change-Id: I70ef08655a603b42ee939935d50cf77ea97878a3
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3791
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 681d17e0bf00a889f3c931d69b9af205c4ab674d
Author: Allen Martin <amartin@nvidia.com>
Date:   Thu Sep 26 11:13:01 2013 -0700

    exynos5420: Fix build warning
    
    Fix "set but not used" variable warning with gcc 4.7.3
    
    Change-Id: Ia27291ecb4f993c4ba6f29b134167dc23a449bf5
    Signed-off-by: Allen Martin <amartin@nvidia.com>
    Reviewed-on: http://review.coreboot.org/3949
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Gabe Black <gabeblack@chromium.org>

commit 616e6fb2521e639eebb95c572f38db1a8bc26894
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Mon Sep 23 15:11:11 2013 +0800

    ASRock IMB_A180: fix Windows 7 HDMI audio issue
    
    Windows 7 cannot find HDMI audio device because of acpi setting.
    I have tested on Windows 7. I can play music.
    
    Change-Id: I53177ce00b676824a903a3397d69338e8c1a38af
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3936
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1bfe37470e8300152b0f6f335a59f88096577bcf
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Jul 2 16:39:28 2013 +0200

    lint: Use temporary build directory
    
    `util/lint/lint-stable-002-build-dir-handling` always overwrites your
    current `config.h` and `auto.conf` when the pre-commit hook is run. It
    can be very confusing when your configuration is suddenly broken. So fix
    it by not using the default build directory.
    
    Change-Id: If2bbc97ac2f12a8203a3769d813386a023f93dd6
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/3593
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit a1179cafdb87e3dfd6df142b128331b02feaa5b2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Sep 17 00:12:05 2013 +0300

    usbdebug AMD: Add choice of EHCI controller
    
    Chipsets sb700 and sb800/hudson have more than one USB EHCI controller,
    implement the selection logic using already existing Kconfig option.
    
    Change-Id: I9e0df1669d73863c95c36a3a7fee40d58f6f097e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3928
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dd6c4ec1ed64f3d9803cca6eb53fa5049cacdd09
Author: Shawn Nematbakhsh <shawnn@chromium.org>
Date:   Fri Aug 23 14:12:24 2013 -0700

    libpayload: Remove unnecessary keyboard mode setting code
    
    keyboard_init attempts to read the existing mode register, set the
    'XLATE' bit, and write it back. The implementation is buggy because the
    keyboard may be active at the time we read the mode, and we can
    misinterpret scancode data as the reply to our command. It leads to
    problems where the KB gets disabled in firmware.
    
    In fact, setting the 'XLATE' bit is completely unnecessary, even if we
    desire QEMU keyboard support. We already set this bit when we initialize
    the keyboard in pc_keyboard_init. Basically, this code does nothing
    (or worse), so just remove it.
    
    Change-Id: Iab23f03fa8bced74842c33a7d263de5f449bb983
    Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
    Reviewed-on: http://review.coreboot.org/3883
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5a7e127cd429b101814cae0a1ca3fb5de912777c
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sun Jul 28 05:36:45 2013 -0400

    southbridge/cimx/sb900: Rename headers to match sb700 & sb800
    
    Northbridge code includes these headers, so they all need to
    have the same name to allow different combinations of northbridge
    and southbridge. This changes the sb900 names to match sb700 &
    sb800, and points agesa/family12 and amd/torpedo to the new file
    names.
    
    Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Reviewed-on: http://review.coreboot.org/3825
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cbf5bdfe67e90f780b9f5b2f8cb9cd6e0d46682d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Sep 10 00:07:21 2013 +0300

    CBMEM: Always select CAR_MIGRATION
    
    If romstage does not make cbmem_initialize() call, linker should
    optimize the code for CAR migration away.
    
    This simplifies design of CBMEM console by a considerable amount.
    As console buffer is now migrated within cbmem_initialize() call there
    is no longer need for cbmemc_reinit() call made at end of romstage.
    
    Change-Id: I8675ecaafb641fa02675e9ba3f374caa8e240f1d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3916
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit de1fe7f655c549e8dce5b34218221890fa5ccc34
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Sep 8 10:08:28 2013 +0300

    CBMEM: Always have early initialisation
    
    Assume EARLY_CBMEM_INIT=y everywhere and remove option from Kconfig.
    
    If romstage does not make the cbmem_initialize() call, features like
    COLLECT_TIMESTAMPS and early CBMEM_CONSOLE will execute during
    romstage, but that data will get lost as no CAR migration is
    executed.
    
    Change-Id: I5615645ed0f5fd78fbc372cf5c3da71a3134dd85
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3917
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit a2f6af3330a754de2f8c4438812e09fc81ad181c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Sep 10 13:50:32 2013 +0300

    ROMCC boards: Fix builds with CBMEM console, timestamps or usbdebug
    
    These features depend on CAR_GLOBAL region, which is not available
    when romstage is built with ROMCC. Exclude these from romstage, keep
    them available for ramstage.
    
    A follow-up patch will fix the dependencies and allows enabling these
    features in menuconfig.
    
    Change-Id: I9de5ad41ea733655a3fbdc734646f818e39cc471
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3919
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 52a27223892936cdc8e1744516a82a2e44584763
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Sep 9 01:31:22 2013 +0300

    CBMEM console: Support late init
    
    It is not compulsory to have CBMEM console initialised in romstage,
    so try add the CBMEM table entry again in ramstage, if not found.
    
    Change-Id: I96ab502df7f05d6bf1d6e6fa84d395ef6306b525
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3915
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit f56ff9069eb49df30d7e99e4e67aad851a54bc7d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Sep 8 13:10:28 2013 +0300

    timestamps: Only collect from BSP CPU
    
    We only have one table to collect timestamps into.
    
    Change-Id: I80180fe9a05226f0351c3e66eacaf2d0cb82c924
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3912
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit c0beb6d4185db33eeabbceefd9004769253973a3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Sep 8 13:48:36 2013 +0300

    timestamps epia-m850: Cleanup without enabling timestamps
    
    Remove the existing hack, platform needs a fix for EARLY_CBMEM_INIT.
    
    Change-Id: I7ce373c9698878d9fa056983e4fb571a68239c52
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3913
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 3d45c4077665a17735c69576638dc510f96a2dff
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Sep 7 20:26:36 2013 +0300

    timestamps: Stash early timestamps in CAR_GLOBAL
    
    Change-Id: I87b454c748cf885491d5b38bfe53a2ec0e9f38c5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3910
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit b766b1c76aa2258bf66569f429fb092c23813bbc
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Sep 7 17:26:08 2013 +0300

    timestamps: Use stash before CBMEM is usable
    
    Change-Id: I9e927abdb1d7d9c233de5620a9a65b419e803ebf
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3909
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit e28bd4ade6f716024afdff0bac48028a42a62e71
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Sep 7 11:38:56 2013 +0300

    timestamps intel: Move timestamp scratchpad to chipset
    
    This retrieves back the value stored with store_initial_timestamp()
    in the bootblock for southbridge.
    
    Change-Id: I377c823706c33ed65af023d20d2e4323edd31199
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3908
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit c8883262cf1375616743ba9d1f259b4fcda20d72
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Sep 19 10:57:58 2013 +0200

    buildgcc: Downgrade to gcc 4.7.3, handle armv7-a
    
    gcc 4.8.x has issues with using ebp, which broke some builds,
    so downgrade. The problem also manifested elsewhere, so it's
    not necessarily our fault.
    
    While at it, gcc complained about "armv7a" where it seems to
    expect "armv7-a".
    
    Change-Id: I6f0c35f49709cb41022475bb47116c12ab1c7ee3
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3930
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d2dac0a7d62c89b24eae9de17bcfdde1aea7a5b3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Aug 23 23:33:16 2013 +0300

    usbdebug: Allow an USB hub on the debug dongle
    
    Some development kits with USB 2.0 HS OTG have an USB hub instead
    of being directly connected to the USB host/device controller.
    
    Send the necessary initialisation sequence, using HUB CLASS requests
    of PORT_POWER and PORT_RESET to enable a pre-selected port number
    where a device supporting debug descriptor is located.
    
    This also adds the Kconfig option for BeagleBone.
    
    Change-Id: I7a5d0ba0962a9ca06bf3196232ed4a03bdfb2b06
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3925
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 8f485dee0d38c1c5f1a29fa8840602774ef5f63d
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat May 4 00:08:34 2013 +0200

    ASUS F2A85-M: Correct and clean up PCIe config
    
    Assign the lanes correctly to the physical slots
    on the motherboard in `PlatformGnbPcie.c`.
    
    • UMI is connected to SB via 4x PCIe bridge 8.
    • The blue x16 slot is not shared with DDI and is routed
      through PCIe bridge 2.
    • The black x8 slot is in fact a x4 slot and uses all 4 GPPs
      from the CPU.
    • Assume that DDI is on out-of-PCIe-band lanes.
    
    Change-Id: I44c4c83e6a8e31d6150a602a0993972ac63105bd
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3194
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>

commit ad690f2e8182b182b4c343d2238bb079e6bb8db2
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Tue Sep 17 10:35:43 2013 +0200

    qemu: q35: fix pci bar placement
    
    Without this coreboot may (depends on the amount of memory) place the
    pci bars below 0xb0000000, then the linux kernel goes move them around
    so they are inside the window declared in the acpi tables.
    
    This breaks vesafb as the vga framebuffer gets moved after vgabios
    initialization.  It's also not exactly nice to expect the OS fix our
    mess ;)
    
    Change-Id: If6b50ea863958eea71b567ccb7a06c6a28076111
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3927
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 3af0aa2533dc4dc7a0a11711c18587cee0104267
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Sep 17 20:59:52 2013 +0200

    buildgcc: Use per-arch build directories
    
    This simplifies debugging and also fixes an issue when build directories
    are kept between buildgcc runs for different architectures.
    
    Change-Id: I5badccd3368e3014680da3eedb607119fff8fa7f
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/3929
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit ecd842491972a523a704faef3badd74d9a70a490
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Sep 13 07:57:49 2013 +0300

    Fix whitespace leaked into tree
    
    Clean whitespace errors that have gotten past lint-stable-003-whitespace
    and gerrit review.
    
    Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3920
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 370ff4af113e698aace3adfa393c76cfc9016d38
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Sep 13 08:03:52 2013 +0300

    lint whitespace: Fix rule to recurse into subdirectories
    
    The rule "-perm +111 -prune" matched any searchable directory
    and did not recursively find files in them. The use of "+mode"
    for -perm is deprecated.
    
    Change-Id: I1b43f89ee9ab37928e56104b0f07241ff84b84c0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3921
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 73cffd69993ed4fbad5237f6ad093da790ed85ae
Author: Gabe Black <gabeblack@chromium.org>
Date:   Sun Sep 15 20:59:08 2013 -0700

    beaglebone: Stop reinitializing the console in bootblock.c.
    
    The console has already been initialized in the generic bootblock code, and
    reinitializing it causes the same banner line to be printed twice and lots of
    artifacts in the actual output. This same change had been made to the other
    ARM boards but not for beaglebone.
    
    Change-Id: I72e3be1326b1a52b7ec438a44e4fd5f87e4ec717
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3924
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4938a329ee42e0f9b413efc0b7ebd5bd903dd7b8
Author: Gabe Black <gabeblack@chromium.org>
Date:   Sun Sep 15 20:53:57 2013 -0700

    ARM: Add some missing dependencies on config.h to ARM's Makefile.inc.
    
    These dependencies came indirectly through kconfig.h which was included
    automatically with a -include option which was either part of INCLUDES or
    specified directly. With this change, I'm able to build for beaglebone with
    make -j 48.
    
    Change-Id: Ib57d0c6a755b747165b235c2328c3c30bd6dd67d
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3922
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ccf4fdd1cd00c0f9cbfdfd1d78c9b89fa95f291c
Author: Gabe Black <gabeblack@chromium.org>
Date:   Sun Sep 15 20:56:49 2013 -0700

    am335x: Update the config vars selected by CPU_TI_AM335X.
    
    The way those variables work has changed twice since this file was last
    changed, and console output was no longer working. Now that they're up to
    date there's serial output from beaglebone again.
    
    Change-Id: I5167fd8c0a8c33438d7f056fdf5951bd054010ed
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3923
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0fbbff48bfc4543ebf2b778d3ed557aae58676da
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jun 23 20:03:50 2013 +0300

    CBMEM: Rename high_tables variables and make them static
    
    Old name was too much x86.
    All external references have been removed.
    
    Change-Id: I982b9abfcee57a7ea421c245dadb84342949efae
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3906
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 625f103ae8c794c92e403f8749f0442d66966cab
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Sep 4 14:36:31 2013 +0300

    CBMEM: Drop parameters from cbmem_init()
    
    The parameters can be dropped as initialisation always happens for
    the region resolved with cbmem_locate_table().
    
    This is no longer referenced externally, make it static.
    
    Change-Id: Ia40350a5232dcbf30aca7b5998e7995114c44551
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3565
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit d50cdf108f9d4b598aa8f6c3205d9a93c3e67131
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jun 23 17:01:29 2013 +0300

    CBMEM: Drop parameter from cbmem_reinit()
    
    Function is always called with get_top_of_ram() - HIGH_MEMORY_SIZE
    which equals cbmem_base, thus no need to pass it as a parameter.
    
    Change-Id: If026cb567ff534716cd9200cdffa08b21ac0c162
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3564
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 95c39c28a3d4beb10143ad9c749241fcbdbfb2dc
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jun 22 14:05:28 2013 +0300

    CBMEM ARM: Prefer get_cbmem_table() over cbmem_late_set_table()
    
    Implementing get_cbmem_table() allows initializing CBMEM earlier.
    
    Change-Id: I973f3a84dd9aaa2839959df5dda22909fdb9edeb
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3560
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit f9f74afdd7b39c12d399a900f3af326a33c87387
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Sep 6 10:46:22 2013 +0300

    CBMEM x86: Unify get_cbmem_toc()
    
    Remove any chipset-specific implementations and use arch-specific
    implementation of get_cbmem_table() instead.
    
    Change-Id: I338ee2c1bd51f5e517462115170dc926e040159e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3907
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit bc90e15d3f8e841ccf229fca5d7df99436ff4bdb
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Sep 4 13:26:11 2013 +0300

    CBMEM: Backup top_of_ram instead of cbmem_toc
    
    AMD northbridges have a complex way to resolve top_of_ram.
    Once it is resolved, it is stored in NVRAM to be used on resume.
    
    TODO: Redesign these get_top_of_ram() functions from scratch.
    
    Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3557
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit c04afd6433cd53acdc727ad760cde9c40090030b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Sep 4 13:31:39 2013 +0300

    CBMEM: Add cbmem_locate_table()
    
    For both romstage and ramstage, this calls an arch-specific function
    get_cbmem_table() to resolve the base and size of CBMEM region. In ramstage,
    the result is cached as the query may be relatively slow involving multiple PCI
    configuration reads.
    
    For x86 CBMEM tables are located right below top of low ram and
    have fixed size of HIGH_MEMORY_SIZE in EARLY_CBMEM_INIT implementation.
    
    Change-Id: Ie8d16eb30cd5c3860fff243f36bd4e7d8827a782
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3558
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit dcb688e5ec88ac1d168509fa757c4665ef335ad4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Sep 4 01:11:16 2013 +0300

    CBMEM: Unify get_top_of_ram()
    
    Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3904
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit e1ea802ea69b70826b997b9bb465e0b2a3b0fce8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Sep 4 14:11:08 2013 +0300

    CBMEM tables: Remove references to global high_tables_base
    
    Unify checks and writing of CBMEM tables for x86 and ARMv7.
    
    Change-Id: I89c012bce1b86d0710748719a8840ec532ce6939
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3559
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 1ae305efe1a0823c270767ddf6cc02c41ce146f8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Sep 4 13:05:01 2013 +0300

    CBMEM: Add cbmem_late_set_table() and drop references to high_tables_base
    
    This helper function is for compatibility only for chipsets that do
    not implement get_top_of_ram() to support early CBMEM.
    
    Also remove references to globals high_tables_base and _size under
    arch/ and from two ARMv7 boards.
    
    Change-Id: I17eee30635a0368b2ada06e0698425c5ef0ecc53
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3902
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 42f4651434877085f2a44939375bffeeecdb2c37
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 27 08:20:09 2013 +0300

    CBMEM northbridges: Remove references to global high_tables_base
    
    Use the new helper function set_top_of_ram() to remove remaining
    uses of high_tables_base and _size under northbridge/.
    
    Change-Id: I6b0d9615002ed2aff578c5811d7bd43dd2594453
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3561
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 2b790f651230589fd66e8121745986b8a939b13b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Sep 3 05:25:57 2013 +0300

    CBMEM AMD: Fix calls to set_top_of_ram_once()
    
    We can postpone the call to set_top_of_ram_once() outside the
    loops and make just one call instead.
    
    As set_top_of_ram() is now only called once, it is no longer
    necessary to check if high_tables_base was already set.
    
    Change-Id: I302d9af52ac40c7fa8c7c7e65f82e00b031cd397
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3895
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e7e847cd5c60d51bf5a50663a191b4e622c5c234
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 27 08:20:09 2013 +0300

    CBMEM AMD: Remove references to global high_tables_base
    
    Prepare for removal of globals high_tables_base and _size
    by replacing the references with a helper function.
    
    Added set_top_of_ram_once() may be called several times,
    but only the first call (with non-zero argument) takes effect.
    
    Change-Id: I5b5f71630f03b6a01e9c8ff96cb78e9da03e5cc3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3894
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 9c7d73ca3f5b2985cb0f498038a746bcc0f2cac7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Sep 9 09:23:19 2013 +0300

    AMD sb800 sb900: Fix corruption of a global ramstage variable
    
    A late for loop may reference over the current array allocation
    and corrupt an unrelated global variable. As a quick fix bumb the
    size of the array allocation uniformly to 6.
    
    Change-Id: Ib067fdf077e091d13e32cc3a8e4a0b713d19bcc2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3914
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit c984f4f30333cde88fbd14a188c5ce599d0fc77c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 29 10:16:14 2013 +0300

    AMD AGESA: Place CAR_GLOBAL in BSP stack
    
    Use BSP CPU's stack space to store CAR GLOBALS for the
    duration of romstage before CAR migration.
    
    NOTE: Such globals can only be accessed from BSP CPU due
    the way AMD platform has memory architecture set up.
    
    TODO: Add compile-time assertions to verify CAR configuration
    matches with the programming in vendorcode.
    
    Change-Id: Ica4700433268f484ce69a24d934732f9cfd4ba41
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3832
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit 6f9fa8634a4d41f475137fc66db2bffd810195f8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 26 08:53:25 2013 +0300

    intel/i5000: remove explicit pcie config accesses
    
    Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
    the pcie explicit accesses. The default config accesses use
    MMIO.
    
    Change-Id: Ibe2fea68854af465900e443959a745a7167fb753
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3813
    Tested-by: build bot (Jenkins)

commit 8aa7e839943560c57d0c39278bfcf3ae3eda29e0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 26 08:52:10 2013 +0300

    intel/i945 intel/i82801gx: remove explicit pcie config accesses
    
    Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
    the pcie explicit accesses. The default config accesses use
    MMIO.
    
    Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3811
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 9b143e1474f425b6d81bf6490d67baf26d03c437
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 26 08:35:09 2013 +0300

    intel/i82801ix: remove explicit pcie config accesses
    
    Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
    the pcie explicit accesses. The default config accesses use
    MMIO.
    
    Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3809
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 35a7249183d2e791eb00b41332e6277c504cdd49
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 1 11:21:53 2013 +0300

    intel/gm45: Use MMCONF_SUPPORT_DEFAULT
    
    Change all PCI configuration accesses to MMIO for all boards
    with gm45 chipset. To enable MMIO style access, add explicit
    PCI IO config write in the bootblock.
    
    Change-Id: Id1c839b7d669946e0ca8b6837e5152ebcb9cd334
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3600
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 25dd2479c1890d45935d7dbfc14599385e1893dd
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Jun 14 15:34:59 2013 +0200

    libpayload: Set heap's header size to 64-bit
    
    For libpayload clients with larger memory needs (eg. FILO with integrated
    flashrom) the current configuration isn't enough.
    
    Change-Id: Ic82d6477c53da62a1325400f2e596d7d557d5d1e
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3889
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.h@gmx.de>

commit 2d4b4cafe62b43815806fa7145e647f9daca0d38
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Jun 14 15:26:49 2013 +0200

    libpayload: Make heap code independent of its header size
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Change-Id: Ie69ceb343494b7dd309847b7d606cb47925f68b6
    Reviewed-on: http://review.coreboot.org/3888
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 0306b502804ead6f56ad9dee814d0bc5062870f7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Aug 13 09:10:31 2013 +0300

    usbdebug: Fixes for LynxPoint LP
    
    Keep the EHCI BAR unchanged to keep usbdebug working.
    
    Change-Id: I7fe0eed24a66cb5058b49ee3fc0350d91089ed7a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3477
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 690bf2f333322e764262e60fd24802205280df5e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jul 6 11:41:21 2013 +0300

    usbdebug: Use CAR migration
    
    If we already initialized EHCI controller and USB device in romstage,
    locate active configuration from salvaged CAR_GLOBAL and avoid doing
    the hardware initialisation again.
    
    Change-Id: I7cb3a359488b25abc9de49c96c0197f6563a4a2c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3476
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit e53cece07b14eab1912db3d18d2cb50423d996ec
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Aug 10 10:50:43 2013 +0300

    usbdebug: Dump low-level protocol details
    
    Dumping these EHCI host controller registers is useful to
    solve problems with debug devices.
    
    Change-Id: I0610cecca57b1b952d4f87211dd00c8c0bc398b9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3866
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 5c87d2f17e162c40b9f43415ccc049ef482f9336
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Aug 19 12:45:16 2013 +0300

    usbdebug: Adjust endpoint retry timeouts
    
    Change Setup Stage of control messages to have no retries, while data
    and status stages may retry until timing out after 1000 retries.
    
    The correct amount of retries might vary by endpoint and device dongle
    used, so make it a variable.
    
    Change-Id: I63313f994d0bd3444a3aab527ca942da5de9e6fa
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3882
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 2de841b355f632bd4cee3f0419dab34ec57ad804
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Aug 19 12:45:16 2013 +0300

    usbdebug: Adjust transaction retries
    
    Transaction consistently completes with 80 to 150 status reads on my
    setups. Hardware should always be able to complete this within 125us
    as the debug port is serviced at the beginning of each microframe.
    
    Timeout is set to DBGP_MICROFRAME_TIMEOUT_LOOPS=1000 status reads. Do not
    retry transactions if this timeout is reached as the host controller
    probably needs full re-initialisation to recover.
    
    If this timeout is not reached, but a transaction is corrupted
    on the wire, or it is otherwise not properly delivered to the USB device,
    transaction is retried upto DBGP_MICROFRAME_RETRIES=10 times.
    
    Change-Id: I44bc0a1bd194cdb5a2c13d5b81fc39bc568ae054
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3881
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 9a91ba199479b25f83bbf7691d8b6acf6eace34e
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Mar 14 15:11:34 2013 +0100

    libpayload: reduce libcbfs verbosity
    
    Prettier in real-world payloads (ie. FILO)
    
    Change-Id: I9ed968fe527c5d46090e707e2d89b7406a43662e
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3887
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 16ae95c4bce956c115deaa7b5d42b3472a72e9e9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 31 08:26:52 2013 +0200

    Add Kconfig options for Linux as payload
    
    These allow to define a kernel image, initrd and command line.
    
    Change-Id: I40155b812728a176b6d15871e1e6c96e4ad693c8
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/3893
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 2f39eae41d750817143f9372f67de6b1ee96b4a6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Aug 31 08:16:27 2013 +0200

    Remove NRV2B compression support
    
    It wasn't even hooked up to the build system anymore.
    
    Change-Id: I4b962ffd945b39451e19da3ec2f7b8e0eecf2e53
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/3892
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit de36d333c27c258bc05ecc0b6649fbdafcae619f
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Aug 27 20:22:21 2013 +0200

    Add a (b)zImage parser to cbfstool
    
    In the great tradition of LinuxBIOS this allows adding
    a kernel as payload. add-payload is extended to also
    allow adding an initial ramdisk (-I filename) and a
    command line (-C console=ttyS0).
    
    Change-Id: Iaca499a98b0adf0134e78d6bf020b6531a626aaa
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/3302
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dcccbd13966379eeaee79b08db0d58d024536ae8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Aug 10 10:08:38 2013 +0300

    usbdebug: Fix control messages
    
    Add support for control messages with a write of data stage.
    
    Add status stage after a read of non-zero length data stage.
    
    Do not retry control message if device responds with STALL.
    
    Change-Id: I16fb9ae39630b975af5461b63d050b9adaccef0f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3867
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit e29584c1410e27db86df6fb4b5dcf5c1c00d6f68
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Aug 10 10:50:38 2013 +0300

    usbdebug: Use separate data toggle for each pipe
    
    USB defines a mechanism to detect certain cases of lost handshakes
    using an alternating data sequence number, referred to as data
    toggling. This patch fixes each pipe to have its own tracking of
    the data toggle state.
    
    Change-Id: I62420bdaeadd0842da3189428a37eeb10c646900
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3865
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 75d006232a010db24e740340a9e8271b1a75e9bb
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Aug 10 10:34:01 2013 +0300

    usbdebug: Reference endpoints by pipes in calls
    
    Add allocation for endpoint0 as a pipe for control messages.
    
    Endpoint number was already stored in the pipe object, place devnum
    there too, although all pipes will use same devnum==127.
    
    Change-Id: I299d139bdd8083af8b04a694e8e41435ec026a25
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3864
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 545b30d151276324cfd04b1d053d2a8c8d7cf7fd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 13 13:51:14 2013 +0300

    intel usbdebug: Add choice of EHCI controller
    
    Add option to choose one of the EHCI controllers in recent
    intel chipsets for usbdebug use.
    
    Since EHCI controller function changes from 0:1d.7 to 0:1d.0 in
    rcba_config() for some mainboards, check the PCI class code
    for match.
    
    Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3440
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 8101aa6bb02c586cd0d1ab2cf99148329319aaf9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Aug 15 16:27:06 2013 +0300

    usbdebug: Support choice of EHCI controller
    
    Nowadays, chipsets or boards do not only have one USB port with the
    capabilities of a debug port but several ones. Some of these ports are
    easier accessible than others, so making them configurable is also necessary.
    This change adds infrastructure to switch between EHCI controllers,
    but does not implement it for any chipset.
    
    Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3438
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 24100100181bd770ce0f1181a1770a0808790cde
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Aug 12 20:40:37 2013 +0300

    usbdebug: Change debug port scanning
    
    On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan
    all physical ports one after other in incrementing order. To avoid
    possible problems with other USB devices, one can select the port
    number here and bypass the scan.
    
    Intel platforms can communicate with usbdebug dongle on one
    physical port only, and this option makes no difference there.
    
    Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3872
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit f7381f8cd1cf4307dcccd5728fc11afce3610439
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Aug 15 14:57:09 2013 +0200

    kontron/ktqm77: Allow disabling onboard NICs
    
    Two new nvram variables control disabling the two non-ME NICs
    on the mainboard. This is implemented by disabling their PCIe bridge.
    
    Change-Id: I086f0d79de3ad0b53fa0ec40648d63378070e3bd
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3870
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ab6d27e8f83db2791bc2b633a02f12a3076a4e5f
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Jul 2 09:54:17 2013 +0200

    lenovo/x60/romstage.c: Collect timestamps in romstage
    
    Collect early timestamps in Lenovo X60’s romstage.
    
    Selecting the option `COLLECT_TIMESTAMPS` in Kconfig and then
    doing `cbmem --timestamps` should output the timestamps.
    
    Change-Id: I7bd30f03a1b85c38e89c19cdf88b2d20b24abed8
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3587
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 3c46ca33a1c878beee839beb658fd93e8d3312a7
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jul 29 13:00:03 2013 -0700

    Sandybridge/Ivybridge: Unify and fix Kconfig defaults
    
    Change-Id: Ia4a5530e6a1a1fd2dec6f348ff163b5c7a8cd4cd
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3830
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 12ba1978baa4738125b576888e435d7c2a3eeb8d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Aug 16 21:33:42 2013 +0200

    kontron/ktqm77: Drop MRC_FILE definition
    
    The northbridge defines it already and to the same value.
    
    Change-Id: Ia5d856258fac52ea0b249142f70a89123ca04f82
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/3876
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dedcc78ff44f4eb7c227ade84ee35e007f183a89
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jul 29 14:02:06 2013 -0700

    Fix up Stumpy/Lumpy PEI data for system agent r6
    
    Change-Id: I79937fd1671af23184ab830d5ba6242c8067d944
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3831
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5bdcff53749dc9397d40c0a7f9270cd3eb854ad3
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Fri Aug 23 19:48:17 2013 -0600

    ASRock IMB-A180: Add CODEC initialization table
    
    Change-Id: Ic4d191bd34179af707449a15026079da1412ed60
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3886
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)

commit 3c4bd91a341bd40df1aa7e99549591c1e2e61504
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Tue Aug 27 10:23:13 2013 +0800

    Locate the generated iasl in acpica-unix-20130626
    
    acpica-unix-20130626 doesn't use bin32 and bin64 to save the objects
    any more.
    
    Change-Id: I419ecc987e2adcd860a8ad1bf2f6b5c4dd40fd8a
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/3885
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f77f734d38364e9ea48d10e4a4e19f4e2da9bde0
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Tue Aug 13 17:09:51 2013 +0800

    ASRock IMB-A180: Add new AMD Embedded G-Series SOC mainboard
    
    Tested on Ubuntu 12.10. S3 is supported. No HD Audio.
    Mainboard details: http://www.asrock.com/ipc/overview.asp?Model=IMB-A180
    
    Change-Id: I75254194ab5da8e5c61383d8f85aa4e300815637
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3880
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit a9b01d13476eae77b4a1f1679b29eced69684492
Author: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date:   Wed Aug 21 10:06:25 2013 +0800

    AMD f16kb: use AZ_PIN in Kconfig to customize AZALIA_PIN in Yangtze
    
    src/southbridge/amd/agesa/hudson/Kconfig config default value,
    mainboard Kconfig config value for specific mainboard.
    bit 1,0 - pin 0
    bit 3,2 - pin 1
    bit 5,4 - pin 2
    bit 7,6 - pin 3
    
    Change-Id: I54a87cf734685515a3e1850838ca7d94387172ce
    Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
    Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3879
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 9090ff91e175423ee6dce4fc36b338135435b8a3
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Sun Aug 25 12:35:09 2013 +0200

    libpayload: Add a few more PCI constants
    
    flashrom has started to use revision IDs to distinguish AMD chipsets
    and fails (even more) to build with libpayload since then because
    PCI_REVISION_ID is undefined in libpayload's pci header.
    
    Change-Id: If7440a48c1005a4ba4fc09303f47cdfa9f408ad1
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3884
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 021fa78bcae3224ca8bcdb7a0f5acbd5e90ab897
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Aug 16 06:34:04 2013 +0300

    usbdebug: Change reference to EHCI BAR
    
    Change the defines, as follow-up patch will replace use of
    constant CONFIG_EHCI_BAR.
    
    Change-Id: I44ff77cb7a2826f3b43d8d46440fd4482a29d18c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3875
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit c73acdb69eb8128bbbb3bed63cb0ca1b943027ee
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jun 15 17:16:56 2013 +0300

    Add test to match struct device with pci_devfn_t
    
    Add a function to test if pci_devfn_t matches with a device
    instance of struct device, by comparing bus:dev.fn.
    
    Change-Id: Ic6c3148ac62c7183246d83302ee504b17064c794
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3474
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 842f0bab0416d223ecda97817fb5326c666b0499
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 20 20:25:21 2013 +0300

    Add pnp_devfn_t and use with  __SIMPLE_DEVICE__
    
    Declare the functions that may be used in both romstage and ramstage
    with simple device model. This will later allow to define PNP access
    functions for ramstage using the inlined functions from romstage.
    
    Change-Id: I2a0bd8194acaf9c4c7252a29376eec363397e3a6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3871
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 3f9a62e5ade9bf2461c93ac8c6b52c4bdca09742
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 20 20:25:21 2013 +0300

    Add pci_devfn_t and use with  __SIMPLE_DEVICE__
    
    Declare the functions that may be used in both romstage and ramstage
    with simple device model. This will later allow to define PCI access
    functions for ramstage using the inlined functions from romstage.
    
    Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3508
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit a2adaeb68cdecc2bc1185613a11b7d49915883ec
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Aug 12 00:09:21 2013 +0300

    usbdebug: Only test two possible USB device numbers
    
    After an USB device sees USB bus reset on the bus, it will reset to
    device number 0. Per the EHCI debug port specification, a debug
    dongle device may reset to the fixed debug device number of 127 instead.
    Thus there is no need to try device numbers from 1 to 126.
    
    Do a sanity-check on a returned debug descriptor as I experienced
    some USB flash memory to respond on this request with zero-fill data.
    
    Change-Id: I78d58f3dc049cd8c20c6e2aa3a4207ad7e6a6d33
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3861
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 16c014578b9662bc2a0f099b77410e7ea3a793d1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Aug 12 15:32:25 2013 +0300

    usbdebug: Halt host controller before resetting it
    
    Resetting an EHCI controller when it is not halted can have
    undefined behaviour. This mostly fixes a case where calling
    usbdebug_init() twice would fail to reset the USB dongle device
    properly.
    
    On amd/persimmon it still requires one extra retry, but at least it
    is now possible to have usbdebug enabled for both romstage and
    ramstage.
    
    Change-Id: Ib0e6e5a0167404f68af2edf112306fdb8def0be9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3862
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1cf85774da278229229fb77891326d645176d24d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Aug 18 12:44:24 2013 +0300

    SPI: Support STMicro partial page write
    
    Ported from spi/winbond.c.
    
    Fixes this error:
       ICH SPI: Too much to write.
       Does your SPI chip driver use CONTROLLER_PAGE_LIMIT?
    
    Change-Id: I50db8fd1104d3b7d319b278b14f97e3ff9cb6404
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3877
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 93b2bd70ff65a534e91c203c7948deea315675d5
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Aug 13 21:51:53 2013 +0300

    usbdebug: Do not support logging from SMM
    
    Letting SMI handler touch EHCI controller is an excellent source
    of USB problems. Remove usbdebug entirely from SMM.
    
    It may be possible to make usbdebug console work from SMM
    after hard work and coordination with payloads and even
    OS drivers. But we are not there.
    
    Change-Id: Id50586758ee06e8d76e682dc6f64f756ab5b79f5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3858
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 6bfe61d5d15d32d307047eeee8493d0e3ffa42ab
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 6 10:33:39 2013 +0300

    usbdebug: Add compatibility quirk for FX2
    
    This quirk is needed with a DIY debug dongle using obsolete
    CY7C68013 (aka FX2) USB chips. Old revision of chip requires a
    SET_CONFIGURATION to be sent, while this is not required in EHCI
    debug port specs.
    
    Change-Id: I4926eb19b7e991d6efeef782682756571ad006b9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3386
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit d79914008abbc3eea4738d702ea7f3256e13327a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Aug 12 16:11:34 2013 +0300

    usbdebug: Block recursive calls of printk
    
    When we create low-level debugging of EHCI controller registers,
    we call printk() within printk(). In ramstage this would leave us
    with deadlock waiting on the console spinlock.
    
    Change-Id: Idbe029af9af76de27094bb2964c60d9ccfdd96e6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3860
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8ff3d68e93c74d82dc289036347c3da74c395c88
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Aug 12 16:11:34 2013 +0300

    usbdebug: Add logging level to debugging
    
    Increase existing level from DEBUG to INFO.
    
    Change-Id: Ic5934aec449f921af96dd3a6524f7275f8de1304
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3859
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit eabfd3a7c162d5eb96f65085ad8b05238e53a437
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Mon Aug 19 11:43:36 2013 +0800

    Don't include LZMA in romstage if ramstage is not compressed.
    
    If ramstage is not compressed, the CBFS module in romstage doesn't
    need to support LZMA. Removing the LZMA module in this case can save
    about 3000 bytes in romstage.
    
    Change-Id: Id6f7869e32979080e2985c07029edcb39eee9106
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3878
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4159a8012eb7e0f492457b789999bbc56efc4713
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Jul 14 00:24:31 2013 +0200

    Correct spelling of shadow, setting and memory
    
    Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3768
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 95b573a2db59c21cc60cd6802194beb999919e7f
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Wed Jun 5 16:40:34 2013 +0200

    AMD Southbridge CS5536: make use of #include <device/smbus_def.h>
    
    Change-Id: Ia2dff49d3e2b086546785d992f2d92bcf4d1ef1c
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3376
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 59c3a0615498b6fa79bb4152deab7e837f7ed389
Author: Bruce Griffith <bruce.griffith@se-eng.com>
Date:   Mon Aug 12 01:53:13 2013 -0600

    AMD AGESA: Remove INVD instruction when transitioning from CAR
    
    The AMD AGESA function to move the stack from cache-as-ram to
    actual RAM doesn't need any help.  The current implementation has
    an INVD instruction just before cache-as-RAM is torn down. It isn't
    needed for Trinity processors and makes Kabini boot unreliable.
    
    Change-Id: Ibe9e4105eee032471ccbb2d537471d5fa5847d22
    Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3852
    Tested-by: build bot (Jenkins)
    Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 540d8eaac975e1036ebc269df89316c705efbd3c
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Aug 15 14:43:13 2013 +0200

    kontron/ktqm77: Update MRC path
    
    It still pointed to the old binary despite implementing the newer interface
    
    Change-Id: Iebd5dae98168f5568f3ad6a18c5ebde9abc3ece0
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3869
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3f34fc4bf37b6f25fa2af4ede3b870c4841a04b6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Aug 15 20:41:15 2013 +0200

    emulation/qemu-i440fx: style cleanup
    
    Drop unused and commented out variable, and fix a comment while at it.
    
    Change-Id: I1bd7d10aca949c8579433ea1c91264fd816a3fb4
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/3873
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 1e44c3ff5a08322afba3f52f5d9d88fb0ede9027
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Aug 16 10:14:38 2013 +0200

    Fix lint-stable target
    
    SEABIOS_PS2_TIMEOUT needs a default, otherwise the "allyesconfig" target
    hangs in an endless loop.
    The given default is correctly overridden by the (currently sole) user,
    the lenovo/x60 target.
    
    Change-Id: I3f5e347c29ccbb4d711a489d067b6c909f030bd0
    Reported-by: Kyösti Mälkki
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3874
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Tested-by: build bot (Jenkins)

commit 361cd8153d3426f2ba4f65ccb396e8e20e738068
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Aug 12 23:29:57 2013 +0300

    console: Squelch console output from AP CPUs in romstage
    
    Add Kconfig option SQUELCH_EARLY_SMP and have it enabled by
    default.
    
    Console drivers have unpredictable results if multiple threads
    attempt to share same resources without spinlock. Serial UARTs
    have not had huge problems, only distorted output, but those
    relying on cache-as-ram (CBMEM and usbdebug) may require this.
    
    Change-Id: I7f406fdea7b6dc6a341c4da2fab56f7b7ff568b4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3854
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 7037840ece7ed221990a8e683293408b81a4cfd1
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Thu Jul 4 03:06:26 2013 +0200

    w83627hf/acpi: Move floppy drive enumeration from _INI into _FDE.
    
    Move the floppy drive enumeration from _INI() and PROB(),
    which stored the enumeration results into _FDE into _FDE().
    _INI is called by any ACPI-capable OS on boot while _FDE
    is rarely used. So it's better to run the enumeration when
    requested rather than unconditionally.
    
    Change-Id: Icf1e2a551806592faa8ba8d80fa8d02681602007
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/3604
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bbf096911d8fefa86120230c97131efb8dd53244
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Sat Jul 6 17:09:39 2013 +0200

    w83627hf/acpi: Make `AddressMax` a multiple of `AddressAlignment`
    
    The parallel port of the W83627HF can be configured on any port
    between 0x100 and 0xFFC with 4 byte alignment for traditional modes
    and 8 byte alignment for EPP mode. As the ACPI specification says
    that the maximum acceptable starting address has to be a multiple
    of the alignment granularity, correct the maximum starting address
    from 0xFFC to 0xFF8.
    
    Change-Id: I272e09d091149791f2867b1d06e4fc27bc1bb2cd
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/2942
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c66f1cbdae6dced6410c0fc108cb0a1e3b3aa1e2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Aug 12 16:09:00 2013 +0300

    Include boot_cpu.c for romstage builds
    
    ROMCC boards were left unmodified.
    
    Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3853
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f040858ec31ffef5b746bb9856be6395a20c98ce
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Jul 9 19:43:09 2013 +0200

    payload/SeaBIOS: Add SEABIOS_PS2_TIMEOUT Kconfig variable
    
    This allows mainboards to preconfigure a ps2-keyboard-spinup
    timeout when SeaBIOS is chosen as the payload.
    
    The Kconfig option can be changed manually if CONFIG_EXPERT is set.
    
    Change-Id: I5732b18ef04f4bdef6236f35039656ad02011aec
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3734
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3bfd5b8252c4a188988c7f3441a3ba608ff46822
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Jul 9 19:39:13 2013 +0200

    cbfstool: Add an add-int command that adds a raw 64-bit integer CBFS file
    
    This simplifies storing SeaBIOS parameters in CBFS.
    
    Change-Id: I301644ba0d7a9cb5917c37a3b4ceddfa59e34e77
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3733
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a4e70578db9268c4f9847ba43e754f3e95d7a4e5
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Fri Aug 9 10:02:22 2013 +0200

    qemu: fix ioapic reservation
    
    The slightly hackish ioapic ressource reservation is needed for i440fx
    emulation only, for q35 the ich9 southbridge driver handles this just
    fine.
    
    [ Side note: The i440fx chipset emulated by qemu is pimped up with alot
                 of stuff which never existed on real hardware, which leads
                 to tweaks like this one. ]
    
    Change-Id: I06bf54cbc247ccf17aa9063fb7dee9def323c605
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3850
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1e1a1798faf9715ceb2bd34b619c3c21f03ce89a
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Apr 2 20:51:15 2013 +0200

    ASUS F2A85-M: Provide HD Audio verb table for Realtek ALC887-VD
    
    Use the same HD Audio [1] verb table for the Realtek ALC887-VD
    audio chip as the one set up by the proprietary vendor BIOS.
    Linux’ ALSA exposes this pin configuration under the virtual
    filesystem sysfs.
    
        /sys/class/sound/hwC1D0/init_pin_configs
    
    The script `alsa-info.sh` [2][3] is able to decode the table.
    
    Only one channel audio playback (rear connectors) is tested [4],
    which worked already before.
    
    [1] http://en.wikipedia.org/wiki/Intel_High_Definition_Audio
    [2] http://mailman.alsa-project.org/pipermail/alsa-devel/2013-March/060717.html
    [3] http://alsa-project.org/main/index.php/Help_To_Debug
    [4] http://review.coreboot.org/#/c/3170/2//COMMIT_MSG
    
    Change-Id: I17fa2d4ab1e1a6bfd84de94e9e4a91bd67b6a0c0
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3170
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 1ae7d475a82327b6a0f26f9ee34308a85c437b24
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat May 4 18:41:54 2013 +0200

    AMD Fam15tn boards: BiosCallOuts.c: Remove board name from `CodecTableList`
    
    The board name in that variable name is not necessary, as it is not board
    dependent, that means using the file as a template for making a new
    coreboot port for another motherboard the variable does not need to be
    changed, and just increases the code differences between AMD Parmer,
    AMD Thather and ASUS F2A85-M. So use a generic name.
    
    The same was done for AMD Persimmon (and inherited by the LiPPERT
    FrontRunner/Toucan-AF) in the following commit.
    
        commit 5e70766f14253f53190ddd49a544460c6bc1e528
        Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
        Date:   Tue Feb 26 15:56:11 2013 +0100
    
            AMD Fam14 boards: reduce unnecessary differences, 2nd attempt
    
            Reviewed-on: http://review.coreboot.org/2529
    
    The board name is *not* removed from the `CODEC_ENTRY` variable name as
    the verb table not only depends on the codec but also on the board [1].
    Having the board name in the variable name is a good indicator that the
    pin configuration needs to be adapted when taking this file as a template
    for a new port. If it was board independent, a default chip configuration
    could be used and shared between all boards, which is unfortunately not
    the case.
    
    [1] Unfortunately I was not able to find Jens’ comment in my mail archive
        and in the Gerrit Web interface. Not sure where it is, but I am sure
        he made that comment.
    
    Change-Id: I440a306cf4ff0a5b1b61d1983d70c66d129904d0
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3199
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit dc92d682ff8d5d2439f4c5cdc4e449bba6d651bb
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Thu Jul 4 03:41:39 2013 +0200

    w83627hf/acpi: Fix logical device power down in ACPI
    
    As Nico noticed for the W83627DHG, the power management bits to power down
    individual logical devices on Winbond superios are named counterintuitively
    and need to be set when the logical device should be powered.
    
    This corrects the power management methods for the W83627HF.
    
    Change-Id: I98bccd550a0513c62bfa9480275f88c566691bc8
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/3605
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit ec3a462d03527b2f4e620f43a5fa8fe518c5dee7
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Jul 1 04:34:29 2013 -0700

    CBFS: Change how the bss is zeroed when loading a stage.
    
    For reasons explained in a previous CL, it might be necessary to "load" a file
    from CBFS in place. The loading code in CBFS was, however, zeroing the area of
    memory the stage was about to be loaded into. When the CBFS data is located
    elsewhere this works fine, but when it isn't you end up clobbering the data
    you're trying to load. Also, there's no reason to zero memory we're about to
    load something into or have just loaded something into. This change makes it
    so that we only zero out the portion of the memory between what was
    loaded/decompressed and the final size of the stage in memory.
    
    Change-Id: If34df16bd74b2969583e11ef6a26eb4065842f57
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3579
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0c605a5a6cf0b5a7bdaa6068168581dc8fb24d22
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Jul 1 04:57:37 2013 -0700

    CBFS: Change the signature of cbfs_decompress.
    
    Instead of returning 0 on success and -1 on error, return the decompressed
    size of the data on success and 0 on error. The decompressed size is useful
    information to have that was being thrown away in that function.
    
    Change-Id: If787201aa61456b1e47feaf3a0071c753fa299a3
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3578
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f31eacca62bb9fda9ed05be941a336163f1ce146
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Jul 9 20:17:28 2013 +0200

    lenovo/t60 lenovo/x60: Default SEABIOS_PS2_TIMEOUT to 3 seconds
    
    The ThinkPad keyboard controller sometimes needs a while in order
    to initialize, so let's ask SeaBIOS to wait for it.
    
    This change ensures that the internal keyboard always functions
    correctly on the ThinkPad when coreboot is built with SeaBIOS as
    payload.
    
    Change-Id: I562475ec98b0c1f5d0debf6e9b597748a420f068
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3735
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 05d3f49fc67f6023f9bc64dbbce56cf4613c4ab9
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Tue Aug 6 10:48:41 2013 +0200

    qemu: reserve ports
    
    QEMU has a bunch of non-standard virtual devices on various I/O ports.
    Allocate resources for them so the coreboot resource management knows
    those ports are used.
    
    Change-Id: I51a85967cf2dcd634b0c883210bb52c0c34c8283
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3851
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 42e11f5a03480f6bc4a7dc54dd87bea4e850042a
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Mon Jul 8 18:19:08 2013 -0600

    AMD Richland: Add new graphics device IDs to Family 15, Models 10-1F
    
    Change-Id: Ic7fdedc0a22e7664f14b105f2f7cecd8f55980be
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3857
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 9e8690b43f4978760ba9464ffdd63d36506fc06a
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Thu Jul 18 10:30:47 2013 -0600

    AMD Fam16: Add OSC method to PCI0
    
    The _OSC method is used to tell the OS what capabilities it can
    take control over from the firmware.  This method is described
    in chapter 6.2.9 of the ACPI spec v3.0.  The method takes 4
    inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and
    returns a Capabilites Buffer the same size as the input Buffer.
    This Buffer is generally 3 Dwords long consisting of an Errors
    Dword, a Supported Capabilities Dword, and a Control Dword.
    The OS will request control of certain capabilities and the
    firmware must grant or deny control of those features.  We do not
    want to have control over anything so let the OS control as much
    as it can.
    
    The _OSC method is required for PCIe devices.  During Linux boot,
    an error is logged to dmesg if _OSC is not found.
    
    Change-Id: Icf6e7a82284d03d23fd30ee7b7db17754e988c9a
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3823
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 6cf5c8ee655ab80d897b7a86bfc4dbde6fb462d5
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Thu Jul 18 10:16:31 2013 -0600

    AMD Fam16: Add secondary bus number to CRES method
    
    Adding the 'WordBusNumber' macro to the PCI0
    CRES ResourceTemplate in the AMD FCH ACPI code.
    This sets up the bus number for the PCI0 device
    and the secondary bus number in the CRS method.
    This change came in response to a 'dmesg' error
    which states:
    '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
    
    By adding the 'WordBusNumber' macro, ACPI can set
    up a valid range for the PCIe downstream busses,
    thereby relieving the Linux kernel from "guessing"
    the valid range based off _BBN or assuming [0-0xFF].
    The Linux kernel code that checks this bus range is
    in `drivers/acpi/pci_root.c`.  PCI busses can have
    up to 256 secondary busses connected to them via
    a PCI-PCI bridge.  However, these busses do not
    have to be sequentially numbered, so leaving out a
    section of the range (eg. allowing [0-0x7F]) will
    unnecessarily restrict the downstream busses.
    
    Change-Id: Ib2d36f69a26b715798ef1ea17deb0905fa0cad87
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3822
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit ac90d8013a26d99df21cb555bb313506ce32979c
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Wed Jul 17 15:14:59 2013 -0600

    AMD Kabini: Split DSDT into common sections
    
    Split the Family16 (Kabini) DSDT file into logical regions.
    Olive Hill is the only mainboard and Kabini is the only NB/CPU
    currently using Family16 AGESA code.
    
    Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3821
    Tested-by: build bot (Jenkins)

commit 81c70fb142326fe9e5ac5391cdd45f93c984e3e6
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Tue Aug 13 16:37:56 2013 +0800

    dmp/vortex86ex: Initialize Reatek ALC262 audio codec
    
    Hook this up into the DMP Vortex86EX. Before under Windows XP
    the microphone did not work. With the new logic it does. Now
    line-in,line-out and microphone all work.
    
    The verb data table is generated by Realtek.
    
    Change-Id: I1bcef898a15547c86c12c4b52ce0069d13e23c84
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3855
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit b7bb70d3de1653275413f4b4e88bc01f9c570d48
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Mon Aug 12 20:07:47 2013 +0800

    Add a generic Intel HD audio (Azalia) module azalia_device.c
    
    This module uses cim_verb_data to detect and initialize HD audio
    codecs.
    The module source code is based on southbridge/intel/sch/audio.c and
    southbridge/nvidia/mcp55/azalia.c.
    
    Change-Id: I810fef6fdcf55d66f62da58c3d7d99f006559d6e
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3844
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 9361daf7fdaa6a4fa81c06e4cdfb7b42b2915051
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Fri Aug 2 14:45:03 2013 +0800

    Fix some wait_for_valid functions return value from 1 to -1.
    
    codec_init expects wait_for_valid returns -1 for timeout, not 1.
    
    Change-Id: I0f2a3ebb1934d0adaf13765434526bbc9efca9a3
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3843
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3be80cce290e3ff2da6abc30addab79f5a5ffa07
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 6 10:46:37 2013 +0300

    usbdebug: Add option for verbose logging of connection
    
    Add option to log changes in USB 2.0 EHCI debug port connection.
    For romstage move usbdebug as the last initialised console so one
    actually can see these messages.
    
    Init order of consoles in ramstage is undetermined and unchanged.
    
    Change-Id: I3aceec8a93064bd952886839569e9f5beb6c5720
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3387
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit a9bbdd39e420d7d99323a28e24636d1a849effa3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Aug 9 02:24:05 2013 +0300

    usbdebug: Fix AMD cimx/sb700 cimx/sb800
    
    These Kconfig entries were forgotten from the commit
    that re-enabled usbdebug for these southbridges.
    
    Change-Id: Ia17f1dd3340408da7c033c2c949404d2636bed44
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3849
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit fd98c65b9d89e1ca665e25b6abf6d2019855e85a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 26 08:50:53 2013 +0300

    intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses
    
    Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
    the pcie explicit accesses. The default config accesses use
    MMIO.
    
    Change-Id: I58c4b021ac87a035ac2ec2b6b110b75e6d263ab4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3810
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 0cc33da5530cf2ef776fc9fa2dbb80bb4dc4c830
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Sat Jul 20 14:28:10 2013 -0600

    ASUS F2A85-M: Split DSDT into common sections (as per Parmer)
    
    Rearranged the F2A85-M DSDT file to match the functionality found
    on Parmer.  As with the Parmer implementation, the F2A85-M dsdt.asl
    file in the mainboard directory contains only #include references to
    the appropriate files.
    
    As with Parmer, some include files have no content but are left as a
    template for other platforms and as placeholders for completing the
    ACPI implementation for F2A85-M.
    
    Change-Id: Ic72cb6004538ca9d9f79826b9b3c8d6aeb25017c
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3805
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>

commit 436a3753ec14f8bde3eb3063b6563e32c1dd72e7
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Sat Jul 20 11:20:18 2013 -0600

    AMD Thatcher: Split DSDT into common sections (as per Parmer)
    
    Rearranged the Thatcher DSDT file to match the functionality found
    on Parmer.  As with the Parmer implementation, the Thatcher dsdt.asl
    file in the mainboard directory contains only #include references to
    the appropriate files.
    
    As with Parmer, some include files have no content but are left as a
    template for other platforms and as placeholders for completing the
    ACPI implementation for Thatcher.
    
    Change-Id: Ie44a32959cc547840914365e872416d4624d33df
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3804
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>

commit 0010bf60a63298700292de40e437d5927a73d49f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jun 11 16:32:01 2013 +0300

    usbdebug: Support AMD cimx/sb700 cimx/sb800 once again
    
    Support code for sb700 and sb800 existed already, but Kconfig and
    compile-time issues prevented from enabling USBDEBUG for boards
    with the affected AMD southbridges.
    
    Change-Id: I49e955fcc6e54927320b9dc7f62ea00c55c3cedf
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3439
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 1fd750812193cbaab7f54696b97a91bf727e87e3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jun 11 16:32:01 2013 +0300

    usbdebug: Use __SIMPLE_DEVICE__ on early enable
    
    With USBDEBUG selected, the file is built for both romstage and
    ramstage. For the ramstage build, we need to explicitly use the
    simple PCI config operations without devicetree.
    
    Change-Id: I2de8d9c77bb458ba797c3aac9e2cd0d653e06684
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3437
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit da940c58357eb45232d808a334879474c33be886
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 31 20:52:04 2013 +0300

    Make EARLY_CONSOLE optional
    
    This change brings back the possibility to disable console
    output while in romstage, like before commit d2f45c65.
    
    For some platforms (AMD multi-socket) USBDEBUG and/or CBMEM
    CONSOLE do not work correctly for romstage due the way
    cache-as-ram is set up, but might already work for ramstage.
    
    Change-Id: Id8d830e02a18129af419d3b5860866acf315d531
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3846
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit cec611a0ea6dc3bb79e409f3f49a58ec1db81dc1
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Jul 30 04:17:37 2013 -0600

    AMD AGESA: Fix comment for `PCIE_DDI_DATA_INITIALIZER`
    
    Copied from a similar commit for Family 10h AGESA [1]
    
    Remove the fourth argument in the comments. Luckily the compiler,
    at least gcc, warns about a wrong number of arguments, and therefore
    no incorrect code resulted from the wrong documentation.
    
    [1] 07e0f1b AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in comments
    [2] fc47bfa Revert "AMD f14 vendorcode: Fix warning"
    
    Change-Id: I3806e368a823e4a40d22e99b91bf3598d9ed2f15
    Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3840
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>

commit 5697df2a84b52f0979d4807fc293dea311e46662
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 14:14:14 2013 -0600

    AMD AGESA: Add missing breaks to switch statement in one file
    
    This is the same patch as an earlier one applied to family 15 [1].
    
    Static analysis often flags case statements that do not include
    a terminating "break;" statement. Eclipse's CODAN is an example
    of this.  This changelist modifies amdlib.c to terminate
    case statements with "break;".
    
    [1] e44a89f amd/agesa/f15/Lib/amdlib.c: Add missing breaks ...
    
    Change-Id: Ibd1ae6f2b52fde07de3d978d174975f4d93647ab
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3839
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>

commit ee7cd8d85d3339291d8f5e72d2d35798164ac0bb
Author: Bruce Griffith <bruce.griffith@se-eng.com>
Date:   Tue Jul 23 21:43:52 2013 -0600

    AMD Olive Hill: Enable WARNINGS_ARE_ERRORS (remove override)
    
    Change-Id: Idf26eb3fb541355bd9553c1897f647738c347eb5
    Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3819
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 4e08a95d2601d7b9ec05f0cb15746d7afb7100d9
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Sun Jul 7 02:04:16 2013 -0600

    AMD Olive Hill: Change SB800 references to Yangtze
    
    Change-Id: I7f6f6ff444fda4bdf233db1383919772afe6b635
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3815
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>

commit effc8d087d56fbdd79fabe77c30146f1e0edb2a7
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Aug 6 03:50:28 2013 -0600

    AMD Olive Hill: Add HUDSON_LEGACY_FREE flag
    
    Olive Hill does not have a Super I/O or keyboard controller.
    
    Change-Id: I8c1e5d8c20c4a964fe8d98df920b416382a26d9d
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3848
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>

commit 2b56e85a50a6383480a5f4d696ff51b04c72a9a6
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Mon Jul 8 11:33:45 2013 -0600

    AMD Olive Hill: Remove default VBIOS vendor/device ID
    
    The VBIOS device ID is set by processor family using the
    map_oprom_vendev() function in the northbridge code.  There
    is rarely a reason why this should be overridden by the mainboard.
    Since Kabini includes a default VBIOS vendor/device ID in the
    northbridge Kconfig code, remove the setting from the Olive Hill
    mainboard settings.
    
    Change-Id: Icd69155f5b51105d564dd82c89e4bb54a6118a82
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3816
    Tested-by: build bot (Jenkins)

commit aea318f35d13e1859efa82f664df01c8c13657c1
Author: Bruce Griffith <bruce.griffith@se-eng.com>
Date:   Mon Jul 29 02:34:26 2013 -0600

    AMD Kabini: Add "const" modifier to AGESA function parameters
    
    Add CONST modifiers to read-only pass-by-reference function
    parameters in AGESA.  This allows the use of "const" modifiers
    on the declaration of lookup tables that are pass-by-reference.
    These will be used to identify tables that are copied onto the
    HEAP but don't need to be.
    
    This same change was made for AMD Trinity APUs (Family15tn) [1].
    
    [1] 283ba78 AGESA: Add "const" modifier to function parameters
    
    Change-Id: I2bdd9fc5e027e938de9df0f923b95da934bb48dc
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3837
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit abebe80161a03c65b22088c7151f01b6681559a5
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Apr 28 14:44:08 2013 +0200

    AMD SATA: Correct "them implement" to "then implement" in comments
    
    This changelist was cherry-picked from merged community code
    for Parmer [1] and the paths modified so that the Parmer
    modification is applied against Olive Hill.
    
    [1] 0086162 AMD SATA: Correct _them implement_ ... in comments
    
    Change-Id: I9849e9a75dacfde15331c4200d72343a59036f14
    Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3841
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 76db07e8c20b1e419ceeaf14eb23c7675839067a
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Sun Jul 7 02:06:53 2013 -0600

    AMD Kabini: Add map_oprom() function for Vendor/Device IDs
    
    Change-Id: I14285f0677003fbf8b9b112207af202658807894
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3806
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 17933e8bc17f04a876a51198dabcc2363f4ee334
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Wed Jul 10 01:26:26 2013 -0600

    AMD Olive Hill: Enable HDMI audio setting in build options
    
    Change-Id: Ifc180e6fcd594dbedc2512ea5bef283a3ad689d3
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3814
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 5912125dffcbe8a1b1ab4d1198c5ff2c9bc0771c
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Wed Jul 10 22:24:47 2013 -0600

    AMD Olive Hill: Eliminate unnecessary memory copy
    
    Eliminate an unnecessary copy of the DDI descriptor list and
    the PCIe port descriptor list.  As descriptor tables, these
    tables do not need dynamic updating and should be used from
    ROM without runtime copying.
    
    There will be a corresponding patch for AGESA that adds CONST
    modifiers to function parameters that are pass-by-reference
    "IN" values (read-only pointers).
    
    Change-Id: I7ab78e58041e9247db22d0f97a6f76d45f338db0
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3818
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 80cf7d5956283b5c79b293d2ffac82f329f6203c
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Tue Jul 9 17:42:43 2013 +0800

    AMD Olive Hill: Add new AMD mainboard using Kabini processor
    
    Change-Id: I1f252b67c039d28df96e8dfd458a1ca6a7dbc816
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3784
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 37a1d6c9552b267c06c471cced5928d2385767e2
Author: Bruce Griffith <bruce.griffith@se-eng.com>
Date:   Tue Jul 23 11:50:12 2013 -0600

    AMD Hudson/Yangtze: Enable support for SATA port multipliers
    
    This patch sets a bit in the Yangtze southbridge to enable
    the extra protocol necessary to handle port multiplier chips.
    This has been turned on during most of Kabini development
    without any notable impact. Olive Hill has an optional daughter
    board that incorporates Silicon Image Steel Vines chips.  This
    change has been tested with and without the daughter board.  This
    change can be regression tested using any Hudson-based motherboard,
    although it has no impact on boards with discreet Hudson/Bolton
    southbridges.
    
    This was tested for impact on SATA performance in the absence of
    a port multiplier using the IOZone benchmarks within the Phoronix
    Test Suite.  A SATA 3 hard drive (6.0 Gbps) and an SSD were
    connected to the ports on Olive Hill without using the port
    multiplier card.  The test results contained more run-to-run
    variation within the same configuration than was seen in the
    aggregate results comparing the interface with and without the
    port multiplier protocol additions.  In other words, the test
    had less accuracy than the impact caused by turning on port
    multiplier support.
    
    Change-Id: Ie87873b093f3e2a6a5c83b96ccb6c898d3e25f72
    Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3808
    Tested-by: build bot (Jenkins)

commit 915714501bc411f83717b41ebf269fc82a5e9657
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Tue Jul 9 17:32:42 2013 +0800

    AMD Kabini: Modify Hudson southbridge to support new AMD processor
    
    Yangtze uses Hudson AGESA wrapper code but has some changes.
    The changes are necessary and have no effects on Hudson.
    
    Change-Id: Iada90d34fdc2025bd14f566488ee12810a28ac0d
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3783
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 3e32cc00d1984e7a0d01039577e5aa6ae3b2aa81
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Tue Jul 9 17:16:20 2013 +0800

    AMD Kabini: Add northbridge AGESA wrapper (new AMD processor)
    
    src/arch/x86/boot/tables.c and src/include/device/pci_ids.h are also
    changed because these two files depend on F16kb northbridge macros
    
    Change-Id: Iedc842f0b230826675703fc78ed8001a978319c5
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3782
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 5d7d09c4abfd60bebb7f17df3dce105fc22e9b92
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Tue Jul 9 17:08:41 2013 +0800

    AMD Kabini: Add CPU AGESA wrapper for new AMD processor family
    
    Change-Id: I4a1d2118aeb2895f3c2acea5e792fbd69c855156
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
    Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3781
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit affe85fbc8a13d35960aa92ae87cbb6330ad253f
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Thu Jul 25 15:14:15 2013 +0800

    AMD Kabini: Add AGESA/PI code for new processor family
    
    Change-Id: Icb6f64e2e3cfd678fb4fb4f13f0e4b678d5acc4a
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Nick Dill <nick.dill@se-eng.com>
    Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3836
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit ae8d06969bdde9b1250bc3c4ad93f5db408dae98
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Fri Aug 2 19:29:17 2013 +0800

    Remove unnecessary space characters.
    
    Change-Id: I4ed9329126b216eb4ae58355672603ce79a6d4ef
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3847
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 386b3e631fe0e2cacc6c936eb66b9a19c4f927cd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 26 08:52:49 2013 +0300

    intel/lynxpoint: remove explicit pcie config accesses
    
    Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
    the pcie explicit accesses. The default config accesses use
    MMIO.
    
    Change-Id: I71923790aa03e51db01ae3a4745e1c44556d281f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3812
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit ef844011491df76eb4976905f2037732e0520295
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jun 25 23:17:43 2013 +0300

    Add directive __SIMPLE_DEVICE__
    
    The tests for __PRE_RAM__ or __SMM__ were repeatedly used
    for detection if dev->ops in the devicetree are not available
    and simple device model functions need be used.
    
    If a source file build for ramstage had __PRE_RAM__ inserted
    at the beginning, the struct device would no longer match the
    allocation the object had taken. This problem is fixed by
    replacing such cases with explicit __SIMPLE_DEVICE__.
    
    Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3555
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 0aede1185be6298bbc9501a0c596e64617bad58b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jul 29 12:43:06 2013 -0700

    Drop unused EXTERNAL_MRC_BLOB
    
    The Kconfig variable EXTERNAL_MRC_BLOB is not used.
    Drop it.
    
    Change-Id: I3caa5c2b6bcf5d2c13b6987da8ab3987bad0e506
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3829
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 71216c9bcdca6036f1032f09cdea64c9823efcf6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jul 28 23:39:37 2013 +0300

    Makefile: Fix adding intel/common
    
    Directory intel/common must be conditionally added in the list
    of source directories, as the parent directory southbridge/intel
    is unconditionally added even for boards without such device.
    
    Change-Id: I7088bc6db9f56909ffa996aa7eff76cd72e177eb
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3827
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit e23c22dd88b421df21d7ee3aff18e67eb5e047c6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jul 28 23:16:47 2013 +0300

    usbdebug: Fix missing include
    
    Change-Id: I74d28c13e6597c56e3b85ccd2b83386b86c200f0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3828
    Tested-by: build bot (Jenkins)

commit 8eaf1e765d811ec61ba28fec26db1541904b0eed
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jul 28 20:39:40 2013 +0300

    cpu/intel/model_67x: Add missing include
    
    The added device.h file was indirectly picked from cpu.h, which will
    have this include removed in a follow-up patch.
    
    Change-Id: Ifc0a4800de3b1ef220ab1034934f583be8c527b0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3826
    Tested-by: build bot (Jenkins)

commit 696561c2a4813d9dd1f0b54726553fb5f5e45714
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Jul 15 12:31:21 2013 +0200

    kontron/ktqm77: Update cmos checksum range
    
    Change-Id: I08e56b4a1c56128c6d4beb751979c5b99cdae829
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3790
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ca4f073f8ee3b7d2bf4d7f1ca63fc5957e6feae2
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jul 18 12:27:00 2013 +0200

    ec/kontron/it8516e: Add sanity checks for values from nvram
    
    Change-Id: Ie52d80fc8657064efdcec51c31dc9309fcc28121
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3787
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1f9f67864ab3d16beba3d6835d09ce44d4812989
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jul 18 11:50:59 2013 +0200

    ec/kontron/it8516e: Comment low-level EC functions
    
    Change-Id: I5f75998356554e08f8c9920e7612494e4710ab15
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3786
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 260c33ba5619dba58c6e32ba998931325fe8086c
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jul 18 11:27:30 2013 +0200

    ec/kontron/it8516e: Remove some unsafe bit shifting
    
    The EC expects the temperature in 64ths degree C. Alter
    it8516e_set_fan_temperature() to just export this interface and
    make the calculation more obvious.
    
    Change-Id: Ibe241b7909f4c02b30b1e1200a1850d47695a765
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3785
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8e1a7cc06fa596516dee5e083106f2ef4cd1c39f
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Jul 12 14:47:50 2013 +0200

    kontron/ktqm77: Squeeze more fan options into cmos.layout
    
    Change-Id: Ic660efec519a9a970ec5a8832fd1dd8c9516318f
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3775
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9ce71b3cca0b59fdc262d89dafc8f75efbc167a6
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Jul 12 14:43:11 2013 +0200

    ec/kontron/it8516e: Add PWM limits option
    
    Add an option to set minimal and maximal PWM percentages when the fan is
    in temperature controlled mode. Also fix a non-ascii flaw.
    
    Change-Id: I85ae244bee2145bf17d6c29e93dd4871540985c8
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3774
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 942b6c2117816dcabdf15109b68aca33edee89c9
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Jul 12 14:40:23 2013 +0200

    ec/kontron/it8516e: Correct fan setting for PWM mode
    
    The EC firmware expects a 255th while we provide a percentage.
    
    Change-Id: Ib06a061b431ac728329043179800729e39e6166b
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3773
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6d6a2ac0559a324603d1c323239e2e6e6e58af77
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Jul 12 14:35:00 2013 +0200

    ec/kontron/it8516e: Add option for external temperature sensor
    
    The IT8516E firmware of Kontron supports some selected external sensors
    attached to the EC via SMBUS or GPIO16.
    
    Change-Id: I4c451c360a393e916430e3bea04a95847455cef7
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3772
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 933b5df6a84d0eaf25b035aef83351f1506c3aa1
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Wed Jul 24 09:56:03 2013 -0600

    AMD Parmer: Fix file permissions on asl files in mainboard
    
    Removed the execute bit on all files in mainboard/amd/parmer/acpi
    
    Change-Id: I85ffa66e0beb9c4bfe826b72968f7f633c224487
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3807
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit b9646a2bdc1c29961a326fc7f657433067d53ff0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 3 08:06:32 2013 +0300

    emulation/qemu-q35: Use MMCONF_SUPPORT_DEFAULT
    
    Change all PCI configuration accesses to MMIO in qemu-q35
    emulation
    
    To enable MMIO style access, add (move) explicit PCI IO config write
    in the bootblock. As there is no northbridge/x/x/bootblock.c
    file, a mainboard/x/x/bootblock.c file is added for this purpose.
    
    Change-Id: I979efb3d9b2f359a9ccbd1b4f6c05f83bab43007
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3599
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit aad0747216cab56a8cee5c1401c094543ed8be2d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 4 17:17:45 2013 +0300

    Redefine pci_bus_default_ops as function
    
    Taking device_t as a parameter, this allows to alter the PCI config
    access handlers. This is useful to add tracing of PCI config writes
    for devices having problems to initialise correctly.
    
    On older AMD platform PCI MMIO may not be able to fully configure all
    PCI devices/nodes, while MMIO_SUPPORT_DEFAULT would be preferred due
    to its atomic nature. So those can be forced to IO config instead.
    
    Change-Id: I2162884185bbfe461b036caf737980b45a51e522
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3608
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 026ff3e436799b54daec8805dc574146793f4903
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 8 18:11:44 2013 +0300

    usbdebug: Split endpoint buffers
    
    Refactor the structure to better support receive and another
    set of endpoints over usbdebug.
    
    Change-Id: Ib0f76afdf4e638363ff30c67010920142c58f250
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3726
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit dcea700762bc97bd7fcabf2e960d47805129aeb1
Author: Damien Zammit <damien@zamaudio.com>
Date:   Wed Jul 17 23:59:40 2013 +1000

    inteltool: Print raw CPUID and make hexadecimal values unambiguous
    
    The raw CPUID is useful for matching the directories under 'src/cpu/intel'
    and is not easy to find out otherwise because it is most often decoded
    already. The decoded values are not obviously hexadecimal so prepend
    them with 0x to make sure they are unambiguous.
    
    The output differences look like this:
    -	CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
    +	CPU: ID 0x20652, Processor Type 0x0, Family 0x6, Model 0x25, Stepping 0x2
    
    Change-Id: Id47f0b00f8db931f0000451c8f63ac1e966442c4
    Signed-off-by: Damien Zammit <damien@zamaudio.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3788
    Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
    Tested-by: build bot (Jenkins)

commit 0d2119da465fac01949385a74fc4ff4896550842
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jul 10 14:27:56 2013 -0700

    buildgcc: Update reference toolchain
    
     * GCC 4.8.1
     * binutils 2.23.2
     * GDB 7.6
     * ACPICA 20130626
     * Python 3.3.2
    
    ... this adds support for Aarch64. For Ron.
    
    Change-Id: Idec91bcd615bc35c83373bd23d4681f1c8eb015c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3758
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b5e777c433642950fbe6e907a234995ed7f34b8d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jul 22 20:17:18 2013 +0200

    X86: make the SIPI num_starts a config variable
    
    The code to figure out how to set num_starts was
    starting to get kludgy. It's a constant for a given
    CPU; constants should be constant; make it a config variable.
    
    This change includes an example of how to override it.
    Build but not boot tested; drivers welcome.
    
    Change-Id: Iddd906a707bb16251615c7b42f2bfb5a044379b4
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3796
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit 4c2ebeba78e437df2d156a4c68f1fb15b62926f5
Author: Damien Zammit <damien@zamaudio.com>
Date:   Sat Jul 20 17:44:15 2013 +1000

    it8728f: Add ITE IT8728F superio early serial support.
    
    This is the first of a series of patches to provide support
    for a new mainboard, Gigabyte GA-B75M-D3V.
    
    This patch provides early serial for the superio and has been
    tested on this mainboard.  The code is based on IT8718F superio.
    
    Change-Id: I5636199b49314166ed3b81e60b41131964dd44ff
    Signed-off-by: Damien Zammit <damien@zamaudio.com>
    Reviewed-on: http://review.coreboot.org/3794
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit ed621ada6309004c54ab922f2b4143427d6d1a84
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Thu Jul 11 02:17:01 2013 -0600

    AMD Yangtze: Update 3rdparty hash for new blobs
    
    Change-Id: I87de13a7284bc38ac7cf2b18a147323c84a9a5c5
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3780
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c71ac38b1f1b8d89d0a06801c99952e1f4fdb0e4
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Jul 9 19:37:20 2013 +0200

    SMBIOS: Clarify prompts and help texts for Serial and Version Numbers
    
    Change-Id: If1fa39db79eeecbef90c8695143d2fe2adf2f21a
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3732
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

commit be8b99de73797a6e75ec98603c529985249f11d8
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Jul 17 22:07:10 2013 +0200

    Revert "lenovo/x60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String"
    
    This reverts commit cd24e3f6a7adecfc9d3b2a2dd2f81d84acffa91b.
    
    Change-Id: I3d1fec75d99d0b480a47b4d433c14a681831d9f8
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3778
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit cd24e3f6a7adecfc9d3b2a2dd2f81d84acffa91b
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jul 6 20:10:36 2013 +0200

    lenovo/x60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String
    
    The Linux thinkpad_acpi.c driver looks for this string while
    reading information about the system it is running on.
    
    This commit does not make the module load but it is one of
    several things that the module looks for on a ThinkPad.
    
    The use of 3 defines for the serial number template
    seems odd but it's done in a way that eliminates
    magic numbers, yet avoids use of strcpy, strlen,
    strindex, strchr, or strspan: we can have some
    correctness assured at compile time. Also, the
    defines can be copy/pasted for other mainboards
    and we should void errors due to people not changing
    magic numbers.
    
    Change-Id: Ief5f28d2e27bf959cb579c4c8eea9eecc9a89a7c
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3620
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5d8474329755905842b692eb70fa61a60e943661
Author: Gabe Black <gabeblack@chromium.org>
Date:   Sun Jul 14 23:17:32 2013 -0700

    beaglebone: Get rid of a redundant CBFS_ROM_OFFSET.
    
    CBFS_ROM_OFFSET was declared in both the am335x config and the beaglebone
    config. This removes it from the beaglebone config.
    
    Change-Id: I657cb8e83a1ee961d8bdc995a41f303920bc53f9
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3771
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit bf0988b0a2fb761fa7afa1574afba1d16b81eb85
Author: Steve Goodrich <steve.goodrich@se-eng.com>
Date:   Wed Jul 10 11:59:11 2013 -0600

    AMD Fam15tn: Split DSDT into common sections
    
    Split the Parmer, Family 15tn, and Hudson DSDT into groups.  This splits
    the DSDT table into includable ASL files which carry details specific
    to the Family 15tn APU, the Parmer platform, and the Hudson FCH.  The
    dsdt.asl file in the mainboard directory contains only #include
    references to the appropriate files.
    
    Initially, this split was done by moving each piece of functionality
    into its own file (e.g. IRQ routing and mapping, processor tree, sleep
    states and sleep methods, etc.) and those pieces were #included in
    dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d)
    with the extant version of the table.  Once the new tables were found
    to exactly match the existing tables, the pieces were rearranged into
    reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.).
    
    Some include files have no content but are left as a template for
    other platforms and as placeholders for completing the ACPI
    implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl,
    sata.asl, etc.).
    
    Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710
    Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3629
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit c6b44162f5cccd72e9b4d9dbf071911249971846
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Jul 1 04:28:23 2013 -0700

    CBFS: Use memmove instead of memcpy when loading a file from CBFS.
    
    It might be the case that a file is being loaded from a portion of CBFS which
    has already been loaded into a limitted bit of memory somewhere, and we want
    to load that file in place, effectively, so that it's original location in
    CBFS overlaps with its new location. That's only guaranteed to work if you use
    memmove instead of memcpy.
    
    Change-Id: Id550138c875907749fff05f330fcd2fb5f9ed924
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3577
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 630e4e8c7efa6306fb831cb1c9b6cabd53747a5a
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Jul 1 05:38:45 2013 -0700

    am335x: Make the default media for the bootblock sram instead of NAND flash.
    
    The SOC's built in ROM loads the bootblock and the ROM stage into the on chip
    memory before handing over control to the bootblock. To avoid having to add
    one or more driver to the bootblock so that it can re-load the ROM stage from
    whatever media Coreboot is stored on, we can just take advantage of the copy
    that's already there. Loading the RAM stage/payloads won't be so simple,
    so the ROM stage and the RAM stage will have to have different media drivers.
    
    Change-Id: Id74ed4bc3afd2063277a36e666080522af2305dd
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3583
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6cfe223da0ac786e1aaf675fbb5dc605e600bb75
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Jul 1 05:16:19 2013 -0700

    am335x: Add the config variable ROMSTAGE_BASE to the CPU's Kconfig.
    
    This variable wasn't being defined and was defaulting to zero when used in the
    ROM stage's linker script. This change defines it as a variable, and gives it
    a value which is slightly beyond the end of the bootblock. By making the ROM
    stage request to be loaded slightly farther into memory than it was loaded by
    the SOC's masked ROM, we ensure that it's moved away from the stage's metadata
    instead of on top of it. When it moves the other way, it clobbers important
    values like the entry point vefore the bootblock has had a chance to use them.
    
    Change-Id: I027a1365d05f1d79d7fc1e1349965ccb7d4e81b9
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3582
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 81cbadadc13a73220e8a02d47c2d0a182fa5b22f
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Jul 1 05:12:40 2013 -0700

    beaglebone: Put some code in romstage.c so we can tell if it ran.
    
    The placeholder code in beaglebone's romstage.c didn't do anything, it just
    immediately tried to load the RAM stage and jump into it. That doesn't
    currently work, and there's no indication whether you actually successfully
    got into the ROM stage or not.
    
    This change adds a few lines which initialize the console and say "Hi" so that
    we can tell that the ROM stage is running.
    
    Change-Id: I45a0908c3ac65b21e0e5020428696d2e54933d0e
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3581
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 978c21512751c50ad92d459cbca39d98d9fc39a9
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Jul 1 05:03:47 2013 -0700

    ARM: Define custom ELF headers for ARM.
    
    At least when building with the gnu toolchain, the headers the linker
    automatically generate save space for the actual ELF headers in one of the
    loadable segments. This creates two problems. First, the data you intended to
    be at the start of the image doesn't actually show up there, it's actually the
    ELF headers. Second, the ELF headers are essentially useless for firmware
    since there's currently nothing to tell you where they are, and even if there
    was, there isn't much of a reason to look at them. They're useful in userspace
    for, for instance, the dynamic linker, but not really in firmware.
    
    This change adds a PHDRS construct to each of the linker scripts used on ARM
    which define a single segment called to_load which does not have the flag set
    which would tell the linker to put headers in it. The first section defined in
    the script has ": to_load" to tell the linker which segment to put it in, and
    from that point on the other sections go in there by default.
    
    Change-Id: I24b721eb436d17afd234002ae82f9166d2fcf65d
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3580
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c392b6477f656331c7e19b22f6eb240cdd5465a1
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jul 6 19:51:12 2013 +0200

    SMBIOS: Add smbios_write_type11() for creating an OEM Strings structure
    
    Change-Id: Id338968429435bac26595c4843b07cdbb91dd64d
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3618
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4e7385b58fcff0f59db6f0c4852a57e74f0d3b00
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Oct 4 21:18:13 2012 +0200

    SMBIOS: Allow overriding default Manufacturer and Product names
    
    The vendor and part name from coreboot is normally stored in these
    SMBIOS structure fields, but it can be useful to override them.
    
    On Lenovo ThinkPads an override is e.g. needed to convince the Linux
    thinkpad_acpi.c driver that it is actually running on a ThinkPad.
    
    Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/1556
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

commit d98cef1956aefecdfeba652085f301ea07118147
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Jul 9 20:44:52 2013 +0200

    lenovo/t60 lenovo/x60: Override SMBIOS Manufacturer to be LENOVO
    
    This is needed for the Linux thinkpad_acpi.c driver to load.
    
    Change-Id: I3d9549395556ffb0abfc3cb52b3d01386c34caa5
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3731
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7a6651ceb3ede6b35053ad65358d6994facc217e
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jul 7 14:15:22 2013 -0700

    arm: Add and enable an arch specific version of memmove.
    
    This version is taken from arch/arm/lib/memmove.S in the Linux kernel.
    
    Change-Id: Ic875d0cf5b1cb407606530b7f465c406b134f0fa
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3763
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ccdc005b015f4211d0fa0d45393c5e4104620c53
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jul 7 14:08:30 2013 -0700

    x86: Add and enable an arch verson of memmove.
    
    This is from memcpy_32.c in the Linux kernel. There was no copyright header
    in the original file either.
    
    Change-Id: Ifd259cb8a87615dce79ed1e551cc4bacb0414b4f
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3762
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 545c0caac8ff5cc5c8cc80b1c4d6dce5a2e17032
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jul 7 14:04:26 2013 -0700

    Add a HAVE_ARCH_MEMMOVE option to allow overriding memmove.
    
    Change-Id: I4b6a57e7d8e7e685c609b1d85368585b9dd197dc
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3761
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit eac991629f40bdb0d0d80319249dd378a295e6fa
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jul 6 20:05:13 2013 +0200

    lenovo/x60: Move mainboard_enable() code into a mainboard_init()
    
    mainboard_enable() is now modelled after google/parrot where the
    enable function only sets dev->ops->init for the root device to
    point to a mainboard_init() function, which in turn is called in a
    later pass over the device tree to do the actual initialization.
    
    Change-Id: Iaf9187532a1e432b991260201b95dda85cc312c5
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3619
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9478297afb0bad081798e716edf29a00f1ef71a1
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Jun 29 11:41:27 2013 +0200

    src/southbridge/intel/{lynxpoint,bd82x6x}/spi.c: correct spelling of attempted
    
    Change-Id: Ic6f6af6298fed2f41f140a7aa62dccf98bf60927
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3572
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Jul 8 16:23:54 2013 -0600

    cpu: Fix spelling
    
    Change-Id: I69c46648de0689e9bed84c7726906024ad65e769
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3729
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0cb07e3476d9408d0935253f9f26c0a8ddc28401
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Tue Jul 9 21:46:01 2013 -0600

    include: Fix spelling
    
    Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3755
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cbe2edefb93ed3ba0a4b08f72a9b208429920675
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 11 07:49:46 2013 +0300

    usbdebug: Cleanup dbgp_ehci_info call
    
    Change-Id: I9cad64796fcfb7a50d9ed9ec95c56ab855c872e3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3766
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 2c516ed3f3074588182b00dce4cfbe02206519dd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 11 06:43:43 2013 +0300

    usbdebug: Drop old includes
    
    Change-Id: I4786bff41fef924c72087c354e394bdc1996cadc
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3764
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 5fbfc911c159dc449d3955367908c5443f23ca19
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jul 7 13:52:37 2013 -0700

    Move the HAVE_ARCH_* config options from src/arch/x86 to src/.
    
    The options that keep track of whether there are arch versions of the standard
    string functions shouldn't be in the arch/x86 directory since they apply to
    all architectures. Move them into the higher level, shared Kconfig defaulting
    to off. Then, in each applicable arch (currently all of them) they can be
    selected to on.
    
    Change-Id: I7ea64a583230fdc28773f17fd7cc23e0f0a5f3d6
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3760
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit db02069d71af6adca96ff432ed0efd7218c076f3
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jul 7 13:35:37 2013 -0700

    arm: Add a W() macro for use in kernel assembler.
    
    Some kernel assembly code uses a W macro to optionally add a .w to
    instructions that need to be 32 bit thumb. The gnu assembler doesn't seem to
    need the .w and won't assemble if it's provided.
    
    Change-Id: I0a288177788b5c61810ee7bd3d2debea66835de2
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3759
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c65001fcda55758d3be1f8bc0571672263f9ab57
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jun 19 10:41:18 2013 +0300

    Fix CBMEM console use with CAR_MIGRATION
    
    With EARLY_CBMEM_INIT and CAR_MIGRATION selected, cbmemc_reinit()
    was called twice during romstage. This effectively deleted output
    of romstage in CBMEM console.
    
    Change-Id: I21072a319c0e4a5f695b0573bc017bf7921fc663
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3609
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit b25a9da6e7692036fd34ee9327bc082e10c29ae0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jun 26 08:19:14 2013 +0300

    Unify PCI configuration cycles
    
    Split PCI IO configuration and MMIO configuration cycles to separate
    files. Modern hardware does not use IO cycles for PCI configuration
    after initial setup in bootblock.
    
    Note that the pci_mmio_ and pcie_ functions were different in masking
    the alignment for register address. PCI standard requires that 16-bit
    and 32-bit configuration register writes do not cross boundaries.
    
    Change-Id: Ie6441283e1a033b4b395e972c18c31277f973897
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3554
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 33e5df3f25b4594c008788625cd405d988fc6e6b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 3 10:51:34 2013 +0300

    Set PCI bus operations at buildtime for ramstage
    
    PCI bus operations are static through the ramstage, and should be
    initialized from the very beginning. For all the replaced instances,
    there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for
    the northbridge, so these continue to use PCI IO config access.
    
    Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3607
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 52914323bf876342ab3497bfc527f139680d1612
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Tue Jul 9 21:29:25 2013 +0800

    Vortex86EX southbridge routes more built-in PCI device IRQs.
    
    Routes IRQs for USB device, SPI1, MOTOR, HD audio, CAN bus.
    
    Change-Id: I995a5c6d3ed6a7dca4f0d21545c928132ccbbc21
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3725
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8ee04d784cbaeb8a30276ac22aa99ddda44092b7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jul 6 11:41:09 2013 +0300

    usbdebug: Put ehci_debug_info in CAR_GLOBAL
    
    Store EHCI Debug Port runtime variables in CAR_GLOBAL.
    For platforms without CAR_MIGRATION, logging on EHCI Debug Port is
    temporarily lost when CAR is torn down at end of romstage.
    
    On model_2065x and model_206ax ehci_debug_info was overlapping the MRC
    variable region and additionally migration used incorrect size for
    the structure.
    
    Change-Id: I5e6c613b8a4b1dda43d5b69bd437753108760fca
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3475
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 41c10cd2d73198e61573af1341d5826654f1133a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 9 04:19:22 2013 +0300

    usbdebug: Move EHCI BAR relocation code
    
    There are other uses for EHCI debug port besides console, so move
    EHCI relocation code from console to lib.
    
    Change-Id: I95cddd31be529351d9ec68f14782cc3cbe08c617
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3626
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 9e7806a788f9617d3dd9139a74ab3f7b03eb9581
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jul 6 11:56:49 2013 +0300

    usbdebug: Move ehci_debug_info allocation
    
    Move ehci_debug_info allocation from console to lib, as console code
    was only built for ramstage.
    
    Implement dbgp_ehci_info() to return the EHCI context. Alread alias this
    as dbgp_console_input() and _output() to return the console stream context
    later on.
    
    Change-Id: Id6cc07d62953f0466df61eeb159e22b0e3287d4e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3625
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4d409b5fc27e44f7c902f8402f661db56d62ac74
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 5 21:38:54 2013 +0300

    usbdebug: Refactor disable logic
    
    Output to usbdebug console needs to be disabled until hardware is
    initialized and while EHCI BAR is relocated. Add separate field
    ehci_info to point to back to EHCI context when hardware is ready
    to transfer data.
    
    Change-Id: If7d441b561819ab8ae23ed9f3f320f7742ed231e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3624
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit d686acd1a358518e8f37452c0e826a3ac381cbe2
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jun 30 05:19:53 2013 -0700

    pit: Redo the display port bridge initialization code.
    
    The display port bridge on pit is different from the one on snow and needs to
    be initialized differently. Instead of waiting for the chip to come up on its
    own and assert the hotplug detect, we need to access it over i2c and get it up
    and running ourselves.
    
    Change-Id: I4bc911cb8e4463edff7beabd2f356cb70ae9f507
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3723
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0570286849b856aff304f5b6cb50c29cde5f1308
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jun 30 06:09:12 2013 -0700

    pit: Enable the ps8625 driver.
    
    Change-Id: Id1277ceefc844a052627483e6c9d01bcb5da975f
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3722
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2ddc9ea0c887d77b242b361d650660f1a788abe5
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jun 30 05:56:26 2013 -0700

    parade: Add a driver for the parade ps8625.
    
    This driver is basically the same as the one in U-Boot but without the device
    tree stuff. That driver is, in turn, a straightforward implementation of the
    sequence of register writes described in the data sheet. Comments were added
    in U-Boot which helpfully describe what the register writes are actually
    doing and are kept.
    
    Change-Id: I64ba6b373478853bb2120f0553a43de901170d02
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/3753
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a5dc0911293d4bdc7e1a0c5a2e3abd80ee51b857
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jun 30 03:47:33 2013 -0700

    i2c: Change the type of the data parameter to uint8_t.
    
    Data is intended to be a byte array, so it should be described by a type which
    has a fixed size equal to an 8 bit byte. Also, the data passed to write
    shouldn't be modified and can be const.
    
    Change-Id: I6466303d962998f6c37c2d4006a39c2d79a235c1
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3721
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3858b3f698d75e05206a8ef8578796f8456e5450
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jun 30 03:37:24 2013 -0700

    pit: Stop setting up the hardware dp hotplug detect in ROM stage too.
    
    This was removed from ramstage a little while ago and should have been removed
    from here as well.
    
    Change-Id: I6a40ed4a98bedac39e5492e4b1aed3427ab4e08b
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3720
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 88ac9b5a1ef756e0151238e51090a70e7640fd54
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Jun 26 17:28:52 2013 -0700

    PIT: add panel to the list of things to be powered up by the PMIC
    
    This appears to be needed, though we have no way to test yet.
    
    Change-Id: I39033581011e056258193f2cdff78814361a8d55
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3719
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit da7b8e4de9a690cbed00a361d282b18792c676d6
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Jun 28 17:27:17 2013 +0800

    armv7/exynos: Prevent unexpected reboots in resume.
    
    In resume path, if memory setup takes too long without setting PS_HOLD, EC watch
    dog may power off or reboot the system. To prevent that, we should enable
    PS_HOLD in same timing as cold boot - right before starting memory setup.
    
    Change-Id: I5c294fa7ae015f8cff57b1fd81e5b80902647b15
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3718
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c0b2144f698fdf82a2402db6b6038e70b19ba984
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Jun 28 14:27:16 2013 -0700

    pit: Replace the tps65090 functions and adjust the hotplug detect line.
    
    The functions which manipulated the tps65090 were removed a while ago because
    it isn't accessible directly from the AP, it's on an I2C bus that has to be
    accessed by the EC on our behalf. Now that that capability has been added, we
    can rewrite the small portion of the the tps65090 we actually used but using
    the EC passthrough commands.
    
    Also, we should not be configuring the hardware display port hotplug detect
    line since we're using it as a GPIO for other purposes. The GPIO we're using
    instead defaults to being an input, but to be safe we should probably
    explicitly configure it as one anyway.
    
    Change-Id: I7f8a8a767e3cccb813513940a5feceea482982f5
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3717
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9f96aa6b5e6bc5af8feb7bb29239f8421ded1f14
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Jun 28 14:24:33 2013 -0700

    chromeec: Add a function to send passthrough i2c messages.
    
    Change-Id: I576d0dbf65693f40d7d1c20d3d5e7a75b8e14dc9
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/3752
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2b3167908be680b5aa1cd6fe2f42a44d4c118f3f
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 26 19:48:43 2013 +0800

    armv7/pit: Correct EC device in mainboard configuration.
    
    The ChromeOS EC for peach_pit is connected to SPI2 bus, not I2C.
    
    Change-Id: Ifeb8a626aa4fc3d3a181a7bc016e3f91be948ae5
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3716
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f473df141956d639ccc9e2ad8c60b313294d6e8d
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 26 21:22:55 2013 +0800

    armv7/exynos5420: Remove the extra reopen when reading SPI.
    
    The workaround of re-opening device in exynos_spi_read has been fixed by the new
    correct open/close and xfer procedure. It's safe to be removed now.
    
    Change-Id: I6b1bf717c916903999a137998a578b0a866829bd
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3715
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a965a37810f5fbbc35a435f1912d7f1617e36a81
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 26 20:31:22 2013 +0800

    armv7/exynos5420: Apply new implementation for SPI transmission.
    
    Switch spi_xfer and exynos_spi_read to use the new spi_rx_tx function.
    
    Change-Id: I01ab43509df1319672bec30dd111f98001d655d0
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3714
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 864420766ad85c8ed0dd98aefd8f527aeb506aa5
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 26 20:29:06 2013 +0800

    armv7/exynos5420: Add output ability and half-duplex mode in SPI driver.
    
    The SPI driver (exynos_spi_rx_tx) was implemented with only "read" ability and
    only full-duplex mode. To communicate with devices like ChromeOS EC, we need
    both output (tx) and half-duplex (searching frame header) features.
    
    This commit adds a spi_rx_tx that can handle all cases we need.
    
    Change-Id: I6aba3839eb0711d49c143dc0620245c0dfe782d8
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3713
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cab3621446542fadf67e9406c4ae39fb63a0536f
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 26 20:22:50 2013 +0800

    armv7/exynos5420: Revise SPI open/close/reset procedure.
    
    The original Exynos SPI open/close procedure was copied from U-Boot SPL with
    some assumptions that only works in SPL stage.  For example, it tries to always
    work in 4-byte transmission mode with only RX data is swapped, and claims a
    packet for initial address command (and with incorrect size).
    
    This commit revises open/close and reset so only the required SPI registers are
    configured.
    
    Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3712
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ed1742cafec5627023e12f8bde52282247d17ddd
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 26 20:17:42 2013 +0800

    armv7/exynos5420: Provide configuration for SPI0~SPI2.
    
    Fill the SPI device parameters for spi_setup_slave on Exynos 5420.
    
    Change-Id: I10b4b9e6cfe46d7bfa34e80e3727c7e7da99ba9d
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3711
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ffa5bada722a60e0115775ee69cd681c3737f17a
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 26 20:16:13 2013 +0800

    armv7/exynos5420: Change SPI module to standard <spi-generic> interface.
    
    The SPI module in Exynos 5420 didn't follow Coreboot's SPI API standard
    (spi-generic.h) and will be a problem when we want to share SPI drivers.
    
    This commit replaces exynos_spi_* by spi_* functions.
    
    Note, exynos_spi_read is kept and changed to a static function because its usage
    is different from the standard API "spi_xfer".
    
    Change-Id: I6de301bc6b46a09f87b0336c60247fedbe844ca3
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3710
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 45d524d2783adad9fee62a5bf909baf675e83fc9
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 26 20:03:47 2013 +0800

    armv7/exynos5420: Clean up unused header and constants in spi.c
    
    Remove unused header and constant definition in SPI module.
    
    Change-Id: I339e603f48186e4a356e83518b0d0b4c907f11b8
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3709
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 16cb01044010b4bd1bacad3160aebf91ebd86681
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 26 19:52:52 2013 +0800

    armv7/exynos5420: Revise SPI device list in cpu.h
    
    Add SPI0 and SPI2 to Exynos 5 SPI list, and correct structure names.
    Also removed the un-enumerated devices (SPI_BASE, base_spi()).
    
    Change-Id: Ica6d9a41f9619c8c61eab664d5e988dd4a428e09
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3708
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0ee7062e305c6ba4457e1edf10de8d5b3b388a70
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 26 19:42:12 2013 +0800

    ec/google: Support ChromeOS EC on SPI bus.
    
    For devices with ChromeOS EC on SPI bus, use the standard SPI driver interface
    (see spi-generic.h) to exchange data.
    
    Note: Only EC protocol v3 is supported for SPI bus.
    
    Change-Id: Ia8dcdecd125a2bd7424d0c7560e046b6d6988a03
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3751
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e946f981a4c603d93eced2e0ccf8837fca7c8cd4
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Sat Jun 22 11:18:39 2013 +0800

    ec/google: Support Chrome EC protocol version 3.
    
    Add the new Chrome EC protocol version 3 to Coreboot.
    
    Note, protocol version 3 is not applied on any bus implementations yet.
    LPC (x86) and I2C (arm/snow) are still using v2 protocol.  The first one to use
    v3 protocol will be SPI bus (arm/pit).  LPC / I2C will be updated to v3 only
    when they are ready to change.
    
    Change-Id: I3006435295fb509c6351afbb97de0fcedcb1d8c4
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3750
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 23fb9979d999a155a2560a9f09f4fcdc1b96e9e7
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Jun 21 20:11:47 2013 +0800

    ec/google: Generalize communication protocol support in EC drivers.
    
    Since EC protocol v3, the packet format will be the same for all buses (inclding
    I2C, SPI, and LPC). That will simplify the implementation in each individual bus
    driver source file.
    
    To prepare for that, we will move the protocol part into crosec_proto.c:
    crosec_command_proto, with bus driver in callback "crosec_io".
    
    Change-Id: I9ccd19a57a182899dd1ef1cd90598679c1546295
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3749
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c357aed3d7954c87375ab5f7f6c0902a302adf09
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jun 24 20:02:01 2013 +0800

    armv7/pit: Setup EC on SPI2.
    
    The Embedded Controller (EC) for Pit is connected via SPI2, and needs to be
    configured before we can talk to it.
    
    Change-Id: I1f8e921b4616f15951f3e5fae1ecbf116de4ba90
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3707
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e42030d23600990e95db2af1e9e1a366ff3d4ec7
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Sun Jun 23 08:14:30 2013 +0800

    arm/exynos: Correct SPI session commands.
    
    Some initialization / shutdown commands should be paired correctly in a SPI I/O
    session. For example, setting CS should be enabled and disabled in each read;
    and the bus width (byte or word) should be configured only when opening /
    closing the SPI device.
    
    Change-Id: Ie56b1c3a6df7d542f7ea8f1193ac435987f937ba
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3706
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8b95c134207de9573f8e5eb758e5cee51741604a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jul 7 11:30:48 2013 +0300

    AMD: Kconfig cleanup
    
    Change-Id: Ie347b32575c26133d52c275622d29d1cd4c6c0c7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3623
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 3ad5a9b97f2d66764880e0cf01b1833d39ddd5ce
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat Jun 22 19:42:15 2013 -0700

    pit: update I2C4 speed constant
    
    Change-Id: I4feabc448945c4664d3114c0c8afdad48338230a
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3705
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f396ad5a6c5dec6c84343005a38c0931e7281e69
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Jun 24 03:20:22 2013 -0700

    exynos5420: i2c: Fix error handling.
    
    The functions which checked the status of a transfer would return success if
    the bus was no longer occupied, even if it's no longer occupied because the
    transfer failed. This change modifies those functions to return three possible
    values, 0 if the transfer isn't done, -1 if there was a fault, and 1 if the
    transaction completed successfully.
    
    Change-Id: Idcc5fdf73cab3c3ece0e96f14113a216db289e05
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3704
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7c2ae7ae53ac2bc4dadc55ba5445d0556ee32251
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Jun 24 03:14:41 2013 -0700

    exynos5420: Clock the mmc blocks off of the mpll.
    
    The exynos manual suggests hooking the mmc ip blocks to the mpll. They had
    been set to use a different pll. This changes them over and modifies the
    divider so that the frequency stays the same.
    
    Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3703
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 04d6e01d43626383fb80936ef1237df67cf23ca1
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Jun 23 03:16:46 2013 -0700

    pit: Configure the pinmux for the i2c busses that are connected on pit.
    
    Change-Id: I2dc4caa370473dd86fee2b5cc8b1b9eb154b970e
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3702
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit be58278a8654ce089dbe94be2193539ef7f26c1e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat Jun 22 19:40:43 2013 -0700

    exynos5420: use speed parameter in i2c_init() for HSI2C
    
    This allows us to set different speeds for each HSI2C bus.
    
    Change-Id: I50cc257aad9ef50025d0837b0516940b956efc02
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3701
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2d2e37fc526741a7308b88c794729295a2c5e3cd
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Jun 22 20:05:37 2013 -0700

    exynos5420: Change some clock settings.
    
    This change adjusts some clock settings so that they match U-Boot. There are
    three different changes.
    
    1. Change the source for psgen from the oscillator clock to the pclk.
    2. Change the pll feeding the SPI busses from epll to mpll, as suggested in
       the manual.
    3. Change the SPI prescaller.
    
    Change-Id: Ib54a255bc14fc286629dac86db9b8cf8e75a610b
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3700
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cf7509cfd1c775f4ee664f7784257c73bffd1513
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Jun 22 19:43:40 2013 -0700

    exynos5420: Fix the way the rate of the input clock for i2c buses is found.
    
    The clock divider was being read from registers incorrectly which meant that
    the periph rate was wrong.
    
    Change-Id: I50efb62849ef29bdfb0efc56c49642d3edca094c
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3699
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7dd581494dbaff64e4a2dd31f29cb254104d2d03
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 5 14:06:55 2013 -0700

    snow: Add flush to UART driver.
    
    Wait for UART FIFO to be ready.
    (Credit to dhendrix for finding the bits to test with.)
    
    Change-Id: Ib6733e422cbc1c61b942bd90d85f88a3f412d6ff
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3698
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ce7a5a790be1cd734c5d1c9f934ade0433c0b96b
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Jun 20 18:57:04 2013 +0800

    ec/chromeec: Merge upstream V3 structure and constant definition.
    
    Chrome EC protocol V3 has several new command structure and constants defined.
    Simply cherry-picking changes from upstream.
    
    Change-Id: I7cb61d3b632ff32743e4fa312e0cc691c1c4c663
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3748
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3a0d0d8622c9f4f14116ecb3f265dddf52fece84
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 20 16:13:19 2013 -0700

    Exynos5420: Initialize USB PHY
    
    ... this is needed for libpayload to talk to USB devices.
    (forward ported from https://gerrit.chromium.org/gerrit/#/c/55554)
    
    Change-Id: I5a20864689efd0c0149775e6d85b658e0cc6715c
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3697
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2ad63c2e08de2cccc7de42c4c3c5efeec7af25ad
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri May 17 11:52:45 2013 -0700

    Exynos5250: Initialize USB PHY
    
    ... this is needed for libpayload to talk to USB devices.
    
    Change-Id: I7eb19003c9e96efb5fa7a3f97c7b15f3ef332687
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3696
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 062c17bb78825a304aefd8b53d07c7be38211e42
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 19 15:51:04 2013 -0700

    Exynos: Only compile UART in if serial console is selected
    
    Change-Id: I5cddffc2e524aae7a31a8f94f67e03a5b7e15c82
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3695
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9d9b0dd20980c5e9b2cafb07c03775bbaa249ea2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 19 15:44:36 2013 -0700

    Don't try to use CBMEM console in bootblock
    
    Otherwise we have to worry about hand off between bootblock and
    romstage. Too much complexity
    
    Change-Id: I89bf8a229dba7e1330accadf9a732d831ebc4827
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3694
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 005151047ed5ab875905a5b3ee3942d09039b945
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Jun 19 15:46:25 2013 -0700

    Exynos5420: add code to make sure resume will work on DRAM.
    
    Found during a perusal of u-boot changes. It looks important.
    For more info: http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=56eab63922d2b2380518238ae03e8d69e99af4fe
    
    Change-Id: Ida2fe2a98be008a4bdfe594cf00d01a33b511b4f
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3693
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6b0bab916a59c6270a1f0fd53002e568052f2b45
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 12 17:07:05 2013 -0700

    ARMv7: Drop duplicate call to bootblock_cpu_init()
    
    This is already called in ARMv7 bootblock_simple.c so we don't
    want to do it twice
    
    Change-Id: I80cb41035b8a77787e04f2ea58a1cd372cea97d8
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3692
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d2f45c651694b2ada2443bb12def23e6c7910b10
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 19 13:42:00 2013 -0700

    Simplify early / bootblock console code
    
    Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3691
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b919809afeaf3c571961ead626c04b8f9e258e11
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jun 19 20:15:57 2013 -0700

    ARM: Don't leave alignment checking on after the exception test.
    
    Currently, the exception handling code on ARM turns on alignment checks as an
    easy way to generate an exception for testing purposes. It was leaving it on
    which disabled unaligned accesses for other, unlreated code running later.
    This change adjusts the code so the original value of the alignment bit is
    restored after the test exception.
    
    Change-Id: Id8d035a05175f9fb13de547ab4aa5496d681d30c
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3690
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 63bb610abb9ffa244a6571132813388a485141c9
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jun 19 03:29:45 2013 -0700

    pit: Replace the snow GPIO indexes with ones for pit.
    
    The GPIOs used by vboot and setting up the display and backlight were still
    the ones for snow. This change updates them so they're correct for pit.
    
    Change-Id: I06ba773da3af249efec723bb90c2e9e8075a777a
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3689
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fdd2356b5766e0e8a95b54d1d56f5c9340c95832
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jun 19 02:37:51 2013 -0700

    pit: Remove the MAX_CPUS option.
    
    The MAX_CPUS option is only used on x86 currently, so there's no reason to
    have it in the pit config.
    
    Change-Id: I270bbfd3aff781d88304791b1d9735777643caab
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3688
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 16c14801b652c0753348d5d43216dda38e87e5b1
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jun 19 02:18:25 2013 -0700

    pit: Stop compiling in the max77686 driver on pit.
    
    That part isn't used on pit.
    
    Change-Id: I48f3a10f7e6eb89b1e9630d2372b6865b4c12a7f
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3687
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f0ebac812728e928e3ca6f3d5fb3a8692c3a7206
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jun 19 02:10:36 2013 -0700

    pit: Stop calling tps65090 functions until we can call through the EC.
    
    On pit, the tps65090 is connected to the EC and has to be accessed by proxy.
    Until we have that implemented, this change removes calls to tps69050 which
    will never succeed, and stops compiling in the driver.
    
    Change-Id: I7218f85f9f26623bd13aaaf8ded0638b3b2f874a
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3686
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 46b57bbded9b7cdb2c5af04f5d381eb0122de2b9
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jun 19 01:37:59 2013 -0700

    exynos5420: Switch to fixed size types in dmc.h.
    
    The members data structures in dmc.h are intended to have a particular size.
    Rather than assume that particular types are the right size, we should use
    types that are guaranteed to be the right size. Also, since the registers are
    at particular offsets as well, the structures should be packed.
    
    Change-Id: I9cc11d7451f92ba3eb85c6be88ecbc62c7a5652d
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3685
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit becb3f62f724dee34e2f3aef6d781c701c0c551b
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jun 19 01:23:50 2013 -0700

    exynos5420: Revamp the high speed I2C driver.
    
    The previous driver was a bit awkward and not entirely correct. This change
    primarily replaces the read/write functions with simpler and more robust
    (hopefully) version.
    
    Change-Id: I55f0ad8faec2de520e27577bd6dad9c0118d8171
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3684
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3511b92d31d645e2a77e2729e2f031d08bba98bb
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 19 12:02:47 2013 -0700

    Samsung CPUs: Unify Kconfig
    
    For all other CPUs, we unconditionally include the CPU Kconfig
    files in the CPU directory, not in the vendor directory. Do the
    same thing for the Exynos CPUs. This allows us to make CPU dependent
    changes in the directory of that CPU alone.
    Also, drop some unused Kconfig variables from the Exynos Kconfig
    files.
    
    Change-Id: I4e4c22a0693988834e619dd33d121bf994ed57e8
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3683
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2867060098e4023a2d33d335afe49981584ec378
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jun 12 15:01:56 2013 -0700

    arm: Fix memory barrier usage in IO operation
    
    The dmb should be executed before reading operations, and before/after writing
    operations.
    
    Change-Id: I572136a2f9a07eb2c38a112f5deeb2de0c0fd46c
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3682
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 83fd23925509026734833c9d8d28890029899458
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Jun 14 19:16:56 2013 -0700

    exynos5420: update I2C code, add HSI2C/USI support
    
    This updates the low-level I2C code to handle the new high-speed
    HSI2C/USI inteface. It also outputs a bit more error information
    when things go wrong. Also adds some more error prints. Timeouts
    really need to be noted.
    
    In hsi2c_wait_for_irq, order the delay so that we do an initial
    sleep first to avoid an early-test that was kicking us out of the
    test too soon. We got to the test before the hardware was ready
    for us. Finally, test clearing the interrupt status register every time
    we wait for it on the write. Works.
    
    Change-Id: I69500eedad58ae0c6405164fbeee89b6a4c6ec6c
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3681
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1e3e2c51dba9b2c205985704aec77c89fcda7fdc
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Jun 14 16:08:05 2013 -0700

    pit: set up the PMIC correctly
    
    This updates the setup_power() function to actually set up the PMIC
    which is on this board (the MAX77802).
    
    Change-Id: I9c6f21f183dacc0bca71277e681e670834412d78
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3680
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 90a42d83cf27afb24c832811995b399955cc3008
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Jun 14 16:06:11 2013 -0700

    max77802: add header for max77802 PMIC
    
    This adds register offsets and important values for the Maxim
    MAX77802 PMIC.
    
    Change-Id: I3724b82bcb235b6684d2b976876f628f1ffbed3f
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3747
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 32450568bc03d7b648d13755345cc647b97664f1
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Jun 18 13:02:23 2013 -0700

    ARM: when setting a GPIO to put, set the value, then the direction
    
    We saw a problem on x86 last year in which setting direction, then value,
    glitched the output and caused problems. Change this code to set the output,
    then the direction.
    
    Change-Id: I3e1e17ffe82ae270eea539530368a58c6cfe0ebe
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3679
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c883fdc964207d3871e8609c67988c07d448a87d
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Jun 18 06:08:42 2013 -0700

    exynox5420: Remove the 5250 clock registers and fix the SPI frequency.
    
    The 5420 clock code still had a data structure in it for the 5250 clock
    registers which was used by some of the clock functions. That caused some
    clocks to be configured incorrectly, specifically the i2c clock which was
    running at about 80KHz instead of about 600KHz as configured by U-Boot.
    
    Also, the registers and bit positions used to set up the SPI bus were not
    consistent with U-Boot, and if the bus clock rate were set to 50MHz, a rate
    which has historically worked on snow, loading would fail. With these fixes
    the clock rate can be set to 50MHz and the device boots as much as is
    expected. I haven't yet measured the actual frequency of the bus to verify
    that it's now being calculated correctly.
    
    Change-Id: Id53448fcb6d186bddb3f889c84ba267135dfbc00
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3678
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e6af9296619a8bc1abe0c19268c9d961bf73843f
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Mon Jun 3 13:03:50 2013 -0700

    PIT: memory setup
    
    Tested and working. Gets us to ramstage.
    
    Change-Id: Ib9ea4a6c912e8152246aaf4f1f084a4aa1626053
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3677
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit eb9517cce9dfdc042ca1a9a2d7f6dd14d6d4fafc
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat Jun 15 19:22:06 2013 -0700

    exynos5420: add I2C8-10 to clock_get_periph_rate()
    
    This adds entries for I2C8-10 to giant switch statement in
    clock_get_periph_rate(). It also eliminates the I2C peripheral's
    usage of clk_bit_info since it's confusing and error-prone.
    
    Change-Id: I30dfc4c9a03fbf16d08e44e074189fb9021edb6d
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3676
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ff7c8e82d10a48f7d123755b33bef9ffbf01d90d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 29 13:12:20 2013 -0700

    armv7a: Enable native memcpy / memset
    
    The code has been there for quite a while but was never enabled.
    
    Change-Id: I4ec3dcbb3c03805ac5c75872614e5d394df667cf
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3675
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e6a44ebb29d7fb9ac6bbef0db4bd0e3100a72f55
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Jun 15 23:40:26 2013 -0700

    exynos5420: Implement support for the pinmux as functions.
    
    Change-Id: I5e0ec360597cd95cb6510fb32b04d8931e6a33db
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3674
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fe6406033fe327d4ae408b02efc060b4b421bc03
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Jun 15 20:33:05 2013 -0700

    exynos5250: De-switch-ify the pinmux configuration code.
    
    The pinmux code for the exynos5250 was all bundled into a single, large
    function which contained a switch statement that would set up the pins for
    different peripherals within the SOC. There was also a "flags" parameter, the
    meaning of which, if any, depended on which peripheral was being set up.
    
    There are several problems with that approach. First, the code is inefficient
    in both time and space. The caller knows which peripheral it wants to set up,
    but that information is encoded in a constant which has to be unpacked within
    the function before any action can be taken. If there were a function per
    peripheral, that information would be implicit. Also, the compiler and linker
    are forced to include the entire function with all its cases even if most of
    them are never called. If each peripheral was a function, the unused ones
    could be garbage collected.
    
    Second, it would be possible to try to set up a peripheral which that function
    doesn't know about, so there has to be additional error checking/handling. If
    each peripheral had a function, the fact that there was a function to call at
    all would imply that the call would be understood.
    
    Third, the flags parameter is fairly opaque, usually doesn't do anything, and
    sometimes has to have multiple values embedded in it. By having separate
    functions, you can have only the parameters you actually want, give them
    names that make sense, and pass in values directly.
    
    Fourth, having one giant function pretends to be a generic, portable API, but
    in reality, the only way it's useful is to call it with constants which are
    specific to a particular implementation of that API. It's highly unlikely that
    a bit of code will need to set up a peripheral but have no idea what that
    peripheral actually is.
    
    Call sights for the prior pinmux API have been updated. Also, pinmux
    initialization within the i2c driver was moved to be in the board setup code
    where it really probably belongs. The function block that implements the I2C
    controller may be shared between multiple SOCs (and in fact is), and those
    SOCs may have different pinmuxes (which they do).
    
    Other places this same sort of change can be made are the pinmux code for the
    5420, and the clock configuration code for both the 5250 and the 5420.
    
    Change-Id: Ie9133a895e0dd861cb06a6d5f995b8770b6dc8cf
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3673
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 001056f560dfec46aa98659f318819cce7098e5b
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Jun 14 15:53:23 2013 -0700

    ARM: Tell the linker memset and memcpy are functions.
    
    The memset and memcpy functions are assembled as ARM code, likely because
    that's the default of the assembler. Without special annotation, the assembler
    and linker don't know that those symbols are functions which need special
    handling so that ARM/thumb issues are handled properly. This change adds that
    annotation which gets those functions working in Coreboot which is compiled as
    thumb. Libpayload and depthcharge are compiled as ARM so they don't *need* the
    annotation since it just works out in ARM mode, but it's the safe thing to do
    in case we change that in the future.
    
    We should explicitly select ARM vs. thumb when assembling assembly files to be
    consistent across builds and toolchains.
    
    Change-Id: I814b137064cf46ae9e2744ff6c223b695dc1ef01
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3672
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fbb11cf97937c345a42a45737fc7a95ee7ee3e7e
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Jun 6 00:21:20 2013 -0700

    ARM: Separate the early console (romstage) from the bootblock console.
    
    It might be that you want an early console in romstage before RAM is up, but
    you can't or don't want to support the console all the way back in the
    bootblock. By making the console in those two different environments
    configurable seperately that becomes possible.
    
    On the 5250 console output as early as the bootblock works, but on the 5420 it
    only starts working in the ROM stage after clocks have been initialized.
    
    Change-Id: I68ae3fcb4d828fa8a328a30001c23c81a4423bb8
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3671
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c2c4f84644bf6f20b0a3b5dffb7edb6a47f02023
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 20 12:51:02 2013 -0700

    google/pit: Don't spew output with GPIO config
    
    There are hundreds of GPIOs on the Exynos5420. Don't
    always print all of them per default.
    
    Change-Id: I2152ab760e31a335dbcd9d6ad32cd1eaae4b89bc
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3670
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 37332b66fa1911144dc2c7cd0bda77f7dbbcfb3b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 29 13:10:56 2013 -0700

    arch: clean up Kconfig and Makefile
    
    remove some unused code
    
    Change-Id: I41602fb391c1910c588a4f9dcc7c2edefe8ab5bc
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3669
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2d8112523aa04bca3f4d56d6ba1660082bf279b5
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 20 15:24:13 2013 -0700

    exynos5420: Clear the framebuffer before making it uncacheable
    
    If we clear the framebuffer and then flush it back to memory using cache
    operations, the writes are going to be full cachelines at a time. If we
    make it uncacheable first, the writes will be serialized writes of
    whatever sized chunks memset uses, probably 4 bytes or less.
    
    Change-Id: I960f87a370e97f9e91236ad796d931573bb3dbb8
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3668
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6c184d6855a11d42f9d77bc9ddb8dfeb608072b6
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 20 15:21:48 2013 -0700

    exynos5420: Don't disable and re-enable the MMU when uncaching the framebuffer
    
    At one time it seemed to be necessary to disable and then re-enable the
    MMU when setting the framebuffer to be uncache-able due to bugs in the
    MMU management code. Since those bugs have been fixed, this is no longer
    necessary.
    
    Change-Id: I7ce825cf5eaaa95119364d780cba0935752e4632
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/3667
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f17519120a4d76cd18d12e94987b65b336f32f59
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 20 15:17:44 2013 -0700

    exynos5420: Simplify the graphics code by eliminating the unused color map
    
    The code that allocated space for the framebuffer was adding space for a
    vestigial color map which was never used. It was also passing around a
    structure which was used to calculate a single value which was already
    known when that structure was put together. Eliminate the extra space,
    and pass the single value instead of the structure.
    
    Change-Id: I29bc17488539dbe695908e47f0b80c07e102e17d
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/3666
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1162103958fad815e10b90524560b3b81f2c0b18
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Jun 6 00:14:08 2013 -0700

    exynos5420: Fix some problems with the clock management code.
    
    The code which figured out the rate of the input clock to a peripheral was
    doing several things wrong. First, it was using the wrong values when
    determing what the source of a clock was set to. Second, it was using the
    wrong offset into that register to find the current source setting.
    
    This change fixes the constants which select a clock source which get some
    more things working, but doesn't attempt to fix the bit position table.
    
    Change-Id: Id7482ee1c78cec274353bae3ce2dccb84705c66a
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3665
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d63bddc4991d9ace037fd716b29c3f7253e9ac94
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jun 11 21:55:58 2013 -0700

    armv7: Reserve space BL1 and checksum header by specifying bootblock offset.
    
    Not all ARM systems need "BL1", and the layout of BL* and bootblock may be
    different (ex, Exynos 5250 may use a new BL1 with variable length checksum
    header).
    
    To support that better, define the real base address (and ROM offset) of boot
    block, and then we can post-processing ROM image file by filling data / checksum
    and any other information.
    
    Change-Id: I0e3105e52500b6b457371ad33a9aa546acf28928
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3664
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 32ab283b1086ef53fadcd4be92df6e41c5d06438
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Jun 11 16:36:37 2013 -0500

    cpu: Add CPU microcode file to cbfs with 16-byte alignment
    
    On x86 there is a 16-byte alignment requirement for the
    addresses containing the CPU microcode. The cbfs files
    containing the microcode are used in memory-mapped fashion
    when loading new mircocode. Therefore, the data payload's
    address/offset of a cbfs file in flash dictates the resulting
    alignment. Fix this by processing the CPU microcode cbfs
    file separately as it uses $(CBFSTOOL) to find the proper
    location within the provided rom image.
    
    Change-Id: Ia200d62dbcf7ff1fa59598654718a0b7e178ca4c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3663
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e221aad27fb860f31be089180d920df9d2243ae2
Author: Bill Richardson <wfrichar@chromium.org>
Date:   Wed Jun 12 10:50:41 2013 -0700

    ec: Reserve correct ioport regions for Chrome OS EC to use
    
    The LPC-based ChromeOS EC uses several ioport regions to communicate with
    the AP. In order for the new unified userspace access method to work, we
    need them to be reserved by the BIOS.
    
    Before /proc/ioports shows:
    
      0800-0803
      0804-08ff
    
    We'd like just a single 256-byte region at 0x800, but ASL can't handle that.
    So this will work:
    
      0800-087f
      0880-08ff
    
    Change-Id: I3f8060bff32d3a49f1488b26830ae26b83dab79d
    Signed-off-by: Bill Richardson <wfrichar@chromium.org>
    Reviewed-on: http://review.coreboot.org/3746
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a86c33a31a6c3faa91df12ee3e592a98f5702bc6
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri May 17 10:34:25 2013 -0700

    google/snow: Don't spew output with GPIO config
    
    There are hundreds of GPIOs on the Exynos5250. Don't
    always print all of them per default.
    
    Change-Id: Ie349f2a4117883302b743027ed13cc9705b804f8
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3661
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6d16c437fc2609a4521de3b7e78a07b4155ceaba
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jun 4 10:07:15 2013 -0700

    slippy/falco/peppy: Enable SERIRQ continuous mode
    
    The Chrome EC still does not tolerate SERIRQ in quiet mode
    and so the keyboard does not work properly.
    
    Change-Id: I9ab052187c9926ce0e2c86b86dfe987dd6564c1b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/3745
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7cced0d20e44c1bbcd0b5d4aced53c682fcd23fc
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jun 4 10:03:34 2013 -0700

    ec: Add romstage function for checking and rebooting EC
    
    Now that we are executing VbInit() in coreboot we can end up
    in a situation where the recovery reason is consumed during
    VbInit (end of romstage) and then the EC is rebooted to RO
    during ramstage EC init, thereby losing the recovery reason.
    
    Two possiblities are to remove the EC check+reboot from ramstage
    and let it happen in depthcharge.  This however means that the
    system has to boot all the way into depthcharge and then reboot
    the EC and the system again.
    
    Instead if we do a check in romstage before VbInit() is called
    then we can reboot the EC into RO early and avoid booting all
    the way to depthcharge first.
    
    This change adds a ramstage version the EC init function and
    calls it from the shared romstage code immediately after the
    PCH decode windows are setup.
    
    Change-Id: I30d2a0c7131b8e4ec30c63eea36944ec111a8fba
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/3744
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 433432b6544fc57c7998a66aaa34c45609e4fc8c
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 3 10:38:22 2013 -0700

    chrome ec: Update EC header from EC repository
    
    - Updated ec_commands.h is copied in directly from EC repo
    - Removed "old" interface and update resources for "new" interface
    - Updated temp sensor constants and added "not calibrated"
    - Update mainboards to remove check for EC_SWITCH_KEYBOARD_RECOVERY
    
    Change-Id: Ic93c1914f86b6f5bc224178270624ed92b5c1e15
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/3743
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e8b08ba47c8b17480bd94eef7dc8a47629191957
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri May 24 15:09:36 2013 -0700

    Drop ELF remains from boot code
    
    This stuff is not used, so let's drop it.
    
    Change-Id: I671a5e87855b4c59622cafacdefe466ab3d70143
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3660
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 93ce3b3a28dc0aad0bb501072bc7fc31e9cd6ce2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri May 24 14:38:48 2013 -0700

    ARMv7: flatten arch/armv7 source tree
    
    With only 19 source files it doesn't make a whole lot of sense to
    create sub directories in arch/armv7, especially since the files
    were distributed somewhat randomly.
    
    Change-Id: I029c7848e915edf1737e1c401c034837c95d179d
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3659
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5420e0913144e3abbd0f36dbfbc0bcbe8f052e7b
Author: Gabe Black <gabeblack@google.com>
Date:   Fri May 17 11:29:22 2013 -0700

    exynos5420: Replace the 5250 clock logic with 5420.
    
    The new code is stolen from U-Boot with little or no understanding of how it
    works.
    
    Change-Id: I3de7d25174072f6068d9d4fdaa308c0462296737
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3658
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 99ed2a83b5ae69d134333deaa7d326b9c0aa08b7
Author: Gabe Black <gabeblack@google.com>
Date:   Fri May 17 11:17:15 2013 -0700

    exynos5420: Make the ps_hold_setup function public.
    
    This function had been declared in a public header file, but was marked
    static when actually defined.
    
    Change-Id: Ia551a5a12e7dbaf7bc00861e085695145ab7b91a
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3657
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 998ab0d5f9fbb43edfa0c8f78d1b99f78cd94180
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 20 12:29:37 2013 -0700

    Exynos5420: Clean up console code
    
     - Don't initialize console twice in the bootblock
     - remove printk in memory init that would mess up the UART
     - unconditionally run console_init() in romstage, as it is
       also unconditionally run in the bootblock.
    
    Change-Id: I983d011c6ca602445f447d17799c1b2a33e8bd1d
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3656
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 045222f31260d60b337b221ed373edd284386fd5
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue May 21 07:49:11 2013 -0700

    ec: Remove hardcoded GPI offset in EC SCI
    
    With LynxPoint-LP the SCI GPE is no longer a GPIO
    that is offset by 16.  Remove the Add and fix up
    the link definition so it is still accurate.
    
    Change-Id: I091141183a09345b5ffe28365583e48019f9f5e5
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/3742
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 39fda6d9159461f04f74259919281baca7cb4393
Author: Gabe Black <gabeblack@google.com>
Date:   Sat May 18 23:06:47 2013 -0700

    exynos5250: Clear the framebuffer before making it uncacheable.
    
    If we clear the framebuffer and then flush it back to memory using cache
    operations, the writes are going to be full cachelines at a time. If we make
    it uncacheable first, the writes will be serialized writes of whatever sized
    chunks memset uses, probably 4 bytes or less.
    
    Change-Id: I1b81731cfed00ae091ba6357451ab186d16f559e
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3655
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 986162b25f1038e5425713883310ba6002859d7d
Author: Gabe Black <gabeblack@google.com>
Date:   Sat May 18 22:57:34 2013 -0700

    exynos5250: Don't disable and re-enable the MMU when uncaching the framebuffer.
    
    At one time it seemed to be necessary to disable and then re-enable the MMU
    when setting the framebuffer to be uncache-able due to bugs in the MMU
    management code. Since those bugs have been fixed, this is no longer
    necessary.
    
    Change-Id: I5f7b9bd14dc9929efe1834ec9a258d388b8c94e9
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3654
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 800790d4e1e4817a140c706a32b5448cbd9d0c45
Author: Gabe Black <gabeblack@google.com>
Date:   Sat May 18 22:45:54 2013 -0700

    ARM: Fix up page table/cachability management.
    
    When modifying the page tables, use writel to ensure the writes happen, flush
    the page tables themselves to ensure they're visible to the MMU if it doesn't
    look at the caches, and invalidate the right TLB entries.
    
    The first two changes are probably safer but may not be strictly necessary.
    The third change is necessary because we were invalidating the TLB using i
    which was in megabytes but using an instruction that expects an address in
    bytes.
    
    One symptom of this problem was that the framebuffer, which was supposed to be
    marked uncacheable, was only being partially updated since some of the updates
    were still in the cache. With this change the graphics show up correctly.
    
    Change-Id: I5475df29690371459b0d37a304eebc62f81dd76b
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3653
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1e797bdb79b9b3d05640abfee93acf1359cda4db
Author: Gabe Black <gabeblack@google.com>
Date:   Sat May 18 15:58:46 2013 -0700

    exynos5250: Simplify the graphics code by eliminating the unused color map.
    
    The code that allocated space for the framebuffer was adding space for a
    vestigial color map which was never used. It was also passing around a
    structure which was used to calculate a single value which was already known
    when that structure was put together. Eliminate the extra space, and pass the
    single value instead of the structure.
    
    Change-Id: Ia6a41cefdf8b29fe7d68f9596a156eced6eb5df8
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3652
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1387b439f125090550ee12fe178e571a1ca40337
Author: Gabe Black <gabeblack@google.com>
Date:   Sat May 18 15:55:47 2013 -0700

    snow: Make coreboot set up pins for busses it knows are hooked up as such
    
    Coreboot knows that, for the snow board, certain pins are to be connected to
    bus controllers in the SOC and to the wires of a bus external to the SOC. It
    can configure them as such and free its payload from having to know how to
    set everything up.
    
    Change-Id: I1bb127c810e9ee077afc4227a6f316eaa53d6498
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3650
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 5688979fbd190af1a6c5181a837341761043a8b2
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Tue Jul 9 21:39:46 2013 -0600

    drivers: Fix spelling
    
    Change-Id: Ib0d98e3ab5b2943c36f88765587e8963a4f49604
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3754
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8940d3e2a7678eabbdd6b3b79498a69019bde77a
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Tue Jul 9 21:52:41 2013 -0600

    ec: Fix spelling
    
    Change-Id: I5e4d35572c43f07bec5ec0bcd75c717723228e2f
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3757
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cbf2bd715a6a3c5d758c52b4634284b260805d17
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Tue Jul 9 21:51:14 2013 -0600

    lib: Fix spelling
    
    Change-Id: I999987af9cb44906e3c3135c0351a0cd6eb210ff
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3756
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 63373edce006983d1e2aef7d71c1653ae337ed18
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Jul 8 16:24:19 2013 -0600

    device: Fix spelling
    
    Change-Id: I53a40d114aa2da76398c5b97443d4096809dcf36
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3730
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 50d887d4f4f5f4c4717a2308f4bf069d86ca4ff7
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Jul 8 16:22:54 2013 -0600

    console: Fix spelling
    
    Change-Id: I1fef27c4a16ee4358ace8014a8d6e9fa92c4f790
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3728
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7b5f8ef2eab7f1211888ae420d76176f49721601
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Jul 8 16:22:10 2013 -0600

    arch: Fix spelling
    
    Change-Id: Ifea10f0180c0c4b684030a168402a95fadf1a9db
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3727
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fb370130f6618d53f506566737f7394ee1417c55
Author: Gabe Black <gabeblack@google.com>
Date:   Sat May 18 21:41:59 2013 -0700

    ARM: Fix the way the space for the page tables is allocated.
    
    The page tables need to be aligned to a 16KB boundary and are 16KB in size.
    The CBMEM allocator only guarantees 512 byte alignment, so to make sure
    things are where they're supposed to be, the code was allocating extra space
    and then adjusting the pointer upwards. Unfortunately, it was adding the size
    of the table to the pointer first, then aligning it. Since it allocated twice
    the space of the table, this had the effect of moving past the first table
    size region of bytes, and then aligning upwards, pushing the end of the table
    out of the space allocated for it.
    
    You can get away with this if you push things you don't care about off the
    end, and it happened to be the case that we were allocating a color map we
    weren't using at the start of the next part of cbmem.
    
    Change-Id: I6b196fc573801b02f27f2e667acbf06163266651
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3651
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 63dd2cb62a780158571c4cf5465ce7953a0e38fc
Author: Gabe Black <gabeblack@google.com>
Date:   Sat May 18 15:52:01 2013 -0700

    exynos5250: When enabling the I2S pins, turn off pull ups/downs.
    
    These pins will be driven by the internal controller which shouldn't have pull
    ups or downs in the pin fighting with them.
    
    Change-Id: I579aed84ace45d8f5f1d3ca64c064d98de842b57
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3649
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ea9c98d454e4ea60452de1bbe38dfeea857c3142
Author: Gabe Black <gabeblack@google.com>
Date:   Fri May 17 02:57:17 2013 -0700

    exynos5420: Replace the 5250 GPIO code with code that should work on 5420.
    
    Change-Id: Iac6615240e94c74037afc801169c32d3ebc4ac03
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3648
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 919c8044255f83c7f86023c561a20e1b2d05a2ce
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 16 10:57:15 2013 -0700

    ARMv7: Clean up console code
    
     - Guard console_init() with CONFIG_EARLY_CONSOLE in bootblock
     - Don't initialize console twice in the bootblock
     - remove printk in memory init that would mess up the UART
     - unconditionally run console_init() in romstage, as it is
       also unconditionally run in the bootblock.
    
    Change-Id: I8f0d60877433162367074d0e55e01f935fd81f8e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3647
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d3163abd4310011c4616e757662d1777188b4a22
Author: Gabe Black <gabeblack@google.com>
Date:   Thu May 16 05:53:40 2013 -0700

    pit: Add a "pit" mainboard which is mostly a copy of "snow".
    
    This change adds a pit mainboard which is mostly a copy of snow, except that
    mentions of the 5250 were replaced with the 5420, and mentions of snow were
    replaced with pit.
    
    Change-Id: I8eb0ce379eb2fa353bb88d5656a0c5e2290afbf0
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3646
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b2d811aa9eae2f9292bd6e9eb3d7ee881ece0ab9
Author: Gabe Black <gabeblack@google.com>
Date:   Mon May 13 15:56:53 2013 -0700

    pit: Fix some settings for the exynos5420 CPU.
    
    Some of the settings which were defaulted to or automatically selected for the
    exynos5420 which were inherited from the exynos5250 were not correct for this
    SOC.
    
    Change-Id: I11ffd8a6b80628405ac493fe2139f79c05d15d7e
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3645
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 607c0b6d63f88c84661582800f2ee9a49325fcdb
Author: Gabe Black <gabeblack@google.com>
Date:   Thu May 16 05:45:57 2013 -0700

    pit: Create an exynos5420 directory which is nearly a copy of exynos5250.
    
    This change creates an exynos5420 directory with code that will eventually
    implement support for the exynos5420 cpu from Samsung. Currently it's a copy
    of the exynos5250 directory with the name changed. There are going to be some
    problems where headers in src/cpu/samsung/exynos-common include headers in the
    exynos5250 directory directly.
    
    Change-Id: Ia8d7244310d32499238bbc171c0c668ec48178e1
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3644
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dc006c1db4fa3606d657c78cc87dc13d056e970d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 15 14:54:07 2013 -0700

    ARMv7: De-uboot-ify Exynos5250 GPIO code
    
    The Exynos GPIO code has three different APIs that, unfortunately,
    were widely used throughout the code base. This patch is cleaning
    up the mess.
    
    Change-Id: I09ccc7819fb892dbace9693c786dacc62f3f8eac
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3643
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 08dc3571463d7226068d4a4c19d453859b148957
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 14 16:57:50 2013 -0700

    ARMv7: De-uboot-ify Exynos5250 code
    
    When starting the Exynos5250 port, a lot of unneeded u-boot code
    was imported. This is an attempt to get rid of a lot of unneeded
    code before the port is used as a basis for further ARM ports.
    
    There is a lot more that can be done, including cleaning up the
    5250's Kconfig file.
    
    Change-Id: I2d88676c436eea4b21bcb62f40018af9fabb3016
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3642
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f73de9b9752229f95b4c2196ebb96a1bb0740cfb
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 9 17:48:03 2013 -0700

    Update 3rdparty hash for latest ARM BL1 binaries
    
    Change-Id: Ice28114e5f53f510d305cd85d095044e2f4bd7b2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3740
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 2cccacff900908a76a1e2d9016a46283490e06f5
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Thu Jul 4 02:51:42 2013 +0200

    w83627hf/acpi: Fix endianess error in floppy drive enumeration code
    
    The enumeration results are stored as five DWORDs in one 20 byte buffer.
    Bytes 3, 7, 11 and 15 were used to set the lowest bit of each DWORD.
    ACPI uses little endian, so 1, 4, 8 and 12 are the correct indices.
    
    Change-Id: I793225cb1bb62fd148ecfa1e61e02f5d7be62cdb
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/3602
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b98dec032f0d8ee158e606bceef9766a905ad503
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 14 13:32:33 2013 -0700

    samsung/exynos5250: unify code
    
    It turns out that the exynos5-common code previously imported from
    u-boot is not common code at all but very specific to the 5250 and
    not compatible with the 5450. Hence, unify the directories exynos5250
    and exynos5-common. We will try to factor out common code while
    progressing with the 5450 port.
    
    Change-Id: Iab595e66fcd01eda8365c96fb8bef896f7602f03
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3641
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 043eb0e35f93b41348eb69061a6aa0355ef544bc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri May 10 16:21:58 2013 -0700

    Wield battle axe at ARM port
    
    This patch unfortunately incorporates a number of changes,
    all of which are making future ARM ports easier.
    
     - drop cruft that came in with u-boot
     - move serial console from mainboard Kconfig to Exynos Kconfig
     - factor out non-board specific wakeup code
     - move generic bootblock code from mainboard to Exynos
     - actually call arch_cpu_init()
     - remove dead code
     - fix up copyright messages
     - remove snow_ prefix from a lot of code to reduce the noise
       when creating a new mainboard based on that code.
    
    Change-Id: Ic05326edf5a7e1a691c5ff841a604cb9e351b562
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3640
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6adef0847e4a62abf00e489209d239c958447830
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 9 16:30:06 2013 -0700

    Rename hardwaremain() to main()
    
    ... and drop the wrapper on ARMv7
    
    Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3639
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2ae6d6f6de3d5fb6c1fdb039d0997814ac0b9798
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 9 16:16:13 2013 -0700

    ARMv7: normalize ramstage code flow
    
    In ram stage, all code flow should be tied to the resource allocator.
    Stuff that has to happen before everything else goes into the mainboard
    enable function in mainboard.c. This patch empties the main() wrapper
    around hardwaremain.c, allowing to get rid of this special case in the
    ARM port.
    
    Change-Id: Ide91a23f1043b64acf64471f180a2297f0f40d97
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3638
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 78c3e3355003ff2c0c2917f445e0c8dd3e083f52
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Apr 24 09:50:56 2013 -0700

    FUI: reorganize include files
    
    We've got enough of a handle on this to realize some things:
    drm_dp_helper.h is by design device and architecture independent
    i915.h is common to most intel graphics chipsets going back several years
    i915_reg.h is as well
    
    Move these files to src/include/device, and adjust the .c files accordingly.
    
    Change-Id: I07512b3695fea0b22949074b467986420783d62a
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3637
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b2893a0169ce603926bf13465432a15c4526de97
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Apr 23 10:59:11 2013 -0700

    Provide support for setting up the framebuffer from EDID
    
    Add three functions to edid.c:
    
    void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
    takes an edid and uintptr_t, and fills in a static lb_framebuffer struct
    as well as setting the static vbe_valid to 1 unless some problem
    is found in the edid. The intent here is that this could be called from
    the native graphics setup code on both ARM and x86.
    
    int vbe_mode_info_valid(void)
    returns value of the static vbe_valid.
    
    void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
    copies the static edid_fb to lb_framebuffer.
    
    There is now a common vbe.h in src/include, removed the two special ones.
    
    In general, graphics in coreboot is a mess, but graphics is always a
    mess.  We don't have a clean way to try two different ways to turn on
    a device and use the one that works. One battle at a time. Overall,
    things are much better.
    
    The best part: this code would also work for ARM, which also uses EDID.
    
    Change-Id: Id23eb61498b331d44ab064b8fb4cb10f07cff7f3
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3636
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3fb30eeb147fecb4124b63c353a7b8aac61d4c2a
Author: Gabe Black <gabeblack@chromium.org>
Date:   Tue Jul 9 13:15:05 2013 -0700

    ChromeEC: Fix the default, depends for EC_GOOGLE_CHROMEEC_I2C.
    
    The default for this variable should be n, it should only depend on
    EC_GOOGLE_CHROMEEC, and it should be (and is) explicitly enabled when
    needed. This prevents it from being turned on when the EC bus is SPI.
    
    Change-Id: Idc6651a764be4f055341a36b9b4a58990f050b0c
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3737
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 54d6abd276ac5c60e3846266050167cc1754dcf0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jun 19 23:05:00 2013 +0300

    Drop some duplicates of PCI-e config functions
    
    These are not specific to Intel. Further work needs to be done to
    combine these with MMCONF_SUPPORT in arch/io.h.
    
    Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3502
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 872c9222965909dffdd091e644b03e676ca2754f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 3 09:44:28 2013 +0300

    Fix MMCONF_SUPPORT_DEFAULT for ramstage
    
    Define at one place whether to use IO 0xcf8/0xcfc or MMIO via
    MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage.
    
    The implementation of pci_default_config() always returned with
    pci_cf8_conf1. This means any PCI configuration access that did
    not target bus 0 used PCI IO config operations, if PCI MMIO config
    was not explicitly requested.
    
    Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3606
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 20b6d91fd33f5d90d1c51e2fb813453349398b73
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Fri May 24 03:37:01 2013 +0200

    southbridge/intel/i82801gx: Make compilation possible with CONFIG_SMM_TSEG
    
    Without that fix, and with CONFIG_SMM_TSEG, we have:
      src/southbridge/intel/i82801gx/smihandler.c: In function 'southbridge_smi_sleep':
      src/southbridge/intel/i82801gx/smihandler.c:340:3: error: implicit declaration of function 'smi_release_lock' [-Werror=implicit-function-declaration]
      cc1: all warnings being treated as errors
      make: *** [build/southbridge/intel/i82801gx/smihandler.smm.o] Error 1
    
    The fix is modelled after src/cpu/x86/smm/smihandler.c which
      ifdefs smi_release_lock().
    
    Change-Id: Icdc6d039b34a1d95d0e607419bba2484d21abc5e
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3281
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1b32a51e515ce25495f87a82d1575d26acd93228
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sun May 26 18:24:41 2013 +0200

    i82801gx: smihandle:  sync with southbridge/intel/bd82x6x/smihandler.c
    
    Change-Id: Ic725b169061bd426aa8206dc1d6d31e67cc639f2
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3304
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b694f10c006168c8497d87d8f33da74724126d01
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sun May 26 18:12:54 2013 +0200

    southbridge: i82801gx: smihandler.c: Correct outl->outw mistake.
    
    This mistake was spoted by comparison with the
      src/southbridge/intel/bd82x6x/smihandler.c file.
    
    Change-Id: I1516f0131d524bd7d001e6780e9a45402d1814d1
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3303
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d1fb5641b6ae3710b7d6c444000a6cbbe0cb6f74
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Jul 1 16:02:36 2013 +0200

    sandybridge: Add option to lock SPI regions on resume
    
    Add an option to mark all SPI regions write protected on each S3 resume.
    We were used to lock the SPI interface in the payload which isn't run on
    the resume path. So we have to do it here.
    
    For the write protection to be effective, all write opcodes in the
    opmenu have to be marked correctly (as write operations) and the whole
    SPI interface has to be locked. Both is already done.
    
    Change-Id: I5c268ae8850642f5e82f18c28c71cf1ae248dbff
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3594
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4f78b187499d8e1f4a2fe3dad8e0997c91f15762
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Apr 17 16:57:30 2013 -0700

    fox_wtm2: First step support for coreboot-based graphics startup
    
    This code is the initial version of FUI for haswell and wtm2.
    
    The code is simplified from before in many ways. I've gotten rid of
    the opcode table, because it obscured meaning and I don't think it is
    needed any more. Register sets, mainly used for reset, are just lines
    of code -- not many of them. There are a bunch of not-yet-documented
    registers here; the VBIOS seemed to think they were necessary and
    testing shows they seem to be right.
    
    As a bit of added paranoia, we always include the VBIOS code as our
    emergency recovery path. You have to run it now anyways, so this is no
    regression from our current situation; and, if all goes well, in a
    week (or so), you'll never have to run it again, but like the Force
    and nose hair, it will be with you always.
    
    The code can return in three ways. The first, best way is success:
    panel is up and the VBIOS need not run. The second mode is that we
    tried to light up the panel but could not, for some reason, but will
    return with the panel partly up. In this case, it's ok not to power
    cycle the panel. The third, worst case, which will NEVER happen, ha
    ha, is that we have to turn the panel off and wait the required 600ms
    for it to cycle. Life sucks sometimes. This failure mode is in the
    'hang on we're going to fix it' category now that we have ramstage in
    RW.
    
    The Big Goal here is to create something other coreboot ports can use
    as well. The guys doing the x60 report that the link FUI works,
    without too many mods, on that chipset, so it seems Intel is keeping
    things from changing too much over time.
    
    Also, again, please note: this and the next 3 versions will ALWAYS fail.
    The goal is to verify the correctness of the recovery path.
    
    The bizarre tab-space formatting in drm_dp_helper.h is from the original,
    as in i915_reg.h
    
    Change-Id: I6ecf454633029d185c29d470980b5a0f3114a8ce
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3635
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2a66d6b804acd22fddc2e51550ba39d2561c1234
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Thu Mar 28 17:01:43 2013 -0700

    FOX_WTM2: First pass at FUI.
    
    This lights up the display. We don't get graphics but we are missing the gttsetup
    at this point, so that is no shock. The real shock is that anything works at all.
    
    Change-Id: I03fc470334e96878aeb8465044b3cc9c90378735
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3634
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f42b83e958f4529ef5a859494807914a5601d2f9
Author: Benoît Legat <benoit.legat@gmail.com>
Date:   Mon Jul 8 12:23:27 2013 +0200

    msrtool: Fix verbose ignored by cpuid().
    
    This is a trivial patch moving cpuid() call after reading argv
    so that verbose is set.
    
    Change-Id: Ic621191ef650495614a041413c1a0f707d4469e6
    Signed-off-by: Benoît Legat <benoit.legat@gmail.com>
    Reviewed-on: http://review.coreboot.org/3627
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 49f620221aee69cf0d5123a1e8f1e73896724934
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Mon Jul 8 19:59:33 2013 +0800

    Fix Vortex86EX devicetree.cb indentation.
    
    Change-Id: If357b55b91618ee2438e6c6b2efb7018c56d26d0
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3628
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d0b04003d0a3ebfa11f54128a2d423ca16b6ba8a
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jul 6 20:20:45 2013 +0200

    Revert "Radio and dock support in EC on X60 and X201"
    
    This reverts commit 7d1ebbff5ad224591a2d1972737611f96a13145c
    
    Change-Id: I4a9d0cd31a3df3d1e092193953f334697ca65167
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3616
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 8cfa33eb7c93c0b4fb24a520b4c521591720999d
Author: Gabe Black <gabeblack@chromium.org>
Date:   Tue Jun 11 21:58:18 2013 -0400

    am335x: Implement support for the UART.
    
    This patch was started by Dave Hendricks and implements the procedure for
    setting up the UART as described in the manual. Some unused code was removed.
    
    Change-Id: If26a424cac401ef3eafaec081147f41184fbcee9
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3490
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 8522f9940af8291772e37eef077339d6f3ffcda9
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Fri Jul 5 17:29:41 2013 +0800

    Add support for DMP Vortex86EX PCI mainboard.
    
    Change-Id: I8d42f765519e356d8f0cc6ed339d9b74f0a3e4d7
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3610
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f66dd6966a2df6af8ec4a4018f1538b1166256f7
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Jul 3 12:07:43 2013 +0200

    w83627hf/acpi: Fix offset of logical device activation
    
    The PnP's logical device activation normally resides at 0x30. This might
    have been overlooked as 0x29 looks very close to 0x30 in human eyes.
    
    Change-Id: Id5d5a92f2683ebe1808b943f686c062151d216da
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3592
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 0bd5dff58cb43b307bcb02ac6baa436a525a5025
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Thu Jul 4 02:54:04 2013 +0200

    w83627hf/acpi: Fix type error in floppy drive enumeration code
    
    The enumeration method tried to evaluate an one-byte OperationRegion
    instead of a field in this OperationRegion, which resulted in an
    AE_TYPE error at runtime.
    Indexing the OperationRegion with a single field fixes this error.
    
    Change-Id: I15dd7aa6ecafb3a215d165d2b721003446815025
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/3603
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9e974232e4896ee971745c5127cbc37f1682171b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 1 11:21:53 2013 +0300

    intel/i5000: Use MMCONF_SUPPORT_DEFAULT
    
    Change all PCI configuration accesses to MMIO on two boards
    with i5000 chipset. To enable MMIO style access, add explicit
    PCI IO config write in the bootblock.
    
    Change-Id: I26f1c2da5ae98aeeda78bdcae0fb1e8c711a3586
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3601
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 575e6817e690d1540bfa14a0b1fc7b8a40ef095a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 2 11:37:35 2013 +0300

    Move select MMCONF_SUPPORT under northbridge (fix)
    
    I missed the board with gm45 when I moved MMCONF_SUPPORT lines.
    
    Also, the intel/i3100 does not have MMCONF_SUPPORT implemented
    even though it was previously selected for intel/eagleheights board.
    
    Change-Id: I9c7f6b0a150b4d54288a1e015277b9d98467fca4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3598
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 032c23db08e6f0c6a2937092edafa26339aa4921
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 1 11:21:53 2013 +0300

    intel/i945: Use MMCONF_SUPPORT_DEFAULT
    
    Change all PCI configuration accesses to MMIO on all boards
    with i945 chipset. To enable MMIO style access, add explicit
    PCI IO config write in the bootblock.
    
    Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3584
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit fbdb085549b6c500e12dc2fb21143a197b4be042
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 1 11:21:53 2013 +0300

    intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT
    
    Change all PCI configuration accesses to MMIO on all boards
    with SandyBridge and IvyBridge. To enable MMIO style access,
    add explicit PCI IO config write in the bootblock.
    
    Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3576
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit 15c4ab7adf594e0707cdedded8fe6797b17da56a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 2 11:37:35 2013 +0300

    Move select MMCONF_SUPPORT under northbridge
    
    Move/remove MMCONF_SUPPORT reference under mainboard Kconfig, as
    that feature originates from northbridge and cannot be disabled
    for a single mainboard.
    
    Change-Id: I6d6861079876ddddaff90b10f18edb6936e93bd0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3589
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 00bf647bf6a980e8b9c3d8d91d79859c9b3de0a1
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Wed Jun 26 21:24:59 2013 +0800

    Add support for DMP Vortex86EX PCI southbridge.
    
    Change-Id: Iad11cb1b22e9d1e2953b12221541b1478cad9665
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3547
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dd94fa93b403a73cc7d7b282eb6cefeb27512d13
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Jul 1 16:29:16 2013 +0200

    winbond/w83627dhg: Fix logical device power down in ACPI
    
    The W83627DHG has some power managements bits to power down individual
    logical devices. These are called `* Power Down`. Counterintuitively and
    in contrast to `Immediate Power Down` (bit to power down the whole chip),
    these bits are set when the respective logical device is powered.
    
    Unfortunately, our ACPI code set them wrong which led to disabled
    devices after a S3 suspend/resume. Adding an option how to set the PM
    bits and setting them to zero for the W83627DHG, corrects it.
    
    Tested with kontron/ktqm77.
    
    Change-Id: I8a472d480d4277721bd17c9f7c2ce44fa84e8ae2
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3590
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1c81128dcd3a723f75d554b0a8d87101d7dd3663
Author: Nico Huber <nico.h@gmx.de>
Date:   Sat Jun 15 20:33:44 2013 +0200

    pnp: Add some default functions to enter/exit config state
    
    Implement some common default functions to enter and exit the
    configuration state. Also provide default pnp_mode_ops for common
    enter()/exit() function pairs.
    
    The following cocci ensures their use:
        @ mode_match @
        identifier enter, exit, ops;
        @@
         struct pnp_mode_ops ops = {
                 .enter_conf_mode  = enter,
                 .exit_conf_mode   = exit,
         };
    
        @ enter_match_8787 @
        identifier mode_match.enter, dev;
        @@
         enter(...)
         {
                 outb(0x87, dev->path.pnp.port);
                 outb(0x87, dev->path.pnp.port);
         }
    
        @ depends on enter_match_8787 @
        identifier mode_match.enter, mode_match.ops;
        @@
         struct pnp_mode_ops ops = {
        -        .enter_conf_mode  = enter,
        +        .enter_conf_mode  = pnp_enter_conf_mode_8787,
         };
    
        @ enter_match_55 @
        identifier mode_match.enter, dev;
        @@
         enter(...)
         {
                 outb(0x55, dev->path.pnp.port);
         }
    
        @ depends on enter_match_55 @
        identifier mode_match.enter, mode_match.ops;
        @@
         struct pnp_mode_ops ops = {
        -        .enter_conf_mode  = enter,
        +        .enter_conf_mode  = pnp_enter_conf_mode_55,
         };
    
        @ depends on enter_match_8787 || enter_match_55 @
        identifier mode_match.enter;
        @@
        -enter(...) {...}
    
        @ exit_match_aa @
        identifier mode_match.exit, dev;
        @@
         exit(...)
         {
                 outb(0xaa, dev->path.pnp.port);
         }
    
        @ depends on exit_match_aa @
        identifier mode_match.exit, mode_match.ops;
        @@
         struct pnp_mode_ops ops = {
        -        .exit_conf_mode   = exit,
        +        .exit_conf_mode   = pnp_exit_conf_mode_aa,
         };
    
        @ depends on exit_match_aa @
        identifier mode_match.exit;
        @@
        -exit(...) {...}
    
        @ depends on enter_match_8787 || enter_match_55 || exit_match_aa @
        @@
         #include <device/pnp.h>
        +#include <superio/conf_mode.h>
    
        @ mode_match_55_aa @
        identifier ops;
        @@
         struct pnp_mode_ops ops = {
                 .enter_conf_mode  = pnp_enter_conf_mode_55,
                 .exit_conf_mode   = pnp_exit_conf_mode_aa,
         };
    
        @@
        identifier mode_match_55_aa.ops;
        @@
        -struct pnp_mode_ops ops = {...};
    
        @@
        identifier mode_match_55_aa.ops, devops;
        @@
         struct device_operations devops = {
        -        .ops_pnp_mode     = &ops,
        +        .ops_pnp_mode     = &pnp_conf_mode_55_aa,
         };
    
        @ mode_match_8787_aa @
        identifier ops;
        @@
         struct pnp_mode_ops ops = {
                 .enter_conf_mode  = pnp_enter_conf_mode_8787,
                 .exit_conf_mode   = pnp_exit_conf_mode_aa,
         };
    
        @@
        identifier mode_match_8787_aa.ops;
        @@
        -struct pnp_mode_ops ops = {...};
    
        @@
        identifier mode_match_8787_aa.ops, devops;
        @@
         struct device_operations devops = {
        -        .ops_pnp_mode     = &ops,
        +        .ops_pnp_mode     = &pnp_conf_mode_8787_aa,
         };
    
    Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3484
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit abe6847cd21b553dd66fcb0540de166f82ebaf00
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed May 8 17:08:55 2013 +0200

    Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c`
    
    Use the same indentation, comment placement and spelling of words.
    Run `indent -linux …`.
    
    Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3220
    Reviewed-by: Nico Huber <nico.huber@secunet.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 59158b2fb0eda826feaa7ae99d5fe2a284c569d3
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Mon Jul 1 14:19:48 2013 -0600

    Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900
    
    The MAX_PIRQ_LINKS is defined in src/Kconfig with a default value
    of 4. The src/northbridge/via/vx900/Kconfig also defines
    MAX_PIRQ_LINKS with a default of 8 and it ends up giving us
    a value of 8 for non-VIA platforms.
    
    Change-Id: Iee1938d38a93ab7c35c8cb6fe9656a92cf3fa21e
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3586
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit dda4095101f8e04924d32dbabfd038b32a93961c
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Tue Jun 18 01:26:50 2013 +0200

    w83627hf: Add comments about parallel port modes in superio.asl
    
    Add comments in PAR0._PRS explaining which dependent resource
    descriptor puts the parallel port into EPP or SPP mode.
    
    Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/3495
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit e978fc265d22d54146ba167b63ed0e3a6d4875a5
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Sun Jun 30 01:05:30 2013 +0200

    cbmem: Fix makefile
    
    The .dependencies rule did not use the CPPFLAGS variable which led
    to funny behavior: a spurious termination message the first time
    (after checkout/make distclean) one executes make. Afterwards the
    (wrongly) empty .dependencies file hides the problem and the binary
    is created anyway.
    
    $ make
    cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory
    compilation terminated.
    cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
    cc   cbmem.o   -o cbmem
    
    $ make
    make: Nothing to be done for `all'.
    
    $ make clean
    rm -f cbmem *.o *~
    
    $ make
    cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
    cc   cbmem.o   -o cbmem
    
    $ make distclean
    rm -f cbmem *.o *~
    rm -f .dependencies
    
    $ make
    cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory
    compilation terminated.
    cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
    cc   cbmem.o   -o cbmem
    
    I fixed that by adding the CPPFLAGS variable to the .dependencies recipe, just
    like Stefan Reinauer did in Chromium (Ia9d2e10a3ef122f30d681d16c2291eb108ead835),
    hence the split sign-off for this tiny change. :)
    
    Change-Id: Icd11b146ad762cbdf9774630b950f70e1253a072
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3548
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit 595ab4f955c98ee486cde7adc1af4eb56cebe569
Author: Gabe Black <gabeblack@chromium.org>
Date:   Sat Jun 29 23:20:14 2013 -0700

    beaglebone: Enable the clocks and pins for the configured UART.
    
    Set up the pinmux to enable the pins and the clocks for whichever UART is
    currently configured.
    
    Change-Id: Iac13f16d9d84320555b99734ea83eafd0a2803fe
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3573
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 94f631cdc9805d61071c29d25a0af9ddea174c22
Author: Gabe Black <gabeblack@chromium.org>
Date:   Sat Jun 29 22:55:15 2013 -0700

    am335x: Fix the address of the pinmux registers.
    
    The pinmux register data structure describes a subset of the control module
    registers, but the address which pointed to the base of the pinmux registers
    was actually being set to the beginning of all the control module registers,
    not just those having to do with the pinmux. With this address fixed, the UART
    now works on the beaglebone black.
    
    Change-Id: I7c99b6f37d7da359af074127cd0c1a86fda2d9a0
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3574
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit caaf0bf483288ea092d721954df0407930c67fc8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 6 10:21:28 2013 +0300

    usbdebug: Support i82801dx/ex southbridge
    
    Tested on i82801dx system with board aopen/dxplplusu.
    
    Change-Id: I522455ac79c87b9b6fc9cd8c4dc0da3563dfbfad
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3381
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 54c586c7e76d9e9ec75ccebaf1555b3fde6114e8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jun 10 11:40:54 2013 +0300

    usbdebug: Unify Intel southbridge builds
    
    EHCI controller enable is identical on the affected chipsets.
    
    Change-Id: I91830b6f5144a70b158ec1ee40e9cba5fab3fbc9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3424
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit fb387dfb920f73abb144183b8a41dc917e2e32da
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 7 22:16:52 2013 +0300

    usbdebug: Drop duplicates of EHCI BAR relocation code
    
    All the additional work that needs to be done in EHCI BAR relocation
    is independent of the hardware platform and was functionally identical
    in all the copies removed.
    
    When USBDEBUG is not selected, PCI EHCI controllers use standard
    pci_dev_read_resources() call.
    
    With USBDEBUG selected, PCI EHCI controller's device_operations
    .read_resources is replaced with pci_ehci_read_resources() call,
    which in turn will replace the device_operations .set_resources call.
    The replacement for .set_resources reconfigures usbdebug driver side,
    and calls the original .set_resources to configure hardware side.
    
    Change-Id: I8e136a5da4efedf60b6dd7068c0488153efaaf8e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3412
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 0d8d482f6316885d7e553d9aeb538ce5bbd2fbba
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Sat Jun 8 10:25:06 2013 +0800

    AMD S3 resume: Add framwork to write bigger data
    
    This patch is based on 'AMD S3: Program the flash in a bigger data packet'[1]
    
    Some AMD south bridge can write bigger data when saving S3 info.
    In this patch, I use config 'AMD_SB_SPI_TX_LEN' to contral data size.
    AMD_SB_SPI_TX_LEN is defined in 'src/southbridge/amd/Kconfig'
    and then can be overridden in the Kconfig for specific
    southbridges that support larger size.
    
    I have tested on AMD Parmer and Thatcher. We will release a new board
    whose south bridge can transfer more than 4 bytes each time.
    
    [1] http://review.coreboot.org/#/c/2306/
    
    Change-Id: Id984955d46eae487e39d45979f1a90054aa9f54b
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3413
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bc2c9efd56a1b7d5c9b97132423ac176b4d21b74
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Wed Jun 26 20:04:49 2013 +0200

    ELOG: Fix warning to fix the compilation.
    
    Without that fix we have:
      src/drivers/elog/elog.c: In function 'elog_is_header_valid':
      src/drivers/elog/elog.c:213:3: error: format '%u' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format]
    
    Change-Id: I71b80a94c03a04eedb688ae107d92c05a878315e
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3551
    Reviewed-by: Nico Huber <nico.huber@secunet.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit c9246da4ddff9fef2bb26d05d87d1f616124b91e
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Thu Jun 27 17:06:27 2013 +0200

    libpayload: Add strerror
    
    Change-Id: I33d45ad7d09473b8c6f5b7ee5fbadc0d184f9dcd
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3537
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit c0b1a48cdaed0a9c955fd98563a1d5906a72b533
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 27 17:17:26 2013 -0700

    Drop WARNINGS_ARE_ERRORS exceptions
    
    Thanks to Bruce's great work, we can finally drop this workaround.
    
    Change-Id: Ie92d1e53ef867fa34aa2489ccfb682d73195b213
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3569
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 160243d73e13f1857299b980a88eb3a0cd7fc4fb
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 19:13:28 2013 -0600

    Supermicro H8SCM/H8QGI: Increase size of bus variable to meet API
    
    Users of mptable_write_buses() pass two pass-by-reference
    parameters reflecting a maximum bus number and a search bus
    number.  These bus numbers are expected to be held in "int"
    variables and are updated by the function.  Both of the
    Supermicro boards define the search bus number as a
    byte value in mptable.c.
    
    For now, change the two Supermicro boards to use "int"
    to hold the search bus index.
    
    Change-Id: Ie71850719c1fa3cda0ac9c8773bb80650de95c70
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3546
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e8dca508d30ae84daebdf8f1acdde942e5e2c57b
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 14:02:41 2013 -0600

    AMD Dinar: Eliminate warnings (initializers/prototypes/unused var)
    
    Fix a bunch of compiler-generated warning messages.  These fixes are
    mainly braces for grouping initializers.  These changes are not
    intended to change any code functionality.  There are two changes where
    function prototypes are added, and two cases where unused variables are
    eliminated.
    
    Change-Id: I93cef8899170b5575e7fb7c55181b381a7bcd9d8
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3545
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 21d6fd9d7819ffbf5416e612d7db87a0afd4d29a
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 14:01:21 2013 -0600

    AMD SB700 boards: Set Azalia configuration flags
    
    The existing code for setting Azalia configuration assumes that
    the configuration bits are contiguous within a single byte and
    can be set using a byte copy addressed into the lowest 2-bit
    subfield.
    
    The fix in Family 14 defines a union that can be addressed as a
    byte to overlay the bit fields.  Since the offset of the four
    subfields is not necessarily fixed, change the code to initialize
    each of the four subfields individually.
    
    Change-Id: I1dff20bb8bd3e1bcd8b4e6b0537e20779d2a3521
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3544
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f9ba7bb4f95f9b8f2626d6c8c23adbd145903fff
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 13:59:36 2013 -0600

    supermicro/h8scm: Add a type cast for printk to correct a warning message
    
    Copy a type cast from the other cases of the same switch statement
    to eliminate compiler warning messages.
    
    Change-Id: I8d0a88892f6a5f8e43227ab5f830041894b07f6a
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3543
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 93b57c55a9424060e5c8024ab18311f087696db3
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 19:27:17 2013 -0600

    Dinar, H8SCM, H8QGI: Add prototype of get_bus_conf()
    
    On Dinar, H8SCM, and H8QGI, add <cpu/amd/amdfam15.h> as an
    include to pick up the prototype definition of get_bus_conf().
    
    Change-Id: Ie4887670ac52aa194745881362df19cd1d75773e
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3542
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 01677b6625bff61b6abc570cf7aec3146c7a8d47
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 14:29:08 2013 -0600

    amd/cimx/sb700/late.c: Add type cast to (UINT8)
    
    This change inserts a type cast to eliminate a compiler warning.
    
    Change-Id: If223f61f1565caeadb1b7e0762975b1b2412eda5
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3541
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 53abac1767c5c40ce0eafe729cd04cca1fcc8292
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 14:27:16 2013 -0600

    amd/cimx/rd890/amd.h: Eliminate redefinition of NULL
    
    This change replaces a redefinition of NULL with the standard
    definition from <stddef.h> to eliminate a compiler redefinition
    warning.
    
    Change-Id: I441fa569f545c0efb00284b5ee58aa27cb6617ba
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3540
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 58fff9d44f14c750aacd63a700581f314d656ef8
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 14:21:44 2013 -0600

    amd/agesa/family15/northbridge.c: Delete unused variable
    
    This change eliminates an unused variable that causes a build warning.
    
    Change-Id: I02487c7dd80d458f562d7afe1827eefcc0fb678b
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3526
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1cc3416f5fb58883fdad7192856c258c01909fd7
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 27 15:59:18 2013 -0700

    Add support to enable/disable builtin GbE (again)
    
    This requires a new system agent binary (v6 / v11 on haswell).
    Note that the existing system agent binaries are long time obsolete
    and won't work with current coreboot, so this update is overdue.
    
    Change-Id: I48d8649576ca84d2b85ab082ce06f3462e189059
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3568
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e44a89f6fd4f421f28ef766b380dca112bf4aea2
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 14:14:14 2013 -0600

    amd/agesa/f15/Lib/amdlib.c: Add missing breaks to switch statement
    
    Static analysis often flags case statements that do not include
    a terminating "break;" statement. Eclipse's CODAN is an example
    of this.  This changelist modifies amdlib.c to terminate
    case statements with "break;".
    
    Change-Id: I3d43acaf64e2e2d9717421cb547fec35e582cf8b
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3539
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit af881b898a11eb5c56407475441f4795548f84a2
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 14:53:24 2013 -0600

    amd/agesa/f15/Proc/CPU: Add length modifier to eliminate compiler warnings
    
    This change adds length modifiers to constant values to eliminate
    compiler warning messages.
    
    Change-Id: I032cb37cec788e2b5f79f5bbf9efc19a7892dc14
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3538
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 940ccaa51066e776ceb8fd59157ab93a619a9ef6
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 25 14:50:57 2013 -0600

    vendorcode/amd/agesa/f15: Eliminate compiler warnings
    
    This change is mostly type casts to eliminate compile time
    warnings. These specific changes are mostly cherry-picked from
    AMD Family 14 code and, as such, contain artifacts copied over
    from F14. For example, there are a number of UINT64 casts that
    are commented out rather than removed.  This is to maintain
    consistency between AGESA versions.  Ultimately, this is in
    preparation for turning on warnings as errors for AMD Family 15
    server parts.
    
    Change-Id: Ic73d0b6ebab18d97015a9dd1130aff4e5e432fb7
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3525
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 673762906b6068d86210873fb681d0694591d4be
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 27 15:34:58 2013 -0700

    Update 3rdparty mark to latest repository
    
    For new systemagent v6 binaries.
    
    Change-Id: I550533fd19c7c5592f3e3c9b514efe2750619c8f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3567
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9aedd918d38ce3bd4f8893b37b6d68bfb4aa99b1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 27 15:32:05 2013 -0700

    gitmodules: Fix 3rdparty updates
    
    Commit 039223a: gitmodules: Ignore 3rdparty in "diff family"
    changed the behavior of our 3rdparty repository and disallowed
    updates to the checked out hash. Instead of "ignore=all" we
    want "ignore=dirty" to ignore local changes but allow changing
    to the HEAD of the 3rdparty repo.
    
    Change-Id: I66c35ad4fcfb0efb0ba611f67648a096a6de1479
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3566
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cb47d89bbba78e370a420d4f15b631c9ce7532c8
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Tue Jun 25 18:48:31 2013 +0200

    libpayload: Add more integer limits
    
    Change-Id: If0963237806804a2a9d7f622c33013321379a04d
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3536
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 3509ad366dceb346025d6882a59a7b6a4a357ee9
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Tue Jun 25 19:25:46 2013 +0200

    libpayload: Fix whitespace errors
    
    Change-Id: Ibc36988745cbc7ede2a00da376b5dd295014ffb1
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3535
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 714212a42115b205b132a901bf86b8876d6aa3f0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jun 26 23:20:13 2013 +0200

    Revert "Add support to enable/disable builtin GbE"
    
    This reverts commit d358a506c4230950e34d783bd0187cd200d60691
    
    http://review.coreboot.org/#/c/3514/ comments:
    The pei_data version changed to 6, so new binaries are needed.
    
    However, demand for new binary blob is not referenced with this commit nor is git submodules hash updated. Also the new binary blob almost doubles its size and no longer fits in the allocation sandybridge defines.
    
    Change-Id: I84eb70517d5b9278c611fdfa587a71f6ca0f657f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3553
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6a008363befb049291fa4a123aa38b2ab2a04701
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Jun 25 15:19:48 2013 +0200

    libpayload: Use longer delay in tinycurses' wgetch()
    
    The counted delay of 1ms was shorter than the time usb_poll() took
    (~30ms observed). So with a given timeout of 100ms it actually took 3s.
    We can lower the problem if we delay 10ms per loop iteration.
    
    Change-Id: I6e084bdd05332111cc8adcd13493a5dfb4bc8b28
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3533
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 99b024db885833ebe46be0917f9c2283e3778fac
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Jun 24 12:39:53 2013 +0200

    bd82x6x: Fix early USB BAR programming (finally?)
    
    The xHCI controller's MMIO space has a length of 64KiB not 4KiB.
    Therefore, setting the xHCI BAR to 0xe8001000 worked the same like
    setting it to 0xe8000000, as bit12 is reserved and ignored. This again
    interfered with the MMIO space of the first EHCI controller and broke
    S3 resume on Ivy Bridge.
    
    AFAIK, the MRC ignores the setting of the xHCI BAR, anyway. So just drop
    these lines.
    
    Change-Id: I8af9c2ba34133f15636a9056fc8880b3b6ab95e0
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3521
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit c000352d5cd3419586107fc93f978fdd94492d5f
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jun 25 11:14:03 2013 +0200

    ktqm77: redesign cmos.layout slightly
    
    BIOS write protects 8 bytes of CMOS, which nvramtool can't cope with.
    This makes initial installation harder, so just mark those as reserved
    to work around the issue.
    
    Change-Id: I210861dff8572e226a0f250556a3b811671ea8f2
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3531
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cb76136420c73eb4f3122137b441835eee147c61
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Feb 21 14:33:25 2013 +0100

    libpayload: Make lpgcc wrapper usable for in-tree builds
    
    Teach lpgcc to look in the in-coreboot tree directory structure, too.
    
    Change-Id: I3809456d072ce2f91542b0edb3fd39f536298cc2
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3530
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8b9d4f3296ce5b6804963bfcc56cd741bb66e7ab
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Tue Jun 25 15:16:03 2013 +0800

    Vortex86EX northbridge.c : Remove Vortex86DX PCI N/B related code.
    
    6021 is Vortex86DX northbridge PCI device ID, not for Vortex86EX.
    
    Change-Id: I9bea799c9033adbcfacc8ad47052280a32f9ee59
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3529
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 99fd30e486146d6ad83cec5a56be8268cf0a645a
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Jun 19 15:57:34 2013 +0200

    sandybridge: Make inclusion of me.bin optional
    
    Current build configuration always wants to include an Intel Management
    Engine firmware (me.bin) on Sandy Bridge systems. However, we can have
    a working coreboot without it, as long as the factory delivered ME
    firmware is kept untouched in the flash ROM. So let the user decide if
    a ME firmware will be included in the build.
    
    Change-Id: I9a1cc29d4940ba22355eb9e653606e436f07e04c
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3522
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 59fb82aab1554889d4e51d988eb8927c7d31babd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jun 19 23:05:00 2013 +0300

    intel/sch: Use MMCONF_BASE_ADDRESS
    
    For iwave/iWRainbowG6 using intel/sch, MMCONF_BASE_ADDRESS was unused
    and different from hardware setting. Change that to match hardware
    programming.
    
    Change-Id: I3324b7ea0e6f092206d4b6b791476d538e826657
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3507
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 66a68a2af8b9c65d3d86a49459ed8217347d2cb1
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Fri May 31 13:33:30 2013 -0600

    abuild: Add xgcc tools to the path
    
    abuild checks the path for toolchains prior to building a
    mainboard. It didn't check xgcc/, which would be picked up
    by the coreboot make, and fail to build when it shouldn't.
    
    Change-Id: If0ca4238e8c57a6b015fdad623ccdbf237ef1ba6
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3350
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 413b0d98462dc877cc53355f425923c116bb490c
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Jun 19 12:41:19 2013 +0200

    ifdfake - Create an IFD with just a section layout
    
    This new tool called `ifdfake` just creates an empty Intel Firmware
    Descriptor (IFD) and writes the IFD signature plus the section layout
    given on the command line.
    
        usage: ifdfake [(-b|-m|-g|-p) <start>:<end>]... <output file>
    
           -b | --bios       <start>:<end>   BIOS region
           -m | --me         <start>:<end>   Intel ME region
           -g | --gbe        <start>:<end>   Gigabit Ethernet region
           -p | --platform   <start>:<end>   Platform Data region
           -h | --help                       print this help
    
        <start> and <end> bounds are given in Bytes, the <end> bound is inclusive.
        All regions must be multiples of 4K in size and 4K aligned.
        The descriptor region always resides in the first 4K.
    
        An IFD created with ifdfake won't work as a replacement for a real IFD.
        Never try to flash such an IFD to your board!
    
    The output of ifdfake can be utilized to build an image with just the
    later added sections (like coreboot itself) being valid. The resulting
    image can then be partially written to a machines flash ROM to just
    update coreboot (i.e. the BIOS section).
    
    Change-Id: I925b47cab5c6d490a79d684bdd7a7a45ac442640
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3523
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit efe1feda19e4799a2acb2e57205604662dde17cc
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Apr 29 18:00:57 2013 +0200

    kontron/ktqm77: New board
    
    Change-Id: Ife1c0a8597c2de04773899cdd87af6b6c630906a
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3392
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a15cd66b9ecba4033ec4ccf767847876236af70b
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Jun 19 16:16:05 2013 +0200

    sandybridge: Make build possible without descriptor.bin
    
    On newer Intel systems, the flash ROM is shared between the host
    processor (BIOS), it's Management Engine (ME) and an integrated ethernet
    controller (GbE). The layout of the flash ROM (and other information) is
    kept in the so called Intel Firmware Descriptor (IFD). If we only want
    to build coreboot to update the BIOS section, all we need is the flash
    layout.
    
    This patch adds the option to specify the flash layout in the
    mainboard's Kconfig, and thus, to build without the real IFD. However,
    with such a build, one has to make sure that the IFD section on the
    flash ROM won't be written over (nor any other section that hasn't been
    included by coreboot). A patch to write selected sections of a flash ROM
    with IFD has been sent to the flashrom mailing list [1].
    
    [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
    
    Change-Id: Ia23e439a00a197fb54852263f8e206f16c3e8851
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3524
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6aeb4a269c2ded6e6f72bf87da12b9295ef903f7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jun 11 17:00:11 2013 +0300

    AMD: Drop empty root_complex
    
    There are no files to build left under AMD nortbridge/x/root_complex
    directories. For some cases, even the Kconfig file was no longer sourced.
    Remove all such references and empty files.
    
    For devicetree.cb treat component paths with "/root_complex" in them valid
    even when the directory does not exists. This is because AMD boards us this
    dummy chip component as the root node in their devicetree.cb.
    
    The generated devicetree file static.c remains unchanged.
    
    Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3434
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit ef561a5582963b21d098e671cfb83ac7bb4819a1
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon May 27 18:45:32 2013 +0200

    Asus F2A85-M: Add IRQs for IOMMU
    
    The IOMMU needs IRQs assigned. So add those.
    
    Change-Id: Ic9f02e28aac593cddf7d222a8abb780a10572d32
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/3318
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5ce0506618c653c663251f94447e23f8c3f39fb7
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon May 27 16:09:44 2013 +0200

    AMD Fam15tn: Add support for AGESA runtime allocation in CBMEM
    
    The IOMMU AGESA needs a reserved scratch space and it wants
    to allocate the stuff for runtime. So provide a simple
    allocator for 4 KB CBMEM page.
    
    Change-Id: I53bdfcd2cd69f84fbfbc6edea53a051f516c05cc
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/3315
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 88ebbeb7e2a914330c869147bacb190b4270532f
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon May 27 16:06:43 2013 +0200

    AMD Fam15tn: Add IOMMU BAR allocation to northbridge
    
    For IOMMU we need to allocate a 512 KB BAR in a non-standard
    location. Use the standard allocator for that and limit the BAR
    to 32-bits to be compatible with older systems.
    
    Change-Id: I44414ce6b264b7f1c086a9b1c7ea275a0830205e
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3314
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 81d3d7d00173eafff0ef134bdf1ee5e632f3868a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jun 15 12:30:13 2013 +0300

    lynxpoint: Fix early EHCI BAR programming
    
    LynxPoint LP has only EHCI controller #1.
    Change EHCI #2 to different BAR from EHCI #1.
    
    Even if the ECHI controllers are not to be addressed, it is bad idea
    to set two different devices to claim the same PCI memory cycles.
    
    Change-Id: I95c59fb9d5f09afd152872e9bc0418dc67e4aeb2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3472
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit dbc6fcd021759280c71b0e246c0ede34f4879bac
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Thu Jun 20 18:05:06 2013 +0200

    inteltool: add initial support for Nehalem
    
    Also, add pretty printing of Westmere's DMI registers (tested on my t410s
    by staring at non-zero output values :)
    
    Apparently Nehalem does not have a MEMBAR? But there are some
    documented memory controller control registers in PCI configuration
    space... left out for now.
    
    The PCIEXBAR is not documented publicly AFAICT, but there is
    a similar register on a device on bus 0xFF. phcoder might know more...
    
    Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3505
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a390d779668146b60fdb89eaa709054d7811df7e
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Jun 22 13:47:06 2013 +0200

    AMD boards: routing.asl: Uniformly start `Package()` with capital letter
    
    In commit  Rudolf Marek discovered, that it is not uniformly written. As
    »ASL names are not case-sensitive and will be converted to upper case.« [2]
    this change does not have any functional change.
    
    The following command was used to create this patch.
    
        $ git grep -l 'package()' src/mainboard | xargs sed -i 's,package(),Package(),'
    
    [1] http://review.coreboot.org/#/c/3318/
    [2] http://www.acpi.info/spec40a.htm
        (18.2.1 ASL Names)
    
    Change-Id: I1784dbc50936a1ef9d4376209a3c324ef1fb85cf
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3516
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit eac00d2dbbe57e10a130ea1c0c6d943c2a9f19c1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 21 15:37:55 2013 +0300

    intel/sandybridge: Locate CBMEM TOC early in ramstage
    
    This patch allows the use of migrated CAR_GLOBAL variables from
    the very beginning of ramstage. Without the patch, CAR_GLOBALS were
    not available until northbridge set_resources().
    
    Change-Id: Ifd4ab2ed52e07dcbe8c77e2e460dc483323e93c0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3513
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 7f5897a1c5bcd6062169368b827975faa9feeebf
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Jun 21 18:02:26 2013 +0300

    Do CAR variable migration only once
    
    Non-S3 resume paths of sandy/ivybridge call cbmem_initialize()
    more than once. Doing car_migrate_variables() more than twice caused
    at least loss of some lines in CBMEM console.
    
    Change-Id: Idd14aba9384984aa3a7d38937a4b3572aa5dc088
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3512
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 065107259774169db73c42e9a2d5777f63a78c29
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Fri Jun 21 21:37:05 2013 +0800

    Add support for DMP Vortex86EX PCI northbridge.
    
    Change-Id: I60675a357f9db430ebb59b17be6d8c92a9cadf43
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3511
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 378d04640d4e946be45952625c9f85efda9066ad
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Wed Jun 19 08:30:33 2013 +0200

    qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM.
    
    This commit was tested on qemu with and without CONFIG_DYNAMIC_CBMEM
      by running cmbmem -c once booted. The qemu command that was used was:
        qemu-system-i386 -bios ./build/coreboot.rom  -serial stdio -hda ../virt/parabola.img
    
    Note that using CONFIG_RELOCATABLE_RAMSTAGE make it fails like that:
      Loading image.
      CBFS: Decompressing stage fallback/coreboot_ram @ 0x3ffbefc0 (184400 bytes)
      Loading module at 3ffbf000 with entry 3ffbf000. filesize: 0x18db8 memsize: 0x2c050
      Processing 1703 relocs with adjust value of 0x3ffbe000
      FATAL: Essential component is missing.
    However without CONFIG_RELOCATABLE_RAMSTAGE set it boots fine.
    
    Change-Id: I633a8c3832eee4e8bed244940fdc370b98dd26f0
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3504
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit d358a506c4230950e34d783bd0187cd200d60691
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 20 16:23:40 2013 -0700

    Add support to enable/disable builtin GbE
    
    In case we are going to use this in future designs.
    
    BUG=none
    TEST=none
    BRANCH=none
    
    Change-Id: I750addf10e4fe6f8240f8c8262253f8af7027e29
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: https://gerrit.chromium.org/gerrit/55844
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3515
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8a0a8488fec6ee3b94e9f1416cc839a20e47573e
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Thu Jun 20 16:24:14 2013 +0200

    Dynamic cbmem: don't compile src/lib/cbmem.c when dynamic cbmem is selected.
    
    src/lib/cbmem.c is for the static cbmem.
    
    Thanks to adurbin for the Makefile.inc pointer and code on #coreboot IRC channel on freenode:
      <adurbin> no. if you have CONFIG_DYNAMIC_CBMEM then cbmem.c shouldn't be compiled
      [...]
      <adurbin> +ifeq ($(CONFIG_EARLY_CBMEM_INIT),y)
      <adurbin> +ifneq ($(CONFIG_DYNAMIC_CBMEM),y) romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c
      <adurbin> +endif
      <adurbin> +endif
    
    Without that fix we have:
      src/lib/cbmem.c:58:43: error: no previous prototype for 'get_cbmem_toc' [-Werror=missing-prototypes]
      src/lib/cbmem.c:76:6: error: no previous prototype for 'cbmem_init' [-Werror=missing-prototypes]
      src/lib/cbmem.c:107:5: error: no previous prototype for 'cbmem_reinit' [-Werror=missing-prototypes]
    
    This commit was tested on qemu-i440fx with the following commit:
      qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM
      ( http://review.coreboot.org/#/c/3504/ ).
    
    Change-Id: I98636aad4bb4b954f3ed3957df67c77f3615964a
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3503
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit e761b71e52e699abcfd22cc5e931b89cf354476e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jun 15 12:29:23 2013 +0300

    bd82x6x: Fix early EHCI BAR programming
    
    Change EHCI #2 to different BAR from EHCI #1.
    
    Even if the ECHI controllers are not to be addressed, it is bad idea
    to set two different devices to claim the same PCI memory cycles.
    
    Change-Id: Ib6f7cfac5acf3f8170508547d1584af90273e8c1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3471
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit cca685936aeadfba65ecbeb854dbe632d6c89e95
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jun 20 14:08:27 2013 -0700

    fix bootstate typo (bs_dev_eanble -> bs_dev_enable)
    
    Change-Id: I2e3fd58404c48e863a3a1b255337fb397086651b
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3506
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 52e665bdd2c71b86643cbb1ee7e2fa5e96223059
Author: Andrew Wu <arw@dmp.com.tw>
Date:   Wed Jun 19 18:55:08 2013 +0800

    Add initial support for DMP Vortex86EX CPU.
    
    Change-Id: I74de250c69a57109362be1b2f00c0b4aa24a64e8
    Signed-off-by: Andrew Wu <arw@dmp.com.tw>
    Reviewed-on: http://review.coreboot.org/3473
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 483ff8253943b134e5e07ac89d08e49fca1c28d8
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jun 18 11:34:01 2013 +0200

    sandybridge: Store MRC cache in CBFS
    
    Location is hard-coded right now, which isn't optimal.
    It must be chip erase block aligned, which might fail on some flash chips
    (it's 64k aligned which should work for most cases).
    
    Change-Id: I6fe0607948c5fab04b9ed565a93e00b96bf44986
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3497
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 44c392f8c27a019ac0ac076c2e6b16d55c624c3b
Author: Nico Huber <nico.h@gmx.de>
Date:   Sun May 26 19:37:47 2013 +0200

    lenovo/t60: Collect timestamps in romstage
    
    Collect early timestamps in T60's romstage like some newer boards do.
    This should also work on X60s (and other ICH7 based systems with
    EARLY_CBMEM_INIT).
    
    Change-Id: I3b2872dd7423f3379ff3b68ad999523ec35fc08e
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3499
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9359f2de0033cfb47fab01b2c73ae36408281fbb
Author: Nico Huber <nico.h@gmx.de>
Date:   Tue Jun 18 22:36:34 2013 +0200

    intel/i82801gx: Store initial timestamp
    
    Upgrade the ICH7 bootblock to store an initial timestamp like we do it
    since Sandy Brigde. I've checked the datasheets for the used scratchpad
    registers and grepped for their usage. I'm pretty sure that they aren't
    used on any ICH7 based board (for anything before the usual S3-resume
    indication).
    
    Change-Id: I28a9b90d3e6f6401a8114ecd240554a5dddc0eb5
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3498
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 414b9478518836ce72084edba1c3a51b0a745d0c
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Tue Jun 18 23:41:21 2013 +0200

    qemu: complete bochs dispi interface vga driver.
    
    Ditch unused fb*.h files.
    Rename init.c (name is _way_ to generic) to bochs.c.
    Add proper bochs dispi interface detection and mode setup.
    Hook up coreboot framebuffer table initialization.
    
    Change-Id: I7154b1593902e7d42606b64819217872eee10683
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3500
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0ea3664bc30f81fbeb9d2ce9b7ca1e83e788aa23
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Tue Jun 18 23:52:26 2013 +0200

    edid: fix warning
    
    src/lib/edid.c:1177: error: ‘y’ may be used uninitialized in this function
    
    Warning is bogus, but seems my gcc (4.4.7 as shipped by RHEL-6)
    isn't clever enougth to figure this on its own.  So help a bit
    by explicitly initializing the variable.
    
    Change-Id: Ia9f966c9c0a6bd92a9f41f1a4a3c8e49f258be37
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3501
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 354066e1179e2c3ca14c5b1216d3a565fb6da813
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Jun 17 17:42:35 2013 +0200

    libpayload: ahci: Increase timeout for signature reading
    
    We can't read the drives signature before it's ready, i.e. spun up.
    So set the timeout to the standard 30s. Also put a notice on the
    console, so the user knows why the signature reading failed.
    
    Change-Id: I2148258f9b0eb950b71544dafd95776ae70afac8
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3493
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cacc58a874092bbbd680cd636ed840c1844c84a1
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue May 14 15:25:26 2013 +0200

    winbond/w83627dhg: Correct resource setting for SPI (LDN6)
    
    The SPI logical device on the W83627DHG uses the second i/o port
    register pair but not the first one. So we have to also set `io1`
    (the second io_info struct) and not `io0` in the pnp_info structure.
    
    Setting the PNP_IO1 flag without a mask in `io1` caused coreboot to
    hang in pnp_enable_devices() until commit aeead274 which added a
    check for an unset mask.
    
    Change-Id: I027d279b4641fecd88afb14d40fbe1c0bfbf81bb
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3391
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit df8d27357f7a23a2f840b3d2af7b67229c16e42b
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Tue Jun 18 11:09:29 2013 +0200

    qemu/q35: uncomment cache-as-ram Kconfig entries
    
    Change-Id: I8371764e3f2d16a3a776beb1c064f461b20a4262
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3496
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5acc76cd3e097e86768c2addc0963ea521f19a49
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Jun 17 01:17:55 2013 -0700

    am335x: Add pinmux support based on the functions in U-Boot
    
    I was unable to find documentation that said what mode numbers correspond
    to what functionality, so I translated over what U-Boot does.
    
    Change-Id: I34fab0f024fa2322d6bb66106aed75224e67354d
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3489
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 56892fc475d61a5e6bfb912098dca8975ecf9b94
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jun 16 17:12:37 2013 +0300

    AMD southbridges: Move HAVE_HARD_RESET
    
    All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c
    file already placed under southbridge/.
    
    All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally
    identical reset.c file under mainboard/. Move those files under
    respective southbridge/.
    
    Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3486
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit d715105d30c2b37a63d783eda45166505b483e7d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jun 17 01:09:07 2013 +0300

    AMD: Use same sourcecode for reset in romstage as ramstage
    
    Confusingly, romstage compiled in different copy of soft_reset()
    than ramstage. Use source in reset.c for both.
    
    Change-Id: I2e4b6d1b89c859c7cf5d9e9c8f7748b43d369775
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3487
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 397ca6176c70f5d8c1db7cdcb0b3dedaa74c3cbd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jun 16 17:30:29 2013 +0300

    AMD boards: Clean use of Kconfig options
    
    The chip component is unconditionally selected for the mainboard
    so these uses are superfluous.
    
    Change-Id: I84b053ab47f7b1f68e88d968cf305e24bc95f4da
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3485
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 0fd6a65243e184e4cdef6c04e20f5d4aeab514aa
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Jun 13 17:30:48 2013 -0600

    Add support for XHCI (USB 3.0)
    
    CONFIG_HUDSON_XHCI_ENABLE will control the XHCI flags in the
    amd/parmer and asus/f2a85-m mainboards.  The XHCI ports on
    amd/thatcher are not wired to USB jacks so always disable the flags.
    This was tested on amd/parmer using a USB 3.0 thumbdrive.
    
    Change-Id: I596b040fec30882d8d4dee34ab9f866dc1f8896b
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3465
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1fa1904e53cd009b1031948f34caa38ae9bcf23f
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Fri Jun 14 07:11:40 2013 -0600

    AMD Hudson: Add config option to enable XHCI
    
    To have USB 3.0 support the XHCI controller needs to be enabled
    and the xhci.bin firmware needs to be added to CBFS.
    
    Change-Id: I0b641b30b67163b7dc73ee7ae67efe678e11c000
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3464
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0b2ee9391079a5092eb99dce764e3836eeb92cd9
Author: Nico Huber <nico.h@gmx.de>
Date:   Sat Jun 15 19:58:35 2013 +0200

    pnp: Remove now plain wrappers for default PnP functions
    
    After removing the enter()/exit() functions for configuration mode,
    most wrappers for our standard PnP functions just call the underlying
    default implementation.
    
    Remove those with a little cocci:
        @ op_match @
        identifier op;
        identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
        type device_t;
        identifier dev;
        @@
         static void op(device_t dev) { pnp_op(dev); }
    
        @@
        identifier op_match.op;
        @@
        -op(...) {...}
    
        /* Three rules to match the alignment, hmmp... */
        @@
        identifier op_match.op, op_match.pnp_op;
        identifier ops;
        @@
         struct device_operations ops = {
        -        .set_resources    = op,
        +        .set_resources    = pnp_op,
         };
    
        @@
        identifier op_match.op, op_match.pnp_op;
        identifier ops;
        @@
         struct device_operations ops = {
        -        .enable_resources = op,
        +        .enable_resources = pnp_op,
         };
    
        @@
        identifier op_match.op, op_match.pnp_op;
        identifier ops;
        @@
         struct device_operations ops = {
        -        .enable           = op,
        +        .enable           = pnp_op,
         };
    
    Change-Id: Idc0e52c7e3600a01f3b6a4e17763557b271b481e
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3483
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 13dc976a5288899756ec6e5d53b51b1ddf64b389
Author: Nico Huber <nico.h@gmx.de>
Date:   Sat Jun 15 19:33:15 2013 +0200

    pnp: Register implementations of enter/exit config state
    
    Find all the (ramstage) implementations of enter()/exit() functions
    for the configuration state, register and call them through the new
    struct pnp_mode_ops. As our standard PnP functions are aware of the
    pnp_mode_ops, it's not necessary to call enter()/exit() around them
    anymore.
    
    Patch generated with the cocci below. It's not perfect. The movement
    of the enter()/exit() calls is somehow fragile. So I checked the
    remaining calls for sense, and changed some empty lines. Also a
    duplicate insertion of pnp_conf_mode_ops had to be removed.
        /* Try to find enter and exit functions by their outb() structure and
           their usage around calls to our standard pnp functions: */
        @ enter_match @
        identifier enter;
        identifier dev;
        type device_t;
        @@
         void enter(device_t dev)
         {
                 <...
                 outb(..., dev->path.pnp.port);
                 ...>
         }
    
        @ exit_match @
        identifier exit;
        identifier dev;
        type device_t;
        @@
         void exit(device_t dev)
         {
                 <...
                 outb(..., dev->path.pnp.port);
                 ...>
         }
    
        @ pnp_match @
        identifier op;
        identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
        identifier enter_match.enter, exit_match.exit;
        type device_t;
        identifier dev;
        @@
         void op(device_t dev)
         {
                 ...
                 enter(dev);
                 ...
                 pnp_op(dev);
                 ...
                 exit(dev);
                 ...
         }
    
        /* Now add enter/exit to a pnp_mode_ops structure: */
        @ depends on pnp_match @
        identifier enter_match.enter;
        identifier exit_match.exit;
        identifier ops;
        @@
        +static const struct pnp_mode_ops pnp_conf_mode_ops = {
        +        .enter_conf_mode  = enter,
        +        .exit_conf_mode   = exit,
        +};
        +
         struct device_operations ops = {
                 ...,
        +        .ops_pnp_mode     = &pnp_conf_mode_ops,
         };
    
        /* Match against the new structure as we change the code and the above
           matches might not work anymore: */
        @ mode_match @
        identifier enter, exit, ops;
        @@
         struct pnp_mode_ops ops = {
                 .enter_conf_mode  = enter,
                 .exit_conf_mode   = exit,
         };
    
        /* Replace enter()/enter() calls with new standard calls (e.g.
           pnp_enter_conf_mode()): */
        @@
        identifier mode_match.enter;
        expression e;
        @@
        -enter(e)
        +pnp_enter_conf_mode(e)
    
        @@
        identifier mode_match.exit;
        expression e;
        @@
        -exit(e)
        +pnp_exit_conf_mode(e)
    
        /* If there are calls to standard PnP functions, (re)move the
           enter()/exit() calls around them: */
        @@
        identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
        expression e;
        @@
        -pnp_enter_conf_mode(e);
         pnp_op(e);
        +pnp_enter_conf_mode(e);
         ...
         pnp_exit_conf_mode(e);
    
        @@
        identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
        expression e;
        @@
         pnp_enter_conf_mode(e);
         ...
        +pnp_exit_conf_mode(e);
         pnp_op(e);
        -pnp_exit_conf_mode(e);
    
        @@
        expression e;
        @@
        -pnp_enter_conf_mode(e);
        -pnp_exit_conf_mode(e);
    
    Change-Id: I5c04b0c6a8f01a30bc25fe195797c02e75b6c276
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3482
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dd4715b6a5beca80ce9655f8711327a83d05b416
Author: Nico Huber <nico.h@gmx.de>
Date:   Mon Jun 10 22:08:35 2013 +0200

    pnp: Implement common handling for PnP config modes
    
    Many super i/o chips only answer to PnP requests if they are in a
    configuration state (sometimes also called ext func mode). To cope with
    that, the code of many chips implements its own version of our default
    PnP functions like pnp_set_resource(), pnp_enable_resource() etc.
    
    To avoid this code duplication, this patch extends our PnP device
    interface with optional functions to enter and exit configuration mode.
    
    Change-Id: I9b7662a0db70ede93276764fa15020f251eb46bd
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3481
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f898f7ba4d10146b45241afe65fd54b3c049cc4f
Author: Nico Huber <nico.h@gmx.de>
Date:   Mon Jun 10 22:57:12 2013 +0200

    pnp: Provide alternative pnp_enable() implementation
    
    The current default implementation of pnp_enable() only disables devices
    - if set so in the devicetree - but does not enable them. Enablement takes
    place in pnp_enable_resources(). Yet, many PnP chips implement their own
    version of pnp_enable() which also enables devices if set in the devicetree.
    
    It's arguable, if enabling those devices makes sense, before they get
    resources assigned. Maybe we can't write the resource registers if not,
    who knows? The least we can do is providing a common implementation for
    this behavior, and get rid of some code duplication.
    
    Used the following cocci:
        @@
        expression e;
        @@
        +pnp_alt_enable(e);
        -pnp_set_logical_device(e);
        (
        -pnp_set_enable(e, !!e->enabled);
        |
        -(e->enabled) ? pnp_set_enable(e, 1) : pnp_set_enable(e, 0);
        |
        -if (e->enabled) { pnp_set_enable(e, 1); }
        -else { pnp_set_enable(e, 0); }
        )
    
    Change-Id: I8d695e8fcd3cf8b847b1aa99326b51a554700bc4
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3480
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a00f9830fb58d3f5061aab71be8553f3ff2e1f70
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Jun 17 17:47:24 2013 +0200

    libpayload: ahci: Fix command engine shutdown
    
    A timeout while waiting for a device' signature has shown that our
    error path wasn't correct. The shutdown of the ports command engine
    always timed out. Fix that by waiting for FR (FIS Receive Running)
    to be cleared independently from CR (Command List Running) and after
    clearing FRE (FIS Receive Enable).
    
    Change-Id: I50edf426ef0241424456f1489a7fc86a2cfc5753
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3494
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3cc151ede0677776f891c959568b92a79b9ecd9a
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jun 13 15:07:02 2013 +0200

    Make intel blob locations configurable
    
    They were hard-coded to be copied from 3rdparty/ which isn't always
    the right choice.
    
    Since the defaults stay the same, this should be compatible.
    
    Change-Id: If2173bef86ad1fcf2335e13472ea8ca41eb41f3d
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3453
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 9cb0941cb2f4ceb77b470c4de617ca915896d9f3
Author: Nico Huber <nico.h@gmx.de>
Date:   Sat Jun 15 15:30:19 2013 +0200

    pnp: Unify some alignment to ease autogenerating patches
    
    Most PnP drivers align the initialization of their `device_operations`
    with spaces. Unify this, so next autogenerated patches always match the
    alignment.
    
    Change-Id: I3f6baef6c8bb294c136354754125ea88c07a61a1
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3479
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7fd1beeaf7a295d298b26880593840033290c329
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Mon Jun 17 10:03:17 2013 +0200

    qemu: i440fx whitespace fixup
    
    Change-Id: I0d499027ffb175638cba0a9830d6ec2041a139db
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3488
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ee941b38d666f11ce5256cbccecea75f38ca86c1
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Fri Jun 7 16:03:44 2013 +0200

    qemu: add q35 support
    
    Add support for the new q35 chipset emulation
    added in qemu 1.4.
    
    Change-Id: Iabfaa1310dc7b54c9d224635addebdfafe1fbfaf
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3430
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9839a385bb778a87fc00a046a77334709ac78930
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Mon Jun 17 12:26:17 2013 +0200

    qemu: add support for memory above 4G
    
    Change-Id: Ic83f55d01b29b43028e3b363749d64b927db5489
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3492
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 44b11f2fe423a04641ca1059d2ba5a188412cdc7
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Mon Jun 17 13:30:50 2013 +0200

    qemu: move ram ressource reservation from "set" to "read" stage
    
    So the pci allocation code knows where memory is and doesn't
    try map pci devices there.  We also don't have to check for
    overlaps between pci hole and memory then.
    
    Change-Id: I5eaea0e4d21210719685860fa1f16ca7b2137cde
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3491
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 156ff1304905845736834d33b6a2d04ef5773ec5
Author: Christopher Kilgour <techie@whiterocker.com>
Date:   Sat Jun 15 23:52:36 2013 -0700

    cpu/amd/geode_lx/cache_as_ram.inc: Use $ for constant value instead of memory reference
    
    An uninitialized RAM value was used to select an MSR because a $ was forgotten
    in front of `CPU_DM_CONFIG0`. It should be the constant value 0x1800, corresponding
    to CPU_DM_CONFIG0 MSR defined in `src/include/cpu/amd/lxdef.h`.
    
    Change-Id: Id53ca98b06cc4a9b55916fd8db23904f98008d45
    Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
    Reviewed-on: http://review.coreboot.org/3478
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

commit 04372975bd2d5c1ac94c6358a32cfdcafccc26e3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 14 17:48:20 2013 +0300

    AMD sb800 agesa/hudson: Use PCI defines
    
    The original lines had contradicting comment and code.
    This change follows the code and sets MASTER bit too.
    
    Change-Id: Id2886bfc107612530f0e9747e5d49a9740fb8532
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3466
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 00cc7f4355ca1bdd621d4618f24f3336b29463cb
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Fri Jun 7 15:46:23 2013 +0200

    qemu: move i440fx bits
    
    Prepare tree for adding q35 support:
    Move emulation/qemu-x86 to emulation/qemu-i440fx.
    Rename some stuff to include 'i440fx'.
    
    Change-Id: Ib8c58175c5734cfcda1b22404ef52c09d38f0462
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3429
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e49679d5a1e6a6225980a9ae8455fef47e56ab12
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jun 8 15:48:14 2013 +0300

    usbdebug: Drop temporary disables of log output
    
    With this patch, output on usbdebug also includes the section of
    MTRR setups for every CPU. This makes usbdebug output almost identical
    with that of serial port and CBMEM console.
    
    Tested with model_206ax. Also tested previously on model_f2x which does
    not have these disable/enable calls in model_f2x_init() without detected issues.
    
    Change-Id: Idfd0e93439907b17255633658195d698feab3895
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3423
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit f55a54257a28d4d0444baa03b5699f73fc6cd05e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jun 14 11:16:25 2013 +0300

    lynxpoint: Fix PCI IDs for EHCI
    
    IDs were leftovers from bd82x6x.
    
    Change-Id: I4ab6062929d346d7f000ce8c0b8c97490bb2b154
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3463
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit ea90963666af1ba49d524c46c9d3257f9438e6c4
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Fri May 31 08:15:57 2013 -0600

    AMD Hudson: Add support for the SD controller
    
    This patch provides the correct SD controller timings for
    the Family16 device. It also will remove the SD controller
    from PCI space when device 0:14.7 is set to off in devicetree.
    This was tested on a AMD Parmer board and a AMD G-series SOC
    reference board. The settings were found in the AMD
    Hudson2 RRG and family16 BKGD.
    
    Change-Id: I6d7e7997ddc39802ab75dc8a211ed29f028c0471
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3348
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9029265cf5d835f2b87fe7e25124706b59df9394
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jun 13 14:37:15 2013 +0200

    libpayload: Fill gaps in the xHCI driver
    
    Well, it turned out to be more as some gaps ;)
    but we finally have xHCI running. It's well tested against a QM77 Ivy
    Bridge board.
    
    We have no SuperSpeed support (yet). On Ivy Bridge, SuperSpeed is not
    advertised and USB 3 devices will just work at HighSpeed.
    
    There are still some bit fields in xhci_private.h, so this might need
    little more work to run on ARM.
    
    Change-Id: I7a2cb3f226d24573659142565db38b13acdc218c
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3452
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5736fab4beb17ea1a04088d1cf16121c57ccf744
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed May 29 15:10:46 2013 +0200

    libpayload: Port usb hub driver to use the generic code
    
    This is mostly a rewrite, don't even try to read a diff.
    
    Tested with an internal rate matching hub on a QM77 board and three hubs
    integrated into DELL monitors.
    
    Change-Id: Ib12fa2aa90af4e0f37143d2ed92c4a1705b6d774
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3451
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0b78de2ee90771c4b37278203e0f59bc3afca487
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed May 29 15:01:17 2013 +0200

    libpayload: Add a generic driver for usb hubs
    
    The current drivers for external usb hubs and root hubs all follow
    the same pattern. Before adding another one with 90% of the same code,
    extract the common parts and rewrite them with a simple interface.
    
    This also adds debouncing of new attachments. Current drivers just
    waited 100ms before they reset the device. However, we should check
    if the device becomes disconnected and reconnected during this period.
    
    Porting of the current hub drivers will take place in separate
    commits (when I have time to test the older HCIs).
    
    Change-Id: I0c0ce0ac1b1cc51fb4cd009b3f9fcd1b9d2ba8fe
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3450
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit aee44fa37d780cfec95c444f43defd89ded021f0
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jun 6 10:20:35 2013 +0200

    libpayload: usb: Add interval attribute to endpoints
    
    Read bInterval from endpoint descriptors and store it in our endpoint_t
    struct. The interval is encoded dependently on the device' speed and the
    endpoint's type. Therefore, it will be normalized to the binary logarithm
    of the number of microframes, i.e.
      t = 125us * 2^interval
    
    The interval attribute will be used in the xHCI driver.
    
    Change-Id: I65a8eda6145faf34666800789f0292e640a8141b
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3449
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 482af6d15ca8eed28b51edc11692815419326d65
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri May 24 15:48:56 2013 +0200

    libpayload: Redirect USB slave init through controller driver
    
    xHCI requires special treatment of set_address since it determines
    the device number itself (instead of the driver, as with the other
    controllers). The controller also wants to validate a chosen device
    configuration and we need to setup additional structures for the
    device and the endpoints.
    
    Therefore, we add three functions to the hci_t structure, namely:
      set_address()
      finish_device_config()
      destroy_device()
    Current implementation for the Set Address request moved into
    generic_set_address() which is set_address() for the UHCI, OCHI and
    EHCI drivers. The latter two are only provided as hooks for the xHCI
    driver.
    
    The Set Configuration request is moved after endpoint enumeration.
    For all other controller drivers nothing changes, as there is no other
    device communication between the lines where the set_configuration()
    call moved.
    
    Change-Id: I6127627b9367ef573aa1a1525782bc1304ea350d
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3447
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4fc7b6c994aabce12bf263d49d1bedddfd847db9
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Jun 4 10:03:45 2013 +0200

    libpayload: Add enum for USB speeds
    
    These values are already used in this usb stack.
    
    Change-Id: If96f1dc2b67fbc13dfc4ae2d84e8f9945aa03163
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3448
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 735f55c29c05055059922b99513043887d7a8e89
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Jun 10 13:43:29 2013 +0200

    libpayload: usb: Skip non-endpoint descriptors during init
    
    During device initialization, skip any non-endpoint descriptor before
    reading the endpoint descriptors. By now, only HID descriptors were
    skipped.
    
    Change-Id: I190f3ae44b864aa71d5f32c3738097cf8f33a61b
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3446
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 088f5694009f710dc0a7fc9437a02d05b08829ed
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Tue May 28 11:30:25 2013 +0200

    util/inteltool: Add support for other 5 chipsets
    
    e4e8e090fa36cb3a098e1ddf0ea44c796c140572 does add support for QM57,
    but there are many more that should work with that code(?).
    
    Does not explode on...
    CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
    Northbridge: 8086:0044 (1st generation (Westmere family) Core Processor)
    Southbridge: 8086:3b0f (QS57)
    
    Change-Id: I85e15ba45678a5bd635415a7a8d69c05bff8f7ef
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3321
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 6c4f3ce4906c32e365825a7d8630945f79b60616
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Fri Jun 7 14:31:19 2013 +0800

    AMD S3 resume: use a function to replace duplicated code
    
    In function OemAgesaSaveMtrr of 'src/cpu/amd/agesa/s3_resume.c',
    there are many code like this:
      msr_data = rdmsr(0x258);
      flash->write(flash, nvram_pos, 4, &msr_data.lo);
      nvram_pos += 4;
      flash->write(flash, nvram_pos, 4, &msr_data.hi);
      nvram_pos += 4;
    Add a function write_mtrr to do this.
    
    Change-Id: Id6464e637db1758b07ac2d79d3be1375a8d49651
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3410
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d2ae6ae7898b00425ace91ebb835299c18a5ad50
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Wed Jun 5 14:32:51 2013 +0800

    AMD Thatcher: fix issue 'S3 fails to suspend after wake up from USB keyboard'
    
    This issue can be reproduced in Linux by the following steps:
    1) use pm-suspend to suspend.
    2) use USB keyboard to wake up.
    3) use pm-suspend to suspend. FAIL To SUSPEND.
    
    The cause of this issue is:
    USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event,
    but this bit is not clear after wake up. So OS thinks there is a
    wake up signal and wake up immediately.
    
    In this patch, I add AcpiGpe0Blk using MMIO access and write 1
    on bit 11. Write 1 to clear as spec says.
    I have tested on Thatcher
    
    The same change was done for AMD Parmer in commit »AMD Parmer:
    fix issue 'S3 fails to suspend after wake up from USB keyboard'
    (03901124) [1].
    
    [1] http://review.coreboot.org/#/c/3347/
        (Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1)
    
    Change-Id: Iaef39237497ef896d0f186e8f5522222c0ce6cb7
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3374
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 59d0d159f4710779043e34618a20dccff2af51dd
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jun 11 16:30:48 2013 +0300

    AMD: Kconfig cleanup
    
    Change-Id: I21182eae1d389790c330f27e6a830d91c3ee4eb6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3433
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 22dcdd914cf36ce657f5e72c975a96d577400a69
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Thu Jun 6 22:10:45 2013 +0200

    Add support for Intel Nehalem CPU
    
    Change-Id: I7ecc394b1e5bc0b8b85a8afac22efc0befe2d36a
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3395
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3a09179f462ad3f6111c7b8ebbad7d78534f9234
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Jun 13 00:13:50 2013 +0200

    Revert "Add support for Intel Ibex Peak (Mobile 5) southbridge"
    
    This reverts commit 0210119b4b95e84f954cfd6dc11aafbc187421af
    
    Change-Id: I5be3f2a54394c592650a0dcd671e4a72ae796cb2
    Reviewed-on: http://review.coreboot.org/3443
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0210119b4b95e84f954cfd6dc11aafbc187421af
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jun 7 00:17:25 2013 +0200

    Add support for Intel Ibex Peak (Mobile 5) southbridge
    
    Change-Id: If56f2cacc5f1b2ef9c7b6aea508d458a43dd1309
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3397
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 26419285bf6643776d5ad6534db7d0422758efb2
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Jun 7 01:34:06 2013 +0200

    Avoid tripping overheat alarm on X201 before ME boots
    
    Until ME boots (which takes seconds on X201) the reported temperature
    is 128 °C which triggers Linux overheat alarm which shuts down.
    Pretend temperature is 40°C until ME boots.
    
    Change-Id: Ia49fa03c6eb27f539a23711f2c8ebfde72b1dc18
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/3404
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fe50d0bcfe96210413d9c2372d3daa779892b520
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Jun 7 01:55:57 2013 +0200

    Make acpi/ec.c usable in romstage
    
    On X201 to enable EHCI debug you need to go through EC if USB power is
    disabled so we need to inclue ec.c.
    
    Change-Id: I8f8b7de639ecaebceaa53cd338136befaeec8214
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/3405
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7d1ebbff5ad224591a2d1972737611f96a13145c
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Wed Jun 5 22:43:44 2013 +0200

    Radio and dock support in EC on X60 and X201
    
    Enable UMTS on Lenovo X60 and X201.
    Enable radios if no options are available.
    Enable dock on Lenovo X201.
    
    Based on my X201 branch.
    
    Change-Id: I6e8d3bbd6a6b1a8e59473dd5cc8125a1583d75df
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/3377
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 942e69dea150fa0318feed1dfab728e62f9ee893
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon May 27 10:32:57 2013 -0700

    am335x: Add struct `am335x_uart` for uart registers
    
    Add a struct for referencing UART registers. The layout is quite
    strange on this chip, as the entire register space can take on three
    different meanings depending on the line control settings (in the LCR
    register) And to make things more confusing, some offsets reference
    different registers depending on if a read or a write operation is
    used.
    
    Change-Id: Ie62af9c0e0edafd01b81686a0fe5c5c1d4fa06c4
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3319
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b7d7cfbb308688170b43f0990229ba29230c65f1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 6 10:39:48 2013 +0300

    usbdebug: Quirk for board aopen/dxplplusu
    
    This ancient board with Intel e7505 invalidates cache while it does HW
    scrubbing for ECC in romstage. This breaks usbdebug console and prevents
    system from booting.
    
    If both EARLY_CONSOLE and USBDEBUG are selected, skip ECC scrubbing under
    these rare conditions to boot system.
    
    Change-Id: I6cb43bf69af54119f4a582dcaf498dd941d4c62d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3385
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5272a5feb74075da2edf2056f3d737543d0890b1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 6 12:53:03 2013 +0300

    usbdebug: Drop printk within console_init()
    
    In case with EARLY_CONSOLE, this printk is called before any other
    console is configured to transmit data. This outputs garbage on
    CONSOLE_SERIAL as baudrate is not yet programmed.
    
    For case without EARLY_CONSOLE, the order in which different console
    drivers initialize is obscure. Might sometimes work properly.
    
    Change-Id: I3792161e0a6dc17e17262048cc9136044dd69dc5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3384
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 1b7fd08ca174e3a3d69feeb7c4105f93c5d4687a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 6 10:28:22 2013 +0300

    usbdebug: Improve solving EHCI debug port problems
    
    Add comment how one can debug the usbdebug hardware init.
    Do not send printk's to usbdebug console when one is debugging
    the usbdebug console initialisation itself.
    
    Change-Id: I21a285cb31cf64e853bc626f8b6a617bc5a8be19
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3382
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 8351243e4a99c7159ec3257db272b735efff218c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jun 5 07:19:31 2013 +0300

    Fix i82801a/b/c/d IOAPIC
    
    Setting IRQ delivery to FSB got lost in the rebase process
    for commit e6143531.
    
    I captured following error on dmesg and this patch fixes it for
    i82801dx.
    
    ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
    ..MP-BIOS bug: 8254 timer not connected to IO-APIC
    ...trying to set up timer (IRQ0) through the 8259A ...
    ..... (found apic 0 pin 2) ...
    ....... failed.
    ...trying to set up timer as Virtual Wire IRQ...
    ..... works.
    
    Change-Id: I0768976cc6b0deab213ad9bd4771e0f278de634c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3371
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 083d35551c5cce5c26e5bc19f400878727594869
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Fri Jun 7 16:37:56 2013 +0200

    Add spkmodem receiver
    
    This is spkmodem receiver counterpart.
    
    Change-Id: Id27d32608502029fb6fcc8154f508811bf5ca77b
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/3411
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 07c3fc089cc0bcc45b436d92580c279a4386d88c
Author: Konstantin Aladyshev <aladyshev@nicevt.ru>
Date:   Thu Mar 7 04:37:02 2013 +0400

    intel/*/smi.c: Output correct GPIO in ALT_GP_SMI_STS register dump
    
    Mapping is as follows: bit 15 corresponds to GPIO15 ... bit 0 corresponds to
    GPIO0.
    
    Change-Id: I661ce56d9373887270ba3c0518892fbbe6d9de7c
    Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/3436
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 550f726d4028c3f29758473da925c8e853272371
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Jun 10 10:49:31 2013 +0200

    intel/bd82x6x/Makefile.inc: Revert duplicate addition of `usb_debug.c`
    
    Currently in Intel BD82x6x southbridge’s `Makefile.inc` the
    file `usb_debug.c` is added twice to the build.
    
    This was introduced in
    
        commit 4063ede3fb571110c3e65c321049cc2687cc54fa
        Author: Ronald G. Minnich <rminnich@google.com>
        Date:   Mon Feb 4 20:31:51 2013 -0800
    
            bd82x6x: Fix compiling with USB debug port support
    
            Reviewed-on: http://review.coreboot.org/2784
    
    but was unneeded because it had been already added in
    the following commit.
    
        commit 4141993536039e0d45caeacb745a89d388f0724b
        Author: Sven Schnelle <svens@stackframe.org>
        Date:   Sat Jul 28 08:52:44 2012 +0200
    
            bd82x6x: Fix CONFIG_USBDEBUG
    
            Reviewed-on: http://review.coreboot.org/1376
    
    Therefore basically revert that hunk.
    
    There is no policy on how to order these additions, so leave
    it to a possible separate commit, unifying this.
    
    Kyösti Mälkki suspects that these additions were meant for
    the Intel Lynx Point [1].
    
    [1] http://review.coreboot.org/#/c/3424/
    
    Change-Id: Iaa8de6fcc0d6f3a0a92a28fcb603d7777aa8b24c
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3425
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 62f8083dfdf0c5e0046efe297b2bf88474928071
Author: Konstantin Aladyshev <aladyshev@nicevt.ru>
Date:   Thu Mar 7 04:04:27 2013 +0400

    Fix cycle error in intel southbridges to display GPI status
    
    Fix obvious mistake in cycle that displays GPI status
    I hope i found all duplicates of it.
    
    Change-Id: Ic21ff3ecab85953463e5c23daf808dd5edc82ff8
    Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/3435
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6e5c86ff7da757687772fc9b1fc3ee41a613684c
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Jun 10 20:49:15 2013 -0400

    am335x: Revert how the header load size is calculated to an earlier method.
    
    The current method will treat hex values as 0 and would calculate the wrong
    size. This change switches back to an earlier method which used shell syntax
    to add the offset and size.
    
    Change-Id: I9fb2d9b323f113cc56a5ad2e38b47d2d22084f08
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3432
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 73b7632ad4e03cdd3d161ea928c10d79e11ebca9
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri May 24 13:48:26 2013 +0200

    winbond/w83627dhg: Add ACPI support
    
    This is loosely based on Christoph Grenz' ACPI code for the W83627HF
    and makes use of the PnP super i/o ACPI framework.
    
    Change-Id: I5e1cd09b83c0041f440562d2a1b73e4560589cb7
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3288
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ae7c96889f3fb6aec5909bec7c7d77377ab59cc9
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu May 23 18:13:23 2013 +0200

    Start ACPI framework for PnP (super i/o) devices
    
    I'm trying to make writing ACPI code for super i/o devices more
    comfortable.
    
    pnp.asl hosts some general cpp macros.
    
    The other four files are to be included in dsdt trees. They are
    controlled by cpp macros which should be defined/undefined before
    inclusion.
    
    Work was inspired by Christoph Grenz' ACPI code for the W83627HF.
    
    Change-Id: Idb55332ba9bc788c98964d30a450e0d734cf28ec
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3286
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1ef5ff277085512a2d24bef0b5f6f185a952b3b7
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Jun 10 02:07:17 2013 -0400

    am335x: Make the iROM load only the bootblock and ROM stage.
    
    The bootblock and ROM stages are the only ones that are really required to be
    loaded in the quite limited on chip RAM during startup. Rather than load the
    whole image which requires everything to be small, load just the bootblock and
    the ROM stage, allowing the rest of the image to be arbitrarily large. Loading
    a minimal amount of stuff should also improve boot performance a little bit.
    
    Change-Id: I2fede63b8d3d8f0d880e4a692ae423021f8232b6
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3421
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 437a1e67a3e4c530292d947ef5e1adbf3cc7650a
Author: Gabe Black <gabeblack@chromium.org>
Date:   Sun Jun 9 23:21:43 2013 -0700

    beaglebone: Expand "ROM" size to 4MB.
    
    Now that the ROM size is decoupled from the size of the on chip RAM,
    it's size is now only constrained by the size of the medium it's loaded
    from and the memory it's being loaded into, probably GBs in both cases.
    Making it 4MB is a reasonable compromise between giving the payload lots
    of breathing room and wasting space on the source medium which won't be
    used.
    
    Change-Id: I80932e0d4ce2dad02c3879345382e7d6ba44503a
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3422
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7cb57a1c30448e60ca06a36c59528e926b68f04d
Author: Gabe Black <gabeblack@chromium.org>
Date:   Wed May 29 16:42:31 2013 +0200

    beaglebone: Force on every other user LED to show that coreboot is running.
    
    Until we get serial working, this is a good way to show that coreboot is
    running. It can be removed once we have better methods.
    
    Change-Id: I62d25e52aa88a97aba4c959538d680b67a0bbbb2
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3329
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 560433b4931f30ab23f602911e3e2491a1cbfae1
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Jun 10 15:47:25 2013 -0500

    VX900: Use MIN/MAX from stdlib.h instead of redefining them
    
    Change-Id: I2dd693b300085493baa65bb652df8d6cce80b63b
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3431
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 37a8a8bd9e9d37da1e899297dbb43c0033cfd6c4
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue May 21 14:51:26 2013 -0500

    Add support for VIA EPIA-M850 board
    
    EPIA-M850 can now boot linux. For a list of issues, see:
    http://www.coreboot.org/VIA_EPIA-M850
    
    That's all folks.
    
    Change-Id: I7624944dbc05fbf3019897a116954d71dfda0031
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/1228
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 23211b0200eac11c64fe9dadadb5ec5ef1deabc6
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sun Jun 9 16:06:07 2013 -0500

    VIA VX900: Add minimal ramstage needed to boot linux
    
    This is the minimal code needed to get past ramstage, load SeaBIOS, jump
    to GRUB2, and boot linux (or load memtest). See individual source files for
    the status of each individual component.
    
    Change-Id: Ib7d5d7593c945f18af2c2fc5e0ae689ba66131a2
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3419
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7d31e7c13897e4b2548136c7a6f701b9121b7ad3
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Jun 8 11:49:10 2013 -0500

    VX900: Add DDR3 initialization
    
    The VX900 can be connected to either DDR2 or DDR3. On my board, it is
    DDR3, hence why there is no and will be no DDR2 code from my side.
    
    This is the raminit for DDR3 dimms for the VX900. I like the term
    "raminit" better than "memory training". This is a device, not a dog.
    
    What works and what doesn't is documented in the code. It does not
    make sense to hide that information in a commit message.
    
    Change-Id: Ib2ebc10e6d4d22d0a937fe9e895c17ce79153c88
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3417
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5239ba2f8fd07806053ff864302ba905fc5f015d
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Sat Jun 8 11:32:36 2013 -0500

    ramtest.c: Add silent ram_check
    
    In some cases, we want a ram_check that does not die and does not
    clobber the terminal with useless output that slows us down a lot.
    Usage examples include Checking if the RAM is up at the start of
    raminit, or checking if each rank is accessible as it is being
    initialized.
    
    As with all other ram_checks, this is more of a "Is my DRAM properly
    configured?" test, which is exactly what we want for something to use
    during memory initialization.
    
    Change-Id: I95d8d9a2ce1e29c74ef97b90aba0773f88ae832c
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3416
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 88a302346f35580f6ede166a9a0f3ee60343c482
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Jun 4 23:37:56 2013 -0500

    VX900: Add support for early romstage
    
    Add support for VX900 early initialization up until, but not including
    raminit. Add the basic infrastructure, add a romstrap table, and
    functionality to configure the CPU bus and SMBus.
    
    This code is necessary and sufficient to prepare us for raminit.
    
    Change-Id: Icc9c41e4927b589f17416836f87a6a5843b24aa7
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3372
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ee2bc27dc58611e83ec7670163fb8a69aa1adb03
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue May 21 12:35:08 2013 -0500

    early_smbus: Add early SMBus implementation for VIA chipsets
    
    Add a common implementation of SMBus functionality for early chipsets. Note
    however, that existing via chipsets are not ported to this code. Porting
    will require hardware testing to make sure everything is fine.
    
    This code is used in the VIA VX900 branch.
    
    Change-Id: If5ad8cd0942ac02d358a0139967e7d85d395660f
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/144
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ddbfc645c2fb9c2aab55c9d5f7c55fa80fd8da64
Author: Gabe Black <gabeblack@chromium.org>
Date:   Wed May 29 16:42:35 2013 +0200

    am335x: Build an omap style header and an image with it at the front.
    
    Loading on an OMAP SOC requires that the first sector of the image have a
    configuration header, and, when not an execute in place image, an additional
    header which describes how big the image is and where it should be loaded.
    This change adds some infrastructure to statically build that header using C
    code, and to paste the header onto the front of coreboot.rom in a new top
    level target file called MLO.
    
    The configuration header we're using is as inert as possible, in line with
    what U-Boot is doing. I think it could be used to give additional
    configuration parameters to the built-in ROM on the SOC, but we don't need to
    do that, and there didn't seem to be any actual documentation how to do that.
    Because the header is built from C and is defined per CPU, it would be
    possible to include extra settings in other CPUs if desired.
    
    Adding a new top level build target is a bit disruptive, but should be
    contained to the am335x directory and not interfere with other mainboards.
    
    Change-Id: I06d346a4050c20963b3c7c6e8a152070bf2d145a
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3332
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b7d81e05bb3e4058cbb28adcc5af0bdccfe88337
Author: Gabe Black <gabeblack@chromium.org>
Date:   Sun Jun 9 21:10:10 2013 -0700

    ARM: Put the ROM stage into the image before other bits.
    
    On ARM, there's frequently some firmware built into the SOC which runs
    first and which loads other firmware like Coreboot from some other
    media. To prevent the bootblock from having to know how to find and load
    the ROM stage from what may be a complicated source (sd card,
    netbooting, etc.), we can put the ROM stage immediately after the
    bootblock and ensure that they're both loaded at the same time.
    
    This change adjusts the Makefile.inc for ARM so that the ROM stage is put
    into the image before any other files so that we know it comes first.
    This changes the behavior of the CONFIG_UPDATE_IMAGE config option used
    by abuild, although it's not entirely clear whether that's still used.
    
    Change-Id: I832386243788156db5f5abbc9760a4e2026cf2cd
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3420
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 1990ab9f151ce3c2ccc2a4c84fd6cda5a5b0e2c1
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Thu May 23 13:26:37 2013 +0200

    OT200: bring LEDs into a defined state
    
    Keep in mind that we can _NOT_ read back the current state
    of the LEDS as some crazy FPGA designer wanted it that way.
    
    Change-Id: I5cd1ac598072318b3234d1ec35a79271655b46ac
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3271
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 641f00ce643fe661de494d3c29118f836664a02d
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Sat Jun 8 11:50:55 2013 +0800

    fam15 vendorcode: Change license to BSD from AMD software license
    
    fam15 vendorcode (src/vendorcode/amd/agesa/f15tn) was licensed under the
    AMD software license agreement. Change this license to 3-clause BSD.
    
    Change-Id: I7cab09bb58ef7cd24602628e2278672d577214a2
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3414
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d2e0dd5bc1002a45ef16b92203850df217233bec
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Jun 9 08:05:45 2013 +0200

    buildgcc: Re-add some break statements
    
    While some of the case .. break statement actually weren't needed,
    too are, since otherwise the option parsing loop hangs.
    
    Exit conditions for that endless loop: "--" or no more arguments,
    in line with GNU command line parsing rules.
    
    Change-Id: I0dbc35e530fb8c93a0f7de05ac47f325555ad4a4
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/3418
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>

commit ecbc0c5cb9c2dd403a2464ddc53ec937931d8cc6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 6 10:29:49 2013 +0300

    usbdebug: Fix use without EARLY_CONSOLE
    
    If EARLY_CONSOLE is not selected, the PCI function for EHCI
    host controller must be configured in ramstage instead.
    
    Change-Id: I20f7569f79484c744bc413450bfa139052f3580f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/3383
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4062f179a755ca3b303f444ee3ef812fb287f9f1
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Tue May 21 03:13:46 2013 +0200

    Lenovo X60: Add int15 handler
    
    Without that commit, with CONFIG_PCI_OPTION_ROM_RUN_YABEL,
      The VGA option rom doesn't init the right display:
      it initializes the external display, where we have
      a black scren(with backlight on).
    
    This commit is based on the code of mainboard.c in
      src/mainboard/roda/rk886ex.
    
    Change-Id: I8457aaf0503e0efdf0fcba9ff5e8a07ac04c5ca6
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3265
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7ed739445ba7ba6ffcf38d647426a44f905ac087
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sun May 26 23:56:43 2013 +0200

    i945: Add Display defines for int15h handler.
    
    Change-Id: I7bc99761c7047e64b4e29c307ad779cec49c17c8
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3306
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 8130b1ec1bc53a1dcd20910e8d73499ad7ada466
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Thu May 30 10:58:06 2013 +0200

    qemu: copy dsdt tables from SeaBIOS, adapt for coreboot and enable acpi
    
    First copy over from SeaBIOS git repo, then adapt for coreboot:
    
    Disable cpu/pci hotplug bits.  Disable dynamic pci window.
    Both depend on stuff in the SSDT tables created by SeaBIOS.
    
    Bits are left in, but deactivated via #if 0, so it's easier
    to see the differences when diffing the coreboot tables with
    the SeaBIOS tables.
    
    Adapt dsdt DefinitionBlock.
    
    Enable acpi table generation in acpi_tables.c.
    
    With this patch linux boots successfully with ACPI enabled.
    It's not bug-free though.  Missing cpu detection leads to
    funky messages like this one:
    
      weird, boot CPU (#0) not listed by the BIOS.
    
    and SMP most likely wouldn't work either.
    
    Change-Id: Ic3803a6f1ef6d54c11cc4ca3844d3032a374ae6b
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3342
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 7bb02512d9e3f1c2c95f83ef02a2209c5366ae58
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu May 23 16:35:05 2013 +0200

    ec/acpi: Add ACPI methods for generic EC access
    
    Port most of the functions found in ec/acpi/ec.c to ACPI Source Language
    (ASL). These functions are used to control embedded controllers with the
    standard ACPI interface (mostly through i/o ports 0x62 / 0x66).
    
    The following methods are implemented and tested against the power
    managements channels of a ITE IT8516E embedded controller:
     * WAIT_EC_SC           Wait for a bit in the EC_SC register
     * SEND_EC_COMMAND      Send one command byte to the EC_SC register
     * SEND_EC_DATA         Send one data byte to the EC_DATA register
     * RECV_EC_DATA         Read one byte of data from the EC_DATA register
     * EC_READ              Read one byte from ec memory (through cmd 0x80)
     * EC_WRITE             Write one byte to ec memory (through cmd 0x81)
    
    To use the provided methods, one should include `ec/acpi/ec.asl` in the
    EC device code. Prior doing so, two macros should be defined to identify
    the used i/o ports:
     * EC_SC_IO     I/o address of the EC_SC register
     * EC_DATA_IO   I/o address of the EC_DATA register
    
    Change-Id: I8c6706075fb4980329c228e5b830d5f4e9b188dd
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3285
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit ccc7d1f229ab4b0dc9b10f63966640bbac750722
Author: Olivier Langlois <olivier@olivierlanglois.net>
Date:   Mon Jun 3 01:30:25 2013 -0400

    Intel Atom cpu support to msrtool
    
    Added support for Intel Atom cpu to msrtool
    Fixed a cut&paste error in nehalem msr bits definition
    
    It has been tested with a N455 cpu and msrtool output can be review at:
    http://www.trillion01.com/coreboot/msrtool_atom.txt
    
    Change-Id: I0ecf455b559185e2d16fa1a655bf021efc2ef537
    Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net>
    Reviewed-on: http://review.coreboot.org/3351
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e1cddc1278d66f6ab776f60e6aecb8113a116a5b
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 4 14:22:25 2013 -0600

    AMD Trinity: Remove unnecessary lookup table copy
    
    The DDI connector table and the PCIe Port List lookup table are
    copied onto HEAP.  This copy is not needed since these are lookup
    tables used to define the platform configuration.
    
    Change-Id: If4760f80e08faa8da4fd11337a3812f89cf805f9
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3394
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 283ba7841581c5ffe64d1f0985cfa94be661b927
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Jun 4 14:16:24 2013 -0600

    AGESA: Add "const" modifier to function parameters
    
    Add CONST modifiers to read-only pass-by-reference function
    parameters in AGESA.  This allows the use of "const" modifiers
    on the declaration of lookup tables that are pass-by-reference.
    These will be used to identify tables that are copied onto the
    HEAP but don't need to be.
    
    Change-Id: Ie1187a427804fddf47b935a110ad23931a3447a9
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3393
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit aa588e027301063731b80e3e22a4ea3b1c0c08f1
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Fri May 31 09:26:55 2013 +0200

    qemu: wind up new cpu chip
    
    Add boot cpu to the device tree.  Figure the number of CPUs installed
    (using the qemu firmware config interface) and add cpu devices for them,
    so they show up in all generated BIOS tables correctly.  This gets SMP
    going.
    
    Change-Id: I0e99f98942d8ca90150b27fc13c1c7e926a1a644
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3345
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cbf30736b60c6076a82ff256b1bd5246a6af83c0
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Fri May 31 09:23:26 2013 +0200

    qemu: add x86 cpu
    
    This patch adds a qemu x86 cpu chip.  It has no initialization function
    as this isn't needed on virtual hardware.  A virtual machine can have
    pretty much any CPU: qemu emulates a wide range of x86 CPUs (try 'qemu
    -cpu ? for a list), also with 'qemu -cpu host' the guest will see a cpu
    which is (almost) identical to the one on the host machine.  So I've
    added X86_VENDOR_ANY as wildcard match for the cpu_table.
    
    Change-Id: Ib01210694b09702e41ed806f31d0033e840a863f
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3344
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a53266bee0bf2b4d92090d0194c694853318a370
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu May 2 15:26:08 2013 +0200

    ec/kontron/it8516e: Add it8516e EC driver
    
    This driver communicates with the IT8516e on the Kontron KTQM77.
    Since we don't know if the firmware and protocol are standard for
    the chip or customized to the board, call it kontron/it8516e.
    
    Change-Id: I7382172c6d865d60106c929124444821a07a5184
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3390
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ea6d6e8c1f1e5785d5c41029f3bb76e726aece6c
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue May 14 15:14:08 2013 +0200

    intel/bd82x6x: Add option to include ethernet firmware
    
    Change-Id: Idf804ed29a67bad732df19e6981f74c8d0c354b5
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3388
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4af2bb5724b7b50b1a7b139da7fe17289e0785c8
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu May 2 11:44:02 2013 +0200

    intel/bd82x6x: fix building usb debug on SNB/IVB
    
    Change-Id: Ica3afbf8277cb025251da7af181f8de0d0036b45
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3389
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5c4645b0ee798e52a6bf18ae1544dd86f8dafdaa
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Jun 5 20:01:42 2013 -0500

    (Trivial) early_smbus: fix printsmbus macro
    
    When I've first written this macro in 2011, the correct define for
    verbose SMBus message was CONFIG_DEBUG_SMBUS_SETUP. This has since
    been changed to CONFIG_DEBUG_SMBUS. I didn't catch that, and this made
    the printsmbus macro always evaluate to an empty statement.
    
    Use the proper CONFIG_DEBUG_SMBUS define. This makes printsmbus
    functional again.
    
    Change-Id: Iaf03354b179cc4a061e0b65f5b746af10f5d2b88
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3379
    Tested-by: build bot (Jenkins)
    Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

commit 3979eda5716f162d18b9fde05aba68b1bb747c6b
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Fri May 31 13:39:24 2013 +0200

    qemu: add power management function to device tree
    
    Needed to make 'register "gpo" = ...' work.
    While being at it add comments saying which device is which.
    
    Change-Id: I911d5e4a7b6c7abf4ad73e863ab201e9e55ee0d4
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3346
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4321d60acba4e629f1ec4922c8b5e31148b332d8
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Thu May 30 13:23:38 2013 +0200

    console: log qemu debugcon detection result
    
    Change-Id: Ie0507475f33d029d6e8ce59f138e0e7da5156d4f
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3339
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 22f01e611be6fbd3ee5a70b27b96478ff1f4e93a
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Thu May 30 10:33:38 2013 +0200

    console: add qemu debugcon detection
    
    The qemu debugcon port returns 0xe9 on reads in case the device is
    present.  Use that for detection and write console output to the
    port only in case the device is actually present.
    
    Change-Id: I41aabcf11845d24004e4f795dfd799822fd14646
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3338
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d7c6e444acfc3284c4a9ff49dd138cd0c37545e2
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Thu May 30 10:32:31 2013 +0200

    console: add qemu prefix to debugcon
    
    Change-Id: Ibcc0a94638c022a76cd3c2e3387af6e1ab757ccb
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3337
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2b9620343bdde1055585182aeccb77726f047c8f
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Thu May 30 15:41:48 2013 +0200

    qemu: Initial support for the qemu firmware config interface.
    
    qemu has a special device to pass configuration information
    from qemu to the firmware.  This patch adds initial support
    the interface, namely some infrastructure, detection code and
    a function to query the number of CPUs.
    
    Change-Id: I43ff5f4fbf12334a91422aa38f514a82a1d5219e
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3343
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 019f0fc2c7ced8a7c02d5334a7ea4342aae97f55
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Jun 5 08:34:20 2013 +0200

    Revert "Asus F2A85-M: Activate IOMMU support"
    
    This reverts commit eed28f97b375a9469a2872996c19eb102647052e.
    
    For whatever reason, the dependencies were lost in Gerrit and the
    commit [1] was submitted without its dependencies. As a result
    buidling the ASUS F2A85-M fails now [2] and therefore commits
    based on this commit fail to pass the buid tests by Jenkins.
    
        […]
        Created CBFS image (capacity = 8387656 bytes)
            LINK       cbfs/fallback/romstage_null.debug
            CC         cbfs/fallback/coreboot_ram.debug
        coreboot-builds/asus_f2a85-m/generated/coreboot_ram.o:(.data+0x16b9c): undefined reference to `GnbIommuScratchMemoryRangeInterface'
        collect2: error: ld returned 1 exit status
        make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/coreboot_ram.debug] Error 1
        make: *** Waiting for unfinished jobs....
        coreboot-builds/asus_f2a85-m/mainboard/asus/f2a85-m/buildOpts.romstage.o:(.data+0x3d8): undefined reference to `GnbIommuScratchMemoryRangeInterface'
        collect2: error: ld returned 1 exit status
        make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1
        […]
    
    Therefore revert the commit to get the tree working again and
    submit this patch with its dependencies again.
    
    [1] http://review.coreboot.org/#/c/3317/
    [2] http://qa.coreboot.org/job/coreboot-gerrit/6618/testReport/junit/(root)/board/i386_asus_f2a85_m/
    
    Change-Id: I911755884da09eb0a0651b8db07ee2a32e6eaaaa
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3373
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 082d2a0ab7a1feabaa4486c19bb981444e402a70
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Wed May 29 14:59:36 2013 +0200

    qemu: fix IRQ routing setup
    
    Do the setup for all PCI slots, not only the third.
    
    Also remove the bogus message, as slot 3 may carry
    any device, not only NICs.
    
    This makes IRQ setup simliar to SeaBIOS.
    
    SeaBIOS assignments (with patch for logging added,
    and a bunch of pci devices for testing purposes):
    
        PCI IRQ [piix]: bdf=00:01.3 pin=1 line=10
        PCI IRQ [piix]: bdf=00:03.0 pin=1 line=11
        PCI IRQ [piix]: bdf=00:04.0 pin=1 line=11
        PCI IRQ [piix]: bdf=00:05.0 pin=1 line=10
        PCI IRQ [piix]: bdf=00:06.0 pin=1 line=10
        PCI IRQ [piix]: bdf=00:1d.0 pin=1 line=10
        PCI IRQ [piix]: bdf=00:1d.1 pin=2 line=10
        PCI IRQ [piix]: bdf=00:1d.2 pin=3 line=11
        PCI IRQ [piix]: bdf=00:1d.7 pin=4 line=11
    
    Coreboot assignments without this patch:
    
        Assigning IRQ 11 to 0:3.0
    
    Coreboot assignments with this patch:
    
        Assigning IRQ 10 to 0:1.3
        Assigning IRQ 11 to 0:3.0
        Assigning IRQ 11 to 0:4.0
        Assigning IRQ 10 to 0:5.0
        Assigning IRQ 10 to 0:6.0
        Assigning IRQ 10 to 0:1d.0
        Assigning IRQ 10 to 0:1d.1
        Assigning IRQ 11 to 0:1d.2
        Assigning IRQ 11 to 0:1d.7
    
    Change-Id: Ie96be39185f2f1cbde3c9fc50e29faff59c28493
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3334
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fd39ddd63528514ddc62a03bee7bafc8bd98e6d7
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Tue Jun 4 04:48:11 2013 +0200

    Intel 945: Select LAPIC_MONOTONIC_TIMER for X86EMU_DEBUG_TIMINGS
    
    X86EMU_DEBUG_TIMING is needed for producing i915tool
      compatible output. So add its dependencies to the
      i945’s Kconfig in order to be able to use X86EMU_DEBUG_TIMINGS,
      which depends on HAVE_MONOTONIC_TIMER which
      LAPIC_MONOTONIC_TIMER provides/selects.
    
    Note that UDELAY_LAPIC is already selected by the Intel CPU.
    
    Change-Id: Ie834ebc92e527eb186a92b39341ebd0a08889fb0
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3356
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit eed28f97b375a9469a2872996c19eb102647052e
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon May 27 16:12:00 2013 +0200

    Asus F2A85-M: Activate IOMMU support
    
    Activate the IOMMU support for the Asus F2A85-M.
    
    Add the device to `devicetree.cb`.
    
        $ pci -s 0.2
        […]
        00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit
    
        $ dmesg
        […]
        [    0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02  AMD   AMDIOMMU 00000001 AMD  00000000)
        [    0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02    AMD     ALIB 00000001 MSFT 04000000)
        [    0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD    POWERNOW 00000001 AMD  00000001)
        [    0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE   COREBOOT 0000002A CORE 0000002A)
        […]
        [    0.465114] [Firmware Bug]: ACPI: no secondary bus range in _CRS
        […]
        [    0.567330] pci 0000:00:00.0: >[1022:1410] type 00 class 0x060000
        [    0.567364] pci 0000:00:00.2: >[1022:1419] type 00 class 0x080600
        [    0.567427] pci 0000:00:01.0: >[1002:9993] type 00 class 0x03000
        […]
        [    0.597731] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
        [    0.597899] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT]
        [    0.597933] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR0._PRT]
        [    0.597972] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR1._PRT]
        [    0.598073]  pci0000:00: >Requesting ACPI _OSC control (0x1d)
        [    0.603808]  pci0000:00: >ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d
        [    0.612397] ACPI _OSC control for PCIe not granted, disabling ASPM
        [    0.620508] Freeing initrd memory: 14876k freed
        […]
        [    0.882674] pci 0000:00:01.0: >Boot video device
        [    0.882876] PCI: CLS 64 bytes, default 64
        [    0.897088] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 extended features:  PreF PPR GT IA
        [    0.905816] pci 0000:00:00.2: >irq 40 for MSI/MSI-X
        [    0.917457] AMD-Vi: Lazy IO/TLB flushing enabled
        [    0.922076] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
        [    0.928500] software IO TLB [mem 0xbb13d000-0xbf13cfff] (64MB) mapped at [ffff8800bb13d000-ffff8800bf13cfff]
        [    0.938535] LVT offset 0 assigned for vector 0x400
        [    0.943338] perf: AMD IBS detected (0x000000ff)
        [    0.948037] audit: initializing netlink socket (disabled)
        [    0.953432] type=2000 audit(1369659616.800:1): initialized
        [    0.977011] HugeTLB registered 2 MB page size, pre-allocated 0 pages
        […]
        [    7.881938] radeon 0000:00:01.0: >VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF (512M used)
        [    7.881941] radeon 0000:00:01.0: >GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF
        […]
        [    7.885516] radeon 0000:00:01.0: >irq 48 for MSI/MSI-X
        [    7.885525] radeon 0000:00:01.0: >radeon: using MSI.
        […]
        [    8.276775] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae000 flags=0x0010]
        [    8.287363] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc00 flags=0x0010]
        [    8.297945] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae200 flags=0x0010]
        [    8.308527] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae080 flags=0x0010]
        [    8.319109] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae240 flags=0x0010]
        [    8.329694] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001accc0 flags=0x0010]
        [    8.340276] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace80 flags=0x0010]
        [    8.350858] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd80 flags=0x0010]
        [    8.361441] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae280 flags=0x0010]
        [    8.372022] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae180 flags=0x0010]
        [    8.382605] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace00 flags=0x0010]
        [    8.393188] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acdc0 flags=0x0010]
        [    8.403770] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace40 flags=0x0010]
        [    8.414353] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae1c0 flags=0x0010]
        [    8.424936] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc40 flags=0x0010]
        [    8.435518] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc80 flags=0x0010]
        [    8.446100] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae2c0 flags=0x0010]
        [    8.456684] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae300 flags=0x0010]
        [    8.467265] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae340 flags=0x0010]
        [    8.477849] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae380 flags=0x0010]
        [    8.488431] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae3c0 flags=0x0010]
        [    8.499013] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae0c0 flags=0x0010]
        [    8.509596] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acec0 flags=0x0010]
        [    8.520179] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd00 flags=0x0010]
        [    8.530761] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad000 flags=0x0010]
        [    8.541343] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae400 flags=0x0010]
        [    8.551925] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae440 flags=0x0010]
        [    8.562509] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf00 flags=0x0010]
        [    8.573090] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae480 flags=0x0010]
        [    8.583675] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae100 flags=0x0010]
        [    8.594257] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae4c0 flags=0x0010]
        […]
        [    8.604840] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf40 flags=0x0010]
        [    8.615421] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd40 flags=0x0010]
        [    8.626004] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad140 flags=0x0010]
        [    8.636587] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad040 flags=0x0010]
        [    8.647169] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad080 flags=0x0010]
        [    8.657751] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae500 flags=0x0010]
        [    8.668335] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad100 flags=0x0010]
        [    8.678917] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad0c0 flags=0x0010]
        [    8.689499] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf80 flags=0x0010]
        [    8.700080] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acfc0 flags=0x0010]
        [    8.710664] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae140 flags=0x0010]
        [    8.721246] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae040 flags=0x0010]
        [    8.731828] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad180 flags=0x0010]
        [    8.742412] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae540 flags=0x0010]
        [    8.752995] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad280 flags=0x0010]
        [    8.763577] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad340 flags=0x0010]
        [    8.774160] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad200 flags=0x0010]
        [    8.784741] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad300 flags=0x0010]
        [    8.795324] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae5c0 flags=0x0010]
        [    8.805906] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae640 flags=0x0010]
        [    8.816490] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad2c0 flags=0x0010]
        [    8.827072] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad1c0 flags=0x0010]
        [    8.837655] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad240 flags=0x0010]
        [    8.848238] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae580 flags=0x0010]
        [    8.858819] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae600 flags=0x0010]
        [    8.869402] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad3c0 flags=0x0010]
        [    8.879985] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad380 flags=0x0010]
        [    8.890568] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae7c0 flags=0x0010]
        [    8.901151] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae740 flags=0x0010]
        [    8.911732] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae6c0 flags=0x0010]
        [    8.922316] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae780 flags=0x0010]
        [    8.932897] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae700 flags=0x0010]
        [    8.943480] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae680 flags=0x0010]
        [    8.963011] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000).
        [    8.963165] radeon 0000:00:01.0: >WB enabled
        […]
    
    It is not known, what the implications of the `IO_PAGE_FAULT` are.
    
    Change-Id: Ic5fde609322a5fdeb1a48052c403847197752a4b
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/3317
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4cdc5d6fc6ea6f460414728e026660954d0adb1d
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Wed May 15 00:19:49 2013 +0200

    Yabel : Add tracing option needed by i915tool.
    
    This patch was made by listenning to what Ron Minnich told
      me to do on #coreboot IRC channel on Freenode with my
      adaptations on top.
    
    i915tool is at https://code.google.com/p/i915tool/ ,
      the one in coreboot is outdated.
    
    Change-Id: I13cd684f4c290114836fbd7babd461153e8d6124
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3277
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 67f556c2962eb56e87e5df0bec78671005822b77
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Aug 10 03:55:42 2012 -0500

    viatool: Add utility to read various configuration bits on VIA systems
    
    viatool is a utility for extracting useful for extracting certain configuration
    bits on VIA chipsets and CPUs. It is a fork of inteltool.
    
    viatool is currently focused on "quirks". Quirks are device configurations that
    cannot be accessed directly. They are implemented as hierarchical configurations
    in the PCI or memory address spaces (index/data register pairs). Such
    configurations refer to hardware parameters that are board specific. Those
    parameters would otherwise be difficult to extract from a system running the
    vendor's firmware.
    
    viatool also preserves inteltool's MSR dumps. VIA CPU and Intel CPU MSRs are
    nearly identical.
    
    Change-Id: Icbd39eaf7c7da5568732d77dbf2aed135f835754
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/1430
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a296ce75e304dcf163a770e3dc6ca580b7a61d29
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri May 31 19:36:52 2013 +0200

    Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture
    
    The MARK_GRAPHICS_MEM_WRCOMB was spreading like a cancer
    since it was defined in sandybridge. It is really
    more of an x86 thing however, and we now have
    three systems that can use it.
    
    I considered making this more general, since it technically
    can apply to PTE-based systems like ARM, and maybe we should.
    But the 'WRCOMB' moniker is usually closely tied to the x86.
    
    Change-Id: I3eb6eb2113843643348a5e18e78c53d113899ff8
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3349
    Tested-by: build bot (Jenkins)

commit 873965e2a7771e9f040b4bbb18bdb9a27ee2bb09
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Wed May 29 21:25:05 2013 +0200

    Lenovo X60: Add CMOS defaults.
    
    After removing power and the CMOS Battery, putting it back
      and booting coreboot we have:
         # ./nvramtool -a
         boot_option = Fallback
         last_boot = Fallback
         baud_rate = 115200
         debug_level = Spew
         hyper_threading = Enable
         nmi = Enable
         boot_devices = ''
         boot_default = 0x40
         cmos_defaults_loaded = Yes
         lpt = Enable
         volume = 0xff
         tft_brightness = 0xbf
         first_battery = Primary
         bluetooth = Enable
    
    The code for handling the invalid CMOS space in mainboard.c
      is now useless and so it was removed.
    
    Change-Id: Ic57a14eeeea861aa034cb0884795b0152757bf5b
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3335
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 649f18f834aaf13674e4c8e9a192b386165b39f1
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Thu May 9 16:14:59 2013 +0200

    Asus M4A785T-M: Add CMOS defaults.
    
    After removing power and the CMOS Battery, putting it back
      and booting coreboot we have:
        # ./nvramtool -a
        boot_option = Fallback
        last_boot = Fallback
        ECC_memory = Enable
        baud_rate = 115200
        hw_scrubber = Enable
        interleave_chip_selects = Enable
        max_mem_clock = 400Mhz
        multi_core = Enable
        power_on_after_fail = Disable
        debug_level = Spew
        boot_first = HDD
        boot_second = Fallback_Floppy
        boot_third = Fallback_Network
        boot_index = 0xf
        boot_countdown = 0xc
        slow_cpu = off
        nmi = Enable
        iommu = Enable
        nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide.
        nvramtool: Warning: Coreboot CMOS checksum is bad.
    
    Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3324
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 03c66202dee7691c7ef7978a1d1fe555f1717834
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Thu May 9 23:35:18 2013 +0200

    PC Engines ALIX.1C: Add CMOS defaults.
    
    After Booting the BIOS, flashing coreboot
      and booting coreboot with that patch we have:
        # ./nvramtool -a
        boot_option = Fallback
        last_boot = Fallback
        ECC_memory = Disable
        baud_rate = 115200
        power_on_after_fail = Disable
        debug_level = Spew
        boot_first = HDD
        boot_second = Fallback_Floppy
        boot_third = Fallback_Network
        boot_index = 0xf
        boot_countdown = 0x7f
        nvramtool: Warning: Coreboot CMOS checksum is bad.
    
    Change-Id: Ia87b09003d859f6dee7c09aa963df002c1d02688
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3323
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit fcf2a17a867fc5d97bb5d2a7a31e7dfd08b9a254
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue May 21 14:50:19 2013 -0500

    pci_ids.h: Add PCI IDs for VIA VX900 chipset
    
    Change-Id: I4a75326fef0a10a6290cdd4b1b93d9af8e3ab23d
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3268
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit e25984b8c80b2f937861ff01abf2d183d380037e
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Apr 25 15:00:15 2013 +0200

    superiotool: Add dump facility for HWM of W83627DHG-P
    
    Change-Id: I9355996a8cf1b7cb91cc415ec04f5108a1cc42a5
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3358
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 28a1324303af20271ef8233eac36702e70236328
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Apr 25 15:10:46 2013 +0200

    superiotool: Add dump facility for ITE IT8516 + I/O 0x20e/f
    
    Change-Id: Iaea08b7eb5aac9ff1e0756f1400a82641bb45b14
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3359
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5d1edf627665cb8792533d8360ed1a154fce70a0
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue May 21 12:26:47 2013 +0200

    libpayload: Whitelist Mobile Panther Point AHCI controller
    
    Add the Mobile Panther Point (PPT) AHCI controller (DEVID 0x1e03) to
    the list of tested controllers. Also comment the only other listed
    controller (Mobile ICH9).
    
    The PPT AHCI controller was tested with a QM77 chipset on a Kontron
    KTQM77 board.
    
    Change-Id: Ia396761411f4f9289af11ec8e1b144512b2fc126
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3361
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ce809b9c3aabdfbfd818c29f95074a0f7443001e
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue May 28 13:56:54 2013 +0200

    fix tinycurses
    
    Change-Id: I9e7bde7b2c90b8b34c6aa8e90a16cd29dc108fe9
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3360
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 359501a7b715c9d7cfcd6cdefddeeb4c0450a2f7
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue May 21 12:17:58 2013 -0500

    coreboot: Add generic early SMBus API
    
    Early SMBUS code with similar functionality is duplicated for all
    southbridges. Add a generic SMBus API (function declarations) designed to
    unify the early SMBus structure.
    
    This patch only adds the API. It does not implement any hardware-specific
    bits.
    
    Change-Id: I0861b7a3f098115182ae6de9f016dd671c500bad
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/143
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 78706fd61f44f2765f54d00bdb5cfc2144bb0de4
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Jun 3 13:58:10 2013 -0500

    DDR3: Add utilities for creating MRS commands
    
    MRS commands are used to tell the DRAM chip what timing and what
    termination and drive strength to use, along with other parameters.
    The MRS commands are defined by the DDR3 specification [1]. This
    makes MRS commands hardware-independent.
    
    MRS command creation is duplicated in various shapes and forms in any
    chipset that does DDR3. This is an effort to create a generic MRS API
    that can be used with any chipset.
    
    This is used in the VX900 branch.
    
    [1] www.jedec.org/sites/default/files/docs/JESD79-3E.pdf
    
    Change-Id: Ia8bb593e3e28a5923a866042327243d798c3b793
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3354
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 775551c69e1f2d0ab69ea35ef6cbccfddec415d6
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Jun 3 23:16:50 2013 -0500

    VIA Nano: Add microcode updates files
    
    While we had support for updating microcode on the VIA Nano CPUs for a
    while now, we never included the actual microcode. Unlike, Intel and
    AMD CPUs, VIA microcode is not available for download, and was
    extracted from the vendor BIOS. It was not included in coreboot since
    we never had explicit permission to do so. I have just received
    confirmation from VIA that we can distribute the microcode.
    
    Change-Id: I4c15b090cd2713cfe5dc6b50db777ff89dbc0f19
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3357
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7bc3575458b7d3bb58210a0a0d8fd41390430090
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Tue Jun 4 17:40:40 2013 +0200

    AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"
    
    Change-Id: I249c63646267ebe8dd8e06980aa6367a16fe7297
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3370
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c4e07bb50345f1b95ae2f80fc42694d3533c628e
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Tue Jun 4 17:34:35 2013 +0200

    AMD Northbridge LX: convert spd_read_byte() to non-static version
    
    Change-Id: Ie329606852dfd7109acb694e9a9ff851b023cc63
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3369
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4eb5aa2894b1115909a672470bb22c7804c20561
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Tue Jun 4 17:27:22 2013 +0200

    AMD Northbridge LX: move #include "northbridge/amd/lx/raminit.h"
    
    Move the include before static inline int spd_read_byte().
    
    Change-Id: I4cac4b1f55368041b067422d95c09208e15d0f2d
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3368
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e2dc80ceacd3d15574f8bd075ab84e4f02920d95
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Tue Jun 4 16:23:43 2013 +0200

    AMD Northbridge LX: rename get_systop() to get_top_of_ram()
    
    Change-Id: I6126d575b8289f76b38858304836e3037200bcdb
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3367
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 84ae76caf829676f84de4d11bfff95763181d406
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Tue Jun 4 14:38:24 2013 +0200

    AMD Northbridge LX: include northbridge.h in raminit.c
    
    Change-Id: Ic2f50ae184678637c611757d3391826c1d2719a1
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3365
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 194ec4d4d567a94297b5c59196530811b0483619
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Tue Jun 4 14:30:50 2013 +0200

    AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-static
    
    Change-Id: Id914be1ae4dac96c51f2640f056af4ce58a248eb
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3364
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6f9f785d9bf226fdf65206c4e45315f6e1533545
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Tue Jun 4 14:12:10 2013 +0200

    AMD Northbridge LX: add some missing includes
    
    This commit fixes problems if we build raminit.c
    for romstage.
    
    Change-Id: Ic1380f3635ac28b939fa2a8ce614814012455c44
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3363
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit eb6322f4b073aa9c430c8c76d2387b9b76b25843
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Tue Jun 4 14:08:46 2013 +0200

    AMD Northbridge LX: make sdram_* function prototypes non-static
    
    In order to get rid of the bad #include "northbridge/amd/lx/raminit.c"
    line we need to do some prepartion steps. This commit is one of them.
    
    Change-Id: I33173660bbda8894e7672e41e1b994d254d7ae8a
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3362
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 29840e234cf6a58313d7d8bc1db1b2fcd5a33bb1
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Tue Jun 4 19:56:22 2013 +0800

    AMD Fam 15tn: Use all memory on systems with more than 4 GB
    
    Take a Parmer board with 4G memory as an example.
    
    Use 'cat /proc/meminfo' to check memory, it reads 'MemTotal 3327540kB'.
    Parmer uses 512M as video memory when it has 4G.
    3327540+512*1024 = 3851828(kB), so some memory is lost.
    
    When Parmer has 4G memory, TOM2 low is 0x1F000000, TOM2 high is
    0x00000001. But in e820 table or coreboot table, the last item is
    
        6: 0000000100000000 - 0000000118000000 = 1 RAM
    
    This is not correct, it should be
    
        6: 0000000100000000 - 000000011f000000 = 1 RAM
    
    This patch changes the memory layout when TOM2 is set.
    
    Change-Id: I4e2d163ae8fe1e65ddc384b520a5112ca067b1d1
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3366
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5b0420a87b913d7c672fa8cd7b21218b6de3a247
Author: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Date:   Tue May 28 16:33:15 2013 -0600

    crossgcc/buildgcc: Remove unneeded 'break' statements
    
    Bash case statements are terminated with ';;'.
    
    Unlike C, bash case statements will not continue to the next case. No 'break' is needed.
    
    Change-Id: I62e7e91f3223ac4052728a1ca12a4681af0dc036
    Signed-off-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
    Reviewed-on: http://review.coreboot.org/3330
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f97ff3f72c038b711fd3c1e7b73abaa05add2094
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue May 21 14:43:45 2013 -0500

    dram: Add utilities for decoding DDR3 SPDs
    
    Add convenience utilities for decoding DDR3 SPDs and printing the
    information to the console. These have proven invaluable when writing the
    VX900 memory initialization.
    
    These are used in the VX900 branch
    
    Information printed has the following format:
    
    > SPD Data for DIMM 51
    >   Revision: 10
    >   Type    : b
    >   Key     : 2
    >   Banks   : 8
    >   Capacity: 1 Gb
    >   Supported voltages: 1.5V
    >   SDRAM width       : 8
    >   Bus extension     : 0 bits
    >   Bus width         : 64
    >   Optional features : DLL-Off_mode RZQ/7 RZQ/6
    >   Thermal features  : ASR ext_temp_range
    >   Thermal sensor    : no
    >   Standard SDRAM    : no
    >   Row    addr bits  : 13
    >   Column addr bits  : 10
    >   Number of ranks   : 1
    >   DIMM Capacity     : 1024 MB
    >   CAS latencies     : 6 7 8 9
    >   tCKmin            :   1.500 ns
    >   tAAmin            :  13.125 ns
    >   tWRmin            :  15.000 ns
    >   tRCDmin           :  13.125 ns
    >   tRRDmin           :   6.000 ns
    >   tRPmin            :  13.125 ns
    >   tRASmin           :  36.000 ns
    >   tRCmin            :  49.125 ns
    >   tRFCmin           : 110.000 ns
    >   tWTRmin           :   7.500 ns
    >   tRTPmin           :   7.500 ns
    >   tFAWmin           :  30.000 ns
    
    Change-Id: I30725a75caf74ac637db0a143344562bd9910466
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3267
    Tested-by: build bot (Jenkins)

commit 32610462d12bee4f901e7f5eefef63f200f22805
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue May 21 14:07:41 2013 -0500

    spd.h: Add all known SPD_MEMORY_TYPE definitions.
    
    This file was missing some definitions, so add them. Also turn the defines
    into an enum. The reason for doing this is that functions can now
    explicitly take an spd_memory_type as a parameter:
    
    > int do_something_with_dram(enum spd_memory_type type, ...)
    
    Which is a lot more explicit and readable than:
    
    > int do_something_with_dram(u8 type, ...)
    
    These are used in the VX900 branch.
    
    Change-Id: Ic7871e82c2523a94eac8e07979a8e34e0b459b46
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/3266
    Tested-by: build bot (Jenkins)

commit 8e4bb92898992446b6264f06b4f20236a65ae962
Author: Nico Huber <nico.huber@secunet.com>
Date:   Sun May 26 18:17:54 2013 +0200

    util/cbmem: Fix format string in cbmem.c
    
    Use PRIx64 to print a u64 instead of "llx". Fixes the following error:
    
    cbmem.c: In function 'parse_cbtable':
    cbmem.c:135:2: error: format '%llx' expects argument of type 'long long unsigned int', but argument 2 has type 'u64' [-Werror=format=]
    
    Change-Id: Ibc2bf8597cb86db5b2e71fba77ec837a08c5e3d4
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3301
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8048e740a334bb7dcf8f23662c73d0ca01e53c7f
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon May 13 18:22:23 2013 +0200

    include/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other defines
    
    Probably due to different (character) widths for a tab, sometimes only
    one tab was used for aligning the define `CPU_ID_EXT_FEATURES_MSR`. For
    the “correct” alignment, that means where a tab is eight characters,
    two tabs are necessary. Change it accordingly.
    
    Change-Id: I450a7796dc00b934b5a6bab8642db04a27f69f4b
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3263
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1b22827cf0f190f26dcccec5ae5f36eb4972cde4
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon May 27 20:39:18 2013 +0200

    Asus F2A85-M: Fix the _CRS PCI0 bus info
    
    On Asus F2A85-M, the Linux kernel complains that the _CRS method does
    not specify the number of PCI busses.
    
        [FIRMWARE BUG]: ACPI: no secondary bus range in _CRS
    
    Just put there 256. This should be part of re-factoring of the whole
    ACPI stuff.
    
    The same change was already done for the AMD Brazos (SB800) boards,
    based on commit »Persimmon DSDT: Add secondary bus range to PCI0«
    (4733c647) [1].
    
    [1] http://review.coreboot.org/2592
    
    Change-Id: I06f90ec353df9198a20b2165741ea0fe94071266
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/3320
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>

commit 01c095ff4c7ab8cf53f608395824f4e01bef1a42
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Wed May 29 20:30:18 2013 +0000

    AMD Geode CS5536: downgrade BIOS_ERR
    
    There is no need to use everywhere BIOS_ERR.
    
    Change-Id: If33d72919109244a7c3bd96674a4e386c8d1a19e
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3307
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 038aa29dc283205a993578f0ff3881df12ebdb0a
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Wed May 29 13:06:22 2013 +0200

    console: add support for QEMU's debugcon
    
    Add support for sending debug output to an I/O port.
    
    It can be used together with QEMU's isa-debugcon driver to log the
    coreboot output to a file.  The port is configurable and defaults
    to 0x402 which has established as the de facto standard. For example,
    SeaBIOS+OVMF [1] use that one too.
    
    [1] http://www.linux-kvm.org/page/OVMF
        Open Virtual Machine Firmware
    Change-Id: I0803f7fc70030242f80003e25c9449c37d71975e
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3331
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 66da043e48c65e6d89b385d840e5f7c53e482db9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue May 28 14:26:29 2013 -0500

    haswell: allow for disabled hyperthreading
    
    There were assumptions being made in the haswell
    MP and SMM code which assumed the APIC id space
    was 1:1 w.r.t. cpu number. When hyperthreading is
    disabled the APIC ids of the logical processors
    are all even. That means the APIC id space is sparse.
    Handle this situation.
    
    Change-Id: Ibe79ab156c0a171208a77db8a252aa5b73205d6c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3353
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 27435d3bcdd4c7bccb326f77ca64a54d3fb1170a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Jun 3 09:46:56 2013 -0500

    haswell: fix overflow handling TOUUD
    
    It's possible that the TOUUD can be set to less than
    4GiB. When that is the case the size_k variable is
    an extremely large value. Instead ensure TOUUD is greater
    than 4GiB before adding said resources.
    
    Change-Id: I456633d6210824e60665281538300fd15656b86d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3352
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 373a20c335bdd747d7a2553f0e72e2b3a46f86e8
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri May 3 12:17:02 2013 +0200

    Intel Lynx Point: LPC: Unify I/O APIC setup
    
    Remove local copies of reading and writing I/O APIC registers by
    using already available functions.
    
    This change is similar to
    
        commit db4f875a412e6c41f48a86a79b72465f6cd81635
        Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
        Date:   Tue Jan 31 17:24:12 2012 +0200
    
            IOAPIC: Divide setup_ioapic() in two parts.
    
            Reviewed-on: http://review.coreboot.org/300
    
    and
    
        commit e614353194c712a40aa8444a530b2062876eabe3
        Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
        Date:   Tue Feb 26 17:24:41 2013 +0200
    
            Unify setting 82801a/b/c/d IOAPIC ID
    
            Reviewed-on: http://review.coreboot.org/2532
    
    and uses `io_apic_read()` and `io_apic_write()` too. Define
    `ACPI_EN` in the header file `pch.h`.
    
    As commented by Aaron Durbin, a separate `pch_enable_acpi()` is
    not needed: “The existing code path *in this file* is about enabling
    the io apic.” [1].
    
    [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c
    
    Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3182
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 9c50e6a4a071a03c4dedd8eb87022644e9ee74c3
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri May 3 12:23:39 2013 +0200

    Intel BD82x6x: LPC: Unify I/O APIC setup
    
    Remove local copies of reading and writing I/O APIC registers by
    using already available functions.
    
    This change is similar to
    
        commit db4f875a412e6c41f48a86a79b72465f6cd81635
        Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
        Date:   Tue Jan 31 17:24:12 2012 +0200
    
            IOAPIC: Divide setup_ioapic() in two parts.
    
            Reviewed-on: http://review.coreboot.org/300
    
    and
    
        commit e614353194c712a40aa8444a530b2062876eabe3
        Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
        Date:   Tue Feb 26 17:24:41 2013 +0200
    
            Unify setting 82801a/b/c/d IOAPIC ID
    
            Reviewed-on: http://review.coreboot.org/2532
    
    and uses `io_apic_read()` and `io_apic_write()` too. Define
    `ACPI_EN` in the header file `pch.h`.
    
    As commented by Aaron Durbin, a separate `pch_enable_acpi()` is
    not needed: “The existing code path *in this file* is about enabling
    the io apic.” [1].
    
    [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c
    
    Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3183
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 42409e87322e974e81db9e0ac8b454e205fe8d3b
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat May 4 18:07:13 2013 +0200

    northbridge/amd/amdmct: Use `static const` instead of `const static`
    
    From ISO C99 standard: »The placement of a storage-class specifier
    other than at the beginning of the declaration specifiers in a
    declaration is an obsolescent feature.«
    
    Found at <http://www.approxion.com/?p=41>.
    
    The following command was used to make the change.
    
        $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/'
    
    As asked by Bruce Griffith, the changes in `src/vendorcode` were
    reverted as that is what AMD prefers.
    
    The same change was done already for AMD Persimmon in the following
    commit.
    
        commit 824e192809e021b3cdee947a44b3a18d276bdb35
        Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
        Date:   Wed Feb 20 21:24:20 2013 +0100
    
            Persimmon: platform_cfg.h: Declare codec arrays as `static const`
    
            Reviewed-on: http://review.coreboot.org/2474
    
    Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3197
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 3aa58162e1be25ad77800879e73a087ddbdc660c
Author: Gabe Black <gabeblack@chromium.org>
Date:   Wed May 29 16:42:20 2013 +0200

    am335x: Clean up/fix some settings in the am335x Kconfig.
    
    Some settings in the am335x Kconfig weren't actually used for anything, some
    where place holders, and some where left over from another CPU. The memory
    addresses are in the internal RAM in the SOC as described in the reference
    manual. The stack is put where the internal ROM had its stack, and the
    bootblock is put at the bottom of that region as the manual suggests. The
    ROM stage offset is set to 10K which is a bit bigger than the ~7.5K the
    bootblock currently takes up.
    
    Change-Id: I1a117d789a791d7e3db1118823f8216b3361433c
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3327
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 29a435597345e1e05a449f2e864c8e3746538c45
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Tue May 28 13:46:12 2013 +0200

    Provide sane Kconfig default for cmos.default.
    
    Without that fix we have with CONFIG_USE_OPTION_TABLE:
    
        OPTION     cmos_layout.bin
      build/util/nvramtool/nvramtool -y /home/gnutoo/x86/coreboot-alix/src/mainboard/pcengines/alix1c/cmos.layout -L build/cmos_layout.bin
      make: *** No rule to make target `nvramtool', needed by `build/coreboot.pre1'.  Stop.
      rm build/util/sconfig/sconfig.tab.c build/cbfs/fallback/bootblock.elf build/util/sconfig/lex.yy.c
    
    That log was captured with make V=1 but the error also appear with make.
    
    Tested on the PC Engines ALIX.1C with the following commit (Change-Id: Ia87b090) [1]:
    
      PC Engines ALIX.1C: Add CMOS defaults.
    
    [1] http://review.coreboot.org/#/c/3323/
    
    Change-Id: I548005a58f430ed7b6da5249a24bbdcae440a1e9
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3223
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 8977b6ac5ca4e99289c1f49a878e6901094c8cc2
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Fri Apr 26 14:49:27 2013 +0200

    Lenovo ThinkPad X60: cleanup Native VGA init.
    
    Change-Id: Iaefa23a6257fd0295357465eb03ccadbef0f70da
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3272
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 474eeedbc85545fce4e5feba21e79bd043d2f858
Author: Steven Sherk <steven.sherk@se-eng.com>
Date:   Wed May 22 13:49:18 2013 -0600

    AMD Trinity boards: Add reserved memory area for SPI base address in ACPI
    
        - SPI controller base address gets overwritten by SD controller under Linux.
    
        - Reason for overwrite is the SPI base address isn't in a standard BAR and doesn't
          get automatically reserved. Solution is to add it as a reserved memory area in
          ACPI.
    
        - This issue was found on the ASUS F2A85-M platform. Currently a workaround on this
          platform was made as part of: http://review.coreboot.org/#/c/3167/3
    
        - Once approved a follow-on patch for other southbridges using a non-standard BAR for
          the spi controller.
    
    Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e
    Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3270
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0390112407c042211428a2aee1ab77422caab338
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Fri May 31 19:36:30 2013 +0800

    AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard'
    
    This issue can be reproduced in Linux by the following steps:
    1) use pm-suspend to suspend.
    2) use USB keyboard to wake up.
    3) use pm-suspend to suspend. FAIL To SUSPEND.
    
    The cause of this issue is:
    USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event,
    but this bit is not clear after wake up. So OS thinks there is a
    wake up signal and wake up immediately.
    
    In this patch, I add AcpiGpe0Blk using MMIO access and write 1
    on bit 11. I have tested on Parmer.
    
    Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3347
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d189229b45866105a8f4a8aac44a59774d030f81
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue May 14 10:06:47 2013 +0200

    AMD Llano, Brazos boards: Use `sizeof(var)` to get its size
    
    Change `sizeof(type) * n`, where n is the number of array
    elements, to `sizeof(variable)` to directly get the size of the
    variable (struct, array). Determining the size by counting array
    elements is error prone and unnecessary.
    
    Rudolf Marek’s patch »ASUS F2A85-M: Correct and clean up PCIe
    config« [1] contains the same change and is ported over. In
    the commit message Rudolf makes the following comment.
    
    »Not sure why the copy is needed instead of direct reference.
    Maybe it has something to do with CAR?«
    
    Testing on the ASRock E350M1, no regressions were noticed.
    
    [1] http://review.coreboot.org/#/c/3194/
    
    Change-Id: I123031b3819a10c9c85577fdca96c70d9c992e87
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3248
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit d3ed411123c9655c6013cb8ed8d3d91cc2dc8c62
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat May 4 00:08:34 2013 +0200

    AMD Trinity boards: Use `sizeof(var)` to get its size
    
    Change `sizeof(type) * n`, where n is the number of array
    elements, to `sizeof(variable)` to directly get the size of the
    variable (struct, array). Determining the size by counting array
    elements is error prone and unnecessary.
    
    Not sure why the copy is needed instead of direct reference.
    Maybe it has something to do with CAR?
    
    These changes are based on Rudolf’s original patch »ASUS F2A85-M:
    Correct and clean up PCIe config« [1], where it was just done for
    the ASUS board.
    
    [1] http://review.coreboot.org/#/c/3194/
    
    Change-Id: I4aa4c6cde5a27b7f335a71afc21d1603f2ae814b
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3247
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit 1a71f4c21f86fe058da9dee3be1d9db5448fe1b7
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Wed May 29 14:53:03 2013 +0200

    qemu: remove vga hook
    
    Extra care for the qemu vga should not be needed any more.
    Since release 0.12 qemu loads the vgabios into the PCI ROM
    bar, so everything works exactly like it does on real hardware.
    
    Change-Id: I4b9bf1244cad437cbe5168600aeee52031456033
    Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
    Reviewed-on: http://review.coreboot.org/3333
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c4fd2973ab7334c810f48d68369b8d0448d0f278
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Mon May 27 08:54:25 2013 +0200

    cpu/amd/geode_lx/Kconfig: Select TSC_MONOTONIC_TIMER
    
    The following is an excerpt from serial log of the Bachmann OT200.
    
    $ grep usec coreboot_log
    clocks_per_usec: 500
    Root Device init 48034 usecs
    CPU_CLUSTER: 0 init 133251 usecs
    PCI: 00:01.0 init 33376 usecs
    PCI: 00:01.1 init 9930 usecs
    PCI: 00:01.2 init 9929 usecs
    PCI: 00:04.0 init 9929 usecs
    PCI: 00:0f.0 init 185788 usecs
    PCI: 00:0f.2 init 21473 usecs
    PCI: 00:0f.3 init 9930 usecs
    PCI: 00:0f.4 init 9930 usecs
    PCI: 00:0f.5 init 9930 usecs
    PCI: 00:0f.6 init 9930 usecs
    PCI: 00:0f.7 init 9929 usecs
    
    Change-Id: I4d0805c4cf8fcb25ec107615787fc6da0c945a30
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/3308
    Tested-by: build bot (Jenkins)

commit e4e8e090fa36cb3a098e1ddf0ea44c796c140572
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sun Mar 31 13:51:37 2013 +0200

    util/inteltool: Add support for mobile 5 chipset
    
    Dump registers on mobile 5. Successfully tested on X201.
    
    Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/2993
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 3c7e939c3e18b3d286c084ff95266611a0150ca1
Author: Gabe Black <gabeblack@chromium.org>
Date:   Sun May 26 07:15:57 2013 -0700

    beaglebone: initial Kconfig and Makefiles
    
    Initial structure of Beaglebone port
    
    Change-Id: Ia255ab207f424dcd525990cdc0d74953e012c087
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3279
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b460a66aa96a42349ebbd2e6e8d450787437e0e3
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun May 26 05:33:35 2013 -0700

    Get buildgcc to behave reasonably with the -p choice.
    
    buildgcc has many wrong choices, and two right ones,
    but you would never guess that. It's even more
    frustrating when it spends lots of time building a
    full tool chain and you find out it's not the one you
    wanted and, still worse, you've forgotten what it does want
    and, even worse, it won't f-ing tell you what the two
    right choices are!.
    
    Have it tell you when you've done something wrong, and have it
    make reasonable decisions when you say things like
    -p arm
    instead of
    -p armv7a-eabi
    
    This change lowers my blood pressure 10 points.
    
    Change-Id: I44a59d7cb7a6260894d8bcb692a693ed25681ff8
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3292
    Tested-by: build bot (Jenkins)

commit ac6ea04b627e9a045a1600fa36e44150e9e5622b
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Apr 29 23:21:07 2013 +0200

    Lenovo ThinkPad T60: Add support for `EARLY_CBMEM_INIT` needed for CBMEM console
    
    Add code to support `EARLY_CBMEM_INIT` needed for CBMEM console
    support by copying GNUtoo’s commit for the Lenovo ThinkPad X60.
    
        commit 4560ca5003fe38a066616e8de1a8a414284750fd
        Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
        Date:   Fri Apr 26 12:21:41 2013 +0200
    
            Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support.
    
            Reviewed-on: http://review.coreboot.org/3142
    
    Change-Id: I0c4ca5a5e60f4bb3b91653a133ec71039fcca6ab
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3187
    Tested-by: build bot (Jenkins)
    Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit c6d1da0b18a35470c5cf5d366d33fac957ae7974
Author: Gabe Black <gabeblack@chromium.org>
Date:   Sun May 26 11:31:56 2013 +0200

    snow: Add a name to the serial console UART choice block.
    
    This allows other boards to have the same choice block without confusing
    kconfig.
    
    Change-Id: Iea5a7f2d1c263aa7992f504b832ca9c862833c3f
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3293
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 330bb6acc8b198d95acc979c89de2d7ed1c0c96f
Author: Roman Zippel <zippel@linux-m68k.org>
Date:   Fri Feb 29 05:10:24 2008 +0100

    kconfig: fix choice dependency check
    
    Properly check the dependency of choices as a group.
    Also fix that sym_check_deps() correctly terminates the dependency loop
    error check (otherwise it would continue printing the dependency chain).
    
    Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
    Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
    
    =======
    
    Cherry-picked from the Linux kernel.
    
    Change-Id: I0c98760dd0f55cf2ff70c53e0b014288b59574c8
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3290
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 48757668a533d3764108555e9b8727d0d84aaffc
Author: Roel Kluin <12o3l@tiscali.nl>
Date:   Thu Mar 20 21:30:32 2008 +0100

    kconfig: reversed borderlines in inputbox
    
    Fix reversal of dlg.border.atr and dlg.dialog.atr for draw_box()
    Makes the inputbox look like expected
    
    Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
    Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
    
    =======
    
    Cherry-picked from the Linux kernel.
    
    Change-Id: I596915aab0204ef0e392fefa56fad8e25204e207
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3289
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 543aa7ba7bcc367d420f910141c33068154e5b3a
Author: Roman Zippel <zippel@linux-m68k.org>
Date:   Fri Feb 29 05:11:50 2008 +0100

    kconfig: add named choice group
    
    As choice dependency are now fully checked, it's quite easy to add support
    for named choices. This lifts the restriction that a choice value can only
    appear once, although it still has to be within the same group,
    but multiple choices can be joined by giving them a name.
    While at it I cleaned up a little the choice type logic to simplify it a
    bit.
    
    Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
    Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
    
    =======
    
    Cherry-picked from the Linux kernel.
    
    Change-Id: If0f00d1783907d606220cda5307b8960d3bfc38d
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3291
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5750fddcba16101e39bf9ec739d9a8bc8e2c0ae9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed May 8 17:08:55 2013 +0200

    Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`
    
    multiply_to_tsc was being copied everywhere, which is bad
    practice. Put it in the tsc.h include file where it belongs.
    Delete the copies of it.
    
    Per secunet, no copyright notice is needed.
    
    This might be a good time to get a copyright notice into tsc.h
    anyway.
    
    Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3242
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 60c54cc017becb842156644bcda2591a13ba10bc
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed May 1 16:36:56 2013 +0200

    cpu/amd/agesa/Kconfig: Select LAPIC_MONOTONIC_TIMER
    
    Thanks to Aaron Durbin coreboot provides monotonic timers. Select
    the LAPIC monotonic timer for the AMD AGESA CPUs.
    
    The following is an excerpt from serial log of the ASRock E350M1.
    
        $ grep usec seriallog-20130502_100902.log
        01.016: Root Device init 1578 usecs
        01.029: CPU_CLUSTER: 0 init 112415 usecs
        01.029: PCI: 00:00.0 init 3240 usecs
        01.088: PCI: 00:01.0 init 104572 usecs
        01.088: PCI: 00:01.1 init 1663 usecs
        01.088: PCI: 00:11.0 init 1662 usecs
        01.088: PCI: 00:14.0 init 1662 usecs
        01.088: PCI: 00:14.3 init 8665 usecs
        01.088: PCI: 00:14.4 init 1665 usecs
        01.088: PCI: 00:18.0 init 1662 usecs
        01.088: PCI: 00:18.1 init 1663 usecs
        01.088: PCI: 00:18.2 init 1663 usecs
        01.088: PCI: 00:18.3 init 1663 usecs
        01.088: PCI: 00:18.4 init 1663 usecs
        01.088: PCI: 00:18.5 init 1665 usecs
        01.088: PCI: 00:18.6 init 1664 usecs
        01.088: PCI: 00:18.7 init 1663 usecs
        01.088: PNP: 002e.2 init 1576 usecs
        01.088: PNP: 002e.5 init 1577 usecs
        01.088: PNP: 002e.a init 1590 usecs
        01.088: PNP: 002e.b init 30144 usecs
        01.088: PCI: 03:00.0 init 1663 usecs
    
    So the graphics device needs around 100 ms for being initialized.
    
    The full serial log is in the Gerrit comments.
    
    Change-Id: Ia7b3012e51fcf94b0f22290cdef2b4424295ad6d
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3172
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 4e01cfb6d5199b9061ec9df79446aab90553380f
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon May 13 23:06:34 2013 +0200

    cpu/intel/haswell/Kconfig: Intend help text with two spaces
    
    Commit »haswell: 24MHz monotonic time implementation« (c46cc6f1) [1]
    added the Kconfig variable `MONOTONIC_TIMER_MSR` with a help text,
    but only used one space instead of the suggested two spaces for
    indentation. So add one space.
    
    »Lines under a "config" definition are indented with one tab, while
    help text is indented an additional two spaces.« [2]
    
    [1] http://review.coreboot.org/3153
    [2] https://www.kernel.org/doc/Documentation/CodingStyle
        (Chapter 10: Kconfig configuration files)
    
    Change-Id: I39cf356bfd54c66a2f1b837c6667dcc915e41f29
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3262
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 87b9bf5bad4f40ec39371df571f806350aa3d9a2
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon May 13 23:59:20 2013 +0200

    include/timer.h: Fix typo in in*iti*alize in comment
    
    Correct a typo in a comment introduced in commit »coreboot:
    introduce monotonic timer API« (a421791d) [1].
    
    [1] http://review.coreboot.org/3152
    
    Change-Id: Ia0abc5304547d419478db1ae37b5525406fa19cc
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3261
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 51837f9dac3cf688a40b6d70ebc56d2f3913c5f4
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri May 17 17:25:25 2013 +0200

    Intel Sandy Bridge: udelay.c: Change comparison from <= to <
    
    Currently code in `udelay.c` differs between the Intel northbridges
    GM45, 945 on the one hand and Sandy Bridge on the other hand.
    
    The reason for this is that a wrong comparison > was used.
    
    The following commit
    
        commit 784ffb3db694dd2c964d9a4e1c6657a835b2d141
        Author: Sven Schnelle <svens@stackframe.org>
        Date:   Tue Jan 10 12:16:38 2012 +0100
    
            i945: fix tsc udelay()
    
            Reviewed-on: http://review.coreboot.org/530
    
    fixed the sign from > to <, whereas Stefan Reinauer changed it from
    > to <= before adding the Sandy Bridge port in the following commit.
    
        commit 00636b0daefc3c499990744226a0e1a316d71731
        Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
        Date:   Wed Apr 4 00:08:51 2012 +0200
    
            Add support for Intel Sandybridge CPU (northbridge part)
    
            Reviewed-on: http://review.coreboot.org/854
    
    As there are no technical reasons for this difference, unify this
    between the chipsets. See the discussion of the other patch set in
    Gerrit [1].
    
    [1] http://review.coreboot.org/#/c/3220/1/src/northbridge/intel/i5000/udelay.c
    
    Change-Id: I64f2aa1db114ad2e9f34181c5f3034f6a8414a11
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3259
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit 1e24f4b37ff4bef3b3130b5399f6302cafa5f555
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed May 1 16:21:53 2013 +0200

    Kconfig: Remove duplicate entry for `USE_OPTION_TABLE`
    
    The following commit
    
        commit eb50c7d922e91f0247b3705eccb2d2eec638c277
        Author: Edwin Beasant <edwin_beasant@virtensys.com>
        Date:   Tue Jul 6 21:05:04 2010 +0000
    
        Re-integrate "USE_OPTION_TABLE" code.
    
    added a duplicate entry `config USE_OPTION_TABLE`. Remove it again.
    
    Change-Id: I3ff64c360bad531439e74fa1b25a06c4a447a33f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3165
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 393619b9a6dc1db73421f9c731feaa9201d85e61
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue May 14 12:28:42 2013 +0200

    intel/gm45: Add more debug output to read/write training
    
    Add debug output for the timing values of the edges found during
    read and write training.
    
    Now, output for one DIMM of DDR3-1066 in a roda/rk9 looks like:
    
    [...]
    Lower bound for byte lane 0 on channel 0: 0.0
    Upper bound for byte lane 0 on channel 0: 8.4
    Final timings for byte lane 0 on channel 0: 4.2
    Lower bound for byte lane 1 on channel 0: 0.0
    Upper bound for byte lane 1 on channel 0: 10.2
    Final timings for byte lane 1 on channel 0: 5.1
    Lower bound for byte lane 2 on channel 0: 0.0
    Upper bound for byte lane 2 on channel 0: 7.5
    Final timings for byte lane 2 on channel 0: 3.6
    Lower bound for byte lane 3 on channel 0: 0.0
    Upper bound for byte lane 3 on channel 0: 11.4
    Final timings for byte lane 3 on channel 0: 5.6
    Lower bound for byte lane 4 on channel 0: 0.0
    Upper bound for byte lane 4 on channel 0: 9.4
    Final timings for byte lane 4 on channel 0: 4.6
    Lower bound for byte lane 5 on channel 0: 0.0
    Upper bound for byte lane 5 on channel 0: 11.2
    Final timings for byte lane 5 on channel 0: 5.5
    Lower bound for byte lane 6 on channel 0: 0.0
    Upper bound for byte lane 6 on channel 0: 8.4
    Final timings for byte lane 6 on channel 0: 4.2
    Lower bound for byte lane 7 on channel 0: 0.0
    Upper bound for byte lane 7 on channel 0: 10.4
    Final timings for byte lane 7 on channel 0: 5.2
    Lower bound for group 0 on channel 0: 1.7.5
    Upper bound for group 0 on channel 0: 2.2.2
    Final timings for group 0 on channel 0: 1.10.7
    Lower bound for group 1 on channel 0: 1.6.1
    Upper bound for group 1 on channel 0: 2.0.2
    Final timings for group 1 on channel 0: 1.9.1
    Lower bound for group 2 on channel 0: 2.0.7
    Upper bound for group 2 on channel 0: 2.8.1
    Final timings for group 2 on channel 0: 2.4.4
    Lower bound for group 3 on channel 0: 2.4.7
    Upper bound for group 3 on channel 0: 3.0.0
    Final timings for group 3 on channel 0: 2.8.3
    [...]
    
    Final timings are always the average of the two bounds. The last dots
    separate eights (not decimals) and the middles are elenvenths or twelfths
    depending on the clock speed (twelfths in this case).
    
    Change-Id: Idb7c84b514716c7265b94890c39b7225de7800dc
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3257
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 12276acfd7d4847a79ce0c6aade8f33b2836f4df
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue May 14 12:15:05 2013 +0200

    intel/gm45: Handle overflows during DDR3 write training
    
    We halted the machine on any overflow during the write training.
    However, overflows during the search for a good to bad edge are
    non-fatal, and should be ignored.
    
    Change-Id: I45ccbabc214e208974039246d806b0d2ca2fdc03
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3256
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 08bee23f7eb31cce4746c51cfde3a7017e0e8b8e
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue May 14 11:58:44 2013 +0200

    intel/gm45: Refactor DDR3 write training
    
    Split some code in individual functions. It's the refactoring part of
    a bigger change, following...
    
    Change-Id: Id19be4588ad8984935040d9bcba4d7c5f2e1114f
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3255
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 35e45c078054a7bd64ba54b8b84b07602e8dd4ff
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue May 14 11:25:59 2013 +0200

    intel/gm45: Handle overflows during DDR3 read training
    
    We halted the machine on any overflow during the read training. However,
    overflows during the search for a good to bad edge are non-fatal, and
    should be ignored.
    
    Change-Id: I77085840ade25bce955480689c84603334113d1f
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3254
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 26a64351234093fbeea6e776be8829eae012ce7f
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue May 14 11:43:03 2013 +0200

    intel/gm45: Refactor DDR3 read training
    
    Split some code in individual functions. It's the refactoring part of
    a bigger change, following...
    
    Change-Id: Ied551a011eaf22f6f8f6db0044de3634134f0b37
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3253
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0da92863a754828eb807f1a15927f0dc288a1788
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue May 14 11:02:43 2013 +0200

    intel/gm45: Fix interpretation of VT-d disable bit
    
    When configuring the GTT size for the integrated graphics, the state
    of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is
    _disabled_.
    
    In the log of a VT-d enabled roda/rk9 we have now:
    
    [...]
    VT-d enabled
    [...]
    IGD decoded, subtracting 32M UMA and 4M GTT
    [...]
    
    Without this patch, only 2M GTT were reported.
    
    Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3252
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0f43af2ebb0d34ef6106d39d8614590253d5f4a9
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri May 17 15:58:35 2013 +0200

    intel/i5000: Remove unused copy of udelay.c
    
    It's a copy from i945 and looks like not beeing included in a
    build at all.
    
    If you should ever want to use that file for the Intel 5000,
    please copy it from another chipset like the Intel 945 as it
    is going to be improved.
    
    Change-Id: I5c113bb0b2fed7b93feb3dcb1b5d962e1442963a
    Reported-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3219
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 883b03f3230ad032dffae9e3e053c6c1963abebc
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon May 6 15:18:57 2013 +0200

    AMD AGESA Hudson: Include `stdint.h` and `io.h` to fix build
    
    Apparently the files `smbus.{h,c}`, where never used and therefore
    build beforehand. Needing one function in them for the ASUS F2A85-M
    the build fails as some headers are missing. Including the headers
    `stdint.h` and `io.h` fixes the following errors.
    
        […]
            CC         southbridge/amd/agesa/hudson/smbus.romstage.o
        In file included from src/southbridge/amd/agesa/hudson/smbus.c:23:0:
        src/southbridge/amd/agesa/hudson/smbus.h:67:24: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:67:43: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:67:55: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:68:25: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:68:44: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:68:56: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:68:69: error: unknown type name 'u8'
        src/southbridge/amd/agesa/hudson/smbus.h:69:24: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:69:43: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:70:24: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:70:43: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:70:55: error: unknown type name 'u8'
        src/southbridge/amd/agesa/hudson/smbus.h:71:20: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:71:35: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:71:49: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:71:59: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:71:69: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:72:20: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:72:35: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:72:49: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:72:59: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:73:20: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:73:32: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:73:44: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.h:73:54: error: unknown type name 'u32'
        src/southbridge/amd/agesa/hudson/smbus.c: In function 'smbus_delay':
        src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'outb' [-Werror=implicit-function-declaration]
        src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'inb' [-Werror=implicit-function-declaration]
        […]
    
    Probably all the (AMD(?)) `smbus.{h,c}` suffer from this and
    should be fixed. Even better, as these function do not differ
    between most boards, the file should be moved out from the
    specific southbridge directories.
    
    [1] http://qa.coreboot.org/job/coreboot-gerrit/6168/testReport/junit/(root)/board/i386_asus_f2a85_m/
    
    Change-Id: I285101fa06a365da44fa27b688c536e614d57f50
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3202
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit b2cddd4c12d99df55a1fd856cceea27372ce3f69
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun May 5 12:09:16 2013 +0200

    ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case
    
    Currently the code in the if statement
    
        if (!byte)
        	do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
    
    only gets executed if `byte == 0x0`, that means only in the
    default case where RAM voltage is 1.5 Volts. But the RAM voltage
    should be changed when configured for the non-default case.
    
    So negate the predicate to alter the RAM voltage for the
    non-default cases.
    
    To prevent the build error
    
        OBJCOPY    cbfs/fallback/coreboot_ram.elf
        coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main':
        /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte'
        collect2: error: ld returned 1 exit status
        make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1
    
    add `southbridge/amd/agesa/hudson/smbus.c` providing the function
    `do_smbus_write_byte` to ROM stage in `Makefile.inc`. That can
    actually be used after the needed header files are included in a
    previous commit.
    
    Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6
    Reported-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3200
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 963bed546f316af15bf1e4d1819388b8998ef5ec
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed May 15 11:47:51 2013 +0200

    Make: Use unaltered object list for dependency inclusion
    
    It looks like the inclusion of dependency files was broken for all
    ramstage objects since the list of those gets processed through the
    ramstage-postprocess macro. Fix that by taking the unaltered list
    for dependency files.
    
    The output of `make printall` (look for DEPENDENCIES=) shows which
    dependency files will be included.
    
    See also:
    
        commit 79f9010e80a04f2e0fb0cca5759e3215dff79aff
        Author: Patrick Georgi <patrick@georgi-clan.de>
        Date:   Sun Nov 25 14:31:08 2012 +0100
    
            build system: Add hook to postprocess classes (object lists)
    
    and:
    
        commit f33e395213f0516a9256f33ede4c6bba3babb0e9
        Author: Patrick Georgi <patrick@georgi-clan.de>
        Date:   Sun Nov 25 17:10:47 2012 +0100
    
            build system: Split linking into multiple steps
    
    Change-Id: If93b1773c5d53240f98382aab11bf7f5a4649ee8
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/3258
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b0fb2234be259a32325f5fc28750bd7b8aebc708
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 16 12:51:07 2013 -0700

    Drop llshell
    
    This feature has not been used and was never fully integrated.
    In the progress of cleaning up coreboot, let's drop it.
    
    Change-Id: Ib40acdba30aef00a4a162f2b1009bf8b7db58bbb
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3251
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d433acb8164aa836aadd14e00d11ed4dc31b029d
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Wed May 15 23:31:56 2013 -0600

    AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
    
    The following commit
    
        commit 05f3b117dd44776ed17bc57318f260766039b7e8
        Author: Paul Menzel <paulepanter@users.sourceforge.net>
        Date:   Tue May 14 09:28:26 2013 +0200
    
            AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
    
            Reviewed-on: http://review.coreboot.org/3246
    
    changed one calculation for the size of the array PortList[] to
    reflect only four elements, but neglected three additional calculations
    of the size of the same table.
    
    Correct that by setting the size for four array elements in all four
    calculations.
    
    [1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbPcie.c
    
    Change-Id: Ib66b7b2b388d847888663e9eb6d1c8c9d50b9939
    Reported-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3250
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 05f3b117dd44776ed17bc57318f260766039b7e8
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue May 14 09:28:26 2013 +0200

    AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
    
    The following commit
    
        commit d0790694b0a66353e5531715648ddaa1a6d577cb
        Author: Kerry Sheh <shekairui@gmail.com>
        Date:   Thu Jan 19 13:18:37 2012 +0800
    
            Inagua: Inagua GNB ddi lanes and pcie lanes config update
    
            Reviewed-on: http://review.coreboot.org/544
    
    assigns lanes 4 and 5 to PCI device number 4, but does not
    adapt the rest of the code.
    
    After the commit above, the array `PortList []` only has four
    elements, but the buffer size `AllocHeapParams.RequestedBufferSize`
    is set to a size as it still has five elements.
    
    Correct that by setting the size for four array elements.
    
    [1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbPcie.c
    
    Change-Id: I3ff07f308ffd417d2bf73117eda9da2a1a05f199
    Reported-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3246
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit 5b54d353aa89685c1cde0d6254a9899cf327a712
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri May 10 00:51:43 2013 -0500

    haswell: enable cache-as-ram migration
    
    The haswell code allows for vboot ramstage verification.
    However, that code path relies on accessing global cache-as-ram
    variables after cache-as-ram is torn down. In order to avoid
    that situation enable cache-as-ram migration.
    
    cbmemc_reinit() no longer needs to be called from romstage
    because it is invoked automatically by the cache-as-ram
    migration infrastructure.
    
    Change-Id: I08998dca579c167699030e1e24ea0af8802c0758
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3236
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2ad6bd23a7ebcaf593f717db9c356284237ed639
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri May 10 00:45:37 2013 -0500

    cbmem console: use cache-as-ram API and cleanup
    
    Allow for automatic cache-as-ram migration for the cbmem
    console. The code was refactored in the thought of making
    it easier to read. The #ifdefs still exist, but they are no
    longer sprinkled throughout the code. The cbmem_console_p
    variable now exists globally in both romstage and ramstage.
    However, the cbmem_console_p is referenced using the
    cache-as-ram API. When cbmem is initialized the console
    is automatically copied over by calling cbmemc_reinit()
    through a callback.
    
    Change-Id: I9f4a64e33c58b8b7318db27942e37c13804e6f2c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3235
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 677e1558c32d1c88ade486e5ac42e60a3da1fdcf
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri May 10 00:42:14 2013 -0500

    chromeos: use cache-as-ram migration API for vbnv
    
    It's possible that the vbnv global variables may be accessed
    in romstage after cache-as-ram is torn down. Therefore use
    the cache-as-ram migration API. Wrappers were written to
    wrap the API to keep the existing code as close as possible.
    
    Change-Id: Ia1d8932f98e00def0a44444a1ead0018a59d3d98
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3234
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cb997d3710900d5950d244edd607e25bb45ea962
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri May 10 00:40:56 2013 -0500

    pc80/tpm: allow for cache-as-ram migration
    
    As the TPM driver can be accessed in romstage after
    cache-as-ram is torn down use the cache-as-ram migration
    API to dynamically determine the global variable address.
    
    Change-Id: I149d7c130bc3677ed52282095670c07a76c34439
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3233
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 716738a6b84535f731ee9749f161505945eab93c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri May 10 00:33:32 2013 -0500

    x86: add cache-as-ram migration option
    
    There are some boards that do a significant amount of
    work after cache-as-ram is torn down but before ramstage
    is loaded. For example, using vboot to verify the ramstage
    is one such operation. However, there are pieces of code
    that are executed that reference global variables that
    are linked in the cache-as-ram region. If those variables
    are referenced after cache-as-ram is torn down then the
    values observed will most likely be incorrect.
    
    Therefore provide a Kconfig option to select cache-as-ram
    migration to memory using cbmem. This option is named
    CAR_MIGRATION. When enabled, the address of cache-as-ram
    variables may be obtained dynamically. Additionally,
    when cache-as-ram migration occurs the cache-as-ram
    data region for global variables is copied into cbmem.
    There are also automatic callbacks for other modules
    to perform their own migration, if necessary.
    
    Change-Id: I2e77219647c2bd2b1aa845b262be3b2543f1fcb7
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3232
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit adc300d88b35ceafafb4d4b6426c6458dc46b685
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Tue May 14 08:43:25 2013 -0600

    libpayload: Fix the logic for hardware-less serial consoles
    
    This fixes the configuration where serial console output is
    being sent to non-existant hardware to be captured with I/O
    trapping. In this configuration where there isn't serial
    hardware present we still want to init the consoles. We just
    never want to read non-existant hardware.
    
    Change-Id: Ic51dc574b9c0df3f6ed071086b0fb2119afedc44
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3249
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4bd7b0cbadabb45f9131da03121a6ca284f24f35
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri May 10 22:18:09 2013 +0200

    EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1.
    
    build-snow got broken when the snow makefile improved. So fix it.
    
    While we're at it, create a script like the update-microcode
    scripts that gets the bl1. I thought about making this a common
    script but the various names and paths always evolve, leaving
    me thinking it's not worth it. This script is just a
    piece of the snow build script.
    
    Change-Id: I65c0f8697a978c62fe12533c4f0152d14dbaefda
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3238
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 3a1457137e52bee5cb136196db97695142e85a5e
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat May 4 18:21:17 2013 +0200

    AMD Fam15tn boards: BiosCallOuts.c: Declare codec arrays as `static`
    
    These arrays are declared as `static` for AMD SB800 based boards,
    so do the same for this generation.
    
    Rudolf Marek just changed `const CODEC_TBL_LIST` to `static const`
    in [1]. Adapt all Fam15tn based boards (AMD Parmer, AMD Thatcher,
    ASUS F2A85-M) to keep the differences between them small.
    
    [1] http://review.coreboot.org/#/c/3170/3/src/mainboard/asus/f2a85-m/BiosCallOuts.c
    
    Change-Id: I353b38bd8bc77ba500a4b7fe9250e9aa3071c530
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3198
    Tested-by: build bot (Jenkins)

commit cd1cef44381be9e50182d693f118b8d636628a30
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat May 4 00:08:34 2013 +0200

    AMD Fam15tn boards: Document lane ID mapping from BKDG
    
    To make it easier to fill in the values, place the table
    from the BIOS and Kernel Developer’s Guide (BKDG) [1]
    as a comment.
    
    [1] http://www.coreboot.org/Datasheets#AMD_Fam15
    
    Change-Id: I218f76e9fa2dc88d47af51ea6c062e315afb0000
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3221
    Tested-by: build bot (Jenkins)

commit 38c326d041218e65d156ce3dd3bfee39e73ceffa
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon May 6 12:22:23 2013 -0500

    x86: add thread support
    
    Thread support is added for the x86 architecture. Both
    the local apic and the tsc udelay() functions have a
    call to thread_yield_microseconds() so as to provide an
    opportunity to run pending threads.
    
    Change-Id: Ie39b9eb565eb189676c06645bdf2a8720fe0636a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3207
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4409a5eef6d1d669caad1bfe3fbefee87ea7734e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon May 6 12:20:52 2013 -0500

    coreboot: add thread cooperative multitasking
    
    The cooperative multitasking support allows the boot state machine
    to be ran cooperatively with other threads of work. The main thread
    still continues to run the boot state machine
    (src/lib/hardwaremain.c).  All callbacks from the state machine are
    still ran synchronously from within the main thread's context.
    Without any other code added the only change to the boot sequence
    when cooperative multitasking is enabled is the queueing of an idlle
    thread. The idle thread is responsible for ensuring progress is made
    by calling timer callbacks.
    
    The main thread can yield to any other threads in the system. That
    means that anyone that spins up a thread must ensure no shared
    resources are used from 2 or more execution contexts. The support
    is originally intentioned to allow for long work itesm with busy
    loops to occur in parallel during a boot.
    
    Note that the intention on when to yield a thread will be on
    calls to udelay().
    
    Change-Id: Ia4d67a38665b12ce2643474843a93babd8a40c77
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3206
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8c8af592ca20e6c2dc48bea2c3ae66aa92c9dca7
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri May 10 09:23:42 2013 +0200

    AMD Brazos/Trinity boards: PlatformGnbPcie.c: Reserve correct amount of memory
    
    In `PlatformGnbPcie.c` AGESA functions are used to reserve memory
    space to save the PCIe configuration to. This is the
    
    With the following definitions in `AGESA.h`
    
        $ more src/vendorcode/amd/agesa/f14/AGESA.h
        […]
        /// PCIe port descriptor
        typedef struct {
          IN       UINT32               Flags;                    /**< Descriptor flags
                                                                   * @li @b Bit31 - last descriptor in complex
                                                                   */
          IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
          IN       PCIe_PORT_DATA       Port;                     ///< PCIe port specific configuration info
        } PCIe_PORT_DESCRIPTOR;
    
        /// DDI descriptor
        typedef struct {
          IN       UINT32               Flags;                    /**< Descriptor flags
                                                                   * @li @b Bit31 - last descriptor in complex
                                                                   */
          IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
          IN       PCIe_DDI_DATA        Ddi;                      ///< DDI port specific configuration info
        } PCIe_DDI_DESCRIPTOR;
    
        /// PCIe Complex descriptor
        typedef struct {
          IN       UINT32               Flags;                    /**< Descriptor flags
                                                                   * @li @b Bit31 - last descriptor in topology
                                                                   */
          IN       UINT32               SocketId;                 ///< Socket Id
          IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
          IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
          IN       VOID                 *Reserved;                ///< Reserved for future use
        } PCIe_COMPLEX_DESCRIPTOR;
        […]
    
    memory has to be reserved for the `PCIe_COMPLEX_DESCRIPTOR` and,
    as two struct members are pointers to arrays with elements of type
    `PCIe_PORT_DESCRIPTOR` and `PCIe_DDI_DESCRIPTOR`, space for these
    times the number of array elements have to be reserved:
    a + b * 5 + c * 2.
    
          sizeof(PCIe_COMPLEX_DESCRIPTOR)
        + sizeof(PCIe_PORT_DESCRIPTOR) * 5
        + sizeof(PCIe_DDI_DESCRIPTOR) * 2;
    
    But for whatever reason parentheses were put in there making this
    calculation incorrect and reserving too much memory.
    
        (a + b * 5 + c) * 2
    
    So, remove the parentheses to reserve the exact amount of memory
    needed.
    
    The ASRock E350M1 still boots with these changes. No changes were
    observed as expected.
    
    Rudolf Marek made this change as part of his patch »ASUS F2A85-M:
    Correct and clean up PCIe config« [1]. Factor this hunk out as it
    affects all AMD Brazos and Trinity based boards.
    
    [1] http://review.coreboot.org/#/c/3194/
    
    Change-Id: I32e8c8a3dfc5e87eb119eb17719d612e57e0817a
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3239
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit c49ae3c655172c98b31bde50796fccf42683ee9f
Author: Peter Stuge <peter@stuge.se>
Date:   Sun May 12 01:25:07 2013 +0200

    Revert "PC Engines ALIX.1C: Add CMOS defaults."
    
    Revert commit f90071faeee3358748d0c8d31e46721b53241e28 [1] as
    it was merged without its dependencies and therefore the source
    tree currently does not build [2][3].
    
            OPTION     option_table.h
            GEN        build.h
            SCONFIG    mainboard/pcengines/alix1c/devicetree.cb
            CC         arch/x86/lib/cbfs_and_run.romstage.o
            CC         arch/x86/lib/memcpy.romstage.o
            CC         arch/x86/lib/memset.romstage.o
            CC         arch/x86/lib/rom_media.romstage.o
            CC         arch/x86/lib/romstage_console.romstage.o
            CC         console/die.romstage.o
            CC         console/post.romstage.o
            CC         console/vtxprintf.romstage.o
            CC         device/device_romstage.romstage.o
            CC         lib/cbfs.romstage.o
            CC         lib/compute_ip_checksum.romstage.o
            CC         lib/gcc.romstage.o
            CC         lib/lzma.romstage.o
            CC         lib/memchr.romstage.o
            CC         lib/memcmp.romstage.o
            CC         lib/memmove.romstage.o
            CC         lib/ramtest.romstage.o
            CC         lib/uart8250.romstage.o
            CC         southbridge/amd/cs5536/smbus.romstage.o
            ROMCC      generated/bootblock.inc
            GEN        generated/bootblock.ld
        make: *** No rule to make target `nvramtool', needed by `coreboot-builds/pcengines_alix1c/coreboot.pre1'.  Stop.
        make: *** Waiting for unfinished jobs....
            OPTION     cmos_layout.bin
    
    [1] http://review.coreboot.org/#/c/3229/
    [2] http://www.coreboot.org/pipermail/coreboot/2013-May/075864.html
    [3] http://qa.coreboot.org/job/coreboot-gerrit/6251/testReport/junit/(root)/board/i386_pcengines_alix1c/
    
    Change-Id: I4764d90c39ccdb4dc7e7a9aef7525c306614e1a8
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3245
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 08d0baa77aaa9430b0f6c03cfaef8666bf19c4ce
Author: Peter Stuge <peter@stuge.se>
Date:   Sun May 12 01:24:50 2013 +0200

    Revert "Asus M4A785T-M: Add CMOS defaults."
    
    Revert commit b8b3e8bff32ee7dddcacec11e015f6683783eb2f [1] as
    it was merged without its dependencies and therefore the source
    tree currently does not build [2][3].
    
            OPTION     option_table.h
            SCONFIG    mainboard/asus/m4a785t-m/devicetree.cb
        make: *** No rule to make target `nvramtool', needed by `coreboot-builds/asus_m4a785t-m/coreboot.pre1'.  Stop.
        make: *** Waiting for unfinished jobs....
            OPTION     cmos_layout.bin
    
    [1] http://review.coreboot.org/3224
    [2] http://www.coreboot.org/pipermail/coreboot/2013-May/075864.html
    [3] http://qa.coreboot.org/job/coreboot-gerrit/6251/testReport/junit/(root)/board/i386_asus_m4a785t_m/
    
    Change-Id: I8bf33b62b56627f0eea9440ff5e5136e4122ef01
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/3244
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit d2898527414718bbcde089ffb217eafcbdfc6180
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Apr 23 08:42:09 2013 -0700

    Remove the wtm1 mainboard
    
    This was an early bring-up reference board for ULT but it is no
    longer being worked on and was never complete enough to be useful
    and I no longer have a board so it is already stale and untested.
    
    All ULT bring-up work has moved to the wtm2 mainboard instead.
    
    Change-Id: If64d61bf7a3fc8c9e16096ffc28fa4128aa99477
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48897
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3231
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit f90071faeee3358748d0c8d31e46721b53241e28
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Thu May 9 23:35:18 2013 +0200

    PC Engines ALIX.1C: Add CMOS defaults.
    
    After removing power and the CMOS Battery, putting it back
      and booting coreboot we have:
        # ./nvramtool -a
        boot_option = Fallback
        last_boot = Fallback
        ECC_memory = Disable
        baud_rate = 115200
        power_on_after_fail = Disable
        debug_level = Spew
        boot_first = HDD
        boot_second = Fallback_Floppy
        boot_third = Fallback_Network
        boot_index = 0xf
        boot_countdown = 0x7f
        nvramtool: Warning: Coreboot CMOS checksum is bad.
    
    Change-Id: Iba2701d4611cd2c2e5a2d76d41ffc23ed65574e8
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3229
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 33cde9a0ba62e8888e614a84f98860fe3a9ce82a
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Fri May 10 13:40:29 2013 -0600

    Make early x86 POST codes written to IO port optional
    
    This continues the work done in patch 6b908d08ab
    http://review.coreboot.org/#/c/1685/
    and makes the early x86 post codes follow the same options.
    
    Change-Id: Idf0c17b27b3516e79a9a53048bc203245f7c18ff
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3237
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c1ef740d88ea88c4ec7ef5449bd8d348fc15a9a2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Apr 23 08:39:19 2013 -0700

    haswell: Fix VGA option rom INT15 handler
    
    The format of this function changed but was not updated in
    all mainboards.  This fixes BaskingRidge and WTM2.
    
    The int15 handler no longer takes a regs structure as an
    argument and instead uses global variables.  The yabel interface
    is now similar enough that we can drop the duplicate handler.
    
    Change-Id: Ia717ae14f99cee6d83ccdb1e26b9d7defe1638c4
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/48896
    Reviewed-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3230
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ec664bcfa4ac3151f58853565b930b20b61b1bdd
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 9 14:06:04 2013 -0700

    romcc: support attribute((packed))
    
    right now this is just a fake option to get rid of ifdefs in
    coreboot's code.
    
    Change-Id: I59233f3c1d266b4e716a5921e9db298c7f96751d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3225
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 711a6fde0db2f7a0c388fc97faec1013caaa2789
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri May 3 18:25:27 2013 +0200

    Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary
    
    This option has never had much if any use. It solved a problem over 10
    years ago that resulted from an argument over the value or lack thereof
    of including all the debug strings in a coreboot image. The answer is
    in: it's a good idea to maintain the capability to print all messages,
    for many reasons.
    
    This option is  also misleading people, as in a recent discussion, to
    believe that log messges are controlled at build time in a way they are
    not. For the record, from this day forward, we can print messages at all
    log levels and the default log level is set at boot time, as directed by
    DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 at build time and
    if you are having trouble override it in CMOS and get more messages.
    
    Besides, a quick glance shows it's always set to max (9 in this case) in
    the very few cases (1) in which it is set.
    
    Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3188
    Tested-by: build bot (Jenkins)

commit c5e036a04368186fe73925c6fb101c594513391c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 9 14:33:14 2013 -0700

    Get rid of a number of __GNUC__ checks
    
    In the process of streamlining coreboot code and getting
    rid of unneeded ifdefs, drop a number of unneeded checks
    for the GNU C compiler. This also cleans up x86emu/types.h
    significantly by dropping all the duplicate types in there.
    
    Change-Id: I0bf289e149ed02e5170751c101adc335b849a410
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3226
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit b8b3e8bff32ee7dddcacec11e015f6683783eb2f
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Thu May 9 16:14:59 2013 +0200

    Asus M4A785T-M: Add CMOS defaults.
    
    After removing power and the CMOS Battery, putting it back
      and booting coreboot we have:
        # ./nvramtool -a
        boot_option = Fallback
        last_boot = Fallback
        ECC_memory = Enable
        baud_rate = 115200
        hw_scrubber = Enable
        interleave_chip_selects = Enable
        max_mem_clock = 400Mhz
        multi_core = Enable
        power_on_after_fail = Disable
        debug_level = Spew
        boot_first = HDD
        boot_second = Fallback_Floppy
        boot_third = Fallback_Network
        boot_index = 0xf
        boot_countdown = 0xc
        slow_cpu = off
        nmi = Enable
        iommu = Enable
        nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide.
        nvramtool: Warning: Coreboot CMOS checksum is bad.
    
    Change-Id: Ifa09c7a468e3e0713b426763266ae633e67d8397
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3224
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e04dc7529fdeb2730b826b687fc365e9720d6647
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Mon Apr 15 17:11:19 2013 +0800

    AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h
    
    The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE,
    GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used.
    
    Change-Id: I5c7b7d45880367dba452ebcd4f01fbd0c15aac22
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3087
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

commit bed88d65b2a142be1a0f278eef8dfbb64859077e
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed May 8 15:09:45 2013 +0200

    northbridge/intel/i5000/udelay.c: Remove unused header `console.h`
    
    Nothing from the header `console.h` is needed in `udelay.c`, so do
    not include it.
    
    This header was included since commit
    »Add Intel i5000 Memory Controller Hub« (17670866) [1].
    
    [1] http://review.coreboot.org/491
    
    Change-Id: Ie136a1b862b55c9471f9293ed616ce27a1d01a50
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3218
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3f5f6d8368031710d4f5847ff285812fcde54009
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue May 7 20:35:29 2013 +0200

    Drop prototype guarding for romcc
    
    Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1]
    made romcc not choke on function prototypes anymore. This
    allows us to get rid of a lot of ifdefs guarding __ROMCC__ .
    
    [1] http://review.coreboot.org/2424
    
    Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3216
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d654f42e271b2daa17a4daddcb7c9603aa25e018
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed May 8 13:23:14 2013 +0200

    AMD: Reduce stack size from 64 KB to the default of 4 KB
    
    Apply the following commit to all AMD boards.
    
        commit 935850e08293cec1cb27d12358b27285e780566a
        Author: Stefan Reinauer <reinauer@chromium.org>
        Date:   Mon May 6 16:16:03 2013 -0700
    
            asrock/e350m1: reduce default stack size
    
            The stack used on the ASRock E350M1 is significantly less than
            what we currently set (64k per core). In fact, we use about half
            of the default stack size (4k) on core 0 and even less on non
            BSP cores [1]:
    
            $ grep stack coreboot_without_patch_but_monotonic_timer.log
            CPU1: stack_base 002a0000, stack_end 002afff8
            CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes
            CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes
    
            […]
    
            Reviewed-on: http://review.coreboot.org/3209
    
    Please note that AGESA seems to define bigger stack sizes. But
    these seem to be too much too.
    
        $ git grep STACK_SIZE src/vendorcode/amd
        […]
        src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define BSP_STACK_SIZE            16384
        src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE0_STACK_SIZE          16384
        src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE1_STACK_SIZE          4096
        src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:  BSP_STACK_SIZE,
        src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:  CORE0_STACK_SIZE,
        src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:  CORE1_STACK_SIZE,
        […]
    
    The following command was used to create the patch.
    
        $ git grep -l STACK_SIZE src/mainboard/ | xargs sed -i '/STACK_SIZE/,+3d'
    
    Change-Id: I36b95b7a6f190b64d0639fc036ce2fb0253f3fa1
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3217
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3949e3783409ec1ddda25116d06da2a7e16c6c51
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 6 16:56:37 2013 -0700

    Drop CONFIG_AP_CODE_IN_CAR
    
    This option has not been enabled on any board and was considered
    obsolete last time it was touched. If we need the functionality,
    let's fix this in a generic way instead of a K8 specific way.
    This was mostly a speedup hack back in the day.
    
    Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3211
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 648d16679c5cf4f91c9f8b48ee77c6a9ada87523
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 6 18:05:39 2013 -0700

    copy_and_run: drop boot_complete parameter
    
    Since this parameter is not used anymore, drop it from
    all calls to copy_and_run()
    
    Change-Id: Ifba25aff4b448c1511e26313fe35007335aa7f7a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3213
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2a3c10677f354f660a759d47a3b26b1d8818e76c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 6 16:49:56 2013 -0700

    hardwaremain: drop boot_complete parameter
    
    it has been unused since 9 years or so, hence drop it.
    
    Change-Id: I0706feb7b3f2ada8ecb92176a94f6a8df53eaaa1
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3212
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 758076cceb450da4848a8ce944fa679d7403147c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue May 7 12:58:12 2013 -0500

    x86: use asmlinkage macro for smm_handler_t
    
    The smm_handler_t type was added before the introduction
    of the asmlinkage macro. Now that asmlinkage is available
    use it.
    
    Change-Id: I85ec72cf958bf4b77513a85faf6d300c781af603
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3215
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 37f8c3af0e8a7527eacac4646ef19239413b3328
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Mon May 6 15:51:39 2013 -0600

    cbfs_core.c: make cfbs searches even less verbose
    
    The cbfs core code would print out the name of the file it is
    searching for and when it is found would print out the name
    again. This contributes to a lot of unnecessary messages in a
    functioning payload’s output. Change this message to a DEBUG one
    so that it will only be printed when CONFIG_DEBUG_CBFS is enabled.
    
    Change-Id: Ib238ff174bedba8eaaad8d1d452721fcac339b1a
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3208
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ea23a6b23f2e15ed1805918d3b7105582f3789f0
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu May 2 10:34:49 2013 +0200

    src/cpu/amd/agesa/Kconfig: Use tabs instead of spaces for alignment
    
    Some entries still used spaces while others used tabulators[1]. Convert
    spaces to tabs to uniformly use tabs.
    
    ---------------------- 8< -------------- 8< -----------------------------
    For all of the Kconfig* configuration files throughout the source tree,
    the indentation is somewhat different.  Lines under a "config" definition
    are indented with one tab, while help text is indented an additional two
    spaces. [2]
    ---------------------- 8< -------------- 8< -----------------------------
    
    [1] http://en.wikipedia.org/wiki/File:HollerithMachine.CHM.jpg
    [2] http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/CodingStyle?id=HEAD
    
    Change-Id: Iee80ad4a90e95b925afbb0c6adc563fa3a6503cf
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3173
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 703aa978aa6db915fbc7fa42e5ca79cf31f57505
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed May 1 15:55:14 2013 -0500

    x86: harden tsc udelay() function
    
    Since the TSC udelay() function can be used in SMM that means the
    TSC can count up to whatever value. The current loop was not handling
    TSC rollover properly. In most cases this should not matter as the TSC
    typically starts ticking at value 0, and it would take a very long time
    to roll it over. However, it is my understanding that this behavior is
    not guaranteed. Theoretically the TSC could start or be be written to
    with a large value that would cause the rollover.
    
    Change-Id: I2f11a5bc4f27d5543e74f8224811fa91e4a55484
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3171
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit ddddf15ca359e932ed2e61e9a6dcec77ed2d4411
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Apr 23 14:40:23 2013 +0200

    Intel 82801Gx: LPC: Unify I/O APIC setup
    
    Remove local copies of reading and writing I/O APIC registers by
    using already available functions.
    
    This change is similar to
    
        commit db4f875a412e6c41f48a86a79b72465f6cd81635
        Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
        Date:   Tue Jan 31 17:24:12 2012 +0200
    
            IOAPIC: Divide setup_ioapic() in two parts.
    
            Reviewed-on: http://review.coreboot.org/300
    
    and
    
        commit e614353194c712a40aa8444a530b2062876eabe3
        Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
        Date:   Tue Feb 26 17:24:41 2013 +0200
    
            Unify setting 82801a/b/c/d IOAPIC ID
    
            Reviewed-on: http://review.coreboot.org/2532
    
    and uses `io_apic_read()` and `io_apic_write()` too.
    
    As commented by Aaron Durbin, a separate `i82801gx_enable_acpi()` is
    not needed: “The existing code path *in this file* is about enabling
    the io apic.” [1].
    
    [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c
    
    Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3181
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 1b3e176468213747188c8979a505a4dd8b83f0bd
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Apr 23 14:49:41 2013 +0200

    x86 I/O APIC: Dump I/O APIC regs in `ioapic.c`
    
    Some southbridges have code in their `lpc.c` files to dump the
    I/O APIC registers.
    
        printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
        for (i=0; i<3; i++) {
                *ioapic_index = i;
                printk(BIOS_SPEW, "  reg 0x%04x:", i);
                reg32 = *ioapic_data;
                printk(BIOS_SPEW, " 0x%08x\n", reg32);
        }
    
    Add similar code to `src/arch/x86/lib/ioapic.c` so all boards using
    the function `set_ioapic_id()` get the debug feature and the other
    boards can be more easily adapted in follow-up patches.
    
    Change-Id: Ic59c4c2213ed97bdf3798b3dc6e7cecc30e135d8
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3184
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit ac75bc682b2c546ea01d6ad254df7b1a48a9f68f
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Apr 23 14:34:43 2013 +0200

    x86 I/O APIC: Make functions `io_apic_{read,write}()` public
    
    Some LPC initialiation can save some lines of code when being able
    to use the functions `io_apic_read()` and `io_apic_write()`.
    
    As these two functions are now public, remove them from the generic
    driver as otherwise we get a build errors like the following.
    
        […]
        Building roda/rk9; i386: ok, using i386-elf-gcc
        Using payload /srv/jenkins/payloads/seabios/bios.bin.elf
          Creating config file... (blobs, ccache) ok;  Compiling image on 4 cpus in parallel .. FAILED after 12s!
        Log excerpt:
        coreboot-builds/roda_rk9/arch/x86/lib/ramstage.o: In function `io_apic_write':
        /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/arch/x86/lib/ioapic.c:32: multiple definition of `io_apic_write'
        coreboot-builds/roda_rk9/drivers/generic/ioapic/ramstage.o:/srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/drivers/generic/ioapic/ioapic.c:22: first defined here
        collect2: error: ld returned 1 exit status
        make: *** [coreboot-builds/roda_rk9/generated/coreboot_ram.o] Error 1
        make: *** Waiting for unfinished jobs....
        […]
    
    Change-Id: Id600007573ff011576967339cc66e6c883a2ed5a
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3180
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 15c671efb5e6834824569a812dcec7bb5d5ce384
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon May 6 10:52:24 2013 -0500

    boot state: remove drain timers option
    
    Internally there were states that had an attribute to
    indicate that the timers needed to be drained. Now that
    there is a way to block state transitions rely on this
    ability instead of draining timers. The timers will
    drain themselves when a state is blocked.
    
    Change-Id: I59be9a71b2fd5a17310854d2f91c2a8957aafc28
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3205
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0748d305545440ae89034542ea761d39b9aab526
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon May 6 10:50:19 2013 -0500

    boot state: add ability to block state transitions
    
    In order to properly sequence the boot state machine it's
    important that outside code can block the transition from
    one state to the next. When timers are not involved there's
    no reason for any of the existing code to block a state
    transition. However, if there is a timer callback that needs to
    complete by a certain point in the boot sequence it is necessary
    to place a block for the given state.
    
    To that end, 4 new functions are added to provide the API for
    blocking a state.
    1. boot_state_block(boot_state_t state, boot_state_sequence_t seq);
    2. boot_state_unblock(boot_state_t state, boot_state_sequence_t seq);
    3. boot_state_current_block(void);
    4. boot_state_current_unblock(void);
    
    Change-Id: Ieb37050ff652fd85a6b1e0e2f81a1a2807bab8e0
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3204
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 39ecc65158f57af5889c957bba4209e8fa59c0bf
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu May 2 09:42:13 2013 -0500

    haswell: use asmlinkage for assembly-called funcs
    
    When the haswell MP/SMM code was developed it was using a coreboot
    repository that did not contain the asmlinkage macro. Now that the
    asmlinkage macro exists use it.
    
    BUG=None
    BRANCH=None
    TEST=Built and booted.
    
    Change-Id: I662f1b16d1777263b96a427334fff8f98a407755
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3203
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d39c650e0616178fe8451afc1d18f6c98adf7f1c
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon May 6 16:12:20 2013 -0700

    exynos5: select HAVE_MONOTONIC_TIMER
    
    We have the monotonic timer implemented on exynos now, and this
    also enables helpful bootstage prints with timing info.
    
    Change-Id: I3baa4c9d70d4b4d059abd5e05eddcabd5258dbfd
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3210
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 8e73b5d9528401a50254eb968080b814b5418152
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed May 1 15:27:09 2013 -0500

    x86: add TSC_CONSTANT_RATE option
    
    Some boards use the local apic for udelay(), but they also provide
    their own implementation of udelay() for SMM. The reason for using
    the local apic for udelay() in ramstage is to not have to pay the
    penalty of calibrating the TSC frequency. Therefore provide a
    TSC_CONSTANT_RATE option to indicate that TSC calibration is not
    needed. Instead rely on the presence of a tsc_freq_mhz() function
    provided by the cpu/board.  Additionally, assume that if
    TSC_CONSTANT_RATE is selected the udelay() function in SMM will
    be the tsc.
    
    Change-Id: I1629c2fbe3431772b4e80495160584fb6f599e9e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3168
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7cb1ba9a61b244800eb65c08729f75d85a504de3
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed May 1 15:39:28 2013 -0500

    haswell: use tsc for udelay()
    
    Instead of using the local apic timer for udelay() use the tsc.
    That way SMM, romstage, and ramstage all use the same delay
    functionality.
    
    Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3169
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 935850e08293cec1cb27d12358b27285e780566a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 6 16:16:03 2013 -0700

    asrock/e350m1: reduce default stack size
    
    The stack used on the ASRock E350M1 is significantly less than
    what we currently set (64k per core). In fact, we use about half
    of the default stack size (4k) on core 0 and even less on non
    BSP cores [1]:
    
        $ grep stack coreboot_without_patch_but_monotonic_timer.log
        CPU1: stack_base 002a0000, stack_end 002afff8
        CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes
        CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes
    
    Removing the Kconfig variable STACK_SIZE to use the default results
    in the following numbers of stack usage.
    
        $ grep stack coreboot_with_patch.log
        CPU1: stack_base 00287000, stack_end 00287ff8
        CPU1: stack: 00287000 - 00288000, lowest used address 00287da8, stack used: 600 bytes
        CPU0: stack: 00288000 - 00289000, lowest used address 0028875c, stack used: 2212 bytes
    
    [1] http://review.coreboot.org/#/c/3154/
        (comment May 2 10:21 AM)
    
    Change-Id: Ibdb2102c86094fce3787e3b5a162ca8423de205c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3209
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3eddcffe2d9f978081ab2c06cc45ddc473939ded
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed May 1 08:40:13 2013 -0500

    libpayload: make searching for a file less verbose
    
    The cbfs core code would print out all unmatched file
    names when searching for a file. This contributes to a lot
    of unnecessary messages in the boot log. Change this
    message to a DEBUG one so that it will only be printed when
    CONFIG_DEBUG_CBFS is enabled.
    
    Change-Id: I34c747e0d3406351318abf70994dbc0bb3fa6c01
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3164
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Tested-by: build bot (Jenkins)

commit 998d0c6d50cd75a703ae6cb161a406a382cdd8a2
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu May 2 16:47:54 2013 -0700

    exynos5250/snow: deprecate time.h
    
    This re-introduces 2fde966 (http://review.coreboot.org/#/c/3177/)
    which was reverted due to unsatisfied dependencies.
    
    time.h We Hardly Knew Ye.
    
    This deprecates time.h which is currently only used by Exynos5250 and
    Snow. The original idea was to try and unify some of the various timer
    interfaces and has been supplanted by the monotonic timer API.
    
    timer_us() is now obsolete. timer_start() is now mct_start() and
    is exposed in exynos5250/clk.h.
    
    Change-Id: I8e60105629d9da68ed622e89209b3ef6c8e2445b
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3201
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 040f25b73a9e131d18c2f64a6c3b60e695e3d7d6
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri May 3 12:28:11 2013 -0700

    timer.h: add mono_time_diff_microseconds()
    
    The current way to get a simple mono_time difference is:
    1. Declare a rela_time struct
    2. Assign it the value of mono_time_diff(t1, t2)
    3. Get microseconds from it using rela_time_in_microseconds().
    
    This patch adds a simpler method. Now one only needs to call
    mono_time_diff_microseconds(t1, t2) to obtain the same value which
    is produced from the above three steps.
    
    Change-Id: Ibfc9cd211e48e8e60a0a7703bff09cee3250e88b
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3190
    Tested-by: build bot (Jenkins)

commit 0bb875be5e575b6eceb081d1a92da467b87aa96b
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu May 2 14:23:51 2013 -0700

    exynos5/5250: Update timer call sites to use monotonic timer API
    
    This goes thru various call sites where we used timer_us() and updates
    them to use the new monotonic timer API.
    
    udelay() changed substantially and now gracefully handles wraparound.
    
    Change-Id: Ie2cc86a4125cf0de12837fd7d337a11aed25715c
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3176
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit c2f177737bb2ae1836b3badeb90daf6bdcc2134f
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Apr 29 23:05:44 2013 +0200

    Lenovo ThinkPad X60: Clean up `romstage.c`
    
    1. Move comment for console init to correct place.
    2. Start output with capital letter and add full stop at the end.
    3. Add missing »)« at the end of description of GPIO 10.
    4. Use tabulators instead of spaces.
    5. Indent the code automatically using GNU indent [1] with the `-sc`
       switch adding stars in front of comment blocks as the good indent
       manual documents.
    
           $ indent -linux -sc src/mainboard/lenovo/x60/romstage.c
    
       Leave the numbers left aligned as it is more beneficial to be
       able to run indent without adapting the result afterward.
    
    [1] http://www.coreboot.org/Development_Guidelines#Coding_Style
    
    Change-Id: I2fa018ec28ff19d23d68754b565c13a7d7a57355
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3185
    Tested-by: build bot (Jenkins)
    Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ab98cfe110353eb7b9ad5a8ca125f0d6cd69b632
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat May 4 01:54:45 2013 +0200

    Revert "exynos5250/snow: deprecate time.h"
    
    This reverts commit 2fde9668b47e74d1bfad2f1688a4481e6b966d04
    
    Somehow this got merged before its dependencies. 3190 must be merged first, followed by 3176. However 3190 will fail while this patch is in. So the situation can't correct itself.
    
    Reverting this until the other two go in.
    
    Change-Id: I176f37c12711849c96f1889eacad38c00a8142c4
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3195
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit cc76d7e011ead7350c8b7017c401a584e88154e2
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Wed May 1 22:29:13 2013 +0200

    Asus F2A85-M Enable the SD controller for F2A85-M
    
    If the SD controller is "off" hudson.c won't disable that because,
    there is no code for this yet.
    
    The PCI device is still visible and PCI BAR will be allocated
    by Linux. Unfortunately it may happen that the particular address
    is used by non-standard BAR for SPI controller.
    
    Change-Id: Ied7c581727541e2c81b0b1c2b70fd32de0014730
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/3167
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dfb0686f8435d8e637a3ab23bc07b0ef5caef0e9
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Tue Apr 23 15:11:52 2013 -0600

    AMD F15: Fix warning in Proc/CPU/Feature
    
    Fix Warning:
    cpuFeatureLeveling.c:265, GNU Compiler 4 (gcc), Priority: Normal
    cast to pointer from integer of different size [-Wint-to-pointer-cast]
    with an intermediate cast to (intptr_t)
    
    Change-Id: I3bfd2ea1e797632316675338789dabef8f73ba64
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3126
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8187f3d32c7ec85d1cc2228e2e7729ffc80c4b89
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Tue Apr 23 15:02:51 2013 -0600

    AMD F15: Fix warnings in Proc/Common
    
    This fixes 3 warnings in the Proc/Common directory:
    
    AmdS3Save.c:250, GNU Compiler 4 (gcc), Priority: Normal
    AmdS3LateRestore.c:123, GNU Compiler 4 (gcc), Priority: Normal
    cast from pointer to integer of different size [-Wpointer-to-int-cast]
    Fixed with a second cast to (intptr_t)
    
    AmdInitReset.c:153, GNU Compiler 4 (gcc), Priority: Normal
    statement with no effect [-Wunused-value]
    Fixed by commenting the line out as it is in the other families code.
    
    Change-Id: Ib35ec466671712af01568b7c2a18ee138fe883c0
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3125
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a98d3061e9e85be2f924850860e76f07cfc5af37
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Apr 11 12:32:32 2013 +0200

    nvramtool: Use CMOS_SIZE for cmos size
    
    We write CMOS data to 128 byte files, which is a problem
    when using them later-on (eg. as part of a coreboot image)
    where nvramtool assumes them to be 256 byte, and so data
    corruption occurs.
    
    Change-Id: Ibc919c95f6d522866b21fd313ceb023e73d09fb9
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3186
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2fde9668b47e74d1bfad2f1688a4481e6b966d04
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu May 2 16:47:54 2013 -0700

    exynos5250/snow: deprecate time.h
    
    time.h We Hardly Knew Ye.
    
    This deprecates time.h which is currently only used by Exynos5250 and
    Snow. The original idea was to try and unify some of the various timer
    interfaces and has been supplanted by the monotonic timer API.
    
    timer_us() is now obsolete. timer_start() is now mct_start() and
    is exposed in exynos5250/clk.h.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Change-Id: I14ebf75649d101491252c9aafea12f73ccf446b5
    Reviewed-on: http://review.coreboot.org/3177
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 37714f33a6ac922c8e3a8e5761c0c7ac505acad1
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Fri Apr 19 00:56:57 2013 +0200

    crossgcc: update to gcc 4.7.3
    
    Update crossgcc to use gcc 4.7.3
    The resulting coreboot.rom is not runtime tested (any volunteers?).
    
    Drop the texinfo patch, rename the armv7a patch.
    
    Some Linux distributions have moved on to gcc 4.8,
    under certain circumstances this version can't (cross-)compile gcc 4.7.2
    Bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56927
    
    Change-Id: Id8ce5f86c34e1a0900d44dc6ae4e81cb9548ecc2
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/3112
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fe9f0f4734fa9072b1d1aa45dbbdd56ee11c9bf8
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri May 3 08:48:45 2013 +0200

    cpu/amd/agesa/family15tn/Kconfig: Remove unneeded `UDELAY_LAPIC`
    
    Commit
    
        commit 825c78b5da98c7155ff6be3322cdaae0e5a060e8
        Author: David Hubbard <david.c.hubbard+coreboot@gmail.com>
        Date:   Thu May 2 18:06:03 2013 -0600
    
            mainboard/{asus/f2a85-m,amd/thatcher}: move UDELAY_LAPIC
    
            Reviewed-on: http://review.coreboot.org/3178
    
    adds `UDELAY_LAPIC` to `cpu/amd/agesa/family15tn/Kconfig`. This is
    not needed, because since commit
    
        commit e135ac5a7ea69b6edcb89345019212f5de412b1e
        Author: Patrick Georgi <patrick.georgi@secunet.com>
        Date:   Tue Nov 20 11:53:47 2012 +0100
    
            Remove AMD special case for LAPIC based udelay()
    
            Reviewed-on: http://review.coreboot.org/1618
    
    `select UDELAY_LAPIC` is present in `src/cpu/amd/agesa/Kconfig` which
    applies also to AMD Family 15tn.
    
    Therefore remove `select UDELAY_LAPIC` again from
    `cpu/amd/agesa/family15tn/Kconfig`.
    
    Change-Id: I98b783a97c4a1e45ecb29b776cb3d3877bad9c0f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3179
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 5ec69ed884852426e17439263e3678c5dfbc71e7
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu May 2 13:23:08 2013 -0700

    exynos5250: monotonic timer implementation (using MCT)
    
    This implements the new monotonic timer API using the global
    multi-core timer (MCT).
    
    Change-Id: Id56249ff5d3e0f85808f5754954c83c0bc75f1c1
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3175
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 008616247d4f03b47b2eb996029072a21789f3e0
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Apr 28 14:44:08 2013 +0200

    AMD SATA: Correct »them implement« to »then implement« in comments
    
    The following command was used to correct all occurences of this typo.
    
        $ git grep -l "them implem" | xargs sed -i 's/them implem/then implem/'
    
    Change-Id: Iebd4635867d67861aaf4d4d64ca8a67e87833f38
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3145
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ac222273701cc6d648d4362093762124662572c3
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Apr 23 13:00:34 2013 +0200

    Intel Lynx Point: Use 2 << 24 to clarify that I/O APIC ID is 2
    
    Commit »haswell: Add initial support for Haswell platforms« (76c3700f)
    [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using
    `2 << 24`, which is the same value, makes it clear, that the
    I/O APIC ID is 2.
    
    Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID
    is 2« (8c937c7e) [2] is used as a template.
    
    [1] http://review.coreboot.org/2616
    [2] http://review.coreboot.org/3100
    
    Change-Id: I28f9e90856157b4fdd9a1e781472cc4f51d25ece
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3123
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit e62b8e9a8fb08d4afd88ec57414a33b7154aaa67
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Apr 26 17:15:07 2013 +0200

    Kconfig: Capitalize CBMEM in description of `EARLY_CBMEM_INIT`
    
    Capitalizing CBMEM seems to be the official spelling as can be seen
    in the descriptions around the `EARLY_CBMEM_INIT` Kconfig option.
    
    Change-Id: I046a678c3b04ef7e681de46aa137cedc405d546f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3143
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e690eda978690e8c44804fe81f545a87a552685f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Apr 25 08:42:23 2013 -0500

    cbfs: make searching for a file less verbose
    
    The cbfs core code would print out all unmatched file
    names when searching for a file. This contributes to a lot
    of unnecessary messages in the boot log. Change this
    message to a DEBUG one so that it will only be printed when
    CONFIG_DEBUG_CBFS is enabled.
    
    Change-Id: I1e46a4b21d80e5d2f9b511a163def7f5d4e0fb99
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3131
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Tested-by: build bot (Jenkins)

commit 825c78b5da98c7155ff6be3322cdaae0e5a060e8
Author: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Date:   Thu May 2 18:06:03 2013 -0600

    mainboard/{asus/f2a85-m,amd/thatcher}: move UDELAY_LAPIC
    
    Stefan Reinauer suggested 'select UDELAY_LAPIC' did not belong in
    f2a85-m/Kconfig. It got there via copy-paste from thatcher/Kconfig
    so this commit removes the 'select UDELAY_LAPIC' from both and puts
    it in cpu/amd/agesa/family15tn/Kconfig
    
    Since f2a85-m is the only Thatcher board coreboot supports right
    now, this should not break any other boards.
    
    Change-Id: I811b579c31f8d259a237d3a6724ad3b17f3a6c3e
    Signed-off-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
    Reviewed-on: http://review.coreboot.org/3178
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 3f39cd2920ccc3286cda152f7abc08590ae49f66
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Apr 30 16:01:50 2013 -0700

    armv7: invalidate TLB entries as they are added/modified
    
    The old approach was to invalidate the entire TLB every time we set up
    a table entry. This worked because we didn't turn the MMU on until
    after we had set everything up. This patch uses the TLBIMVAA wrapper
    to invalidate each entry as it's added/modified.
    
    Change-Id: I27654a543a2015574d910e15d48b3d3845fdb6d1
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3166
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 5c2025c40f747c383e6106799f06c4a92cd07201
Author: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date:   Tue Apr 23 14:31:55 2013 -0600

    AMD Hudson A55E: Remove GEC firmware blob kconfig prompt
    
    The "gigabit ethernet controller" (GEC) block was added to AMD
    Hudson A55E to integrate ethernet capabilities into an AMD
    southbridge.
    
    The GEC is designed to work with B50610 and B50610M gigabit PHY
    chips from Broadcom.  These parts may not be generally available
    in small quantities for embedded development.
    
    The GEC block requires an opaque firmware blob to function.  The
    GEC blob is controlled by AMD and Broadcom and is not available
    from coreboot.org.
    
    This change removes GEC support from AMD Parmer and AMD Thatcher
    mainboards since these boards do not have the Broadcom PHY.
    
    AMD has requested that the GEC be hidden for Hudson FCH since
    the PHY parts are not generally available.  This Kconfig option
    can make it appear that this is a viable and supported way to
    add Ethernet to an embedded board.  It is possible to use the
    Hudson GEC block with other PHYs, but this requires development
    of a custom GEC blob and a custom Ethernet driver.  A custom GEC
    blob has been developed for a Micrel PHY, but there is no
    accompanying driver.
    
    Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3
    Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3127
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 052942923b2320ee9cb2a1bcc2d2689c179ad4f5
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Apr 30 15:41:13 2013 -0500

    device tree: track init times
    
    With the introduction of a monotonic timer it is possible to
    track the individual times of each device's init() call. Add this
    ability behind a HAVE_MONOTONIC_TIMER option.
    
    Example log messages:
    Root Device init 5 usecs
    CPU_CLUSTER: 0 init 66004 usecs
    PCI: 00:00.0 init 1020 usecs
    PCI: 00:02.0 init 456941 usecs
    PCI: 00:13.0 init 3 usecs
    PCI: 00:14.0 init 3 usecs
    PCI: 00:15.0 init 92 usecs
    PCI: 00:15.1 init 37 usecs
    PCI: 00:15.2 init 36 usecs
    PCI: 00:15.3 init 35 usecs
    PCI: 00:15.4 init 35 usecs
    PCI: 00:15.5 init 36 usecs
    PCI: 00:15.6 init 35 usecs
    PCI: 00:16.0 init 3666 usecs
    PCI: 00:17.0 init 63 usecs
    PCI: 00:1b.0 init 3 usecs
    PCI: 00:1c.0 init 89 usecs
    PCI: 00:1c.1 init 15 usecs
    PCI: 00:1c.2 init 15 usecs
    PCI: 00:1c.3 init 15 usecs
    PCI: 00:1c.4 init 15 usecs
    PCI: 00:1c.5 init 16 usecs
    PCI: 00:1d.0 init 4 usecs
    PCI: 00:1f.0 init 495 usecs
    PCI: 00:1f.2 init 29 usecs
    PCI: 00:1f.3 init 4 usecs
    PCI: 00:1f.6 init 4 usecs
    
    Change-Id: Ibe499848432c7ab20166ab10d6dfb07db03eab01
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3162
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit c0466d46b7ea511f102eb6e57da59d95bf4ef95f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 30 10:11:30 2013 -0700

    ARMV7: add a function to disable MMU entries
    
    It is useful to be able to lock out certain address ranges,
    NULL being the most important example.
    
    void mmu_disable_range(unsigned long start_mb, unsigned long size_mb)
    
    will allow us to lock out selected virtual addresses on MiB boundaries.
    As in other ARM mmu functions, the addresses and quantities are in units
    of MiB.
    
    Change-Id: If516ce955ee2d12c5a409f25acbb5a4b424f699b
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3160
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 043b823a736d101da46a120cfa883c5c48e3ab81
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Apr 30 16:14:35 2013 +0800

    Google/Snow: Revise bootblock initialization.
    
    It's fine to always start timer even in suspend/resume mode, so we can
    move the timer_start() back to the very beginning of boot procedure.
    That provides more precise boot time information.
    
    With that timer change, the wake up state test procedure can be simplified.
    
    Verified by building and booting firmware image on Google/Snow successfully,
    and then suspend-resume without problem (suspend_stress_test).
    
    Change-Id: I0d739650dbff4eb3a75acbbf1e4356f2569b487d
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3151
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c99ae5d9a93212cbecff0d10a1710b68f26e966e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Apr 30 12:20:53 2013 -0700

    armv7: add wrapper for tlbimvaa
    
    This adds an inline wrapper for the TLBIMVAA instruction (invalidate
    unified TLB by MVA, all address space identifiers).
    
    Change-Id: Ibcd289ecedaba8586ade26e36c177ff1fcaf91d3
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3161
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 0004c0deec8d60cf952426746e2d9519f6de38d6
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Apr 30 16:11:32 2013 +0800

    Google/Snow: Remove duplicated SPI1 initialization in bootblock.
    
    The firmware media source (SPI1) is already initialized by Exynos iROM.
    There is no need to do it again.
    
    Verified by building and booting Google/Snow successfully.
    
    Change-Id: I89390506aa825397c0d7e52ad7503f1cb808f7db
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3147
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8fc41e1b84301e76921730caa4e6b8e8bf27cc35
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Apr 29 23:22:01 2013 -0500

    boot state: run timers on state entry
    
    When TIMER_QUEUE is configured on call the timer callbacks on
    entry into a state but before its entry callbacks. In addition
    provide a barrier to the following states so that timers are drained
    before proceeding. This allows for blocking state traversal for key
    components of boot.
    	BS_OS_RESUME
    	BS_WRITE_TABLES
    	BS_PAYLOAD_LOAD
    	BS_PAYLOAD_BOOT
    
    Future functionality consists of evaluating the timer callbacks within
    the device tree. One example is dev_initialize() as that seems state
    seems to take 90% of the boot time. The timer callbacks could then be
    ran in a more granular manner.
    
    Change-Id: Idb549ea17c5ec38eb57b4f6f366a1c2183f4a6dd
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3159
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 340ca91f18a448e09973341f60bb6f46102d2410
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Apr 30 09:58:12 2013 -0500

    coreboot: add timer queue implementation
    
    A timer queue provides the mechanism for calling functions
    in the future by way of a callback. It utilizes the MONOTONIC_TIMER
    to track time through the boot. The implementation is a min-heap
    for keeping track of the next-to-expire callback.
    
    Change-Id: Ia56bab8444cd6177b051752342f53b53d5f6afc1
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3158
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6b0fb0dc3c1cb89af52224a1610daf7b9e943aa6
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Apr 26 20:54:16 2013 -0500

    boot state: track times for each state
    
    When the MONOTONIC_TIMER is available track the entry, run, and exit
    times for each state. It should be noted that the times for states that
    vector to OS or a payload do not have their times reported.
    
    Change-Id: I6af23fe011609e0b1e019f35ee40f1fbebd59c9d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3156
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e850164bac08a5b3b4cd09f587775e68ad1b40c2
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Apr 29 22:22:55 2013 -0500

    tsc: provide monotonic timer
    
    Implement the timer_monotonic_get() using the TSC.
    
    Change-Id: I5118da6fb9bccc75d2ce012317612e0ab20a2cac
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3155
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fd8291c9d438917e334f4211fb1142b6a7bb7e32
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Apr 29 17:18:49 2013 -0500

    lapic: monotonic time implementation
    
    Implement the timer_monotonic_get() functionality based off of
    the local apic timer.
    
    Change-Id: I1aa1ff64d15a3056d6abd1372be13da682c5ee2e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3154
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c46cc6f149c42653344d6e9f3656a4212fc46cef
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Apr 29 16:57:10 2013 -0500

    haswell: 24MHz monotonic time implementation
    
    Haswell ULT devices have a 24MHz package-level counter. Use
    this counter to provide a timer_monotonic_get() implementation.
    
    Change-Id: Ic79843fcbfbbb6462ee5ebd12b39502307750dbb
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3153
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a421791db815fb2e2da9b1ce4bec78c97665b62f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Apr 29 22:31:51 2013 -0500

    coreboot: introduce monotonic timer API
    
    The notion of a monotonic timer is introduced. Along with it
    are helper functions and other types for comparing times. This
    is just the framework where it is the responsibility of the
    chipset/board to provide the implementation of timer_monotonic_get().
    
    The reason structs are used instead of native types is to allow
    for future changes to the data structure without chaning all the
    call sites.
    
    Change-Id: Ie56b9ab9dedb0da69dea86ef87ca744004eb1ae3
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3152
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 001de1aeb00e604e4664659b831ca99d1a940d57
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 24 22:59:45 2013 -0500

    boot state: rebalance payload load vs actual boot
    
    The notion of loading a payload in the current boot state
    machine isn't actually loading the payload. The reason is
    that cbfs is just walked to find the payload. The actual
    loading and booting were occuring in selfboot(). Change this
    balance so that loading occurs in one function and actual
    booting happens in another. This allows for ample opportunity
    to delay work until just before booting.
    
    Change-Id: Ic91ed6050fc5d8bb90c8c33a44eea3b1ec84e32d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3139
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bebf66909a11201a1bbfbdf7f1af40285d76a457
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 24 20:59:43 2013 -0500

    x86: use boot state callbacks to disable rom cache
    
    On x86 systems there is a concept of cachings the ROM. However,
    the typical policy is that the boot cpu is the only one with
    it enabled. In order to ensure the MTRRs are the same across cores
    the rom cache needs to be disabled prior to OS resume or boot handoff.
    Therefore, utilize the boot state callbacks to schedule the disabling
    of the ROM cache at the ramstage exit points.
    
    Change-Id: I4da5886d9f1cf4c6af2f09bb909f0d0f0faa4e62
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3138
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 243aa44b74935cfc969106dbbe2420ee4a2c39b2
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 24 17:31:49 2013 -0500

    boot: remove cbmem_post_handling()
    
    The cbmem_post_handling() function was implemented by 2
    chipsets in order to save memory configuration in flash. Convert
    both of these chipsets to use the boot state machine callbacks
    to perform the saving of the memory configuration.
    
    Change-Id: I697e5c946281b85a71d8533437802d7913135af3
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3137
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 40131cfa46bc195ad3bdf2ce9b9af67dcbfd71ca
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 24 16:39:08 2013 -0500

    cbmem: use boot state machine
    
    There were previously 2 functions, init_cbmem_pre_device() and
    init_cbmem_post_device(), where the 2 cbmem implementations
    implemented one or the other. These 2 functions are no longer
    needed to be called in the boot flow once the boot state callbacks
    are utilized.
    
    Change-Id: Ida71f1187bdcc640ae600705ddb3517e1410a80d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3136
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4dd87fb2d852a61fd1677dd81e0a5573e9023eb1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 24 16:28:52 2013 -0500

    coverage: use boot state callbacks
    
    Utilize the static boot state callback scheduling to initialize
    and tear down the coverage infrastructure at the appropriate points.
    The coverage initialization is performed at BS_PRE_DEVICE which is the
    earliest point a callback can be called. The tear down occurs at the
    2 exit points of ramstage: OS resume and payload boot.
    
    Change-Id: Ie5ee51268e1f473f98fa517710a266e38dc01b6d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3135
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0a6c20a2a3bc16aa12b04dd3db1d1260777edf0e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 24 22:33:08 2013 -0500

    acpi: split resume check and actual resume code
    
    It's helpful to provide a distinct state that affirmatively
    describes that OS resume will occur. The previous code included
    the check and the actual resuming in one function. Because of this
    grouping one had to annotate the innards of the ACPI resume
    path to perform specific actions before OS resume. By providing
    a distinct state in the boot state machine the necessary actions
    can be scheduled accordingly without modifying the ACPI code.
    
    Change-Id: I8b00aacaf820cbfbb21cb851c422a143371878bd
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3134
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a4feddf897023b37cfac2af529e787504849f985
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 24 16:12:52 2013 -0500

    boot state: schedule static callbacks
    
    Many of the boot state callbacks can be scheduled at compile time.
    Therefore, provide a way for a compilation unit to inform the
    boot state machine when its callbacks should be called. Each C
    module can export the callbacks and their scheduling requirements
    without changing the shared boot flow code.
    
    Change-Id: Ibc4cea4bd5ad45b2149c2d4aa91cbea652ed93ed
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3133
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7e35efa83cdd6240e4f9282cc4d2703c40d472d5
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 24 15:14:01 2013 -0500

    ramstage: introduce boot state machine
    
    The boot flow currently has a fixed ordering. The ordering
    is dictated by the device tree and on x86 the PCI device ordering
    for when actions are performed. Many of the new machines and
    configurations have dependencies that do not follow the device
    ordering.
    
    In order to be more flexible the concept of a boot state machine
    is introduced. At the boundaries (entry and exit) of each state there
    is opportunity to run callbacks. This ability allows one to schedule
    actions to be performed without adding board-specific code to
    the shared boot flow.
    
    Change-Id: I757f406c97445f6d9b69c003bb9610b16b132aa6
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3132
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e1be5ae2f485989f88ae9af92a97e0577b033155
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Apr 29 13:53:41 2013 -0500

    rmodule: put all code/data bits in one section
    
    While debugging a crash it was discovered that ld was inserting
    address space for sections that were empty depending on section
    address boundaries. This led to the assumption breaking down that
    on-disk payload (code/data bits) was contiguous with the address
    space. When that assumption breaks down relocation updates change
    the wrong memory. Fix this by making the rmodule.ld linker script
    put all code/data bits into a payload section.
    
    Change-Id: Ib5df7941bbd64662090136e49d15a570a1c3e041
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3149
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit ac4b00e230a7f0dfa308d45a7b6034e96a243ab0
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Apr 26 11:58:35 2013 -0500

    string: Add STRINGIFY macro
    
    STRINGIFY makes a string from a token. It is generally useful.
    Even though STRINGIFY is not defined to be in the C library it's
    placed in string.h because it does make a string.
    
    Change-Id: I368e14792a90d1fdce2a3d4d7a48b5d400623160
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3144
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 032dd14514e72777475c3e39395486627846b7c9
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Apr 30 15:31:48 2013 +0800

    Google/Snow: Remove unnecessary serial console init code.
    
    The "console_init" does initialize UART driver (which will setup peripheral and
    pinmux) and print starting message. Duplicated initialization can be removed.
    
    Also, console_init (from console.c) is always linked to bootblock (and will do
    nothing if CONFIG_EARLY_CONSOLE is not defined) so it's safe to remove #ifdef.
    
    Verified by building and booting on Google/Snow, with and without
    CONFIG_EARLY_CONSOLE.
    
    Change-Id: I0c6b4d4eb1a4e81af0f65bcb032978dfb945c63d
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3150
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4560ca5003fe38a066616e8de1a8a414284750fd
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Fri Apr 26 12:21:41 2013 +0200

    Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support.
    
    Enable `EARLY_CBMEM_INIT` for CBMEM console support by looking how
    other boards do this.
    
    This commit is tested by enabling the CBMEM console (`CONSOLE_CBMEM` in
    Kconfig) and then in GRUB 2 (as a payload) with the cbmemc command from
    the cbmemc module and in userspace with ./cbmem -c. Both worked.
    
    Change-Id: I34618a55ded7292a411bc232eb76267eec17d91e
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3142
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit bf92b19b2a234d63d88fea6bd55ad83361e18574
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Apr 29 22:11:22 2013 +0800

    Google/Snow: Temporary fix for resume failure.
    
    The DDR3 memory initialization (with "mem_reset" set on normal boot) will cause
    resume to be unstable, especially when X is running. System may show X screen
    for few seconds, then crash randomly and unable to recover - although text
    console may still work for a while.  Probably caused by corrupted memory pages.
    
    'mem_reset' (which refers to RESET# in DDR3 spec) should be enabled according
    to DDR3 spec. But it seems that on Exynos 5, memory can be initialized without
    setting mem_reset for both normal boot and resume - at least no known failure
    cases are found yet.  So this can be a temporary workaround.
    
    Verified by booting a Google/Snow device with X Window and ChromeOS, entering
    browser session with fancy web pages, closing LID to suspend for 5 seconds, then
    re-opening to resume.  Suspend/resume worked as expected.
    
    Also tried the "suspend_stress_test" with X running and finished 100 iterations
    of suspend/resume test without failure.
    
    Change-Id: I7185b362ce8b545fe77b35a552245736c89d465e
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3148
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3f73eec4d3ea2bfdbece083dc0b8721e458b46fb
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Apr 25 19:49:40 2013 +0800

    Google/Snow: Enable suspend/resume.
    
    Add the suspend/resume feature into bootblock and romstage.
    
    Note, resuming with X and touchpad driver may be still unstable.
    
    Verified by building and booting successfully on Google/Snow, and then executing
    the "suspend_stress_test" in text mode ("stop ui; suspend_stress_test") in
    Chromium OS, passed at least 20 iterations.
    
    Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3102
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 31039e315c78b1b8a2cbef108ec4c07cb95c5e60
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Apr 25 19:30:19 2013 +0800

    google/snow: Revise romstage initialization code.
    
    Move board setup procedure to snow_setup_* functions, and Snow board-specific
    (wakeup) code to snow_* for better function names and comments.
    
    Verified by successfully building and booting on Google/Snow.
    
    Change-Id: I2942d75064135093eeb1c1da188a005fd255111d
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3130
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 526a46ed7e4feb9e2cb02dffccbf40182c8cc014
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Apr 23 13:00:34 2013 +0200

    Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2
    
    Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used
    `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which
    is the same value, makes it clear, that the I/O APIC ID is 2.
    
    Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID
    is 2« (8c937c7e) [2] is used as a template.
    
    [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f5560015ab9905f1ccc2e08c73e0
    [2] http://review.coreboot.org/3100
    
    Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3122
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dfad17de0293a56f68626ce47bfc14300f15e15c
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Apr 25 18:00:58 2013 -0700

    exynos5250: uncomment $(INTERMEDIATE)
    
    This makes the intermediate rule visible so BL1 gets automatically
    placed in the final image.
    
    Change-Id: Iffb0268e5bbcbe135f2d39863ed64fa302409a22
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3141
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 64a69e8e4d942b08732e77fb82b0ea364eb2f398
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 2 17:48:49 2013 -0800

    armv7: invoke intermediate build rules
    
    This adds $$(INTERMEDIATE) as a pre-requisite for coreboot.rom on
    armv7. It is modeled after the $(obj)/coreboot.rom rule for x86.
    
    Change-Id: I483a88035fa2288829b6e042e51ef932c8c4f23c
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2095
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bd7f5f64924353add8a2508eac65b8fbb77d0ed4
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Apr 25 17:38:55 2013 +0800

    google/snow: Add "wakeup" module for suspend/resume.
    
    The "wakeup" procedure will be shared by bootblock and romstage for different
    types of resume processes.
    
    Note, this commit does not include changes in romstage/bootblock to enable
    suspend/resume feature. Simply adding functions to handle suspend/resume.
    
    Verified by successfully building and booting Google/Snow firmware image.
    
    Change-Id: I17a256afb99f2f8b5e0eac3393cdf6959b239341
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3129
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 55c753d3a948fc06d8ccbc3cef678ef2e71f616f
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Apr 25 16:14:19 2013 +0800

    arm/exynos: Allow DRAM controller to be initialized without clearing RAM content.
    
    To support suspend/resume, PHY control must be reset only on normal boot
    path.  So add a new param "mem_reset" to specify that.
    
    Verified to boot successfully on Google/Snow.
    
    Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3128
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 175ad4aa6eca2d7f884745959bd175b37c5ffc31
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Mon Apr 15 17:58:57 2013 +0800

    AMD Thatcher: ConnectorTypeDP supports both DP and HDMI
    
    It seems that ConnectorTypeDP in DdiList supports both DP and HDMI monitors.
    I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter.
    Video and audio are OK. Hot plugging is also supported.
    
    This commit partially reverts commit >AMD Thatcher: Fix PCIE link issues< (7f23aeb0) [1].
    
    [1] http://review.coreboot.org/3011
    
    Change-Id: I23cf1c69a8274f47daf56f1a12aafd88bad4a128
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3088
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2810afa57de26871c99e1c5bb7b3c2fbdcaf4f98
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Apr 18 18:09:24 2013 -0700

    GOOGLE/SNOW: get graphics working
    
    This adds support for display bring-up on Snow. It
    includes framebuffer initialization and LCD enable functions.
    
    Change-Id: I16e711c97e9d02c916824f621e2313297448732b
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3116
    Tested-by: build bot (Jenkins)

commit 2c88cc0696be2b01ebd4df6f7593d8658c8fe419
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Mar 30 12:04:23 2013 +0100

    Intel microcode: Return when `microcode_updates` is `NULL`
    
    Add a safety check in function `intel_update_microcode` to return when
    accidentally `NULL` is passed as `microcode_updates`, which would lead
    to a null pointer dereference later on.
    
        for (c = microcode_updates; m->hdrver; m = (const struct microcode *)c) {
    
    While at it, use `return NULL` for clarity in function
    `intel_microcode_find` and include the header file `stddef.h`. for it.
    
    The review of this patch had some more discussion on adding more
    comments and more detailed error messages. But this should be done in
    a separate patch.
    
    For clarity here some history, on how this was found and what caused
    the discussion and confusion.
    
    Originally when Vladimir made this improvement, selecting
    `CPU_MICROCODE_IN_CBFS` in Kconfig but not having the microcode blob
    `cpu_microcode_blob.bin` in CBFS resulted in a null pointer dereference
    later on causing a crash.
    
        for (c = microcode_updates; m->hdrver; m = (const struct microcode *)c) {
    
    Vladimir fixed this by returning if `microcode_updates` is `NULL`,
    that means no file is found and successfully tested this on his
    Lenovo X201.
    
    When pushing the patch to Gerrit for review, the code was rewritten
    though by Aaron in commit »intel microcode: split up microcode loading
    stages« (98ffb426) [1], which also returns when no file is found. So
    the other parts of the code were checked and the safety check as
    described above is added.
    
    [1] http://review.coreboot.org/2778
    
    Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2990
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit aee444f453f38e53f3e2ac54b560707616767869
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Apr 22 16:03:11 2013 -0700

    exynos5250: ungate the product ID register
    
    This makes sure that the product ID (PRO_ID) register can be read
    when the OS kernel is figuring out what kind of CPU it's running on.
    
    For historical reference, the original U-Boot code seems to have
    worked basically by accident here. The hardware has a quirk where by
    reading the value before gating the IP block keeps the value
    persistent. U-Boot reads the chip ID early on to distinguish between
    chip family, but we do not mix code the same way so we do not read
    the chip ID. Since the value has been read before the clock gating
    happens, the value remains available for the kernel to use during the
    decompression stage. We don't want to rely on that behavior when using
    coreboot. Instead the kernel should gate unused IPs.
    
    (credit to Gabe for finding symptom in the kernel)
    
    Change-Id: Iaa21e6e718b9000b5558f568020f393779fd208e
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3121
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit e8a91347b182281f18c969229f02e07102e21898
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Apr 22 10:46:53 2013 -0700

    GOOGLE/SNOW: fix stupid paren error
    
    This simple error led to corrupted graphics.
    How annoying.
    
    Change-Id: I2295c0df0f1d16014a603dc5d66bd4d72f3fb7c9
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3120
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit c0c620e74ab4578ac8bd8ca80c7265fc4c62a37c
Author: Frank Rysanek <Frantisek.Rysanek@post.cz>
Date:   Fri Apr 5 10:44:10 2013 +0200

    superiotool: add CR dump for W83627UHG = NCT6627UD
    
    This commit adds "register dump capability" to
    superiotool for a specific chip by Winbond/Nuvoton:
    the W83627UHG   AKA   NCT6627UD  (same chip, different package).
    In other words, it fills in the "CR map" definitions in winbond.c,
    which so far have been void for this chip.
    -
    superiotool r4.0-3976-g190011e
    Found Winbond W83627UHG = NCT6627UD (id=0xa2, rev=0x32) at 0x2e
    Register dump:
    idx 02 20 21 22 23 24 25 26  27 28 29 2a 2b 2c 2d 2e  2f
    val ff a2 32 ff f0 44 00 00  ff 00 00 00 00 03 00 00  ff
    def 00 a2 NA ff f0 MM 00 MM  RR 00 00 00 00 02 00 00  00
    LDN 0x00 (Floppy)
    idx 30 60 61 70 74 f0 f1 f2  f4 f5
    val 00 00 00 00 02 8e 00 ff  00 00
    def 01 03 f0 06 02 8e 00 ff  00 00
    LDN 0x01 (Parallel port)
    idx 30 60 61 70 74 f0
    val 00 03 78 0c 04 3f
    def 01 03 78 07 04 3f
    LDN 0x02 (UART A)
    idx 30 60 61 70 f0
    val 01 03 f8 04 00
    def 01 03 f8 04 00
    LDN 0x03 (UART B)
    idx 30 60 61 70 f0 f1
    val 01 02 f8 03 00 44
    def 01 02 f8 03 00 00
    LDN 0x05 (Keyboard)
    idx 30 60 61 62 63 70 72 f0
    val 01 00 60 00 64 01 0c 82
    def 01 00 60 00 64 01 0c 83
    LDN 0x06 (UART C)
    idx 30 60 61 70 f0
    val 01 03 e8 05 80
    def 01 03 e0 04 00
    LDN 0x07 (GPIO 3, GPIO 4)
    idx 30 e0 e1 e2 e3 e4 e5 e6  e7
    val 04 ff ff ff ff ff ff ff  ff
    def 00 ff 00 00 00 ff 00 00  00
    LDN 0x08 (WDTO#, PLED, GPIO 5,6 & GPIO Base Address)
    idx 30 60 61 e0 e1 e2 e3 e4  e5 e6 e7 f5 f6 f7
    val 01 00 00 ff ff ff ff ff  ff ff ff 02 00 00
    def 02 00 00 ff 00 00 00 ff  1f 00 00 00 00 00
    LDN 0x09 (GPIO 1, GPIO 2 and SUSLED)
    idx 30 e0 e1 e2 e3 e4 e5 e6  e7 f3
    val 02 ff ff ff ff 00 ff 00  00 00
    def 00 ff 00 00 00 ff 00 00  00 00
    LDN 0x0a (ACPI)
    idx 30 70 e0 e1 e2 e3 e4 e5  e6 e7 e8 e9 f2 f3 f4 f6  f7 fe
    val 01 00 01 00 0a 00 00 00  0c 00 09 00 01 00 00 00  00 00
    def 00 00 01 00 ff 08 00 00  1c 00 RR RR 3e 00 00 00  00 00
    LDN 0x0b (Hardware monitor)
    idx 30 60 61 70 f0 f1 f2
    val 01 02 48 00 81 ff 81
    def 00 00 00 00 RR RR 00
    LDN 0x0c (PECI, SST)
    idx e0 e1 e2 e3 e4 e5 e6 e7  e8 f1 f2 f3 fe ff
    val 00 48 48 48 48 00 00 00  00 4c 50 10 23 5a
    def 00 48 48 48 48 00 RR RR  00 48 50 10 23 5a
    LDN 0x0d (UART D)
    idx 30 60 61 70 f0
    val 00 00 00 00 00
    def 00 02 e0 03 00
    LDN 0x0e (UART E)
    idx 30 60 61 70 f0
    val 00 00 00 00 80
    def 00 03 e8 04 00
    LDN 0x0f (UART F)
    idx 30 60 61 70 f0
    val 01 02 38 0a 00
    def 00 02 e8 03 00
    
    Change-Id: I834f8767b29f3148f353004edb22cfd7db5ddd56
    Signed-off-by: Frank Rysanek <Frantisek.Rysanek@post.cz>
    Reviewed-on: http://review.coreboot.org/3027
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 69743962617b9de1a0263dc372bd9116671b5025
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Apr 19 10:05:57 2013 +0200

    AMD SB800 based boards: Use `#include <sb_cimx.h>` instead of `"sb_cimx.h"`
    
    Due to
    
        $ more src/southbridge/amd/cimx/sb800/Makefile.inc
        […]
        romstage-y += cfg.c
        romstage-y += early.c
        romstage-y += smbus.c
    
        ramstage-y += cfg.c
        ramstage-y += late.c
        […]
    
    `src/southbridge/amd/cimx/sb800/` is passed with the switch `-I` to
    the compiler, where it is also going to find the header file
    `sb_cimx.h`. Therefore use `#include <sb_cimx>` everywhere, which is
    what some AMD SB800 based boards already do.
    
    The only effect is, that the compiler will not needlessly look into
    directories which do not contain the header file [1].
    
    The following command was used for the replacement.
    
        $ git grep -l sb_cimx.h src/mainboard/ | xargs sed -i 's/#include "sb_cimx.h"/#include <sb_cimx.h>/'
    
    [1] http://gcc.gnu.org/onlinedocs/cpp/Search-Path.html
    
    Change-Id: I96ab34bac1524e6c38c85dfe9d99cb6ef55e6d7c
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3118
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 642b1db7336d4770d882684e42157103f3f38b19
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Apr 18 18:01:34 2013 -0700

    Eliminate use of pointers in coreboot table
    
    Because pointers can be 32bit or 64bit big,
    using them in the coreboot table requires the
    OS and the firmware to operate in the same mode
    which is not always the case. Hence, use 64bit
    for all pointers stored in the coreboot table.
    Guess we'll have to fix this up once we port to
    the first 128bit machines.
    
    Change-Id: I46fc1dad530e5230986f7aa5740595428ede4f93
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3115
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 8d5bc9f7726ac70e1c1a4f293827d67628650824
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Apr 18 13:46:00 2013 -0700

    google/snow: disable unused USB3.0 PLL to save power
    
    This PLL is unused and can be disabled to save about 250mW.
    
    Change-Id: I1be37304d6ea5ff78696e05ad1023ce3c57f636c
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3109
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 95399327193f9ae23b6cd323cac6a0383c269865
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Apr 18 17:27:07 2013 -0700

    exynos5: eliminate lcd_base variable
    
    The original imported code used "lcdbase" and "lcd_base" which quite
    predictably caused confusion and bugs. Let's put an end to this little
    bit of insanity.
    
    Change-Id: I4f995482cfbff5f23bb296a1e6d35beccf5f8a91
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3114
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit ec10ce8971221463314bf1f88e054e1d399bd7a9
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Apr 18 16:45:47 2013 -0700

    google/snow: Minor clean-ups for display setup code in ramstage
    
    This just cleans up a few areas:
    - Removed an unnecessary delay from exynos_dp_bridge_setup()
    - The delay at the end of exynos_dp_bridge_init() is necessary, so
      removed the comment suggesting that it might not be.
    - Simplified exynos_dp_hotplug
    
    Change-Id: I44150f5ef3958e333985440c1022b4f1544a93aa
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3113
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 954d25484b0f4d4881c1b6d5662c587c85c920a2
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Apr 18 13:49:57 2013 -0700

    google/snow: enable clock gating to save power
    
    This enables clock gating to save power on unused IPs.
    
    Change-Id: I9ab2a2535ebb91bb4110390a6f055a67146bdbf9
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3110
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8a275c1810ecd1aa2cec543c14696313f379a9ee
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Mon Apr 15 19:10:24 2013 +0800

    AMD Parmer: change DdiList to ConnectorTypeDP to support DP and HDMI
    
    This patch is based on >>AMD Thatcher: ConnectorTypeDP supports both DP and HDMI<< (I23cf1c6) [1]
    I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter.
    Video and audio are OK. Hot plugging is also supported.
    
    [1] http://review.coreboot.org/#/c/3088/
    
    Change-Id: I291beff43609ecb68ece24939f2dbc7c08dd0374
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3090
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d83c117e86acf21f179495f7a607f9a2fd9349a2
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Apr 18 16:10:29 2013 -0700

    exynos5250: get xres and yres out of the device tree and into the panel descriptor
    
    We neglected to copy xres and yres out; now we do.
    
    Change-Id: Icc4a8eb35799d156b11274f71bcfb4a1d10e01e3
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3111
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 34240b06d8c5d6cc9068279e627ac4d1ebca625b
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Apr 18 15:19:40 2013 -0700

    [3/3] google/snow: enable TMU
    
    This enables the thermal management unit (TMU) on Snow.
    
    Change-Id: Idd76af40bf0a5408baf61ef2665fd52ae4e260ba
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3108
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit cd14ed71bb25bf04ea450bdbd02805be5f9b1941
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Apr 18 14:21:15 2013 -0700

    [2/3] exynos5: modify thermal management unit code for coreboot
    
    This updates the Exynos TMU code for coreboot:
    - Remove dependency on device tree
    - Add Makefile entries
    
    Change-Id: I55e1b624d7c7b695b1253ec55f6ae3de8dc671bc
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3107
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 90a70093b1ca20781b7a92dd04500881a94539b2
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Apr 18 14:01:45 2013 -0700

    [1/3] exynos5: import thermal management unit code
    
    This simply imports the Exynos TMU driver from u-boot. It is not
    built and thus should not break anything.
    
    Change-Id: I7861132fbf97f864e4250ffbda1ef3843f296ddc
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3106
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit b9e6e1ab35c54ed5bd32a2f25a86f73c46d1acb3
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Apr 18 15:04:43 2013 -0700

    exynos5: move power_enable_hw_thermal_trip() prototype
    
    This moves the prototype for power_enable_hw_thermal_trip() to
    a generic location so it can be used by generalized thermal
    management code. The implementation will still be CPU-specific.
    
    Change-Id: Iae449cb8c72c8441dedaf65b73db9898b4730cef
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3105
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 45988dab6bfbc480443979081a3260b7bce04fd8
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Mar 30 02:02:13 2013 +0100

    spkmodem console
    
    Change-Id: Ie497e4c8da05001ffe67c4a541bd24aa859ac0e2
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/2987
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8a6f7a77f3ab169480b8d22caf1a8d70e3188c62
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Apr 17 18:21:09 2013 -0600

    AMD/SB800: Define the GPP PCIe lane distribution
    
    Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't
    distribute the 4 GPP PCIe lanes amongst the enabled PCIe ports.
    This fix was verified by openvoid on a AsRock E350M1 motherboard.
    
    Change-Id: I0116c5f518e0d000be609013446e53da4112f586
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3104
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6ceed0929d1e11c9d8807427750bb6e4f14806fd
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Apr 8 16:55:47 2013 -0700

    libpayload: Don't sneak in compiler includes
    
    The way we got to include the compiler includes was kind of whacky.
    Instead of mixing in potentially problematic headers, make libpayload
    self-contained by adding some missing header files. Also clean up
    conflicting definitions of size_t throughout the tree.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I0ad1194de1a00b7133c5477c00eb167d63a2ee85
    Reviewed-on: https://gerrit.chromium.org/gerrit/47608
    Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3058
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ba7ed4b6a1965692057710d61eacde14b2b58424
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Mar 29 13:33:39 2013 -0600

    AMD Fam14: Split out the AMD Fam14 DSDT
    
    Same splitting as done on Persimmon and ASRock.
    Moving common DSDT code to common areas and adding
    new files as necessary.  Boards updated are:
    	Inagua
    	Union-Station
    	South-Station
    
    Change-Id: I8c9eea62996b41cea23a9c16858c4249197f6216
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3051
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4b213a8d1fd02061c1e879ff98167bcb47f13bd2
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Thu Mar 28 14:24:39 2013 +0100

    Intel i945: ACPI: Add _OSC method
    
    Add the ACPI Operating System Capabilities Method and let the
    operation system control everything.
    
    Commit »AMD Fam14 DSDT: Add OSC method« (00a0e76b) [1] is used as
    a template.
    
    The Lenovo X60 [2] running the Parabola GNU/Linux distribution [3] is
    used for testing.
    
    Before that change:
    
        $ dmesg | egrep -e OSC -e ASPM
        [    0.108036] pci_root PNP0A08:00: ACPI _OSC support notification failed, disabling PCIe ASPM
        [    0.108040] pci_root PNP0A08:00: Unable to request _OSC control (_OSC support mask: 0x08)
        [    0.118089] ACPI _OSC control for PCIe not granted, disabling ASPM
        [   16.874569] e1000e 0000:01:00.0: Disabling ASPM L0s L1
    
    With that change:
    
        $ dmesg | egrep -e OSC -e ASPM
        [    0.107962] pci_root PNP0A08:00: Requesting ACPI _OSC control (0x1d)
        [    0.108003] pci_root PNP0A08:00: ACPI _OSC control (0x1d) granted
        [    0.111052] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'
        [   17.537970] e1000e 0000:01:00.0: Disabling ASPM L0s L1
    
    [1] http://review.coreboot.org/2738
    [2] http://www.coreboot.org/Lenovo_x60x
    [3] https://parabolagnulinux.org/
    
    Change-Id: I1caffa44eea447d553c01caaf431f2db241ea5ea
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2938
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ab348528b58e987994eb783a7622404515a18cd8
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Apr 8 16:43:25 2013 -0700

    ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOT
    
    This used to contain the path for the EC include files, but
    those files are included in coreboot now.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I4fce9831c5e21b0a69a6295dbda2580e1ca83369
    Reviewed-on: https://gerrit.chromium.org/gerrit/47606
    Reviewed-by: Randall Spangler <rspangler@chromium.org>
    Commit-Queue: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3057
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1fb11d105b4cc0d424884a08814f65e73d36504a
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Apr 12 15:11:05 2013 -0700

    armv7/exynos5250: Deprecate sdelay in favor of udelay
    
    This gets rid of the clock-tick based sdelay in favor of udelay().
    udelay() is more consistent and easier to work with, and this allows
    us to carry one less variation of timers (and headers and sources...).
    
    Every 1 unit in the sdelay() argument was assumed to cause a delay of
    2 clock ticks (@1.7GHz). So the conversion factor is roughly:
    sdelay(N) = udelay(((N * 2) / 1.7 * 10^9) * 10^6)
              = udelay((N * 2) / (1.7 * 10^3))
    
    The sdelay() periods used were:
    sdelay(100) --> udelay(1)
    sdelay(0x10000) --> udelay(78) (rounded up to udelay(100))
    
    There was one instance of sdelay(10000), which looked like sort of a
    typo since sdelay(0x10000) was used elsewhere. sdelay(10000) should
    approximate to about 12us, so we'll stick with that for now and leave
    a note.
    
    Change-Id: I5e7407865ceafa701eea1d613bbe50cf4734f33e
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3079
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1a0b5e1c0594cb1bfe5094ad0c6eb183c9f3a593
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Apr 11 12:58:25 2013 -0700

    google/snow: enable 32KHz sleep clock
    
    Change-Id: I9db91826e4534b8a6eea2b13bcf7c6abd848b4e4
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3075
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 130aafacb0998bddef222f1a4ae6e44003433279
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 16 16:00:23 2013 -0700

    Samsung/exynos5250: convert unsigned {int,char} to u32/u8
    
    The types are (esp. int) are confusing at times as to size.
    Make them definite as to size.
    
    Change-Id: Id7808f1f61649ec0a3403c1afc3c2c3d4302b7fb
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3103
    Tested-by: build bot (Jenkins)
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 88d0c7330e1a10d621e331398a041458d1c940b2
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Tue Apr 16 13:59:37 2013 +0800

    AMD Parmer: remove unused macros and turn off unused pcie port
    
    1) The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE,
    GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used.
    This is based on >AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h< [1].
    
    2) Disable unused PCIE port in devicetree.cb.
    PCIE port 3 is not used in Parmer.
    This is based on item 3 of >AMD Thatcher: Fix PCIE link issues< [2].
    
    [1] http://review.coreboot.org/#/c/3087/
    [2] http://review.coreboot.org/#/c/3011/
    
    Change-Id: Id6f00d5e77ce5133d9ef3db07f95ad03a59e061a
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3099
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8d9ffd93b59781299bb2ed06d7f9ad30c7aac41b
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Apr 13 18:25:56 2013 +0200

    cbmem: map_memory: Use length modifier `j` and cast for an `off_t`  argument
    
    cbmem currently fails to build due to `-Werror` and the following
    warning.
    
        $ make
        cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
        cbmem.c: In function ‘map_memory’:
        cbmem.c:87:2: error: format ‘%zx’ expects argument of type ‘size_t’, but argument 2 has type ‘off_t’ [-Werror=format]
        […]
    
    Casting the argument of type `off_t` to `intmax_t` and using the
    length modifier `j`
    
        $ man 3 printf
        […]
               j      A following integer conversion corresponds to an intmax_t or uintmax_t argument.
        […]
    
    instead of `z` as suggested in [1] and confirmed by stefanct and
    segher in #coreboot on <irc.freenode.net>, gets rid of this warning
    and should work an 32-bit and 64-bit systems, as an `off_t` fits
    into `intmax_t`.
    
    [1] http://www.pixelbeat.org/programming/gcc/int_types/
    
    Change-Id: I1360abbc47aa1662e1edfbe337cf7911695c532f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3083
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8c937c7e3cb9768c83e49a445f13e87a58d79768
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Tue Mar 12 15:53:44 2013 +0100

    Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2
    
    Commit »Add support for Intel Panther Point PCH« (8e073829) [1] used
    `1 << 25` to set the APIC ID of 2. Using `2 << 24`, which is the same
    value, instead makes it clear, that the APIC ID is 2.
    
    [1] http://review.coreboot.org/853
    
    Change-Id: I5044dc470120cde2d2cdfc6e9ead17ddb47b6453
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3100
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 8a2bc62d4ce86689353021843b2377c8bb8fab56
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Apr 15 20:36:01 2013 -0700

    snow: Return 0 from get_recovery_mode_from_vbnv.
    
    This function isn't yet used for much, or perhaps anything, but where it
    appears in the code it's ored with other values. Since we're not actually
    retrieving anything, it might be best to return 0 so that the other values
    that are being ored in can be expressed and this function can stay dormant
    until it actually has something to do.
    
    Change-Id: I6edc222a5c2d00ece2ecfad5191a615331eeaf16
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3098
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 5cda30845c370d079a1ba2ff27628d76342da08d
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Apr 15 19:59:10 2013 -0700

    snow: Report the state of the power button GPIO in the coreboot tables.
    
    Change-Id: Ia7ce2b7342e186c565b92211e3ac15d80ce24b38
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3097
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit e2b20f2d5ad6b061d7645528c45a4bfc4beb1f29
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Apr 15 19:47:40 2013 -0700

    snow: Configure the power button as an input GPIO.
    
    We need to read it to report its value to the payload. The kernel will
    reconfigure it as an external interrupt, but we'll make it a regular input
    for now.
    
    Change-Id: I019bd2c2731144d3b7bb53fad0c2c903874f616c
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3096
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit acb9d4459973627f3b082dafb3f184a56a5d4219
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Apr 15 19:45:10 2013 -0700

    snow: Fix the name of some constants in romstage.c.
    
    These names were inherited from chromeos.c where they've already been
    fixed.
    
    Change-Id: I7ad57b979b7b8f42f6bd68d1ecf887caba3fa3f1
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3095
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 88beef0a8e58c1b0404f2f91707fcdba7b113471
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Apr 15 19:07:10 2013 -0700

    snow: Get rid of the oprom loaded GPIO.
    
    ARM doesn't use option ROMs, so this value doesn't make sense.
    
    Change-Id: I1a0f0854e1dd4b9594ca0c147e590337520436da
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3094
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit a5d914e47c84bf66f7a91264f431cad3e8d54f2f
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Apr 15 18:22:11 2013 -0700

    snow: Tidy up chromeos.c.
    
    Got rid of a lot of #defines, some of which were converted to enums and
    the rest which were eliminated entirely. Got rid of cruft in
    get_developer_mode_switch and started using it for the dev mode GPIO.
    Instead of a macro defining how many GPIOs are expected, now the code
    actually counts the GPIOs as they're added.
    
    Change-Id: I97b6b9f52a72d1276eb3cf36d7f9dd7b335b4d19
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3093
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 7fa726a9146ab9a6468a639ef6a95e5d69fbde02
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Apr 15 18:09:15 2013 -0700

    snow: Add support for EC based recovery.
    
    Implement the get_recovery_mode_switch function using the newly added I2C
    based Chrome EC support.
    
    Change-Id: I9d0200629887f202edf017cba3222a7d7f5b053e
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3092
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit a554e237231ad12c8dc23d1173f55fb4e1d100b3
Author: Gabe Black <gabeblack@chromium.org>
Date:   Mon Apr 15 16:25:02 2013 -0700

    snow: Fix some comments in chromeos.c.
    
    The comment about the lid switch was left over from when this file was copied
    from another board and was incorrect. Also fixed a capitalization
    inconsistency.
    
    Change-Id: Icefd19047971e13c08f615578e4a181e82a2997f
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3091
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit ed7e29e6202485ba7b4f27bd415c891abdbb9f1d
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sun Feb 24 12:01:44 2013 +0100

    Lenovo ThinkPad X60: Add Native VGA init.
    
    The code has been taken from the google link mainboard
      and modified to fit the ThinkPad X60.
    
    Change-Id: Ie16e45163acdc651ea46699ecc33055bfd34099c
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/2998
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cef4ea7fb53f01a74126b85232503a2d106d9933
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Tue Feb 26 18:10:52 2013 +0800

    documentation: Complete the AMD-S3.txt
    
    Fix some typos and finish empty sections.
    
    Change-Id: I08cc971e763252b035ab8ed2118180140e34ac72
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2483
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 76720d064da18d67c1be53ab4c0b2af6f1fcfd06
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Apr 15 18:06:32 2013 +0800

    ec/google: Move plug-n-play initialization to LPC protocol.
    
    "Plug-n-play" is not supported on all platforms using Google's Chrome EC.
    For example, EC on I2C bus will need explicit configuration and initialization.
    So move the plug-n-play initialization to the LPC implementation.
    
    Verified by building Google/Link (with EC/LPC) successfully.
    
    Change-Id: I49e5943503fd5301aa2b2f8c1265f3813719d7e3
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3089
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6bfbb33a64f95bcfdf46f8a35c342177886bb594
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Apr 15 18:27:24 2013 +0800

    ec/google: Support Google's Chrome EC on I2C interface.
    
    Google's Chrome EC can be installed on LPC or I2C bus, using different command
    protocol.  This commit adds I2C support for devices like Google/Snow.
    
    Note: I2C interface cannot be automatically probed so the bus and chip number
    must be explicitly set.
    
    Verified by booting Google/Snow, with following console output:
      Google Chrome EC: Hello got back 11223344 status (0)
      Google Chrome EC: version:
         ro: snow_v1.3.108-30f8374
         rw: snow_v1.3.128-e35f60e
        running image: 1
    
    Change-Id: I8023eb96cf477755d277fd7991bdb7d9392f10f7
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3074
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 07e0f1bf1a2781102e6f6a242a7a97944b0f3ba0
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Apr 13 15:58:03 2013 +0200

    AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in comments
    
    When looking into possible reasons for a proposed revert [1], I noticed
    that the comments use four arguments for `PCIE_DDI_DATA_INITIALIZER`,
    but the actual definition only uses three.
    
        $ git grep -A1 PCIE_DDI_DATA_INITIALIZER # manually squeeze whitespace in output
        […]
        --
        src/vendorcode/amd/agesa/f10/AGESA.h:#define  PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
        src/vendorcode/amd/agesa/f10/AGESA.h-{mConnectorType, mAuxIndex, mHpdIndex}
        --
        src/vendorcode/amd/agesa/f10/AGESA.h:   *      PCIE_DDI_DATA_INITIALIZER (ConnectorType
        src/vendorcode/amd/agesa/f10/AGESA.h-   *    },
        --
        src/vendorcode/amd/agesa/f10/AGESA.h:   *      PCIE_DDI_DATA_INITIALIZER (ConnectorType
        src/vendorcode/amd/agesa/f10/AGESA.h-   *    }
        --
        […]
    
    So remove the fourth argument in the comments. Luckily the compiler,
    at least gcc, warns about a wrong number of arguments, and therefore
    no incorrect code resulted from the wrong documentation.
    
    [1] http://review.coreboot.org/#/c/3077/
    
    Change-Id: I3e5a02c66a23af1eb2d86be8dbc7aaa3e5cea05e
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3080
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8764b0e1c03c6934ebefd47fbe4dc26069911f3d
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Thu Apr 4 16:05:11 2013 -0600

    Fam14 DSDT: Also return for unrecognized UUID in _OSC
    
    Fixing warnings introduced by the following patches:
    http://review.coreboot.org/#/c/2684/
    http://review.coreboot.org/#/c/2739/
    http://review.coreboot.org/#/c/2714/
    
    These patches were meant to fix the dmesg warning about
    the OSC method not granting control appropriately.  These
    patches then introduced warnings during the coreboot build
    process which were missed during the patch submission
    process.  These warnings are below:
    
    	Intel ACPI Component Architecture
    	ASL Optimizing Compiler version 20100528 [Oct 15 2010]
    	Copyright (c) 2000 - 2010 Intel Corporation
    	Supports ACPI Specification Revision 4.0a
    
    		dsdt.ramstage.asl  1143:    Method(_OSC,4)
    		Warning  1088 -                       ^ Not all control paths return a value (_OSC)
    
    		dsdt.ramstage.asl  1143:    Method(_OSC,4)
    		Warning  1081 -                       ^ Reserved method must return a value (Buffer required for _OSC)
    
    	ASL Input:  dsdt.ramstage.asl - 1724 lines, 34917 bytes, 889 keywords
    	AML Output: dsdt.ramstage.aml - 10470 bytes, 409 named objects, 480 executable opcodes
    
    	Compilation complete. 0 Errors, 2 Warnings, 0 Remarks, 494 Optimizations
    
    This patch gives the following compilation status:
    
    	Intel ACPI Component Architecture
    	ASL Optimizing Compiler version 20100528 [Oct  1 2012]
    	Copyright (c) 2000 - 2010 Intel Corporation
    	Supports ACPI Specification Revision 4.0a
    
    	ASL Input:  dsdt.ramstage.asl - 1732 lines, 33295 bytes, 941 keywords
    	AML Output: dsdt.ramstage.aml - 10152 bytes, 406 named objects, 535 executable opcodes
    
    	Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 432 Optimizations
    
    The fix is simply adding an Else statement to the If which checks
    for the proper UUID.  This way, all outcomes will return a full
    control package.  This patch has no effect on the dmesg output.
    
    Change-Id: I8fa246400310b26679ffa3aa278069d2e9507160
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3052
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 17c05f23e215ff741bfc3fa611d7d2087198c3c1
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Apr 3 10:00:33 2013 +0200

    inteltool: pcie.c: Use `0xffULL` instead of `0xff` to avoid shift overflow
    
    When building inteltool with Clang, it warns about the following.
    
        $ clang --version
        Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2)
        Target: i386-pc-linux-gnu
        Thread model: posix
        $ CC=clang make
        […]
        clang -O2 -g -Wall -W   -c -o pcie.o pcie.c
        pcie.c:297:40: warning: signed shift result (0xFF0000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                        pciexbar_phys = pciexbar_reg & (0xff << 28);
                                                        ~~~~ ^  ~~
        pcie.c:301:41: warning: signed shift result (0xFF8000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                        pciexbar_phys = pciexbar_reg & (0x1ff << 27);
                                                        ~~~~~ ^  ~~
        pcie.c:305:41: warning: signed shift result (0xFFC000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
                        pciexbar_phys = pciexbar_reg & (0x3ff << 26);
                                                        ~~~~~ ^  ~~
        3 warnings generated.
        […]
    
    Specifying the length by using the suffix `0xffULL` fixes these issues
    as now enough bits are available.
    
    These issues were introduced in commit 1162f25a [1].
    
        commit 1162f25a49e8f39822123d664cda10fef466b351
        Author: Stefan Reinauer <stepan@coresystems.de>
        Date:   Thu Dec 4 15:18:20 2008 +0000
    
            Patch to util/inteltool:
            * PMBASE dumping now knows the registers.
            * Add support for i965, i975, ICH8M
            * Add support for Darwin OS using DirectIO
    
    [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1162f25a49e8f39822123d664cda10fef466b351
    
    Change-Id: I7b9a15b04ef3bcae64e06266667597d0f9f07b79
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3015
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 18ac0d52b79aae665276303624c30f249630a603
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Mar 13 11:44:39 2013 +0200

    Drop add_mainboard_resources and HAVE_MAINBOARD_RESOURCES again
    
    These are not defined since commit »Drop HAVE_MAINBOARD_RESOURCES«
    (1c5071d1) [1] but were unfortunately introduced again in new ports.
    
    [1] http://review.coreboot.org/1414
    
    Change-Id: I5eb61628141aefd08779615702d51ca155fa632a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/2707
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit c3fc1e05a65e28c92db99c423fb6727add7ad360
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Apr 5 11:39:42 2013 +0200

    cbmem: Makefile: Allow to override `CC` variable
    
    Now users can use a different compiler from GCC like Clang by for example
    doing `CC=clang make`.
    
    Change-Id: I664a36df79f7496a56d89bdb61948b2eda33a6b4
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3082
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 15a1fd1db9dd93004f808badcb15ca635177def6
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Apr 14 13:00:22 2013 +0200

    inteltool: Use portable type `uint64_t` instead of `u64`
    
    In [1] Idwer Vollering noted, that the type `u64` is not portable so
    on his FreeBSD system, the following warning is shown.
    
        $ clang -O2 -Wall -W -I/usr/local/include   -c -o amb.o amb.c
        amb.c:441:22: error: use of undeclared identifier 'u64'
                        ambconfig_phys = ((u64)pci_read_long(dev16, 0x4c) << 32) |
    
    The type `uint64_t` seems to be defined also on FreeBSD, so using this
    fixes the warning.
    
    Note, this warning is not reproducable with Debian Sid/unstable for
    example. I have no idea why though.
    
    [1] http://review.coreboot.org/#/c/3015/
    
    Change-Id: Ic22f4371114b68ae8221d84a01fef6888d43f365
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3086
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0b3128679688b76f8fc92a770615270707a80afd
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Apr 12 14:03:04 2013 +0200

    AMD CIMx sb800/SATA.c, sb900/Sata.c:  Fix R*AI*D typo in comments
    
    Spell RAID correctly in comments. Found with the following command.
    
        $ git grep -i riad
    
    Change-Id: I68e8476d885a88df589d25f88cc158d71eb04e07
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3081
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cb891de07ffe605897010776fc1becc9589d3648
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Apr 13 18:35:32 2013 +0200

    cbmem: parse_cbtable: Use length modifier `ll` `u64` argument
    
    Currently on a 32-bit system cbmem fails to build due to `-Werror`
    and the following warning.
    
        $ make
        cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86  -c -o cbmem.o cbmem.c
        […]
        cbmem.c: In function ‘parse_cbtable’:
        cbmem.c:135:2: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘u64’ [-Werror=format]
        cc1: all warnings being treated as errors
        […]
    
    Using the length modifier `ll` instead of `l` gets rid of this
    warning.
    
    Change-Id: Ib2656e27594c7aaa687aa84bf07042933f840e46
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3084
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b8eb0a802f777bd4b2c24bca571afc1d89352006
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sat Apr 13 23:06:17 2013 +0200

    link/graphics: Remove the inclusion of an AMD header.
    
    link(google chromebook pixel) is an intel machine.
    
    Change-Id: I9d40f1e945021d8e190879477cd12be7d0262733
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/3085
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cd4c8c1e0e9049b264bdbe62e9f2192dee8c3d31
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Apr 12 16:02:44 2013 -0700

    exynos5/snow: remove wait_ms arg from dp_controller_init()
    
    This removes the wait_ms argument from the dp_controller_init(). The
    only delay involved is a constant 60ms delay that happens if
    everything else goes well. This delay is derived from the LCD spec
    so there's no reason it should be baked into the controller code.
    
    (This patch also has the side-effect of fixing a bug where we were
    delaying on an undefined value for wait_ms).
    
    Change-Id: I03aa19f2ac2f720524fcb7c795e10cc57f0a226e
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3078
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c0b972f60dbd1a3dadfc568b5245c6b0ee6df559
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Apr 11 15:03:28 2013 -0700

    Exynos5250: add a microsecond timer
    
    Add a microsecond timer, its declaration, the function to start it,
    and its usage.  To start it, one calls timer_start().  From that point
    on, one can call timer_us() to find microseconds since the timer was
    started.
    
    We show its use in the bootblock. You want it started very early.
    
    Finally, the delay.h change having been (ironically) delayed, we
    create time.h and have it hold one declaration, for the timer_us() and
    timer_start() prototype.
    
    We feel that these two functions should become the hardware specific
    functions, allowing us to finally move udelay() into src/lib where it
    belongs.
    
    Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3073
    Tested-by: build bot (Jenkins)

commit 2c8f81b57b20c14edf4b77d3f5dcd2bcce717180
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Apr 11 10:45:11 2013 +0200

    cbfstool: cbfs-mkstage.c: Free `buffer` on error path
    
    Cppcheck warns about a memory leak, present since adding romtool,
    which was renamed to cbfstool, in commit 5d01ec0f.
    
        $ cppcheck --version
        Cppcheck 1.59
        […]
        [cbfs-mkstage.c:170]: (error) Memory leak: buffer
        […]
    
    Indeed the memory pointed to by `buffer` is not freed on the error path,
    so add `free(buffer)` to fix this.
    
    Change-Id: I6cbf82479027747c800c5fe847f20b779e261ef4
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3069
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e76d8d7ced79d618291f6f0b1331d60a86855f2e
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Thu Apr 11 12:01:19 2013 +0200

    acpica: update URL
    
    The URL to acpica-unix-20121114 has changed, update the URL.
    
    Change-Id: I1c8c228094f19455af3682f36f1990586fe3934c
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/3070
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8ecec215be54fc15ba1cc6f2e5c452ffb833c29a
Author: Nico Huber <nico.h@gmx.de>
Date:   Wed Apr 10 19:14:41 2013 +0200

    Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region"
    
    This reverts commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5:
    
        commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5
        Author: Patrick Georgi <patrick.georgi@secunet.com>
        Date:   Tue Apr 9 15:41:23 2013 +0200
    
            siemens/sitemp_g1p1: Make ACPI report the right mmconf region
    
            ACPI reported the entire space between top-of-memory and some
            (relatively) arbitrary limit as useful for MMIO. Unfortunately
            the HyperTransport configuration disagreed. Make them match up.
    
            Other boards are not affected since they don't report any region
            for that purpose at all (it seems).
    
            Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e
            Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
            Reviewed-on: http://review.coreboot.org/3047
            Tested-by: build bot (Jenkins)
            Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    
    It sneaked in without it's dependencies and, therefore, broke the build for
    all amdk8 targets. Paul Menzel already commented on the issue in [1]. It
    also doesn't look like the dependencies would be pulled soon [2].
    
    [1] http://review.coreboot.org/#/c/3047/
    [2] http://review.coreboot.org/#/c/2662/
    
    Change-Id: Ica89563aae4af3f0f35cacfe37fb608782329523
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3063
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7f23aeb05d57d4989783b35afce0017d3772fde6
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Tue Apr 2 10:49:09 2013 +0800

    AMD Thatcher: Fix PCIE link issues
    
    1). Thatcher PCIE x8 slot is reverse order.
    Although the PCIE slot is x16, it actually uses 8 lanes(15:8).
    Because the PCIE slot is configured by PortList[0], fix this item can enable the slot.
    A x1 PCIE network adapter works well in this slot.
    
    2). Fix DdiList to detect DP monitor or HDMI monitor.
    GPIO50 can be used to detect DP0/HDMI0 monitor.
    If GPIO50 is 1, it is DP monitor. If GPIO50 is 0, it is HDMI monitor.
    GPIO51 can be used to detect DP1/HDMI1 in the same way.
    
    3). Disable unused PCIE port and clean up code in PlatformGnbPcie.c and devicetree.cb.
    PCIE port 3 and 7 are not used in Thatcher.
    
    Change-Id: I8524b6fc1b6cdc03ba92e7191186bfb0986767c8
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3011
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit a904f9ef691062a43baa5542cf63daed45a1185a
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Apr 11 15:58:12 2013 +0800

    ec/google: Isolate EC bus protocol implementation.
    
    The Chrome EC can be connected by different types of bus like LPC / I2C / SPI,
    and the current implementation is only for LPC.
    
    To support other types, we must first isolate the LPC protocol stuff and add
    configuration variable (EC_GOOGLE_CHROMEEC_LPC) to specify bus type.
    
    Verified by building google/link (with chromeec) configuration successfully.
    
    Change-Id: Ib2920d8d935bcc77a5394e818f69e9265e26e8a0
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/3068
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit d9de6c4f0eb1c863f8fd81ede326973ad1aab0f2
Author: Steven Sherk <steven.sherk@se-eng.com>
Date:   Thu Apr 11 08:40:57 2013 -0600

    Add new superio device
    
    - Added in new support for Nuvoton NCT5104D LPC device.
    
    Change-Id: I0af8c5e3e46fdd0a549475b30917897ae9e144a7
    Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3072
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6a1210901dff47a65dac157445f0a76219be0d55
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Apr 10 11:33:37 2013 +0200

    AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in comment
    
    Reading the paste of code in a message to the mailing list [1],
    a typo was spotted and found in one more place.
    
        $ git grep egnoring
        src/southbridge/amd/rs780/cmn.c:                         * egnoring the reversal case
        src/southbridge/amd/sr5650/sr5650.c:                     * egnoring the reversal case
    
    These typos are there since when the code was committed and are
    now corrected.
    
    [1] http://www.coreboot.org/pipermail/coreboot/2013-April/075644.html
    
    Change-Id: I55c65f71e4834f209b60d678f0d44bc2f4217099
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3062
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 573a1d6fa8d72e6d3f738bb889a34b405952046c
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Mon Mar 18 11:19:26 2013 -0600

    Persimmon/Fam14/SB800 DSDT: Split into common areas
    
    Split the Persimmon DSDT into common code areas.
    For example, split the Southbridge specific code into
    the Southbridge directory and CPU specific code into
    the CPU directory.  Also adding the superio.asl file
    to the Persimmon DSDT tree. This file is empty for
    the moment but will be necessary in the future.  I have
    also emptied the thermal.asl file in the mainboard
    directory because it does not seem to perform as
    intended (fan control does not change when it is
    brought back into the code base) and it has been
    inside a '#if 0' statement for a long time.  Removing
    it until it is decided that it is actually necessary.
    
    This change was verified in three different ways:
    	1. Visual comparison of the compiled DSDT pulled from the
    	Persimmon after booting into Linux using the ACPI tools
    	acpidump, acpixtract, and iasl.  The comparison was done
    	between the DSDT before and after doing the split work.
    
    	This test is somewhat difficult considering the expanse
    	of the changes.  Blocks of code have been moved, and
    	others changed.
    
    	2. Linux logs were dumped before and after the DSDT split.
    	Logs dumped and compared include dmesg and lspci -tv.
    	Neither log changed significantly between the two compare
    	points.
    
    	3. The test suite FWTS was run on the Coreboot build both
    	before and after doing the DSDT split with the command
    	'sudo fwts -b -P -u'.  The flag -b specifies all batch jobs,
    	-P specifies all power tests, and -u specifies utilities.
    	Interactive jobs were not run as most of them consist of
    	laptop checks.  Again, there were no significant changes
    	between the two endpoints.
    
    These tests lead me to believe that there was no change in
    the functionality of the ACPI tables apart from what is
    known and expected.
    
    This patch is the first of a series of patches to split the DSDT.
    The ASRock patch was merged before this one and breaks the ASROCK
    E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/).
    Please be aware of this dependency when pulling these patches.
    Other patches that depend on this patch are
    'AMD Fam14: Split out the AMD Fam14 DSDT'
    (http://review.coreboot.org/#/c/3051/)
    and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC'
    (http://review.coreboot.org/#/c/3052/)
    
    Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3048
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 109a7107436ec142b8028e2b8afc013af80107f1
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Apr 11 15:19:04 2013 +0200

    libpayload: storage.c: Fix typo in st*orage in comment
    
    Reading commit »libpayload: New AHCI, ATA and ATAPI drivers«
    (1f6bd94f) [1], the spelling error was found and is now fixed.
    
    [1] http://review.coreboot.org/1622
    
    Change-Id: Id418bcb99c1a9a400a49fc04078e465bd0908074
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3071
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1a5c9cd33b6f08f80d574acaca611550ae596841
Author: Gabe Black <gabeblack@chromium.org>
Date:   Wed Apr 10 14:34:57 2013 -0700

    Snow: Set up the ChromeOS GPIOs as inputs during the ROM stage.
    
    We need these to be inputs so they can be read when populating the coreboot
    tables. It seems like a good idea to do this early to ensure that the input
    gate capacitance has had a chance to charge, and if we decide to use
    actually use that information during the ROM stage to do earlier RW
    firmware selection.
    
    It is not guarded by a ChromeOS config variable because those lines are
    always intended to be input GPIOs, regardless of whether we're running
    ChromeOS or not.
    
    Change-Id: Id76008931b5081253737c6676980a1bdb476ac09
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3067
    Tested-by: build bot (Jenkins)

commit fe3b024a44451b2f11d497ba6e2715fa6d6539a7
Author: Gabe Black <gabeblack@chromium.org>
Date:   Wed Apr 10 14:39:09 2013 -0700

    Snow: Fix the recovery GPIO polarity, and lid GPIO polarity and number.
    
    Change-Id: I34097f878291367b28962048190e11ccaacfc514
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3066
    Tested-by: build bot (Jenkins)

commit 514f20293957666d10f1ae3f946dc6f94d635364
Author: Gabe Black <gabeblack@chromium.org>
Date:   Wed Apr 10 14:32:56 2013 -0700

    ARM: Unmask aborts very early in the bootblock.
    
    It's better to recognize aborts when they occur than to mask them to
    discover them later without knowing where they actually came from.
    
    Change-Id: Ic8f5321415f411afac94b5ef9dd440790df6d82c
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/3065
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 8d80a3fb9fe88fd5017c147786ccb51b00e935f1
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Mar 29 11:33:42 2013 -0600

    ASRock DSDT: Split the ASRock DSDT
    
    This is the same split as was done on the Persimmon.
    
    Change-Id: I25bd63f23417b7926232f07eaaa7917170af9d60
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/3050
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b48605da209ed92832fdc1f067feda63b5421e7e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 9 14:35:35 2013 -0700

    Exynos5250: Use new chip settings for the cpu
    
    Properly use the chip settings when configuring the CPU,
    at this point being purely graphics.
    
    Change-Id: I9bc2d32c1037653837937b314e4041abc0024835
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3054
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 1fde22c54cacb15493bbde8835ec9e20f1d39bf5
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Apr 9 15:41:23 2013 +0200

    siemens/sitemp_g1p1: Make ACPI report the right mmconf region
    
    ACPI reported the entire space between top-of-memory and some
    (relatively) arbitrary limit as useful for MMIO. Unfortunately
    the HyperTransport configuration disagreed. Make them match up.
    
    Other boards are not affected since they don't report any region
    for that purpose at all (it seems).
    
    Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/3047
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7576f2515ed81a67e6271cb6a88fa94b626e2938
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 9 14:39:34 2013 -0700

    GOOGLE/SNOW: add edp support to ramstage
    
    Add basic edp support to the ramstage. Not working.
    
    Change-Id: I15086e03417edca7426c214e67b51719d8ed9341
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3055
    Tested-by: build bot (Jenkins)

commit 765ff76d8f1c09fefdc533b2facd0d99b1787eca
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Apr 9 17:20:07 2013 -0700

    [2/2] tps65090: re-factor for coreboot
    
    This does basic re-factoring to fit the driver into coreboot.
    
    Change-Id: Id5f8c12a73ec37ddd545d50b3e8e9b3012657db1
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3061
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6e877ec63e034691139897cd4de876f06fa6def5
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Apr 9 16:58:02 2013 -0700

    [1/2] initial import of TI TPS65090
    
    This imports TPS65090 PMIC from u-boot and adds/updates Makefiles
    and Kconfig files. The follow-up patch will re-factor the code.
    
    Change-Id: Ic9e43b9665ddf7f55feae8fa17fbf3d2d5f4756d
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3060
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 767edfc542369720798f9f3ec194b0898fe5cecd
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 9 14:32:32 2013 -0700

    GOOGLE/SNOW: clean up the device tree
    
    This is a simpler device tree that is also more correct,
    and has graphics settings as well.
    
    Change-Id: I342d8be7dddb76e6992876c73f5c625c926977d3
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3053
    Tested-by: build bot (Jenkins)

commit 798f6649a91262bf4f073c349b0439b42975a5c4
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 9 14:29:42 2013 -0700

    exynos5-common: Enable fimd_bypass and minor cleanup
    
    Basic cleanup, this code still does not work.
    
    Change-Id: I84ed9f08fd04cd8eb74cd860e0775d8c602f42d6
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3049
    Tested-by: build bot (Jenkins)

commit 086b369dfc6421c698cd5a386e75fde68cb838dc
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Apr 8 20:01:18 2013 -0700

    armv7: replace read/write macros with inlines
    
    This enables type checking for safety as to help prevent errors like
    http://review.coreboot.org/#/c/3038/ . Now compilation fails if the
    wrong type is passed into readb/readw/readl/writeb/writew/writel
    or other macros in io.h.
    
    This also deprecates readw/writew. The previous definition was 16-bits
    which is incorrect since wordsize on ARMv7 is 32-bits and there was
    only 1 instance of writew (#if 0'd anyway). Going forward we should
    always use read{8,16,32} and write{8,16,32} where N specifies the
    exact length rather than relying on ambiguous definition of wordsize.
    
    Since many macros relied on __raw_*, which were basically the same
    (minus data memory barrier instructions), this patch also gets rid
    of __raw_*. There were parts of the code which ended up using these
    macros consecutively, for example:
    	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
    	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
    
    In such cases the safe versions of readl() and writel() should be
    used anyway.
    
    Note: This also fixes two dubious casts as to avoid breaking
    compilation.
    
    Change-Id: I8850933f68ea3a9b615d00ebd422f7c242268f1c
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3045
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b959fbb87adb274b442bc6ab812e5a2ce92ca220
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Apr 5 16:11:12 2013 -0700

    exynos5: Re-factor I2C code
    
    This re-factors the Exynos5 I2C code to be simpler and use the
    new API, and updates users accordingly.
    
    - i2c_read() and i2c_write() functions updated to take bus number
      as an argument.
    
    - Get rid of the EEPROM_ADDR_OVERFLOW stuff in i2c_read() and
      i2c_write(). If a chip needs special handling we should take care
      of it elsewhere, not in every low-level i2c driver.
    
    - All the confusing bus config functions eliminated. No more
      i2c_set_early_config() or i2c_set_bus() or i2c_get_bus(). All this
      is handled automatically when the caller does a transaction and
      specifies the desired bus number.
    
    - i2c_probe() eliminated. We're not a command-line utility.
    
    - Let the compiler place static variables automatically. We don't need
      any of this fancy manual data placement.
    
    - Remove dead code while we're at it. This stuff was ported early on
      and much of it was left commented out in case we needed it. Some
      also includes nested macros which caused gcc to complain.
    
    - Clean up #includes (no more common.h, woohoo!), replace debug() with
      printk().
    
    Change-Id: I8e1f974ea4c6c7db9f33b77bbc4fb16008ed0d2a
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3044
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cfb73607be05e57237592c5c94a98589aba04833
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Apr 5 13:42:39 2013 -0700

    replace device/i2c.h with simpler version
    
    The existing header was imported along with the Exynos code and left
    mostly unchanged. This is the first patch in a series intended to
    replace the imported u-boot I2C API with a much simpler and cleaner
    interface:
    
    - We only need to expose i2c_read() and i2c_write() in our public API.
      Everything else is board/chip-dependent and should remain hidden
      away.
    
    - i2c_read and i2c_write functions will take bus number as an arg
      and we'll eliminate i2c_get_bus and i2c_set_bus. Those are prone to
      error and end up cluttering the code since the user needs to save
      the old bus number, set the new one, do the read/write, and restore
      the old value (3 added steps to do a simple transaction).
    
    - Stop setting default values for board-specific things like SPD
      and RTC bus numbers (as if we always have an SPD or RTC on I2C).
    
    - Death to all the trivial inline wrappers. And in case there was any
      doubt, we really don't care about the MPC8xx. Though if we did then
      we would not pollute the public API with its idiosyncrasies.
    
    Change-Id: I4410a3c82ed5a6b2e80e3d8c0163464a9ca7c3b0
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3043
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4026b034f1d4b8b6e7628c66b4bb8e7ba15082e7
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Tue Apr 9 09:57:27 2013 +0200

    FrontRunner/Toucan-AF: boards will be renamed to fit ADLINK scheme
    
    Originally developed by LiPPERT and after the acquisition marketed as
    'LiPPERT by ADLINK', the plan is now to streamline both boards into the
    ADLINK naming scheme.  But AFAIK a few have already been sold and as of
    this writing the website still advertises the old names.  And in any case
    the veteran LX products will continue to be sold by ADLINK under their
    original names.
    
    So create CONFIG_VENDOR_ADLINK, currently only telling users to look under
    LiPPERT (however any future boards will be added here).
    
    Further add an explanation to CONFIG_VENDOR_LIPPERT, and in the Mainboard
    model selection show both names.
    
    Change-Id: Iaafa88533ef4cce33243293c3d55754e7e93d003
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/3046
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f4a0d019fa07a0d867a23b36673ff300cdefce6c
Author: Vladimir Serbinenko <phcoder@gmail.com>
Date:   Sat Mar 30 12:15:12 2013 +0100

    util/cbmem: Don't output trailing garbage for cbmemc
    
    Current code outputs the whole cbmemc buffer even if only part of
    it is really used. Fix it to output only the used part and notify
    the user if the buffer was too small for the required data.
    
    Change-Id: I68c1970cf84d49b2d7d6007dae0679d7a7a0cb99
    Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
    Reviewed-on: http://review.coreboot.org/2991
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 33e83caff59f7b6ff2ba62d3b496235ef5c4e543
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Apr 8 11:20:55 2013 -0700

    cbfstool: completely initialize input and output streams
    
    The LZMA glue code in cbfstool was recently rewritten from C++
    to plain C code in:
    
            commit aa3f7ba36ebe3a933aa664f826382f60b31e86f1
            Author: Stefan Reinauer <reinauer@chromium.org>
            Date:   Thu Mar 28 16:51:45 2013 -0700
    
                cbfstool: Replace C++ code with C code
    
                Reviewed-on: http://review.coreboot.org/3010
    
    In the progress of doing so, the stream position for the
    input stream and output stream was not reset properly. This
    would cause LZMA producing corrupt data when running the
    compression function multiple times.
    
    Change-Id: I096e08f263aaa1931517885be4610bbd1de8331e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3040
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bb2cc714809150e1f1d6a502e29ef524232ee7a9
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Apr 5 13:51:11 2013 -0700

    Fix read_option invocation in uart8250mem.c
    
    read_option was unified between ramstage and romstage a while ago.
    However, it seems some invocations were not fixed accordingly.
    This patch switches uart8250mem.c to use the new scheme.
    
    Change-Id: I03cef4f6ee9188a6412c61d7ed34fbaff808a32b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3033
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 84463efb9448425c9c498425a4fc80b53ed5db73
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Apr 5 13:49:55 2013 -0700

    Fix compilation when coverage debugging is enabled
    
    With CONFIG_DEBUG_COVERAGE enabled, the build currently fails with
    
    src/lib/gcov-glue.c: In function 'fseek':
    src/lib/gcov-glue.c:87:2: error: format '%d' expects argument of type 'int', but argument 4 has type 'long int' [-Werror=format]
    src/lib/gcov-glue.c:87:2: error: format '%d' expects argument of type 'int', but argument 4 has type 'long int' [-Werror=format]
    
    Change-Id: Iddaa601748c210d9dad06ae9dab2a3deaa635b2c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3032
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9e8af58263b7c84ee276354b97c19ad31992c8e9
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Nov 8 19:31:23 2012 -0800

    libpayload: Handle multifunction bridge devices better.
    
    This change modifies the code in libpayload that scans the PCI hierarchy for
    USB controllers. Previously, if a devices primary function (function 0) was a
    bridge, then none of the other functions, if any, would be looked at. If one
    of the other functions was a bridge, that wouldn't be handled either. The new
    version looks at each function that's present no matter what, and if it
    discovers that it's a bridge it scans the other side.
    
    Change-Id: I37f269a4fe505fd32d9594e2daf17ddd78609c15
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2517
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 6d0fe9cad003d752af3214ae9a91d7411d582950
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sun Apr 7 17:26:34 2013 -0700

    armv7: specify condition code for msr instruction
    
    This adds condition codes when using the msr instruction. Although
    described as "optional" in the Cortex-A series programmer's guide,
    our experience with using the msr instruction in the payload suggests
    that the condition code is not optional and that this only worked
    in coreboot (and u-boot) because the processor comes up in SVC32 mode.
    
    (credit to Gabe Black for finding this, I'm only uploading the patch)
    
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Change-Id: I0aa4715ae415e1ccc5719b7b55adcd527cc1597b
    Reviewed-on: http://review.coreboot.org/3037
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c7e5d798420bb00f2c1853ca6abc11a7ee027886
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sun Apr 7 17:38:32 2013 -0700

    exynos5250: add missing address-of operator in UART driver
    
    This adds a missing address-of operator. This was a subtle bug that
    didn't seem to cause problems at first since the serial console
    appeared to work. However it caused an imprecise external abort which
    became apparent later on when aborts were unmasked in the kernel via
    the CPSR_A bit.
    
    (credit goes to Gabe Black for finding this)
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Change-Id: I80a33b147d92d559fa8fefbe7d5642235deb9aea
    Reviewed-on: http://review.coreboot.org/3038
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0c8b7d1ac272d5578e61c260a14f4fabbf3f53eb
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Fri Apr 5 20:38:08 2013 +0200

    inteltool: remove unused file descriptor variable and ifdefs
    
    Change-Id: I6a119b1f362f481914377e8d14c713159f895130
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3030
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit db9eaf4cb2a2fe65b0d08dc5b47426f7399d6757
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Apr 5 15:38:12 2013 -0700

    snow/exynos5250: move board-specific power stuff to mainboard dir
    
    This moves highly board-specific code out from the Exynos5250
    power_init() into Snow's romstage.c. There's no reason the CPU-
    specific code should care about which PMIC we are using and
    which bus it is on.
    
    Change-Id: I52313177395519cddcab11225fc23d5e50c4c4e3
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/3034
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 161ccc76ea0f8941a34c5bed323cc9ba1fe0221d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Apr 5 13:35:29 2013 -0700

    exynos5250: add a chip.h file for the display register settings
    
    Display hardware is part of this SOC, and we need to be able
    to set certain variables in devicetree.cb. This chip file
    contains the initial things we think we need to set.
    
    Change-Id: I16f2d4228c87116dbeb53a3c9f3f359a6444f552
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3031
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 6ccb1abfd4aff94711b9950f75b0eb6758c4f4d1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 3 09:57:53 2013 -0500

    mtrr: add rom caching comment about hyperthreads
    
    Explicitly call out the effects of hyperthreads running the
    MTRR code and its impact on the enablement of ROM caching.
    
    Change-Id: I14b8f3fdc112340b8f483f2e554c5680576a8a7c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3018
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0dc775e894a3a7b3539eeeb4210bf8b796062274
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Fri Apr 5 01:15:04 2013 +0200

    inteltool: use inttypes for prints in memory.c
    
    This fixes at least one warning on my machine where "llx" is replaced by PRIx64.
    
    Change-Id: Iee3e5027d327d4d5f8e6d8b2d53d051f74bfc354
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/3024
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ce801b55fa21f119f19f39eacc15d8b63e639890
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Apr 5 09:56:18 2013 -0700

    exynos5-common: get rid of displayport trial code
    
    This was a first pass at display port support, we have
    realized that it was ultimately a bad path. The display
    hardware is intimately tied into a specific cpu and
    mainboard combination, and the code has to be elsewhere.
    
    The devicetree formatting is ugly, but it matters not:
    it's changing soon.
    
    Change-Id: Iddce54f9e7219a7569315565fac65afbbe0edd29
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/3029
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5f3754e66dbe3b04c71c19fb106a92b30d475ab4
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Apr 5 00:12:21 2013 +0200

    inteltool: cpu.c: Use conversion specifier `u` for unsigned integers
    
    Cppcheck [1], a static code analysis tool, warns about the
    following.
    
        $ cppcheck --version
        Cppcheck 1.59
        $ cppcheck --enable=all .
        […]
        Checking cpu.c...
        [cpu.c:951]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
        [cpu.c:962]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
        […]
    
    And indeed, `core` is an unsigned integer and `man 3 printf` tells
    the following about conversion specifiers.
    
           d, i   The int argument is converted to signed decimal notation. […]
    
           o, u, x, X
                  The unsigned int argument is converted to unsigned octal (o), unsigned decimal (u), or  unsigned  hexadecimal  (x  and  X)
                  notation.
    
    So use `u` and Cppcheck does not complain anymore.
    
    [1] http://cppcheck.sourceforge.net/
    
    Change-Id: If8dd8d0efe75fcb4af2502ae5100e3f2062649e4
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3026
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 72ef8881a319de48464e640ccd37e8e282320284
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Apr 4 14:12:26 2013 +0200

    libpayload, superiotool: README: Prepend `coreboot/` to path of change directory line
    
    Nico Huber spotted [1], that commit (4d6ab4e2) [1] updating
    superiotools’s `README` with the Git command line
    
        superiotool: Update README with Git repository URL and directory location
    
    missed, that after `git clone` one sitll has to change into
    the cloned directory.
    
    So prepend the path with `coreboot/` to fix that. The same error
    happened in the commit (e1ea5151) for libpayload [2]
    
        libpayload: Update README with Git repository URL and directory location
    
    and is fixed in this patch too.
    
    [1] http://review.coreboot.org/#/c/3019/
    [2] http://review.coreboot.org/2228
    
    Change-Id: Ib6e8b678af6276556a40ccfd52ae35ca7e674455
    Reported-by: Nico Huber <nico.h@gmx.de>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3021
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit 3402a7fa7001e40035b6ae303b2e47b6281fef1c
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Apr 1 18:26:58 2013 +0200

    inteltool: Cast to `intptr_t` instead of `uint64_t`
    
    When building inteltool under x86-32, the following warnings are
    shown.
    
        $ gcc --version
        gcc-4.7.real (Debian 4.7.2-15) 4.7.2
        Copyright (C) 2012 Free Software Foundation, Inc.
        This is free software; see the source for copying conditions.  There is NO
        warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
        $ make
        […]
        amb.c: In function ‘amb_read_config32’:
        amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        amb.c: In function ‘amb_read_config16’:
        amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        amb.c: In function ‘amb_read_config8’:
        amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        […]
    
    Nico Huber commented the following [1].
    
        I don't see those warnings because I build for x86-64. I guess
        they could be fixed by casting to `ptrdiff_t` (from stddef.h)
        instead of `uint64_t`.
    
    And indeed, using `ptrdiff_t` fixes the warning. But as Stefan
    Reinauer commented in [2], `intptr_t` is more appropriate as this
    is just a pointer and no pointer difference.
    
    So `intptr_t` is taken, which fixes these issues warned about too.
    
    These warnings were introduced in commit »inteltool: Add support for
    dumping AMB registers« (4b7b320f) [3].
    
    [1] http://review.coreboot.org/#/c/2996/1//COMMIT_MSG
    [2] http://review.coreboot.org/#/c/3002/1/util/inteltool/amb.c
    [3] http://review.coreboot.org/525
    
    Change-Id: I2ea1a31dc1e3db129e767d6a9e0433fd75a77d0f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3002
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit 190011e47c6187479db69344ccf87762009af444
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Mar 25 12:48:49 2013 +0200

    AMD: Drop six copies of wrmsr_amd and rdmsr_amd
    
    Based on comments in cpu/x86/msr.h for wrmsr/rdmsr, and for symmetry,
    I have added __attribute__((always_inline)) for these.
    
    Change-Id: Ia0a34c15241f9fbc8c78763386028ddcbe6690b1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/2898
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 4d6ab4e2ae25c8148e699e3821b71991ac4d80dc
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Apr 3 23:10:22 2013 +0200

    superiotool: Update README with Git repository URL and directory location
    
    Change-Id: I36d980cea5ca9cc67262dba809441091757e1fb5
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3019
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 5b5cf3d610f28bd44b15b0ef7a0816fd41d326af
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Apr 4 01:50:17 2013 +0200

    AMD GX1: Remove useless copied header file `northbridge.h`
    
    This was there since the beginning
    
        commit d24d6993b6d7bcf7977d74d081e718e1b076d1b0
        Author: arch import user (historical) <svn@openbios.org>
        Date:   Wed Jul 6 17:06:46 2005 +0000
    
            Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-26
            Creator:  Hamish Guthrie <hamish@prodigi.ch>
    
            Added AMD GX1 northbridge and cs5530 Southbridge
    
    but blindly copied from Intel 440 BX and is not used anywhere.
    
    Thanks to Idwer Vollering for spotting this.
    
    Change-Id: I38b3d3feb25966c3aa382994d323e59c3f3c9e6c
    Reported-by: Idwer Vollering
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3020
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Tested-by: build bot (Jenkins)

commit 3c156dd98c03dda5d579e0530ffc724399ed84fe
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Apr 1 14:40:59 2013 -0700

    lynxpoint: Cosmetic cleanup
    
    src/southbridge/intel/lynxpoint/pmutil.c was committed with two
    things that needed fixing.
    
    Change-Id: Ib83343a75840aa29847b607b0275971eb8140f12
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3003
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 27a1be9169eb165d4f23ef19042f26db3769c24f
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Wed Apr 3 10:12:55 2013 +0200

    Partially revert "AMD Inagua: broadcom.c: Add missing prototype for `broadcom_init()`"
    
    Commit 5d741567 added a prototype to broadcom.c to fix a warning.  This part
    is fine.
    
    It also changed mainboard.c to #include broadcom.c.  But broadcom.c is
    already in Makefile.inc, now building will fail because the linker gets
    broadcom_init() twice.
    
    Undo the change to mainboard.c but keep the change to broadcom.c.
    
    Change-Id: Ieccc098f477ffacccf4174056998034a220a9744
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/3012
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit c6f27226a84434182771dbbcd593d223072801f7
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 3 09:56:57 2013 -0500

    sandybridge: enable ROM caching
    
    If ROM caching is selected the sandybridge chipset code will
    will enable ROM caching after all other CPU threads are brought
    up.
    
    Change-Id: I3a57ba8753678146527ebf9547f5fbbd4f441f43
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3017
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 23f50166c64be0c1d3656ca67839843bf11a5274
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Apr 3 09:55:22 2013 -0500

    haswell: enable ROM caching
    
    If ROM caching is selected the haswell CPU initialization code
    will enable ROM caching after all other CPU threads are brought
    up.
    
    Change-Id: I75424bb75174bfeca001468c3272e6375e925122
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3016
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 13cc952a13ea29d9c5016a861d97da8326c87c4e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Apr 1 16:49:31 2013 -0500

    haswell: keep ROM cache enabled
    
    The MP code on haswell was mirroring the BSPs MTRRs. In addition it
    was cleaning up the ROM cache so that the MTRR register values were
    the same once the OS was booted. Since the hyperthread sibling of
    the BSP was going through this path the ROM cache was getting torn
    down once the hyperthread was brought up.
    
    That said, there was no differnce in observed boot time keeping the
    ROM cache enabled.
    
    Change-Id: I2a59988fcfeea9291202c961636ea761c2538837
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3008
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0f0fe100cb27770d615a70d5a78310ad47cb1abf
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Apr 1 15:40:45 2013 -0500

    haswell: use new interface to disable rom caching
    
    The haswell code was using the old assumption of which MTRR
    was used for the ROM cache. Now that there is an API for doing
    this use it as the old assumption is no longer valid.
    
    Change-Id: I59ef897becfc9834d36d28840da6dc4f1145b0c7
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/3007
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d46161e9eaaca8ec1d95f52461feb9647a99d5f3
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Mar 30 21:01:13 2013 +0100

    intel/microcode.h: Fix typo in comment: micr*o*code
    
    Introduced in commit »intel microcode: split up microcode loading
    stages« (98ffb426) [1].
    
    [1] http://review.coreboot.org/2778
    
    Change-Id: I626508b10f3998b43aaabd49853090b36f5d3eb0
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2992
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 64a7ed6dfae7e8d780930aad153f15e2c48753c3
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Wed Apr 3 17:02:58 2013 +0800

    Add PXE ROM selection to Kconfig menu
    
    Adding a pxe rom manually is inconvenient.
    With this patch, PXE ROM can be added automatically by selecting PXE_ROM in Kconfig.
    I have tested this patch on AMD Parmer and Thatcher with iPXE.
    iPXE would be a boot device in Seabios when pressing F12.
    iPXE works well with coreboot and Seabios.
    
    Change-Id: I2c4fc73fd9ae6c979f0af2290d410935f600e2c8
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/3013
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b81754becae18d54915a3d724ee5c0f1dfb096d5
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Apr 3 11:36:50 2013 +0200

    ASRock E350M1: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errors
    
    Now that the ASRock E350M1 builds without any warnings, remove the
    config option `WARNINGS_ARE_ERRORS` set to no by default from
    the file `Kconfig` so warnings are treated as errors to prevent
    code from being added in the future introducing warnings.
    
    Change-Id: Idfecfb1434158969334a4b37972b5fc6fd76e72a
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/3014
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit a8db717d4af799fabd26383e6a748de94318d280
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Mar 31 22:02:16 2013 +0200

    inteltool: Use `ll` instead of `l` as the length modifier for `uint64_t`
    
    When buidling inteltool with GCC, the following warning is printed.
    
        $ make
        […]
        gcc -O2 -g -Wall -W   -c -o memory.o memory.c
        memory.c: In function ‘print_mchbar’:
        memory.c:287:7: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t’ [-Wformat]
        […]
    
    This was introduced in commit »inteltool: Add support for H65 Express
    chipset« (c7fc4422) [1].
    
    Address this warning, by using `%llx` instead of `%lx`.
    
    [1] http://review.coreboot.org/1258
    
    Change-Id: I4f714edce7e8b405e1a7a417d02fa498322c88a8
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2994
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Tested-by: build bot (Jenkins)

commit aa3f7ba36ebe3a933aa664f826382f60b31e86f1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Mar 28 16:51:45 2013 -0700

    cbfstool: Replace C++ code with C code
    
    cbfstool was using a C++ wrapper around the C written LZMA functions.
    And a C wrapper around those C++ functions. Drop the mess and rewrite
    the functions to be all C.
    
    Change-Id: Ieb6645a42f19efcc857be323ed8bdfcd9f48ee7c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3010
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 60a4a73fcd7babd4819853542a5566293a097ed4
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Mar 28 16:46:07 2013 -0700

    cbfstool: fix --machine
    
    The help text says --machine, but the code
    actually checked for --arch. Fix it!
    
    Change-Id: Ib9bbf758b82ef070550348e897419513495f154b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/3009
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0499da98859332b739f2ee5ea3329f6f57b4db96
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Mar 29 19:55:56 2013 +0100

    ASRock E350M1: buildOpts.c: Add missing memory related defines
    
    When building the ASRock E350M1, the following warnings are shown.
    
        $ make # on Jenkins (build server)
        […]
            CC         mainboard/asrock/e350m1/buildOpts.romstage.o
        In file included from src/mainboard/asrock/e350m1/buildOpts.c:294:0:
        src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2071:6: warning: "DDR1333_FREQUENCY" is not defined [-Wundef]
        src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2071:40: warning: "DDR1866_FREQUENCY" is not defined [-Wundef]
        src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2089:5: warning: "TIMING_MODE_AUTO" is not defined [-Wundef]
        src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2089:31: warning: "TIMING_MODE_SPECIFIC" is not defined [-Wundef]
        src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2113:5: warning: "QUADRANK_UNBUFFERED" is not defined [-Wundef]
        src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2113:33: warning: "QUADRANK_UNBUFFERED" is not defined [-Wundef]
        src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2127:5: warning: "POWER_DOWN_BY_CHIP_SELECT" is not defined [-Wundef]
        src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h:2127:28: warning: "POWER_DOWN_BY_CHIP_SELECT" is not defined [-Wundef]
        […]
    
    Adding the corresponding defines as done for AMD Persimmon in
    
        commit d7a696d0f229abccc95ff411f28d91b9b796ab74
        Author: efdesign98 <efdesign98@gmail.com>
        Date:   Thu Sep 15 15:24:26 2011 -0600
    
            Persimmon updates for AMD F14 rev C0
    
            Reviewed-on: http://review.coreboot.org/137
    
    addresses the warnings.
    
    Change-Id: Id311b2dacdba5f2e6b4d834e43db0310213a35f9
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2962
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 032daad6975cb21da22eb5d7c4881aa808a0e4ba
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Jan 25 15:36:59 2013 +0100

    libpayload: cbfs_core.h: Add missing third person s in »it need*s*«
    
    Introduced in »libpayload: New CBFS to support multiple firmware
    media sources.« (d01d0368) [1].
    
    [1] http://review.coreboot.org/2191
    
    Change-Id: I9feb9ab49825744cd00d6392a526f7af0ed053d1
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2997
    Reviewed-by: Nico Huber <nico.huber@secunet.com>
    Tested-by: build bot (Jenkins)

commit 9c07c8f53db10e1c93f41e37a9ba8a246fa0336e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 22 11:08:39 2013 -0700

    lynxpoint: Move ACPI NVS into separate CBMEM table
    
    The ACPI NVS region was setup in place and there was a CBMEM
    table that pointed to it.  In order to be able to use NVS
    earlier the CBMEM region is allocated for NVS itself during
    the LPC device init and the ACPI tables point to it in CBMEM.
    
    The current cbmem region is renamed to ACPI_GNVS_PTR to
    indicate that it is really a pointer to the GNVS and does
    not actually contain the GNVS.
    
    Change-Id: I31ace432411c7f825d86ca75c63dd79cd658e891
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2970
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ebf142a12ce4911b766bd618483434519efba0d5
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 29 16:23:23 2013 -0500

    boot: add disable_cache_rom() function
    
    On certain architectures such as x86 the bootstrap processor
    does most of the work. When CACHE_ROM is employed it's appropriate
    to ensure that the caching enablement of the ROM is disabled so that
    the caching settings are symmetric before booting the payload or OS.
    
    Tested this on an x86 machine that turned on ROM caching. Linux did not
    complain about asymmetric MTRR settings nor did the ROM show up as
    cached in the MTRR settings.
    
    Change-Id: Ia32ff9fdb1608667a0e9a5f23b9c8af27d589047
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2980
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b39ba2efcfb0da48c8e7719d1c8db037b567a8bc
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 22 11:21:14 2013 -0700

    lynxpoint: Basic configuration of SerialIO devices
    
    This adds configuration of SerialIO devices in the Lynxpoint-LP
    chipset.  This includes DMA, I2C, SPI, UART, and SDIO controllers.
    
    There is assorted magic setup necessary for the devices and
    while it is similar for each device there are subtle differences
    in some register settings.
    
    These devices must be put into "ACPI Mode" in order to take
    advantage of S0ix.  When in ACPI mode the allocated PCI BARs
    must be passed to ACPI so it can be relayed to the OS.  When
    the devices are in ACPI mode BAR0+BAR1 is saved into ACPI NVS
    and then updated and returned when the OS calls _CRS.
    
    Note that is is not entirely complete yet.  We need to update
    the IASL compiler in our build environment to support ACPI 5.0
    in order to be able to pass the FixedDMA entries to the kernel.
    There are also no ACPI methods defined yet to do D0->D3->D0
    transitions for actually entering/exiting S0ix states.
    
    This is hard to test right now because our kernel does not support
    any of these devices in ACPI mode.  I was able to build and test
    the upstream bleeding-edge branch of the linux-pm git tree.  With
    that tree I was able to enumerate and load the driver for the
    DesignWare I2C driver and attempt to probe the I2C bus -- although
    there are no devices attatched.
    
    I am also able to see the resources from ACPI in /proc/iomem get
    reserved properly in the kernel.
    
    Change-Id: Ie311addd6a25f3b7edf3388fe68c1cd691a0a500
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2971
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9591210d2caaa356bce63528f48e3cb02f787136
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 22 11:22:24 2013 -0700

    wtm2: Enable SerialIO devices in ACPI mode
    
    This enables all of the SerialIO devices and sets the flag
    to put them in ACPI mode.
    
    Change-Id: I7436c47d26028e95bbefafc320854c7cc34a4d44
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2972
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a2d6a40480c97043e9126c0fbc9e1a79db22d408
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 22 11:24:45 2013 -0700

    lynxpoint: Fix LP clock gating setup for LPC
    
    This bit offset is incorrect and should only be set based
    on another bit in a different register.
    
    Change-Id: I6037534236e3a4a5d15e15011ed9b5040b435eaf
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2973
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0ce2b4368286df8267bfb290b206671825981248
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Mon Apr 1 13:45:44 2013 +0200

    Minor Kconfig help text fix
    
    I did not check what was once after the 'and'.
    
    Change-Id: I9f3f725bec281a94abdb2eeb692a96fecdebcc0c
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/2999
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0703ec4fb2f0342e88fa50dfae21710019774ad1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 27 00:16:11 2013 -0500

    chromeos: honor MOCK_TPM=1
    
    The TPM code wasn't previously honoring MOCK_TPM=1. Because of this,
    boards with TPMs that didn't handle S3 resume properly would cause a
    hard reset. Allow one to build with MOCK_TPM=1 on the command line so
    that S3 can still work.
    
    Change-Id: I9adf06647de285c0b0a3203d8897be90d7783a1e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2976
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d6d6db3717d09f2b6a4590eec6016ca7d417c2f9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 27 21:13:02 2013 -0500

    lynxpoint: fix enable_pm1() function
    
    The new enable_pm1() function was doing 2 things wrong:
    
    1. It was doing a RMW of the pm1 register. This means we were
       keeping around the enables from the OS during S3 resume. This
       is bad in the face of the RTC alarm waking us up because it would
       cause an infinite stream of SMIs.
    2. The register size of PM1_EN is 16-bits. However, the previous
       implementation was accessing it as a 32-bit register.
    
    The PM1 enables should only be set to what we expect to handle in the
    firmware before the OS changes to ACPI mode.
    
    Change-Id: Ib1d3caf6c84a1670d9456ed159420c6cb64f555e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2978
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bab0a0b577ba8cc28aa1e2b2e9ec65fb98edced1
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Mar 27 09:50:30 2013 +0100

    PDCurses: pdcscrn.c: Use `#ifdef` instead of `#if CONFIG_SPEAKER`
    
    Building libpayload with the PDCurses backend the following warning
    is shown.
    
        /src/coreboot/payloads/libpayload(master) $ make clean
        /src/coreboot/payloads/libpayload(master) $ make
        […]
            CC         curses/pdcurses-backend/pdcscrn.libcurses.o
        curses/pdcurses-backend/pdcscrn.c: In function 'PDC_scr_open':
        curses/pdcurses-backend/pdcscrn.c:75:5: warning: "CONFIG_SPEAKER" is not defined [-Wundef]
        […]
    
    The GCC documentation states [1]
    
        In some contexts this shortcut is undesirable. The -Wundef option
        causes GCC to warn whenever it encounters an identifier which is
        not a macro in an ‘#if’.
    
    and therefore use `#ifdef` [2] to silence this warning. No functional
    change is done, as `CONFIG_SPEAKER` is assigned the value `Y` when
    defined.
    
    There was some discussion going on the list [3], but my points in there
    turned out to be incorrect.
    
    [1] http://gcc.gnu.org/onlinedocs/cpp/If.html
    [2] http://gcc.gnu.org/onlinedocs/cpp/Ifdef.html
    [3] http://www.coreboot.org/pipermail/coreboot/2013-March/075561.html
    
    Change-Id: I8e9c9b5d01985b21ad05018986d614cf9bf2b439
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2934
    Reviewed-by: Nico Huber <nico.huber@secunet.com>
    Tested-by: build bot (Jenkins)

commit af3158c0cfd6034bbdc42a0488382c4be1a7a388
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 27 20:57:28 2013 -0500

    lynxpoint: split clearing and enabling of smm
    
    Previously southbridge_smm_init() was provided that did both
    the clearing of the SMM state and enabling SMIs. This is
    troublesome in how haswell machines bring up the APs. The BSP
    enters SMM once to determine if parallel SMM relocation is possible.
    If it is possible the BSP releases the APs to do SMM relocation.
    Normally, after the APs complete the SMM relocation, the BSP would then
    re-enter the relocation handler to relocate its own SMM space.
    However, because SMIs were previously enabled it is possible for an SMI
    event to occur before the APs are complete or have entered the
    relocation handler. This is bad because the BSP will turn off parallel
    SMM save state. Additionally, this is a problem because the relocation
    handler is not written to handle regular SMIs which can cause an
    SMI storm which effectively looks like a hung machine. Correct these
    issues by turning on SMIs after all the SMM relocation has occurred.
    
    Change-Id: Id4f07553b110b9664d51d2e670a14e6617591500
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2977
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9ebd8ea7cfd379cca56a2c48324bdfbe52ff6bab
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Mar 31 22:15:43 2013 +0200

    inteltool: Allow to override Makefile variables
    
    Allow to override the variables `CC`, `INSTALL`, `PREFIX`,
    `CFLAGS` and `LDFLAGS`. Though append `-lpci -lz` to `LDFLAGS`.
    
    This way for example a different compiler can easily be used.
    
        CC=clang make
    
    As a side note, Clang in contrast to GCC does *not* issue the
    following warnings.
    
        $ clang --version
        Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2)
        Target: i386-pc-linux-gnu
        Thread model: posix
        $ gcc --version
        gcc-4.7.real (Debian 4.7.2-15) 4.7.2
        Copyright (C) 2012 Free Software Foundation, Inc.
        This is free software; see the source for copying conditions.  There is NO
        warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
        $ make
        […]
        amb.c: In function ‘amb_read_config32’:
        amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        amb.c: In function ‘amb_read_config16’:
        amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        amb.c: In function ‘amb_read_config8’:
        amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
        […]
    
    These are only shown under 32-bit and not 64-bit
    
        $ uname -m
        i686
    
    and are going to be fixed in a separate patch.
    
    Change-Id: Id75dea081ecb35390f283520a7e5dce520f4c98d
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2996
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 42c5501c3941ce0ddfc14bcd5b9d02d73d4f4e30
Author: Nico Huber <nico.h@gmx.de>
Date:   Mon Apr 1 15:38:44 2013 +0200

    inteltool: Add Cougar/Panther Point GPIO defaults
    
    This adds default values for the GPIO setup on Intel's Cougar Point and
    Panther Point platform controller hubs (PCH). Values are taken from [1] and
    [2], respectively. I've tested this with an H77 PCH. See below for the
    output.
    
    [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
        Document-Number: 324645-006
    
    [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
        Datasheet
        Document-Number: 326776-003
    
    $ ./inteltool -G
    CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
    Northbridge: 8086:0150 (unknown)
    Southbridge: 8086:1e4a (H77)
    
    ========== GPIO DIFFS ===========
    
    GPIOBASE = 0x0500 (IO)
    
    gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
    gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
    gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
    
    gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
    gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
    gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
    
    gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
    gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
    gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
    
    gpiobase+0x002c: 0x00002000 (GPI_INV)
    gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
    gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
    
    gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
    gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
    gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
    
    gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
    gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
    gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
    
    gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
    gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
    gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
    
    gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
    gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
    gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
    
    gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
    gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
    gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
    
    gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
    gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
    gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
    
    gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
    
    $ ./inteltool -gG
    CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
    Northbridge: 8086:0150 (unknown)
    Southbridge: 8086:1e4a (H77)
    
    ============= GPIOS =============
    
    GPIOBASE = 0x0500 (IO)
    
    gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
    gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
    gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
    gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
    gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
    gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
    gpiobase+0x0008: 0x00000000 (RESERVED)
    gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
    gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
    gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
    gpiobase+0x0010: 0x00000000 (RESERVED)
    gpiobase+0x0014: 0x00000000 (RESERVED)
    gpiobase+0x0018: 0x00040000 (GPO_BLINK)
    gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
    gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
    gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
    gpiobase+0x0028: 0x0000     (GPI_NMI_EN)
    gpiobase+0x002a: 0x0000     (GPI_NMI_STS)
    gpiobase+0x002c: 0x00002000 (GPI_INV)
    gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
    gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
    gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
    gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
    gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
    gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
    gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
    gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
    gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
    gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
    gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
    gpiobase+0x003c: 0x00000000 (RESERVED)
    gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
    gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
    gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
    gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
    gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
    gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
    gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
    gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
    gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
    gpiobase+0x004c: 0x00000000 (RESERVED)
    gpiobase+0x0050: 0x00000000 (RESERVED)
    gpiobase+0x0054: 0x00000000 (RESERVED)
    gpiobase+0x0058: 0x00000000 (RESERVED)
    gpiobase+0x005c: 0x00000000 (RESERVED)
    gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
    gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
    gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
    gpiobase+0x006c: 0x00000000 (RESERVED)
    gpiobase+0x0070: 0x00000000 (RESERVED)
    gpiobase+0x0074: 0x00000000 (RESERVED)
    gpiobase+0x0078: 0x00000000 (RESERVED)
    gpiobase+0x007c: 0x00000000 (RESERVED)
    
    Change-Id: If99cf8d5c93e34ad28f52080fff64e01c220eb27
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3001
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 09dcbf0cdbae2e9a2b26f6753c290d8c70749bba
Author: Nico Huber <nico.h@gmx.de>
Date:   Mon Apr 1 15:08:04 2013 +0200

    inteltool: Add option to show differences in GPIO setup
    
    This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
    that differ from platform defaults. For differing registers, the current,
    the default, and an xor of the default and the current value is printed. A
    follow-up commit will add defaults for the Cougar/Panther Point platform
    controller hubs. If you specify both, -g and -G on the command line, all
    GPIO registers will be printed interleaved with the diff.
    
    Here's a preview:
    
    $ ./inteltool -G
    CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
    Northbridge: 8086:0150 (unknown)
    Southbridge: 8086:1e4a (H77)
    
    ========== GPIO DIFFS ===========
    
    GPIOBASE = 0x0500 (IO)
    
    gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
    gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
    gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
    
    gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
    gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
    gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
    
    gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
    gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
    gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
    
    gpiobase+0x002c: 0x00002000 (GPI_INV)
    gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
    gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
    
    gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
    gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
    gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
    
    gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
    gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
    gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
    
    gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
    gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
    gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
    
    gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
    gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
    gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
    
    gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
    gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
    gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
    
    gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
    gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
    gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
    
    gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
    
    $ ./inteltool -gG
    CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
    Northbridge: 8086:0150 (unknown)
    Southbridge: 8086:1e4a (H77)
    
    ============= GPIOS =============
    
    GPIOBASE = 0x0500 (IO)
    
    gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
    gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
    gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
    gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
    gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
    gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
    gpiobase+0x0008: 0x00000000 (RESERVED)
    gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
    gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
    gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
    gpiobase+0x0010: 0x00000000 (RESERVED)
    gpiobase+0x0014: 0x00000000 (RESERVED)
    gpiobase+0x0018: 0x00040000 (GPO_BLINK)
    gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
    gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
    gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
    gpiobase+0x0028: 0x0000     (GPI_NMI_EN)
    gpiobase+0x002a: 0x0000     (GPI_NMI_STS)
    gpiobase+0x002c: 0x00002000 (GPI_INV)
    gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
    gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
    gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
    gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
    gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
    gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
    gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
    gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
    gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
    gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
    gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
    gpiobase+0x003c: 0x00000000 (RESERVED)
    gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
    gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
    gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
    gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
    gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
    gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
    gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
    gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
    gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
    gpiobase+0x004c: 0x00000000 (RESERVED)
    gpiobase+0x0050: 0x00000000 (RESERVED)
    gpiobase+0x0054: 0x00000000 (RESERVED)
    gpiobase+0x0058: 0x00000000 (RESERVED)
    gpiobase+0x005c: 0x00000000 (RESERVED)
    gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
    gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
    gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
    gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
    gpiobase+0x006c: 0x00000000 (RESERVED)
    gpiobase+0x0070: 0x00000000 (RESERVED)
    gpiobase+0x0074: 0x00000000 (RESERVED)
    gpiobase+0x0078: 0x00000000 (RESERVED)
    gpiobase+0x007c: 0x00000000 (RESERVED)
    
    Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/3000
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d86a3a17e6fbf25e20e146aefd6925b943957bda
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Mar 28 13:46:16 2013 +0100

    Winbond W83627HF: Rename and move ASL snippet to `acpi/superio.asl`
    
    Put the ASL snippet for inclusion in the DSDT under the `acpi/`
    folder as it is done for the other Super I/O devices.
    
        $ find src/superio/ -name *asl
        src/superio/ite/it8772f/acpi/superio.asl
        src/superio/smsc/mec1308/acpi/superio.asl
        src/superio/smsc/sio1007/acpi/superio.asl
        src/superio/winbond/w83627hf/devtree.asl
    
    As there are no users of this file yet, no other adaptations need
    to be made.
    
    Change-Id: Id10cd8897592b780c9fd3bd6b45ada4cf1fcf33e
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2937
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6758c6887ec7daea9d14229ae674d899ba219166
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Mar 29 20:37:42 2013 +0100

    ASRock E350M1: mptable.c: Remove unused variable `dev`
    
    When building the ASRock E350M1, the following warning is shown.
    
        $ make # on Jenkins (build server)
        […]
            CC         mainboard/asrock/e350m1/mptable.ramstage.o
        src/mainboard/asrock/e350m1/mptable.c:64:12: warning: unused variable 'dev' [-Wunused-variable]
        […]
    
    Removing the variable `dev` addresses the warning.
    
    The same change was done in the following commit for the
    AMD Persimmon board.
    
        commit d7a696d0f229abccc95ff411f28d91b9b796ab74
        Author: efdesign98 <efdesign98@gmail.com>
        Date:   Thu Sep 15 15:24:26 2011 -0600
    
            Persimmon updates for AMD F14 rev C0
    
            Reviewed-on: http://review.coreboot.org/137
    
    Change-Id: I83f4630cb6ab1e4c95d04b4e8423850ed1858e45
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2965
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cd966dd075c5dbe5987bf8618d0ebe430cc331ac
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Mar 29 20:20:56 2013 +0100

    ASRock E350M1: mptable.c: Include `cpu/amd/amdfam14.h` for `get_bus_conf`
    
    When building the ASRock E350M1, the following warning is shown.
    
        $ make # on Jenkins (build server)
        […]
            CC         mainboard/asrock/e350m1/mptable.ramstage.o
        src/mainboard/asrock/e350m1/mptable.c: In function 'smp_write_config_table':
        src/mainboard/asrock/e350m1/mptable.c:58:3: warning: implicit declaration of function 'get_bus_conf' [-Wimplicit-function-declaration]
        […]
    
    Including the header file `cpu/amd/amdfam14.h` declaring the
    function addresses this warning.
    
    The same change was done in the following commit for the
    AMD Persimmon board.
    
        commit d7a696d0f229abccc95ff411f28d91b9b796ab74
        Author: efdesign98 <efdesign98@gmail.com>
        Date:   Thu Sep 15 15:24:26 2011 -0600
    
            Persimmon updates for AMD F14 rev C0
    
            Reviewed-on: http://review.coreboot.org/137
    
    Change-Id: I7912571fa57f6512b10fc9b5845427fcb6eb50c0
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2966
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 22bbb6942181771381081ef88089552a0408754a
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Mar 29 15:39:54 2013 +0100

    ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite`
    
    When building the ASRock E350M1, the following warning is shown.
    
        $ make # on Jenkins (build server)
        […]
            CC         mainboard/asrock/e350m1/mainboard.ramstage.o
        src/mainboard/asrock/e350m1/mainboard.c: In function 'mainboard_enable':
        src/mainboard/asrock/e350m1/mainboard.c:63:2: warning: implicit declaration of function 'pm_iowrite' [-Wimplicit-function-declaration]
        […]
    
    This warning was introduced by moving the initialization of the
    ASF registers using `pm_iowrite` to `mainboard.c` in
    
        commit db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3
        Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
        Date:   Thu Mar 21 22:21:28 2013 +0100
    
            Asrock E350M1: Use SPD read code from F14 wrapper
    
            Reviewed-on: http://review.coreboot.org/2875
    
    and is fixed by including `southbridge/amd/cimx/cimx_util.h`
    declaring `pm_iowrite`.
    
    Note, that the other AMD SB800 based boards seem to use the
    header file `southbridge/amd/sb800/sb800.h`, so no warning is shown
    for those. But since the CIMx SB800 code is used, the routines
    from the CIMx directory are more appropriate to declare these functions.
    
    So delete the commented out include line for this header too.
    
    Change-Id: I179aad5157c5a91294339a3e7b6c4c1715c6f099
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2957
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5ed986b8ab6bbcf1dfcb7d43ab9d9c8c4bf2f60f
Author: Nico Huber <nico.h@gmx.de>
Date:   Fri Mar 29 19:00:37 2013 +0100

    inteltool: Support PM registers on Cougar/Panther Point
    
    This adds the power management register definitions for Intel's Cougar
    Point and Panther Point platform controller hubs (PCH). The definitions
    are actually a subset of the older ICH10R registers: I've added just
    those that are mentioned in the public specifications in [1] and [2].
    I've tested dumping with an H77 PCH.
    
    NM70 is missing in [1]. Therefore, I didn't add it here.
    
    [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
        Document-Number: 324645-006
    
    [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
        Datasheet
        Document-Number: 326776-003
    
    Change-Id: Ia6945fe96cd96b568ed5191e91dbba5556e1ee95
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/2985
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 82d2d442c05255b073c97f78810de17101299602
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 29 16:37:18 2013 -0500

    wtm2: select write-combining memory for graphics
    
    Auto-select marking the graphics memory as write-combining.
    
    Change-Id: Icf61c5cbd129a97a106f0aaeca4e010d4799b4b8
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2981
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 13a97f5f4112c93878d483b61e2827adf7e0b44a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 29 16:38:01 2013 -0500

    link: select write-combining memory for graphics
    
    Auto-select marking the graphics memory as write-combining.
    
    Change-Id: I0b913f0b318bf57275643d3cfb5bc54ca8a005f5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2982
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ce872cb9afd55bc7bee8ebf08319e1400c860e71
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Mar 28 15:59:19 2013 -0500

    pci: don't load vga option rom before S3 check
    
    The pci device code was probing and loading the option rom before
    it did the S3 resume check for VGA option roms. Instead move this
    check before probing and loading so that we don't unnecessarily
    do work.
    
    Change-Id: If2e62d0c0e4b34b4f1bcd56ebcb9d3f54c6d0d24
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2979
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 8b5b764af6562235823f03c04e8184f048ab6320
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Wed Feb 13 11:07:38 2013 +0100

    console: Make use of CONFIG_USE_OPTION_TABLE
    
    It makes much more sense to use CONFIG_USE_OPTION_TABLE instead
    of CONFIG_HAVE_CMOS_DEFAULT. As we want to read the used
    debug_level from our CMOS. This change makes it possible to
    change log_debug via nvramtool and make use of the new
    value after a reboot/poweroff.
    
    CONFIG_HAVE_CMOS_DEFAULT does have an other meaning
    
    Change-Id: I438dd01a2b4171dba2b73f2001511c71f4317725
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/2381
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d2be1f11e11b68d88f9065ae75f32d7982cc3fe6
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Mar 11 13:17:27 2013 -0600

    AMD hudson & SB800 - Fix issues with mawk
    
    When calculating the offsets of the various binary blobs within the
    coreboot.rom file, we noticed that using mawk as the awk tool instead
    of using gawk led to build issues.  This was finally traced to the
    maximum value of the unsigned long variables within mawk - 0x7fff_ffff.
    Because we were doing calculations on values up in the 0xffxxxxxx
    range, these numbers would either be turned into floating point values
    and printed using scientific notation, or truncated at 0x7fff_ffff.
    
    To fix this, we print the values out as floating point, with no decimal
    digits.  This works in gawk, mawk, and original-awk and as the testing
    below show, seems to be the best way to do this.
    
    printf %u 0xFFFFFFFF | awk '{printf("%.0f %u %d", $1 , $1 , $1 )}'
    mawk:         4294967295 2147483647 2147483647
    original-awk: 4294967295 2147483648 4294967295
    gawk:         4294967295 4294967295 4294967295
    
    The issue of %d not matching gawk and original-awk has been reported
    to ubuntu.
    
    In the future, I'd recommend that whenever awk is used, a format is
    specified. It doesn't seem that we can count on the representation
    being the same between the different versions.
    
    Change-Id: I7b6b821c8ab13ad11f72e674ac726a98e8678710
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2628
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d0d7e7d7619e469dc936a579a6ce2adee9425ca6
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 22 11:05:38 2013 -0700

    lynxpoint: Rework ACPI NVS to add new SerialIO variables
    
    This reclaims space in ACPI NVS by removing unused fields and
    adds new fields for SerialIO BARs which will be used to communicate
    the allocated resources to ACPI.
    
    Change-Id: I002bf396cf7b495bc5b7e54b741527e507aff716
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2969
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f6763db83e7cf45f1ece8c1c8ecefe2b6a9f886d
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 22 11:01:37 2013 -0700

    wtm1/wtm2/baskingridge: Enable TPM ACPI device
    
    This enables the TPM device in ACPI tables so the OS is able
    to probe for the TPM without needing it be force loaded.
    
    Change-Id: I21e660ac1c12e3e1341cf266cf8f0bf03763df5a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2968
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 08e3656b517cf029dec5f9830c2e09b947e46e8b
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Mar 25 15:02:29 2013 -0700

    armv7: import updated cache/MMU stuff from coreboot
    
    This imports the newest cache and MMU code from coreboot. This
    time it's so new that it hasn't even been checked in to coreboot.
    
    However, this version at least allows DMA to work properly for the
    MSHC driver. So even if we rebase a few more times, this version is
    at least a step in the right direction.
    
    Note: This omits the stuff that sets up dcache policy since
    libpayload should not need to worry about that and it depends
    on cbmem stuff.
    
    Change-Id: Idd42b083e8019634aaaa44d5bf5b51db6c3912f5
    Signed-off-by: David Hendricks <dhendrix@google.com>
    Reviewed-on: http://review.coreboot.org/2975
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 2fba5e27d4aa2cb8f0c96b5e8fb8479f249e8ff8
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 14 19:06:11 2013 -0700

    armv7: import new cache maintenance API from coreboot
    
    This imports the new cache maintenance API from coreboot at
    commit bba8090. This is a BSD-licensed implementation which
    exposes cache maintenance opertaions necessary for payloads
    for things such as DMA transfers.
    
    Change-Id: I554676db89517bebc6edae4f7ab7e5882e6f986d
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2974
    Tested-by: build bot (Jenkins)

commit bc073f4a545e883f4af3971904ac23b2ad2bd1a3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Mar 28 16:30:56 2013 +0200

    x86: Drop BOARD_HAS_FADT
    
    There is a wildcard rule to include mainboard/fadt.c.
    
    Change-Id: I7f59d6b241c683b62c2c41c5795e45184882635e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/2940
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 14290b3cbb4428cc6416d087433e9be09605ab17
Author: Nico Huber <nico.h@gmx.de>
Date:   Fri Mar 29 19:08:39 2013 +0100

    inteltool: Add Cougar/Panther Point IDs to rootcmplx.c
    
    This adds the PCI IDs of Intel's Cougar Point and Panther Point platform
    controller hubs (PCH) to the dumping of the root complex configuration
    under the root complex base address (RCBA). Those PCHs are handled exactly
    as the older ICHs which can be seen in [1] and [2]. I've tested dumping
    with an H77 PCH.
    
    NM70 is missing in [1]. Therefore, I didn't add it here.
    
    [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
        Document-Number: 324645-006
    
    [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
        Datasheet
        Document-Number: 326776-003
    
    Change-Id: I2296caae57e614171300362d41715deecec77762
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/2986
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit f0813bb7edabd4e6df810782c843b73d3d8f55fd
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Mar 29 15:59:13 2013 +0100

    AMD Hudson boards: Use `hudson.h` for `pm_ioread` and delete `pmio.h`
    
    Unfortunately, an unneeded mainboard specific `pmio.h` was created
    when merging the AMD Parmer and Thatcher ports.
    
    Rudolf used the header from a more generic location
    
        southbridge/amd/agesa/hudson/hudson.h
    
    doing the the ASUS F2A85-M port, but did not delete the `pmio.h`
    now unused `pmio.h` header file.
    
    So adapt AMD Parmer and Thatcher to use the Hudson one as done for
    the ASUS F2A85-M and delete the now unused mainboard specific header
    file `pmio.h` to avoid duplication.
    
    Change-Id: I961cd145ebc3b83e31c638ac453ac95ee19c18db
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2958
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 20ed4b7bf3fd8d270f28d7ea35ba03b3861f58a0
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Mar 29 14:36:33 2013 +0100

    ASRock E350M1: irq_tables.c: Include `cpu/amd/amdfam14.h` for `get_bus_conf`
    
    When building the ASRock E350M1, the following warning is shown.
    
        $ make # on Jenkins (build server)
        […]
            CC         mainboard/asrock/e350m1/irq_tables.ramstage.o
        src/mainboard/asrock/e350m1/irq_tables.c: In function 'write_pirq_routing_table':
        src/mainboard/asrock/e350m1/irq_tables.c:64:2: warning: implicit declaration of function 'get_bus_conf' [-Wimplicit-function-declaration]
        […]
    
    Including the header file `cpu/amd/amdfam14.h` declaring the
    function addresses this warning.
    
    The same change was done in the following commit for the
    AMD Persimmon board.
    
        commit d7a696d0f229abccc95ff411f28d91b9b796ab74
        Author: efdesign98 <efdesign98@gmail.com>
        Date:   Thu Sep 15 15:24:26 2011 -0600
    
            Persimmon updates for AMD F14 rev C0
    
            Reviewed-on: http://review.coreboot.org/137
    
    Change-Id: I40b5735feb7116961ca0c4d6940ec55cdf42d3c6
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2956
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 21204600378d71655f90c781d400c0249d1cd284
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Mar 29 13:23:31 2013 +0100

    ASRock E350M1: get_bus_conf.c: Include `agesawrapper.h` for `agesawrapper_amdinitlate`
    
    When building the ASRock E350M1, the following warning is shown.
    
        $ make # on Jenkins (build server)
        […]
            CC         mainboard/asrock/e350m1/get_bus_conf.ramstage.o
        src/mainboard/asrock/e350m1/get_bus_conf.c: In function 'get_bus_conf':
        src/mainboard/asrock/e350m1/get_bus_conf.c:82:3: warning: implicit declaration of function 'agesawrapper_amdinitlate' [-Wimplicit-function-declaration]
        […]
    
    Including the header file `agesawrapper.h` declaring the function
    `agesawrapper_amdinitlate` fixes this warning.
    
    All AMD Family 14 based boards already include that header file. For
    example for the board AMD Persimmon the following patch fixed this
    warning.
    
        commit d7a696d0f229abccc95ff411f28d91b9b796ab74
        Author: efdesign98 <efdesign98@gmail.com>
        Date:   Thu Sep 15 15:24:26 2011 -0600
    
            Persimmon updates for AMD F14 rev C0
    
            Reviewed-on: http://review.coreboot.org/137
    
    Change-Id: I695420b7071e07cb7d4667b2479b9a26ea13723d
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2955
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit e4807f30c50df8302f3ed34bad2febf073f85ab3
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Mar 29 12:51:31 2013 +0100

    ASRock E350M1: PlatformGnbPcie.c: Do not return anything for void return type
    
    When building the ASRock E350M1, the following warning is shown.
    
        $ make # on Jenkins (build server)
        […]
            CC         mainboard/asrock/e350m1/PlatformGnbPcie.romstage.o
            CC         mainboard/asrock/e350m1/agesawrapper.romstage.o
            CC         mainboard/asrock/e350m1/buildOpts.romstage.o
        src/mainboard/asrock/e350m1/PlatformGnbPcie.c: In function 'OemCustomizeInitEarly':
        src/mainboard/asrock/e350m1/PlatformGnbPcie.c:131:5: warning: 'return' with a value, in function returning void [enabled by default]
        […]
    
    The function signature is (the return type might not be part of this though [1]),
    
        VOID
        OemCustomizeInitEarly (
          IN  OUT AMD_EARLY_PARAMS    *InitEarly
          )
    
    so do not return anything.
    
    All other AMD Family 14 boards already have the correct code. For example
    following commit fixed this for AMD Persimmon.
    
        commit d7a696d0f229abccc95ff411f28d91b9b796ab74
        Author: efdesign98 <efdesign98@gmail.com>
        Date:   Thu Sep 15 15:24:26 2011 -0600
    
            Persimmon updates for AMD F14 rev C0
    
            Reviewed-on: http://review.coreboot.org/137
    
    [1] http://cboard.cprogramming.com/cplusplus-programming/117286-what-exactly-function-signature.html
    
    Change-Id: Ie60246bd9bb8452efd096e6838d8610f6364a6aa
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2954
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 1877ceed212b586f13277b4b2057598d39b78894
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Mar 29 15:40:34 2013 -0700

    armv7: change some unsigned ints to uint32_t
    
    Use register-sized types in case the inline assembler doesn't do
    so automatically.
    
    Change-Id: I3202ba972ef2548323fe557f45dc4b0b1cf6c818
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2983
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Gabe Black <gabe.black@gmail.com>
    Tested-by: build bot (Jenkins)

commit 58779358362ef0c9ed433c310416a93c8b9c9211
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Mar 29 13:40:09 2013 -0700

    armv7: remove loop from dcache_mmu_disable()
    
    dcache_mmu_disable() no longer needs to have its own iterative loop
    to select each cache level of cache since
    dcache_clean_invalidate_all() does that now.
    
    Change-Id: I5ca273f98943981b943c1c1622f4574d7133fb50
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2967
    Reviewed-by: Gabe Black <gabe.black@gmail.com>
    Tested-by: build bot (Jenkins)

commit 26e8f2fe0125cc6e7727d024bf4bfbd6231c8b27
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 28 19:05:29 2013 -0700

    snow: explicitly configure L2 cache
    
    This adds a call to explicitly configure L2 cache (though defaults
    should be set correctly).
    
    Change-Id: I120e29c986918c2904a0332e46fcf9f1c5380d85
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2950
    Reviewed-by: Gabe Black <gabe.black@gmail.com>
    Tested-by: build bot (Jenkins)

commit c01d1380138e807fa941976d9f102fb1b200ad01
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 28 19:04:58 2013 -0700

    exynos5250: Add function for configuring L2 cache
    
    This adds a new function to configure L2 cache for the
    exynos5250 and deprecates the old function.
    
    Change-Id: I9562f3301aa1e2911dae3856ab57bb6beec2e224
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2949
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Gabe Black <gabe.black@gmail.com>
    Tested-by: build bot (Jenkins)

commit bae3f062457cf52da8e06e6abebfb99084411646
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Mar 28 13:03:38 2013 +0100

    AMD CIMx SB800: Update Kconfig help texts to new SATA mode default
    
    In the following commit
    
        commit ee5c111755ac4acc6dfb6e10a4e271211e149a39
        Author: Paul Menzel <paulepanter@users.sourceforge.net>
        Date:   Tue Mar 12 12:41:40 2013 +0100
    
            AMD CIMx SB800: Enable AHCI mode for SATA controller by default
    
            Reviewed-on: http://review.coreboot.org/2661
    
    I forgot to update the help texts to the new SATA mode default. Do
    so now.
    
    Additionally note that help texts for `choice` do not seem to be
    shown.
    
    Change-Id: I17f401633a2136efca2b21a621482e0724ff9f04
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2936
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit be2c6340b3ce8e48a40724ef8136eb3c80ef4448
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Mar 28 11:44:19 2013 +0100

    superiotool: Allow to override Makefile variables `CC`, `INSTALL` and `PREFIX`
    
    This way for example a different compiler can easily be used.
    
        CC=clang make
    
    Change-Id: I50b83554fd4826d00d87e60a30eb1f6a88834397
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2935
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e85f4eb1b0f63535ceb36315712a03d7d7f656ac
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 26 21:34:01 2013 -0700

    armv7: update sync barrier usage in dcache_op_set_way()
    
    This moves the dsb() before the loop to sync any outstanding memory
    accesses, and adds an isb() after the loop to ensure all outstanding
    instructions are completed.
    
    Change-Id: I1a11b39f104ae780370cfd2db3badcf4e91dc017
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2929
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dc82fc563486794005ada364f498167df9b686d6
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 29 14:36:10 2013 -0500

    wtm2: auto-select CACHE_ROM
    
    The WTM2 board has a fairly static configuration. As such
    it's been tested to properly handle CACHE_ROM given the number
    of MTRRs the boards' CPUs supports.
    
    Change-Id: Ic67cd1eebce580003dc6b6655cac2b2a92dd1b5f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2964
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b5146b394a11642649d7645be97ad5c5f8e2892e
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Mar 29 11:17:25 2013 +0100

    AMD Inagua: Kconfig: Remove `WARNINGS_ARE_ERRORS` to treat warnings as errors
    
    Now that the AMD Inagua builds without any warnigs, remove the
    config option `WARNINGS_ARE_ERRORS` set to no by default from
    the file `Kconfig` so warnings are treated as errors to prevent
    code from being added in the future introducing warnings.
    
    Change-Id: I0b58bd74b06dc54d180b16d6a207354b5fea0d0f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2953
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5d7415673f93ddac743de71fb2272fccdd7300fb
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Mar 29 11:07:22 2013 +0100

    AMD Inagua: broadcom.c: Add missing prototype for `broadcom_init()`
    
    Building the AMD Inagua board, the following warning is thrown.
    
            CC         mainboard/amd/inagua/get_bus_conf.ramstage.o
        src/mainboard/amd/inagua/broadcom.c:319:6: warning: no previous prototype for 'broadcom_init' [-Wmissing-prototypes]
    
    This warning was introduced by commit 3926b4c5.
    
        commit 3926b4c520e74da9dc22e3d136a8a178483e0d25
        Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
        Date:   Fri Mar 1 19:41:41 2013 +0100
    
            AMD Inagua: add GEC firmware, document Broadcom BCM57xx Selfboot Patch format
    
            Reviewed-on: http://review.coreboot.org/2831
    
    Adding the prototype to `broadcom.c` and removing it from
    `mainboard.c` fixes the warning.
    
    Change-Id: I1da0c4e972e129047dd8230d573f1c43fd71eb20
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2952
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6983a6829ab20f31f351f39e6421710935c6a744
Author: Nico Huber <nico.h@gmx.de>
Date:   Fri Mar 29 18:08:13 2013 +0100

    inteltool: Support GPIO registers on Cougar/Panther Point
    
    This adds the GPIO register definitions for Intel's Cougar Point and
    Panther Point platform controller hubs (PCH). All information is taken
    from the public specifications in [1] and [2]. I've tested it with an
    H77 PCH.
    
    NM70 is missing in [1]. Therefore, I didn't add it here.
    
    [1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
        Document-Number: 324645-006
    
    [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
        Datasheet
        Document-Number: 326776-003
    
    Change-Id: I31711e24f852e68b3c113e3bd9243dc7e89ac197
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/2961
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 76d60494ef97399d4233f398be5814574f1d4a1b
Author: Nico Huber <nico.h@gmx.de>
Date:   Fri Mar 29 17:57:15 2013 +0100

    inteltool: Add definitions for Cougar/Panther Point PCI IDs
    
    This adds correspondings #defines for the PCI IDs of the LPC device on
    Intel's Cougar Point and Panther Point platform controller hubs. Those
    will be used more in later commits.
    
    I've checked all those IDs against the specification updates [1] and [2].
    
    [1] Intel 6 Series Chipset and Intel C200 Series Chipset Specification
        Update
        Document-Number: 324646-019
    
    [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)
        Family - Datasheet Specification Update
        Document-Number: 326777-010
    
    Change-Id: Ibef5a30d283c568c345eb8d8149723e7a3049272
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/2960
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2c2a85fc6d107265716bad930e7505fc87a52a1f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 29 14:33:03 2013 -0500

    google boards: auto-select CACHE_ROM
    
    Automatically select CACHE_ROM for all Google boards.
    Tested by generating a config for the link board. CACHE_ROM
    was selected and was unable to unselect it using
    'make oldconfig'.
    
    Change-Id: I8e34207e3929a020bb0280657f95ba7a000ad024
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2963
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 53924240be1c4ebc57282d7903e82f447ba2eb6b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 29 11:48:27 2013 -0500

    x86: mtrr: optimize hole carving above 4GiB
    
    There is an optimization that can take place when hole
    carving in ranges above 4GiB. If the range is the last
    range then there is no need to carve UC holes out from
    the larger WB range.
    
    This optimization also has the same assumption of choosing
    WB as the default MTRR type: the OS needs to properly
    handle accessing realloacted MMIO resources with PAT so
    that the MTRR type can be overidden.
    
    Below are results using a combination of options. The
    board this was tested on has 10 variable MTRRs at its
    disposal. It has 4GiB of RAM.
    
    IO hole config #1: hole starts at 0xad800000
    
    No CACHE_ROM and no WRCOMB resources (takes 4 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x0000000100000000 size 0x52800000 type 0
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 4/6.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
    MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
    
    No CACHE_ROM and 1 WRCOMB resource (takes 6 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 6/7.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
    MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
    MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
    
    CACHE_ROM and no WRCOMB resources (takes 7 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000ff800000 size 0x52000000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 11/7.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6
    MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6
    MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 5 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 6 base 0x0000000100000000 mask 0x0000007f00000000 type 6
    
    CACHE_ROM and 1 WRCOMB resource (takes 8 MTRRs):
    Previously this combination was impossible without the optimization.
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 12/8.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6
    MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6
    MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 5 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 6 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 7 base 0x0000000100000000 mask 0x0000007f00000000 type 6
    
    IO hole config #1: hole starts at 0x80000000
    
    No CACHE_ROM and no WRCOMB resources (takes 1 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x0000000100000000 size 0x80000000 type 0
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 1/2.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x0000000080000000 mask 0x0000007f80000000 type 0
    
    No CACHE_ROM and 1 WRCOMB resource (takes 3 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 4/3.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6
    
    CACHE_ROM and no WRCOMB resources (takes 3 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000ff800000 size 0x7f800000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 9/3.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6
    
    CACHE_ROM and 1 WRCOMB resource (takes 4 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 10/4.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 2 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 3 base 0x0000000100000000 mask 0x0000007f00000000 type 6
    
    Change-Id: Ia3195af686c3f0603b21f713cfb2d9075eb02806
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2959
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e383442943344f3a14b97e5625a8223f73cac5b0
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Mar 28 20:48:51 2013 -0500

    x86: mtrr: add hole punching support
    
    Some ranges would use less variable MTRRs if an UC area
    can be carved off the top of larger WB range. Implement this
    approach by doing 3 passes over each region in the addres space:
      1. UC default type. Cover non-UC and non-WB regions with respectie type.
         Punch UC hole at upper end of larger WB regions with WB type.
      2. UC default type. Cover non-UC regions with respective type.
      3. WB default type. Cover non-WB regions with respective type.
    The hole at upper end of a region uses the same min alignment of 64MiB.
    
    Below are results using a combination of options. The board this was
    tested on has 10 variable MTRRs at its disposal. It has 4GiB of RAM.
    
    IO hole config #1: hole starts at 0xad800000
    
    No CACHE_ROM or WRCOMB resources (takes 4 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x0000000100000000 size 0x52800000 type 0
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 4/9.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
    MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
    
    No CACHE_ROM. 1 WRCOMB resource (takes 6 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 6/10.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
    MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
    MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
    
    CACHE_ROM and no WRCOMB resources (taks 10 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000ff800000 size 0x52000000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 11/10.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6
    MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6
    MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 5 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 6 base 0x0000000100000000 mask 0x0000007fc0000000 type 6
    MTRR: 7 base 0x0000000140000000 mask 0x0000007ff0000000 type 6
    Taking a reserved OS MTRR.
    MTRR: 8 base 0x000000014f600000 mask 0x0000007fffe00000 type 0
    Taking a reserved OS MTRR.
    MTRR: 9 base 0x000000014f800000 mask 0x0000007fff800000 type 0
    
    A combination of CACHE_ROM and WRCOMB just won't work.
    
    IO hole config #2: hole starts at 0x80000000:
    
    No CACHE_ROM or WRCOMB resources (takes 1 MTRR):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x0000000100000000 size 0x80000000 type 0
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 1/5.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x0000000080000000 mask 0x0000007f80000000 type 0
    
    No CACHE_ROM. 1 WRCOMB resource (takes 4 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 4/6.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x0000000080000000 mask 0x0000007fc0000000 type 0
    MTRR: 1 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
    MTRR: 2 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 3 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
    
    CACHE_ROM and no WRCOMB resources (takes 6 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000ff800000 size 0x7f800000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 9/6.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 2 base 0x0000000100000000 mask 0x0000007f80000000 type 6
    MTRR: 3 base 0x000000017ce00000 mask 0x0000007fffe00000 type 0
    MTRR: 4 base 0x000000017d000000 mask 0x0000007fff000000 type 0
    MTRR: 5 base 0x000000017e000000 mask 0x0000007ffe000000 type 0
    
    CACHE_ROM and 1 WRCOMB resource (takes 7 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 10/7.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 2 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 3 base 0x0000000100000000 mask 0x0000007f80000000 type 6
    MTRR: 4 base 0x000000017ce00000 mask 0x0000007fffe00000 type 0
    MTRR: 5 base 0x000000017d000000 mask 0x0000007fff000000 type 0
    MTRR: 6 base 0x000000017e000000 mask 0x0000007ffe000000 type 0
    
    Change-Id: Iceb9b64991accf558caae2e7b0205951e9bcde44
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2925
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f6f6e13c46a4320f03fdf1286e37e05a8d047e56
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 26 21:22:42 2013 -0500

    memrange: add 2 new range_entry routines
    
    Two convenience functions are added to operate on a range_entry:
    - range_entry_update_tag() - update the entry's tag
    - memranges_next_entry() - get the next entry after the one provide
    
    These functions will be used by a follow on patch to the MTRR code
    to allow hole punching in WB region when the default MTRR type is
    UC.
    
    Change-Id: I3c2be19c8ea1bbbdf7736c867e4a2aa82df2d611
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2924
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e63d5d83e438ac3710f68f9cddddd5f1e294dbf6
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 26 14:52:04 2013 -0500

    chromeos: remove CACHE_ROM automatic selection
    
    It's not appropriate for the chromeos Kconfig to automatically
    select CACHE_ROM. The reason is that enabling CACHE_ROM is
    dependent on the board and chipset atrributes.
    
    Change-Id: I47429f1cceefd40226c4b943215d627a3c869c7b
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2921
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a09760eb451466c7972614ef9d73752e16a1bf69
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 26 13:34:37 2013 -0500

    libpayload: add x86 ROM variable MTRR support
    
    On x86, coreboot may allocate a variable range MTRR for enabling caching
    of the system ROM. Add the ability to parse this structure and add the
    result to the sysinfo structure.
    
    An example usage implementation would be to obtain the variable MTRR
    index that covers the ROM from the sysinfo structure. Then one would
    disable caching and change the MTRR type from uncacheable to
    write-protect and enable caching. The opposite sequence is required
    to tearn down the caching.
    
    Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2920
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bc07f5d93552640793254ce003937ec646120a21
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 26 13:09:39 2013 -0500

    x86: add rom cache variable MTRR index to tables
    
    Downstream payloads may need to take advantage of caching the
    ROM for performance reasons. Add the ability to communicate the
    variable range MTRR index to use to perform the caching enablement.
    
    An example usage implementation would be to obtain the variable MTRR
    index that covers the ROM from the coreboot tables. Then one would
    disable caching and change the MTRR type from uncacheable to
    write-protect and enable caching. The opposite sequence is required
    to tearn down the caching.
    
    Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2919
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f567f16af4c3cbfcadc3bc5c44b569a592829262
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 22:25:37 2013 -0500

    sandybridge: add option to mark graphics memory write-combining.
    
    The graphics memory can be accessed in a faster manner by
    setting it to write-combing mode.  Add an option to enable
    write-combining for the graphics memory.
    
    Change-Id: I7d37fd78906262aabef92c2b4f4cab0e3f7e4f6d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2894
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fcfe67c3b2b3391a8131eb26cc546a9afaa28822
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 22:23:05 2013 -0500

    haswell: add option to mark graphics memory write-combining.
    
    The graphics memory can be accessed in a faster manner by
    setting it to write-combing mode. Add an option to enable
    write-combining for the graphics memory.
    
    Change-Id: I797fcd9f0dfb074f9e45476773acbfe614eb4b0a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2893
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 77a5b4046ab7e7bee887990b342a7356554fd391
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 26 12:47:47 2013 -0500

    x86: mtrr: add CONFIG_CACHE_ROM support
    
    The CONFIG_CACHE_ROM support in the MTRR code allocates an MTRR
    specifically for setting up write-protect cachine of the ROM. It is
    assumed that CONFIG_ROM_SIZE is the size of the ROM and the whole
    area should be cached just under 4GiB. If enabled, the MTRR code
    will allocate but not enable rom caching. It is up to the callers
    of the MTRR code to explicitly enable (and disable afterwards) through
    the use of 2 new functions:
    - x86_mtrr_enable_rom_caching()
    - x86_mtrr_disable_rom_caching()
    
    Additionally, the CACHE_ROM option is exposed to the config menu so
    that it is not just selected by the chipset or board. The reasoning
    is that through a multitude of options CACHE_ROM may not be appropriate
    for enabling.
    
    Change-Id: I4483df850f442bdcef969ffeaf7608ed70b88085
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2918
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9b027fe5b028011593c98d2af8727199b74d3e4c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 26 14:10:34 2013 -0500

    mtrr: honor IORESOURCE_WRCOMB
    
    All resources that set the IORESOURCE_WRCOMB attribute which are
    also marked as IORESOURCE_PREFETCH will have a MTRR set up that
    is of the write-combining cacheable type. The only resources on
    x86 that can be set to write-combining are prefetchable ones.
    
    Change-Id: Iba7452cff3677e07d7e263b79982a49c93be9c54
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2892
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a05a8522ce1dd90c6d667b70bafb24757a27c656
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 20:44:46 2013 -0500

    lib: add memrange infrastructure
    
    The memrange infrastructure allows for keeping track of the
    machine's physical address space. Each memory_range entry in
    a memory_ranges structure can be tagged with an arbitrary value.
    It supports merging and deleting ranges as well as filling in
    holes in the address space with a particular tag.
    
    The memrange infrastructure will serve as a shared implementation
    for address tracking by the MTRR and coreboot mem table code.
    
    Change-Id: Id5bea9d2a419114fca55c59af0fdca063551110e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2888
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3ece5ac40c66c78b4abce74eeec6521ad661c53c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Mar 28 16:17:11 2013 -0500

    stdlib: add ALIGN_UP and ALIGN_DOWN macros
    
    There wasn't an equivalent to align down so add ALIGN_DOWN.
    For symmetry provide an ALIGN_UP macro as well.
    
    Change-Id: I7033109311eeb15c8c69c649878785378790feb9
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2951
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4fa5fa5088503ff5c168b4fb8d548dd90034d29e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 22:16:58 2013 -0500

    resources: introduce IORESOURCE_WRCOMB
    
    Certain MMIO resources can be set to a write-combining cacheable
    mode to increase performance. Typical resources that use this would
    be graphics memory.
    
    Change-Id: Icd96c720f86f7e2f19a6461bb23cb323124eb68e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2891
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a75561415e75d3a4dc813fc061140570e39b7078
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 22:09:46 2013 -0500

    resources: remove IORESOURCE_[UMA_FB|IGNORE_MTRR]
    
    The IORESOURCE_UMA_FB and IORESOURCE_IGNORE_MTRR attributes
    on a resource provided hints to the MTRR algorithm. The
    IORESOURCE_UMA_FB directed the MTRR algorithm to setup a uncacheable
    space for the resource. The IORESOURCE_IGNORE_MTRR directed
    the MTRR algorithm to ignore this resource as it was used reserving
    RAM space.
    
    Now that the optimizing MTRR algorithm is in place there isn't a need
    for these flags. All IORESOURCE_IGNORE_MTRR users are handled by the
    MTRR code merging resources of the same cacheable type. The users
    of the IORESOURCE_UMA_FB will find that the default MTRR type
    calculation means there isn't a need for this flag any more.
    
    Change-Id: I4f62192edd9a700cb80fa7569caf49538f9b83b7
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2890
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bb4e79a332f0a4f79d402c91b61010157d8a7886
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 26 14:09:47 2013 -0500

    x86: add new mtrr implementation
    
    The old MTRR code had issues using too many variable
    MTRRs depending on the physical address space layout dictated
    by the device resources. This new implementation calculates
    the default MTRR type by comparing the number of variable MTRRs
    used for each type. This avoids the need for IORESOURE_UMA_FB
    because in many of those situations setting the default type to WB
    frees up the variable MTTRs to set that space to UC.
    
    Additionally, it removes the need for IORESOURCE_IGNORE_MTRR
    becuase the new mtrr uses the memrange library which does merging
    of resources.
    
    Lastly, the sandybridge gma has its speedup optimization removed
    for the graphics memory by writing a pre-determined MTRR index.
    That will be fixed in an upcoming patch once write-combining support
    is added to the resources.
    
    Slight differences from previous MTRR code:
    - The number of reserved OS MTRRs is not a hard limit. It's now advisory
      as PAT can be used by the OS to setup the regions to the caching
      policy desired.
    - The memory types are calculated once by the first CPU to run the code.
      After that all other CPUs use that value.
    - CONFIG_CACHE_ROM support was dropped. It will be added back in its own
      change.
    
    A pathological case that was previously fixed by changing vendor code
    to adjust the IO hole location looked like the following:
    
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    
    As noted by the output below it's impossible to accomodate those
    ranges even with 10 variable MTRRS. However, because the code
    can select WB as the default MTRR type it can be done in 6 MTRRs:
    
    MTRR: default type WB/UC MTRR counts: 6/14.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
    MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
    MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
    
    Change-Id: Idfcc78d9afef9d44c769a676716aae3ff2bd79de
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2889
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 28adb6ead6d82073f32e4e786728e27326ccbc6c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Sat Mar 23 00:06:36 2013 -0500

    coreboot table: use memrange library
    
    Use the memrange library for keeping track of the address
    space region types. The memrange library is built to do just
    that for both the MTRR code and the coreboot memtable code.
    
    Change-Id: Iee2a7c37a3f4cf388db87ce40b580f274384ff3c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2917
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7762091fcb91710615f20229d43fc7fc7246ccdb
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 28 18:37:29 2013 -0700

    armv7: set cache level explicitly for dcache/unified cache case
    
    This adds a missing CSSELR write in the case of a dcache or unified
    cache being invalidated by armv7_invalidate_caches(), ensuring that
    all levels of dcache/unified cache are invalidated as expected when
    the function is called.
    
    Change-Id: Ie90184bf8a8181afa3afe0786897455b30b7f022
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2947
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit d4d6a407f74e241c0d00c2eeac2fb85e7f08f989
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 28 18:28:30 2013 -0700

    armv7: invalidate TLB after changing translation table entries
    
    This adds a call to tlb_invalidate_all() after configuring a range
    of memory.
    
    Change-Id: I558402e7e54b6bf9e0b013f153d9b84c0873a6cf
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2946
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7b19f669025a9f1dfc32035d7c93231e7a59c456
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 28 18:26:03 2013 -0700

    armv7: iterate thru all levels when doing dcache ops
    
    This makes dcache maintenance functions operate on all levels
    of cache instead of just the current one.
    
    Change-Id: I2708fc7ba6da6740dbdfd733d937e7c943012d62
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2945
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 8234874fbc10d71f620a2814a1faaed3b097db6c
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 28 19:04:14 2013 -0700

    armv7: add functions for reading/writing L2CTLR
    
    This adds simple accessor functions for reading/writing L2CTLR.
    
    Change-Id: I2768d00d5bb2c43e84741ccead81e529dac9254d
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2948
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fa244a6c09611833e78641604c96c1ea98b3bf6f
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 28 18:07:30 2013 -0700

    armv7: use stdint.h in cache and MMU files
    
    This makes it easier to copy + paste code into libpayload since
    libpayload since both coreboot and libpayload have stdint.h and
    it defines the types needed.
    
    Change-Id: Ifa55f04a9bdddd17bc1a2679321a6744c75f25a8
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2944
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit eca48438fcac64d3b68f6028bcbe98b24547f033
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 26 21:26:51 2013 -0700

    armv7: added paranoia for cache library
    
    This adds some paranoia to cache manipulation routines:
    - "memory" is added to the clobber list for functions which clean
      and/or invalidate dcache or TLB entries.
    - Remove unneeded clobber list for read_sctlr()
    
    Change-Id: Iaa82ef78bfdad4119f097c3b6db8219f29f832bc
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2928
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dbc11e2f766ab520fe2ccb61fdfed69b89e9d623
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 26 21:39:03 2013 -0700

    armv7: clean+invalidate all cache levels when disabling MMU
    
    This iterates thru all cache levels and cleans + invalidates all
    data and unified caches before disabling dcache and MMU.
    
    Change-Id: I8a671b4c90d7b88b8d0a95947bfa17f912cebaa2
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2930
    Reviewed-by: Gabe Black <gabe.black@gmail.com>
    Tested-by: build bot (Jenkins)

commit 19f3092b5297b2f6e128a97698176ed1173be909
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 26 17:47:05 2013 -0700

    armv7: cosmetic changes to dcache_op_mva()
    
    This is just a cosmetic change to dcache_op_mva() to (hopefully) make
    it a easier to follow and more difficult to screw up.
    
    Change-Id: Ia348b2d58f2f2bf5c3cafabcfba06bc411937dba
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2927
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8f398876170c4076a52850cf3f9cbeb23b951204
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 28 13:45:19 2013 -0700

    armv7: fix a bad variable assignment
    
    '<' was used when '<<' is needed. Oops!
    
    Change-Id: I8451f76888e86219df16b50739cd2c8db80dcb14
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2941
    Reviewed-by: Gabe Black <gabe.black@gmail.com>
    Tested-by: build bot (Jenkins)

commit d21ca52adebab875c66ff1843adcbb979400532f
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 26 17:45:39 2013 -0700

    armv7: pass incremented value to dccimvac
    
    This passes the correct value into dccimvac.
    
    Change-Id: I6098440ea48a9b6429380d5913fce6d36e3afb41
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2926
    Reviewed-by: Gabe Black <gabe.black@gmail.com>
    Tested-by: build bot (Jenkins)

commit 69a21b1eb9de9ab931959ac6efaa69333ffd2807
Author: Nico Huber <nico.h@gmx.de>
Date:   Thu Mar 28 15:08:20 2013 +0100

    crossgcc: Fix building with texinfo-5.x
    
    If you have a recent version of texinfo installed, building the reference
    toolchain fails with the following error:
    (in util/crossgcc/build-gcc/crossgcc-build.log)
    
    [...]/gcc-4.7.2/gcc/doc/cppopts.texi:806: @itemx must follow @item
    
    Looks like a warning-became-an-error problem in texinfo, to me. Fix that by
    making every erroneous @itemx an @item.
    
    Change-Id: I685ae1ecfee889b7c857b148cfab7411a10e7ecd
    Signed-off-by: Nico Huber <nico.h@gmx.de>
    Reviewed-on: http://review.coreboot.org/2939
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>

commit 3cc0d1eb3f611cb7bf0e45d8ccdb0c84f54f54dc
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 26 16:28:21 2013 -0700

    exynos5250: assign RAM resources in cpu_init()
    
    This moves the ram resource allocation into cpu_init() so that we
    no longer rely on declaring a domain in devicetree.cb (which is kind
    of weird for this platform). This does not cause any actual changes
    to the coreboot memory table, and paves the way for further updates
    to Snow's devicetree.
    
    Change-Id: I141277f59b5d48288f409257bf556a1cfa7a8463
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2923
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6b0d0d6e14f8e385e1457df5699136473144ed60
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Dec 14 17:16:21 2012 -0600

    cbfstool: Add update-fit command
    
    Add support for filling in the Firmware Interface Table.
    For now it only supports adding microcode entries.
    
    It takes 2 options:
    1. Name of file in cbfs where the mircocode is located
    2. The number of empty entries in the table.
    
    Verified with go firmware tools. Also commented out updating
    microcode in the bootblock. When romstage runs, the CPUs indicate
    their microcode is already loaded.
    
    Change-Id: Iaccaa9c226ee24868a5f4c0ba79729015d15bbef
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2712
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit dc7bc8e589c4b9f45e57327c2f989ef8f2a0e7c4
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Mar 26 12:51:36 2013 -0700

    cbfstool: Fix cbfs_image.c
    
    - The read-only structures are const now
    - cosmetic fixes
      - put { on a new line for functions
      - move code after structures
    
    Change-Id: Ib9131b80242b91bd5105feaebdf8306a844da1cc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2922
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 42f5513d3d09e50eee6279c401897f34b1eb0053
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Mar 25 19:50:11 2013 -0700

    armv7: fixes for dcache_op_by_mva()
    
    This fixes a couple issues with dcache_op_by_mva():
    - Add missing data and instruction sync barriers.
    - Removes unneded -1 from loop terminating condition.
    
    Change-Id: I098388614397c1e53079c017d56b1cf3ef273676
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2913
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 49675b950f2cbd40455dd1584ae8dfb50a1f3274
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Mar 26 11:28:47 2013 -0700

    ARMv7: Drop ROMSTAGE_BASE from Makefile.inc
    
    It's not used (instead ARM puts it in Kconfig)
    
    Change-Id: Ia22a7ac756bec4cb6fee00a4d946a020ea6290aa
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2916
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 0a527e7e5d3be94add22b654b74defd259f0ea76
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Mar 25 15:38:21 2013 -0700

    libpayload: Fix prototype warnings in PDCurses
    
    This fixes the following PDCurses warnings:
    
        CC         curses/pdcurses-backend/pdcsetsc.libcurses.o
    curses/pdcurses-backend/pdcsetsc.c: In function 'PDC_curs_set':
    curses/pdcurses-backend/pdcsetsc.c:17:9: warning: implicit declaration of function 'serial_cursor_enable' [-Wimplicit-function-declaration]
    curses/pdcurses-backend/pdcsetsc.c:22:9: warning: implicit declaration of function 'video_console_cursor_enable' [-Wimplicit-function-declaration]
        CC         curses/pdcurses-backend/pdcutil.libcurses.o
    curses/pdcurses-backend/pdcutil.c:30:6: warning: no previous prototype for 'curses_enable_serial' [-Wmissing-prototypes]
    curses/pdcurses-backend/pdcutil.c:35:6: warning: no previous prototype for 'curses_enable_vga' [-Wmissing-prototypes]
    curses/pdcurses-backend/pdcutil.c:40:5: warning: function declaration isn't a prototype [-Wstrict-prototypes]
    curses/pdcurses-backend/pdcutil.c:45:5: warning: function declaration isn't a prototype [-Wstrict-prototypes]
    
    Change-Id: If0d4d475d3006f1a77f67ec46c6bdf4ee2906981
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2908
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c7b6d7db092cfd925f1fb6333e166a54663310e7
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Mar 25 15:03:41 2013 -0700

    libpayload: Fix type issues
    
    There were a number of type issues in libpayload that sneaked in
    with 903f8e0.
    
    - size_t and ssize_t were conflicting with gcc builtins
    - some stdint types were used in libpayload but not defined
      in our stdint.h
    
    With this patch it's possible to compile libpayload with the
    reference toolchain again.
    
    Change-Id: Idd5ccfdd9f3536b36bceca2d101e7405883b10bc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2903
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e21f5e14834af6426bd6fc3e7f37f6b18243f416
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Mar 25 15:13:20 2013 -0700

    libpayload: fix size_t handling
    
    libcbfs was using printf for size_t typed variables. However, printf
    did not support printing those. This patch fixes the issue, removing
    the warning when compiling ram_media.c
    
    libcbfs/ram_media.c:52:10: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'long unsigned int' [-Wformat]
    libcbfs/ram_media.c:52:10: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat]
    
    Change-Id: Iaf6e723f9a5b0a61a39d3125036fee9853e37ba8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2904
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a6c495edcaaade187280262db1bbce887fa28003
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Mar 25 15:15:16 2013 -0700

    libpayload: Fix const warnings in keyname() and termname()
    
    The keyname() and termname() functions were creating a whole lot of warnings of
    the style
    
    curses/PDCurses-3.4/pdcurses/keyname.c:41:9: warning: initialization discards 'const' qualifier from pointer target type [enabled by default]
    
    This patch fixes them.
    
    Change-Id: Iae3c4e5201b48c2d2033cac48577e0462a34f309
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2905
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 8d225f141d45e3eba5bb39973e4889e884d9a64f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Mar 25 15:30:30 2013 -0700

    libpayload: Fix variable shadowing in PDCurses
    
    PDCurses has a function called overlay() and also uses
    overlay as a variable name in some functions.
    
    This patch fixes the ambiguity that caused warnings like
    curses/PDCurses-3.4/pdcurses/overlay.c: In function '_copy_win':
    curses/PDCurses-3.4/pdcurses/overlay.c:51:39: warning: declaration of 'overlay' shadows a global declaration [-Wshadow]
    In file included from curses/PDCurses-3.4/curspriv.h:16:0,
                     from curses/PDCurses-3.4/pdcurses/overlay.c:3:
    curses/PDCurses-3.4/curses.h:1014:9: warning: shadowed declaration is here [-Wshadow]
    
    Change-Id: I907653df0c8bb32c98bdcbc6476e94d2da6e0e90
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2906
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 0fef4fe61ba4a6775fa8ab671212bf0acc9a8adf
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Mar 25 15:32:25 2013 -0700

    libpayload: Fix missing prototype warning for Xinitscr()
    
    Xinitscr is only used internally in PDCurses, unless XCURSES
    is defined. This patch fixes a warning that is produced because
    of that.
    
    Change-Id: I211f75717276cf028e0b435f328d1687d3536eb7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2907
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit d5c79f9cc897ef74ee7c376553572c67ed532662
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Mar 25 15:56:08 2013 -0700

    libpayload: Fix unused function warning in EHCI stack
    
    The function dump_qh() was added a while back but never used.
    Hide it behind USB_DEBUG so it doesn't cause warnings when not
    debugging the USB stack.
    
    Change-Id: Idb3c7bb214895ef82676d181836a578bf161e8e0
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2909
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit cf4a3f4a9781dab1e08aa2d0c937d4bd196e02f6
Author: Aaron Durbin <adurbin@google.com>
Date:   Tue Mar 26 18:07:32 2013 +0100

    Revert "coreboot table: use memrange library"
    
    This reverts commit 56075eaefcd7ef51464206166b24a0a47a59147f
    
    Change-Id: I8a37ce1f5ce36e4a120941ec264140abc9447ff5
    Reviewed-on: http://review.coreboot.org/2915
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 5a767fdfcb08f0c23f6a9763a8f90a282de49326
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Sat Mar 23 00:12:19 2013 -0500

    x86: dynamic cbmem: fix acpi reservations
    
    If a configuration was not using RELOCTABLE_RAMSTAGE, but it
    was using HAVE_ACPI_RESUME then the ACPI memory was not being
    marked as reserved to the OS. The reason is that memory is marked as
    reserved during write_coreboot_table(). These reservations were
    being added to cbmem after the call to write_coreboot_table(). In
    the non-dynamic cbmem case this sequence is fine because cbmem area
    is a fixed size and is already reserved. For the dynamic cbmem case
    that no longer holds by the nature of the dynamic cbmem.
    
    Change-Id: I9aa44205205bfef75a9e7d9f02cf5c93d7c457b2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2897
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 56075eaefcd7ef51464206166b24a0a47a59147f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Sat Mar 23 00:06:36 2013 -0500

    coreboot table: use memrange library
    
    Use the memrange library for keeping track of the address
    space region types. The memrange library is built to do just
    that for both the MTRR code and the coreboot memtable code.
    
    Change-Id: Ic667df444586c2b5b5f2ee531370bb790d683a42
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2896
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0175587c5ea1db0ef76b3000db027e353b383de9
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 26 04:25:46 2013 +0100

    Revert "samsung/exynos5: add resource functions for the display port"
    
    This reverts commit 9427ca151e44644238b1b52138894195a9f5175f
    
    Looks like we were a bit too anxious to see this one get in. The devicetree.cb change seems to have broken things.
    coreboot memory table:
     0. 0000000050000000-000000005000ffff: RESERVED
     1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES
     2. 0000014004000000-00000140044007ff: RESERVED
    
    Before this patch:
    coreboot memory table:
     0. 0000000040000000-00000000bfefffff: RAM
     1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES
    
    Change-Id: I618e4f1976265d56cfd6a61d0c5736c55a0f3cec
    Reviewed-on: http://review.coreboot.org/2914
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 7f86c0586add7836b8c44805b6ef9eaa59fac787
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Mar 25 17:50:17 2013 -0700

    ARMv7: Drop XIP relocation code for romstage
    
    It was never used, because we pushed romstage_null into the CBFS
    instead of romstage_xip. It's not surprising this worked, but it
    was a crude hack. Get rid of all the intermediate objects that are
    not needed.
    
    This could probably be further simplified to use the default cbfs
    mechanism in our build system instead of having a specific rule for
    romstage, but that's for another day.
    
    Change-Id: I492ca2015ec81e13499fcd8dd331371f46a31c78
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2912
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 9427ca151e44644238b1b52138894195a9f5175f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Mar 18 09:49:54 2013 -0700

    samsung/exynos5: add resource functions for the display port
    
    This does NOT turn on the graphics.
    
    The device tree has been changed enough so that, at the very least, the correct
    functions are called at the correct time, with the correct paramaters. We
    decided to yank the I2C entries as they did not obvious function and might
    not even have been correct.
    
    Not working, seemingly, but we need to add a 4M resource for
    memory, and it seems it needs to be fixed at the address shown.
    This address was chosen from current hardware.
    
    We realized that the display code should be part of the cpu -- that's how
    the hardware works!
    
    Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2615
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit f9be756b559ccc567e5412c85b5ded98f19617e7
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 21 21:58:50 2013 -0700

    armv7: add new dcache and MMU setup functions
    
    This adds new MMU setup code. Most notably, this version uses
    cbmem_add() to determine the translation table base address, which
    in turn is necessary to ensure payloads which wipe memory can tell
    which regions to wipe out.
    
    TODOs:
    - Finish cleaning up references to old cache/MMU stuff
    - Add L2 setup (from exynos_cache.c)
    - Set up ranges dynamically rather than in ramstage's main().
    
    Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2877
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 04d352db41522b3c7aec2ce574ff90484bc0ad8a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Mar 25 14:13:43 2013 -0700

    libpayload: Fix Config.in warning
    
    PDcurses is already default. Hence drop the additional attempt
    that is not supported by Kconfig.
    
    Config.in:123:warning: defaults for choice values not supported
    
    Change-Id: I12cb5ea0bef2f146cf237c7a3cc9293a600d736b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2902
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 3926b4c520e74da9dc22e3d136a8a178483e0d25
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Fri Mar 1 19:41:41 2013 +0100

    AMD Inagua: add GEC firmware, document Broadcom BCM57xx Selfboot Patch format
    
    The Broadcom BCM5785 GbE MAC integrated in the AMD Hudson-E1 requires a
    secret sauce firmware blob to work.  As Broadcom wasn't willing to send us
    any documentation (or a firmware adapted to our Micrel PHY) I had to figure
    out everything by myself in many weeks of hard detective work.
    
    In the end we had to settle for a different solution, the modified firmware
    I devised for the Micrel KSZ9021 PHY on our early FrontRunner-AF prototypes
    is no longer needed for the production version.  However the information
    contained here might be very useful for others who'd like to use a
    competing PHY instead of Broadcom's 50610, so it should not get lost.
    
    And of course the unmodified, but now in large parts documented Selfboot
    Patch is needed to get Ethernet on AMD Inagua.  The code introduced here
    should make the Hudson's internal MAC usable without having to add the
    proprietary firmware blob. - At least in theory.
    
    Unfortunately we've been unable to actually test this patch on Inagua,
    therefore the broadcom_init() call in mainboard.c was left commented out.
    If you have the hardware and can confirm it works please enable it.
    
    The fun thing is: as Broadcom refused to do any business with us at all,
    or send us any documentation, we never had to sign an NDA with them.  This
    leaves me free to publish everything I have found out.  :-)
    
    Change-Id: I94868250591862b376049c76bd21cb7e85f82569
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2831
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 59c020ab15fcc090e0605df1e17f41ffa861b153
Author: Mathias Krause <minipli@googlemail.com>
Date:   Sun Mar 24 19:40:02 2013 +0100

    libpayload: fix use-after-free in usb_exit()
    
    The controller's shutdown function free()s the controller structure so
    we shouldn't access it any more after calling shutdown.
    
    As all controllers detach themself, i.e. unchain themself from usb_hcs,
    just keep iterating over usb_hcs until it's NULL.
    
    Change-Id: Ie85caba0f685494c3fe04c550a5a14bc4158a94e
    Signed-off-by: Mathias Krause <minipli@googlemail.com>
    Reviewed-on: http://review.coreboot.org/2900
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 7a9da71c5f276cdfd986ad81b2b344fc641bd0a7
Author: Mathias Krause <minipli@googlemail.com>
Date:   Sun Mar 24 19:40:01 2013 +0100

    libpayload: EHCI - detach controller in ehci_shutdown()
    
    It shouldn't be used any more as we're about to free() the memory behind
    the controller -- therefore detach it.
    
    Change-Id: I875322a9940570c51d412a7f3bfb6af4ea3b3764
    Signed-off-by: Mathias Krause <minipli@googlemail.com>
    Reviewed-on: http://review.coreboot.org/2899
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Nico Huber <nico.huber@secunet.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c15551ab0878c16f61335a701dd34c7d0e89120e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Sat Mar 23 00:00:54 2013 -0500

    dynamic cbmem: fix memconsole and timestamps
    
    There are assumptions that COLLECT_TIMESTAMPS and CONSOLE_CBMEM
    rely on EARLY_CBMEM_INIT. This isn't true in the face of
    DYNAMIC_CBMEM as it provides the same properties as EARLY_CBMEM_INIT.
    Therefore, allow one to select COLLECT_TIMESTAMPS and CONSOLE_CBMEM
    when DYNAMIC_CBMEM is selected.  Lastly, don't hard code the cbmem
    implementation when COLLECT_TIMESTAMPS is selected.
    
    Change-Id: I053ebb385ad54a90a202da9d70b9d87ecc963656
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2895
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c965076c3ecec6ccf8eb0eb1d57d6a0a312dab04
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 22:03:09 2013 -0500

    resources: introduce reserved_ram_resource()
    
    mmio_resource() was previously being used for reserving
    RAM from the OS by using IORESOURCE_IGNORE_MTRR atrribute.
    Instead, be more explicit for those uses with
    reserved_ram_resource(). bad_ram_resource() now calls
    reserved_ram_resource(). Those resources are marked as cacheable
    but reserved.
    
    The sandybridge and haswell code were relying on the implementation
    fo the MTRR algorithm's interaction for reserved regions. Instead
    be explicit about what ranges are MMIO reserved and what are RAM
    reserved.
    
    Change-Id: I1e47026970fb37c0305e4d49a12c98b0cdd1abe5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2886
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0135702802601c19937eec57513f3a6e2f4d1e00
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 20:23:17 2013 -0500

    x86: mark .textfirst as allocatable and executable
    
    When the linking of ramstage was changed to use an intermeidate
    object with all ramstage objects in it the .textfirst section
    was introduced to keep the entry point at 0. However, the
    section was not marked allocatable or executable. Nor was it
    marked as @progbits. That didn't cause an issue on its own since
    .textfirst was directly called out in the linker script. However,
    the rmodule infrastructure relies on all the relocation entries
    being included in the rmodule. Without the proper section attributes
    the .rel.textfirst section entries were not being included in
    the final ramstage rmodule.
    
    Change-Id: I54e7055a19bee6c86e269eba047d9a560702afde
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2885
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b467f1ddafb0ad4769b5d51b88563966af7d563c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 19:59:52 2013 -0500

    relocatable ramstage: fix linking
    
    The ramstage is now linked using an intermediate object that
    is created from the complete list of ramstage object files.
    The rmodule code was developed when ramstage was linked using
    an archive file. Because of the fact that the rmodule headers
    are not referenced from any other object the link could start
    by specifying the rmodule header object for ramstage. That,
    however, is not the case as all ramstage objects are included
    in the intermediate linked object. Therefore, the
    ramstage_module_header.ramstage.o object file needs to be removed
    from the object list for the ramstage rmodule.
    
    Change-Id: I6a79b6f8dd1dbfe40fdc7753297243c3c9b45fae
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2884
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c875e2aaabb1226b0ecbf98df6112ef8ce28dd41
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 19:48:39 2013 -0500

    vboot module: fix compilation issues
    
    There were 3 things stopping the vboot module from being
    compiled:
    
    1. The vboot_reference code removed in the firmware/arch/$(ARCH)/include
       directory. This caused romcc to fail because romcc fails if -I<dir>
       points to non-existent directory.
    2. The rmodule API does not have the no-clearing-of-bss variant of the
       load function.
    3. cbfs API changes.
    
    Change-Id: I1e1296c71c5831d56fc9acfaa578c84a948b4ced
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2881
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1989b4bd560045b524fad2f5d189907e4a8abe26
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 19:52:42 2013 -0500

    x86: expose console_tx_flush in romstage
    
    The vboot module relied on being able to flush the console
    after it called vtxprintf() from its log wrapper function.
    Expose the console_tx_flush() function in romstage so the
    vboot module can ensure messages are flushed.
    
    Change-Id: I578053df4b88c2068bd9cc90eea5573069a0a4e8
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2882
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d23e292ef624ae1000b700399ece00c72946ede1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 19:55:35 2013 -0500

    rmodule: align ld script with latest x86 ld script
    
    The x86 linker script added a .textfirst section. In
    order to properly link ramstage as a relocatable module
    the .textfirst section needs to be included.
    
    Also, the support for code coverage was added by including
    the constructor section and symbols. Coverage has not been
    tested as I suspect it might not work in a relocatable
    environment without some tweaking. However, the section
    and symbols are there if needed.
    
    Change-Id: Ie1f6d987d6eb657ed4aa3a8918b2449dafaf9463
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2883
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2bd2e37536a7bc31023233cf3b7c6682cbd8176b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 19:46:16 2013 -0500

    cbfs: fix relocation ramstage compiler errors
    
    There were some cbfs calls that did not get transitioned
    to the new cbfs API. Fix the callsites to conform to the
    actual cbfs, thus fixing the copilation errors.
    
    Change-Id: Ia9fe2c4efa32de50982e21bd01457ac218808bd3
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2880
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 73982c3c685395b74b611cde7f13f0145b8c0a4d
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 22 19:35:56 2013 -0500

    xcompile: honor LINKER_SUFFIX variable
    
    In commit e820e5cb3aed810fa9ba6047ce9b8bf352335e32 titled
    "Make xcompile support multiple architectures" the LINKER_SUFFIX
    variable was introduced to bypass gold if the bfd linker was
    available. However, the LINKER_SUFFIX wasn't honored when
    the compiler evironment variables were set. Fix the original
    intention.
    
    Change-Id: I608f1e0cc3d0bea3ba1e51b167d88c66d266bceb
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2879
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a438ea838e16ac4f3c2e7250ed2530671de4747d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 26 17:24:41 2013 +0200

    Unify setting i82801e LPC
    
    Make it more similar to i82801d LPC init.
    
    Change-Id: I7b32747ee8012c220c8628994d749999c144b716
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/2545
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit d1cc812799d3156888cd667d13f93bfa44c639c1
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Feb 8 12:39:28 2013 +0100

    libpayload: Add comments on virtual pointers in lib_sysinfo
    
    After another incident related to virtual pointers in lib_sysinfo (and
    resulting confusion), I decided to put some comments on the matter into
    the code.
    
    Remember, we decided to always use virtual pointers in lib_sysinfo, but
    it's not always obvious from the code, that they are.
    
    See also:
    425973c libpayload: Always use virtual pointers in struct sysinfo_t
    593f577 libpayload: Fix use of virtual pointers in sysinfo
    
    Change-Id: I886c3b1d182cba07f1aab1667e702e2868ad4b68
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/2878
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 57686f848597f6b133c9d45a9b98a54638399b32
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 20 15:50:59 2013 -0500

    x86: unify amd and non-amd MTRR routines
    
    The amd_mtrr.c file contains a copy of the fixed MTRR algorithm.
    However, the AMD code needs to handle the RdMem and WrMem attribute
    bits in the fixed MTRR MSRs. Instead of duplicating the code
    with the one slight change introduce a Kconfig option,
    X86_AMD_FIXED_MTRRS, which indicates that the RdMem and WrMem fields
    need to be handled for writeback fixed MTRR ranges.
    
    The order of how the AMD MTRR setup routine is maintained by providing
    a x86_setup_fixed_mtrrs_no_enable() function which does not enable
    the fixed MTRRs after setting them up. All Kconfig files which had a
    Makefile that included amd/mtrr in the subdirs-y now have a default
    X86_AMD_FIXED_MTRRS selection. There may be some overlap with the
    agesa and socket code, but I didn't know the best way to tease out
    the interdependency.
    
    Change-Id: I256d0210d1eb3004e2043b46374dcc0337432767
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2866
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit c8eab2c0441851a141ef47d10022fb385d0eacad
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Wed Mar 20 21:43:50 2013 +0100

    Add support for ASUS F2A85-M board
    
    The patch is based on Thatcher board. So far it boots Linux (3.2/3.7),
    internal network adapter works, AHCI works. External PCI/PCIe slots
    works too. Power management/ACPI seems to work.
    
    Internal VGA works with dumped ROM (VGA/DVI), but lacks GART.
    
    PCI pref devices are being relocated by Linux, reason unknown.
    
    This is a good start.
    
    USB and XHCI untested but visible.
    
    Change-Id: I1869aecb2634d548b00b3c9139517d6a0e0c9817
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/2038
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 5605f1b4ab7661f893bf0f10aea72cacdd51dc99
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Mar 21 18:43:51 2013 -0700

    Fix compilation of Intel LynxPoint based boards
    
    The haswell patches that verified correctly were not yet submitted,
    but verified correctly. However they still used romcc_io.h which was
    dropped in another patch earlier today.
    
    With a lot of development happening in parallel, this is
    unfortunately nothing that the gerrit 2.6 Rebase If Necessary submit
    type could have fixed.
    
    Change-Id: Ifef9ae05b22c408e78d6cff37defd68e4ed91ed9
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2876
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Thu Mar 21 22:21:28 2013 +0100

    Asrock E350M1: Use SPD read code from F14 wrapper
    
    Changes:
     - Get rid of the E350M1 mainboard specific code and use the
       platform generic function wrapper that was added in change
       http://review.coreboot.org/#/c/2497/
       AMD f14: Add SPD read functions to wrapper code
    
     - Move DIMM addresses into devicetree.cb
    
     - Add the ASF init that used to be in the SPD read code into
       mainboard_enable()
    
    Notes:
     - The DIMM reads only happen in romstage, so the function is not
       available in ramstage.  Point the read-SPD callback to a generic
       function in ramstage.
    
    Change-Id: I08c2aebc62facc14f94400ee1ad188901ba73f19
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2875
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 3db86ccfd7caaec5a1c494dfe3bfe9b092837f65
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Thu Mar 21 22:31:19 2013 +0100

    FrontRunner/Toucan-AF: Use SPD read code from F14 wrapper
    
    Changes:
     - Get rid of the LiPPERT FrontRunner-AF and Toucan-AF mainboard
       specific code and use the platform generic function wrapper that
       was added in change
       http://review.coreboot.org/#/c/2497/
       AMD f14: Add SPD read functions to wrapper code
    
     - Move DIMM addresses into devicetree.cb
    
     - Add the ASF init that used to be in the SPD read code into
       mainboard_enable()
    
    Notes:
     - The DIMM reads only happen in romstage, so the function is not
       available in ramstage.  Point the read-SPD callback to a generic
       function in ramstage.
    
    Change-Id: I4ee5e1bc34f4caee20615c48248d4f7605c09377
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2874
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 36b6f367c064e9d5d64bc2246bf7cc85bb7c62d3
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Mar 9 10:36:10 2013 +0100

    libpayload: initial test case + tiny "framework"
    
    This adds a test case for using CBFS images that reside in RAM
    and a Makefile to run it (and maybe other tests in the future).
    
    The test concerns an issue in libcbfs when using x86 style CBFS
    images in non-canonical locations (eg. when loading CBFS images
    for processing).
    
    Use with "make run" inside the tests directory.
    
    Change-Id: I1af3792a1451728ff9594ba7f0410027cdecb59d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2623
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b02c873190990698350a7c2a9bce52ce81c0f1b2
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Mar 15 17:40:08 2013 +0800

    cbfstool: Fix initial empty space in image creation.
    
    When calculating initial CBFS empty entry space, the size of header itself must
    be not included (with the reserved space for entry name). This is a regression
    of the old cbfstool size bug.
    
    Before this fix, in build process we see:
     OBJCOPY    cbfs/fallback/romstage_null.bin
     W: CBFS image was created with old cbfstool with size bug.
        Fixing size in last entry...
    
    And checking the output binary:
     cbfstool build/coreboot.pre1 print -v -v
     DEBUG: read_cbfs_image: build/coreboot.pre1 (262144 bytes)
     DEBUG: x86sig: 0xfffffd30, offset: 0x3fd30
     W: CBFS image was created with old cbfstool with size bug.
        Fixing size in last entry...
     DEBUG: Last entry has been changed from 0x3fd40 to 0x3fd00.
     coreboot.pre1: 256 kB, bootblksz 688, romsize 262144, offset 0x0 align: 64
     Name                           Offset     Type         Size
     (empty)                        0x0        null         261296
     DEBUG:  cbfs_file=0x0, offset=0x28, content_address=0x28+0x3fcb0
    
    After this fix, no more alerts in build process.
    Verified to build successfully on x86/qemu and arm/snow configurations.
    
    Change-Id: I35c96f4c10a41bae671148a0e08988fa3bf6b7d3
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2731
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3e4e3038584fb2055c482fd346bb821b3d6236fc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Mar 20 14:08:04 2013 -0700

    Unify coreboot table generation
    
    coreboot tables are, unlike general system tables, a platform
    independent concept. Hence, use the same code for coreboot table
    generation on all platforms. lib/coreboot_tables.c is based
    on the x86 version of the file, because some important fixes
    were missed on the ARMv7 version lately.
    
    Change-Id: Icc38baf609f10536a320d21ac64408bef44bb77d
    Signed-off-by: Stefan Reinauer <reinauer@coreboot.org>
    Reviewed-on: http://review.coreboot.org/2863
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Aaron Durbin <adurbin@google.com>
    Tested-by: build bot (Jenkins)

commit 93a6665e0cf29971b92550ff020b8c2f67c17202
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 19 15:25:46 2013 -0500

    wtm2: build-time dev and recovery settings
    
    It's helpful to switch back and forth for developer and
    recovery settings while testing boards. The wtm2 board
    currently doesn't have gpios which dynamically seelect that.
    Might as well make it easy to change the value for each
    setting with one define. The original defaults are kept.
    
    Change-Id: I7b928c592fd20a1b847e4733f4cdef09d6ddad4c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2861
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 54553d9fc18d28033202c6b48c6b8cb49967c7e5
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 19 12:43:18 2013 -0500

    vboot: pass correct coreboot include paths
    
    The coreboot include were not being passed correctly when
    building vboot_reference. The paths being included were of the
    src/<dir> form. However, vboot_reference lives in
    src/../vboot_reference. That coupled with the recursive make
    call made vboot_reference not see coreboot's header files.
    Fix this by appending ../ to coreboot's default include paths.
    
    Change-Id: I73949c6f854ecfce77ac36bb995918d51f91445e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2860
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8dddc30eb55bc57b1e319d35a66a1889a9716ca1
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 15 09:42:00 2013 -0700

    haswell: Add microcode for ULT C0 stepping 0x40651
    
    Change-Id: I53982d88f94255abdbb38ca18f9d891d4bc161b0
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2858
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dd32a31fbafafb6fa3dd1dc342884ffe88a7aa04
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Mar 7 23:15:06 2013 -0600

    coreboot: add vboot_handoff to coreboot tables
    
    The vboot_handoff structure contians the VbInitParams as well as the
    shared vboot data. In order for the boot loader to find it, the
    structure address and size needs to be obtained from the coreboot
    tables.
    
    Change-Id: I6573d479009ccbf373a7325f861bebe8dc9f5cf8
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2857
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d02bb62a4fefcb39063bc058afb60521fe819bad
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 1 17:40:49 2013 -0600

    haswell: vboot path support in romstage
    
    Take the vboot path in romstage. This will complete the haswell
    support for vboot firmware selection.
    
    Built and booted. Noted firmware select worked on an image with
    RW firmware support. Also checked that recovery mode worked as
    well by choosing the RO path.
    
    Change-Id: Ie2b0a34e6c5c45e6f0d25f77a5fdbaef0324cb09
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2856
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0df4de9e96887ddc4b8c5f79064701e9d1448ea9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 1 17:38:59 2013 -0600

    haswell boards: support added chromeos function
    
    The get_write_protect_state() function was added to the
    chromeos API that needs to be supported by the boards.
    Implement this support.
    
    Built and booted. Noted firmware select worked on an image with
    RW firmware support. Also checked that recovery mode worked as
    well by choosing the RO path.
    
    Change-Id: Ifd213be25304163fc61d153feac4f5a875a40902
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2855
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fd79562915bbdea93fc7b37e657856acf808e64f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 1 17:12:26 2013 -0600

    romstage: add support for vboot firmware selection
    
    This patch implements support for vboot firmware selection. The vboot
    support is comprised of the following pieces:
    
    1. vboot_loader.c - this file contains the entry point,
       vboot_verify_firmware(), for romstage to call in order to perform
       vboot selection. The loader sets up all the data for the wrapper
       to use.
    2. vboot_wrapper.c - this file contains the implementation calling the vboot
       API. It calls VbInit() and VbSelectFirmware() with the data supplied
       by the loader.
    
    The vboot wrapper is compiled and linked as an rmodule and placed in
    cbfs as 'fallback/vboot'. It's loaded into memory and relocated just
    like the way ramstage would be. After being loaded the loader calls into
    wrapper. When the wrapper sees that a given piece of firmware has been
    selected it parses firmware component information for a predetermined
    number of components.
    
    Vboot result information is passed to downstream users by way of the
    vboot_handoff structure. This structure lives in cbmem and contains
    the shared data, selected firmware, VbInitParams, and parsed firwmare
    components.
    
    During ramstage there are only 2 changes:
    
    1. Copy the shared vboot data from vboot_handoff to the chromeos acpi
       table.
    2. If a firmware selection was made in romstage the boot loader
       component is used for the payload.
    
    Noteable Information:
    - no vboot path for S3.
    - assumes that all RW firmware contains a book keeping header for the
      components that comprise the signed firmware area.
    - As sanity check there is a limit to the number of firmware components
      contained in a signed firmware area. That's so that an errant value
      doesn't cause the size calculation to erroneously read memory it
      shouldn't.
    - RO normal path isn't supported. It's assumed that firmware will always
      load the verified RW on all boots but recovery.
    - If vboot requests memory to be cleared it is assumed that the boot
      loader will take care of that by looking at the out flags in
    VbInitParams.
    
    Built and booted. Noted firmware select worked on an image with
    RW firmware support. Also checked that recovery mode worked as well
    by choosing the RO path.
    
    Change-Id: I45de725c44ee5b766f866692a20881c42ee11fa8
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2854
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c0650894f8ca50a7609971418e8eaa4c674f36a9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 1 17:10:28 2013 -0600

    rmodule: add vboot rmodule type
    
    For completeness add a vboot rmodule type since vboot will be
    built as an rmodule.
    
    Change-Id: I4b9b1e6f6077f811cafbb81effd4d082c91d4300
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2853
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 22919ce62ce110b351133cd4c18d5229291beef3
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 1 17:07:51 2013 -0600

    timestamp: add vboot check points
    
    It's desirable to measure the vboot firmware selection time.
    Therefore add vboot check points to the timestamp ids.
    
    Change-Id: Ib103a9e91652cf96abcacebf0f211300e03f71fd
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2852
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 0c6946db3f777e212c9b2c5a7443f6c2946a199e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 13 12:48:33 2013 -0500

    cbmem: add vboot cmbem id
    
    The vboot firmware selection from romstage will need to
    pass the resulting vboot data to other consumers. This will
    be done using a cbmem entry.
    
    Change-Id: I497caba53f9f3944513382f3929d21b04bf3ba9e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2851
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c0cbd6e8c2bad5453f7c3b6961bc12d03862497a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 13 13:51:20 2013 -0500

    haswell: use dynamic cbmem
    
    Convert the existing haswell code to support reloctable ramstage
    to use dynamic cbmem. This patch always selects DYNAMIC_CBMEM as
    this option is a hard requirement for relocatable ramstage.
    
    Aside from converting a few new API calls, a cbmem_top()
    implementation is added which is defined to be at the begining of the
    TSEG region. Also, use the dynamic cbmem library for allocating a
    stack in ram for romstage after CAR is torn down.
    
    Utilizing dynamic cbmem does mean that the cmem field in the gnvs
    chromeos acpi table is now 0. Also, the memconsole driver in the kernel
    won't be able to find the memconsole because the cbmem structure
    changed.
    
    Change-Id: I7cf98d15b97ad82abacfb36ec37b004ce4605c38
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2850
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dd4a6d2357decf0cf505370234b378985c68f97f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Feb 27 22:50:12 2013 -0600

    coreboot: dynamic cbmem requirement
    
    Dynamic cbmem is now a requirement for relocatable ramstage.
    This patch replaces the reserve_* fields in the romstage_handoff
    structure by using the dynamic cbmem library.
    
    The haswell code is not moved over in this commit, but it should be
    safe because there is a hard requirement for DYNAMIC_CBMEM when using
    a reloctable ramstage.
    
    Change-Id: I59ab4552c3ae8c2c3982df458cd81a4a9b712cc2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2849
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 24d1d4b47274eb82893e6726472a991a36fce0aa
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Mar 21 11:51:41 2013 -0700

    x86: Unify arch/io.h and arch/romcc_io.h
    
    Here's the great news: From now on you don't have to worry about
    hitting the right io.h include anymore. Just forget about romcc_io.h
    and use io.h instead. This cleanup has a number of advantages, like
    you don't have to guard device/ includes for SMM and pre RAM
    anymore. This allows to get rid of a number of ifdefs and will
    generally make the code more readable and understandable.
    
    Potentially in the future some of the code in the io.h __PRE_RAM__
    path should move to device.h or other device/ includes instead,
    but that's another incremental change.
    
    Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2872
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 55ed3106556a9bcbe36d3389dc5230d4a4ee2a40
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 1 17:00:39 2013 -0600

    rmodule: correct ordering of bss clearing
    
    This patch fixes an issue for rmodules which are copied into memory
    at the final load/link location. If the bss section is cleared for
    that rmodule the relocation could not take place properly since the
    relocation information was wiped by act of clearing the bss. The
    reason is that the relocation information resides at the same
    address as the bss section. Correct this issue by performing the
    relocation before clearing the bss.
    
    Change-Id: I01a124a8201321a9eaf6144c743fa818c0f004b4
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2822
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit df3a109b72907419d503c81257ea241becdbb915
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 13 12:41:44 2013 -0500

    cbmem: dynamic cbmem support
    
    This patch adds a parallel implementation of cbmem that supports
    dynamic sizing. The original implementation relied on reserving
    a fixed-size block of memory for adding cbmem entries. In order to
    allow for more flexibility for adding cbmem allocations the dynamic
    cbmem infrastructure was developed as an alternative to the fixed block
    approach. Also, the amount of memory to reserve for cbmem allocations
    does not need to be known prior to the first allocation.
    
    The dynamic cbmem code implements the same API as the existing cbmem
    code except for cbmem_init() and cbmem_reinit(). The add and find
    routines behave the same way. The dynamic cbmem infrastructure
    uses a top down allocator that starts allocating from a board/chipset
    defined function cbmem_top(). A root pointer lives just below
    cbmem_top(). In turn that pointer points to the root block which
    contains the entries for all the large alloctations. The corresponding
    block for each large allocation falls just below the previous entry.
    
    It should be noted that this implementation rounds all allocations
    up to a 4096 byte granularity. Though a packing allocator could
    be written for small allocations it was deemed OK to just fragment
    the memory as there shouldn't be that many small allocations. The
    result is less code with a tradeoff of some wasted memory.
    
               +----------------------+ <- cbmem_top()
      |   +----|   root pointer       |
      |   |    +----------------------+
      |   |    |                      |--------+
      |   +--->|   root block         |-----+  |
      |        +----------------------+     |  |
      |        |                      |     |  |
      |        |                      |     |  |
      |        |   alloc N            |<----+  |
      |        +----------------------+        |
      |        |                      |        |
      |        |                      |        |
     \|/       |   alloc N + 1        |<-------+
      v        +----------------------+
    
    In addition to preserving the previous cbmem API, the dynamic
    cbmem API allows for removing blocks from cbmem. This allows for
    the boot process to allocate memory that can be discarded after
    it's been used for performing more complex boot tasks in romstage.
    
    In order to plumb this support in there were some issues to work
    around regarding writing of coreboot tables. There were a few
    assumptions to how cbmem was layed out which dictated some ifdef
    guarding and other runtime checks so as not to incorrectly
    tag the e820 and coreboot memory tables.
    
    The example shown below is using dynamic cbmem infrastructure.
    The reserved memory for cbmem is less than 512KiB.
    
    coreboot memory table:
     0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
     1. 0000000000001000-000000000002ffff: RAM
     2. 0000000000030000-000000000003ffff: RESERVED
     3. 0000000000040000-000000000009ffff: RAM
     4. 00000000000a0000-00000000000fffff: RESERVED
     5. 0000000000100000-0000000000efffff: RAM
     6. 0000000000f00000-0000000000ffffff: RESERVED
     7. 0000000001000000-000000007bf80fff: RAM
     8. 000000007bf81000-000000007bffffff: CONFIGURATION TABLES
     9. 000000007c000000-000000007e9fffff: RESERVED
    10. 00000000f0000000-00000000f3ffffff: RESERVED
    11. 00000000fed10000-00000000fed19fff: RESERVED
    12. 00000000fed84000-00000000fed84fff: RESERVED
    13. 0000000100000000-00000001005fffff: RAM
    Wrote coreboot table at: 7bf81000, 0x39c bytes, checksum f5bf
    coreboot table: 948 bytes.
    CBMEM ROOT  0. 7bfff000 00001000
    MRC DATA    1. 7bffe000 00001000
    ROMSTAGE    2. 7bffd000 00001000
    TIME STAMP  3. 7bffc000 00001000
    ROMSTG STCK 4. 7bff7000 00005000
    CONSOLE     5. 7bfe7000 00010000
    VBOOT       6. 7bfe6000 00001000
    RAMSTAGE    7. 7bf98000 0004e000
    GDT         8. 7bf97000 00001000
    ACPI        9. 7bf8b000 0000c000
    ACPI GNVS  10. 7bf8a000 00001000
    SMBIOS     11. 7bf89000 00001000
    COREBOOT   12. 7bf81000 00008000
    
    And the corresponding e820 entries:
    BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16
    BIOS-e820: [mem 0x0000000000001000-0x000000000002ffff] usable
    BIOS-e820: [mem 0x0000000000030000-0x000000000003ffff] reserved
    BIOS-e820: [mem 0x0000000000040000-0x000000000009ffff] usable
    BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved
    BIOS-e820: [mem 0x0000000000100000-0x0000000000efffff] usable
    BIOS-e820: [mem 0x0000000000f00000-0x0000000000ffffff] reserved
    BIOS-e820: [mem 0x0000000001000000-0x000000007bf80fff] usable
    BIOS-e820: [mem 0x000000007bf81000-0x000000007bffffff] type 16
    BIOS-e820: [mem 0x000000007c000000-0x000000007e9fffff] reserved
    BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved
    BIOS-e820: [mem 0x00000000fed10000-0x00000000fed19fff] reserved
    BIOS-e820: [mem 0x00000000fed84000-0x00000000fed84fff] reserved
    BIOS-e820: [mem 0x0000000100000000-0x00000001005fffff] usable
    
    Change-Id: Ie3bca52211800a8652a77ca684140cfc9b3b9a6b
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2848
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c3221183ee4c5280103238a0068086479cf31ded
Author: Shawn Nematbakhsh <shawnn@google.com>
Date:   Mon Feb 25 12:12:05 2013 -0800

    cbfs: Change false ERROR print to a WARNING.
    
    Change "ERROR" to "WARNING" -- not finding the indicated file is usually
    not a fatal error.
    
    Change-Id: I0600964360ee27484c393125823e833f29aaa7e7
    Signed-off-by: Shawn Nematbakhsh <shawnn@google.com>
    Reviewed-on: http://review.coreboot.org/2833
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 71c7cdc8f40d9dc10c8cf44f8114d45ea54c8fae
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Mar 19 13:38:12 2013 -0700

    Intel: Update CPU microcode for 6fx CPUs
    
    Using the CPU microcode update script and
    Intel's Linux* Processor Microcode Data File
    from 2013-02-22
    
    Change-Id: I9bb60bdc46f69db85487ba923e62315f6e5352f9
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2845
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b70197bfcbba39ca0a0a801ccc50ccaf0f942fa2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Mar 19 13:33:50 2013 -0700

    Intel: Update CPU microcode for 106cx CPUs
    
    Using the CPU microcode update script and
    Intel's Linux* Processor Microcode Data File
    from 2013-02-22
    
    Change-Id: Icaf0e39978daa9308cc2f0c4856d99fb6b7fdffa
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2844
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b631f9cd3f36eb900c115288f3efc4fdaa0ee765
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Mar 19 13:20:47 2013 -0700

    Intel: Update CPU microcode script
    
    for latest URL of their microcode tar ball
    
    Change-Id: I3da2bdac4b2ca7d3f48b20ed389f6a47275d24fe
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2842
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7b8952c19d8d809b7aeec629b31e1c3d66f19884
Author: Shawn Nematbakhsh <shawnn@google.com>
Date:   Thu Mar 14 11:03:59 2013 -0700

    Butterfly, Stout: Force SATA link speed to 3 Gbps
    
    Force link speed on these platforms to 3 Gbps to defeat buggy SATA
    drives.
    
    Change-Id: Ia38a7c486fb1f4469cd67ca5244bbf61f877d556
    Signed-off-by: Shawn Nematbakhsh <shawnn@google.com>
    Reviewed-on: http://review.coreboot.org/2823
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2b7c88f99ed55682378bc0b1aae8004e6e27fe7b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Mar 1 16:56:34 2013 -0600

    rmodule: add string functions to rmodules class
    
    The standard string functions memcmp(), memset(), and memcpy()
    are needed by most programs. The rmodules class provides a way to
    build objects for the rmodules class. Those programs most likely need
    the string functions. Therefore provide those standard functions to
    be used by any generic rmodule program.
    
    Change-Id: I2737633f03894d54229c7fa7250c818bf78ee4b7
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2821
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit deb90f475992c6991f03dbf6035d7b82d2ee9044
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 8 17:22:37 2013 -0800

    lynxpoint: Fix up handling for LynxPoint-LP chipsets
    
    This configures power management registers according to
    the 1.2.0 reference code drop.  There are many inconsistencies
    with the documentation and I tried to note those with ?.
    
    This does not do the same for LynxPoint-H yet.
    
    Change-Id: I9b8f5c24a8b0931075a44398571c9b0d54cce6a6
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2819
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 70f04b41ce07ba5ae0dbdb3112e1d8ed32c83b64
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 8 17:17:33 2013 -0800

    lynxpoint: Change sata.c to get rid of #if
    
    This uses the new helper function added earlier.
    
    Change-Id: Icdb5d5c51f70eeb7e39e11062276ceb3eb3d9473
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2818
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d604090b2866f4d8526731034e55e2ea65a305c6
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 8 17:16:37 2013 -0800

    lynxpoint: Fix ELOG logging of power management events
    
    This is updated to handle LynxPoint-H and LynxPoint-LP
    and a new wake event is added for the power button.
    
    Boot, suspend/resume, reboot, etc on WTM2
    and then check the event log to see if expected events
    have been added.
    
    Change-Id: I15cbc3901d81f4fd77cc04de37ff5fa048f9d3e8
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2817
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 467f31de92ca2ed9df1530270e9aabdd69fe8f88
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 8 17:00:37 2013 -0800

    haswell/lynxpoint: Use new PCH/PM helper functions
    
    This makes use of the new functions from pmutil.c that take
    care of the differences between -H and -LP chipsets.
    
    It also adds support for the LynxPoint-LP GPE0 register block
    and the SMI/SCI routing differences.
    
    The FADT is updated to report the new 256 byte GPE0 block on
    wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address
    block so that part is zeroed to prevent IASL and the kernel
    from complaining about a mismatch.
    
    This was tested on WTM2.  Unfortunately I am still unable to get an
    SCI delivered from the EC but I suspect that is due to a magic
    command needed to put the EC in ACPI mode.  Instead I verified that
    all of the power management and GPIO registers were set to expected
    values.
    
    I also tested transitions into S3 and S5 from both the kernel and
    by pressing the power button at the developer mode screen and they
    all function as expected.
    
    Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2816
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7922b468b51eea58c7238f11b21820b8d3747d6b
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 8 16:34:33 2013 -0800

    lynxpoint: Fix GPIO and PM base reservations
    
    The kernel ACPI was not happy with the Add inside a
    ResourceTemplate (or perhaps within the IO declaration)
    
    Instead make a buffer of IO reservations and turn _CRS
    into a method that updates the buffer depending on the
    chipset type.
    
    This adds an \ISLP() method that checks the chipset LPC
    device ID to see if it is -LP or -H.
    
    It also increases the PM base reservation to 256 bytes
    and moves both GPIO and PM base to above 0x1000 on -LP
    chipsets.
    
    Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2815
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f5966b14e8d2a0613d5cbafbf73d76bed371899d
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 8 16:06:06 2013 -0800

    lynxpoint: remove DEBUG_PERIODIC_SMIS
    
    This was put in for debugging and experimentation on i945
    and has been copied around since. Drop it from lynxpoint.
    
    Change-Id: I0b53f4e1362cd3ce703625ef2b4988139c48b989
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2814
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 55cdf5519074ebaf972edff488be7f1340436ca1
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Mar 8 16:01:44 2013 -0800

    lynxpoint: Add power management helper functions
    
    There are subtle yet significant differences in some of the
    registers in the power management region between LynxPoint-H
    and LynxPoint-LP.
    
    In order to reduce code that is accessing these registers and
    would need special cases this adds a number of helper functions
    that can be used in both ramstage and SMM.
    
    This commit just adds the new functions, subsequent commits will
    start to use them.
    
    Change-Id: I411da75da519f5b3198a408078cbf3114e426992
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2813
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1ad5564dd675a246f5b0a05d03482836d49d44a9
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Mar 7 14:08:04 2013 -0800

    lynxpoint: Add helper functions for reading PM and GPIO base
    
    These base addresses are used in several places and it
    is helpful to have one location that is reading it.
    
    Change-Id: Ibf589247f37771f06c18e3e58f92aaf3f0d11271
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2812
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5cc51c08cd44e2749f4a27775cefffd4b91e0a50
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Mar 7 14:06:43 2013 -0800

    lynxpoint: Add function for checking for LP chipset
    
    Add a helper function pch_is_lp() that will return 1 if
    the current chipset is of the new "low power" variant used
    with Haswell ULT.
    
    Additionally these functions are added to SMM so it can
    be used there.
    
    Change-Id: I9acdea2c56076cd8d9627aba66cf0844c56a38fb
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2811
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7a3fd4de053e055ce6854e7ec42fb00da532d3d3
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Mar 7 14:00:43 2013 -0800

    lynxpoint: Enable EC IO ports 0x62/0x66
    
    In order to be able to talk to an EC via standard path.
    
    Change-Id: I3fe76882dec9a0596cbc1c844afa2ddb03ed771c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2810
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 969ac8db18214cd56cf7d928cc3962554152a2de
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Mar 7 13:59:39 2013 -0800

    haswell: Drop the device ID check in graphics init path
    
    Change-Id: I10c4264d317b5fac02a44f50ed10b457e1865e17
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2809
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b37d1fb95ae810bf8f55cc30aa6a5ca921c1ca05
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Feb 25 10:51:52 2013 -0600

    lynxpoint: update MBP give up routine
    
    I'm not sure if I screwed this up originally or the Intel docs changed
    (I didn't bother to go back and check). According to ME BWG 1.1.0 the give
    up bit is in the host general status #2 register.
    
    Change-Id: Ieaaf524b93e9eb9806173121dda63d0133278c2d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2808
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b86113fd9ade587f7cb69b8c0c5d6407917fb185
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Feb 19 08:59:16 2013 -0600

    haswell: RESET_ON_INVALID_RAMSTAGE_CACHE option
    
    The RESET_ON_INVALID_RAMSTAGE_CACHE option indicates what to do
    when the ramstage cache is found to be invalid on a S3 wake. If
    selected the system will perform a system reset on S3 wake when the
    ramstage cache is invalid. Otherwise it will signal to load the
    ramstage from cbfs.
    
    Change-Id: I8f21fcfc7f95fb3377ed2932868aa49a68904803
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2807
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f7cdfe5b328dbddeead9ff62d19e9bed37f0295f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Sat Feb 16 00:05:52 2013 -0600

    haswell: implement ramstage caching in SMM region
    
    Cache the relocated ramstage into the SMM region. There is
    a reserved region within the final SMM region (TSEG). Use that
    space to cache the relocated ramstage program. That way, on S3 resume
    there is a copy that can be loaded quickly instead of accessing the
    flash. Caching the ramstage in the SMM space is also helpful in that
    it prevents the OS from tampering with the ramstage program.
    
    Change-Id: Ifa695ad1c350d5b504b14cc29d3e83c79b317a62
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2806
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit de1f890186ce84963eb3dd1638784473193909c3
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 15 23:26:52 2013 -0600

    coreboot: add caching loaded ramstage interface
    
    Instead of hard coding the policy for how a relocated ramstage
    image is saved add an interface. The interface consists of two
    functions.  cache_loaded_ramstage() and load_cached_ramstage()
    are the functions to cache and load the relocated ramstage,
    respectively. There are default implementations which cache and
    load the relocated ramstage just below where the ramstage runs.
    
    Change-Id: I4346e873d8543e7eee4c1cd484847d846f297bb0
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2805
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8ce667e50684bea7c60db43c0ca7dd1b3ec3fde3
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 15 21:45:06 2013 -0600

    haswell: add multipurpose SMM memory region
    
    The SMM region is available for multipurpose use before the SMM
    handler is relocated. Provide a configurable sized region in the
    TSEG for use before the SMM handler is relocated. This feature is
    implemented by making the reserved size a Kconfig option. Also
    make the IED region a Kconfig option as well. Lastly add some sanity
    checking on the Kconfig options.
    
    Change-Id: Idd7fccf925a8787146906ac766b7878845c75935
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2804
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 67481ddc2e53cd3420fa8c723edb4fe47dccc196
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 15 15:08:37 2013 -0600

    haswell: set TSEG as WB cacheable in romstage
    
    The TSEG region is accessible until the SMM handler is relocated
    to that region. Set the region as cacheable in romstage so that it
    can be used for other purposes with fast access.
    
    Change-Id: I92b83896e40bc26a54c2930e05c02492918e0874
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2803
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8584b223fe1a0c9da9a94e28b135cfc7414601dc
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Feb 15 13:52:28 2013 -0800

    LynxPoint: Move RCBA helper function to its own file
    
    So it can get used in both romstage and ramstage.
    
    Change-Id: Ief9eaafdd91df2a7b668de1a9b83aea3af3ff894
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2802
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 738af675d1b29847112f32b3fb2ac2524bb7c4ca
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Feb 13 11:22:25 2013 -0600

    haswell: support for parallel SMM relocation
    
    The haswell processors support the ability to save their SMM state
    into MSR space instead of the memory. This feaure allows for parallel
    SMM relocation handlers as well as setting the same SMBASE for each
    CPU since the save state memory area is not used.
    
    The catch is that in order determine if this feature is available the
    CPU needs to be in SMM context. In order to implement parallel SMM
    relocation the BSP enters the relocation handler twice. The first time
    is to determine if that feature is available. If it is, then that
    feature is enabled the BSP exits the relocation handler without
    relocating SMBASE. It then releases the APs to run the SMM relocation
    handler. After the APs have completed the relocation the BSP will
    re-enter the SMM relocation handler to relocate its own SMBASE to the
    final location.  If the parallel SMM feature is not available the BSP
    relocates its SMBASE as it did before.
    
    This change also introduces the BSP waiting for the APs to relocate
    their SMBASE before proceeding with the remainder of the boot process.
    
    Ensured both the parallel path and the serial path still continue
    to work on cold, warm, and S3 resume paths.
    
    Change-Id: Iea24fd8f9561f1b194393cdb77c79adb48039ea2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2801
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 159f2ef03a59607c58c0474f9b2941b03710b498
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Feb 12 00:50:47 2013 -0600

    ramstage: cache relocated ramstage in RAM
    
    Accessing the flash part where the ramstage resides can be slow
    when loading it. In order to save time in the S3 resume path a copy
    of the relocated ramstage is saved just below the location the ramstage
    was loaded. Then on S3 resume the cached version of the relocated
    ramstage is copied back to the loaded address.
    
    This is achieved by saving the ramstage entry point in the
    romstage_handoff structure as reserving double the amount of memory
    required for ramstage. This approach saves the engineering time to make
    the ramstage reentrant.
    
    The fast path in this change will only be taken when the chipset's
    romstage code properly initializes the s3_resume field in the
    romstage_handoff structure. If that is never set up properly then the
    fast path will never be taken.
    
    e820 entries from Linux:
    BIOS-e820: [mem 0x000000007bf21000-0x000000007bfbafff] reserved
    BIOS-e820: [mem 0x000000007bfbb000-0x000000007bffffff] type 16
    
    The type 16 is the cbmem table and the reserved section contains the two
    copies of the ramstage; one has been executed already and one is
    the cached relocated program.
    
    With this change the S3 resume path on the basking ridge CRB shows
    to be ~200ms to hand off to the kernel:
    
    13 entries total:
    
       1:95,965
       2:97,191 (1,225)
       3:131,755 (34,564)
       4:132,890 (1,135)
       8:135,165 (2,274)
       9:135,840 (675)
      10:135,973 (132)
      30:136,016 (43)
      40:136,581 (564)
      50:138,280 (1,699)
      60:138,381 (100)
      70:204,538 (66,157)
      98:204,615 (77)
    
    Change-Id: I9c7a6d173afc758eef560e09d2aef5f90a25187a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2800
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bf396ff21c60f364e5d0af4eda1e38f4603fc3b1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Feb 11 21:50:35 2013 -0600

    haswell: use s3_resume field in romstage_handoff
    
    Now that there is a way to disseminate the presence of s3 wake more
    formally use that instead of hard coded pointers in memory and stashing
    magic values in device registers. The northbridge code picks up the
    field's presence in the romstage_handoff structure and sets up the
    acpi_slp_type variable accordingly.
    
    Change-Id: Ida786728ce2950bd64610a99b7ad4f1ca6917a99
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2799
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 605ca1bb9c7e9da8bacf07e96e2da187acf3090b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Feb 12 00:46:17 2013 -0600

    haswell: cbmem_get_table_location() implementation
    
    Provide the implemenation of cbmem_get_table_location() so that
    cbmem can be initialized early in ramstage when CONFIG_EARLY_CBMEM_INIT
    is enabled. The cbmem tables are located just below the TSEG region.
    
    Change-Id: Ia160ac6aff583fc52bf403d047529aaa07088085
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2798
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 25fe2d04d583cfaaf55b8f3861f1fad86885d818
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Feb 12 00:40:30 2013 -0600

    ramstage: Add cbmem_get_table_location()
    
    When CONFIG_EARLY_CBMEM_INIT is selected romstage is supposed to have
    initialized cbmem. Therefore provide a weak function for the chipset
    to implement named cbmem_get_table_location(). When
    CONFIG_EARLY_CBMEM_INIT is selected cbmem_get_table_location() will be
    called to get the cbmem location and size. After that cbmem_initialize()
    is called.
    
    Change-Id: Idc45a95f9d4b1d83eb3c6d4977f7a8c80c1ffe76
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2797
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c00457d065a0b57e8e2e8abc9318fc6e1198ee64
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Feb 11 21:15:12 2013 -0600

    romstage_handoff: add s3_resume field
    
    Provide a field in the romstage_handoff structure to indicate if the
    current boot is an ACPI S3 wake boot. There are currently quite a few
    non-standardized ways of passing this knowledge to ramstage from
    romstage. Many utilize stashing magic numbers in device-specific
    registers. The addition of this field adds a more formalized method
    passing along this information. However, it still requires the romstage
    chipset code to initialize this field. In short, this change does not
    make this a hard requirement for ramstage.
    
    Change-Id: Ia819c0ceed89ed427ef576a036fa870eb7cf57bc
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2796
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f2b20d898a652889a819478174316cff235a501b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Feb 11 21:07:18 2013 -0600

    romstage_handoff: provide common logic for setup
    
    The romstage_handoff structure can be utilized from different components
    of the romstage -- some in the chipset code, some in coreboot's core
    libarary. To ensure that all users handle initialization of a newly
    added romstage_handoff structure properly, provide a common function to
    handle structure initialization.
    
    Change-Id: I3998c6bb228255f4fd93d27812cf749560b06e61
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2795
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ef4275bc2e4332ed9b6f3ac25060687794f0b98d
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 8 22:31:33 2013 -0600

    x86: protect against abi assumptions from compiler
    
    Some of the functions called from assembly assume the standard
    x86 32-bit ABI of passing all arguments on the stack. However,
    that calling ABI can be changed by compiler flags. In order to
    protect against the current implicit calling convention annotate
    the functions called from assembly with the cdecl function
    attribute. That tells the compiler to use the stack based parameter
    calling convention.
    
    Change-Id: I83625e1f92c6821a664b191b6ce1250977cf037a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2794
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e2d9e5bfa99e56eff56ab9b0f3389cfccd9670d6
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 8 17:38:35 2013 -0600

    haswell: support for CONFIG_RELOCATABLE_RAMSTAGE
    
    Now that CONFIG_RELOCTABLE_RAMSTAGE is available support it on
    Haswell-based systems. This patch is comprised of the following changes:
    
    1. Ensure that memory is not preserved when a relocatable ramstage is
       enabled. There is no need.
    2. Pick the proper stack to use after cache-as-ram is torn down. When
       the ramstage is relocatable, finding a stack to use before vectoring
       into ramstage is impossible since the ramstage is a black box with an
       unknown layout.
    
    Change-Id: I2a07a497f52375569bae9c994432a8e7e7a40224
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2793
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8e4a355773cc64a89b3fc4d79981cfb02bda7e66
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 8 17:28:04 2013 -0600

    coreboot: introduce CONFIG_RELOCATABLE_RAMSTAGE
    
    This patch adds an option to build the ramstage as a reloctable binary.
    It uses the rmodule library for the relocation. The main changes
    consist of the following:
    
    1. The ramstage is loaded just under the cmbem space.
    2. Payloads cannot be loaded over where ramstage is loaded. If a payload
       is attempted to load where the relocatable ramstage resides the load
       is aborted.
    3. The memory occupied by the ramstage is reserved from the OS's usage
       using the romstage_handoff structure stored in cbmem. This region is
       communicated to ramstage by an CBMEM_ID_ROMSTAGE_INFO entry in cbmem.
    4. There is no need to reserve cbmem space for the OS controlled memory for
       the resume path because the ramsage region has been reserved in #3.
    5. Since no memory needs to be preserved in the wake path, the loading
       and begin of execution of a elf payload is straight forward.
    
    Change-Id: Ia66cf1be65c29fa25ca7bd9ea6c8f11d7eee05f5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2792
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin@google.com>

commit 43e4a80a92bf00540e4d9b0734eb53f32044226f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Mar 21 13:15:45 2013 -0700

    Fix race condition building console code
    
    On ARMv7 the console code can also be built into
    the bootblock. Currently building the ARM targets
    on a reasonably fast machine can fail, because
    console.bootblock.o is attempted to build before
    build.h is created. This patch adds a specific
    rule for the bootblock variant of console.c, to
    match the other variants so that the race condition
    goes away.
    
    Change-Id: I52e4242c66a02f011ef26b854aa50c2606a1f81f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2873
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cddcc80048ab963f96d13575a3f63070cf6d7c14
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 8 17:15:53 2013 -0600

    coreboot: introduce romstage_handoff structure
    
    The romstage_handoff structure is intended to be a way for romstage and
    ramstage to communicate with one another instead of using sideband
    signals such as stuffing magic values in pci config or memory
    scratch space. Initially this structure just contains a single region
    that indicates to ramstage that it should reserve a memory region used
    by the romstage. Ramstage looks for a romstage_handoff structure in cbmem
    with an id of CBMEM_ID_ROMSTAGE_INFO. If found, it will honor reserving
    the region defined in the romstage_handoff structure.
    
    Change-Id: I9274ea5124e9bd6584f6977d8280b7e9292251f0
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2791
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a1db81b47a74ce53b8403eed28876efccf0bcefe
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 8 17:11:28 2013 -0600

    cbmem: add CBMEM_ID_ROMSTAGE_INFO id
    
    Introduce a new cbmem id to indicate romstage information. Proper
    coordination with ramstage and romstage can use this cbmem entity
    to communicate between one another.
    
    Change-Id: Id785f429eeff5b015188c36eb932e6a6ce122da8
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2790
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit a146d58ca0375a12f23dc5a4bd25adfa3423114f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 8 16:56:51 2013 -0600

    ramstage: prepare for relocation
    
    The current ramstage code contains uses of symbols that cause issues
    when the ramstage is relocatable. There are 2 scenarios resolved by this
    patch:
    
    1. Absolute symbols that are actually sizes/limits. The symbols are
       problematic when relocating a program because there is no way to
       distinguish a symbol that shouldn't be relocated and one that can.
       The only way to handle these symbols is to write a program to post
       process the relocations and keep a whitelist of ones that shouldn't
       be relocated. I don't believe that is a route that should be taken
       so fix the users of these sizes/limits encoded as absolute symbols
       to calculate the size at runtime or dereference a variable in memory
       containing the size/limit.
    
    2. Absoulte symbols that were relocated to a fixed address. These
       absolute symbols are generated by assembly files to be placed at a
       fixed location. Again, these symbols are problematic because one
       can't distinguish a symbol that can't be relocated. The symbols
       are again resolved at runtime to allow for proper relocation.
    
    For the symbols defining a size either use 2 symbols and calculate the
    difference or provide a variable in memory containing the size.
    
    Change-Id: I1ef2bfe6fd531308218bcaac5dcccabf8edf932c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2789
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit e8c866ad45d80de768c9422474449e171d133575
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 8 17:05:36 2013 -0600

    rmodule: add ability to calculate module placement
    
    There is a need to calculate the proper placement for an rmodule
    in memory. e.g. loading a compressed rmodule from flash into ram
    can be an issue. Determining the placement is hard since the header
    is not readable until it is decompressed so choosing the wrong location
    may require a memmove() after decompression. This patch provides
    a function to perform this calculation by finding region below a given
    address while making an assumption on the size of the rmodule header..
    
    Change-Id: I2703438f58ae847ed6e80b58063ff820fbcfcbc0
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2788
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 426ce4192bd127ceaab52d94468b66d718608572
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 19 18:38:48 2013 -0700

    armv7: add function for dcache_clean_by_mva()
    
    This adds a function for using the DCCMVAC instruction (dcache clean
    by MVA at point of coherency (main memory)). We already have the
    inline defined, it's just not used by anything.
    
    Change-Id: Ia0641566a8881335bed8da2963e1db8321d74267
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2871
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 758abdd75b22108b14427edc3704a84783759c27
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 19 17:57:59 2013 -0700

    armv7: add a helper function for dcache ops by MVA
    
    This adds a helper function for dcache ops by MVA which will perform
    the specified operation on a given memory range. This will make it
    more trivial to add other data cache maintenance routines.
    
    Change-Id: I01d746d5fd2f4138257ca9cab9e9d738e73f8633
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2870
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit a54efdcf8cd8cc0f5f879fdf229b2e479bf0bcd1
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 19 17:32:54 2013 -0700

    armv7: cosmetic changes to new cache code
    
    This clarifies and/or fixes formatting of some comments and
    alphabetizes some function prototypes and inlines. It also
    corrects references to "modified virtual address" (MVA).
    
    Change-Id: Ibcdda4febf915cc4a1996a5bbb4ffecbcb50a324
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2869
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 2138afe943edec9237790583bc1b699436fd4da4
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 19 17:12:46 2013 -0700

    armv7: remove old isb() and dsb() macros
    
    This removes some old macros that we no longer use.
    
    Change-Id: I9d87beb5c2deca228cdf89a98e54b2779be0f0ea
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2868
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 8ec69053f1a9f107f73f018fd613cf3038a12c7c
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 19 17:11:31 2013 -0700

    armv7: move armv7_invalidate_caches() to cache.c
    
    This just moves cache maintenance stuff from the armv7 bootblock
    code to cache.c
    
    Change-Id: I0b3ab58a1d8a3fe3d9568e02e156a36b6f33ca0b
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2867
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit eb06a4259b48128faed94b4ca3f8c64d3cd5a4c3
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Mar 20 13:49:27 2013 -0500

    x86: don't clear bss in ramstage entry
    
    The cbfs stage loading routine already zeros out the full
    memory region that a stage will be loaded. Therefore, it is
    unnecessary to to clear the bss again after once ramstage starts.
    
    Change-Id: Icc7021329dbf59bef948a41606f56746f21b507f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2865
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1cc4737c3bc7e0b1e560f3d049f4edbef9340177
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Wed Mar 20 15:28:31 2013 +0800

    f15tn/Include/OptionIdsInstall.h: Remove idle `… || )`
    
    Change-Id: I4aba6cc490ab24c6db345c0c5a64a6a9985ed0ab
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/2864
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 70ae9ecb9beed3964c215362494e58c6ef37f95e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Feb 28 11:19:23 2013 -0600

    ARM: remove assembly code dump when stages.o is built
    
    For diagnostic purposes we had been dumping the assembly
    code when stages.o was built. We've past the need to do this
    and it's confusing to watch.
    
    Change-Id: Ib84cb73ed9dad3454efcb2be90d990ce88575229
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2555
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 9f3a7a3251f605a30464472e91c04a1dd8baf67e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Feb 28 15:21:41 2013 -0600

    ARM: Fix the ldscripts so that exit/enter stage work correctly.
    
    Remove the spurious creation of a start symbol, and use the
    stage_entry symbol directly.
    
    Change-Id: Ia62d5c056ac8b20c8ffdb78bff3d306065b6c45f
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2560
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 28b99c05a1424848254d82d0736cdf99c90f5b67
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Fri Mar 8 11:57:52 2013 -0700

    Supermicro H8SCM: Use SPD read code from F15 wrapper
    
    Changes:
     - Get rid of the h8scm mainboard specific code and use the
       platform generic function wrapper that was added in change
       http://review.coreboot.org/#/c/2777/
       AMD Fam15: Add SPD read functions to wrapper code
    
     - Move DIMM addresses into devicetree.cb
    
    Notes:
     - The DIMM reads only happen in romstage, so the function is not
       available in ramstage.  Point the read-SPD callback to a generic
       function in ramstage.
    
    Change-Id: I575221039ad65a59ae0f93397ef1038b669e81c7
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2829
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2a9145e743ee9d10174c469a9fc1dad0ad75d73d
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Thu Mar 7 17:12:36 2013 -0700

    AMD Dinar: Use SPD read code from F15 wrapper
    
    Changes:
     - Get rid of the dinar mainboard specific code and use the
       platform generic function wrapper that was added in change
       http://review.coreboot.org/#/c/2777/
       AMD Fam15: Add SPD read functions to wrapper code
    
     - Move DIMM addresses into devicetree.cb
    
    Notes:
     - The DIMM reads only happen in romstage, so the function is not
       available in ramstage.  Point the read-SPD callback to a generic
       function in ramstage.
     - select_socket() and restore_socket() were created from code that
       was removed from AmdMemoryReadSPD() in dimmSpd.c.  The functionality
       is specific to the dinar mainboard configuration and was therefore
       split from the generic read SPD functionality.
    
    Change-Id: I1e4b9a20dc497c15dbde6d89865bd5ee7501cdc0
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2830
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b37ec540affaaeb3a8a230895c08778c54f1d076
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Fri Mar 8 15:31:49 2013 -0700

    Tyan S8226: Use SPD read code from F15 wrapper
    
    Changes:
     - Get rid of the s8226 mainboard specific code and use the
       platform generic function wrapper that was added in change
       http://review.coreboot.org/#/c/2777/
       AMD Fam15: Add SPD read functions to wrapper code
    
     - Move DIMM addresses into devicetree.cb
    
    Notes:
     - The DIMM reads only happen in romstage, so the function is not
       available in ramstage.  Point the read-SPD callback to a generic
       function in ramstage.
     - select_socket() and restore_socket() started by duplicating
       sp5100_set_gpio() and sp5100_restore_gpio(), which were in
       dimmSpd.c.  In addition to renaming the functions to more
       specifically state their purpose, some cleanup and magic number
       reduction was done.
    
    Change-Id: I1eaf64986ef4fa3f89aed2b69d3f9c8c913f726f
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2827
    Tested-by: build bot (Jenkins)
    Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit eef45f9cfd016343fbcf92b4df5b3d76a39c5136
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Fri Mar 8 13:54:10 2013 -0700

    Supermicro H8QGI: Use SPD read code from F15 wrapper
    
    Changes:
     - Get rid of the h8qgi mainboard specific code and use the
       platform generic function wrapper that was added in change
       http://review.coreboot.org/#/c/2777/
       AMD Fam15: Add SPD read functions to wrapper code
    
     - Move DIMM addresses into devicetree.cb
    
    Notes:
     - The DIMM reads only happen in romstage, so the function is not
       available in ramstage.  Point the read-SPD callback to a generic
       function in ramstage.
     - select_socket() and restore_socket() started by duplicating
       sp5100_set_gpio() and sp5100_restore_gpio(), which were in
       dimmSpd.c.  In addition to renaming the functions to more
       specifically state their purpose, some cleanup and magic number
       reduction was done.
    
    Change-Id: I346ebd8399d4ba3e280576e667fdc62fa75a63b8
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2828
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e4ea2ca18d4764f8c79560d373d548d52532566d
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Mar 19 12:24:43 2013 +0800

    cbfstool locate: Implement alignment switch --align/-a
    
    cbfstool usage change:
     "-a" for "cbfstool locate" can specify base address alignment.
    
    To support putting a blob in aligned location (ex, microcode needs to be aligned
    in 0x10), alignment (-a) is implemented into "locate" command.
    
    Verified by manually testing a file (324 bytes) with alignment=0x10:
     cbfstool coreboot.rom locate -f test -n test -a 0x10
     # output: 0x71fdd0
     cbfstool coreboot.rom add -f test -n test -t raw -b 0x71fdd0
     cbfstool coreboot.rom print -v -v
     # output: test                           0x71fd80   raw          324
     # output:  cbfs_file=0x71fd80, offset=0x50, content_address=0x71fdd0+0x144
    
    Also verified to be compatible with old behavior by building i386/axus/tc320
    (with page limitation 0x40000):
     cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000
     # output: 0x44
     cbfstool coreboot.rom locate -f x.bin -n romstage -P 0x40000 -a 0x30
     # output: 0x60
    
    Change-Id: I78b549fe6097ce5cb6162b09f064853827069637
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2824
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit b3b72f350e22ecdfa8e228b820f46da805d4f230
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Mar 13 14:35:01 2013 -0700

    link/graphics: Add support for EDID
    
    This code is taken from an EDID reader written at Red Hat.
    
    The key function is
    int decode_edid(unsigned char *edid, int size, struct edid *out)
    
    Which takes a pointer to an EDID blob, and a size, and decodes it into
    a machine-independent format in out, which may be used for driving
    chipsets. The EDID blob might come for IO, or a compiled-in EDID
    BLOB, or CBFS.
    
    Also included are the changes needed to use the EDID code on Link.
    
    Change-Id: I66b275b8ed28fd77cfa5978bdec1eeef9e9425f1
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2837
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a95a13bd474fa7738840496b657cd46784e3f6b2
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Mar 5 17:07:40 2013 -0800

    link/graphics: New state machine
    
    This is a new state machine. It is more programmatic, in the
    case of auxio, and has much more symbolic naming, and very few
    "magic" numbers, except in the case of undocumented settings.
    
    As before, the 'pre-computed' IO ops are encoded in the iodefs
    table. A function, run, is passed and index into the table and
    runs the ops.
    
    A new operator, I, has been added. When the I operator is hit,
    run() returns the index of the next operator in the table.
    
    The i915lightup function runs the table. All the AUX channel ops
    have been removed from the table, however, and are now called as
    functions, using the previously committed auxio function.
    
    The iodefs table has been grouped into blocks of ops, which end in
    an I operator. As the lightup function progresses through startup,
    and the run() returns, the lightup function performs aux channel
    operations.
    
    This code is symbolic enough, I hope, that it will make haswell
    graphics bringup simpler.
    
    i915io.c, and the core of the code in i915lightup.c, were
    programatically generated, starting with IO logs from the DRM
    startup code in the kernel. It is possible to apply the tools that
    do this generation to newer IO logs from the kernel.
    
    Change-Id: I8a8e121dc0d9674f0c6a866343b28e179a1e3d8a
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2836
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ec2d914e198928f89928838476ddbd6e5ef61b98
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Tue Mar 5 13:32:24 2013 -0800

    link/graphics: implement a palette setting operator
    
    Add a  new operator, P, for the state machine, meaning
    implement a palette fill.
    
    Implement a function (palette) that fills the palette when the
    P operator is hit.
    
    This replaces 256 lines in the state machine table with 1.
    
    Change-Id: I67d9219fe7de0ecf1fb9faf92130c00c9f5f8e88
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/2835
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d466d750d71f979ccd6636306b51f2d87cb19cba
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Mar 19 12:41:29 2013 -0500

    x86: provide more C standard environment
    
    There are some external libraries that are built within
    coreboot's environment that expect a more common C standard
    environment. That includes things like inttypes.h and UINTx_MAX
    macros. This provides the minimal amount of #defines and files
    to build vboot_reference.
    
    Change-Id: I95b1f38368747af7b63eaca3650239bb8119bb13
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2859
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0013a69e7098804a461ab005b33240b8addfbf8f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Mar 7 14:20:13 2013 -0800

    haswell: drop memory reservation for sandybridge GPU bug
    
    This is not needed in haswell.
    
    Change-Id: I23817c2e01be33855f9d5a5e389e8ccb7954c0e2
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2847
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2c3f16182523dbfd7b2ba490a93698377232ce57
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Mar 19 13:46:03 2013 -0700

    Intel: Update CPU microcode for Sandybridge/Ivybridge CPUs
    
    Using the CPU microcode update script and
    Intel's Linux* Processor Microcode Data File
    from 2013-02-22
    
    Change-Id: I853e381240b539b204c653404ca3d46369109219
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2846
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 511c4b7f638a0f22761b135a42cba0a57fdb5e8f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Mar 19 13:30:27 2013 -0700

    Intel: Update CPU microcode for 1067x CPUs
    
    Using the CPU microcode update script and
    Intel's Linux* Processor Microcode Data File
    from 2013-02-22
    
    Change-Id: I4585288905cf7374e671894ab37f125220ae535e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2843
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 665e3d23f0ca5bfac0d1ad9b7a8cde383ec56289
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Feb 27 09:54:47 2013 -0800

    link/graphics: add functions to support aux channel communications
    
    For full integration of FUI into coreboot, we need aux channel
    communcations.  The intel_dp.c is a file taken from Linux and is
    used for aux channel comms.  This file has been cut down to work
    with coreboot.  For now it is associated with the link mainboard
    until we get a better handle on how this all fits together.  This
    code is almost certainly usable on other platforms in the long term.
    But one step at a time.
    
    Change-Id: I7be4c56e0a7903f3901ac86e12b28f3bdc0f7947
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/2834
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bba809042191bd3e421bdec0b974ce697e85bcba
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 14 15:24:57 2013 -0700

    armv7/exynos/snow: new cache maintenance API
    
    This adds a new API for cache maintenance operations. The idea is
    to be more explicit about operations that are going on so it's easier
    to manage branch predictor, cache, and TLB cleans and invalidations.
    
    Also, this adds some operations that were missing but required early
    on, such as branch predictor invalidation. Instruction and sync
    barriers were wrong earlier as well since the imported API assumed
    we compield with -march=armv5 (which we don't) and was missing
    wrappers for the native ARMv7 ISB/DSB/DMB instructions.
    
    For now, this is a start and it gives us something we can easily use
    in libpayload for doing things like cleaning and invalidating dcache
    when doing DMA transfers.
    
    TODO:
    - Set cache policy explicitly before re-enabling. Right now it's left
      at default.
    - Finish deprecating old cache maintenance API.
    - We do an extra icache/dcache flush when going from bootblock to
      romstage.
    
    Change-Id: I7390981190e3213f4e1431f8e56746545c5cc7c9
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2729
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f7c6d489ae28af611811515c1df96cfb10c79e9f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Feb 6 15:47:31 2013 -0600

    rmodule: add ramstage support
    
    Coreboot's ramstage defines certain sections/symbols in its fixed
    static linker script. It uses these sections/symbols for locating the
    drivers as well as its own program information.  Add these sections
    and symbols to the rmodule linker script so that ramstage can be
    linked as an rmodule. These sections and symbols are a noop for other
    rmodule-linked programs, but they are vital to the ramstage.
    
    Also add a comment in coreboot_ram.ld to mirror any changes made there
    to the rmodule linker script.
    
    Change-Id: Ib9885a00e987aef0ee1ae34f1d73066e15bca9b1
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2786
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 991ce8fc74ff80cbe2c1c892e40aac0b209f35c4
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Mar 18 21:54:13 2013 -0700

    google/snow: fix a GPIO array index
    
    This fixes a trivial error with the recovery mode GPIO index.
    
    Change-Id: I7290c1e23cdddaf91c9021d4e4252c0c772b6eab
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2825
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 94998c4d3fa1c9f1f0aaf3623a070e8c7e364f8b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Jan 22 13:54:12 2013 -0600

    lynxpoint: Add cbfs_load_payload() implementation
    
    SPI accesses can be slow depending on the setup and the access pattern.
    The current SPI hardware setup to cache and prefetch. The alternative
    cbfs_load_payload() function takes advantage of the caching in the CPU
    because the ROM is cached as write protected as well as the SPI's
    hardware's caching/prefetching implementation. The CPU will fetch
    consecutive aligned cachelines which will hit the ROM as
    cacheline-aligned addresses. Once the payload is mirrored into RAM the
    segment loading can take place by reading RAM instead of ROM.
    
    With the alternative cbfs_load_payload() the boot time on a baskingridge
    board saves ~100ms. This savings is observed using cbmem.py after
    performing warm reboots and looking at TS_SELFBOOT_JUMP (99) entries.
    This is booting with a depthcharge payload whose payload file fits
    within the SMM_DEFAULT_SIZE (0x10000 bytes).
    
    Datapoints with TS_LOAD_PAYLOAD (90) & TS_SELFBOOT_JUMP (99) cbmem entries:
    
    Baseline                          Alt
    --------                          --------
    90:3,859,310  (473)               90:3,863,647  (454)
    99:3,989,578  (130,268)           99:3,888,709  (25,062)
    
    90:3,899,450  (477)               90:3,860,926  (463)
    99:4,029,459  (130,008)           99:3,890,583  (29,657)
    
    90:3,834,600  (466)               90:3,890,564  (465)
    99:3,964,535  (129,934)           99:3,920,213  (29,649)
    
    Booted baskingridge many times and observed 100ms reduction in
    TS_SELFBOOT_JUMP times (time to load payload).
    
    Change-Id: I27b2dec59ecd469a4906b4179b39928e9201db81
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2783
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 633f11274fcbc9442be0be0d0bc531f43a74981b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Feb 6 15:28:40 2013 -0600

    x86: remove stack definition in linker script
    
    In order to prepare the ramstage to be linked by the rmodule linker the
    stack needs to be self-contained within the ramstage objects. The
    reasoning is that the rmodule linker provides a way to define a heap,
    but it doesn't currently have a region for the stack.
    
    The downside to this is that memory footprint of the ramstage can change
    when compared before this change. The size difference stems from the
    link ordering of the objects as the stack is now defined within
    c_start.S. The size fluctuation ranges from 0 to CONFIG_STACK_SIZE - 1
    because of the previous behavior or aligning to CONFIG_STACK_SIZE. It
    should be noted that such an alignment is unnecessary for 32-bit x86 as
    the alignment requirement for the stacks are 4 byte alignment. Also the
    memory footprint is still dominated by CONFIG_RAMTOP and CONFIG_RAMBASE.
    
    Change-Id: I63a4ddd249104bc27aff2ab6b39fc6db12b54028
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2785
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 81108b90593e1c8a459c499307404955771c54f3
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Jan 22 13:22:02 2013 -0600

    cbfs: alternative support for cbfs_load_payload()
    
    In certain situations boot speed can be increased by providing an
    alternative implementation to cbfs_load_payload(). The
    ALT_CBFS_LOAD_PAYLOAD option allows for the mainboard or chipset to
    provide its own implementation.
    
    Booted baskingridge board with alternative and regular
    cbfs_load_payload().
    
    Change-Id: I547ac9881a82bacbdb3bbdf38088dfcc22fd0c2c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2782
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 4063ede3fb571110c3e65c321049cc2687cc54fa
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Mon Feb 4 20:31:51 2013 -0800

    bd82x6x: Fix compiling with USB debug port support
    
    At some point, compiles with USB Debug port stopped working. This change makes
    a trivial reordering in the code and adds two makefile entries to make it build
    without errors. It also works on stout.
    
    Build and boot as normal. Works. Enable CONFIG_USB, connect USB debug hardware
    to the correct port (on stout, that's the one on the left nearest the back) and
    watch for output.
    
    Change-Id: I7fbb7983a19b0872e2d9e4248db8949e72beaaa0
    Signed-off-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/2784
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit fa91819e898b6df59fbff44c0f4dfccf2fee6e48
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Thu Mar 7 16:42:09 2013 -0700

    AMD Fam15: Add SPD read functions to wrapper code
    
    Change:
    This is the initial step for moving the AMD F15 & HUDSON1,2,3
    SPD-read callout out of the mainboard directories and into
    the wrapper.  The next step is to update the platforms to use
    this routine in BiosCallouts.c and to delete the code from the
    mainboard directories.  The DIMM addresses should be moved into
    devicetree.cb.
    If there are significant differences or reasons that the mainboard
    needs to override this code, it's perfectly reasonable to keep using
    the version in the mainboard, but this allows us to remove duplicated
    code and simplify the mainboard directories.
    
    Notes:
    This started by duplicating what was in Dinar, and was changed to
    use the devicetree.cb structures.  Significant cleanup and magic
    number reduction was done as well.
    
    It is intended that this file will not be included in ramstage as
    the DIMM init is all done in romstage.
    
    This is similar to what was done for Parmer/Thatcher in commit
    7fb692bd - http://review.coreboot.org/#/c/2190/
    Fam15tn: Move SPD read from mainboards into wrapper
    
    Yes, it would make sense to split this into two separate files
    and move the SMBus initialization and access into the southbridge
    wrapper.  Maybe that can come next.
    
    Change-Id: I4e00ada288e1486cf30684403505e475f9093ec2
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2777
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit e91983767c64f5541bae44d3b95fa2646bc1a311
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Mar 19 12:17:12 2013 +0800

    cbfstool locate: Rename -a align switch to -P for page size
    
    cbfstool usage change:
       The "-a" parameter for "cbfstool locate" is switched to "-P/--page-size".
    
    The "locate" command was used to find a place to store ELF stage image in one
    memory page. Its argument "-a (alignment)" was actually specifying the page size
    instead of doing memory address alignment. This can be confusing when people are
    trying to put a blob in aligned location (ex, microcode needs to be aligned in
    0x10), and see this:
      cbfstool coreboot.rom locate -f test.bin -n test -a 0x40000
      # output: 0x44, which does not look like aligned to 0x40000.
    
    To prevent confusion, it's now switched to "-P/--page-size".
    
    Verified by building i386/axus/tc320 (with page limitation 0x40000):
     cbfstool coreboot.rom locate -f romstage_null.bin -n romstage -P 0x40000
     # output: 0x44
    
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Change-Id: I0893adde51ebf46da1c34913f9c35507ed8ff731
    Reviewed-on: http://review.coreboot.org/2730
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit e29e2ff8e8fb919c1074e3d31076f83b0a1aac45
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Jan 18 16:50:25 2013 +0800

    Include byteorder.h for the definition of ntohl in romstage.c
    
    A fix to eliminate warnings when building romstage files with ChromeOS
    compilers
    
    Change-Id: Ia5d7bbdde3aa3439fd493f5795f2cc2bf4c4c187
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2781
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8c20399a42a6bb76f537042b4d7ba725ac78f10c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 17 11:13:46 2013 -0600

    haswell: wait 10ms after INIT IPI
    
    There should be a fixed 10ms wait after sending an INIT IPI. The
    previous implementation was just waiting up to 10ms for the IPI to
    complete the send. That is not correct. The 10ms is unconditional
    according to the documentation. No ill effects were observed with the
    previous behavior, but it's important to follow the documentation.
    
    Change-Id: Ib31d49ac74808f6eb512310e9f54a8f4abc3bfd7
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2780
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 305b1f0d30b68c310d4dfa7e1a5f432769a65b31
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Jan 15 08:27:05 2013 -0600

    haswell: Parallel AP bringup
    
    This patch parallelizes the AP startup for Haswell-based devices. It
    does not touch the generic secondary startup code. Instead it provides
    its own MP support matching up with the Haswell BWG. It seemed to be too
    much trouble to support the old startup way and this new way. Because of
    that parallel loading is the only thing supported.
    
    A couple of things to note:
    1. Micrcode needs to be loaded twice. Once before MTRR and caching is
       enabled. And a second time after SMM relocation.
    2. The sipi_vector is entirely self-contained. Once it is loaded and
       written back to RAM the APs do not access memory outside of the
       sipi_vector load location until a sync up in ramstage.
    3. SMM relocation is kicked off by an IPI to self w/ SMI set as the
       destination mode.
    
    The following are timings from cbmem with dev mode disabled and recovery mode
    enabled to boot directly into the kernel. This was done on the
    baskingridge CRB with a 4-core 8-thread CPU and 2 DIMMs 1GiB each. The
    kernel has console enabled on the serial port. Entry 70 is the device
    initialization, and that is where the APs are brought up. With these two
    examples it looks to shave off ~200 ms of boot time.
    
    Before:
       1:55,382
       2:57,606 (2,223)
       3:3,108,983 (3,051,377)
       4:3,110,084 (1,101)
       8:3,113,109 (3,024)
       9:3,156,694 (43,585)
      10:3,156,815 (120)
      30:3,157,110 (295)
      40:3,158,180 (1,069)
      50:3,160,157 (1,977)
      60:3,160,366 (208)
      70:4,221,044 (1,060,677)
      75:4,221,062 (18)
      80:4,227,185 (6,122)
      90:4,227,669 (484)
      99:4,265,596 (37,927)
    1000:4,267,822 (2,225)
    1001:4,268,507 (685)
    1002:4,268,780 (272)
    1003:4,398,676 (129,896)
    1004:4,398,979 (303)
    1100:7,477,601 (3,078,621)
    1101:7,480,210 (2,608)
    
    After:
       1:49,518
       2:51,778 (2,259)
       3:3,081,186 (3,029,407)
       4:3,082,252 (1,066)
       8:3,085,137 (2,884)
       9:3,130,339 (45,202)
      10:3,130,518 (178)
      30:3,130,544 (26)
      40:3,131,125 (580)
      50:3,133,023 (1,897)
      60:3,133,278 (255)
      70:4,009,259 (875,980)
      75:4,009,273 (13)
      80:4,015,947 (6,674)
      90:4,016,430 (482)
      99:4,056,265 (39,835)
    1000:4,058,492 (2,226)
    1001:4,059,176 (684)
    1002:4,059,450 (273)
    1003:4,189,333 (129,883)
    1004:4,189,770 (436)
    1100:7,262,358 (3,072,588)
    1101:7,263,926 (1,567)
    
    Booted the baskingridge board as noted above. Also analyzed serial
    messages with pcserial enabled.
    
    Change-Id: Ifedc7f787953647c228b11afdb725686e38c4098
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2779
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 98ffb426f40593f930388c006f8058c199defff4
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Jan 15 15:15:32 2013 -0600

    intel microcode: split up microcode loading stages
    
    This patch only applies to CONFIG_MICROCODE_IN_CBFS. The intel microcode
    update routine would always walk the CBFS for the microcode file. Then
    it would loop through the whole file looking for a match then load the
    microcode. This process was maintained for intel_update_microcode_from_cbfs(),
    however 2 new functions were exported:
    	1.  const void *intel_microcode_find(void)
    	2.  void intel_microcode_load_unlocked(const void *microcode_patch)
    
    The first locates a matching microcode while the second loads that
    mircocode. These new functions can then be used to cache the found
    microcode blob w/o having to re-walk the CBFS.
    
    Booted baskingridge board to Linux and noted that all microcode
    revisions match on all the CPUs.
    
    Change-Id: Ifde3f3e5c100911c4f984dd56d36664a8acdf7d5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2778
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3c734bb355b6cf15e61e3bc8755f622d4117e7c2
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Fri Mar 15 12:19:45 2013 -0600

    AMD Dinar: Remove Unused Oem.h Header File
    
    Having this header file in the mainboard directory breaks
    the dinar build on cygwin because the header file in the
    dinar mainboard is used instead of the correct header file
    src/vendorcode/amd/cimx/sb700/OEM.h.  The build probably works
    fine on Linux systems because, due to case-sensitivity, Oem.h
    will not match the #include "OEM.h" statement in
    src/southbridge/amd/cimx/sb700/Platform.h.
    
    The Oem.h file in the dinar mainboard is not used by any other
    source files, and the defines in the dinar mainboard are duplicated
    by defines in the correct OEM.h file.  Therefore, the file can be
    safely removed.
    
    Change-Id: I81b97eca8116d63644d335edc3bb51f90c7094d9
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2776
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit c2fe1e0a0999f65f7954ba88b69e63c3d2737291
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Mar 14 17:53:19 2013 -0700

    SMM: link against libgcc
    
    The non-relocatable SMM code was changed to link against libgcc a while back
    so that printk could use built-in division instead of a hand crafted div()
    function. However, the relocatable SMM code was not adapted by mistake.
    This patch links the relocatable SMM against libgcc, too, so we can enable it
    for Haswell.
    
    Change-Id: Ia64a78e2e62348d115ae4ded52d1a02c74c5cea4
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2727
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7492ec1ca62efee1f244d8306b03ed3d74ac2e53
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 8 22:18:04 2013 -0600

    haswell: add romstage_after_car() function
    
    There are changes coming to perform more complex tasks after cache-as-ram
    has been torn down but before ramstage is loaded. Therefore, add the
    romstage_after_car() function to call after cache-as-ram is torn down.
    Its responsibility is for loading the ramstage and any other complex
    tasks. For example, the saving of OS-controlled memory in the resume
    path has now been moved into C instead of assembly.
    
    Change-Id: Ie0c229cf83a9271c8995b31c534c8e5a696b164e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2757
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2ad1dbaf2a2dfe373ff89927202acc01e36c7cd4
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Feb 7 00:51:18 2013 -0600

    haswell: move call site of save_mrc_data()
    
    The save_mrc_data() was previously called conditionally
    in the raminit code. The save_mrc_data() function was called
    in the non-S3 wake paths. However, the common romstage_common()
    code was checking cbmem initialization things on s3 wake. Between
    the two callers cbmem_initialize() was being called twice in the
    non-s3 wake paths.  Moreover, saving of the mrc data was not allowed
    when CONFIG_EARLY_CBMEM_INIT wasn't enabled.
    
    Therefore, move the save_mrc_data() to romstage_common. It already has
    the knowledge of the wake path. Also remove the CONFIG_EARLY_CBMEM_INIT
    requirement from save_mrc_data() as well as the call to cbmem_initialize().
    
    Change-Id: I7f0e4d752c92d9d5eedb8fa56133ec190caf77da
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2756
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 38d9423dbe300514e1ba7224a962650980a96217
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Feb 7 00:03:33 2013 -0600

    haswell: romstage: pass stack pointer and MTRRs
    
    Instead of hard coding the policy for the stack and MTRR values after
    the cache-as-ram is torn down, allow for the C code to pass those
    policies back to the cache-as-ram assembly file. That way, ramstage
    relocation can use a different stack as well as different MTRR policies.
    
    Change-Id: Ied024d933f96a12ed0703c51c506586f4b50bd14
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2755
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a267161362f23b94f2e7677a8ea55f729578a049
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Feb 6 21:41:01 2013 -0600

    haswell: unify romstage logic
    
    This commit pulls in all the common logic for romstage into
    the Haswell cpu directory. The bits specific to the mainboard
    still reside under their respective directories. The calling
    sequence bounces from the cpu directory to mainboard then back
    to the cpu directory. The reasoning is that Haswell systems use
    cache-as-ram for backing memory in romstage. The stack is used to
    allocate structures. However, now changes can be made to the
    romstage for Haswell and apply to all boards.
    
    Change-Id: I2bf08013c46a99235ffe4bde88a935c3378eb341
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2754
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9b7f9b97686bd5594518828249a5e0e2e6f377e7
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Feb 7 00:09:59 2013 -0600

    haswell: remove unused sys_info structure
    
    This structure is not used nor the variable being instantiated on the
    stack. Remove them.
    
    Change-Id: If3abe2dd77104eff49665dd33570b07179bf34f5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2753
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3d0071bde363bbcd2ef3d68bac67400feced1778
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Jan 18 14:32:50 2013 -0600

    haswell: adjust CAR usage
    
    It was found that the Haswell reference code was smashing through the
    stack into the reference code's heap implementation. The reason for this
    is because our current CAR allocation is too small. Moreover there are
    quite a few things to coordinate between 2 code bases to get correct.
    This commit separates the CAR into 2 parts:
      1. MRC CAR usage.
      2. Coreboot CAR usage.
    Pointers from one region can be passed between the 2 modules, but one
    should not be able to affect the others as checking has been put into
    place in both modules.
    
    The CAR size has effectively been doubled from 0x20000 (128 KiB) to
    0x40000 (256KiB). Not all of that increase was needed, but enforcing
    a power of 2 size only utilizes 1 MTRR.
    
    Old CAR layout with a single contiguous stack with the region starting
    at CONFIG_DCACHE_RAM_BASE:
    
    +---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE
    |  MRC global variables                 |
    |  CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes |
    +---------------------------------------+
    |  ROM stage stack                      |
    |                                       |
    |                                       |
    +---------------------------------------+
    |  MRC Heap 30000 bytes                 |
    +---------------------------------------+
    |  ROM stage console                    |
    |  CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes |
    +---------------------------------------+
    |  ROM stage CAR_GLOBAL variables       |
    +---------------------------------------+ Offset 0
    
    There was some hard coded offsets in the reference code wrapper to start
    the heap past the console buffer. Even with this commit the console
    can smash into the following region depending on what size
    CONFIG_CONSOLE_CAR_BUFFER_SIZE is.
    
    As noted above This change splits the CAR region into 2 parts starting
    at CONFIG_DCACHE_RAM_BASE:
    
    +---------------------------------------+
    |  MRC Region                           |
    |  CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes |
    +---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE
    |  ROM stage stack                      |
    |                                       |
    |                                       |
    +---------------------------------------+
    |  ROM stage console                    |
    |  CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes |
    +---------------------------------------+
    |  ROM stage CAR_GLOBAL variables       |
    +---------------------------------------+ Offset 0
    
    Another variable was add, CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE,
    which represents the expected stack usage for the romstage. A marker
    is checked at the base of the stack to determine if either the stack
    was smashed or the console encroached on the stack.
    
    Change-Id: Id76f2fe4a5cf1c776c8f0019f406593f68e443a7
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2752
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9be4c470bc4b9303b7b449249e1e78aeacf2773f
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Sat Jan 12 00:41:44 2013 -0600

    rmodule: add rmodules class and new type
    
    Add an rmodules class so that there are default rules for compiling
    files that will be linked by the rmodule linker. Also, add a new type
    for SIPI vectors.
    
    Change-Id: Ided9e15577b34aff34dc23e5e16791c607caf399
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2751
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7542fc7dd267da8502f23ce89644dba8e9e703c5
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Mar 14 14:59:10 2013 -0700

    wtm2: Disable USB port 7 (SD card) due to hang
    
    This is causing a hang in depthcharge.  For now just disable
    this port.
    
    Change-Id: I87a6db2d8361588e82eee640c74cea690115bed5
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2764
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f06111aaf4fdb9974e79e130b7ac95cdffcaaa7c
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Mar 12 15:50:08 2013 -0700

    libpayload: Fix the config file dependency in the Makefile template
    
    The template had a dependency on config.h which was correct for coreboot,
    where this build system originally came from, but not for libpayload which
    uses the differently named libpayload-config.h, presumably to avoid colliding
    with a config.h used by the actual payload. Because libpayload-config.h is now
    effectively a dependency of everything, it doesn't have to be added piecemeal
    in Makefile.inc.
    
    Change-Id: I01f20d363cb1393fa1cdcf0dc916670db90294e9
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2763
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a2d786f0e6a0db1c88d955ea80b040bebdea4396
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Mar 12 15:44:56 2013 -0700

    libpayload: Make keycode constants available outside of curses.h.
    
    And include the new, split out version in drivers/keyboard.c and
    drivers/usb/usbhid.c. Those files were including curses.h just for those
    definitions, but the include path was only fixed up to to point to the
    libpayload versions of those files if one of the variants of curses was
    compiled in. If neither was, gcc would fall back to the system version of that
    header which is wrong.
    
    Change-Id: I8c2ee0baf5f0702bd8c713c8dd4613a4bb269ce5
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2762
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 02fdf718a4b2a7053f19748a0ac0011aa576eb69
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Feb 5 11:09:49 2013 -0600

    rmodule: include heap in bss section
    
    By including the heap in the bss output section the size is accounted
    for in a elf PT_LOAD segment. Without this change the heap wasn't being
    put into a PT_LOAD segment. The result is a nop w.r.t. functionality,
    but readelf and company will have proper MemSiz fields.
    
    Change-Id: Ibfe9bb87603dcd4c5ff1c57c6af910bbba96b02b
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2750
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3bf0ce79b91a432344c42287b22a7704561ab68e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Feb 6 12:47:26 2013 -0600

    rmodule: add 16 bytes of padding
    
    There is a plan to utlize rmodules for loading ramstage as a
    relocatable module. However, the rmodule header may change.
    In order to provide some wiggle room for changing the contents
    of the rmodule header add some padding. This won't stop the need
    for coordinating properly between the romstage loader that may be
    in readonly flash and rmodule header fields.  But it will provide
    for a way to make certain assumptions about alignment of the
    rmodule's program when the rmodule is compressed in the flash.
    
    Change-Id: I9ac5cf495c0bce494e7eaa3bd2f2bd39889b4c52
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2749
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8e345d4ca2a13ebdf9edf1071d7c4f03d084d143
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Jan 15 15:34:08 2013 -0600

    haswell: lapic timer support
    
    Haswell's BCLK is fised at 100MHz like Sandy/Ivy. Add Haswell's model
    to the switch statement.
    
    Change-Id: Ib9e2afc04eba940bfcee92a6ee5402759b21cc45
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2747
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 18af4d23f6b17827dda50d17d8dc9da5b2656eef
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Dec 19 13:17:06 2012 -0800

    lynxpoint: Move a bit of generic RCBA into early_pch
    
    Rather than have to repeat this bit in every mainboard.
    
    Also, remove the reset of the RTC power status from here.
    We had done this in TOT for current platforms but did not
    carry it back to emeraldlake2 where this branched from.
    
    If we clear the status here then we don't get an event
    logged later which can be important for the devices that
    do not have a CMOS battery.
    
    Change-Id: Ia7131e9d9e7cf86228a285df652a96bcabf05260
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2683
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ad93552b86579afd29e99da1b2fcacb0d872cd1a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Dec 24 14:28:37 2012 -0600

    lib: add rmodule support
    
    A rmodule is short for relocation module. Relocaiton modules are
    standalone programs. These programs are linked at address 0 as a shared
    object with a special linker script that maintains the relocation
    entries for the object. These modules can then be embedded as a raw
    binary (objcopy -O binary) to be loaded at any location desired.
    
    Initially, the only arch support is for x86. All comments below apply to
    x86 specific properties.
    
    The intial user of this support would be for SMM handlers since those
    handlers sometimes need to be located at a dynamic address (e.g. TSEG
    region).
    
    The relocation entries are currently Elf32_Rel. They are 8 bytes large,
    and the entries are not necessarily in sorted order. An future
    optimization would be to have a tool convert the unsorted relocations
    into just sorted offsets. This would reduce the size of the blob
    produced after being processed. Essentialy, 8 bytes per relocation meta
    entry would reduce to 4 bytes.
    
    Change-Id: I2236dcb66e9d2b494ce2d1ae40777c62429057ef
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2692
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 21efd8c0378a8a42ee2fd71957be318416b6f5af
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 17 09:39:39 2013 -0600

    haswell: fix ACPI MCFG table
    
    The acpi_fill_mcfg() was still using ivy/sandy PCI device ids which Hawell
    obviously doesn't have. This resulted in an empty MCFG table. Instead of
    relying on PCI device ids use dev/fn 0/0 since that is where the host
    bridge always resides. Additionally remove the defines for the IB and SB
    pci device ids. Replace them with mobile and ult Haswel device ids and
    use those in the pci driver tables for the northbridge code.
    
    Booted to Linux and noted that MCFG was properly parsed.
    
    Change-Id: Ieaab2dfef0e9daf3edbd8a27efe0825d2beb9443
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2748
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7af20698f69bbf10c4f18aa4fcc35ae7cf8cb866
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Jan 14 14:54:41 2013 -0600

    haswell: enable caching before SMM initialization
    
    The SMM handler resides in the TSEG region which is far above
    CONFIG_RAM_TOP (which is the highest cacheable address) before
    MTRRs are setup. This means that calling initialize_cpus() before
    performing MTRR setup on the BSP means the SMM handler is copied
    using uncacheable accesses.
    
    Improve the SMM handler setup path by enabling performing MTRR setup on
    for the BSP before the call to initialize_cpus(). In order to do this
    the haswell_init() function was split into 2 paths: BSP & AP paths.
    There is a cpu_common_init() that both call to perform similar
    functionality. The BSP path in haswell_init() then starts the APs using
    intel_cores_init(). The AP path in haswell_init() loads microcode and
    sets up MTRRs.
    
    This split will be leveraged for future support of bringing up APs in
    parallel as well as adhering to the Haswell MP initialization
    requirements.
    
    Change-Id: Id8e17af149e68d708f3d4765e38b1c61f7ebb470
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2746
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 24614af9b85bc615b0d9af3f37fa393de039c9f8
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Sat Jan 12 01:07:28 2013 -0600

    haswell: Clear correct number of MCA banks
    
    The configure_mca() function was hard coding the number of
    banks the cpu supported. Query this dynamically so that it
    no longer clears only 7 banks.
    
    Change-Id: I33fce8fadc0facd1016b3295faaf3ae90e490a71
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2745
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a416bfecedb7d55cf3c631d230e3500b314fc880
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Sat Jan 12 00:45:10 2013 -0600

    haswell: move definition of CORE_THREAD_COUNT_MSR
    
    This just moves the definiton of CORE_THREAD_COUNT_MSR so
    that future code can utilize it.
    
    Change-Id: I15a381090f21ff758288f55dc964b6694feb6064
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2744
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 29ffa54969414b833de5c61b507b061f920d650b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Dec 21 21:21:48 2012 -0600

    haswell: Use SMM Modules
    
    This commit adds support for using the SMM modules for haswell-based
    boards. The SMI handling was also refactored to put the relocation
    handler and permanent SMM handler loading in the cpu directory. All
    tseg adjustment support is dropped by relying on the SMM module support
    to perform the necessary relocations.
    
    Change-Id: I8dd23610772fc4408567d9f4adf339596eac7b1f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2728
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b7ecf6d83047e70ed5846ac35833a04983318b9c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Mar 13 17:13:32 2013 -0700

    Add support for "Stout" Chromebook
    
    We're happy to announce coreboot support for the "Stout"
    Chromebook, a.k.a Lenovo X131e Chromebook.
    
    Change-Id: I9b995f8d0dd48e41c788b7c3d35b4fac5840e425
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2636
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit afad056c2298824caeb2c58d1541576c73bfef5d
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jan 14 08:50:03 2013 -0800

    Add Intel Whitetip Mountain 2 mainboard
    
    This is mostly a copy of Whitetip Mountain 1 with specific GPIO
    map for this Customer Reference Board (CRB).
    
    This mainboard currently has basic funcionality and is able to
    boot a Linux Kernel but many of the new Haswell ULT specific
    devices are not yet enabled.
    
    Change-Id: I999452d86f00a2c245fa39b1b76080f6a3b1e352
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2725
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ab9b71d54c0638f051e93b0109e04f7da39ee6ab
Author: Андрей Павлов <7134956@gmail.com>
Date:   Sun Mar 17 19:11:05 2013 +0300

    superiotool: Add support for the IT8728F Super I/O
    
    $ superiotool -d
    superiotool r4.0-3712-gd549279
    Found ITE IT8728F (id=0x8728, rev=0x1) at 0x2e
    Register dump:
    idx 02 07 20 21 22 23 24 2b  2e 2f
    val 00 0a 87 28 01 00 00 40  00 00
    def NA NA 87 28 01 00 00 MM  00 00
    LDN 0x00 (Floppy)
    idx 30 60 61 70 74 f0 f1
    val 00 03 f0 06 02 00 00
    def 00 03 f0 06 02 00 00
    LDN 0x01 (COM1)
    idx 30 60 61 70 f0 f1
    val 01 03 f8 04 00 50
    def 00 03 f8 04 00 50
    LDN 0x02 (COM2)
    idx 30 60 61 70 f0 f1
    val 00 02 f8 03 00 50
    def 00 02 f8 03 00 50
    LDN 0x03 (Parallel port)
    idx 30 60 61 62 63 70 74 f0
    val 01 03 78 00 00 07 04 08
    def 00 03 78 07 78 07 03 03
    LDN 0x04 (Environment controller)
    idx 30 60 61 62 63 70 f0 f1  f2 f3 f4 f5 f6 f9 fa fb
    val 01 0a 30 0a 20 09 00 80  00 00 20 00 f0 48 00 00
    def 00 02 90 02 30 09 00 00  00 00 00 MM MM MM MM MM
    LDN 0x05 (Keyboard)
    idx 30 60 61 62 63 70 71 f0
    val 01 00 60 00 64 01 02 08
    def 01 00 60 00 64 01 02 48
    LDN 0x06 (Mouse)
    idx 30 70 71 f0
    val 01 0c 02 00
    def 00 0c 02 00
    LDN 0x07 (GPIO)
    idx 25 26 27 28 29 2a 2c 2d  60 61 62 63 64 65 70 71  72 73 74 b0 b1 b2 b3 b4  b8 b9 ba bb bc bd c0 c1  c2 c3 c4 c8 c9 ca cb cc  cd ce cf e0 e1 e2 e3 e4  e9 f0 f1 f2 f3 f4 f5 f6  f7 f8 f9 fa fb
    val 00 f3 10 00 00 00 80 00  00 00 0a 00 00 00 00 00  20 00 00 00 00 00 00 00  20 00 00 00 00 00 01 00  00 40 00 01 00 00 00 00  00 00 00 00 00 00 00 00  21 10 42 00 00 00 00 1c  00 00 00 00 00
    def 00 f3 00 00 00 00 03 00  00 00 00 00 00 00 00 00  20 38 00 00 00 00 00 00  20 00 00 00 00 00 01 00  00 40 00 01 00 00 40 00  00 00 00 00 00 00 00 00  MM 00 00 00 00 00 00 00  00 00 00 00 00
    LDN 0x0a (Consumer IR)
    idx 30 60 61 70 f0
    val 00 03 10 0b 06
    def 00 03 10 0b 06
    
    Change-Id: Ifb45d28005d78b2a99d8552b59154d11bdf44f6f
    Signed-off-by: Андрей Павлов <7134956@gmail.com>
    Reviewed-on: http://review.coreboot.org/2775
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 15ba2bcf2d78181de1047f46b6ae28e44fbd3f86
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Nov 14 12:25:15 2012 -0800

    Intel HD Audio: clean up initialization code
    
    - Some initialization steps were done twice
    - One step was missing for Panther Point HDA
    - Added a 1ms delay after reset
    - Increased timeout to 1ms for all codec operations
    
    Change-Id: Ib751f1a16ccd88ea2fbbb2a10737f76277574026
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2518
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6dcceddff53ad309b91b61661ae7deab37f272ec
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Dec 3 16:17:40 2012 -0600

    x86 intel: Add Firmware Interface Table support
    
    Haswell CPUs require a FIT table in the firmware. This commit
    adds rudimentary support for a FIT table. The number of entries
    in the table is based on a configuration option. The code only
    generates a type 0 entry. A follow-on tool will need to be developed
    to populate the FIT entries as well as checksumming the table.
    
    Verified image has a FIT pointer and table when option is selected.
    
    Change-Id: I3a314016a09a1cc26bf1fb5d17aa50853d2ef4f8
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2642
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 239c2e843f976d5915964c8cb1923305c574f8b5
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Dec 19 11:31:17 2012 -0600

    haswell platforms: restructure romstage main
    
    There was a mix of setup code sprinkled across the various components:
    southbridge code in the northbridge, etc. This commit reorganizes the
    code so that northbridge code doesn't initialize southbridge components.
    Additionally, the calling dram initialization no longer calls out to ME
    code. The main() function in the mainboard calls the necessary ME
    functions before and after dram initialization.
    
    The biggest change is the addition of an early_pch_init() function
    which initializes the BARs, GPIOs, and RCBA configuration. It is also
    responsible for reporting back to the caller if the board is being
    woken up from S3. The one sequence difference is that the RCBA config
    is performed before claling the reference code.
    
    Lastly the rcba configuration was changed to be table driven so that
    different board/configurations can use the same code. It should be
    possible to have board/configuration specific gpio and rcba
    configuration while reusing the romstage code.
    
    Change-Id: I830e41b426261dd686a2701ce054fc39f296dffa
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2681
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 218a6864ff9528ecdb381d91991c9045bbb6843f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Jan 11 09:54:55 2013 -0800

    Add Intel Whitetip Mountain 1 mainboard
    
    Lots of things are still placeholder and need work.
    
    Due to the useful GPIOs being run to either the EC or the SIO1007
    I have hard coded developer mode on and recovery mode off.
    
    Change-Id: I4c308bd90db03ac5bffdfde566e5adbbaabac632
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2724
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c9fc0297ad6a63d9edf981a46f29f9372d11634c
Author: Shawn Nematbakhsh <shawnn@google.com>
Date:   Thu Mar 14 10:44:13 2013 -0700

    bd82x6x: Add config option to force SATA link to different speeds.
    
    Certain SATA devices claim to support SATA 6 Gbps, but in fact have
    bugs. For these devices, add a config option to force the SATA link
    speed to something other than default.
    
    Change-Id: I2dc1793cd58771298a392345162d39d20eb0afbb
    Signed-off-by: Shawn Nematbakhsh <shawnn@google.com>
    Reviewed-on: http://review.coreboot.org/2765
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 645b376ec82c5343bd197f04fa9e7bb53ee23d69
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Feb 12 14:00:47 2013 -0800

    Pantherpoint: Add XHCI device init
    
    This enables power management and clock gating on XHCI.
    
    Change-Id: I124ea6c5aca034b7ec4b5286d971c2adfce25c88
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2761
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8aa210bbf0343b1da1ab4e164c22da13c985a796
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Feb 8 16:14:07 2013 -0600

    bd82x6x: don't use absolute symbols
    
    objcopy -B provides symbols of the form _binary_<name>_(start|end|size).
    However, the _size variant is an absoult symbol.  If one wants to
    relocate the smi loading the _size symbol will be relocated which is
    wrong since it is suppose to be a fixed size. There is no way to
    distinguish symbols that shouldn't be relocated vs ones that can.
    Instead use the _start and _end variants to determine the size.
    
    Change-Id: I55192992cf36f62a9d8dd896e5fb3043a3eacbd3
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2760
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 058d70f163e1a46e16d8577de4e612af04b9aeca
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Mon Feb 11 14:39:28 2013 -0700

    Add bd82x6x XHCI(USB3) S3/S4 workaround
    
    The bd82x6x requires some additional setting on S3/S4 entry.
    
    Change-Id: I24489ab94dd7cd5a4a64044f25153f5b01a45b77
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2759
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 783f226208f0d25cc25ff3a9d56e108a09fb4cff
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Mon Feb 11 14:36:35 2013 -0700

    Add bd82x6x PCH functions to SMM
    
    Add the PCH function to SMM for follow-on SMM patches that
    require these functions.
    
    Change-Id: I7f3a512c5e98446e835b59934d63a99e8af15280
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2758
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e6c3b1d30d3fa88af6da6fcc115aa6cba3c55d1c
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Dec 21 21:22:07 2012 -0600

    haswell: include TSEG region in cacheable memory
    
    The SMRR takes precedence over the MTRR entries. Therefore, if the TSEG
    region is setup as cacheable through the MTTRs, accesses to the TSEG
    region before SMM relocation are cached. This allows for the setup of
    SMM relocation to be faster by caching accesses to the future TSEG
    (SMRAM) memory.
    
    MC MAP: TOM: 0x140000000
    MC MAP: TOUUD: 0x18f600000
    MC MAP: MESEG_BASE: 0x13f000000
    MC MAP: MESEG_LIMIT: 0x7fff0fffff
    MC MAP: REMAP_BASE: 0x13f000000
    MC MAP: REMAP_LIMIT: 0x18f5fffff
    MC MAP: TOLUD: 0xafa00000
    MC MAP: BGSM: 0xad800000
    MC MAP: BDSM: 0xada00000
    MC MAP: TESGMB: 0xad000000
    MC MAP: GGC: 0x209
    
    TSEG->BGSM:
       PCI: 00:00.0 resource base ad000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 4
    BGSM->TOLUD:
       PCI: 00:00.0 resource base ad800000 size 2200000 align 0 gran 0 limit 0 flags f0000200 index 5
    
    Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
    Setting variable MTRR 1, base: 2048MB, range:  512MB, type WB
    Setting variable MTRR 2, base: 2560MB, range:  256MB, type WB
    Adding hole at 2776MB-2816MB
    Setting variable MTRR 3, base: 2776MB, range:    8MB, type UC
    Setting variable MTRR 4, base: 2784MB, range:   32MB, type UC
    Zero-sized MTRR range @0KB
     Allocate an msr - basek = 00400000, sizek = 0023d800,
    Setting variable MTRR 5, base: 4096MB, range: 2048MB, type WB
    Setting variable MTRR 6, base: 6144MB, range:  256MB, type WB
    Adding hole at 6390MB-6400MB
    Setting variable MTRR 7, base: 6390MB, range:    2MB, type UC
    
    MTRR translation from MB to addresses:
    
    MTRR 0: 0x00000000 -> 0x80000000 WB
    MTRR 1: 0x80000000 -> 0xa0000000 WB
    MTRR 2: 0xa0000000 -> 0xb0000000 WB
    MTRR 3: 0xad800000 -> 0xae000000 UC
    MTRR 4: 0xae000000 -> 0xb0000000 UC
    
    I'm not a fan of the marking physical address space with MTRRs as being
    UC which is PCI space, but it is technically correct.
    
    Lastly, drop a comment describing AP startup flow through coreboot.
    
    Change-Id: Ic63c0377b9c20102fcd3f190052fb32bc5f89182
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2690
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 86a1110837ca61b63a9c012600302ed722997e3f
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Mar 15 14:11:37 2013 +0100

    i945: Replace some two magic values by defined names
    
    Devoutly to be wish'd. To die,—to sleep;—
    To sleep! perchance to dream:—ay, there's the rub;
    For in that sleep of death what dreams may come,
    
    (Since who could argue with William Shakespeare?)
    
    Change-Id: I4e4c617dcd3ede81a0abbe16f9916562d24fa8ce
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/2733
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 594ea4ac5fef354dda573b3b3670fe946ce65cd9
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Mar 15 11:11:12 2013 -0600

    ASROCK Fam14 DSDT: Add secondary bus range to PCI0
    
    Adding the 'WordBusNumber' macro to the PCI0
    CRES ResourceTemplate in the Persimmon DSDT.
    This sets up the bus number for the PCI0 device
    and the secondary bus number in the CRS method.
    This change came in response to a 'dmesg' error
    which states:
    '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
    
    By adding the 'WordBusNumber' macro, ACPI can set
    up a valid range for the PCIe downstream busses,
    thereby relieving the Linux kernel from "guessing"
    the valid range based off _BBN or assuming [0-0xFF].
    The Linux kernel code that checks this bus range is
    in `drivers/acpi/pci_root.c`.  PCI busses can have
    up to 256 secondary busses connected to them via
    a PCI-PCI bridge.  However, these busses do not
    have to be sequentially numbered, so leaving out a
    section of the range (eg. allowing [0-0x7F]) will
    unnecessarily restrict the downstream busses.
    
    This is the same change as made to Persimmon with
    change-id I44f22:
    http://review.coreboot.org/#/c/2592/
    
    Change-Id: I5184df8deb7b5d2e15404d689c16c00493eb01aa
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2736
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8c72670ba5c4283b2a1a2513f47f40b949094648
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Mar 15 13:31:20 2013 -0600

    AMD Fam14 DSDT: Remove INI method from AZHD device
    
    I am removing the _INI method from the AZHD device because
    it does not seem to do anything and causes errors in the
    FWTS[1] (Firmware Test Suite) test 'method'. The INI
    method performs device specific initialization and is
    run when OSPM loads a description table.  It must only
    access OperationRegions that have been indicated as
    available by the _REG (Region) method.  We do not have a
    _REG method and during my testing, I added a REG method
    but it did not seem to make a difference in the PCI
    register space.  The bit fields defined as NSDI (Disable
    No Snoop), NSDO (Disable No Snoop Override), and NSEN
    (Enable No Snoop Request) do not ever get written from
    their default values.  And writing to these bit fields
    does not seem to be necessary because I did not notice
    any change in audio functionality.
    
    In an effort to clean up as many FWTS errors as possible,
    I propose removing this method altogether.  I have seen no
    change in operation (audio works with and without this
    method) and there does not seem to be any change in lspci
    or dmesg.
    
    FWTS information can be found here:
    [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts
    
    This is the same chagne as made to Persimmon in
    Change-ID If8d86f:
    http://review.coreboot.org/#/c/2726/
    
    Change-Id: Id560ea85a38f73aaba2c35447bbce46bd9c0d0dd
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2741
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 60d84ca22b57ae5705c0659aa07a59a3407c094e
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Mar 15 13:36:25 2013 -0600

    ASROCK Fam14 DSDT: Remove INI method from AZHD device
    
    I am removing the _INI method from the AZHD device because
    it does not seem to do anything and causes errors in the
    FWTS[1] (Firmware Test Suite) test 'method'. The INI
    method performs device specific initialization and is
    run when OSPM loads a description table.  It must only
    access OperationRegions that have been indicated as
    available by the _REG (Region) method.  We do not have a
    _REG method and during my testing, I added a REG method
    but it did not seem to make a difference in the PCI
    register space.  The bit fields defined as NSDI (Disable
    No Snoop), NSDO (Disable No Snoop Override), and NSEN
    (Enable No Snoop Request) do not ever get written from
    their default values.  And writing to these bit fields
    does not seem to be necessary because I did not notice
    any change in audio functionality.
    
    In an effort to clean up as many FWTS errors as possible,
    I propose removing this method altogether.  I have seen no
    change in operation (audio works with and without this
    method) and there does not seem to be any change in lspci
    or dmesg.
    
    FWTS information can be found here:
    [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts
    
    This is the same change as made to Persimmon in
    Change-ID If8d86f:
    http://review.coreboot.org/#/c/2726/
    
    Change-Id: Iae70c3d0af1cdaca31b206ad6daba4d38ee6b780
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2742
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 109c08e05ac482c72c541ae1a3e408a686c9fb03
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Mar 15 13:40:13 2013 -0600

    Lippert Fam14 DSDT: Remove INI method from AZHD device
    
    I am removing the _INI method from the AZHD device because
    it does not seem to do anything and causes errors in the
    FWTS[1] (Firmware Test Suite) test 'method'. The INI
    method performs device specific initialization and is
    run when OSPM loads a description table.  It must only
    access OperationRegions that have been indicated as
    available by the _REG (Region) method.  We do not have a
    _REG method and during my testing, I added a REG method
    but it did not seem to make a difference in the PCI
    register space.  The bit fields defined as NSDI (Disable
    No Snoop), NSDO (Disable No Snoop Override), and NSEN
    (Enable No Snoop Request) do not ever get written from
    their default values.  And writing to these bit fields
    does not seem to be necessary because I did not notice
    any change in audio functionality.
    
    In an effort to clean up as many FWTS errors as possible,
    I propose removing this method altogether.  I have seen no
    change in operation (audio works with and without this
    method) and there does not seem to be any change in lspci
    or dmesg.
    
    FWTS information can be found here:
    [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts
    
    This is the same change as made to Persimmon in
    Change-ID If8d86f:
    http://review.coreboot.org/#/c/2726/
    
    Change-Id: Iff594d4a3493531561eb25d1cceeb97bcefde424
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2743
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 42ad2006572ea784548a79aabfaa3b00295d1215
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Mar 15 13:05:59 2013 -0600

    Lippert Fam14 DSDT: Add secondary bus range to PCI0
    
    Adding the 'WordBusNumber' macro to the PCI0
    CRES ResourceTemplate in the Persimmon DSDT.
    This sets up the bus number for the PCI0 device
    and the secondary bus number in the CRS method.
    This change came in response to a 'dmesg' error
    which states:
    '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
    
    By adding the 'WordBusNumber' macro, ACPI can set
    up a valid range for the PCIe downstream busses,
    thereby relieving the Linux kernel from "guessing"
    the valid range based off _BBN or assuming [0-0xFF].
    The Linux kernel code that checks this bus range is
    in `drivers/acpi/pci_root.c`.  PCI busses can have
    up to 256 secondary busses connected to them via
    a PCI-PCI bridge.  However, these busses do not
    have to be sequentially numbered, so leaving out a
    section of the range (eg. allowing [0-0x7F]) will
    unnecessarily restrict the downstream busses.
    
    This is the same change as made to Persimmon with
    change-id I44f22:
    http://review.coreboot.org/#/c/2592/
    
    Change-Id: Ie36b60973c6a5f9076bb55c8f451532711a2f8a8
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2737
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 00a0e76bc5ffaba01c98f1c1384b0499516fdaef
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Mar 15 13:17:52 2013 -0600

    AMD Fam14 DSDT: Add OSC method
    
    The _OSC method is used to tell the OS what capabilities
    it can take control over from the firmware.  This method
    is described in chapter 6.2.9 of the ACPI spec v3.0.
    The method takes 4 inputs (UUID, Rev ID, Input Count,
    and Capabilities Buffer) and returns a Capabilites
    Buffer the same size as the input Buffer.  This Buffer
    is generally 3 Dwords long consisting of an Errors
    Dword, a Supported Capabilities Dword, and a Control
    Dword.  The OS will request control of certain
    capabilities and the firmware must grant or deny control
    of those features.  We do not want to have control over
    anything so let the OS control as much as it can.
    
    The _OSC method is required for PCIe devices and dmesg
    checks for its existence and issues an error if it is
    not found.
    
    This is the same change made to Persimmon with Change-ID
    I149428:
    http://review.coreboot.org/#/c/2684/
    
    Change-Id: If6dd1a558d9c319d9a41ce63588550c8e81e595f
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2738
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9c3d112bb686f1c044aeb501ef810e2fb8c9310e
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Mar 15 13:22:32 2013 -0600

    ASROCK Fam14 DSDT: Add OSC method
    
    The _OSC method is used to tell the OS what capabilities
    it can take control over from the firmware.  This method
    is described in chapter 6.2.9 of the ACPI spec v3.0.
    The method takes 4 inputs (UUID, Rev ID, Input Count,
    and Capabilities Buffer) and returns a Capabilites
    Buffer the same size as the input Buffer.  This Buffer
    is generally 3 Dwords long consisting of an Errors
    Dword, a Supported Capabilities Dword, and a Control
    Dword.  The OS will request control of certain
    capabilities and the firmware must grant or deny control
    of those features.  We do not want to have control over
    anything so let the OS control as much as it can.
    
    The _OSC method is required for PCIe devices and dmesg
    checks for its existence and issues an error if it is
    not found.
    
    This is the same change made to Persimmon with Change-ID
    I149428:
    http://review.coreboot.org/#/c/2684/
    
    Change-Id: I2701d915338294bdade2ad334b22a51db980892e
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2739
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 061c66406ffebb298ba06ac7ecf7e14c5d55cc24
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Mar 15 13:24:53 2013 -0600

    Lippert Fam14 DSDT: Add OSC method
    
    The _OSC method is used to tell the OS what capabilities
    it can take control over from the firmware.  This method
    is described in chapter 6.2.9 of the ACPI spec v3.0.
    The method takes 4 inputs (UUID, Rev ID, Input Count,
    and Capabilities Buffer) and returns a Capabilites
    Buffer the same size as the input Buffer.  This Buffer
    is generally 3 Dwords long consisting of an Errors
    Dword, a Supported Capabilities Dword, and a Control
    Dword.  The OS will request control of certain
    capabilities and the firmware must grant or deny control
    of those features.  We do not want to have control over
    anything so let the OS control as much as it can.
    
    The _OSC method is required for PCIe devices and dmesg
    checks for its existence and issues an error if it is
    not found.
    
    This is the same change made to Persimmon with Change-ID
    I149428:
    http://review.coreboot.org/#/c/2684/
    
    Change-Id: Iaf7b8153cec4d730efbceae3e6957d2904b8fae4
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2740
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 71346c064b4f2d27e5a5a0499d1a4eed2f40ffbc
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jan 10 13:20:40 2013 -0800

    lynxpoint: Add support for disabling ULT devices
    
    These enables are hidden behind IOBP for some reason.
    
    Boot to linux with SDIO disabled and see that
    the SDIO driver does not load and crash the system.
    
    Change-Id: Icfbfa117e9e57a51d32db7f6366a9d0d790adcf0
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2695
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit aa3f4287d40f7f3c7b1fca1af5cfa426ff4fa27f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 15 20:17:26 2013 -0700

    stddef.h: Add standard defines for KiB, MiB, GiB, and TiB
    
    Paul points out that some people like 1024*1024, others like
    1048576, but in any case these are all open to typos.
    
    Define KiB, MiB, GiB, and TiB as in the standard so people can use them.
    
    Change-Id: Ic1b57e70d3e9b9e1c0242299741f71db91e7cd3f
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2769
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 5c66f08a3a901eb3e1fe6cfd7f22b90cecbf3cf7
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Jan 8 10:10:33 2013 -0600

    haswell: don't add a 0-sized memory range resource
    
    It's possible that TOUUD can be 4GiB in a small physical memory
    configuration. Therefore, don't add a 0-size memory range resouce
    in that case.
    
    Change-Id: I016616a9d9d615417038e9c847c354db7d872819
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2691
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c2c97231e3f36e9d3f1ee8de2394220ec7beadeb
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 15 15:57:13 2013 -0700

    Show the device tree.
    
    This is a bit of a hack but it's very handy. It compiles in your static.c
    and then shows what coreboot would see when it is run. It uses your static.c
    and functions pulled from src/device/device_util.c.
    I've already used it to debug problems with the snow device tree.
    
    I'm waiting someone to tell me this is already written :-)
    
    Change-Id: Ia8c8a5d08d8757bec49eaf70473efa701bc56581
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2767
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 20ff75f1fc302b83f4184526fbb082718b61501e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 15 14:40:40 2013 -0700

    google/snow: rename a file so that it is clear what board it is for
    
    One might wonder what a board named 'build' does. Rename the file to
    build-snow. The fact that it is in a directory with google in the name
    should be enough to identify the vendor.
    
    Change-Id: I0b473cdce67d56fc6b92032b55180523eb337d66
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2766
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 039223a4741d513c7ea3c9cc1bb84ad612773768
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Mar 16 00:05:09 2013 +0100

    gitmodules: Ignore 3rdparty in "diff family"
    
    This should help avoid wrong 3rdparty commit ids
    creeping in.
    
    Change-Id: I2134ad1d3ad0237ef3f12baf4d4aafb02009e7bc
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2768
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 69efaa0388c2989cd224821adb07715d64623953
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Feb 26 10:07:40 2013 -0800

    Google Link: Add remaining code to support native graphics
    
    The Link native graphics commit 49428d84 [1]
    
        Add support for Google's Chromebook Pixel
    
    was missing some of the higher level bits, and hence could not be
    used.  This is not new code -- it has been working since last
    August -- so the effort now is to get it into the tree and structure
    it in a way compatible with upstream coreboot.
    
    1. Add options to src/device/Kconfig to enable native graphics.
    2. Export the MTRR function for setting variable MTRRs.
    3. Clean up some of the comments and white space.
    
    While I realize that the product name is Pixel, the mainboard in the
    coreboot tree is called Link, and that name is what we will use
    in our commits.
    
    [1] http://review.coreboot.org/2482
    
    Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2531
    Tested-by: build bot (Jenkins)

commit 26855fc70b05cf0294cbe3d5f2195bfb95806780
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Mar 15 10:53:40 2013 -0600

    AMD Fam14 DSDT: Add secondary bus range to PCI0
    
    Adding the 'WordBusNumber' macro to the PCI0
    CRES ResourceTemplate in the Persimmon DSDT.
    This sets up the bus number for the PCI0 device
    and the secondary bus number in the CRS method.
    This change came in response to a 'dmesg' error
    which states:
    '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
    
    By adding the 'WordBusNumber' macro, ACPI can set
    up a valid range for the PCIe downstream busses,
    thereby relieving the Linux kernel from "guessing"
    the valid range based off _BBN or assuming [0-0xFF].
    The Linux kernel code that checks this bus range is
    in `drivers/acpi/pci_root.c`.  PCI busses can have
    up to 256 secondary busses connected to them via
    a PCI-PCI bridge.  However, these busses do not
    have to be sequentially numbered, so leaving out a
    section of the range (eg. allowing [0-0x7F]) will
    unnecessarily restrict the downstream busses.
    
    This is the same change as made to Persimmon with
    change-id I44f22:
    http://review.coreboot.org/#/c/2592/
    
    Change-Id: I9017a7619b3b17e0e95ad0fe46d0652499289b00
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2735
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c4dfae835f956df8ebc2d4da62fb05ec3772cda1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 15 10:04:20 2013 -0700

    Update 3rdparty mark to latest repository
    
    For google/stout binaries
    
    Apparently the actual marker got lost in the rebase / change of the
    commit message.
    
    Change-Id: I4f18b9ddba326988b58f2595c0025a113feb0d68
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2734
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9ae1eb6961b483c9905423fb113100a8038b4507
Author: Wolfgang Kamp <wmkamp@datakamp.de>
Date:   Mon Mar 11 16:35:42 2013 +0100

    Super I/O W83627DHG: Enable UART B by redirecting pins
    
    Pins 78-85 are set to GPIO after power on or reset. To enable
    UART B the pins must be redirected to it.
    
    Look at W83627DHG databook version 1.4 page 185 Chip
    (global) Control Register CR2C.
    
    Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845
    Signed-off-by: Wolfgang Kamp <wmkamp@datakamp.de>
    Reviewed-on: http://review.coreboot.org/2626
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 8d629c14eb776ce6e243218bb554a335dc0f3672
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Thu Mar 14 16:07:09 2013 -0600

    Persimmon DSDT: Remove INI method from AZHD device
    
    I am removing the _INI method from the AZHD device because
    it does not seem to do anything and causes errors in the
    FWTS[1] (Firmware Test Suite) test 'method'. The INI
    method performs device specific initialization and is
    run when OSPM loads a description table.  It must only
    access OperationRegions that have been indicated as
    available by the _REG (Region) method.  We do not have a
    _REG method and during my testing, I added a REG method
    but it did not seem to make a difference in the PCI
    register space.  The bit fields defined as NSDI (Disable
    No Snoop), NSDO (Disable No Snoop Override), and NSEN
    (Enable No Snoop Request) do not ever get written from
    their default values.  And writing to these bit fields
    does not seem to be necessary because I did not notice
    any change in audio functionality.
    
    In an effort to clean up as many FWTS errors as possible,
    I propose removing this method altogether.  I have seen no
    change in operation (audio works with and without this
    method) and there does not seem to be any change in lspci
    or dmesg.
    
    FWTS information can be found here:
    [1]: https://wiki.ubuntu.com/Kernel/Reference/fwts
    
    Change-Id: If8d86f959822d528c44ab011a851659d486289b5
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2726
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e31c0ed9b5f789cb0207740c588c769f7eda5f0e
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Tue Mar 12 10:21:24 2013 -0600

    Persimmon DSDT: Add OSC method
    
    The _OSC method is used to tell the OS what capabilities
    it can take control over from the firmware.  This method
    is described in chapter 6.2.9 of the ACPI spec v3.0.
    The method takes 4 inputs (UUID, Rev ID, Input Count,
    and Capabilities Buffer) and returns a Capabilites
    Buffer the same size as the input Buffer.  This Buffer
    is generally 3 Dwords long consisting of an Errors
    Dword, a Supported Capabilities Dword, and a Control
    Dword.  The OS will request control of certain
    capabilities and the firmware must grant or deny control
    of those features.  We do not want to have control over
    anything so let the OS control as much as it can.
    
    The _OSC method is required for PCIe devices and dmesg
    checks for its existence and issues an error if it is
    not found.
    
    Change-Id: I1494285def7440972f0549b7cb73eb94dafc72c2
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2684
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 35c2f4fd4aac8b14421ee73be490bde06dbcef56
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Mar 14 13:00:14 2013 -0700

    Drop CHIP_NAME from intel/baskingridge
    
    It's no longer required.
    
    Change-Id: I621226a3bdfba9bc8edfd6e511a5337ae603ae19
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2723
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 1570260ba15692e8eafe6af1718aebbbf4ab6a43
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Dec 21 22:18:58 2012 -0600

    haswell: Fix BDSM and BGSM indicies in memory map
    
    This wasn't previously spotted because the printk's were correct.
    However if one needed to get the value of the BDSM or BGSM register
    the value would reflect the other register's value.
    
    Change-Id: Ieec7360a74a65292773b61e14da39fc7d8bfad46
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2689
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1fef1f51779307ff65a82b8fd86ff9fa6d2bcae0
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Dec 19 17:15:43 2012 -0600

    haswell: reserve default SMRAM space
    
    Currently the OS is free to use the memory located at the default
    SMRAM space because it is not marked reserved in the e820. This can
    lead to memory corruption on S3 resume because SMM setup doesn't save
    this range before using it to relocate SMRAM.
    
    Resulting tables:
    
    	coreboot memory table:
    	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
    	 1. 0000000000001000-000000000002ffff: RAM
    	 2. 0000000000030000-000000000003ffff: RESERVED
    	 3. 0000000000040000-000000000009ffff: RAM
    	 4. 00000000000a0000-00000000000fffff: RESERVED
    	 5. 0000000000100000-0000000000efffff: RAM
    	 6. 0000000000f00000-0000000000ffffff: RESERVED
    	 7. 0000000001000000-00000000acebffff: RAM
    	 8. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
    	 9. 00000000ad000000-00000000af9fffff: RESERVED
    	10. 00000000f0000000-00000000f3ffffff: RESERVED
    	11. 00000000fed10000-00000000fed19fff: RESERVED
    	12. 00000000fed84000-00000000fed84fff: RESERVED
    	13. 0000000100000000-000000018f5fffff: RAM
    
    	e820 map has 13 items:
    	  0: 0000000000000000 - 0000000000030000 = 1 RAM
    	  1: 0000000000030000 - 0000000000040000 = 2 RESERVED
    	  2: 0000000000040000 - 000000000009f400 = 1 RAM
    	  3: 000000000009f400 - 00000000000a0000 = 2 RESERVED
    	  4: 00000000000f0000 - 0000000000100000 = 2 RESERVED
    	  5: 0000000000100000 - 0000000000f00000 = 1 RAM
    	  6: 0000000000f00000 - 0000000001000000 = 2 RESERVED
    	  7: 0000000001000000 - 00000000acec0000 = 1 RAM
    	  8: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
    	  9: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
    	  10: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
    	  11: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
    	  12: 0000000100000000 - 000000018f600000 = 1 RAM
    
    Booted and checked e820 as well as coreboot table information.
    
    Change-Id: Ie4985c748b591bf8c0d6a2b59549b698c9ad6cfe
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2688
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c12ef9723efac1006307c7fae13e34cb444cee36
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Dec 18 14:22:49 2012 -0600

    haswell: resource allocation
    
    The previous code w.r.t. resource allocation was getting lucky
    based on the way fixed mmio resources on the system were being
    chosen. Namely, PCIEXBAR was the lowest mmio space and the other
    fixed non-standar BARs were above it. The resource allocator would
    then start allocating standard BARs below that.
    
    On top of that other resources were being added when
    dev_ops->set_resources() was being called on the PCI domain. At that
    point the PCI range limit were already picked for where to start
    allocating from.
    
    To ensure we no longer get lucky during resource allocation add the
    fixed resources in the host bridge and add the memory controller
    cacheable memory areas. With those resources added the range limit
    for standard PCI BARs is chosen properly.
    
    Depending on haswell board configurations we may need to adjust and
    pass in the size of physical address space needed for PCI resources
    to the reference code. For the time being the CRBs appear to be OK.
    
    Lastly, remove the SNB workaround for reserving 2MiB at 1GiB and 512MiB.
    
    Output from 6GiB memory configuration:
    	MC MAP: TOM: 0x140000000
    	MC MAP: TOUUD: 0x18f600000
    	MC MAP: MESEG_BASE: 0x13f000000
    	MC MAP: MESEG_LIMIT: 0x7fff0fffff
    	MC MAP: REMAP_BASE: 0x13f000000
    	MC MAP: REMAP_LIMIT: 0x18f5fffff
    	MC MAP: TOLUD: 0xafa00000
    	MC MAP: BDSM: 0xada00000
    	MC MAP: BGSM: 0xad800000
    	MC MAP: TESGMB: 0xad000000
    	MC MAP: GGC: 0x209
    
    	coreboot memory table:
    	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
    	 1. 0000000000001000-000000000009ffff: RAM
    	 2. 00000000000a0000-00000000000fffff: RESERVED
    	 3. 0000000000100000-0000000000efffff: RAM
    	 4. 0000000000f00000-0000000000ffffff: RESERVED
    	 5. 0000000001000000-00000000acebffff: RAM
    	 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
    	 7. 00000000ad000000-00000000af9fffff: RESERVED
    	 8. 00000000f0000000-00000000f3ffffff: RESERVED
    	 9. 00000000fed10000-00000000fed17fff: RESERVED
    	10. 00000000fed18000-00000000fed18fff: RESERVED
    	11. 00000000fed19000-00000000fed19fff: RESERVED
    	12. 00000000fed84000-00000000fed84fff: RESERVED
    	13. 0000000100000000-000000018f5fffff: RAM
    
    	e820 map has 11 items:
    	  0: 0000000000000000 - 000000000009fc00 = 1 RAM
    	  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
    	  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
    	  3: 0000000000100000 - 0000000000f00000 = 1 RAM
    	  4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
    	  5: 0000000001000000 - 00000000acec0000 = 1 RAM
    	  6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
    	  7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
    	  8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
    	  9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
    	  10: 0000000100000000 - 000000018f600000 = 1 RAM
    
    Output from 4GiB memory configuration:
    	MC MAP: TOM: 0x100000000
    	MC MAP: TOUUD: 0x14f600000
    	MC MAP: MESEG_BASE: 0xff000000
    	MC MAP: MESEG_LIMIT: 0x7fff0fffff
    	MC MAP: REMAP_BASE: 0x100000000
    	MC MAP: REMAP_LIMIT: 0x14f5fffff
    	MC MAP: TOLUD: 0xafa00000
    	MC MAP: BDSM: 0xada00000
    	MC MAP: BGSM: 0xad800000
    	MC MAP: TESGMB: 0xad000000
    	MC MAP: GGC: 0x209
    
    	coreboot memory table:
    	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
    	 1. 0000000000001000-000000000009ffff: RAM
    	 2. 00000000000a0000-00000000000fffff: RESERVED
    	 3. 0000000000100000-0000000000efffff: RAM
    	 4. 0000000000f00000-0000000000ffffff: RESERVED
    	 5. 0000000001000000-00000000acebffff: RAM
    	 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
    	 7. 00000000ad000000-00000000af9fffff: RESERVED
    	 8. 00000000f0000000-00000000f3ffffff: RESERVED
    	 9. 00000000fed10000-00000000fed17fff: RESERVED
    	10. 00000000fed18000-00000000fed18fff: RESERVED
    	11. 00000000fed19000-00000000fed19fff: RESERVED
    	12. 00000000fed84000-00000000fed84fff: RESERVED
    	13. 0000000100000000-000000014f5fffff: RAM
    
    	e820 map has 11 items:
    	  0: 0000000000000000 - 000000000009fc00 = 1 RAM
    	  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
    	  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
    	  3: 0000000000100000 - 0000000000f00000 = 1 RAM
    	  4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
    	  5: 0000000001000000 - 00000000acec0000 = 1 RAM
    	  6: 00000000acec0000 - 00000000afa00000 = 2 RESERVED
    	  7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
    	  8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
    	  9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
    	  10: 0000000100000000 - 000000014f600000 = 1 RAM
    
    Output from 2GiB memory configuration:
    	MC MAP: TOM: 0x40000000
    	MC MAP: TOUUD: 0x100600000
    	MC MAP: MESEG_BASE: 0x3f000000
    	MC MAP: MESEG_LIMIT: 0x7fff0fffff
    	MC MAP: REMAP_BASE: 0x100000000
    	MC MAP: REMAP_LIMIT: 0x1005fffff
    	MC MAP: TOLUD: 0x3ea00000
    	MC MAP: BDSM: 0x3ca00000
    	MC MAP: BGSM: 0x3c800000
    	MC MAP: TESGMB: 0x3c000000
    	MC MAP: GGC: 0x209
    
    	coreboot memory table:
    	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
    	 1. 0000000000001000-000000000009ffff: RAM
    	 2. 00000000000a0000-00000000000fffff: RESERVED
    	 3. 0000000000100000-0000000000efffff: RAM
    	 4. 0000000000f00000-0000000000ffffff: RESERVED
    	 5. 0000000001000000-000000003bebffff: RAM
    	 6. 000000003bec0000-000000003bffffff: CONFIGURATION TABLES
    	 7. 000000003c000000-000000003e9fffff: RESERVED
    	 8. 00000000f0000000-00000000f3ffffff: RESERVED
    	 9. 00000000fed10000-00000000fed17fff: RESERVED
    	10. 00000000fed18000-00000000fed18fff: RESERVED
    	11. 00000000fed19000-00000000fed19fff: RESERVED
    	12. 00000000fed84000-00000000fed84fff: RESERVED
    	13. 0000000100000000-00000001005fffff: RAM
    
    	e820 map has 11 items:
    	  0: 0000000000000000 - 000000000009fc00 = 1 RAM
    	  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
    	  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
    	  3: 0000000000100000 - 0000000000f00000 = 1 RAM
    	  4: 0000000000f00000 - 0000000001000000 = 2 RESERVED
    	  5: 0000000001000000 - 000000003bec0000 = 1 RAM
    	  6: 000000003bec0000 - 000000003ea00000 = 2 RESERVED
    	  7: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
    	  8: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
    	  9: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
    	  10: 0000000100000000 - 0000000100600000 = 1 RAM
    
    Verified through debug messages that range limits as well as
    resources were being properly honored.
    
    Change-Id: I2faa7d8a2a34a6a411a2885afb3b5c3fa1ad9c23
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2687
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 6f561afa4a635958dedf20ffda9a40c6f5e5699e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Dec 19 14:38:01 2012 -0600

    lynxpoint: lpc resource reservations
    
    This commit updates the Lynx Point resource reservations before
    the coreboot allocator assigns resources. There is no need to mark
    anything as subtractive decode because there are no devices/buses
    linked to the LPC device.
    
    The I/O range reservations consists of claiming the first 4KiB
    of I/O space. The PMBASE, GPIOBASE, and LPC generic I/O decode
    ranges are checked against the default claimed range. If those
    ranges overlap or fall outside of the default range then those
    resources are added.
    
    The MMIO range reservations consist of claiming everything from
    the I/O APIC to 4GiB. The RCBA and the LPC Generic Memory range
    register are then conditionally added if they fall outside of
    the default MMIO range.
    
    Change-Id: I0f560a03814a2b15961fdbe61e4164cd54cff7a5
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2682
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 26e7dd703dea8dce30829d8bb73c1f27a2178d72
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Dec 19 09:12:31 2012 -0800

    haswell: more ULT/LP support and minor tweaks
    
    - Add ME device ID for Lynxpoint LP
    - Add GPU device IDs for ULT
    - SATA init tweaks from checking against DXE reference code
    - Remove the ICH7 from the SPI driver so it works on all lynxpoint
    without having to add more LPC device ID checks
    - Add function disable for audio dsp and xhci, remove PCI bridge
    - Add interrupt route registers for new devices (needs romstage setup)
    
    Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2680
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit eb58bc5af6b8bf626f38d0c07bf55db2835f53b5
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Dec 19 09:14:10 2012 -0800

    baskingridge: Report static temperature in _TMP
    
    The current code is attempting to convert from an invalid
    starting temperature.  Since we aren't sure where the temperature
    will come from yet just return a static value.
    
    This stops the kernel from going to S5 on boot because it
    thinks the temperature is too high.
    
    Change-Id: I433fa407e545458344af5842b353df5bc71bfdad
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2679
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ed7b52d3cb4c5f3f4ecfd43d93c0c5e2d459fe23
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Dec 18 14:18:53 2012 -0600

    haswell: remove CONFIG_GFXUMA
    
    This option is not required for haswell. Enabling the option doesn't
    do anything aside from complicate mtrr calculation. Therefore, remove
    it.
    
    Change-Id: I897523ff7d3606eb89961674c2eb3d384e584857
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2678
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f7fa218359cdfa981a2e6ea8c8eba32cb0567693
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Dec 18 17:01:57 2012 -0600

    x86: improve lb_cleanup_memory_ranges
    
    There are 2 issues in lb_cleanup_memory_ranges(). The first
    is that during sort there is a neighbor comparison that initially
    starts with the current entry. The second issue is that merging
    has an off by one comparison for adjacent entries.
    
    Before:
    	coreboot memory table:
    	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
    	 1. 0000000000001000-000000000009ffff: RAM
    	 2. 00000000000a0000-00000000000fffff: RESERVED
    	 3. 0000000000100000-0000000000efffff: RAM
    	 4. 0000000000f00000-0000000000ffffff: RESERVED
    	 5. 0000000001000000-00000000acebffff: RAM
    	 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
    	 7. 00000000ad000000-00000000af9fffff: RESERVED
    	 8. 00000000f0000000-00000000f3ffffff: RESERVED
    	 9. 00000000fed10000-00000000fed17fff: RESERVED
    	10. 00000000fed18000-00000000fed18fff: RESERVED
    	11. 00000000fed19000-00000000fed19fff: RESERVED
    	12. 00000000fed84000-00000000fed84fff: RESERVED
    	13. 0000000100000000-000000018f5fffff: RAM
    
    After:
    	coreboot memory table:
    	 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
    	 1. 0000000000001000-000000000009ffff: RAM
    	 2. 00000000000a0000-00000000000fffff: RESERVED
    	 3. 0000000000100000-0000000000efffff: RAM
    	 4. 0000000000f00000-0000000000ffffff: RESERVED
    	 5. 0000000001000000-00000000acebffff: RAM
    	 6. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES
    	 7. 00000000ad000000-00000000af9fffff: RESERVED
    	 8. 00000000f0000000-00000000f3ffffff: RESERVED
    	 9. 00000000fed10000-00000000fed19fff: RESERVED
    	10. 00000000fed84000-00000000fed84fff: RESERVED
    	11. 0000000100000000-000000018f5fffff: RAM
    
    Change-Id: I656aab61b0ed4711c9dceaedb81c290d040ffdec
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2671
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0160d76152ecfbcbed599bb697917b423931b92b
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Dec 13 16:51:41 2012 -0600

    baskingridge: dev, recovery, and WP switch support
    
    This commit adds support for the deveveloper, recovery,
    and write protect querying. It just uses jumpers on the
    Basking Ridge board.
    
    Noted ability to togggle jumpers results in toggling the
    respective modes.
    
    Change-Id: Iac189a1fa0245654591e2e9075380db422a329a0
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2676
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit bdd89d0dc23ab4cd2efe5fcb9f0753a09aa14dc9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Dec 13 16:50:10 2012 -0600

    baskingridge: update gpio map documentation
    
    While looking at the Basking Ridge schematic I noticed some changes
    and wanted to make sure they were reflected in the GPIO map.
    
    Change-Id: I686653c164314ae9f68c42331d2f950751411d4a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2675
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 711612989930fdb3c1d60b3fc99ccb6918c3f135
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Dec 13 16:43:32 2012 -0600

    haswell: Add VGA PCI ID mappings
    
    Needed to map VGA OPROM IDs to actual device IDs
    
    Change-Id: I6743905c3db52519bf18f4bcc1a972aec43d3e9d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2674
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit ef8f4c78a55bc8c2874b02177e0612c8bffb5e39
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Dec 12 12:32:43 2012 -0600

    baskingridge: zero out alt_gp_smi_en in devicetree
    
    The baskingridge has a non-zero alt_gp_smi_en value in the
    devicetree.cb file. It has just to be determined which GPI
    pins should trigger an SMI on basking ridge. Without this change
    the board would hang during boot (presumably through a SMI flood).
    
    No more hangs once the value is zero.
    
    Change-Id: I9704071bb7966bd3d0bbbc4aafede3f42d829b17
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2673
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e265d209374812f103fa401be518db624b79520d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Mar 12 14:32:26 2013 -0700

    baskingridge: rename graysreef to baskingridge
    
    The Grays Reef CRB is deprecated by order of Intel. Basking Ridge
    is the new hotness. Therefore, rename graysreef to basking ridge.
    
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    
    Change-Id: I203497e165d8efc99d3438c4c548140a6e9cc649
    Reviewed-on: http://review.coreboot.org/2672
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 74c0d05cf51e089357712b2c855f344caba680fb
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Dec 17 11:31:40 2012 -0800

    lynxpoint: Update device IDs and clock gating setup
    
    - Add device IDs for lynxpoint mobile and LP variants.
    - Update the clock gating setup based on BWG
    - Update the SATA programming based on BWG
    - Add a DEVSLP0 mux config register
    
    Change-Id: Icf4d7bab7f3df7adef5eb7c5e310a6995227a0e5
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2649
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 045f153a4fe2b6e1cb193db01866218d0316f253
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Dec 17 11:29:10 2012 -0800

    lynxpoint: Add new GPIO interface for Lynxpoint-LP
    
    The low power variant of the chipset introduces a completely
    new interface to the GPIOs.
    
    This is a 1KB region and so needs to be moved as well so it does
    not conflict with other IO regions.
    
    Also expose the gpio_get functions to ramstage and move the
    prototypes to pch.h so they can be used for both GPIO interfaces.
    
    Change-Id: I20bc18669525af16de8cdf99f0ccfa9612be63ad
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2648
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 51254049b91a816c53b5cadf72d254f11e882818
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Dec 17 11:24:45 2012 -0800

    haswell: Add ULT CPUID and updated microcode
    
    This adds microcode ffff000a and the CPUIDs for ULT.
    
    Change-Id: I341c1148a355d8373b31032b9f209232bd03230a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2647
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit df7be71374a8b80708c58fd13e26b9e3fc6ed54c
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Dec 17 11:22:57 2012 -0800

    haswell: Add ULT device IDs
    
    Device IDs for northbridge and GPU.
    
    Also mask off the lock bit in the memory map registers.
    
    Change-Id: I9a4955d4541b938285712e82dd0b1696fa272b63
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2646
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit fb9928f2ec240babb5d3138136c03a7a78c53cc4
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Dec 17 11:11:26 2012 -0800

    lynxpoint: Add Kconfig entry for Low Power chipset
    
    There are enough subtle differences that it is useful to have
    a Kconfig entry to differentiate the ULT/LP chipet from the
    desktop/mobile versions.
    
    Change-Id: I04ca1bc6f90bcf9e6994ea7125c98347e8def898
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2645
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit be98524ab208be4764c7d79bdcc7c35162210af1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Dec 12 12:40:33 2012 -0600

    lynxpoint: ME to BIOS Payload Updates
    
    This commit contains a bevy of updates:
    
    - PCI device id is updated to match Lynx Point EDS in the ME driver.
    - Allocate the memory to store the consumption of the MBP.
    - me_bios_payload structure is now a structure of pointers that point
      into the allocated memory.
    - The ICC profile structure was updated to correctly reflect the
      documentation.
    
    Verfied that output of MBP reading can handle unknown items.
    
    Change-Id: I43cc45e6b797444c105e7c842eb5684e9c104687
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2641
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 569c653a72cce2a29688f86849d48a5f0f935cf1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Dec 11 17:17:38 2012 -0600

    lynx point: add new ME status information
    
    According to the 0.8.0 ME BWG this is a new state. It's not very clear
    what exactly it entails, but the Basking Ridge CRB was tripping it when
    MRC_DEBUG was enabled (presumably because of a DID timeout).
    
    Instead of 0x17 one can now see the proper message for this state.
    
    Change-Id: I5bda1de7d3d957d38a4760a02dcd170ec48782e9
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2640
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f72ad02158945c0c80aedd81218fb4fc4080cf1e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Nov 2 09:19:43 2012 -0500

    graysreef: update platform information
    
    Some of the Lynx Point ids were off. Correct those and make
    the pei data BAR fields consistent with the others.
    
    Change-Id: I4102439588362cdb94643bd1ce69c9fa4278329e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2622
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4412bc4ae8f8ab33a49cdd00098754ff7c333a01
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Tue Mar 12 11:07:07 2013 +0100

    OT200: reset MFGTP7 (backlight pwm)
    
    The CS5536 companion device has three different power domains.
    * working domain
    * standby domain
    * RTC domain
    
    When the system is "off" only the standby domain is powered.
    MFGPT[7:6] are member of the standby power domain.
    
    MFGPT7 is used to control the backlight of the device and so the
    timer gets used and configured during system boot. If the system
    does a reboot the timer stays configured and the Linux driver
    can not use it:
       "ot200-backlight: ot200-backlight.0: MFGPT 7 not availale"
    
    The cs5535-mfgpt has a function to hard-reset all MFGPTs but the
    system hangs after the first access to a MFGPT register - cause
    unknown.
    
    /*
     * This is a sledgehammer that resets all MFGPT timers. This is required by
     * some broken BIOSes which leave the system in an unstable state
     * (TinyBIOS 0.98, for example; fixed in 0.99).  It's uncertain as to
     * whether or not this secret MSR can be used to release individual timers.
     * Jordan tells me that he and Mitch once played w/ it, but it's unclear
     * what the results of that were (and they experienced some instability).
     */
    static void reset_all_timers(void)
    {
    	uint32_t val, dummy;
    
    	/* The following undocumented bit resets the MFGPT timers */
    	val = 0xFF; dummy = 0;
    	wrmsr(MSR_MFGPT_SETUP, val, dummy);
    }
    
    After playing around with this undocumented MSR it looks like I only
    need to set bit 7 to free the MFGPT7.
    
    BTW, all MFGPT[0:5] will be reset during pll_reset().
    
    Change-Id: I54a8d479ce495b0fc2f54db766a8d793bbb5d704
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/2527
    Tested-by: build bot (Jenkins)
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 138f2cede491b65cfd8c73b9185a2dc7ee10b8b3
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Dec 12 09:22:34 2012 -0800

    haswell: remove GPIO60 memory reset gate on S3 transition
    
    This is no longer tied to a GPIO but has a proper chipset pin.
    
    Change-Id: Iba70338e8c67e3c3c1cb32e69bfea1282fda8cb5
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2643
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 89f79a019fd049f26ed7bf40618ff960bd9e095e
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Oct 31 23:05:25 2012 -0500

    haswell: remove explicit pcie config accesses
    
    Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
    the pcie explicit accesses. The default config accesses use
    MMIO.
    
    Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2618
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b9ea8b3fb0082840b0c9d449535f4c49c2e885ac
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Nov 2 09:10:30 2012 -0500

    lynxpoint: PMIR register rename
    
    The register that controls global reset is named the Power
    Mangement Initialization Regiser (PMIR). Update the defines
    to reflect the documentation.
    
    Additionally, there is no core well reset control according to the
    EDS. There is, however, a CF9 lock field to lock this register down.
    
    Change-Id: I773c33bec63a06cdb869eb9f94553d476e492798
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2619
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9aa031e47157e37e8f3cd80cbc80215e2843eaa9
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Nov 2 09:16:46 2012 -0500

    lynxpoint: Management Engine Updates
    
    The ME9 requirements have added some registers and changed some
    of the MBP state machine. Implement the changes found so far in
    the ME9 BWG. There were a couple of reigster renames, but the
    majority of th churn in the me.h header file is just introducing
    the data structures in the same order as the ME9 BWG.
    
    Change-Id: I51b0bb6620eff4979674ea99992ddab65a8abc18
    Signed-Off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2620
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dc278f8fd0318caf0c11330478dff8453bb1107d
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Dec 11 17:15:13 2012 -0600

    haswell: Properly Guard Engergy Policy by CPUID
    
    The IA32_ENERGY_PERFORMANCE_BIAS MSR can only be read or written
    to if the CPU supports it. The support is indicated by ECX[3] for
    cpuid(6). Without this guard, some Haswell parts would GP# fault
    in this routine.
    
    No more GP# while running on haswell CRBs.
    
    Change-Id: If41e1e133e5faebb3ed578cba60743ce7e1c196f
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2639
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit c1989c494e2628618067d03d9e192ac25b4f42d1
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Dec 11 17:13:17 2012 -0600

    haswell: add PCI id support
    
    In order for coreboot to assign resources properly the pci
    drivers need to have th proper device ids. Add the host controller
    and the LPC device ids for Lynx Point.
    
    Resource assignment works correctly now w/o odd behavior because
    of conflicts.
    
    Change-Id: Id33b3676616fb0c428d84e5fe5c6b8a7cc5fbb62
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2638
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit b6b5aa15cecf2a9226bf5c265f15bf905c90e558
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Dec 7 09:50:40 2012 -0600

    haswell: Remove logic to send dram init done to ME
    
    The reference code sends the dram init done command to the ME.
    Therefore, there is no need for coreboot to do this.
    
    Change-Id: I6837d6c50bbb7db991f9d21fc9cdba76252c1b7b
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2633
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 68724fd1e327d3e33c93bceec56973c0a4f7f505
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Fri Dec 7 09:47:16 2012 -0600

    basking ridge: update gpio, spd addresses, and OC
    
    Even though this is under the graysreef board it really
    applies to the Basking Ridge board. A subsequent patch will
    rename graysreef to baskingridge.
    
    The GPIO pins were updated to reflect the Basking Ridge schematics
    as well as the DIMM spd addresses and USB over current pins.
    
    Change-Id: Ice4e05f5203de3024cd463dfccf0bcfec1e247c1
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2632
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 30c3900451756793144bb579acc59205381138ab
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 29 17:21:51 2012 -0600

    haswell: notes and updates.
    
    Add a FIXME about checking a MCHBAR register that isn't setup yet.
    Also, remove revision updating because I can't find anything in the
    docs that suggest this is required for haswell.
    
    Change-Id: Ia8a6e08f82e18789e31c6c2ec2c1d63740c18dc4
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2631
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8256a9b715df14dc8914b641796344ac513cb889
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Nov 29 17:18:53 2012 -0600

    haswell: align pei_data structure with intel-framework
    
    The intel-framework code has an updated pei_data structure.
    Use the new structure and revision. Also, remove the scrambler
    seed saving in CMOS since that appears to be handled in the saved
    data from the reference code.
    
    Change-Id: Ie09a0a00646ab040e8ceff922048981d055d5cd2
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2630
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b9adf7ba4bf6e8f11bf174973230c5317cbb3b6d
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Mon Nov 12 10:14:55 2012 -0600

    haswell: use #defines for constants in udelay.c
    
    Change the hard coded values in udelay.c to use the #defines
    for MSRs and BCLK.
    
    Change-Id: I2bbeb0b478d2e3ca155e8f82006df86c29a4f018
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2629
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f6933a6f56f8bdc7e249b6629824acce646d5f6a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Oct 30 09:09:39 2012 -0500

    Mainboard: Add support for Grays Reef
    
    Grays Reef is one of Intel's CRBs for the Haswell processor. The
    platform is named Shark Bay.
    
    GPIOs were the main focus so IRQ routing and ACPI still needs to be
    further looked at.
    
    Change-Id: Ie94b7af66f772714992a92612c76ca93b9b27088
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2621
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ce36b12c2702d88e95e5c0294035bcd5e1de22ab
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jan 10 13:23:48 2013 -0800

    haswell: Add LPT LP device IDs to platform report
    
    Boot haswell ULT and see LPT reported properly.
    
    Change-Id: I48344a8dde6adbbf331c91231342de45b1b6c32a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2697
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 67113e95cf054e051c63e813814b91f909798ac9
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jan 10 13:23:04 2013 -0800

    haswell: Update GPU power management setup
    
    This is the steps outlined in the BWG.
    
    It seems this is a lot simpler now (so far) which is good.
    
    To test, boot to chromeos with 3.7 kernel + i915.preliminary_hw_support=1 and
    see that the i915 driver complains a lot less than before and that a
    splashscreen is displayed.
    
    Change-Id: I722c90ecd351860949cedab24533f6c10e5b90e5
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2696
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7302d1e4cec1149a3da61824497160cea514e2ca
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jan 10 13:19:23 2013 -0800

    lynxpoint: Update IOBP programming method
    
    This follows the new method outlined in the LPT BWG.
    
    It is also very pedantic about its operation so it
    is easier to read and compare against the docs and
    the reference code implementation.
    
    Change-Id: I235d634cded0c75ec0e9f53488f5b366107a18fa
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/2694
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 50a34648cdc7fc55e1fa75d51ece608c0e27245a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Jan 3 17:38:47 2013 -0600

    x86: SMM Module Support
    
    Add support for SMM modules by leveraging the RMODULE lib. This allows
    for easier dynamic SMM handler placement. The SMM module support
    consists of a common stub which puts the executing CPU into protected
    mode and calls into a pre-defined handler. This stub can then be used
    for SMM relocation as well as the real SMM handler. For the relocation
    one can call back into coreboot ramstage code to perform relocation in
    C code.
    
    The handler is essentially a copy of smihandler.c, but it drops the TSEG
    differences. It also doesn't rely on the SMM revision as the cpu code
    should know what processor it is supported.
    
    Ideally the CONFIG_SMM_TSEG option could be removed once the existing
    users of that option transitioned away from tseg_relocate() and
    smi_get_tseg_base().
    
    The generic SMI callbacks are now not marked as weak in the
    declaration so that there aren't unlinked references. The handler
    has default implementations of the generic SMI callbacks which are
    marked as weak. If an external compilation module has a strong symbol
    the linker will use that instead of the link one.
    
    Additionally, the parameters to the generic callbacks are dropped as
    they don't seem to be used directly. The SMM runtime can provide the
    necessary support if needed.
    
    Change-Id: I1e2fed71a40b2eb03197697d29e9c4b246e3b25e
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2693
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5ca4f4119bf00a1ec64358f3e6b41d696b1dc123
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Thu Mar 7 23:22:24 2013 -0600

    libpayload: add support for vboot_handoff
    
    The vboot_handoff structure needs to be parsed from the coreboot tables.
    Add a placeholder in sysinfo as well as the ability to parse the
    coreboot table entry concering the vboot_handoff structure.
    
    Built with unified boot loader and ebuild changes. Can find and use
    the VbInitParams for doing kernel selection.
    
    Change-Id: If40a863b4a445fa5f7814325add03355fd0ac647
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2720
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1cb414de638d6885ad3a8510594ea1df7d4d96a6
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Mar 8 04:38:13 2013 -0800

    libpayload: Turn the endian conversion macros into functions.
    
    In their current macro form, any arguments that are expressions will be
    evaluated multiple times. That can cause problems if they have side effects,
    and might not even compile if the overall expression is ambiguous, for
    instance if you pass in foo++.
    
    Built with code that previously wouldn't compile because the macros
    expanded to ambiguous expressions.
    
    Change-Id: I378c04d7aff5b4ad40581930ce90e49ba7df1d3e
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2719
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7e568559634199668859b7c662aea7f6b41f3920
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Mar 13 17:03:04 2013 -0700

    Support ITE IT8518 embedded controller running Quanta's firmware
    
    Change-Id: Ib406b9d5005243d79eea5d2c0c6c86b5aa949891
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2721
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5c0b7abe786d7b4370ed1dd7ef323a3091d9620c
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Feb 22 16:38:53 2013 -0800

    libpayload: Generalize and redistribute timekeeping code
    
    The timekeeping code in libpayload was dependent on rdtsc, and when it was
    split up by arch, that code was duplicated even though it was mostly the same.
    This change factors out actually reading the count from the timer and the
    speed of the timer and puts the definitions of ndelay, udelay, mdelay and
    delay into generic code. Then, in x86, the timer_hz and timer_get_raw_value
    functions which used to be in depthcharge were moved over to libpayload's
    arch/x86/timer.c. In ARM where there isn't a single, canonical timer, those
    functions are omitted with the intention that they'll be implemented by a
    specific timer driver chosen elsewhere.
    
    Change-Id: I9c919bed712ace941f417c1d58679d667b2d8269
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2717
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6a0b3611c5b057907aabe2a1c05302440da9bc19
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jan 16 03:18:45 2013 -0800

    libpayload: Put dump_td/dump_ed in ohci.c behind #ifdef USB_DEBUG
    
    This function is static and not used in that file. To avoid the compiler
    complaining about that fact, put the two functions and the call to dump_ed
    (currently #if 0) behind #ifdef USB_DEBUG
    
    Change-Id: Ic373313b5fff81f09800f286b32238350ab699c6
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2716
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6d04f0f89e4bf8ea4bea35dd850dad7469ca5ab3
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Oct 31 22:57:16 2012 -0500

    haswell: always use MMIO PCI config accesses
    
    Add a bootblock.c file for the northbridge and setup the
    PCIEXBAR as the first thing using IO PCI config acceses.
    After that all PCI config accesses can use MMIO.
    
    Change-Id: I51d229c626c45705dda1757c2f14265cbc0e6183
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2617
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 76c3700f02f79b49fec30d6ef18d336f122cbf50
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Tue Oct 30 09:03:43 2012 -0500

    haswell: Add initial support for Haswell platforms
    
    The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore,
    the southbridge support is included as well. The basis for this code is
    the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires
    more attention, but this is a good starting point.
    
    This code partially gets up through the romstage just before training
    memory on a Haswell reference board.
    
    Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2616
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cc86e63e835ab0bceb62215460a13266a791cdd3
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Mar 2 03:32:19 2013 -0800

    libpayload: Don't declare the loop counter within the for loop
    
    'for' loop initial declarations are only allowed in C99 mode
    
    I didn't realize we don't enable 14 year old features when building
    libpayload, and I must have accidentally not rebuilt everything when making my
    final tweaks to my earlier change.
    
    Change-Id: I6caeeffad177b6d61fa30175f767e85084c061f4
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2718
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 0f5a3fc36794fa23210ada7abf671495e4a98226
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 12 20:16:44 2013 -0700

    exynos5250: add RAM resource beginning at physical address
    
    The original code attempted to reserve a space in RAM for coreboot to
    remain resident. This turns out not to be needed, and breaks things
    for the kernel since the exynos5250-smdk5250 kernel device tree starts
    RAM at 0x40000000.
    
    (This patch was originally by Gabe, I'm just uploading it)
    
    Change-Id: I4536edaf8785d81a3ea008216a2d57549ce5edfb
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2698
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7bc153c6aef0f2615e3dadb274b9fed56ed15732
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Wed Mar 13 16:28:16 2013 -0600

    Eagleheights DSDT: Grant OS control through OSC
    
    Change the OSC method to actually grant control of
    PCIe capabilities to the OS instead of granting no
    control.  I believe the logic was backwards in the
    original commit.  Bits should be set when granting
    control and cleared when not granting control.  By
    setting the return value to 0x00, we effectively
    tell the OS that it cannot control any PCIe
    capability.  See section 6.2.9 of the ACPI spec
    version 3.0 for more information.
    
    This edit is a duplication of the OSC method that
    is in the src/southbridge/intel/bd82x6x/pch.asl
    file.
    
    Change-Id: Id2462ab12203afceb9033f24d06b4dfbf2236d2e
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2714
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 00e5da6f25483f5d29aefadfff56a11dd0f3c97c
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Mar 6 04:46:00 2013 -0800

    libpayload: Don't do unaligned accesses during LZMA decompression
    
    Use memcpy to access a uint32_t that's inherently unaligned due to the layout
    of the LZMA header format.
    
    Built and booted on Daisy and saw a data abort go away. Built and booted
    into developer mode on Link and verified that bitmaps were
    decompressed/displayed correctly.
    
    Change-Id: Id3ae746c04d23bcb0345cb71797bfa219479cc8f
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2670
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 903f8e03307de8a689244eec5bf9aface73850b1
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Feb 26 23:18:24 2013 -0800

    libpayload: Add size_t and ssize_t types for ARM and x86
    
    Some new TPM drivers in depthcharge require that type. I added it to
    arch/types.h which seemed appropriate, but I'm not sure that's exactly the
    right header to use, or in other words if you'd get that type from libpayload
    the same way you'd get it if you were building a standard Linux program.
    
    Also, I attempted to determine what underlying types gcc would use, and while
    I think I picked the right ones I'm not 100% certain of that either.
    
    Change-Id: Ic5c0b4173c8565ede3bfce8870976d596d69e51d
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2669
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a0e27979c06088912489633a67644254bc5a1f70
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Feb 26 19:08:28 2013 -0800

    libpayload: Move over to the payload's stack during startup
    
    Don't keep using the coreboot stack on ARMv7.
    
    Change-Id: I734c5d77f8584e30ee0c720d41e21e3040f56db4
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2668
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0274919bf6853b7a437025a8abf6624b824b3d91
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 12 22:00:43 2013 -0700

    exynos5250/snow: enable branch prediction
    
    This enables branch prediction. We can probably find a better place
    to do this, but for now we'll do it in snow's romstage main().
    
    Change-Id: I86c7b6bc9e897a7a432c490fb96a126e81b8ce72
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2701
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 49ff3c50dd7c4aca145f274a3346f36a2233c7d2
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Jan 16 03:18:02 2013 -0800

    libpayload: ARCH-$(CONFIG_ARCH_ARMV7) was defined twice, make one POWERPC
    
    Change-Id: Ia85a7cd6a0b85119cce6b2f9c42a7fc31ffd9f97
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2654
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dc9e77f45135452166cdd9fb96c2234753febed6
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Feb 1 20:19:27 2013 -0800

    libpayload: Add usb_generic_(create|remove) functions for unrecognized devices
    
    It might be useful to provide a USB driver in the payload itself instead of in
    libpayload. For example there are multiple payloads being built and linked
    against the same libpayload, and they might not need or even want to have the
    same set of drivers installed.
    
    This change adds two new functions, usb_generic_create and usb_generic_remove,
    which behave like the usbdisk_create and usbdisk_remove functions which are
    defined for USB mass storage devices. If a USB device isn't recognized and
    claimed by one of the built in USB class drivers (currently hub, hid, and msc)
    and the create function is defined, then it will be called to give the payload
    a chance to use the device. Once it's removed, if usb_generic_remove is
    defined it will be called, effectively giving the payload notice.
    
    Built and booted depthcharge on Link. Built depthcharge for Daisy. Built
    a netbooting payload, called usb_poll() with those functions implemented, and
    verified that they were called and that the devices they were told about were
    reasonable and the same as what was reported by lsusb in the booted system.
    
    Change-Id: Ief7c0a513b60849fbf2986ef4ae5c9e7825fef16
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2666
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 69eea7c01af0ce095aa7618eadae72e86f6eebbe
Author: Julius Werner <jwerner@chromium.org>
Date:   Fri Jan 11 16:25:52 2013 -0800

    libpayload: Split EHCI bulk transfers on packet boundaries over qTDs
    
    EHCI controllers see transfers as a queue of transfer descriptors
    (qTDs), each of which can represent an aligned area of up to 20KB. Each
    qTD is processed separately, which means that a single USB packet cannot
    span multiple qTDs.
    
    While this should not be a problem according to the specification, some
    USB storage devices seem to get confused when a packet in the middle of
    a transfer is smaller than the maximum packet size (512 bytes) due to
    falling on a qTD boundary. This patch aligns the total transfer length
    per qTD to 512 bytes to avoid that problem (any excess bytes will simply
    roll over to the next qTD).
    
    Change-Id: I0b5db07507699a3861b30c1a5ee774c45dda7fdd
    Signed-off-by: Julius Werner <jwerner@chromium.org>
    Reviewed-on: http://review.coreboot.org/2651
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 716375dd3ee8ec695c38b2ab25e714a0cc116fb0
Author: Vincent Palatin <vpalatin@chromium.org>
Date:   Thu Oct 25 17:38:43 2012 -0700

    libpayload: add support for 64-bit EHCI controllers
    
    Initialize the high part of the address
    and use 64-bit compatible descriptors.
    (waste a few bytes on 32-bit but should be harmless)
    
    Read USB stick on a SandyBridge system which has 64-bit EHCI.
    
    Change-Id: I59cc842459acecdde8f8bdd4795ebfeccb842c8f
    Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2650
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 613c0f630a5fdcb0837d36b8a9104007f0ee7137
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Jan 18 15:04:07 2013 -0800

    libpayload: Stub out time keeping functions for ARM as well
    
    These were currently stubbed out for PowerPC but not for ARM.
    
    Change-Id: I08f45174877bf5751d972078b8c53d82898b7f2b
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2655
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1617e1f0ab0d8e280e60caee693606ad88c37a86
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Jan 15 15:48:55 2013 -0800

    libpayload: If no video drivers initialize in video_init, return 1.
    
    Change-Id: I56f810dfa6654ac1e9d1696ad15e7f1b8bfe59bd
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2652
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit b7b57d97512f1a5fc9a102ae0374ff08242b6e0c
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Jan 18 18:37:29 2013 -0800

    libpayload: If there's no IO address space, don't try to use it for serial
    
    Change-Id: I01b1fa42139af925716cd5d57f96dc24da6df5a7
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2660
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d8d4d113f005c28f3b8d9cc2c6b57627bdf35de1
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Jan 18 18:24:46 2013 -0800

    libpayload: If there's no IO space, complain if the serial claims to use it
    
    Change-Id: I36c750d520ff034c9ca9b9af46bd99bd49af7355
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2659
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1c1171208ff9978ec45d01ade8a0836c3f93b59f
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Jan 18 18:04:44 2013 -0800

    libpayload: Consolidate io vs. mem mapped serial into accessor functions
    
    This way we won't have two copies of the hardware init function, and three
    copies of the putchar, havechar, and getchar functions.
    
    Change-Id: Ifda7fec5d582244b0e163ee93ffeedeb28ce48da
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2657
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d267987083f84253c98d0bbfd1e46cec56aa1dcd
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Jan 18 15:49:00 2013 -0800

    libpayload: Make whether or not there's an IO address space configurable
    
    Default it to no to be consistent with the other architecture wide options
    (endianness), and turn it on explicitly for x86 and PowerPC.
    
    Change-Id: Idda26d580156bbbf08ea11b28abe75cfa6b594b2
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2658
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ffc13bdb2a314046cf86489df88ed28c596f0c4f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Mar 11 14:50:30 2013 -0700

    Update 3rdparty mark to latest repository
    
    For google/stout binaries
    
    Change-Id: I4ef3f9cc35dfb6d27e1c9f074759f0e3ddee73c4
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2635
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ba949d32ba97d96422510967df33532dd39e47c0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Mar 13 13:42:55 2013 -0700

    libpayload: Start using only internal and compiler headers.
    
    When building other payloads with lpgcc the -nostdinc flag was injected into
    CFLAGS, but when building libpayload itself some headers were being used from
    the host system. This change puts -nostdinc into the Makefile and xcompile
    script, fixes up one include path in include/inttypes.h, adds the compiler
    provided include directory to the include search path, and deletes the two now
    redundant stdint.h files.
    
    BUG=None
    TEST=With this and other changes, built libpayload and depthcharge for Daisy,
    Link, and Fox.
    BRANCH=None
    
    Change-Id: Ia7817fceab5297cd82ccc0d392330de0df61980e
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2710
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2def2625e0b49ea3ae85ae8b821979e5901c6638
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Jan 31 04:27:39 2013 -0800

    libpayload: Add more parenthesis to the endian conversion macros
    
    There weren't enough parenthesis in the macros so operations might only apply
    to the last part of an expression passed in as an argument.
    
    Change-Id: I5afb406f9409986e45bbbc598bcbd0dd8507ed35
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2665
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit b53a73ef7726ccbaea73cb560b6f72cdb166eb50
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Feb 11 20:43:45 2013 -0800

    libpayload: Make the source for lzma decompression const
    
    Change-Id: I9a16331dedc97f17af94bf2cf535a9c93d1729a0
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2667
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit aeda4b8c0a47afc52e079faa4c0ea0ee71de9bbf
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Mar 13 13:29:44 2013 +0100

    src/mainboard: Drop redundant `CHIP_NAME` again for new ports
    
    Since commit »Drop redundant CHIP_NAME in mainboard.c« (a93c3fe7) [1]
    `CHIP_NAME` is unneeded for mainboards as the name is composed
    automatically in `src/devices/root_device.c` from the strings in
    Kconfig.
    
    Unfortunately the ports for Google Butterfly, Link and Parrot as
    as well as IEI PM-LX2-800-R10 introduced CHIP_NAME again. So drop
    it again too.
    
    [1] http://review.coreboot.org/1635
    
    Change-Id: Ice7577a2a5c6070e196f2647c440b7a8e140e27e
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2708
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e112b746e0559a4a31bfe0eccbf0cabef89630c8
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Mar 13 18:08:29 2013 +0800

    libpayloads: Provide BSD/glibc style endian functions.
    
    The functions in endian.h (betoh{l,w,ll} and others) were named differently from
    the well-known BSD/glibc style endian functions (ex, betoh{16,32,64}). We should
    provide the BSD/glibc style functions to prevent confusion.
    
    Change-Id: Ia3bee481ba7989ac25b79ddb89bc6819d52fd8c3
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2705
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a0996a9c7c445b891ce9e87ba63b16f2fe271582
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 12 21:38:19 2013 -0700

    exynos5250: Don't set PS_HOLD in bootblock_cpu_init
    
    PS_HOLD gets set in exynos' power_init().
    
    Change-Id: Ib08e0afcad23cbd07dc7e3727fd958a1bc868b5a
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2700
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d2bed05e6adc7ea22188917c9551f4cb2d8c949d
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Mar 12 21:28:07 2013 -0700

    exynos5250/snow: call PMIC's power_init() function
    
    Call the power_init() function. We appear to have forgotten about it
    when deprecating lowlevel_init_subsystems(), but it didn't seem to
    cause problems until we got to doing more interesting stuff recently.
    
    There are some clean-ups to do from the original code, such as not
    attempting to configure I2C from PMIC code, which we'll get around
    to in follow-up patches.
    
    (Credit to Gabe for spotting this)
    
    Change-Id: I6a59379e9323277d0b61469de9abe6d651ac5bfb
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2699
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e0c974185c32a89206cb3037f9a9f35aa0dd82d7
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Jan 18 15:14:03 2013 -0800

    libpayload: Remove unnecessary include of arch/msr.h
    
    The functions defined in that header aren't used anywhere in the actual code,
    and that include breaks things on ARM.
    
    Built for ARM with COREBOOT_VIDEO_CONSOLE turned on and saw compiler
    errors go away.
    
    Change-Id: I56d6fe5e00c8fccda6e31ef8752326bd36398e74
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2656
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 2c2c4fae2221f87aeff88162fa3216f3a91af793
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Jan 15 16:22:04 2013 -0800

    libpayload: In the USBMSC read_capacity function, make buf an array of u32.
    
    That way when it's treated as a u32 when its value is extracted for numblocks
    and blocksize below, it doesn't make the compiler unhappy, and it ensures that
    the buffer will be properly aligned on architectures where that sort of thing
    matters.
    
    Built and saw warnings about type punning go away.
    
    Change-Id: I254e0b5e70847112d660675b7df0ac9cb52e4051
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2653
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit ee5c111755ac4acc6dfb6e10a4e271211e149a39
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Mar 12 12:41:40 2013 +0100

    AMD CIMx SB800: Enable AHCI mode for SATA controller by default
    
    The current default is IDE mode which is slower compared to AHCI
    mode. Therefore use AHCI mode by default.
    
    A similar change was made for AMD Persimmon in commit
    »Enable SATA AHCI for faster boot with SeaBIOS.« (96be74c7) [1]
    but was indirectly reverted by »sb800: Add sata ahci/raid mode
    kconfig option« (d4a0e7d0) [2].
    
    [1] http://review.coreboot.org/220
    [2] http://review.coreboot.org/225
    
    Change-Id: I4fa31b0a3280891e7a3f37675ae8415205818947
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2661
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 5021209f5a94e862c6b2915e4e6993b4931364fe
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Mar 11 18:32:50 2013 +0100

    watchdog.h: Fix compile time error on disabling watchdog handling
    
    There's a compile time error that we didn't catch since the
    board defaults as used by the build bot won't expose it.
    
    Just make watchdog_off() a no-op statement so there aren't any
    stray semicolons in the preprocessor output.
    
    Change-Id: Ib5595e7e8aa91ca54bc8ca30a39b72875c961464
    Reported-by: 'lautriv' on irc.freenode.net/#coreboot
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2627
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit db2e3aa2578a931924f5bd269b0279bd403263ea
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Mar 9 10:52:50 2013 +0100

    libpayload: Fix reading x86 CBFS images from RAM
    
    Three issues:
     1. the hardcoded dereferenced pointer at 0xfffffffc
     2. "RAM media" has no idea about ROM relative addresses
     3. off-by-one in RAM media: it's legal to request 4 bytes from 0xfffffffc
    
    Change-Id: I671ac12d412c71dc8e8e6114f2ea13f58dd99c1d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2624
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>

commit 6e7abcd4b58326dc2ea45f1523968d5a099bf6e1
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Mon Dec 10 15:47:23 2012 -0800

    Fix 'git describe' invocation
    
    The 'git describe' command is used to obtain the source tree status
    information when building coreboot. As used this command expects git
    tags to be defined, so it can report the discrepancy between the
    current state of the tree and the latest tag.
    
    The problem is that the coreboot source tree does not have any git
    tags defined, so when 'git describe' is invoked, it reports "fatal: No
    names found, cannot describe anything.". This scary message can be
    seen on the console during coreboot builds.
    
    The solution is to add --always to the `git describe' invocation,
    which causes it to report the discrepancy with the latest sha1, if
    any, which is better than nothing.
    
      $ rm -rf /tmp/li && mkdir /tmp/li
      $ cp configs/config.link .config
      $ make obj=/tmp/li oldconfig
      $ make obj=/tmp/li
      $ grep COREBOOT_VERSION /tmp/li/build.h
      #define COREBOOT_VERSION "1623c06"
      $ echo '#' >> Makefile.inc
      $ grep COREBOOT_VERSION /tmp/li/build.h
      $ make obj=/tmp/li
      #define COREBOOT_VERSION "1623c06-dirty"
      $ git checkout Makefile.inc
    
    Change-Id: Ia77428b7cd765cbbd59bdbf8251b7bef489d47a5
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/2637
    Tested-by: build bot (Jenkins)

commit 68daf3a8757cabb4154c8e2e9712059bab603c3f
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Mar 9 13:24:43 2013 +0100

    pci.h: Drop unused `mainboard_pci_subsystem*` prototypes
    
    We used to allow mainboards to override subsystems using
    mainboard_pci_subsystem_vendor_id and mainboard_pci_subsystem_device_id.
    
    Mechanisms have changed and the only occurrence of these names is in
    the header.
    
    Change-Id: Ic2ab13201a2740c98868fdf580140b7758b62263
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2625
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit ce8410e1d3c6565d288c4cfd6c315db0e65b968e
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Mar 8 12:10:16 2013 +0100

    ASUS M5A88-V: Kconfig: Fix mainboard model name
    
    Despite everywhere the model name M5A88-V is used, in Kconfig the
    string M5A88PM-V is used. Searching for that model string on the
    WWW does not return anything which is unrelated to coreboot, so
    change that string to M5A88-V.
    
    Change-Id: I25cf9d4a5fc3f9b9356e8616452066ebf873f44c
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2613
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: QingPei Wang <wangqingpei@gmail.com>

commit e7ae96f48834d57fd1a6c8940fa3f64b97520ed9
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Nov 13 15:07:45 2012 -0700

    Add Intel Panther Point USB3 initialization
    
    Add PEI updates and ACPI updates for supporting EHCI to XHCI
    USB port support.
    
    Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2519
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 4733c647bc64cef86f03efd64a145e4da6fef123
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Tue Mar 5 14:21:28 2013 -0700

    Persimmon DSDT: Add secondary bus range to PCI0
    
    Adding the 'WordBusNumber' macro to the PCI0
    CRES ResourceTemplate in the Persimmon DSDT.
    This sets up the bus number for the PCI0 device
    and the secondary bus number in the CRS method.
    This change came in response to a 'dmesg' error
    which states:
    '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
    
    By adding the 'WordBusNumber' macro, ACPI can set
    up a valid range for the PCIe downstream busses,
    thereby relieving the Linux kernel from "guessing"
    the valid range based off _BBN or assuming [0-0xFF].
    The Linux kernel code that checks this bus range is
    in `drivers/acpi/pci_root.c`.  PCI busses can have
    up to 256 secondary busses connected to them via
    a PCI-PCI bridge.  However, these busses do not
    have to be sequentially numbered, so leaving out a
    section of the range (eg. allowing [0-0x7F]) will
    unnecessarily restrict the downstream busses.
    
    This change will apply to other AMD mainboards and
    will be in a different commit.
    
    Change-Id: I44f22bc03a0dcbcd2594d4291508826cc2146860
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2592
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit ae0e8d3613ad9cb6872c58cd95fc9774b3b17f5b
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Mar 6 20:43:55 2013 -0800

    Eliminate do_div().
    
    This eliminates the use of do_div() in favor of using libgcc
    functions.
    
    This was tested by building and booting on Google Snow (ARMv7)
    and Qemu (x86). printk()s which use division in vtxprintf() look good.
    
    Change-Id: Icad001d84a3c05bfbf77098f3d644816280b4a4d
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2606
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 31c5e07a04e90c03822d216d2dc92454b42e21ce
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Wed Mar 6 16:18:09 2013 -0700

    AMD Inagua: Use SPD read code from F14 wrapper
    
    Changes:
     - Get rid of the inagua mainboard specific code and use the
       platform generic function wrapper that was added in change
       http://review.coreboot.org/#/c/2497/
       AMD f14: Add SPD read functions to wrapper code
    
     - Move DIMM addresses into devicetree.cb
    
     - Add the ASF init that used to be in the SPD read code into
       mainboard_enable()
    
    Notes:
     - The DIMM reads only happen in romstage, so the function is not
       available in ramstage.  Point the read-SPD callback to a generic
       function in ramstage.
    
    Change-Id: Id05227fcf18c6ab94ffe1beb50b533ab7b0535db
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2607
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit a5ddac02f40e2ebe5606ea65e5c22c63baa2c1c9
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Mar 3 10:56:15 2013 +0100

    AMD CIMx SB800 boards: platform_cfg.h: Integrate Kconfig SATA Mode choice
    
    Currently for Advansus A785E-I, ASRock E350M1 and ASUS M5A88-V
    despite what is chosen in Kconfig »Chipset« menu item,
    
        $ more .config
        […]
        # CONFIG_ENABLE_IDE_COMBINED_MODE is not set
        CONFIG_IDE_COMBINED_MODE=0x1
        # CONFIG_SB800_SATA_IDE is not set
        CONFIG_SB800_SATA_AHCI=y
        # CONFIG_SB800_SATA_RAID is not set
        CONFIG_SB800_SATA_MODE=0x2
        […]
    
    the SATA controller is put into IDE mode.
    
        $ lspci -nn | grep SATA
        00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] [1002:4390] (rev 40)
    
    Commit »sb800: Add sata ahci/raid mode kconfig option«
    (d4a0e7d0) [1] added the options above to configure the mode
    using Kconfig and some SB800 boards were adapted already. For
    example commit »persimmon: sb800 sata mode configure update«
    (1386fa74) [2] did so for AMD Persimmon.
    
    Doing the same by assigning the Kconfig variable to the value in
    `platform_cfg.h` integrates this with the three remaining boards
    listed above.
    
    The patch is successfully tested with the ASRock E350M1.
    
        $ lspci -nn | grep SATA
        00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (rev 40)
    
    [1] http://review.coreboot.org/225
    [2] http://review.coreboot.org/227
    
    Change-Id: I227257e2c8f04f18c27ff00fe62d42e372de67e4
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2610
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit b55b74fc24afc5f64dd93dd402d44e9d453bb8ea
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Mar 7 22:41:25 2013 +0100

    AMD Persimmon: mainboard.c: Make comment generic to reduce difference
    
    Replace »persimmon« by »board« in comment to keep `diff` output
    between boards small.
    
    Change-Id: Ieae2a63782c488ae35f22eb30f5b1049200d12c8
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2611
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 9ca4f51bd441638f177a18a744c78c3655988a4d
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Thu Mar 7 09:10:29 2013 -0700

    AMD Union Station: Use SPD read code from F14 wrapper
    
    Changes:
     - Get rid of the union_station mainboard specific code and
       use the platform generic function wrapper that was added
       in change http://review.coreboot.org/#/c/2497/
       AMD f14: Add SPD read functions to wrapper code
    
     - Move DIMM addresses into devicetree.cb
    
     - Add the ASF init that used to be in the SPD read code into
       mainboard_enable()
    
    Notes:
     - The DIMM reads only happen in romstage, so the function is not
       available in ramstage.  Point the read-SPD callback to a generic
       function in ramstage.
    
    Change-Id: I19d6b0d674b67294519383f80928471b37da1e14
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2609
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit a2f8eb98f5dcc9551a6cfc0ce83eee3eb8fb564f
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Thu Mar 7 08:54:36 2013 -0700

    AMD South Station: Use SPD read code from F14 wrapper
    
    Changes:
     - Get rid of the south_station mainboard specific code and
       use the platform generic function wrapper that was added
       in change http://review.coreboot.org/#/c/2497/
       AMD f14: Add SPD read functions to wrapper code
    
     - Move DIMM addresses into devicetree.cb
    
     - Add the ASF init that used to be in the SPD read code into
       mainboard_enable()
    
    Notes:
     - The DIMM reads only happen in romstage, so the function is not
       available in ramstage.  Point the read-SPD callback to a generic
       function in ramstage.
    
    Change-Id: If4291d25ea81bf375f55b64c07c223a847a211d0
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2608
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit b21eaa74a656fa33f943f76ea0c53ca8374760f6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Mar 7 15:23:45 2013 -0800

    ARMV7 and Google/Snow: Add exception support code to the ramstage
    
    This is previously used exception code from libpayload.
    On startup it installs and then tests an exception handler.
    The test is an unaligned memory operation.
    
    Yes, we've seen what might be exceptions in the ramstage, and
    it makes sense to handle them. This code is identical in structure
    and operation to the previously committed payload exception handler,
    though we reserve the right to change it as circumstances require.
    
    The remaining question is whether we need it in romstage.
    
    Change-Id: I24484686c33c9757af8ba171ebae9773828fb69d
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2614
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit c2f2bd0a6d00a7f8df4005f148f67373db6d26d6
Author: Konstantin Aladyshev <aladyshev@nicevt.ru>
Date:   Wed Mar 6 22:13:42 2013 +0400

    AGESA: Fix CR0_PE bit define
    
    AGESA code has wrong definition of CR0_PE bit (1 instead of 0).
    
    PE [Protected Mode Enable] is 0 bit in CR0 register
    (If PE=1, system is in protected mode, else system is in real mode)
    
    Bit 1 is MP [Monitor co-processor]
    (Controls interaction of WAIT/FWAIT instructions with TS flag in CR0)
    
    System uses CR0_PE define, but I didn't expect any consequences because of this bug.
    
    Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1
    Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/2591
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 4c1e906e36252db3361d7df4c3764b352f53e2f3
Author: Konstantin Aladyshev <aladyshev@nicevt.ru>
Date:   Wed Mar 6 21:39:40 2013 +0400

    Supermicro H8QGI: set up right frequency limits for memory controller
    
    According to BKDG:
    "Memory controller (MCT) and DRAM controllers (DCTs) additions:
    • Support for 933 MHz (1866 MT/s) MEMCLK frequency."
    
    Change-Id: I6f307ce3fcb355d5445f1ea86def73a41b928a57
    Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/2589
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 7fcbbb09fd788a9a1791c2abab96359ce960a2cc
Author: Konstantin Aladyshev <aladyshev@nicevt.ru>
Date:   Wed Mar 6 19:58:38 2013 +0400

    AGESA: Fix bug in AMD_DISABLE_STACK_FAMILY_HOOK_F15
    
    _RDMSR instruction loads the contents of a 64-bit model specific register (MSR)
    specified in the ECX register into registers EDX:EAX.
    The EDX register is loaded with the high-order 32 bits of the MSR
    and the EAX register is loaded with the low-order 32 bits.
    
    EDX:EAX = MSR[ECX]
    
    So bit 49 will be contained in EDX register.
    
    Buggy code instead of bit 49 (CombineCr0Cd) sets bit [49-32=17] (PfcStrideDis).
    PfcStrideDis bit disables stride prefetch generation. This leads to memory
    bandwidth loss.
    
    _________
    
    Supermicro H8QGI board
    
    After applying this change i observed huge memory bandwidth increase in tests
    that runs on small amount of cores. But unfortunately it doesn't affect
    overall bandwidth results on 4P system with 48 cores.
    So i think that in this system leading limiting factor is
    AMD HT-ASSIST feature (Probe filter).
    
    But right now it is not working. System stucks in Linux boot. I have done
    some experiments and figured out that stuck happens when system have cores in
    compute unit (CU) other than CU with BSC (boot strap core).
    CU is two cores (primary and seconary) that shares some things (L2 cache, FPU ...)
    So with probe filter i can boot Linux with one (BSC)
    or two (BSC + secondary core in its CU) cores.
    And with this configuration i can see memory bandwidth on 1 core (or two cores)
    close to original bios.
    
    Change-Id: I5a95f5b753d600c70d3c93d36fecc687610c61cd
    Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/2588
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 00d673d165006b28bbbe5b2d84ef80d8665d8f34
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Thu Mar 7 19:02:15 2013 +0100

    FrontRunner/Toucan-AF: lower SPI speed to 22 MHz
    
    The Hudson-E1's default SPI speed for normal i.e. non-fast reads is 66 MHz,
    but the SST 25VF032B datasheet allows max. 25.  Lower the speed to 22 MHz,
    otherwise BIOS flashing fails.
    
    Change-Id: I22e87d833a3ebd316b6e873595a2480831533ab1
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2605
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 45f72ce60f41a655514c29698678cf3c1fb0c1a9
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sun Feb 24 12:58:33 2013 -0700

    AMD Persimmon: Use SPD read code from F14 wrapper
    
    Changes:
     - Get rid of the persimmon mainboard specific code which has been
       moved into the wrapper as a platform generic function in change
       http://review.coreboot.org/#/c/2497/
       AMD f14: Add SPD read functions to wrapper code
    
     - Move DIMM addresses into devicetree.cb
    
     - Add the ASF init that used to be in the SPD read code into
       mainboard_enable()
    
    Notes:
     - The DIMM reads only happen in romstage, so the function is not
       available in ramstage.  Point the read-SPD callback to a generic
       function in ramstage.
    
    Change-Id: I5f017dbb8dee5a09ec19734a6069ff9b71a6ab50
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2500
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 3b2653b1fc207111e96585a273294cedffc49141
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sun Feb 24 10:46:11 2013 -0700

    AMD Fam14: Add SPD read functions to wrapper code
    
    Change:
    This is the initial step for moving the AMD F14 & HUDSON1,2,3
    SPD-read callout out of the mainboard directories and into
    the wrapper.  The next step is to update the platforms to use
    this routine in BiosCallouts.c and to delete the code from the
    mainboard directories.  The DIMM addresses should be moved into
    devicetree.cb.
    If there are significant differences or reasons that the mainboard
    needs to override this code, it's perfectly reasonable to keep using
    the version in the mainboard, but this allows us to remove duplicated
    code and simplify the mainboard directories.
    
    Notes:
    This started by duplicating what was in Persimmon, and was changed to
    use the devicetree.cb structures.  The ASF setup was also removed from
    the persimmon copy (PMIO writes to 0x28 & 0x29) as that's not needed
    for the SPD access and doesn't make sense to initialize here.
    Significant cleanup and magic number reduction was done as well.
    
    It is intended that this file will not be included in ramstage as
    the DIMM init is all done in romstage.
    
    This is similar to what was done for Parmer/Thatcher in commit
    7fb692bd - http://review.coreboot.org/#/c/2190/
    Fam15tn: Move SPD read from mainboards into wrapper
    
    Yes, it would make sense to split this into two separate files
    and move the SMBUS initialization and access into the southbridge
    wrapper.  Maybe that can come next.
    
    Change-Id: I1e106d3912c160b0015bf02158d9faba4f578ee3
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2497
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit be738eb1336a856bc6f2494ccd7ede3194e6c618
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Mar 7 11:05:28 2013 -0600

    Remove UTF-8 characters from comments
    
    I've used an operating system for over 10 years now that makes
    UTF-8 easy. It's not called Linux or OSX.
    
    When UTF-8 is needed, of course, then we can look again.
    I can't think of a single redeeming feature of placing
    it in the comment in this manner. It's certainy not
    needed.
    
    The inclusion of UTF-8 characters is inconvenient,
    especially from a text terminal.
    I don't really want to start using compose in
    CROSH shell terminals on chromeos.
    
    We might want to incorporate "no UTF-8" as a
    commit filter. For now, get rid of these
    characters.
    
    Change-Id: If94cc657bae1dbd282bec8de6c5309b1f8da5659
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2604
    Reviewed-by: Bernhard Urban <lewurm@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 147cdc3b171c8f02434dc3b6bbd70b6406de93ee
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Mar 7 00:58:10 2013 +0100

    Revert "ARMv7: Simplify div64"
    
    This reverts commit 1cd616082100f47dc2d6d73669c6aa2e5eb039ad
    
    Division bites us again. I don't know how or why, but printk() seems to break (again) with this patch. I'm surprised we didn't encounter problems earlier on...
    
    Change-Id: I81cb9f20879f5eb73a76e1af47b96a68d1e81dc8
    TODO: Find a better solution for div64. This one is too painful, but seems necessary for now (and sort-of works with our vtxprintf hack).
    Reviewed-on: http://review.coreboot.org/2600
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d9b16f3b048243fd7d4c4513875f7f241261ce50
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Mar 6 19:16:10 2013 -0800

    snow: add real values for GPIOs in fill_lb_gpios()
    
    This adds some real GPIO mappings where virtual GPIOs were used before.
    
    Change-Id: I25d4be45f986c8d622b97151f8bdae2651baf3e6
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2603
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1d290eeb1c72a31b5d49a1fca57f99b081fe24d4
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Mar 6 20:11:20 2013 -0800

    exynos5: add GPIO port enums
    
    This adds an enum for GPIO ports on the Exynos5. To make them
    useful, they are assigned the absolute MMIO address where a
    s5p_gpio_bank struct can point to.
    
    Change-Id: Ia539ba52d7393501d434ba8fecde01da37b0d8aa
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2602
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2323f3551fe630e33f7ef59f1309db56956af5d4
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Mar 6 15:56:14 2013 -0800

    google/snow: fix coding style
    
    cosmetics
    
    Change-Id: Iea33768d901641861aa7b2c76af8753a848f584d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2601
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 0f4c0e2669f76bf1081bf13019bc664b4f0e6b38
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Feb 22 12:33:08 2013 +0100

    src/arch/x86/boot/acpigen.c: Small coding style and comment fixes
    
    While reading through the file fix some spotted errors like
    indentation, locution(?), capitalization and missing full stops.
    
    Change-Id: Id435b4750e329b06a9b36c1df2c39d2038a09b18
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2484
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit d59fc5340ea2fc12f6cf98a2e2166435869f0d3c
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Feb 28 00:32:25 2013 +0200

    Fix build by adding `cbmem.c` to `COLLECT_TIMESTAMPS`
    
    A board without HAVE_ACPI_RESUME did not build with
    COLLECT_TIMESTAMPS enabled as `cbmem.c` was not built.
    
    Change-Id: I9c8b575d445ac566a2ec533d73080bcccc3dfbca
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/2549
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>

commit 41dd3dbd5e5619b9957de6850541af7cfe21a1a8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 3 11:36:44 2012 +0300

    Intel e7505: provide get_top_of_ram
    
    This is required to enable EARLY_CBMEM_INIT.
    
    Change-Id: I6d8caf382aa48eded81c1e94bbbcd3975ea88a1a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/2550
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 5a22b14d47955a2cce1d51d883a3c0ee4df39df0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 26 13:49:56 2013 +0200

    Fix socket LGA775
    
    Models 6ex and 6fx select UDELAY_LAPIC so cannot select
    contradicting UDELAY_TSC here.
    
    Model 1067x requires speedstep.
    
    Change-Id: I69d3ec8085912dfbe5fe31c81fa0a437228fa48f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/2525
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e988b515f11fa9483fc5209a9894b8d485525a61
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Feb 23 00:15:49 2013 +0100

    ASRock E350M1: Let `BiosGnbPcieSlotReset()` return `AGESA_UNSUPPORTED`
    
    Quoting Jens Rottmann [1]:
    
    Nevertheless I still think this whole function is bogus for the E350M1.  The
    function assumes GPIO21 is wired to reset APU PCIe lane 0+1 (PCIe x8, port 4+5
    as Coreboot/AGESA calls it), GPIO25 resets lane 2 (PCIe x4) and GPIO02 lane 3.
    But the E350M1 has PCIe x16 i.e. probably APU lanes 0-3 bundled, completely
    different layout.  They could have chosen GPIO21 to force resets, or 25 - or
    maybe 50 like on the Persimmon or any other they fancied or - and this is the
    most probable - none at all.  Having BiosGnbPcieSlotReset() toggle some GPIOs
    without knowing what they do on the E350M1 (if anything at all) is nonsense.
    In my opinion this whole function should just "return AGESA_UNSUPPORTED" and
    good riddance.
    
    [1] http://review.coreboot.org/#/c/2445/
    
    Change-Id: Iac66da41182e838c7e6925250cc3982adbb3e4ec
    Reported-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2489
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>

commit 6bde149d9c56a824eff5db7bb06d7c386fb2be30
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 1 10:18:14 2013 -0800

    samsung/exynos5: add display port and framebuffer defines and initialization
    
    These are essential functions for setting up the display port and
    framebuffer, and also enable such things as aux channel
    communications.  We do some very simple initialization in romstage,
    mainly set a GPIO so that the graphics is powering up, but the complex
    parts are done in the ramstage. This mirrors the way in which graphics
    is done in the x86 size.
    
    I've added a first pass at a real device, and put it in the mainboard
    Kconfig, hoping for corrections. Because startup is so complex,
    depending on device type, I've created a 'displayport' device that
    removes some of the complexity and makes the flow *much* clearer.  You
    can actually follow the flow by looking at the code, which is not true
    on other implementations. Since display port is perhaps the main port
    used on these chips, that's a reasonable compromise. All parameters of
    importance are now in the device tree.
    
    Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2570
    Tested-by: build bot (Jenkins)

commit a4b802ce866a1f3397f0e93e530bf77e253f60ee
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Mar 6 18:42:02 2013 +0100

    ASRock E350M1: mainboard.c: Add declarations for `set_pcie_{,de}reset`
    
    Since the merg of the ASRock E350M1 port (a649a96e) the compiler
    warns about the following [1].
    
        mainboard.c:35, GNU Compiler 4 (gcc), Priorität: Normal
        no previous prototype for 'set_pcie_reset' [-Wmissing-prototypes]
        mainboard.c:43, GNU Compiler 4 (gcc), Priorität: Normal
        no previous prototype for 'set_pcie_dereset' [-Wmissing-prototypes]
    
    Adding the function prototypes to the beginning of the file as
    done in commit »Persimmon updates for AMD F14 rev C0« (d7a696d0)
    addresses the warning.
    
    [1] http://qa.coreboot.org/job/coreboot-gerrit/4975/warnings13Result/package.-139448264/file.-1544928473/
    [2] http://review.coreboot.org/137
    
    Change-Id: Iad2e62ec37c3a2f749a264974b61ac7c226e9b83
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2590
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 31dc0acd9b8c3e5d30aa4e64ab1f24fac84bac1a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Mar 6 08:50:50 2013 -0800

    Google/Snow: enable sound hardware clocks
    
    Set up the clocks used for sound and turn on the sound clock.
    
    Change-Id: Ic59bfa9ae87116299503e6d25aeefba98c842fb8
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2587
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit f4861df1e749885ec68ea0f17a3589aa6e79d13f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Mar 4 16:39:35 2013 -0800

    google/snow: Change MMC0 to work in 8 bit mode.
    
    The MMC0 on google/snow can run in 8 bit mode. To simplify driver development,
    we thought disabling it (using zero, which runs in 1-bit / 4-bit mode) may help.
    
    However, after some experiments in payload drivers, setting pinmux to 8 bit mode
    can still allow MMC to run in 1-bit / 4-bit mode, so it's pretty safe to enable
    8 bit mode by default for better performance.
    
    Verified to boot on google/snow, and got MMC0 working.
    
    Change-Id: Ic0acc723fe6a8aecf373429d3801beadd70815d9
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2585
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 3914a316c3d3ab1ba45fe33394f37aaefdc62d61
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Tue Feb 19 15:01:06 2013 +0100

    AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio
    
    The power up default for the 14M_25M_48M_OSC switchable clock output ball of
    the SB800 chipset is 14 MHz.  sb800/bootblock.c changes this to 48 MHz,
    which is the correct value for almost all SIOs.  However, not for
    'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not
    configurable for other clock speeds.  A wrong SIO clock supply results in
    funny RS232 output (wrong bit speed) and non-working PS/2.
    
    We could switch back to 14 MHz in the mainboard's romstage.c, but then the
    clock frequency would change twice.  The resulting short 48 MHz burst causes
    a handful of rubbish characters on RS232 on every boot until the SIO clock
    has stabilized again.
    
    This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz.
    This does not affect any boards currently in the repository (yet).
    
    Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2454
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 069795a94716cdc5d5dbeed81d491004c3e6a58e
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Mon Mar 4 21:13:57 2013 +0100

    FrontRunner/Toucan-AF: drop unnecessary compile time CPU model selection
    
    The first reason for selecting the CPU model at compile time was a
    multi-second pause if booting a single core Fusion T40R with MAX_CPUS=2.
    Recent tests show the pause has disappeared, someone must have fixed it.
    
    The second reason was me not knowing how to make a single vgabios image
    work with two different PCI IDs.  Many thanks to Martin Roth for educating
    me!  Quote:
    
    "The way to make coreboot use the same vbios for different video device IDs
     is through the map_oprom_vendev function. In family 14 it's in
     northbridge/amd/agesa/family14/amdfam14_conf.c You would name your video
     bios 1002,9802 in the config and all the other device/vendor IDs for the
     family 14h processors will fall through the initial check for the video
     bios and will get remapped to use that vbios. This only works if you're
     initializing the vbios inside coreboot. I don't know if you're using
     SeaBios as a payload, but if you are you can add the vbios to cbfs as
     vgaroms/vbios.rom and the rom will always be initialized."
    
    I'd like to add the vgabios is added as type 'optionrom' when Coreboot make
    adds it, however to work with SeaBios it has to be added manually with
    cbfstool and with type 'raw', or it will hang.
    
    Change-Id: I8190d0c3202a60dfccb77dde232f9ba7ce5ce318
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2584
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c8e4284acbdddd5afbef49c100e6aba44aba849c
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Mar 1 03:22:22 2013 -0800

    libpayload: Turn on thumb interworking in libpayload.
    
    Things work better with it turned on, and the overhead should be negligable.
    
    Built and booted into depthcharge on Snow. Verified that calling between
    various bits of thumb and ARM code worked correctly.
    
    Change-Id: I08d1006e113d2cca08634bf19240aca138a449d9
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2567
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9907c6edeb2c30a9c243219803141f6c0fa91ae6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Mar 3 20:52:05 2013 -0800

    libpayload: Catch exceptions and print out an error message.
    
    Give some indication what happened instead of just crashing.
    As part of setup, cause an exception and make sure that we get
    the right one, and that we recover correctly. Hence we have
    some assurance that if they really happen we can handle them.
    
    Built and booted into test payload on Snow. Saw the built in test function
    worked correctly. Artificially added code which got an exception and saw that
    the error information prints correctly.
    
    Change-Id: I2e0d022f090ee422fb988074fbb197afa2485caa
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2569
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 026bbda071161ad56822dceaabea03bceefac9ac
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Mar 4 09:46:31 2013 -0800

    ARM: remove code that is IMHO a dangerous design
    
    OK, this is tl;dr. But I need to write this in hopes we make
    sure we don't put code like this into coreboot. Ever.
    
    Our excuse in this case is that it was imported, not obviously wrong,
    and easily changed. It made sense to get it in, make it work, then
    do a cleanup pass, because changing everything up front is almost
    impossible to debug.
    
    The exynos code has bunch of base register values, e.g.
    
    These are base addresses of things that look like a memory-mapped
    struct. To get these to a pointer, they created the following macro,
    which creates an inline function.
    
    static inline unsigned int samsung_get_base_##device(void)	\
    {								\
    	return cpu_is_exynos5() ? EXYNOS5_##base : 0;		\
    }
    
    And then invoke it 31 times in a .h file, e.g.:
    SAMSUNG_BASE(clock, CLOCK_BASE)
    
    to create 31 functions.
    
    And then use it:
            struct exynos5_clock *clk =
    	                (struct exynos5_clock *)samsung_get_base_clock();
    
    OK, what's wrong with this? It's easier to ask what's right with it. Answer: nothing.
    
    I have a long list of what's wrong, and I may leave some things out,
    but here goes:
    1. the "function" can return a NULL if we're not on exynos5. Most uses of the code
       don't check the return value.
    2. And why would this function be running, if we're not on an exynos5? Why compile it in?
    3. Note the cast everywhere a samsung_get_base_xxx is used.
       The function returns an untyped variable, requiring the *user* to get two
       things right: the cast, and the function invocation. One can replace that _clock(); with
       _power(); in the code above, and they will be referencing the wrong registers, and
       they'll never get an error!
       We have a C compiler; use it to type data.
    4. You're generating 31 functions using cpp each and every time the file is included.
       The C compiler has to parse these each time. It's not at all like a simple cpp
       macro which is only generated on use.
    5. You can't tags or etags this code
    6. In fact, any kind of analysis tool will be unable to do anything with this cpp magic.
    
    That's only a partial list.
    
    So what's the right way to do it? Just make typed constants, viz:
    
    Or, since I expect people will want the lower case function syntax, I've left
    it that way:
    
    Now we've got something that is efficient, and we don't even need to protect with
    any more.
    
    Hence this change. We've got something that is type checked, does not require users to
    cast on each use, will catch simple programming errors, can be analyzed with standard tools,
    and builds faster.
    
    So if we make a mistake:
           struct exynos5_clock *clk =
                           samsung_get_base_adc();
    
    We'll see it:
    src/cpu/samsung/exynos5250/clock.c: In function 'get_pll_clk':
    src/cpu/samsung/exynos5250/clock.c:183:3: error: initialization from incompatible pointer type [-Werror]
    
    which we would not have seen before.
    
    As a minor benefit, it shaves most of a second off the compilation.
    
    Change-Id: Ie67bc4bc038a8dd1837b977d07332d7d7fd6be1f
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2582
    Tested-by: build bot (Jenkins)

commit 1a43309bf7222fc25e8583d128c9685ec251dd76
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Sat Mar 2 18:27:05 2013 +0100

    bump SeaBIOS to 1.7.2.1
    
    Update coreboot to use SeaBIOS' tag rel-1.7.2.1
    
    Change-Id: I01969407964a7cf64f7c4800b59c6aed845b24f9
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/2575
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 56ad905e4ca5cf09a0b0d93ee6586e7ac02ad8fc
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Mar 3 12:01:15 2013 +0100

    AMD Persimmon, LiPPERT Fam14: Fix typo code*c* in comment
    
    Commit f154c018
    
        Author: Marc Jones <marcj303@gmail.com>
        Date:   Wed Dec 14 11:24:00 2011 -0700
    
            Persimmon audio codec verb patch.
    
        Reviewed-on: http://review.coreboot.org/490
    
    has a typo code*c* in the comments for `AZALIA_OEM_VERB_TABLE`. As
    this was copied over to the LiPPERT Fam14 boards, use the following
    command to fix the typo.
    
        $ git grep -l cocec | xargs sed -i s,cocec,codec,
    
    Change-Id: I1525b0445edab81ab136b3adece52b78ba7abc71
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2576
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit f35ce497d1bbf646e3397ba34dc350b43ac81a44
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Feb 27 11:17:59 2013 +0100

    ASRock E350M1: Remove non-existing PCI devices 12.1 and 13.1
    
    Looking at the coreboot log
    
        […]
        PCI: 00:12.0 [1002/4397] enabled
        sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it.
        sb800_enable() PCI: 00:12.2 [1002/4396] ops
        PCI: 00:12.2 [1002/4396] enabled
        sb800_enable() PCI: 00:13.0 [1002/4397] ops
        PCI: 00:13.0 [1002/4397] enabled
        sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it.
        sb800_enable() PCI: 00:13.2 [1002/4396] ops
        PCI: 00:13.2 [1002/4396] enabled
        […]
    
    and the `lspci -tnvv` output running the proprietary vendor BIOS
    attached to the Wiki page of the ASRock E350M1 [1][2]
    
            -[0000:00]-+-00.0  1022:1510
                       +-01.0  1002:9802
                       +-01.1  1002:1314
                       +-04.0-[01]--
                       +-11.0  1002:4391
                       +-12.0  1002:4397
                       +-12.2  1002:4396
                       +-13.0  1002:4397
                       +-13.2  1002:4396
            […]
    
    both PCI devices do not exist, so remove them from `devicetree.cb`.
    
    Commit 48918f7 [3]
    
        Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) does
    
    did the same for AMD Inagua and AMD Persimmon.
    
    [1] http://www.coreboot.org/ASRock_E350M1
    [2] http://www.coreboot.org/File:ASRock_E350M1_info_dump.tar.bz2
    [3] http://review.coreboot.org/2463
    
    Change-Id: Ief6de1bda093d1f29d5925985e5c3839cdded537
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2536
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit f91c8f290b2a723d1bda9a5dd7d668390672317e
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Fri Mar 1 19:01:00 2013 +0100

    FrontRunner/Toucan-AF: work around AGESA RAM init crashing on reboot
    
    If you try to reset the system with outb(3,0x92), outb(4,0xcf9) or a
    triple-fault it will instead crash with a messy screen.  As the more common
    outb(0xFE, 0x64) doesn't work with our setup, Linux will crash whenever you
    ask it to reboot.  Closer inspection shows that on a warm boot of Coreboot
    agesawrapper_amdinitpost() always fails with error code 7.  Looks like DDR3
    re-init goes wrong somehow.  I tried find the reason for this but was
    unable to.  I am convinced this is not board specific but a bug in AGESA.
    
    In the end I had to settle for a workaround:  if amdinitpost returns 7 this
    patch resets the system harder with outb(0x06, 0x0cf9), after that RAM init
    will succeed.  As amdinitpost is early in POST this automatic reset is
    quick enough not to be noticable.
    
    I'd perfer a real fix, but that's all I have.
    
    Change-Id: I4763254b489f42a135232e45328ecf0d5c4d961a
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2573
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 68c9f2bdc50d5bf51a3d09dc6ebc51bed2ec5d30
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Fri Mar 1 17:20:42 2013 +0100

    LiPPERT Toucan-AF [2/2]: actually implement mainboard support
    
    Step 2: change the Persimmon code to adapt it to the new board's hardware.
    
    The Toucan-AF is a COM Express Compact Type 6 form factor embedded board:
    - AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU
      - 1-4 GB DDR3 memory down
      - 1x VGA, 2x DisplayPort (1 switchable to LVDS)
    - AMD A55E (Hudson-E1) southbridge
      - 8x USB 2.0
      - 4x SATA
      - HD Audio (with codec on baseboard)
      - NEC uPD78F0532 microcontroller on I2C ("SEMA")
    - 7x PCIe2.0 x1 (1 on PEG)
    - Intel I210 GbE (on APU PCIe x1, can be disabled for additional PCIe)
    - 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS)
    
    The Toucan-AF has no SIO on board.  This patch includes basic support for a
    Winbond W83627DHG (PS/2, 2x RS232), because the ADLINK ExpressBase-6 used
    for evaluation happens to have one.  The code may have to be adapted to the
    actual baseboard of the application.
    
    http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132
    
    Change-Id: I9041b905bad45852ac9b402fcbd5decbc98b377b
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2572
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1664404652e2db51845e21db302d162a63eb0347
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Fri Mar 1 17:12:56 2013 +0100

    LiPPERT Toucan-AF [1/2]: create board by forking AMD Persimmon
    
    Step 1: copy all files unmodified from Persimmon.  This makes it much
    easier later to see how the two boards actually and deliberately differ
    when porting bugfixes from one to the other.  Git's copy detection is
    imperfect (and slow).
    
    Change-Id: I1ff02913479c07679f8c3ae5e6dd7876e6000b55
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2571
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 23d13b1d454a6482d436cc65f50bb367c027c10f
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Thu Feb 28 10:24:20 2013 +0100

    LiPPERT FrontRunner-AF [2/2]: actually implement mainboard support
    
    Step 2: change the Persimmon code to adapt it to the new board's hardware.
    
    The FrontRunner-AF is a PC/104+ form factor embedded board:
    - AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU
      - DDR3 SO-DIMM socket (1.5 or 1.35V)
      - VGA and LVDS (via Analogix ANX3110)
    - AMD A55E (Hudson-E1) southbridge
      - 6x USB 2.0
      - 1x SATA, 1x CFast socket
      - HD Audio (via Realtek ALC886)
      - PCI and ISA (via ITE IT8888)
      - NEC uPD78F0532 microcontroller on I2C ("SEMA")
    - Intel I210 GbE (on APU PCIe x1)
    - SMSC SCH3112 SIO
      - PS/2
      - 2x RS232/485
    - 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS)
    
    http://www.adlinktech.com/PD/web/PD_detail.php?pid=1131
    
    Change-Id: Id55f89d224ad669b351c36128b12299802b721ba
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2553
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 73d4965be99cc93cec277afca4cdae979433b2b0
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Thu Feb 28 09:56:20 2013 +0100

    LiPPERT FrontRunner-AF [1/2]: create board by forking AMD Persimmon
    
    Step 1: copy all files unmodified from Persimmon.  This makes it much
    easier later to see how the two boards actually and deliberately differ
    when porting bugfixes from one to the other.  Git's copy detection is
    imperfect (and slow).
    
    Change-Id: I2fd1bf8428fc8a1e7becee888b6182b9bd8166a0
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2552
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d895827c0f54f627bb5fd654bbf1eda40d8f29b4
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Mar 1 03:29:19 2013 -0800

    libpayload: Mark "halt" as a function.
    
    The linker uses that info so interworking can work correctly.
    
    Built and booted into depthcharge on Snow and saw interworking start to
    work correctly.
    
    Change-Id: I0ac54f1c424ec70f8244edf6541a10b089ce47b4
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2568
    Tested-by: build bot (Jenkins)

commit a46a712610c130cdadfe1ebf6bec9ad22e474dac
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Feb 23 18:37:27 2013 +0100

    GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
    
    In the file `COPYING` in the coreboot repository and upstream [1]
    just one space is used.
    
    The following command was used to convert all files.
    
        $ git grep -l 'MA  02' | xargs sed -i 's/MA  02/MA 02/'
    
    [1] http://www.gnu.org/licenses/gpl-2.0.txt
    
    Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2490
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit f12e56181788387c560c9b8d0f3d61fce4a4333a
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Mar 1 10:34:04 2013 +0800

    armv7/snow: Add S5P MSHC initialization in ROM stage.
    
    The SD/MMC interface on Exynos 5250 must be first configured with, GPIO, and
    pinmux settings before it can be detected and used in ramstage / payload.
    
    Verified on armv7/snow and successfully boot into ramstage.
    
    Change-Id: I26669eaaa212ab51ca72e8b7712970639a24e5c5
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2561
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 27bd64a8be3b4e3bff883377e3a0f5ae55d176c7
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Feb 28 17:47:00 2013 +0100

    Revert "ARMv7: drop special handling for stages.c"
    
    This breaks booting, and in fact stages.c is always going to be special: for it to work it has to be compiled for arm only, no thumb allowed. It's probably better to leave the stages.o target in explicitly so it's clear that it has to be compiled with a particular set of flags, rather than try to remember that we must always have the default rules no break stages.c compilation. That would be a mess. I will be pushing a CL to get rid of the assembly dump, but will be a trivial fix.
    
    This reverts commit 8f4647a24bf19a96531af9905b23ae8a2fc2675a
    
    Change-Id: I5e3d8e5b991f6ccf4d49078378cd4615fb230ca0
    Reviewed-on: http://review.coreboot.org/2554
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1bc9efaf6500f2341ec83011e550a42ea68c3901
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Feb 28 01:18:29 2013 +0100

    CBMEM: always initialize early if the board supports it
    
    This allows to drop some special cases in romstage.c
    
    Change-Id: I53fdfcd1bb6ec21a5280afa07a40e3f0cba11c5d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2551
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit f2e1f6a8628d4c13640688790be9550aa9839b34
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Feb 28 00:12:18 2013 +0100

    Drop SRC_ROOT from mainboard Makefile.incs
    
    It's not used, and not needed.
    
    Change-Id: Ifca92f3606ac58fc26e09676488c3add5d84ae79
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2548
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit ef650a5d2456196d653667de7d02abc0591ec024
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Nov 21 02:16:13 2012 -0800

    libpayload: Check for completion more often in ehci_set_periodic_schedule.
    
    This function was using mdelay in a loop to check for the completion of an USB
    controller operation. Since we're busy waiting anyway, we might as well wait
    only 1 us before checking again and potentially seeing the completion 999 us
    earlier than we would otherwise.
    
    Change-Id: I177b303c5503a0078c608d5f945c395691d4bd8a
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2522
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 1cca340942957009ad74e24ef04bdd5eb44aabaf
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 26 19:21:39 2013 +0200

    Use defines for some i82801ex/gx registers
    
    Change-Id: I0069ec26278b82d61ce5bcfb94d77647dfd3254b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/2530
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8f4647a24bf19a96531af9905b23ae8a2fc2675a
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Feb 27 21:00:01 2013 +0100

    ARMv7: drop special handling for stages.c
    
    This is a leftover from when we were debugging
    this code. Let's make it easier to understand.
    
    Change-Id: Ia3d0ab1504ff9dd9634d5f393d3c59fe1e43a0c0
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2543
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fd611f9c2c8c751069c6cd1634a3e3e523ff098b
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Feb 27 23:45:20 2013 +0100

    Drop CONFIG_WRITE_HIGH_TABLES
    
    It's been on for all boards per default since several years now
    and the old code path probably doesn't even work anymore. Let's
    just have one consistent way of doing things.
    
    Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2547
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9c29cfae8cc6214478a0a555e6901779eb19ef54
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Feb 27 20:24:11 2013 +0100

    Fix microcode selection code
    
    The ARM CPUs we know of don't have CPU microcode updates,
    so don't show the selection in Kconfig.
    
    Also simplify (and fix) the microcode selection in the Makefile
    that would try to include microcode even though none is available.
    
    Change-Id: I502d9b48d4449c1a759b5e90478ad37eef866406
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2540
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit eeb36326b9402aaa009c0a672c3b3ecb80300297
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Feb 27 10:12:03 2013 -0800

    Google/snow: update the GPIO emulation.
    
    Add two more GPIOs (total 6) as needed by the Google Snow laptop.
    These are faking out settings for now. This code is tested and working.
    
    Change-Id: I2077ffb8b85958eefdf54e19763d57cc1178ce89
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2538
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit fc14874352a07a11d91f59ae24e0b162b85821c8
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Wed Feb 27 15:21:21 2013 +0100

    Persimmon: remove HDMI Audio, PCI device 00:01.1 from devicetree.cb
    
    Commit 8487229b (Persimmon doesn't have HDMI so the GNB HD Audio should be
    disabled.) turned off the device in AGESA.  Now remove it from
    devicetree.cb, too.  This prevents the following boot message:
    
    PCI: Left over static devices:
    PCI: 00:01.1
    PCI: Check your devicetree.cb.
    
    Also clarify the line's comment a bit for the Fam14 boards which still
    retain this device (to counter the loss of information ;-).
    
    Change-Id: Ib671ed2e0d04bdef2869e8d70208d6e55cdea3fd
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2537
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit fdfd89f21326f13a279b37abfa05313434d48ac9
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Feb 27 16:38:38 2013 +0800

    selfboot: Report correct entry point address in debug message.
    
    Entry point in payload segment header is a 64 bit integer (ntohll). The debug
    message is currently reading that as a 32 bit integer (which will produce
    00000000 for most platforms).
    
    Change-Id: I931072bbb82c099ce7fae04f15c8a35afa02e510
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2535
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 62f100b02888c2de21d61caf5d850f1184e8be1a
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Nov 7 12:27:29 2012 -0600

    smm: Update rev 0x30101 SMM revision save state
    
    According to both Haswell and the SandyBridge/Ivybridge
    BWGs the save state area actually starts at 0x7c00 offset
    from 0x8000. Update the em64t101_smm_state_save_area_t
    structure and introduce a define for the offset.
    
    Note: I have no idea what eptp is. It's just listed in the
    haswell BWG. The offsets should not be changed.
    
    Change-Id: I38d1d1469e30628a83f10b188ab2fe53d5a50e5a
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/2515
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit da3087f67d516350249779745927861c4da2173d
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Mon Nov 5 17:25:52 2012 -0700

    Mainboard SMI S state handler was using the wrong defines
    
    The PCH register bit definition for sleep type is a little confusing.
    For example, 7 is S5. To make this simpler for the mainbaord developer,
    the mainboard smi sleep hander is called as mainboard_sleep(slp_typ-2).
    A couple mainboard SMI handlers were using the PCH define for slp_ty,
    so S3 code would be run for S5 and S5 code would never be run.
    
    Change-Id: Iaecf96bfd48cf00153600cd119760364fbdfc29e
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2514
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit db4f875a412e6c41f48a86a79b72465f6cd81635
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jan 31 17:24:12 2012 +0200

    IOAPIC: Divide setup_ioapic() in two parts.
    
    Currently some southbridge codes implement the set_ioapic_id() part
    locally and do not implement the load_vectors() part at all.
    This change allows clean-up of those southbridges without introducing
    changed behaviour.
    
    Change-Id: Ic5e860b9b669ecd1e9ddac4bbb92d80bdb9c2fca
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/300
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e614353194c712a40aa8444a530b2062876eabe3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 26 17:24:41 2013 +0200

    Unify setting 82801a/b/c/d IOAPIC ID
    
    Remove obscure local copy of writing the ioapic registers.
    
    Change-Id: I133e710639ff57c6a0ac925e30efce2ebc43b856
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/2532
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cf4ecfbe0183b633f362d88d9ebf18b6d846d3d2
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Feb 25 14:58:23 2013 +0100

    AMD Inagua: buildOpts.c: Adapt whitespace to coding style
    
    Mainly replace spaces by tabs and format comments correctly.
    
    Commit »Inagua: Indent and wihtespace cleanup« (f03360f3) [1] was
    unfortunately incomplete and also used spaces instead of tabs in
    some cases.
    
    Hopefully fix this once and for all to have a template for the
    other boards.
    
    [1] http://review.coreboot.org/547
    
    Change-Id: If15c797581dfefe2a57cd6f26e5bdac4cdd014dd
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2526
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 030902b774c672df217d9862fe73fade9c5265b1
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Tue Feb 26 12:37:22 2013 +0100

    AGESA: skip s3_resume.h if CONFIG_HAVE_ACPI_RESUME is disabled
    
    Commit »AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'« (22ec9f9a) [1]
    introduced a check throwing an error if S3_DATA_SIZE isn't big enough.
    
    However without CONFIG_HAVE_ACPI_RESUME the variable S3_DATA_SIZE
    isn't defined at all and compilation will fail if s3_resume.h is
    included.
    
    This patch makes it again possible turn off HAVE_ACPI_RESUME relatively
    easily in Parmer/Thatcher/Persimmon's Kconfig if you don't care about S3
    and don't want flash writes on every boot.
    
    [1] http://review.coreboot.org/2383
    
    Change-Id: I999e4b7634bf172d8380fd14cba6f7f03468fee3
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/2528
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 89ccc9285e3bdc3108e6d33dbe83ac9a4f048bc0
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Nov 1 18:46:05 2012 -0700

    libpayload: Add a pointer for user data on the USB MSC data structure.
    
    This is so the user of libpayload can attach data to the device which it can
    retrieve when the device is referred to later, for instance in usbdisk_remove.
    Otherwise, there's no direct connection from the usbdev_t structure to any
    bookkeeping in the host firmware.
    
    Change-Id: I36fe693b0dcd2098e359c26744e376e73bd3a723
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2513
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit 5e70766f14253f53190ddd49a544460c6bc1e528
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Tue Feb 26 15:56:11 2013 +0100

    AMD Fam14 boards: reduce unnecessary differences, 2nd attempt
    
    This patch reduces unnecessary differences between AMD Inagua, Persimmon,
    Union Station, South Station and Asrock E350M1. It's only cosmetical, but
    makes them a little bit easier to compare.
    
    This is the remainder of the original http://review.coreboot.org/2464,
    parts of which somehow got lost in a flurry of refactoring and splitting
    patches.
    
    Change-Id: I034228be9edaaa4122506763d7bb4158f8e0ec53
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2529
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 37ef52d44b3d527d6a4fb84eaffa4260b7521d4a
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Nov 21 01:52:27 2012 -0800

    libpayload: Correct a constant used for scanning for USB controllers.
    
    When checking to see if a PCI device exists at a particular bus/dev/func,
    libpayload was checking the vendor and device id fields together against a 16
    bit 0xffff. The two fields together are 32 bits, however, so the check was
    never true, and all dev/func combinations on a particular bus would be
    checked. That was slightly wasteful, but had relatively small impact.
    
    Change-Id: Iad537295c33083243940b18e7a99af92857e1ef2
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2521
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit b4523bb691037f78a0823299ef44c0e350e17759
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Nov 21 01:01:50 2012 -0800

    libpayload: Change the measurement interval for get_cpu_speed to 2 ms.
    
    The interval used to be about 55 ms which is excessively long. Coreboot only
    waits for 2 ms and gets a reasonable answer. That should be good enough for us
    as well.
    
    Change-Id: I4d4e8b25b6ba540c9e9839ed0bbaa1f04f67cce1
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/2520
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 502533f656d41632f3b8ec19c385e8efa8c264a6
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Mon Feb 25 10:39:48 2013 -0700

    Revert "AMD S3: Program the flash in a bigger data packet"
    
    This reverts commit ca6e1f6c04c96c435bdbf30a1b88cab0e5be330b.
    The packet size changes ends up corrupting the flash when booting
    Persimmon. I did figure out that the maximum number of bytes that
    can be sent is actually 8 bytes according to the sb800 spec. There
    must be additional problems beyond that since setting the packet
    size to 8 still causes problems.
    
    Change-Id: Ieb24247cf79e95bb0e548c83601dfddffbf6be59
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2509
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>

commit a96d24d672abfd2ce91caa2d762fdce3d67da600
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Mon Feb 25 10:41:28 2013 -0700

    AMD Southbridge: Add RTC init to lpc_init
    
    Adding RTC init code to the Southbridge initialization
    code in 'lpc_init'.  This initializes the RTC so that the
    Date Alarm register is set to a valid value (0x00) at
    startup.  By setting the Date Alarm register to 0x00,
    it does not get evaluated along with the seconds,
    minutes, and hours when running 'fwts s3'.
    Information about fwts (Firmware Test Suite) can be
    found here:
    https://wiki.ubuntu.com/Kernel/Reference/fwts
    
    This is the same edit made to the CIMX SB800 titled
    'AMD/Persimmon: Add RTC init to CIMX SB800' with commit
    ID: c4d3d which can be viewed here:
    http://review.coreboot.org/#/c/2488/
    
    Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2510
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 7675d8a481c6cbeba418f00f2eb733d904171a41
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sun Feb 24 15:09:11 2013 -0700

    Supermicro H8SCM & H8QGI: Fix printk warnings
    
    Changes:
     - Fix printk warnings for these two platforms by getting rid of the
       l length specifier and casting to unsigned int.
       This gets rid of a bunch of warnings like this one:
         agesawrapper.c:279, GNU Compiler 4 (gcc), Priority: Normal
         format '%lu' expects argument of type 'long unsigned int',
           but argument 3 has type 'UINT32' [-Wformat]
    
    Notes:
     - This is the same change that was done for Tyan s8226 in change:
       ddff32eb - http://review.coreboot.org/#/c/2451/
       Tyan S8226: Fix printk warnings
    
     - I have not tested this change on either of these platforms, I have
       just compiled it.
    
    Change-Id: I46b4c13fde7473cd2a084c7c7cb5c893f1731b02
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2502
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4f5a433a987faeed2cf21fbfca5d2604ef2d7edb
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sun Feb 24 14:12:32 2013 -0700

    AMD Southstation: Fix final warning
    
    Changes:
     - Add #include of delay.h in mainboard.c to pick up declaration of
       mdelay function.
    
    Notes:
     - This fixes this warning:
       mainboard.c:69, GNU Compiler 4 (gcc), Priority: Normal
       implicit declaration of function 'mdelay' [-Wimplicit-function-declaration]
    
    Change-Id: I72f333cd87215a7fc1e62d1d7ee4b2395444b03e
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2501
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4fc600442b578e3e79acb221040638ab52f600ed
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Jan 21 18:43:12 2013 +0100

    AMD Fam14 boards: Set P_BLK length to 6 for all processors
    
    Currently on for example on AMD Persimmon and ASRock E350M1 Linux
    complains, that the PBLK length is invalid [1].
    
            ACPI: Invalid PBLK length [0]
    
    Consequently, frequency scaling might not work correctly, though for
    these two boards it seems to work according to PowerTOP.
    
    Indeed, according to the ACPI specification [2], setting PBlockLength
    to 0 is only allowed if there is no PBlockAddress. Otherwise it has to
    be set to 6.
    
            18.5.93 Processor (Declare Processor)
    
            […]
    
            PBlockAddress provides the system I/O address for the processors
            register block. Each processor can supply a different such
            address. PBlockLength is the length of the processor register
            block, in bytes and is either 0 (for no P_BLK) or 6. With one
            exception, all processors are required to have the same
            PBlockLength. The exception is that the boot processor can have
            a non-zero PBlockLength when all other processors have a zero
            PBlockLength. It is valid for every processor to have a
            PBlockLength of 0.
    
    And that is exactly what Linux is checking in
    `drivers/acpi/processor_driver.c` [3].
    
            static int acpi_processor_get_info(struct acpi_device *device)
            {
            […]
                    /*
                     * On some boxes several processors use the same processor bus id.
                     * But they are located in different scope. For example:
                     * \_SB.SCK0.CPU0
                     * \_SB.SCK1.CPU0
                     * Rename the processor device bus id. And the new bus id will be
                     * generated as the following format:
                     * CPU+CPU ID.
                     */
                    sprintf(acpi_device_bid(device), "CPU%X", pr->id);
                    ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id,
                                      pr->acpi_id));
    
                    if (!object.processor.pblk_address)
                            ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No PBLK (NULL address)\n"));
                    else if (object.processor.pblk_length != 6)
                            printk(KERN_ERR PREFIX "Invalid PBLK length [%d]\n",
                                        object.processor.pblk_length);
                    else {
                            pr->throttling.address = object.processor.pblk_address;
                            pr->throttling.duty_offset = acpi_gbl_FADT.duty_offset;
                            pr->throttling.duty_width = acpi_gbl_FADT.duty_width;
    
                            pr->pblk = object.processor.pblk_address;
    
                            /*
                             * We don't care about error returns - we just try to mark
                             * these reserved so that nobody else is confused into thinking
                             * that this region might be unused..
                             *
                             * (In particular, allocating the IO range for Cardbus)
                             */
                            request_region(pr->throttling.address, 6, "ACPI CPU throttle");
                    }
            […]
            }
    
    This issue has proliferated to all AMD based boards so fix it for
    all of them by setting P_BLK length to 6.
    
    The DSDT of for example AMD Parmer and AMD Thatcher also set it
    to 6 everywhere so this solution is taken instead of setting the
    P_BLK system I/O base to 0 for all but the first processor which
    is how it is done for earlier AMD based boards.
    
    As note having to set this manually should not be needed and
    this should be autogenerated as done for most of the Intel boards
    and the AMD K8 based boards (`src/cpu/amd/model_fxx/powernow_acpi.c`).
    
    [1] http://www.coreboot.org/pipermail/coreboot/2013-January/073636.html
    [2] http://acpi.info/DOWNLOADS/ACPIspec40a.pdf
    [3] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/acpi/processor_driver.c;h=e83311bf1ebdaaaea1adbf2de1351cca907d3465;hb=5da1f88b8b727dc3a66c52d4513e871be6d43d19#l351
    
    Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
    • ASRock E350M1:
    Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
    • AMD Persimmon:
    Tested-by: Martin Roth <martin.roth@se-eng.com>
    Change-Id: Ie79fe4812532d124cc81747c75a4f3d88d00531c
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2189
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit a48918f75dda6f53ebdeb8c6371b6de6eb601205
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Wed Feb 20 21:12:37 2013 +0100

    Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) does
    
    USB ports 0-4 are handled by PCI devices 12.0 (OHCI) and 12.2 (EHCI). 12.1
    simply does not exist, so remove it from devicetree.cb.  While at it make the
    comment more detailed.  Likewise for all USB ports.
    
    USB device 14.6 is the Broadcom GbE MAC integrated in the Hudson-E1.  Add it
    to devicetree.cb.  It's used on Inagua (on), but not on Persimmon (off).
    
    Change-Id: Idea27b3390fa4470f2592e79fdd633d5a218b97b
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2463
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 12d60247ab071e775cad6dc7fe78c2d7bc9bab45
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Feb 21 15:54:50 2013 +0100

    AMD boards: ACPI DSDT: Use COREBOOT for the OEM Table ID field
    
    The DSDT header contains the fields OEMID and OEM Table ID. See
    for example ACPI specification 4.0a [1]
    
        5.2.11.1 Differentiated System Description Table (DSDT)
    
    on page 135. There Table 5-16 contains the descriptions.
    
    Field         Byte Length  Byte Offset  Description
    ===================================================
    OEMID         6            10           OEM ID
    OEM Table ID  8            16           The manufacture model ID.
    
    Currently in coreboot there is no common method what to put in
    these fields.
    
    Mostly Intel based boards populate it with "CORE  " ore "COREv4"
    and AMD based boards populate it with the board vendor and
    model number, abbreviated appropriately to fit into these fields.
    
    On most boards the proprietary vendor BIOS seems to leave these
    fields – displayed with `sudo dmidecode` under System Information –
    blank
    
        To Be Filled By O.E.M.
    
    and fill out the Base Board Information with the board vendor and
    model name.
    
    In [2] Jens Rottmann argues that the this is really just the table
    ID used for naming it and that »99% of the DSDT code is not board
    specific«.
    
    Both approaches seem to have their advantages, but using the
    second one, developers often seem to forget to update them (for
    example AMD Thather).
    
    The current situation is at least not optimal. and therefore at
    least unify the string in the OEM Table ID. If unifying the
    OEM ID is also a good idea this should be done too.
    
    If later on it should be decided that the board vendor and model
    should be used again, this should be somehow derived from
    Kconfig.
    
    The following command was used for the change [3].
    
        $ git grep -l '\/\* TABLE ID \*\/' | xargs sed -i '/TABLE ID/s/"\([^"]*\)"/"COREBOOT"/'
    
    This patch is split out from [2].
    
    [1] http://www.acpi.info/spec40a.htm
    [2] http://review.coreboot.org/#/c/2464/
    [3] http://stackoverflow.com/questions/5207838/sed-regex-matching-text-between-to-double-quotes-when-a-certain-text-appears-i
    
    Change-Id: Iec98c615ce37f928abc1b500eff5aa865d772cb2
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2472
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3faa2c77ed9103839002d1092424676790f07017
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Feb 20 15:46:46 2013 -0800

    google/snow: enable GPIO entries and CHROMEOS in building
    
    These were not separable or it would have been two CLs.
    
    Enable CHROMEOS configure option on snow. Write gpio support code for
    the mainboard.  Right now the GPIO just returns hard-wired values for
    "virtual" GPIOs.
    
    Add a chromeos.c file for snow, needed to build.
    
    This is tested and creates gpio table entries that our hardware can use.
    
    Lots still missing but we can now start to fill in the blanks, since
    we have enabled CHROMEOS for this board. We are getting further into
    the process of actually booting a real kernel.
    
    Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2467
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5f20b3522212f58b5e6858ff7028fb5a8e0879f5
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Feb 24 14:27:03 2013 +0100

    QEMU x86: northbridge.c: Name enabling device function to `northbridge_enable`
    
    Similar to the discussion on the coreboot list [1]
    
        Am Freitag, den 22.02.2013, 02:17 +0100 schrieb Peter Stuge:
    
        […]
    
        > Function names should try to be descriptive. "enable_dev" is not very
        > descriptive. I like "mainboard_enable" because it makes output such
        > as
        >
        > printk("%s: foo", __func__);
        >
        > useful.
    
    rename the function for the northbridge to `northbridge_enable`.
    
    [1] http://www.coreboot.org/pipermail/coreboot/2013-February/074549.html
    
    Change-Id: I262311ec511e394550330214621b8c37780c1d4e
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2496
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 30901baabcf1e26f3ba4cd32f5bd90eb1c6ed35c
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sat Feb 23 15:32:11 2013 -0700

    Persimmon: Fix warning, enable warnings as errors
    
     - Fix redefinition warning for SB_GPIO_REG50 introduced in commit
         fa8702cf - http://review.coreboot.org/#/c/2446/
         Persimmon: adapt PCIe reset code copied from Inagua to actually
                     match Persimmon
         The warning being fixed is:
            SB800.h:1491, GNU Compiler 4 (gcc), Priority: Normal
            "SB_GPIO_REG50" redefined [enabled by default]
    
     - Enable warnings as errors so no more warnings will be accidentally
         committed.
    
    Change-Id: Ib443b2bd2067f0b7d5f93f79170899a0f8f61060
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2494
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 528640d141193b4aaeb6b8956d4fbc7381df9eb3
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Feb 23 21:31:23 2013 +0100

    mainboard.c: Name enable_dev function uniformly `mainboard_enable`
    
    To reduce the differences between these file name the enabling
    device function in the directory `src/mainboard` uniformly
    `mainboard_enable` [1].
    
    Thanks to the awesome help of gnomon and BlastHardcheese in the
    IRC channel #sed on <irc.freenode.net>. gnomon came up with the
    following command to do the actual work.
    
        $ cd src/mainboard
        $ for f in */*/mainboard.c ; \
        > do src="$(awk '/\.enable_dev = /{v=$NF; sub(/,$/,"",v); print v}' "$f")" ; \
        > [[ -z $src ]] && continue ; \
        > printf '%s\n' "g/${src}/s/${src}\([,(]\)/mainboard_enable\1/p" w | ed -s "$f" ; \
        > done
    
    `src/mainboard/digitallogic/msm586seg/mainboard.c` and
    `src/mainboard/technologic/ts5300/mainboard.c` had to be adapted
    manually as no comma was used separating the struct members.
    
    And with the following statement, gnomon is even more likable!
    
        My pleasure entirely.  Good luck with coreboot; I'm a big fan of the project.
    
    [1] http://www.coreboot.org/pipermail/coreboot/2013-February/074548.html
    
    Change-Id: Ife9cd0c2d9cc1ed14afc6d40063450553f06a6c6
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2493
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1fc7416545bde75d9cc401638f28ebfb751b663e
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Feb 23 21:11:15 2013 +0100

    Technologic TS5300: mainboard.c: Move { to next line
    
    This is coreboot’s coding style.
    
    Change-Id: I7441f2c1927a49a3b7171112b7798dae6b56cfb5
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2492
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bernhard Urban <lewurm@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1cd616082100f47dc2d6d73669c6aa2e5eb039ad
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 15:53:18 2013 -0800

    ARMv7: Simplify div64
    
    We don't need the overly complex optimized version, since
    we're only doing this in very few non-critical places.
    
    Also, add the div* files to the bootblock, they're needed
    if we do printk.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I83bd766d4b03b488326ade1c13b7c364a7119e7b
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2508
    Tested-by: build bot (Jenkins)

commit 14c2398ce936da3856ae64e97f976767f3c7669c
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sat Feb 23 19:33:19 2013 +0100

    Siemens SITEMP G1P1: mainboard.c: Rename `init` to `mainboard_init`
    
    This is the common way to name that function, so unify that.
    
    Change-Id: I8a01051bd304039662894b89eed53ce14dde98b6
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2491
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e533fdaa5902d228c4db694db390113b437a9777
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sat Feb 23 16:29:25 2013 -0700

    AMD f14 vendorcode: Fix warning
    
    Add brackets around initializer in #define for
    PCIE_DDI_DATA_INITIALIZER to fix the warning:
      PlatformGnbPcie.c:89, GNU Compiler 4 (gcc), Priority: Normal
      missing braces around initializer [-Wmissing-braces]
    
    This warning happens for Inagua and South Station
    
    Change-Id: I7d8f742dd8335b704b0493aa6e9eaebc3cc50b1e
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2495
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 49428d840323210433c96740545246296d65b3f2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 21 15:48:37 2013 -0800

    Add support for Google's Chromebook Pixel
    
    Ladies and gentlemen, I'm very happy to announce coreboot support for
    the latest and greatest Google Chromebook: The Chromebook Pixel.
    
    See the link below for more information on the Chromebook Pixel, and
    its exciting specs:
    http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel
    
    The device is running coreboot and open source firmware on the EC
    (see ChromeEC commit for more information on that exciting topic)
    
    Change-Id: I03d00cf391bbb1a32f330793fe9058493e088571
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2482
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 940095fe5e4181f1708ff2298f17f7056b8e18ff
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Wed Feb 20 21:24:20 2013 +0100

    AMD based boards: platform_cfg.h: Replace `_*BOARDNAME*_CFG_H_` with `_PLATFORM_CFG_H_`
    
    Reduce unnecessary differences between AMD based boards only
    using the file `platform_cfg.h` for configuration making them
    a little bit easier to compare.
    
    Inagua & co. mention the board name in several places which are really not
    that board specific.  Sometimes people even forget to change it:
    Union Station’s platform_cfg.h starts with "#ifndef _PERSIMMON_CFG_H_".
    Funny.  Change that to "_PLATFORM_CFG_H_" everywhere.
    
    The following command was used.
    
        $ find . -name platform_cfg.h | xargs sed -i '/_CFG_H_/s/_.*_/_PLATFORM_CFG_H_/'
    
    More boards seem to use that kind of naming (`git grep _CFG_H_`)
    but it is not certain that this will not break anything as for
    example the board AMD Dinar also has header files for
    configuration stuff for the north- and southbridge.
    
        $ git grep _CFG_H_
        […]
        src/mainboard/amd/dinar/platform_cfg.h:#ifndef _PLATFORM_CFG_H_
        src/mainboard/amd/dinar/platform_cfg.h:#define _PLATFORM_CFG_H_
        src/mainboard/amd/dinar/platform_cfg.h:#endif //_PLATFORM_CFG_H_
        src/mainboard/amd/dinar/rd890_cfg.h:#ifndef  _RD890_CFG_H_
        src/mainboard/amd/dinar/rd890_cfg.h:#define _RD890_CFG_H_
        src/mainboard/amd/dinar/rd890_cfg.h:#endif //_RD890_CFG_H_
        src/mainboard/amd/dinar/sb700_cfg.h:#ifndef _SB700_CFG_H_
        src/mainboard/amd/dinar/sb700_cfg.h:#define _SB700_CFG_H_
        src/mainboard/amd/dinar/sb700_cfg.h:#endif //_SB700_CFG_H
        […]
    
    Change-Id: Ida15fa6a7adfc770240ac30e795946000dae3f16
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2464
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit ac529b1e15a2872b6e2894b0661fb49b11c95169
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Fri Feb 22 13:18:31 2013 -0700

    AMD/Persimmon: Add RTC init to CIMX SB800
    
    Adding RTC init code to the Southbridge initialization
    code in 'late.c'.  This initializes the RTC so that the
    Date Alarm register is set to a valid value (0x00) at
    startup.  By setting the Date Alarm register to 0x00,
    it does not get evaluated along with the seconds,
    minutes, and hours when running 'fwts s3'.
    Information about fwts (Firmware Test Suite) can be
    found here:
    https://wiki.ubuntu.com/Kernel/Reference/fwts
    
    This was tested on a Persimmon but will apply to
    other mainboards as well.
    
    Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2488
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d6682e88afc31f0d05f74638c28f6cc60fa2ba69
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 21 15:39:35 2013 -0800

    Add support for Google ChromeEC
    
    Google ChromeEC is an EC with completely open source firmware.
    See https://gerrit.chromium.org/gerrit/gitweb?p=chromiumos/platform/ec.git;a=summary
    for the EC firmware source code (aka more information about the ChromeEC)
    
    This patch adds support for the ChromeEC on coreboot's side.
    
    Great thanks to the ChromeEC team for this amazing work. It's another
    important milestone towards a free and open firmware stack on modern
    hardware.
    
    Change-Id: Iace78af9d291791d2f5f80ccca1587b418738cec
    Signed-off-by: Stefan Reinauer <reinauer@coreboot.org>
    Reviewed-on: http://review.coreboot.org/2481
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 50f313c8b2cae372d3d3868940c445aeb221ec1e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Feb 22 20:19:20 2013 +0100

    */acpi_tables.c: Use ALIGN macro
    
    At the request of Paul Menzel, I reran an
    old classic of a coccinelle script:
      @@
      expression E;
      @@
      -(E + 7) & -8
      +ALIGN(E, 8)
    
      @@
      expression E;
      @@
      -(E + 15) & -16
      +ALIGN(E, 16)
    
    Change-Id: I01da31b241585e361380f75aacf3deddb13d11c3
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2487
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 12781422d5ee2afcfe8da6a3f1b4f6c9d257dec8
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Feb 21 14:03:47 2013 +0100

    nvramtool: reduce memory mapping
    
    Instead of trying to map the first megabyte, only map what is
    required to read the tables.
    
    Change-Id: I9139dbc8fd1dd768bef7ab85c27cd4c18e2931b3
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/2485
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit fbf078311f37ae392b1c97dd5271035f1a056486
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Feb 20 15:50:06 2013 +0800

    libpayload: cbfs: Fix CBFS max size calculation.
    
    Cherry-picking CBFS fix from http://review.coreboot.org/#/c/2292/
    
    For x86, the old CBFS search behavior was to bypass bootblock and we should keep
    that.  This will speed up searching if a file does not exist in CBFS.
    For arm, the size in header is correct now so we can remove the hack by
    CONFIG_ROM_SIZE.
    
    Change-Id: I286ecda73bd781550e03b0b817ed3fb567d6b8d7
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2458
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 58fd5e1d3d4153ae86a997fcc9b0cfc5fd85e4b7
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Feb 20 15:43:47 2013 +0800

    libcbfs: Fix legacy CBFS API, typos
    
    Pulling CBFS fix from libpayload: http://review.coreboot.org/#/c/2455/2
    
    get_cbfs_header expects CBFS_HEADER_INVALID_ADDRESS (0xffffffff)
    instead of NULL when something is wrong.
    Also, fix typo.
    
    Change-Id: I7f393f7c24f74a3358f7339a3095b0d845bdc02d
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2457
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 39d497d5cfe62457bcacdd3826663c544b8bab37
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 21 15:39:01 2013 -0800

    Update 3rdparty mark to latest repository
    
    Change-Id: Ied5515a332e3f2f9abbed1c015cad76f7bb4cd9f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2480
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 2872f4e946b5cc9ccad2b1b47cea18db95e3191d
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Feb 21 13:10:24 2013 +0100

    AMD Fam14 boards: Unify `acpi_table.c` by mainly using Inagua’s one
    
    There were just whitespace differences and three boards did not
    contain
    
        printk(BIOS_DEBUG, "alib\n");
        dump_mem(ssdt, ((void *)alib) + alib->length);
    
    which is enclosed `#if DUMP_ACPI_TABLES == 1` to dump the ACPI
    tables.
    
    Basically the whitespace in the license header in Inagua’s file
    was fixed and then the file copied over to the other directories.
    
    Change-Id: I23f73acad427b5ec14cf51651af67240871f7488
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2470
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alvaro G. <andor@pierdelacabeza.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 522b55638f98ba773aecd4ccd2b5a424d933aa59
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Feb 21 17:09:01 2013 +0100

    AMD boards: Fix typo `@brief` in comment
    
    The following command was used to correct the typo.
    
        $ git grep -l @breif | xargs sed -i 's/@breif/@brief/'
    
    Change-Id: If0b579279de3c41571b9cda643836f5748a752a2
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2473
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 824e192809e021b3cdee947a44b3a18d276bdb35
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Wed Feb 20 21:24:20 2013 +0100

    Persimmon: platform_cfg.h: Declare codec arrays as `static const`
    
    From ISO C99 standard: »The placement of a storage-class specifier
    other than at the beginning of the declaration specifiers in a
    declaration is an obsolescent feature.«
    
    Found at <http://www.approxion.com/?p=41>.
    
    Change-Id: Iee7878affb2a5d157a94763083689d75e8218b2f
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2474
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3138bb875c57c3962cd0ee00e0e297af1a315108
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Thu Feb 21 14:01:39 2013 +0100

    Persimmon: dimmSpd.c: Use spaces for alignment of if-predicate
    
    The relational operators in the if-predicate are aligned in all
    `dimmSpd.c` files so revert part of the change in
    
        commit 36abff1dc8e74beafa47ad83de17416681970916
        Author: Marc Jones <marcj303@gmail.com>
        Date:   Mon Nov 7 23:26:14 2011 -0700
    
            Cleanup Persimmon mainboard whitespace.
    
            Reviewed-on: http://review.coreboot.org/427
    
    to remove the incorrectly introduced tabs and to unify that. It
    might contradict the current coding style but it is even used in
    the latest code as seen in the following file.
    
         src/northbridge/amd/agesa/family15tn/dimmSpd.c
    
    Change-Id: Ib611267f99090d0830bdc2319527389f193ea1eb
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2471
    Reviewed-by: Alvaro G. <andor@pierdelacabeza.com>
    Tested-by: build bot (Jenkins)

commit cec4cfdb138dc87d2ef69d330d659e75636b51c7
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Feb 20 12:45:01 2013 +0100

    Persimmon: Indent comment
    
    This was overlooked in the following commit.
    
        commit 36abff1dc8e74beafa47ad83de17416681970916
        Author: Marc Jones <marcj303@gmail.com>
        Date:   Mon Nov 7 23:26:14 2011 -0700
    
            Cleanup Persimmon mainboard whitespace.
    
            Reviewed-on: http://review.coreboot.org/427
    
    Change-Id: If6bf4836b46077614a04c1e106c241a4f97da166
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2468
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alvaro G. <andor@pierdelacabeza.com>

commit df729d7778a7e5878fac5545883f68e42372456a
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Tue Feb 19 14:46:31 2013 +0100

    AMD Fam14 boards: dimmSpd.c: Set `iobase` to `SMBUS0_BASE_ADDRESS` instead of `0xB00`
    
    For AMD Inagua, the following two commits
    
        commit 01f7ab93359ae0fee5784d35effbcbe0b596df18
        Author: Kerry Sheh <shekairui@gmail.com>
        Date:   Thu Jan 19 13:18:36 2012 +0800
    
            Inagua: Synchronize AMD/inagua mainboard.
    
            Reviewed-on: http://review.coreboot.org/542
    
    and
    
        commit d91c9b7e3cb9fdaeb9399a21907996130f3120bb
        Author: efdesign98 <efdesign98@gmail.com>
        Date:   Thu Sep 15 10:59:55 2011 -0600
    
            AMD Inagua platform updates
    
            Reviewed-on: http://review.coreboot.org/136
    
    replaced the constant `iobase` is set to by the define `SMBUS0_BASE_ADDRESS` from `OEM.h`.
    
    Do the same for AMD Persimmon, South Station, Union station and ASRock E350M1.
    
    Change-Id: If095cd9d9b28b118b4072c7c9d345bf620b774c9
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2453
    Tested-by: build bot (Jenkins)

commit 22ec9f9a72955d2364061db72520b85602077414
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Feb 18 16:56:09 2013 +0800

    AMD S3: Introduce Kconfig variable 'S3_DATA_SIZE'
    
    Currently the size of the volatile storage for S3 reserved in the
    image is hardcoded to 32768 bytes. Make that configurable by
    introducing the Kconfig 'S3_DATA_SIZE'.
    
    As the storage space is needed for storing non-volatile, volatile and
    MTRR data, add a check if the size is big enough.
    
    Change-Id: I9152797cf0045c8da48109a9d760e417717686db
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2383
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit c8fadd9f465428cb2470d78c72b77766acb058d9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Feb 20 14:13:01 2013 -0800

    ARMV7: create a correct LB_SERIAL table entry
    
    If CONFIG_CONSOLE_SERIAL is set, and we can call the standard function
    and get a non-zero uart address, then we create an lb table entry.
    
    The code was mostly right, just needed a tweak.
    
    Change-Id: I5b36c7b4e580a23319b7ba92cc8ad61592b1757a
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2466
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit a8ae1c66f919a41c8756d0cdb09a77243d1121eb
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Feb 20 13:21:20 2013 +0100

    Whitespace: Replace tab character in license text with two spaces
    
    For whatever reason tabs got inserted in the license header text.
    Remove one occurrence of that with the following command [1].
    
        $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[        ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,'
    
    [1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt
    
    Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2460
    Tested-by: build bot (Jenkins)
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>

commit 7d75fbd223d097886dd441acb2ef0f7a4c3db36f
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Feb 20 13:40:14 2013 +0100

    Persimmon: Replace tab with space in address in license header
    
    The following commit was too eager replacing spaces with tabs.
    
        commit 36abff1dc8e74beafa47ad83de17416681970916
        Author: Marc Jones <marcj303@gmail.com>
        Date:   Mon Nov 7 23:26:14 2011 -0700
    
            Cleanup Persimmon mainboard whitespace.
    
            Reviewed-on: http://review.coreboot.org/427
    
    Fix that with the following command.
    
        $ git grep -l 'Floor, Boston, MA'$'\t''02110-1301 USA' | xargs sed -i 's/Boston, MA[         ]*02110-1301 USA/Boston, MA 02110-1301 USA/'
    
    Change-Id: Ia118a8c19d94ce1f1048280a0f1d49d447cfa2a7
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2461
    Tested-by: build bot (Jenkins)
    Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>

commit 836fd19aa812388ba78de7c330f7c0bd1b6788a8
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Feb 20 13:24:35 2013 -0800

    armv7: Don't let users set ram parameters that are fixed in hardware.
    
    The SDRAM base is fixed in hardware. It makes no sense to make it configurable.
    The TEXT start is a magic number that should also be fixed, not settable.
    
    Change-Id: Ie44cc5c8da1dc38fc00eb602c4a295b045ca5364
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2465
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 601b27596ffdf526adf5b41c1f8366a5fdddc554
Author: Ronald G. Minnich <rminnich@google.com>
Date:   Wed Feb 20 09:24:29 2013 -0800

    ARMV7: minor tweaks to inter-stage calling and payload handling.
    
    Payloads, by design, can return. There's lots of mechanism in the payload code
    to support it, and the chooser payload relies on it. Hence, we should not mark
    the function call in exit_stage as noreturn.
    
    Not all ARM have unified caches, and it's not always easy to tell what
    to do. So we are very paranoid. Before we call between stages, we
    should carefully flush the dcache to memory and invalidate the icache.
    This may be more than is necessary on all architectures but it
    doesn't really hurt for the most part.
    
    So compile cache management code into all stages, and call the
    flush dcache/invalidate icache from all stages.
    
    Change-Id: Ib9cc625c4dfd2d7d4b3c69a74686cc655a9d6484
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2462
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c9f35f5300c8c4a171fa7f8d1f35732e88563e7e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Feb 19 16:55:51 2013 -0800

    libpayload: Fix license headers
    
    Not only were these files checked in with the Chromium OS Authors
    copyright, but in addition they were wrongly licensed as GPL.
    Switch to 3-clause BSD (and, since we're changing it, fix copyright,
    too)
    
    Change-Id: I3656c1f4304d53e343d89bb7c909fd4b929249f4
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2456
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0fd0a054d46673e7375eb4808a3b66952fbd9ad3
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Feb 18 21:23:16 2013 -0700

    Tyan S8226: Fix incompatible pointer warning
    
    Fix warning:
      mptable.c:52, GNU Compiler 4 (gcc), Priority: Normal
      passing argument 3 of 'mptable_write_buses' from incompatible pointer type [enabled by default]
    
    mptable_write_buses is expecting a pointer to an int, so I changed the
    U8 isa_bus to an int to match.  A U8 doesn't make sense if the value could
    be greater than 255 - certainly unlikely, but possible since the value
    of isa_bus gets set to the maximum PCI bus number + 1.
    
    Change-Id: I7ea416f48285922d6cf341382109993fd3f6405c
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2450
    Tested-by: build bot (Jenkins)
    Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 510171e23bc6beaf502b0549e6ee446e47860715
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Feb 18 21:42:18 2013 -0700

    Tyan S8226: Fix integer truncated warning
    
    Fix Warning:
      sb700_cfg.c:129, GNU Compiler 4 (gcc), Priority: Normal
      large integer implicitly truncated to unsigned type [-Woverflow]
    
    The issue here was that an 8 bit value was being placed into a 2-bit
    bitfield.
    
        $ more src/vendorcode/amd/cimx/sb700/SBTYPE.h
        […]
        UINT32  AzaliaSdin0     :2;                     //6
        UINT32  AzaliaSdin1     :2;                     //8
        UINT32  AzaliaSdin2     :2;                     //10
        UINT32  AzaliaSdin3     :2;                     //12
        $ more src/mainboard/tyan/s8226/sb700_cfg.h
        […]
         *  SDIN0 is define at BIT0 & BIT1
         *   00 - GPIO PIN
         *   01 - Reserved
         *   10 - As a Azalia SDIN pin
         *  SDIN1 is define at BIT2 & BIT3
         *  SDIN2 is define at BIT4 & BIT5
         *  SDIN3 is define at BIT6 & BIT7
         */
        #ifndef AZALIA_SDIN_PIN
        #define AZALIA_SDIN_PIN              0x2A
        #endif
        […]
        $ more src/mainboard/tyan/s8226/sb700_cfg.c
        […]
        	sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN;
        […]
    
    The 8 bit value 0x2A (binary 00 10 10 10), was being used incorrectly
    – I believe the original intent of this value was to enable the SDIN
    pins 0, 1, & 2. Because it was getting truncated as it was put into
    AzaliaSdin0, this wasn't happening and only SDIN0 was being enabled.
    
    I am leaving only SDIN0 enabled at this point to as not change the
    actual behavior on the platform.
    
    Change-Id: Icaeb956926309dbfb5af25a36ccb842877e17a34
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2452
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ddff32eb8cc8271d486537a085ed64eff5de5365
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Feb 18 21:33:04 2013 -0700

    Tyan S8226: Fix printk warnings
    
    Fix 84 warnings all like this one:
    agesawrapper.c:289, GNU Compiler 4 (gcc), Priority: Normal
    format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'UINT32' [-Wformat]
    
    Fixed by getting rid of the l length specifier and casting to unsigned int.
    
    Change-Id: Ic143c1034f760fa5efb2220aa33861e399ddd708
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2451
    Tested-by: build bot (Jenkins)
    Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit f87855ceab7e735221c1b85ed405a0b47e329125
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Mon Feb 18 18:56:48 2013 +0100

    Inagua+children: fix simple copy & paste error in code to reset PCIe slots
    
    Looking at AssertSlotReset, the comments and all other case's it's
    obvious this is a simple copy & paste error where someone just forgot
    to change one occurrance of the GPIO nr. Also the AMD Inagua
    schematics show that GPIO02 is what they really meant.
    
    Also forward the fix to boards copied from Inagua (AMD South
    Station, Union Station, Asrock E350M1).
    
    Change-Id: I6b9a3d473245fa27604b2f148a730290277a88ed
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2445
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 46cb96bb887c88ab0c03dc83ebd6ba107a5d908c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Feb 19 17:59:21 2013 +0100

    libpayload: libcbfs: Fix legacy CBFS API, typos
    
    get_cbfs_header expects CBFS_HEADER_INVALID_ADDRESS (0xffffffff)
    instead of NULL when something is wrong.
    
    Also, fix typo.
    
    Change-Id: Ibe56c9eab3b9fdfc6d0b14bc848ca75f3a4fc2f1
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2455
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 82682d50ec8d0850020a57db1911f91748811a2e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 15 19:32:01 2013 -0800

    exynos5250: add uartmem_getbaseaddr() in uart driver
    
    Change-Id: I76545ad3fca3cc0997050253be77ea83b5d74cb2
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2423
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fdcef1ace9ee75f7db50fabcf200f9e699bfbba0
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 15 19:29:12 2013 -0800

    move uartmem_getbaseaddr() to generic uart header
    
    This moves uartmem_getbaseaddr() from an 8250-specific header to the
    generic uart header. This is to accomodate non-8250 memory-mapped
    UARTs.
    
    Change-Id: Id25e7dab12b33bdd928f2aa4611d720aa79f3dee
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2422
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6802dc8abe250abbe1b89532a9895b7c5d3f77f7
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 15 16:18:28 2013 -0800

    armv7/snow: add CPU and RAM resources via allocator
    
    This adds necessary device operations to add CPU and RAM resources.
    
    Change-Id: Ief8f66627ef37f4fa786bfc3f7899529d3e5b037
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2419
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 249cdc39431362241d154b6d091228e3c4c4e028
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 15 16:23:23 2013 -0800

    snow: add cpu_cluster and domain resources via devicetree.cb
    
    This patch will cause the resource allocator to actually set aside
    the memory resources using methods in the previous patch. The coreboot
    table output will include "RAM" entries (there were none before):
    
    coreboot memory table:
     0. 0000000040400000-00000000bff001ff: RAM
     1. 00000000bff00200-00000000bff00fff: CONFIGURATION TABLES
     2. 00000000bff01000-00000000bfffffff: RAM
    
    Change-Id: I5cd76e93fc232fdae1754253efb4e9269b3a20c0
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2420
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 11a7db3b570eb07759a7f4b5d8397be87518388d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Feb 16 20:16:34 2013 +0100

    romcc: Don't fail on function prototypes
    
    Instead, ignore them. One is as non-standard as the other
    and ignoring is more convenient since we don't need to
    guard prototypes with #ifndef __ROMCC_ all the time.
    
    Change-Id: I7be93a2ed0966ba1a86f0294132a204e6c8bf24f
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2424
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 70c85eab83564a9a5533afa16d4aa95416fb4424
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Feb 16 01:06:57 2013 +0100

    build system: Retire REQUIRES_BLOB
    
    REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory,
    builds failed when all files were configured to point to other sources.
    
    This change modifies the blob mechanism so that cbfs-files can be tagged as
    "required" with some specification what is missing.
    
    If the configured files can't be found (wrong path, missing file), the build
    system returns a list of descriptions, then aborts.
    
    Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2418
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit f57d0dce95e258e6c065ceac32b9ce0935a141cb
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Sun Feb 17 17:01:34 2013 +0800

    AMD S3: Change S3_VOLATILE_POS to S3_DATA_POS
    
    S3_DATA_POS defines address where the whole S3 data is stored.
    
    Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2438
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 832452a7ea71af1cba160fdb34c1856c7c9216fd
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Mon Feb 18 08:34:49 2013 -0700

    RTC: Use the correct index when setting the default month
    
    Change-Id: I947a8b7ccd6141f164d1e63f7b8f524efa6c00f2
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2442
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b313e90162fcc305178d26408533b183ce045965
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 15 17:50:20 2013 -0800

    armv7: init stack to 0xdeadbeef to detect stack overflows
    
    This adds a simple loop which initializes the stack to 0xdeadbeef
    which is used by checkstack().
    
    Change-Id: I8aecf7bfb1067de68c4080c1fcb7eefa28fd04a7
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2421
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 384ee9f1429db8543724e868b7ffd5fc7e2aa915
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Mon Feb 18 20:26:50 2013 +0100

    Persimmon: drop useless DDR3 voltage code copied from Inagua
    
    Inagua can use GPIOs 178,179 to switch VMEM to 1.5, 1.35 or 1.25 V,
    which it does according to data read from the SO-DIMM's SPD EEPROM.
    
    On Persimmon (according to DB-FT1 rev. D schematics) both GPIOs are
    unconnected, there is no way to change the 1.5 V DDR3 voltage (save
    unsoldering a resistor). The whole code copied over from Inagua is
    useless.
    
    Removed the code, instead a comment hints at Inagua, for people who do designs
    based on Persimmon but do have a way to change VMEM.
    
    The line ...->DDR3Voltage = VOLT1_5; is supposed to make the AGESA DDR3 code
    select the RAM timings for the actually supplied voltage instead of the
    hoped-for but unavailable lower voltage. I have no idea how to test this, but
    in any case it can't hurt.
    
    Change-Id: Id098e09418b665645814a6ee2d41a3bff72238ba
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2448
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 9fba303435be16d5eb66ef11ed52ad71cc00c459
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Mon Feb 18 20:13:27 2013 +0100

    Persimmon: disable APU PCIe port 3
    
    According to DB-FT1 rev. D schematics the APU PCIe lane 3 is unconnected.
    Reflect this fact in the mainboard code.
    
    Change-Id: Ic98f4a63ef971628df7fbf97f56b80ebe7cb8517
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2447
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit fa8702cf2a30f32a2d9918548276e1b7b6ec0d2a
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Mon Feb 18 19:40:33 2013 +0100

    Persimmon: adapt PCIe reset code copied from Inagua to actually match Persimmon
    
    Comparing Persimmon and Inagua schematics and Coreboot code show the PCIe reset
    code has been blindly copied even though it doesn't suit the Persimmon at all.
    
    The Inagua can employ GPIOs 21, 25, 02 to manually reset devices on APU PCIe
    lanes 0/1, 2, 3 respectively. (Appearently the motivation for this is to revive
    buggy PCIe gen1 devices which got confused by PCIe gen2 signal training.)
    
    However the Persimmon not only doesn't support this, it even needs these 3 pins
    for the PCI interface! Instead it uses GPIO50 to reset devices on lanes 0-2 all
    at once. Lane 3 is unconnected anyway.
    
    This patch adapts the Persimmon mainboard code according to the DB-FT1 rev. D
    schematics.
    
    Change-Id: I05a657d9bf8cc59acc4f5174eb20375165c860c7
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2446
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 686dc0d66b2c83898d8a9ad845cf908c4b8294d2
Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Date:   Mon Feb 18 17:26:01 2013 +0100

    Kconfig: string option doesn't work properly inside choice section
    
    At least not in menuconfig. Move it after the endchoice.
    
    Change-Id: I87d2f70e7c1fbe539cd78cb602a39335b2886d8d
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Reviewed-on: http://review.coreboot.org/2443
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 7b654a9702640c2d9fb8c37e4ae7f6b27ca949a0
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Feb 18 18:35:00 2013 +0800

    cbfstool: Fix compile warnings caused by incorrect data types.
    
    The "offset" in cbfs-mkpayload should be printed as type %lu
    instead of %d as `gcc` rightfully warns about.
    
        gcc -g -Wall -D_7ZIP_ST -c -o /srv/filme/src/coreboot/util/cbfstool/cbfs-mkpayload.o cbfs-mkpayload.c
        cbfs-mkpayload.c: In function ‘parse_fv_to_payload’:
        cbfs-mkpayload.c:284:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat]
        cbfs-mkpayload.c:296:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat]
    
    This warning was introduced in the following commit.
    
        commit 4610247ef1744ccabbcc6bfc441a3583aa49f7b5
        Author: Patrick Georgi <patrick@georgi-clan.de>
        Date:   Sat Feb 9 13:26:19 2013 +0100
    
            cbfstool: Handle alignment in UEFI payloads
    
            Reviewed-on: http://review.coreboot.org/2334
    
    Change-Id: I50c26a314723d45fcc6ff9ae2f08266cb7969a12
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2440
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 475d42a16c0a9ce3946c1ac2b3d20c32feec4fec
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Feb 18 11:56:13 2013 +0100

    cbfstool: Add `-Werror` to make all warnings into errors
    
    Ensure that no changes with warnings are committed. Although using
    `-Werror` is debatable [1][2].
    
    [1] http://blog.flameeyes.eu/2009/02/future-proof-your-code-dont-use-werror
    [2] http://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html
    
    Change-Id: I402f2d82dd4087d8a575b0a85305a02ef04bb537
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2441
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ca6e1f6c04c96c435bdbf30a1b88cab0e5be330b
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Sun Feb 17 17:27:46 2013 +0800

    AMD S3: Program the flash in a bigger data packet
    
    According to spi.c in src/southbridge/amd/agesa/hudson
    readwrite = (bytesin + readoffby1) << 4 | bytesout;
    We can see that Hudson limits the SPI programming data
    packet size as 15.
    
    We used to write data to SPI in dword mode. It didn't
    take full advantage of the data packet size. We need to
    leverage that to speed up programming time.
    
    Change-Id: I615e3c8e754e58702247bc26cfffbedaf5827ea8
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2306
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 178df1121d638650f5eed3210ee94da1981070ea
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Sun Feb 17 16:41:14 2013 +0800

    AMD S3: Fix typo vol*a*tile in southbridge Kconfig
    
    Change non-volitile to non-volatile.
    
    Change-Id: Idfc7db3b3dcf078f0f3134fc62679bed439a4fd2
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2437
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 92f03c0a063e842febf616641a0a9ff967dd2013
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sun Feb 10 14:53:35 2013 -0700

    AMD Family12h: Fix warnings
    
    Add needed prototypes to .h files.
    Remove unused variables and fix types in printk statements.
    Add #IFNDEFs around #DEFINEs to keep them from being defined twice.
    Fix a whole bunch of casts.
    Fix undefined pre-increment behaviour in a couple of macros.  These now
      match the macros in the F14 tree.
    Change a value of 0xFF that was getting truncated when being assigned
      to a 4-bit bitfield to a value of 0x0f.
    
    This was tested with the torpedo build.
    This fixes roughly 132 of the 561 warnings in the coreboot build
      so I'm not going to list them all.
      Here is a sample of the warnings fixed:
    
    In file included from src/cpu/amd/agesa/family12/model_12_init.c:35:0:
    src/include/cpu/amd/amdfam12.h:52:5: warning: redundant redeclaration of 'get_initial_apicid' [-Wredundant-decls]
    In file included from src/cpu/amd/agesa/family12/model_12_init.c:34:0:
    src/include/cpu/amd/multicore.h:48:5: note: previous declaration of 'get_initial_apicid' was here
    
    src/northbridge/amd/agesa/family12/northbridge.c:50:10: warning: no previous prototype for 'get_node_pci' [-Wmissing-prototypes]
    src/northbridge/amd/agesa/family12/northbridge.c: In function 'get_hw_mem_hole_info':
    src/northbridge/amd/agesa/family12/northbridge.c:302:13: warning: unused variable 'i' [-Wunused-variable]
    src/northbridge/amd/agesa/family12/northbridge.c: In function 'domain_set_resources':
    src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
    src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
    src/northbridge/amd/agesa/family12/northbridge.c:716:1: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat]
    
    In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
                     from src/northbridge/amd/agesa/family12/northbridge.c:38:
    src/vendorcode/amd/agesa/f12/AGESA.h:1282:0: warning: "TOP_MEM" redefined [enabled by default]
    In file included from src/northbridge/amd/agesa/family12/northbridge.c:34:0:
    src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition
    In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
                     from src/northbridge/amd/agesa/family12/northbridge.c:38:
    src/vendorcode/amd/agesa/f12/AGESA.h:1283:0: warning: "TOP_MEM2" redefined [enabled by default]
    
    src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetNumberOfComplexes':
    src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:99:19: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]
    src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfPcieEnginesList':
    src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:126:20: warning: operation on 'PciePortList' may be undefined [-Wsequence-point]
    src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfDdiEnginesList':
    src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:153:19: warning: operation on 'DdiLinkList' may be undefined [-Wsequence-point]
    src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetComplexDescriptorOfSocket':
    src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:225:17: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]
    
    src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c:246:1: warning: no previous prototype for 'PcieFmForceDccRecalibrationCallback' [-Wmissing-prototypes]
    
    In file included from src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c:58:0:
    src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h:120:5: warning: large integer implicitly truncated to unsigned type [-Woverflow]
    
    And fixed a boatload of these types of warning:
    src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress':
    src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:687:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:694:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:701:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:702:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:705:23: warning: assignment makes integer from pointer without a cast [enabled by default]
    src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:709:21: warning: assignment makes integer from pointer without a cast [enabled by default]
    
    Change-Id: I97fa0b8edb453eb582e4402c66482ae9f0a8f764
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2348
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 96508a794969f35f10e8a346c227dfa7a026e9ea
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Sun Feb 17 16:25:36 2013 +0800

    AMD S3: Include the s3_resume.h only when S3 is enabled.
    
    Change-Id: I9a6c4f61e5dda6665f92c8526bb26a458ee2b739
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2384
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 7b6945405a7c703bb371cab973238e0c15b07cdf
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Feb 15 08:13:29 2013 -0800

    libpayload: only compile drivers/serial.c on machines that use it.
    
    Create a new serial console variable, X86_SERIAL_CONSOLE
    which is only enabled when SERIAL_CONSOLE and ARCH_X86 are defined.
    
    Builds for x86 and ARM.
    
    Change-Id: I607253c418de015975a839e3c33577842885ec0c
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2412
    Tested-by: build bot (Jenkins)
    Reviewed-by: Gabe Black <gabeblack@chromium.org>

commit 802921562f2f9b94686b1464e994c761416ad88e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 15 15:20:32 2013 -0800

    exynos5250: clean out some stale IRAM-related config variables
    
    This cleans out some obsolete Kconfig variables pertaining to IRAM
    usage.
    
    Change-Id: Ie53f5f7204eadc3a3dddc739d2b4b6237242b198
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2417
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 882fdcf2271d385f1110c0f3737ceeb5e30d2861
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Feb 14 16:41:54 2013 -0800

    armv7/exynos5250: fix usage of _stack and _estack
    
    This patch fixes up the usage of stack pointer and regions.
    The current approach only works by coincidence, so this fixes a few
    things at once to get it into a working state and allow us to use
    checkstack() again:
    
    - Add a STACK_SIZE Kconfig variable. Earlier on it was evaluated to 0.
    
    - Assign _stack and _estack using CPU-specific Kconfig variables since
      it may reside elsewhere in memory (not necessarily DRAM).
    
    - Make the existing IRAM stack variables more useful in this context.
    
    Change-Id: I4ca5b5680c9ea7e26b1b2b6b3890e028188b51c2
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2416
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 1cf46a7bbf7881275ea74520e9e926abe18e5ffe
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 17:06:43 2013 -0800

    ARMv7: Drop u-boot type remains
    
    Just a mechanical cleanup.
    
    Change-Id: I0815625e629ab0b7ae6c948144085f1bd8cabfb5
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2408
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 37955a21d16e3626427f3685fdafe08297f9c67d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 16:58:00 2013 -0800

    Exynos5250: Drop unused file ehci-s5p.h
    
    Change-Id: I39014377af718766ef86c149e2d2da3d97eaa728
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2407
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit b97ee89684265e735e3da7bdcd7d19ee81fa1ae3
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Thu Feb 14 12:08:30 2013 +0100

    OT200: add CMOS support
    
    nvramtool works as expected.
    
    root@CHGM-DEV-OT200:~# /home/vis/nvramtool -a
    baud_rate = 19200
    debug_level = Emergency
    
    Change-Id: Ia25dc5b4f0ed3a2dd7cc67b7d3174db3a6eff70e
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/2382
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)

commit 8deb5c6e0fde0b326881c7684056fe9ec4f310e9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Feb 14 17:35:49 2013 -0800

    libpayload: Use the same type for 32 bit data in readl as in uint32_t.
    
    The compiler gets mad when the types are equivalent size but not necessarily
    interchangeable because of strict aliasing checks. Since uint32_t is likely to
    be used when trying to read 32 bit data, it makes sense for them to be the
    compatible.
    
    Signed-off-by: Gabe Black <gabeblack@google.com>
    
    Change-Id: If73d794866055dc026fc06d6268e692adac0f835
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2411
    Tested-by: build bot (Jenkins)
    Reviewed-by: Gabe Black <gabeblack@chromium.org>

commit 1a29c1e7665c22476b74d469952d7e689d475cdf
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Feb 14 15:26:09 2013 -0800

    libpayload: fix compiler flags
    
    lpgcc was unconditionally setting -m32.
    
    Most of the flags it sets in the common case are right, however: no need
    to duplicate them everywhere, and we only want to change the common ones
    in one place, so it would be a shame to duplicate _CFLAGS all over the place.
    
    So add another variable, _ARCHEXTRA, which can be used to add
    special flags to _CFLAGS. We onlu use it at present for the x86; this may
    change.
    
    This allows us to get through compiling on arm and x86.
    
    Change-Id: I12f1620982c4ee10f76b3953e4225f13db31531e
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2399
    Tested-by: build bot (Jenkins)
    Reviewed-by: Gabe Black <gabeblack@chromium.org>

commit 2cc105c741357e7dc13a456726456bdbb6fcb5e6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Feb 14 15:09:21 2013 -0800

    libpayload: get time to compile cross-arch
    
    Get rid of the nest of includes, and make separate sections
    for each architecture. Also gets rid of the "there's X86 and there's
    everything else" structure of this file.
    
    Change-Id: I4232f50f048fa05e911e5de3aa9ec1530931b461
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2397
    Tested-by: build bot (Jenkins)
    Reviewed-by: Gabe Black <gabeblack@chromium.org>

commit c1ee8641cb350de289fd77e9e9231bda46d6a386
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Feb 14 14:36:46 2013 -0800

    libpayload: make functions static that are unused outside memory.c
    
    The default_ functions in memory.c are only used to initialize a weak
    variable.  They should not be used outside memory.c. Make them
    invisible.
    
    Remove the declaration from libpayload.h. For real this time.
    
    Change-Id: Id54c1fd172c78748f01a958ce4065dd0eb53bbc3
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2394
    Tested-by: build bot (Jenkins)
    Reviewed-by: Gabe Black <gabeblack@chromium.org>

commit f2e10cb544996872298c95ed23241149e3eab418
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Feb 14 17:31:37 2013 -0800

    libpayload: Use an appropriate range of memory when looking for cb tables.
    
    These live at the bottom of memory on x86, but that's IO mapped on the exynos.
    The particular range used will likely need to be configurable, but this will
    make it work in one more case than it used to.
    
    Change-Id: I4d4963b9732cf538d00f8effb4398f30cbbde6aa
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2410
    Tested-by: build bot (Jenkins)
    Reviewed-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit ba1008e33f35a8c1174f76c8d0bdba0fec519561
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 17:10:39 2013 -0800

    Exynos: Drop dead code in cpu.h
    
    Change-Id: Ibb5fa27a0d45ddd8f57e8e8c28961d204e2ef1e3
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2409
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8bc58da8ac7b2d91b7a6571e622876346df6f4cd
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 16:56:05 2013 -0800

    ARMv7: straighten out reset code
    
    We don't need three different implementations.
    
    Change-Id: Ie7b5fa90794676ea38838454a33e8e9188428eb7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2406
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5dbf689b62367f5386441cdc35434f14b39ac17b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 16:35:47 2013 -0800

    Exynos5: Drop S5P directory and merge files
    
    s5p-common mostly contained duplicate files, drop the whole directory
    and merge the few pieces that we are using into exynos5-common.
    
    Change-Id: I5f18e8a6d2379d719ab6bbbf817fe15bda70d17f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2405
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 7512e4593ed535bdd1bc33a91dfb769566146a39
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 15:56:08 2013 -0800

    ARMv7: Drop sr32, and wait_on_value
    
    They're unused. Also drop some unused defines in system.h
    
    Change-Id: Ia5afc3a676a4a94787041430f05d08f333033c73
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2404
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 0663dfd3d5a64a0da3bf9114c0e8cb981d52871f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 15:55:07 2013 -0800

    ARMv7: Fix include file names in memset & memcpy
    
    We don't have asm/
    
    Change-Id: I7f80f47e9d7f457b7a5a64603c59b14d3b536a8c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2403
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 8a4ce28fc4b009d2ff1bd438b23545214c974a67
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 15:51:31 2013 -0800

    ARMv7: Drop more unused files
    
    Change-Id: I0dd83f96d2a9598e9677d1b0b114229de6724287
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2401
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2149ad3c9cf5c1f38ca9e217883855ef7e1e712a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Feb 14 15:14:58 2013 -0800

    libpayload: add a ldscript for arm
    
    I think this needs to be its own ldscript. I'm pretty sure this one
    is going to need some work however. Is libpayload PIC? That would be
    best if so.
    
    Change-Id: I44578d70dfa72de527af8901a86583c2a60130ec
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2398
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 5ae44ded5cf5b8b9e0337feb6aa5ea42cda828ca
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 15:50:53 2013 -0800

    Drop include/arch-generic/div64.h
    
    It's unused.
    
    Change-Id: Id67ca754ff7ad148ff1ecd4f1e5c986a4e7585a8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2400
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 8e7b3c458c176bcb9b72de94fe4c8794566b4555
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 14:43:42 2013 -0800

    Exynos: Drop unused include files
    
    Change-Id: Ib533938446a289167725f5beda77c2ee5236e8a5
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2395
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit a957b7ad21a72c4be3bb09efe6370ec3515c7074
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 13:39:25 2013 -0800

    ARMv7: drop multiboot support
    
    Multiboot is an x86 only thing. Drop support on ARM.
    
    Change-Id: I13fafa464a794206d5450b4a1f23a187967a8338
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2392
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0928eb342976e2bc759207ad4ec0ea28b3b71cd2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 13:38:38 2013 -0800

    Exynos: Drop duplicate copy of watchdog.h
    
    Change-Id: I4c9bfa9eb7708420dc42c16bc152d761d2bdfee3
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2391
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fc4823d2454fa158970da1ca49808fdb691923a6
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 13:42:55 2013 -0800

    ARMv7: Drop SKIP_LOWLEVEL_INIT
    
    It's not used.
    
    Change-Id: I713d60209815f0aad93f5d4d3afef9f825db427e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2393
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit f151a81f8b348bb0ec0f65259f1cc9a25880a97f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Feb 14 13:36:52 2013 -0800

    Exynos5250: Drop SHA implementation
    
    We don't need SHA in coreboot.
    
    Change-Id: I1985d5e2c74fac39ff9dcdba4c23bb34fa857ec7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2390
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit c2e8cf56757b72b963753848d46c7932445029d5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Feb 14 11:32:29 2013 -0800

    libpayload; put the ldscript into an arch-dependent directory path
    
    Since it's utterly architecture-dependent, put it in arch/x86.
    Avoid the temptation to make yet another directory with just one
    file in it. Fix the makefile to pick up the proper arch-dependent script.
    
    Change-Id: I21ea02551a97bdcbc38419714f3b38cf8335c178
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2389
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 7df4ec03035d0bbc6f206527164ac4839d29cd0b
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Feb 12 13:12:51 2013 +0100

    Chromebooks: mainboard.c: Do not spell Chromebook in CamelCase
    
    »Chromebook« is the official spelling [1]. So correct that with
    the following command.
    
        $ git grep -l ChromeBook | xargs sed -i s,ChromeBook,Chromebook,
    
    The incorrect spelling was only used for the chip name.
    
    [1] http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html#hp-pav
    
    Change-Id: I9c19f399a3e3d36bd644ec375822daa384a14961
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2370
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 835df770e37b42c9a842ffe1696689bc21ad90e1
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Feb 12 12:51:25 2013 +0100

    Google Butterfly: thermal.h: Align macro content
    
    Change-Id: I3729f9bf66fcd72fa8870bb56a9c253a7368c774
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2371
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 0aa37c488bf785466e0db9897805ebf287af48eb
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Feb 12 15:20:54 2013 -0800

    sconfig: rename lapic_cluster -> cpu_cluster
    
    The name lapic_cluster is a bit misleading, since the construct is not local
    APIC specific by concept. As implementations and hardware change, be more
    generic about our naming. This will allow us to support non-x86 systems without
    adding new keywords.
    
    Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2377
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 398e84c71a15b7db8c631bb5b17d1a1a60c91128
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Feb 13 20:00:49 2013 -0800

    armv7: don't write a forward entry in coreboot tables
    
    We don't seem to need it, and it currently confuses the payload.
    
    (credit to Gabe Black for this, I'm just uploading it)
    
    Change-Id: I4e3a60eceb9b24e3bc8e50db431c1a731d1cdbae
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/2385
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a86e4ba8bdc7fd45ab76697d32d4e95cf3116700
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Feb 12 15:37:12 2013 -0800

    snow: Set up MMU after DRAM is working
    
    This was omitted earlier while we were debugging DRAM code (0a5bc7f).
    It was likely broken due to inconsistent units earlier on. Now that
    things are cleaned up and working, let's add it back in.
    
    Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2379
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2d0b55bd6bfc2985950224dbca29668cc1aa7eba
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Feb 13 20:29:27 2013 -0800

    snow: remove superfluous printk's from romstage main
    
    These were left over from earlier debugging and are no longer
    needed. They don't indicate any status or useful info (other
    than which line of code has been executed). Error messages are
    available in case something needs attention.
    
    Change-Id: Ie09fac29c42908cb8924169e56d8927fb76f02da
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2386
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4aff4458f58398f54c248604694c7005294c1747
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Feb 12 14:17:15 2013 -0800

    sconfig: rename pci_domain -> domain
    
    The name pci_domain was a bit misleading, since the construct is only
    PCI specific in a particular (northbridge/cpu) implementation, but not
    by concept. As implementations and hardware change, be more generic
    about our naming. This will allow us to support non-PCI systems without
    adding new keywords.
    
    Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2376
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dc8259ce1d2e866f3133da49c1d6f4773f5698c1
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Feb 12 22:57:04 2013 -0800

    armv7/exynos: remove some stale files leftover from initial import
    
    This removes some files leftover from the initial port. Some are
    leftover from U-Boot and some were leftover from the skeleton code
    derived from x86.
    
    There's a bit more that we'll get in another sweep.
    
    Change-Id: I325793ecb902b3b9430dcf531714ce025d201de6
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2380
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b25208fc8bce4142c420afcacd3c16e649fa2a5c
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Feb 12 15:30:17 2013 -0800

    armv7: use start and size parameters in mmu_setup()
    
    mmu_setup() was originally written in U-Boot to utilize board-specific
    global data. Since we're trying to avoid that, we added start and size
    parameters so that board-specific info can be passed in via mainboard
    code. Let's start using it that way.
    
    Change-Id: I7d7de0e42bd918c9f9f0c177acaf56c110bf8353
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2378
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 1b6fecd64d40cae3693d5424a26b9f34e419fd06
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Feb 12 13:41:14 2013 +0100

    armv7: stages.c: Fix grammar: s,The is to,This is to,
    
    The comment introduced in
    
        commit 50c0a50ac6a3fa54ed1286e8b76f933701b6d053
        Author: David Hendricks <dhendrix@chromium.org>
        Date:   Thu Jan 31 17:05:50 2013 -0800
    
            armv7: unify stage hand-off routines
    
            Reviewed-on: http://review.coreboot.org/2254
    
    contained a typo, which is corrected now.
    
    Change-Id: I87f7cfa82fcd12b6961d3329e634b4c201cc047e
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2372
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fd72d5a838875d02277099eee065faed77d4eecb
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Feb 12 12:30:26 2013 +0100

    Google Butterfly: acpi/thermal.asl: Fix typo »The*re* is no …«
    
    The commit introducing support for the Google Butterfly Chromebook
    
        commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2
        Author: Stefan Reinauer <reinauer@chromium.org>
        Date:   Mon Feb 11 11:11:36 2013 -0800
    
            Add support for "Butterfly" Chromebook
    
            Reviewed-on: http://review.coreboot.org/2359
    
    contains the typo, which is corrected now.
    
    Change-Id: I932f4cd248cac71c3ede39a7da97162e791827cb
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2373
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 1236b842347c1b0671aa56ed80fa0278ded8d6cc
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Feb 12 10:32:00 2013 +0100

    Google Butterfly: gpio.h: Correct whitespace errors
    
    Correct some whitespace inconsistencies introduced in the
    following commit.
    
        commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2
        Author: Stefan Reinauer <reinauer@chromium.org>
        Date:   Mon Feb 11 11:11:36 2013 -0800
    
            Add support for "Butterfly" Chromebook
    
            Reviewed-on: http://review.coreboot.org/2359
    
    Change-Id: Ifeda7eb29ddf855cdfea41ddbd685441ede55756
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2374
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit d60bb4927a7af101245591253a439af7ee6f9aee
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Feb 12 12:38:20 2013 +0100

    Google Parrot/Butterfly: fadt.c: Align macros correctly
    
    The commits adding support for the Google Parrot Chromebook
    
        commit a7198b34ccf120df2a9e5b9f104812e96916ad08
        Author: Stefan Reinauer <reinauer@chromium.org>
        Date:   Tue Dec 11 16:00:47 2012 -0800
    
            Add support for Google Parrot Chromebook
    
            Reviewed-on: http://review.coreboot.org/2026
    
    and the Google Butterfly Chromebook
    
        commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2
        Author: Stefan Reinauer <reinauer@chromium.org>
        Date:   Mon Feb 11 11:11:36 2013 -0800
    
            Add support for "Butterfly" Chromebook
    
            Reviewed-on: http://review.coreboot.org/2359
    
    had macros in `fadt.c` which were not aligned correctly and did
    not adhere to the coding style which uses just one space after
    `#define`. Fix this and use tabs instead of spaces everywhere.
    
    Change-Id: I1422c57a3bdc2faa29d2a6e2064e4d3aeed0f1cb
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2375
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit d01d0368f492b84ea093875f918086a23bc0ec7a
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Jan 25 12:42:40 2013 +0800

    libpayload: New CBFS to support multiple firmware media sources.
    
    Upgrade CBFS in libpayload to use new media-based implementation from coreboot
    ( http://review.coreboot.org/#/c/2182/ ).
    
    Old CBFS functions (cbfs_find, cbfs_find_file, get_cbfs_header) are still
    supported, although the recommended way is to use new CBFS API.
    
    To migrate your existing x86 payload source:
    	- Change cbfs_find to cbfs_get_file
    	- Change cbfs_find_file to cbfs_get_file_content
    	- Prefix every CBFS call with a CBFS_DEFAULT_MEDIA argument.
    
    Ex, char *jpeg_data = cbfs_find_file("splash.jpg", CBFS_TYPE_BOOTSPLASH);
     => char *jpeg_data = cbfs_get_file_content(
    		CBFS_DEFAULT_MEDIA, "splash.jpg", CBFS_TYPE_BOOTSPLASH);
    
    The legacy setup_cbfs_from_{ram,flash} is also supported, although the better
    equivalent is to make a new media instance:
    	struct cbfs_media ram_media;
    	init_cbfs_ram_media(&ram_media, start, size);
    	char *data = cbfs_get_file_content(&ram_media, "myfile", my_type);
    
    Verified by being successfully linked with filo.
    
    Change-Id: If797bc7e3ba975d7e3be905c59424f7a93b8ce11
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2191
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 02ae0bf8feb554ab408a9129fd9fffd1dc4cf6aa
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Feb 9 15:45:02 2013 +0100

    build system: Don't run the full build system on "make clean"
    
    When running "make clean" the build system used to parse the entire
    build system. Besides costing time, it prevents cleaning the tree
    if a blobs-board is selected but blobs are not enabled.
    
    Instead, clean always removes all of $(obj) and .xcompile, while
    distclean additionally removes .config and the like.
    
    Besides cleaning up more completely (eg. dependency files), a side
    effect is that this also removes $(obj)/util, if it exists
    (default location for build tools).
    
    Change-Id: Ief6362460d4eb7edcb4b0a47ec76cb9a61bf3b86
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2338
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9a0001623839d62d50a59060d0b653df006653d1
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Feb 11 19:05:36 2013 -0800

    fix an error message in checkstack()
    
    The order of some printk arguments were reversed.
    
    Change-Id: I5e8f70b79050b92ebe8cfa5aae94b6cd1a5fd547
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2364
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ca3198f5d646847fe2bf66f4a7c9dcc2e8d7a179
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Feb 11 18:22:44 2013 -0800

    armv7: jump to ELF image using stage_exit()
    
    This is just to get us to the payload.
    
    TODO: Do we want to implement any of the stuff from the x86 version,
    such as copying coreboot to a new location?
    
    Change-Id: Ia0544f111d7a1189ebd92d0ba3e11448eabd6252
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2363
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7635a60ca848b50ff4a0ac85a667adc7151a5abf
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Feb 12 00:07:38 2013 +0800

    armv7: Add emulation/qemu-armv7 board.
    
    To simplify testing ARM implementation, we need a QEMU configuration for
    ARM. The qemu-armv7 provides serial output, CBFS simulation, and full
    boot path (bootblock, romstage, ramstage) to verify the boot loader
    functionality.
    
    To run with QEMU:
     export QEMU_AUDIO_DRV=none
     qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom
    
    Verified to boot until ramstage loaded successfully by QEMU v1.0.50.
    
    Change-Id: I1f23ffaf408199811a0756236821c7e0f2a85004
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2354
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bc64cae995ddab369289e19b41501df5dbc58751
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Feb 11 22:12:55 2013 +0100

    spi-generic.h: Adapt include guard
    
    Rename _SPI_H_ to _SPI_GENERIC_H_ to match recent file rename.
    
    Change-Id: I8b75e2e0a515fb540587630163ad289d0a6a0b22
    Reported-by: Peter Stuge <peter@stuge.se>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2360
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit d7bd4eb003f5b6a13943418ae0ac53248a2e34d2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Feb 11 11:11:36 2013 -0800

    Add support for "Butterfly" Chromebook
    
    We're happy to announce coreboot support for the "Butterfly"
    Chromebook, a.k.a HP Pavilion Chromebook.
    
    More information at:
    http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html
    
    This commit also includes support for the ENE KB3940Q embedded controller
    running on Quanta's firmware.
    
    Change-Id: I194f847a94005218ec04eeba091c3257ac459510
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2359
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Tested-by: build bot (Jenkins)

commit 4815913968a1077fa7e56d8ec226a9cf18c80ea9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Feb 11 20:56:46 2013 +0100

    build system: Mark clean-for-update phony
    
    build system hygiene, not known if this actually matters.
    
    Change-Id: Ic800a2acecff123fc2055047fab67df107ac43ab
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2356
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit bd5e1a0ff362b6f37dfd756f451db3b1630efddb
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Feb 11 12:08:58 2013 -0800

    Update 3rdparty mark to latest repository
    
    Change-Id: Iad3ee8eae9c3551a4078bd48c3f187e694ba6837
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2358
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5e11f849f77552acc01c6eb661f402d02afb61e8
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Feb 11 11:53:42 2013 -0800

    snow: fix high_tables_base calculation
    
    It was off by a few orders of magnitude. D'oh.
    
    Change-Id: I9c8a3d5bd9ce261f914cfc7d05d86a1c61519b81
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2355
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 600784e8b9d11dd1e1afc1918e6eda004ac69de4
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Thu Feb 7 17:30:23 2013 +0800

    spi.h: Rename the spi.h to spi-generic.h
    
    Since there are and will be other files in nb/sb folders, we change
    the general spi.h to a file name which is not easy to be duplicated.
    
    Change-Id: I6548a81206caa608369be044747bde31e2b08d1a
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2309
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8cc846897132f6d6baa49118005815aefb5f560f
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Feb 9 15:56:04 2013 +0100

    Intel: Replace MSR 0xcd with MSR_FSB_FREQ
    
    And move the corresponding #define to speedstep.h
    
    Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2339
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3b19cbae37ab340bd530e35412800a171733fda6
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Fri Feb 8 13:16:58 2013 -0700

    AMD/Persimmon: Enable the 2nd COM port
    
    The hardware is there, so turn it on.
    
    Change-Id: I40aff1e84a22a05599c62b9f0b20397df0a40b15
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2353
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ebae438bf25514fe058aa9262adfe6625786da43
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Sat Feb 9 13:08:03 2013 +0800

    crossgcc: Support hosts using non-GNU make as default make.
    
    On hosts using non-GNU make as default make program (ex, FreeBSD's default is
    BSD make and having GNU make as "gmake"), building acpica will fail. We should
    use the correct path of make $(MAKE).
    
    Verified to build on FreeBSD 9.0 with gcc 4.7 from ports. Note, the shipped gcc
    in FreeBSD 9.0 is 4.2.1 and needs more patches to remove -Wbad-function-case and
    -Wempty-body. That should be fixed in a future patch.
    
    Change-Id: Iacbf5a05e84a8a53d9d3e783a10131de603282c9
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2333
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 3d990ffc88f5d54f32de28cc6a2a87f490bd701a
Author: Konstantin Aladyshev <aladyshev@nicevt.ru>
Date:   Fri Jan 25 19:20:51 2013 +0400

    Supermicro H8QGI: Substract 1 from MMCONF range limit
    
    MMCONF space is defined by two config parameters:
    MMCONF_BASE_ADDRESS (0xF800 0000)
    MMCONF_BUS_NUMBER (64)
    
    Coreboot allocates 1MB per bus, so MMCONF limit should be:
    0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF
    
    Current code does not have (-1) component, this makes MMCONF limit
    equal 0xFC00 FFFF. Not 0xFC00 0000, because according to BKDG
    lower two bytes of MMIO limit always equal 0xFFFF:
    MMIOLimit = {MMIOLimitRegister[47:16], FFFFh}.
    
    Add (-1) to correct this issue.
    
    No functionality change has been experienced. The five times
    slower RAM speed compared to the proprietary vendor BIOS still
    remains.
    
    Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9
    Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/2193
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 96e3035a1f9f6ade63d31c4f5e6f806df609f5c1
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sun Feb 10 14:26:20 2013 -0700

    AMD SB900: fix warnings
    
    Add a prototype to a .h file
    Remove an unused file (GppHp.c) from the build by deleting it from the
      makefile. I left the file since this is vendorcode. This is the code
      for PCIe hotplug.
    Inside GppHp.c, make functions not called from outside static.
      This obviously isn't important since the file isn't used, but for
      the sake of the cleanup I thought I'd go ahead with it...
    
    This was tested with the torpedo build.
    
    This fixes these warnings:
    
    src/vendorcode/amd/cimx/sb900/Dispatcher.c: In function 'LocateImage':
    src/vendorcode/amd/cimx/sb900/Dispatcher.c:193:38: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    
    src/vendorcode/amd/cimx/sb900/Usb.c:740:1: warning: no previous prototype for 'XhciA12Fix' [-Wmissing-prototypes]
    
    src/vendorcode/amd/cimx/sb900/GppHp.c:65:1: warning: no previous prototype for 'sbGppHotPlugSmiProcess' [-Wmissing-prototypes]
    src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotPlugSmiProcess':
    src/vendorcode/amd/cimx/sb900/GppHp.c:76:5: warning: implicit declaration of function 'SbStall' [-Wimplicit-function-declaration]
    src/vendorcode/amd/cimx/sb900/GppHp.c: At top level:
    src/vendorcode/amd/cimx/sb900/GppHp.c:101:1: warning: no previous prototype for 'sbGppHotUnplugSmiProcess' [-Wmissing-prototypes]
    src/vendorcode/amd/cimx/sb900/GppHp.c:134:1: warning: no previous prototype for 'sbGppHotplugSmiCallback' [-Wmissing-prototypes]
    src/vendorcode/amd/cimx/sb900/GppHp.c: In function 'sbGppHotplugSmiCallback':
    src/vendorcode/amd/cimx/sb900/GppHp.c:158:5: warning: implicit declaration of function 'outPort80' [-Wimplicit-function-declaration]
    
    Change-Id: I5a1a20eeb81e1f4d59e3e3192f081e11d8506f56
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2349
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c52e1065df07c24606381efb7598b1d29dc625b1
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Sun Feb 10 21:20:39 2013 +0800

    AMD S3: Add missing erasing flash sector for saving MTRR register
    
    It has worked up to now because the region is already erased
    the first time the board boots, and every additional boot the
    same data is being written over the old data.(by Dave Frodin)
    
    Change-Id: Id334c60668e31d23c1d552d0ace8eb6ae5513e6b
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2304
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e07e253bc87d6a86e5fb7f62bb63438ae4f6c5ba
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Sun Feb 10 21:10:52 2013 +0800

    AMD S3: Change the hardcoded data size to macros.
    
    Change-Id: Ieefc4213a6dee9c399826b1daa98bbf4bc10d881
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2303
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e7c76b475c03ee7f907dbbef87ca7d755bcef6d1
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sun Feb 10 16:05:26 2013 -0800

    snow: make build script erase 192KB instead of 128KB
    
    This will make the build script wipe out more flash memory content.
    Our image is a bit bigger now that we're testing with payloads, so
    this is just added paranoia to prevent weird surprises caused by not
    flashing the full image.
    
    Change-Id: I31969922079e96886573d9d802266eb0052277cd
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2352
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5d994634a268d29b61c98f40f4793334078509c4
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sun Feb 10 15:50:20 2013 -0800

    armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP}
    
    RAMBASE and RAMTOP are leftovers from the x86 port and do not apply
    the same way on ARM platforms. On x86 they refer to the low memory
    region where coreboot tables reside.
    
    However on ARM we don't have such a region which is architecturally
    defined. So instead we'll use the CPU-defined DRAM base address and
    the mainboard-defined DRAM size.
    
    This also has the pleasant side-effect of fixing the coreboot tables
    to not clobber ramstage code...
    
    Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2351
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a40435af84c5cd2175b842ff0cbd9d1e909c2ce6
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Feb 8 13:49:10 2013 +0800

    armv7/snow: Remove unused modules in bootblock and romstage.
    
    For Exynos/snow, cpu_info and power modules and also some parts of
    the GPIO API (which require timer and pwm modules) are not used in the
    current bootblock. Clock init only needs to be used if early console
    is enabled.
    
    Now our bootblock is 22420 bytes with early serial console and 11192
    bytes without. Those include the 8KB BL1 region.
    
    Change-Id: I9c958dafb9cf522df0dcfbef373ce741aa162544
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2322
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0b153bdda97fad6033a1d5aea58af1dd9df6125d
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat Feb 9 17:24:17 2013 -0800

    exynos/snow: move SPI GPIO setup to mainboard bootblock code
    
    This moves GPIO setup from chip-specific SPI code to mainboard-
    specific bootblock code. This makes exynos_spi_open a bit more
    generic so it can eventually be used for any SPI channel. This
    also benefits CBFS since the user can set media->context to
    to any set of SPI registers.
    
    Change-Id: I2bcb9de370df0a79353c14b4d021b471ddebfacd
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2347
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0f7b400f2e3497cf37758f4b14040930bea22391
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat Feb 9 16:42:23 2013 -0800

    exynos/snow: set SPI clock rate in romstage main
    
    This moves the setting of SPI clock rate into romstage's main,
    which allows us to eliminate a bunch of dependencies from the
    bootblock (about 7KB worth).
    
    Change-Id: I371499bb4af6a6aa838294bc56f9dbc21864957a
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2346
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e50e3434709f1f37359eb3df25aded61fca76850
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat Feb 9 14:58:45 2013 -0800

    armv7/exynos5250: place .id between .start and bootblock main
    
    This places the .id section toward the lower region of the coreboot
    image, before the bootblock. It's easier for humans to find by dumping
    the image and it also eliminates ID_SECTION_OFFSET which is currently
    the upper bound on our image size.
    
    Change-Id: I7d737b901dac659ddf9aa437cee5dc32f1080546
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2345
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f5a302378aa062916b5838a81c26567b59f93a8f
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat Feb 9 14:53:47 2013 -0800

    armv7: make bootblock linker script more explicit
    
    This adds a .bl1 and .start symbol that is placed at the beginning
    of the .rom section.
    
    The goal is to move the .id section in between the reset vector and
    bootblock_main.
    
    Change-Id: Ie732ce656d697c059cc0fa40c844b39f53fc214c
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2344
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 74e27b419dc9da8ea7c7ceb9cc0ad203176d24f9
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat Feb 9 13:51:55 2013 -0800

    armv7/exynos: make BL1_SIZE_KB consistent with numbers used...
    
    The Kconfig variable indicates KB, but the number used was bytes.
    Let's just assume KB is correct for now.
    
    Change-Id: I910c126104f0222fc48b70a18df943f2afddeca3
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2341
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 644e83b0070c28ffa0f68ac1966df968b0a500d9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Feb 9 15:35:30 2013 +0100

    speedstep: Deduplicate some MSR identifiers
    
    In particular:
    MSR_PMG_CST_CONFIG_CONTROL
    MSR_PMG_IO_BASE_ADDR
    MSR_PMG_IO_CAPTURE_ADDR
    
    Change-Id: Ief2697312f0edf8c45f7d3550a7bedaff1b69dc6
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2337
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dbc6ca7aea6e2474c30b4c3892abe0b3055abf67
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Feb 9 15:26:47 2013 +0100

    romcc: Use default romcc flags for most boards
    
    Except for one board, the flags can be derived from CONFIG_MMX
    and CONFIG_SSE.
    
    Change-Id: I64a11135ee7ce8676f3422b2377069a3fa78e24d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2336
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f03d22efd7abe6870f1216bc6b1e07aaba446c84
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Feb 9 14:35:55 2013 +0100

    romcc: Don't use user overridable romcc flags for bootblock
    
    The bootblock is typically run before fpu/mmx/sse setup, so
    we can't rely on -mcpu=p4 and the like to increase the
    register space.
    
    bootblock_romccflags does that for SSE, but they're controlled
    separately.
    
    Change-Id: I2b0609ac18b2394a319bf9bbbee1f77d2e758127
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2335
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4610247ef1744ccabbcc6bfc441a3583aa49f7b5
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Feb 9 13:26:19 2013 +0100

    cbfstool: Handle alignment in UEFI payloads
    
    Tiano for X64 is much cleaner to start up when using higher alignments in
    firmware volumes. These are implemented using padding files and sections
    that cbfstool knew nothing about. Skip these.
    
    Change-Id: Ibc433070ae6f822d00af2f187018ed8b358e2018
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2334
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 408aefd17645a95a0b1cac23b0ca7ad9c9df6925
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Sat Feb 9 10:38:55 2013 +0800

    cbfstool: Fix crash on image without bootblock in end of ROM.
    
    On platforms with CBFS data filling end of ROM image without bootblock in the
    end (ex, ARM), calculation of "next valid entry" may exceed ROM image buffer in
    memory and raise segmentation fault when we try to compare its magic value.
    
    To fix this, always check if the entry address is inside ROM image buffer.
    
    Verified to build and boot successfully on qemu/x86 and armv7/snow.
    
    Change-Id: I117d6767a5403be636eea2b23be1dcf2e1c88839
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2330
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 1c270b155863e48a2b2a6d855c6b7ea2f38ef8c6
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 8 18:02:31 2013 -0800

    armv7: update coreboot tables for armv7
    
    This is a first-pass attempt at cleaning up the coreboot tables
    for ARM. The most noticable difference is that there is no longer
    both a high and a low table.
    
    Change-Id: I5ba87ad57bf9a697b733511182c0326825071617
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2329
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 896edc28af423cedbb6eab6d0a83c090e3fb2ef5
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 8 18:04:59 2013 -0800

    snow: do something useful in ramstage()
    
    This cleans up Snow's trivial ramstage, gives it a coreboot table
    address and calls hardwaremain().
    
    Change-Id: I84c904bcfd57a5f9eb3969de8a496f01e43bc2f6
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2328
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b73d904cff574bb8447c75457a07353a81100ad5
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 8 19:10:33 2013 -0800

    armv7/snow: add BL1_SIZE_KB and get rid of magic constants
    
    This adds a BL1_SIZE_KB config variable so that we can get rid of
    some magic constants.
    
    Change-Id: I9dbcfb407d3f8e367be5d943e95b032ce88b0ad0
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2332
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3001c5b69c85414e8d762610794dd0dafc3c1813
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 8 19:09:04 2013 -0800

    armv7: include $(obj)/config.h when building bootblock
    
    Explicitly including it allows us to get rid of some magic constants
    in the bootblock linker script.
    
    Change-Id: I095899babc997addce6b383f00e5ebf135e99d5e
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2331
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c146d668ef56c3cc21a1e2afd7df7776a3aed9e3
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 8 16:33:52 2013 -0800

    DEBUG_CBFS should not depend on TPM
    
    This seemed to have been introduced in fe422184.
    
    Change-Id: I4f9ecfbec42aa8c0bb8887675a3add8951645b98
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2327
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 223af0dc4480dbcf55802e879c723003909bf1e1
Author: Mike Frysinger <vapier@chromium.org>
Date:   Fri Feb 8 17:45:27 2013 -0500

    document Intel VMX locking behavior
    
    Add a comment explaining that the existing lock bit logic is correct
    and "as designed" even though the manual states otherwise.  This way
    people don't have to "just know" what is going on.
    
    Change-Id: I14e6763abfe339e034037b73db01d4ee634bb34d
    Signed-off-by: Mike Frysinger <vapier@chromium.org>
    Reviewed-on: http://review.coreboot.org/2326
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 22ae2b937856d6927216d88b7f61b7623eabdb8c
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Feb 8 08:48:20 2013 -0800

    VBE: Skip graphics mode setting for non-VGA devices
    
    This hit me when running the latest Qemu with coreboot:
    First the graphics OPROM is running, then an iPXE OPROM.
    The iPXE OPROM has no int10 support (obviously) so calling
    vbe_set_graphics() wipes the framebuffer information from
    the coreboot table.
    
    Change-Id: Ie0453c4a908ea4a6216158f663407a3e72ce4d34
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2325
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 882f7e35ea1dc2f6be4ba6c2529ed59915863e81
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Feb 8 09:38:49 2013 +0100

    console: Fix using CMOS for options
    
    Just a tiny mistake, but it made the console driver assume that
    CMOS data isn't available.
    
    Change-Id: I4e6f53e9ed59024de7b09333f82f0ce3235ef8f6
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/2323
    Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 69e432eedd72516343cbafd73bed5b10915de0bf
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Feb 7 18:19:23 2013 -0800

    oprom: fix compilation for Qemu target (and possibly others)
    
    Not sure why this didn't bite us earlier..
    
    src/device/oprom/realmode/x86.c: In function 'fill_lb_framebuffer':
    src/device/oprom/realmode/x86.c:272:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:274:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:275:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:276:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:278:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:280:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:281:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:283:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:284:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:286:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:287:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:289:13: error: dereferencing pointer to incomplete type
    src/device/oprom/realmode/x86.c:290:13: error: dereferencing pointer to incomplete type
    
    Change-Id: Ie3b0f731a7b995e954a26e745b07fc122088ca9f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2321
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 87d6550c1f2a902592be6604921a7f557c264168
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Feb 7 21:38:41 2013 +0800

    armv7/snow: Move clock initialization from bootblock to romstage.
    
    Exynos system clock can be initialized before RAM init, not necessary to be in
    the very beginning (boot block). This helps reducing bootblock dependency.
    
    Verified to boot on armv7/snow.
    
    Note: this patch was originally introduced in 2308, but there were
    some ordering issues so it was reverted.
    
    Change-Id: Ibc91c0e26ea8881751fc088754f5c6161d011b68
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2320
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b868d40830787ba5a92721d131c38165285b7795
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Feb 6 22:01:18 2013 +0800

    armv7: Use same console initialization procedure for all ARM stages
    
    Use same console initialization procedure for all ARM stages (bootblock,
    romstage, and ramstage):
    
    	#include <console/console.h>
    	...
    	console_init()
    	...
    	printk(level, format, ...)
    
    Verified to boot on armv7/snow with console messages in all stages.
    
    Change-Id: Idd689219035e67450ea133838a2ca02f8d74557e
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2301
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 580fa2bf316d4796e5ed76cbbd3e454479fb0688
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Feb 6 21:51:15 2013 +0800

    console: Only print romstage messages with EARLY_CONSOLE enabled.
    
    Revise console source file dependency (especially for EARLY_CONSOLE) and
    interpret printk/console_init according to EARLY_CONSOLE setting (no-ops if
    EARLY_CONSOLE is not defined).
    
    Verified to boot on x86/qemu and armv7/snow. Disabling EARLY_CONSOLE correctly
    stops romstage messages on x86/qemu (armv7/snow needs more changes to work).
    
    Change-Id: Idbbd3a26bc1135c9d3ae282aad486961fb60e0ea
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2300
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit f7fcb2056f2ddf151517366a4caf2b6c52b0d920
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Feb 7 13:41:56 2013 +0800

    console: Always allow setting "EARLY_CONSOLE" configuration.
    
    Early console should always be allowed to be turned on / off (for generating
    production and debug versions), and should not be enforced by "select" Kconfig
    rule.
    
    A new "DEFAULT_EARLY_CONSOLE" is introduced for devices to select if they
    prefer early console output by default.
    
    Verified Kconfig value on qemu/x86 (default y by CACHE_AS_RAM), snow/x86
    (default y by EXYNOS5 config), and intel/jarrell (default n).
    
    Change-Id: Ib1cc76d4ec115a302b95e7317224f1a40d1ab035
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2307
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 31bb2df5086bfde706378b1d80bd53fec69697a2
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Feb 7 19:30:40 2013 +0800

    exynos/snow: Configure UART peripheral during console initialization.
    
    For Exynos platforms, the UART component on pinmux must be first selected and
    configured. This should be done as part of UART console initialization.
    
    Note, that the current implementation hard-codes the device index as UART3,
    while the base port can be assigned to different device in Kconfig. This will be
    fixed later.
    
    Verified to work on armv7/snow.
    
    Change-Id: Ie63e76e2dac09fec1132573d1b0027fce55333a1
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2315
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit ad173ea70bee9ca0dc8eb5b79be8497a51dbe1c8
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Feb 6 21:24:12 2013 +0800

    console: Revise serial console configuration names.
    
    The console drivers (especially serial drivers) in Kconfig were named in
    different styles. This change will rename configuration names to a better naming
    style.
    
     - EARLY_CONSOLE:
            Enable output in pre-ram stage. (Renamed from EARLY_SERIAL_CONSOLE
            because it also supports non-serial)
    
     - CONSOLE_SERIAL:
            Enable serial output console, from one of the serial drivers. (Renamed
            from SERIAL_CONSOLE because other non-serial drivers are named as
            CONSOLE_XXX like CONSOLE_CBMEM)
    
     - CONSOLE_SERIAL_UART:
    	Device-specific UART driver. (Renamed from
    	CONSOLE_SERIAL_NONSTANDARD_MEM because it may be not memory-mapped)
    
     - HAVE_UART_SPECIAL:
            A dependency for CONSOLE_SERIAL_UART.
    
    Verified to boot on x86/qemu and armv7/snow, and still seeing console
    messages in romstage for both platforms.
    
    Change-Id: I4bea3c8fea05bbb7d78df6bc22f82414ac66f973
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2299
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 1c3187932d1399bef60788759f75a60179a6a474
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Feb 8 01:25:04 2013 +0100

    Revert "armv7/snow: Move clock initialization from bootblock to romstage."
    
    This reverts commit 9029f4b63f6d0e29bf1608e666cdb025de45ca24
    
    This patch needs to go at the end of the UART patch set. Sorry 'bout the confusion!
    
    Change-Id: I5702c7d6130daf95776f2c15d24e5d253691cefd
    Reviewed-on: http://review.coreboot.org/2319
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 9029f4b63f6d0e29bf1608e666cdb025de45ca24
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Feb 7 21:38:41 2013 +0800

    armv7/snow: Move clock initialization from bootblock to romstage.
    
    Exynos system clock can be initialized before RAM init, not necessary to be in
    the very beginning (boot block). This helps reducing bootblock dependency.
    
    Verified to boot on armv7/snow.
    
    Change-Id: Ic863e222871a157ba4279a673775b1e18c6eac0d
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2308
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 632d6fe3fc8b71e00438bddf972ff2936447a03c
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Feb 7 15:53:54 2013 +0100

    YABEL: use system {in,out}[bwl] on x86
    
    The prototypes that were recently defined only work for the
    internal implementations.
    
    Change-Id: Ib34bb75a0b882533da550b9cd17cd777c2463e02
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/2318
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 77608b21d3d745a10bba08fe316995a05f2371e2
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Feb 7 21:25:15 2013 +0800

    armv7/snow: Remove power_init from bootblock.
    
    The power_init is not required on Exynos 5250 (snow) in bootblock stage. To get
    a cleaner and faster bootblock, we can remove it.
    
    Note, power_init internally calls max77686 and s3c24x0_i2c, so both files are
    also removed.
    
    Verified to boot on armv7/snow.
    
    Change-Id: I5b15dfe5ac7bf4650565fea0afefc94a228ece29
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2317
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 60485a3e915ad44783d564e07d5ed6e7b74b277b
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Feb 7 21:15:42 2013 +0800

    armv7/snow: Remove redundant I2C initialization calls in bootblock.
    
    The I2C initialization (on component MAX77688) is already done in power_init, so
    we should not need an explicit call inside bootblock.
    
    Verified to boot on armv7/snow.
    
    Change-Id: I68c248a8b5fee4ab838b2fb708649e112559cc41
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2316
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5f83f6cb7a3f179482db54aaff38f23795dc1acf
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Feb 4 14:38:03 2013 +0800

    armv7: Clean up arm/snow bootblock build process.
    
    Remove duplicated / testing code and share more driver for bootblock, romstage
    and ramstage.
    
    The __PRE_RAM__ is now also defined in bootblock build stage, since bootblock is
    executed before RAM is initialized.
    
    Change-Id: I4f5469b1545631eee1cf9f2f5df93cbe3a58268b
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2282
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c720d8d5d419d8e9128392cd7ab90e3a3fca1d4b
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Feb 6 12:11:57 2013 +0800

    cbfs: Fix CBFS max size calculation.
    
    For x86, the old CBFS search behavior was to bypass bootblock and we should keep
    that.  This will speed up searching if a file does not exist in CBFS.
    
    For arm, the size in header is correct now so we can remove the hack by
    CONFIG_ROM_SIZE.
    
    Change-Id: I541961bc4dd083a583f8a80b69e293694fb055ef
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2292
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 439e0d2502bb0c38f7e7bf876dd5568331c6fe9c
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Feb 6 17:48:20 2013 +0800

    armv7: Clean up: remove deprecated SPL.
    
    "SPL" from U-Boot is deprecated by bootblock in coreboot/arm, so we don't need
    it anymore.
    
    Change-Id: Id16877075d0b870839a10160073ad70777a2af0a
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2297
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 23b5afe565b80387b2587c11493d0198794b1533
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Feb 5 15:24:54 2013 -0800

    snow: remove dead code from bootblock
    
    This attempts to clean out some dead code which was copy + pasted
    into Snow's bootblock.c file, along with some unnecessary headers.
    
    Change-Id: If9f157a52395a047c249a2a6385e0e8ddf310e59
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2291
    Tested-by: build bot (Jenkins)

commit da147d7ae30b64c94cde5648cccbb3ace3077060
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Feb 6 18:03:40 2013 +0800

    armv7: Clean up: replace hang() by hlt().
    
    hang() is the legacy function from U-boot and should be replaced by hlt() in
    coreboot.
    
    Change-Id: I0f390b1b6f9ff71487ea36cf16c462724b66d8ca
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2298
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 9efc42e85b4db0735145ddb561d62627f2c11003
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Tue Feb 5 21:06:21 2013 -0700

    AMD Fam14 - Fix warnings
    
    Added casts and a couple of #ifdefs to fix the warnings in the
    vendorcode/amd/agesa/f14 codebase.  This will allow us to re-enable
    'all warnings being treated as errors' in boards such as Persimmon
    that are using this code.  That change will follow.
    
    These are the warnings that are fixed by this patch:
    
    src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c: In function 'CopyHeapToTempRamAtPost':
    src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:219:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c: In function 'CopyHeapToMainRamAtPost':
    src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:372:30: warning: comparison between pointer and integer [enabled by default]
    src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c:381:33: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    
    src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c: In function 'ApUtilSetupIdtForHlt':
    src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c:863:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c:872:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    
    src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c: In function 'LoadMicrocode':
    src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c:211:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    
    src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c: In function 'HeapManagerInit':
    src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:167:52: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:183:14: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress':
    src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:669:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:676:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:683:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:684:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:687:23: warning: assignment makes integer from pointer without a cast [enabled by default]
    src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:691:21: warning: assignment makes integer from pointer without a cast [enabled by default]
    src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c:696:3: warning: return makes pointer from integer without a cast [enabled by default]
    
    In file included from src/mainboard/amd/persimmon/agesawrapper.h:30:0,
                     from src/northbridge/amd/agesa/family14/northbridge.c:36:
    src/vendorcode/amd/agesa/f14/AGESA.h:1132:0: warning: "TOP_MEM" redefined [enabled by default]
    In file included from src/northbridge/amd/agesa/family14/northbridge.c:34:0:
    src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition
    In file included from src/mainboard/amd/persimmon/agesawrapper.h:30:0,
                     from src/northbridge/amd/agesa/family14/northbridge.c:36:
    src/vendorcode/amd/agesa/f14/AGESA.h:1133:0: warning: "TOP_MEM2" redefined [enabled by default]
    In file included from src/northbridge/amd/agesa/family14/northbridge.c:34:0:
    src/include/cpu/amd/mtrr.h:34:0: note: this is the location of the previous definition
    
    Verified on persimmon.
    
    Change-Id: I1671b191c72dfc1d63ada41126ae3418bc8f86ae
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2293
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Steven Sherk <steven.sherk@se-eng.com>

commit 30b895f7e2809e1c624789f909e5cf0cc96f520d
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Wed Feb 6 18:04:40 2013 +0800

    crossgcc: Save the script itself when cross build is over.
    
    In case that the new toolchains don't work well, we can trace back
    and reproduce the old tools by checking the xgcc folder. It is useful
    when my team members need to get my old toolchains on their own host
    machines.
    
    Change-Id: I54e4bc6afcfbbf622165af6eae27bbb6efc2e8cc
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2247
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 315dec48ea6ae4f06dc3a0751dfa2ddf9ff55fba
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Feb 6 11:37:08 2013 +0100

    bootblock: Reduce register load
    
    The common part of the bootblock resets the nvram data if it's found
    to be invalid. Since that code is compiled with romcc in i386 mode,
    there's a shortage on registers.
    
    Try to reduce the strain by doing things smarter: cmos_write_inner
    is the same as cmos_write, just that it doesn't check if the RTC is
    disabled. Since we just disabled it before, we can assume that it is so.
    
    Change-Id: Ic85eb2a5df949d1c1aff654bc1b40d6f2ff71756
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2296
    Tested-by: build bot (Jenkins)
    Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

commit c5ff6487e65294aac4dccbf6b2a56ac518f982e2
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Feb 6 12:41:49 2013 +0800

    armv7: Prevent CBFS data overlapping bootblock.
    
    For arm/snow, current bootblock is larger than previously assigned CBFS offset
    and will fail to boot. To prevent this happening again in future, cbfstool now
    checks if CBFS will overlap bootblock.
    
    A sample error message:
    	E: Bootblock (0x0+0x71d4) overlap CBFS data (0x5000)
    	E: Failed to create build/coreboot.pre1.tmp.
    
    arm/snow offset is also enlarged and moved to Kconfig variable.
    
    Change-Id: I4556aef27ff716556040312ae8ccb78078abc82d
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2295
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 966e2dbb6537e9368514dfb3dfba24a8345c49bf
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Feb 6 12:25:27 2013 +0800

    cbfs: Revise debug messages.
    
    Some variables are using incorrect data type in debug messages.
    Also corrects a typo (extra 'x').
    
    Change-Id: Ia3014ea018f8c1e4733c54a7d9ee196d0437cfbb
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2294
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit d87d639e262544ec0b4f2fc06fa7d43e217c8333
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Feb 5 15:17:56 2013 -0800

    replace uchar and uint with standard types in generic i2c header
    
    Change-Id: Ie72985bb5291bcef2e837a2f4f2ec929a0c086ce
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2290
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0d4f97e27045209fdb9af452b013a6cfaebcaebc
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sun Feb 3 18:09:58 2013 -0800

    exynos/snow: Move core/memory clock-related and board ID code
    
    This patch moves ARM core and DRAM timing functions around to simplify
    the dependencies for system_clock_init().
    
    The original code was architected such that the system_clock_init()
    function called other functions to obtain core and memory timings.
    Due to the way memory timing information must be obtained on Snow,
    which entails decoding platform-specific board straps, the bottom-
    up approach resulted in having the low-level clock init code
    implicitly depend on board and vendor-specific info:
    
    main()
      ->system_clock_init()
        -> get_arm_ratios()
           -> CPU-specific code
        -> clock_get_mem_timings()
           -> board_get_revision()
              -> read GPIOs (3-state logic)
              -> Decode GPIOs in a vendor-specific manner
           -> Choose memory timings from module-specific look-up table
      ...then proceed to init clocks
    ...come back to main()
    
    The new approach gathers all board and vendor-specific info in a
    more appropriate location and passes it into system_clock_init():
    main()
      -> get_arm_ratios()
         -> CPU-specific code
      -> get_mem_timings()
         -> board_get_config()
            -> read GPIOs (3-state logic)
            -> Decode GPIOs in a vendor-specific manner
         -> Choose memory timings from module-specific look-up table
      -> system_clock_init()
    ...back to main()
    
    Change-Id: Ie237ebff76fc2d8a4d2f4577a226ac3909e4d4e8
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2271
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 94e230aa9319ca3421867efc080c985f9bcaaef4
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Feb 5 14:50:30 2013 -0800

    snow: use bootblock build class for I2C code
    
    This gets rid of a bunch of duplicate I2C code in the bootblock.
    
    Change-Id: I51f625a0f738cca4ed2453fbcb78092e4110bc7e
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2289
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 00e480e22d00088d4d6f8bb6b0a6b5c1f840f6a2
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Feb 5 14:43:52 2013 -0800

    snow: use bootblock build class for GPIO
    
    This gets rid of a bunch of copy + pasted GPIO code.
    
    Change-Id: I548b2b5d63642a9da185eb7b34f80cbebf9b124f
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2288
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6aaf856cd2f47d762962a8c06d73f3bb2e61e146
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Feb 5 14:51:46 2013 -0800

    exynos5250: Move the ID section again
    
    Move the ID section again due to bootblock bloat. So long
    as it's within the first 32K of our address space, we're good.
    
    TODO:
    1. Place ID section near start of ROM to avoid this issue.
    2. Reduce bootblock bloat.
    3. Make bootblock debugging a Kconfig option.
    
    Change-Id: I3f0764a3345a8cbbafcc15e4d06c38cd6327758c
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2287
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e87641840f1d7461d22e4297002db39544087c4a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Feb 5 13:46:49 2013 -0800

    cbfstool: Add support for 64bit UEFI
    
    Right now cbfstool only accepts firmware volumes with
    a x86 SEC core and refuses an x86-64 SEC core because
    some magic values and the extended PE header are
    different. With this patch, both IA32/x64 images are
    supported. (No check is done whether the mainboard
    actually supports 64bit CPUs, so careful!)
    
    This needs another patch to Tiano Core that switches
    to long mode after jumping to the 64bit entry point.
    Right now that code assumes we're already in 64bit code
    and the machine crashes.
    
    Change-Id: I1e55f1ce1a31682f182f58a9c791ad69b2a1c536
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2283
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 275fb63832158c0131575bcd2b6b441a0a1c5df1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Feb 5 13:58:29 2013 -0800

    Don't add another Kconfig special case for Tiano
    
    We don't need a special Kconfig variable anymore
    because the FV _is_ the payload, unlike with the
    old tianocoreboot implementation.
    
    Change-Id: I349b5a95783e4146e3ab7f926871188cf2021935
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2284
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 15a66a10b53c257b549f6c9efe6355e39556a8c5
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Feb 4 20:42:12 2013 -0800

    snow: use bootblock build class for UART code
    
    This gets rid of a bunch of copy + pasted code from Exynos UART
    files.
    
    Change-Id: I9fbb6d79a40a338c9fdecd495544ff207909fd37
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2286
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 4c2aafe586d5214409b4de0affb5f743477d2f1c
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Feb 4 20:40:47 2013 -0800

    exynos: de-duplicate UART header content
    
    Some header content got duplicated during the initial porting
    effort. This moves generic UART header stuff to exynos5-common
    and leaves exynos5250 #defines in the AP-specific UART header.
    
    Change-Id: Ifb6289d7b9dc26c76ae4dfcf511590b3885715a3
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2285
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 543a6824580331373a2d77694c23905dc7ca48a7
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Feb 4 15:39:13 2013 -0800

    cbfstool: support parsing UEFI firmware volumes
    
    This removes the hack implemented in http://review.coreboot.org/#/c/2280
    (and should make using 64bit Tiano easier, but that's not yet supported)
    
    Change-Id: Ie30129c4102dfbd41584177f39057b31f5a937fd
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2281
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c13e4bf3e16080993fb42399327501201c4f9f13
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jan 29 15:22:11 2013 +0800

    cbfstool: Use cbfs_image API for "add-*" (add-payload, add-stage, ...) commands.
    
    add-payload, add-stage, and add-flat-binary are now all using cbfs_image API.
    To test:
    	cbfstool coreboot.rom add-stage -f FILE -n fallback/romstage -b 0xXXXX
    	cbfstool coreboot.rom add-payload -f FILE -n fallback/pyload
    And compare with old cbfstool.
    
    Verified to boot on ARM(snow) and X86(qemu-i386).
    
    Change-Id: If65cb495c476ef6f9d90c778531f0c3caf178281
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2220
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5f3eb26d857628615e6c92180a2dc2213011dd09
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jan 29 10:24:00 2013 +0800

    cbfstool: Use cbfs_image api for "add" command.
    
    The "add" command is compatible with all legacy usage. Also, to support
    platforms without top-aligned address, all address-type params (-b, -H, -l) can
    now be ROM offset (address < 0x8000000) or x86 top-aligned address (address >
    0x80000000).
    
    Example:
    	cbfstool coreboot.rom add -f config -n config -t raw -b 0x2000
    	cbfstool coreboot.rom add -f stage -n newstage -b 0xffffd1c0
    
    Verified boot-able on both ARM(snow) and x86(QEMU) system.
    
    Change-Id: I485e4e88b5e269494a4b138e0a83f793ffc5a084
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2216
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f56c73f1e1c2b13c7b2b989fc44358138394cc68
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jan 29 09:45:12 2013 +0800

    cbfstool: Use cbfs_image API for "create" command.
    
    Usage Changes: To support platforms with different memory layout, "create" takes
    two extra optional parameters:
    
        "-b": base address (or offset) for bootblock. When omitted, put bootblock in
              end of ROM (x86  style).
        "-H": header offset. When omitted, put header right before bootblock,
              and update a top-aligned virtual address reference in end of ROM.
    
      Example: (can be found in ARM MAkefile):
        cbfstool coreboot.rom create -m armv7 -s 4096K -B bootblock.bin \
                 -a 64 -b 0x0000 -H 0x2040 -o 0x5000
    
    Verified to boot on ARM (Snow) and X86 (QEMU).
    
    Change-Id: Ida2a9e32f9a459787b577db5e6581550d9d7017b
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2214
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 215d1d7c9b8fdd94582bdec711e98111d1db5bb7
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jan 29 03:46:02 2013 +0800

    cbfstool: Use cbfs_image API for "locate" command.
    
    To support platforms without top-aligned address mapping like ARM, "locate"
    command now outputs platform independent ROM offset by default.  To retrieve x86
    style top-aligned virtual address, add "-T".
    
    To test:
    	cbfstool coreboot.rom locate -f stage -n stage -a 0x100000 -T
    	# Example output: 0xffffdc10
    
    Change-Id: I474703c4197b36524b75407a91faab1194edc64d
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2213
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 49fcd75564e8308d695cf44f54e0e92d693df69b
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jan 29 03:16:20 2013 +0800

    cbfstool: Fix incorrect CBFS free space by old cbfstool.
    
    Old cbfstool may produce CBFS image with calculation error in size of last empty
    entry, and then corrupts master header data when you really use every bit in
    last entry. This fix will correct free space size when you load ROM images with
    cbfs_image_from_file.
    
    Change-Id: I2ada319728ef69ab9296ae446c77d37e05d05fce
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2211
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c03d9b0c4387f7218e6c9c7d94cf86a5e2b3943e
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jan 29 02:38:40 2013 +0800

    cbfstool: Use cbfs_image API for "remove" command.
    
    To delete a component (file) from existing CBFS ROM image.
    
    To test:
    	cbfstool coreboot.rom remove -n fallback/romstage
    	# and compare with old cbfstool output result.
    
    Change-Id: If39ef9be0b34d8e3df77afb6c9f944e02f08bc4e
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2208
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0f8af71f1a40e8ae960ba616cb9a5bf14f10fb13
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jan 29 02:29:49 2013 +0800

    cbfstool: Use cbfs_image API for "extract" command.
    
    Change the "extract" command to use cbfs_export_entry API. Nothing changed in
    its usage.
    
    To verify, run "cbfstool coreboot.rom extract -f blah -n blah" and check if the
    raw type file is correctly extracted.
    
    Change-Id: I1ed280d47a2224a9d1213709f6b459b403ce5055
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2207
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3bb035b095a0e4144adfa55fa45b2332e3a6c7d5
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jan 29 02:15:49 2013 +0800

    cbfstool: Use cbfs_image API for "print" command.
    
    Process CBFS ROM image by new cbfs_image API.
    To verify, run "cbfstool coreboot.rom print -v" and compare with old cbfstool.
    
    Change-Id: I3a5a9ef176596d825e6cdba28a8ad732f69f5600
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2206
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit eab2c81949c8859892443c1e71449f391bc52d97
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jan 29 01:56:17 2013 +0800

    cbfstool: Add cbfs_image new CBFS image manipulation API.
    
    Current cbfstool implementation is relying on global variables to pass processed
    data, and the calculation of address is based on x86 architecture (ex, always
    assuming 0x0000 as invalid address), not easy to be used on platforms without
    top-aligned memory mapping. This CL is a first step to start a new cbfstool
    without global variables, and to prevent assuming memory layout in x86 mode.
    
    The first published APIs are for reading and writing existing CBFS ROM image
    files (and to find file entries in a ROM file).
    
    Read cbfs_image.h for detail usage of each API function.
    
    Change-Id: I28c737c8f290e51332119188248ac9e28042024c
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2194
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3cfacbf1961accff8670997368b403d8068ad94c
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jan 30 00:43:46 2013 +0800

    cbfstool: Add buffer management API.
    
    Many functions in cbfstool need to deal with a memory buffer - both location and
    size. Right now it's made by different ways: for ROM image using global variable
    (romsize, master_header); and in cbfs-* using return value for size and char**
    to return memory location.
    
    This may cause bugs like assuming incorrect return types, ex:
    	uint32_t file_size = parse();	// which returns "-1" on error
    	if (file_size <= 0) { ...
    And the parse error will never be caught.
    
    We can simplify this by introducing a buffer API, to change
    	unsigned int do_something(char *input, size_t len, char **output, ...)
    into
    	int do_something(struct buffer *input, struct buffer *output, ...)
    
    The buffer API will be used by further commits.
    
    Change-Id: Iaddaeb109f08be6be84c6728d72c6a043b0e7a9f
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2205
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f04e68e9e2a651b5db4d769d20d78d807426f109
Author: Steven Sherk <steven.sherk@se-eng.com>
Date:   Wed Jan 30 16:02:14 2013 -0700

    Add MMCONF resource to AMD fam15 PCI_DOMAIN
    
    This is a port of the following:
    commit d5c998be99709c92f200b3b08aed2ca3fee2d519
    
    	The coreboot resource allocator doesn't respect resources
    	claimed in the APIC_CLUSTER. Move the MMCONF resource to the
    	PCI_DOMAIN to prevent overlap with PCI devices.
    
    original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
        Signed-off-by: Marc Jones <marc.jones@se-eng.com>
        URL - http://review.coreboot.org/#/c/2167/
    
    Change-Id: I6e585d5cf0d46bd58337a6801fb0690ab2dd000c
    Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2248
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit ed08bcc12dddfd65edb38353530fec5fae17258d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Feb 4 19:15:06 2013 +0100

    Hook up corebootPkg as Tianocore payload
    
    This unplugs Stefan's PIANO project.
    
    Change Tianocore payload configuration to use corebootPkg.
    As argument you have to give it the COREBOOT.FD generated by
    the Tianocore build system.
    
    It automatically determines base address and entry point.
    
    Compression setting is honored (ie. no compression if you don't
    want), but corebootPkg currently assumes that coreboot is doing
    it. Loading a 6MB payload into CBFS without compression will fail
    more often than not.
    
    Change-Id: If9c64c9adb4a846a677c8af40f149ce697059ee6
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2280
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 63950f83f941c0a6747b5f22b1d7edafb67f5476
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Feb 1 23:51:40 2013 +0100

    AGESA boards: Fix grammar in description of `OemCustomizeInitEarly`
    
    The following command was used to correct the grammatical mistake.
    
        $ git grep -l 'This is the stub function will call' | xargs sed -i s,This is the stub function will call,This stub function will call, '{}'
        sed: -e Ausdruck #1, Zeichen 6: Nicht beendeter `s'-Befehl
    
    As this file seems to have been copied around a lot, it originally
    seems to have come with the following commit for AMD Persimmon and
    AMD Inagua.
    
        commit 69da1b676cd3f126b27a6fd3c23c557ac1a03961
        Author: Frank Vibrans <frank.vibrans@amd.com>
        Date:   Mon Feb 14 19:04:45 2011 +0000
    
            Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8.
    
    Change-Id: I2e6630a5172738b01e6def7062284f167e5508b1
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2268
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 5e272a4c4a8d9b00239d61da089e65fc4d6cfa8d
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Mon Feb 4 16:22:46 2013 +0100

    smbios: show CONFIG_LOCALVERSION in DMI bios_version
    
    If somebody makes use of CONFIG_LOCALVERSION show this
    user provided config string for DMI bios_version.
    
    As requested I have attached example output.
    
    CONFIG_LOCALVERSION=""
    CONFIG_CBFS_PREFIX="fallback"
    CONFIG_COMPILER_GCC=y
    ...
    
    root@OT:~# cat /sys/class/dmi/id/bios_version
    4.0-3360-g5be6673-dirty
    
    CONFIG_LOCALVERSION="V1.01.02 Beta"
    CONFIG_CBFS_PREFIX="fallback"
    CONFIG_COMPILER_GCC=y
    ...
    
    root@OT:~# cat /sys/class/dmi/id/bios_version
    V1.01.02 Beta
    
    Change-Id: I5640b72b56887ddf85113efa9ff23df9d4c7eb86
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/2279
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 7407f43c2b3273320ad8eadc5454d8f5375f2064
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Thu Jan 31 10:17:02 2013 -0700

    Family 12: Update for string portability
    
    Update function messages to be more portable by using
    the __func__ compiler command instead of hard coded
    function names.
    
    Change-Id: I3368a831770df1b8449eb0c97ae4bb24f6678efd
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2250
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit e133aab5b582cf98f28e9174931c88ebb95c5b06
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Wed Jan 30 16:00:43 2013 -0700

    Family 15tn: Update for string portability
    
    Update function messages to be more portable by using
    the __func__ compiler command instead of hard coded
    function names.
    
    Change-Id: Ib8ab97666340a9481f3ab71f0f347382e964994f
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2251
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 6eced514bfa66d0f52839e3952465ed929c27744
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Thu Jan 31 10:19:31 2013 -0700

    Family 10: Update for string portability
    
    Update function messages to be more portable by using
    the __func__ compiler command instead of hard coded
    function names.
    
    Change-Id: Idf479980e427bbf0399bdbc15045d80f402f6dbe
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2249
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 84014534860964d7b20fa681cd83151952dcc62b
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Wed Jan 30 14:12:01 2013 -0700

    Family 15: Update for string portability
    
    Update function messages to be more portable by using
    the __func__ compiler command instead of hard coded
    function names.
    
    Change-Id: Ie71fec39df5e7703d35d6505dc7d5b55179e2c7e
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2234
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 1cbabb00d9c4fb2f5a8e2e305ae3eb2e6c596897
Author: Steven Sherk <steven.sherk@se-eng.com>
Date:   Fri Feb 1 09:22:35 2013 -0700

    Add MMCONF resource to AMD fam15tn PCI_DOMAIN
    
    In the process of verifying change it was discovered the MMCONF
    default base address 0xA0000000 was set below mem_top 0xE0000000
    and bus number 256 wasn't a relistic number. The Kconfig defaults were
    changed to mirror fam15 defaults base address 0xF8000000 and bus
    number 64. Verified changes with boot to OS.
    
    This is a port of the following:
    commit d5c998be99709c92f200b3b08aed2ca3fee2d519
    
    	The coreboot resource allocator doesn't respect resources
    	claimed in the APIC_CLUSTER. Move the MMCONF resource to the
    	PCI_DOMAIN to prevent overlap with PCI devices.
    
    original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
        Signed-off-by: Marc Jones <marc.jones@se-eng.com
        URL - http://review.coreboot.org/#/c/2167/
    
    Change-Id: I47660061538f8889f528b9b880a82645074886a7
    Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2260
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 17aed0204881c0fd224c5d9d18545824ca4a1886
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Feb 4 10:46:33 2013 +0100

    ASRock 939A785GMH: Align comments of DSDT’s `IndexField`
    
    Remove superfluous spaces and use tabulators.
    
    Change-Id: Ic8b32b10c4e287a058a395e54214b9923ee48bdd
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2276
    Tested-by: build bot (Jenkins)
    Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit cb54f31e6801394fa65bf0d313655e73f45ef17d
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Feb 4 12:05:46 2013 +0100

    ASRock 939A785GMH: Align comments in DSDT header with tabs
    
    Change-Id: Ie64c231188310c4248ad0aaf9cdfcea12666bf2f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2275
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 6a427b9bc70aac945a0615df47e4ce11c4dc12ff
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Feb 4 11:38:01 2013 +0100

    Use tabs instead of spaces to align comments in DSTD header
    
    AOpen DXPL Plus-U and Intel XE7501devkit use »COREBOOT« as
    OEM Table ID.
    
    Unify the DSDT by aligning the comments in the DSDT header with
    tabs in accordance with the coding style [1].
    
    [1] http://www.coreboot.org/Development_Guidelines#Coding_Style
    
    Change-Id: I78e6aa8d0318b519b1df5e2178d387dc58e48323
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2278
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit d2e0e29b1623288b9345ab3591e81bb8e263f004
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Mon Feb 4 10:31:34 2013 +0100

    Intel based boards: Use tab instead of spaces to align comment in DSDT
    
    Mainboards using `COREBOOT` as their OEM Table ID in their DSDT
    header were copied from the same source and therefore had spaces
    instead of a tab to align that comment for that header field. These
    are mostly Intel based  boards.
    
    Fix that in accordance with the coding style [1].
    
    [1] http://www.coreboot.org/Development_Guidelines#Coding_Style
    
    Change-Id: I299b955930dbd50b9717e8ff141ce8f3fd534e5f
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2277
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit dada1259a2bdedff998bb0a11e1f22879f185d8d
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Feb 4 01:37:50 2013 -0800

    crossgcc: add armv7a-eabi to list of working toolchains
    
    Change-Id: Ibf221db4ca60d802b460d56f5fcca95ff49fc542
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2273
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 5be66730cf6d1a3814cd227d34f4265ffcf82ee1
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jan 29 10:30:17 2013 +0800

    cbfstool: Update example file.
    
    The syntax of cbfstool has been changed for a while (using getopt). Updated
    EXAMPLE file to show the right way to test cbfstool.
    
    Change-Id: I5cb41b76712d8c2403fffc9fdad83c61fb2af98c
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2215
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 18ee01ed05429df70d90133be0f0e0e4ff1daf51
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sun Feb 3 18:50:37 2013 -0800

    exynos5250: make lowlevel_init_c.c benign
    
    This file has mostly (but not entirely) been replaced by coreboot
    stage files. We'll keep it around for a bit longer as a reference,
    but in the meantime we'll stop compiling it as to avoid comptilation
    issues as we change other parts of the code.
    
    Change-Id: I669fb1e5a1517f35979590957d581bd33df53d29
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2269
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2354ef8869a287cf4c7de792c17485ad82b026cf
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sun Feb 3 20:47:38 2013 -0800

    exynos/snow: get rid of board-specific arbitration code
    
    Snow's AP, EC, PMU, and smarty battery share a bus. Both the AP and
    EC can act as a master, so to avoid conflicts an arbitration
    mechanism consisting of two GPIOs is used.
    
    By default, the AP "owns" the bus unless it is off (in which case
    the EC doesn't monitor the arbitration pins). This means the boot
    firmware does not need to worry about these lines. The payload may
    if it needs to communicate with the EC, though.
    
    In any case, board-specific bus arbitration logic does not belong
    in a low-level driver that is supposed to be generic for an entire
    CPU family. If the payload needs to talk to the EC, we'll deal with
    it there.
    
    Change-Id: I0774d4592af2b21b6ad668441532c5ceab988404
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2272
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit aa6701c090c013c1783b138e02277090615508ee
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sun Feb 3 19:13:36 2013 -0800

    exynos/snow: partial clean-up of snow bootblock using build class
    
    This removes some duplicate code from Snow's mainboard bootblock
    by utilizing the bootblock build class.
    
    Change-Id: I153247370a8c5127260082dcdca3ebdc5e104fb8
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2270
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ad7f98cb0163d0ef2b0e6f75d334cdbd6faf846c
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat Feb 2 17:02:36 2013 -0800

    exynos/s5p: Add helper function for reading a single MVL3 GPIO
    
    This adds a helper function to read only a single GPIO which uses
    3-state logic. Examples of this typically include board straps which
    are used to provide mainboard-specific information at the hardware-
    level, such as board revision or configuration options.
    
    This is part of a larger clean-up effort for Snow. We may want to
    genericise this for other CPUs in the future.
    
    Change-Id: Ic44f5e589cda89b419a07eca246847e9ce7dcd8d
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2266
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d58ba2add4b0ae955126ca746db39aa9fa98fd9f
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat Feb 2 16:57:11 2013 -0800

    add gpio.h for generic GPIO-related definitions
    
    This adds /src/include/gpio.h which currently contains generic GPIO
    enums for type (in/out/alt) and 3-state logic.
    
    The header was originally written for another FOSS project
    (code.google.com/p/mosys) and thus the BSD license.
    
    Change-Id: Id1dff69169e8b1ec372107737d356b0fa0d80498
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2265
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 10883945dcb089d7c4908eacaab7cb8d955657a3
Author: David Hendricks <dhendrix@chromium.org>
Date:   Sat Feb 2 20:19:58 2013 -0800

    exynos5250: remove CPU check from samsung_get_base_* macro
    
    The cpu_is_exynos5() macro seems broken at the moment, so skip it.
    The macro is superfluous and will probably be replaced eventually,
    but at least this will un-break usage sites.
    
    Change-Id: Ibd360cbfa18047ad8a3488d4f24c3fc4d7415eba
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2264
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit fe18792a0887b5ba1ce8e0c8f9f6f1911395552a
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Feb 1 01:09:24 2013 +0800

    armv7: Add 'bootblock' build class.
    
    For ARM platform, the bootblock may need more C source files to initialize
    UART / SPI for loading romstage. To preventing making complex and implicit
    dependency by using #include inside bootblock.c, we should add a new build class
    "bootblock".
    
    Also #ifdef __BOOT_BLOCK__ can be used to detect if the source is being compiled
    for boot block.
    
    For x86, the bootblock is limited to fewer assembly files so it's not using this
    class. (Some files shared by x86 and arm in top level or lib are also changed
    but nothing should be changed in x86 build process.)
    
    Change-Id: Ia81bccc366d2082397d133d9245f7ecb33b8bc8b
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2252
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit e876819975087654c1d3325928b044acf7f89b20
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Fri Feb 1 10:43:19 2013 -0700

    Fix libpayload xcompile xgcc path
    
    The libpaylaod xcompile script path to xgcc should look
    for coreboot/util, not libpayload/util.
    
    Change-Id: I565801549cdcdfcf55ecef1b543a982f969f435b
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2261
    Tested-by: build bot (Jenkins)
    Reviewed-by: Steven Sherk <steven.sherk@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2d5c0e6885baff21d345e63c7521a7899f9485ac
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Fri Feb 1 08:21:50 2013 -0700

    AMD/Persimmon: LVDS assignment was made to wrong DPx
    
    The LVDS is on DP0, not DP1.
    
    Change-Id: I724764d0f013e7a10d974a8716e075139982ded2
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2259
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>

commit c07fb15f17c7da73ec3bb97fe565f7740a879987
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Wed Dec 19 12:32:32 2012 +0400

    libpayload: add EHCI QH/qTD debugging
    
    Improve USB debugging for EHCI by adding dump_qh
    and enhacing dump_td to dump all queue chain and information.
    
    Change-Id: Ia8ecf19c6dac085cf9558bdf659a5e74ce332714
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/2053
    Tested-by: build bot (Jenkins)
    Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit d0ef387033c0f55dea4019475db06493e6fdb679
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Feb 1 15:27:39 2013 +0800

    armv7: Fix entry point in ram stage.
    
    Eliminate the warning message:
     ld: warning: cannot find entry symbol _start; defaulting to 040000000
    
    The "_start" from c_start.S is deprecated so we need to define entry
    point again in link description file.
    
    Change-Id: I174428faa2e7f08cd91fe96a53e6efea9dc3634e
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2258
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 332795cc5951c6d65badd2bbf3c79f6b63dbdbc2
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jan 28 15:53:34 2013 +0800

    cbfstool: Make endian detection functions to work without prior setup.
    
    The 'host_bigendian' variable (and functions relying on it like ntohl/htonl)
    requires host detection by calling static which_endian() first -- which may be
    easily forgotten by developers.  It's now a public function in common.c and
    doesn't need initialization anymore.
    
    Change-Id: I13dabd1ad15d2d6657137d29138e0878040cb205
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2199
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit d723c5b554786794217a92acb4ce0096bf924da8
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 31 17:49:22 2013 -0800

    clean-up for arch/armv7/Makefile.inc
    
    This removes a few lines which are obsolete or unneeded.
    
    We may want to do something with SMP eventually (can we use it for
    decompression?) but for now we'll assume non-bootstrap cores are idle
    until the OS does something with them.
    
    Change-Id: Iff6b196e008e803bcfd00e5de07cf471bd2357ea
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2257
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0a5bc7fb474a15b77747b2007340dd7589413d8d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jan 30 15:55:36 2013 -0800

    snow: make romstage init DRAM controller and call ramstage
    
    This is a first cut at a romstage. It sets up memory, although that
    needs some work; and finds and loads a ramstage.
    
    Change-Id: I02a0eb48828500bf83c3c57d4bacb396e58bf9a5
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2245
    Tested-by: build bot (Jenkins)

commit c9f26a169d854cf682f3d9d55124dce70b84620f
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 31 17:25:16 2013 -0800

    exynos5250: hard-code array index for memory timings
    
    Discovering memory timings is a bit complicated due to the need
    to obtain and decode board config. To make things worse, the imported
    code makes a mess of dependencies. Hard-code the memory timings
    for now to get us further along (the instability won't really matter
    until we're loading depthcharge anyway).
    
    Change-Id: I1f341ad597db0c31ed4ae6bc703fc22b6596a803
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2256
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ea60473b9dea41571e1eac9afe93f712d66e557a
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 31 17:22:50 2013 -0800

    exynos5250: #define the dram controller interleaving size
    
    Change-Id: Iab184aa85be68b6ca5107d278d2fe821e5b2e611
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2255
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d51557ade2a9f29cbb4e0f38d5a4920b42486168
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Thu Jan 31 12:14:46 2013 +0800

    lib: Prevent unaligned memory access and fix endianess in LZMA decode library.
    
    LZMA decode library used to retrieve output size by:
      outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
    
    'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address like
    src+5, and using that as integer pointer may fail on platforms like ARM. Also
    this will fail on systems using big-endian (outSize was encoded in
    little-endian).
    
    To fix this, reconstruct outSize in little-endian way.
    
    Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2246
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 05dccae75df4ed0c6a75867a89cf1a4055507e28
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jan 28 15:04:30 2013 +0800

    cbfstool: move flat-binary parsing to cbfs-mkpayload.
    
    The ELF parsing and payload building in add-flat-binary command should be
    isolated just like mkpayload and mkstage.
    
    Since the add-flat-binary command creates a payload in the end , move payload
    processing to cbfs-mkpayload.c.
    
    To test:
       cbfstool coreboot.rom add-flat-binary -f u-boot.bin -n fallback/payload \
    	-l 0x100000 -e 0x100020
    
    To verify, get output from "cbfstool coreboot.rom print -v":
       fallback/payload               0x73ccc0   payload      124920
       INFO:     code  (no compression, offset: 0x38, load: 0x1110000, length:..)
    
    Change-Id: Ia7bd2e6160507c0a1e8e20bc1d08397ce9826e0d
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2197
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 4d87d4e09b38d152425f060f088f3a44b7dacfcb
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jan 28 14:39:43 2013 +0800

    cbfstool: Add -v (verbose) output.
    
    Add -v (verbose) to every command, and allow printing debug messages.
    
    Revise logging and debugging functions (fprintf(stderr,...), dprintf...)
    and verbose message printing with following macros:
    	ERROR(xxx):	E: xxx
    	WARN(xxx)	W: xxx
    	LOG(xxx)	xxx
    	INFO(...)	INFO: xxx  (only when runs with -v )
    	DEBUG(...)	DEBUG: xxx (only when runs with more than one -v)
    
    Example:
    	cbfstool coreboot.rom print -v
    	cbfstool coreboot.rom add -f file -n file -t raw -v -v
    
    Normal output (especially for parsing) should use printf, not any of these
    macros (see usage() and cbfs_locate(), cbfs_print_directory() for example).
    
    Change-Id: I167617da1a6eea2b07075b0eb38e3c9d85ea75dc
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2196
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 7fb692bd867b271834be797029a6b4f72e4601bd
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Sun Jan 20 10:38:58 2013 -0700

    Fam15tn: Move SPD read from mainboards into wrapper
    
    Continuing with the mainboard cleanup for F15tn, move the functions
    to read the SPD from the mainboards for Thatcher and Parmer into the
    wrapper for the northbridge/amd/agesa/family15tn.
    
    Move the SPD address customization for the mainboard into the
    devicetree.cb file.
    
    Unrelated side note - Porting.h has an un-closed #pragma pack(1)
    that can cause confusing side-effects.  AGESA's structures all
    use this, but coreboot's don't.  Be sure to include the coreboot
    .h files BEFORE Porting.h is included, not after.
    
    This fix has been tested.
    
    Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2190
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>

commit 50c0a50ac6a3fa54ed1286e8b76f933701b6d053
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 31 17:05:50 2013 -0800

    armv7: unify stage hand-off routines
    
    This replaces the current stage-specific exit/entry functions with
    generic versions. Now all stages compile with stage_entry(), which
    is placed at .text.stage_entry.armv7, and stage_exit().
    
    Snow's ramstage files are also updated to avoid build breakage.
    
    Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2254
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 79e36d90608a929c33b655c6fb6376f33f332e6f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jan 30 14:29:34 2013 -0800

    Improve how our printk calls do_div by using constants.
    
    The do_div code has a nice optimization in it when it is called with
    constants. The current highly generalized use of it defeats those
    optimizations and causes trouble on ARM, resulting in a complex and
    buggy code path.
    
    Since we only need to print in bases 8, 10, and 16, do a minor
    restructuring of the code so that we call do_div with constants.
    If you need base 2, print in base 16 and do it in your head. :-)
    
    This fixes an ongoing problem with ARM, will not harm X86, and will
    help PPC should we ever want to support it again.
    Plus, I don't have to ever try to understand the div64 assembly and where
    it's going wrong :-)
    
    Change-Id: I6a480011916eb0834e05c5bb10909d83330fe797
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2235
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bc3abbbaf05123f87cee143845868bf6b95fdd3e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jan 30 15:05:19 2013 -0600

    armv7: don't hang on divide by zero
    
    People make mistakes. Hanging the box is not a good reason to kill the firmware,
    esp. since this is probably happening in a printk.
    
    The only issue with the recursive call to printk is that we may
    deadlock if we have locked something. But we can at least try.
    Hanging is certainly not what we want ...
    
    Change-Id: Ib3bc87bc395ae89e115cf6d042f4167856422ca1
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2233
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit b7e05358621344e0d777853c34960944d680f804
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jan 29 14:35:35 2013 -0800

    Exynos5250: Get DDR3 working by changing what is compiled and add a function
    
    This is a minor set of changes to get DDR3 going.
    
    Move compilation of DDR3 startup to the romstage. Fix a prototype that
    was missing a void. Remove a function that is overly flexible, and
    even though it is overly flexible only actually can handle one type of
    RAM. Mainboards only support one type of DRAM, so create a function
    to explicitly initialize the type of DDR we have -- DDR3.
    
    With these changes, and the previous changes, google snow is ready to run
    the ramstage.
    
    Change-Id: I37e0ab0d2dbc1dd121fb175386a46bc2fb1285e5
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2224
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 21d0fc0d3701d1c359fb4d4267383aeaa5886a7e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jan 30 13:41:03 2013 -0600

    Add a clean target to the run firmware (runfw) Makefile
    
    It's just good hygiene.
    
    Change-Id: Ie7d4557c1d0dcf7fc015852c4c9b2eae29c4acfc
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2232
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 7e494050d6ae7626a2eef06fb9bdd1d25e0e74c4
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Wed Jan 30 20:02:02 2013 +0800

    armv7: Add SPI driver for Exynos.
    
    The SPI flash driver for Exynos chipset.
    
    Verified to boot on snow/armv7.
    
    Change-Id: I7eef67a9c57f825d09f13ea44c2b59b54345fa7b
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2229
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6fe0cab205e131525efbfce4f59da344b1e76598
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Tue Jan 22 18:57:56 2013 +0800

    Extend CBFS to support arbitrary ROM source media.
    
    Summary:
    	Isolate CBFS underlying I/O to board/arch-specific implementations as
    	"media stream", to allow loading and booting romstage on non-x86.
    
    	CBFS functions now all take a new "media source" parameter; use
    	CBFS_DEFAULT_MEDIA if you simply want to load from main firmware.
    	API Changes:
    		cbfs_find => cbfs_get_file.
    		cbfs_find_file => cbfs_get_file_content.
    		cbfs_get_file => cbfs_get_file_content with correct type.
    
    CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM,
    the ROM may come from USB, UART, or SPI -- any serial devices and not available
    for memory mapping.
    
    To support these devices (and allowing CBFS to read from multiple source
    at the same time), CBFS operations are now virtual-ized into "cbfs_media".  To
    simplify porting existing code, every media source must support both "reading
    into pre-allocated memory (read)" and "read and return an allocated buffer
    (map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*"
    provides simple memory mapping simulation.
    
    Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA
    is defined for CBFS functions to automatically initialize a per-board default
    media (CBFS will internally calls init_default_cbfs_media).  Also revised CBFS
    function names relying on memory mapped backend (ex, "cbfs_find" => actually
    loads files). Now we only have two getters:
    	struct cbfs_file *entry = cbfs_get_file(media, name);
    	void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type);
    
    Test results:
     - Verified to work on x86/qemu.
     - Compiles on ARM, and follow up commit will provide working SPI driver.
    
    Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2182
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5fc64dca45b01556a9325bea0fb563d6f0d16f75
Author: Steven Sherk <steven.sherk@se-eng.com>
Date:   Tue Jan 29 15:46:05 2013 -0700

    Rename family15 pci northbridgeops functions.
    
    This is a port of the following
    commit 8a49ac7f808f76821e7d63070420cfd98f707c7c
    
        Rename fam14 pci northbridge ops functions.
    
        Clarify the northbridge ops function names.
    
    original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
        Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    
    Change-Id: Id7889bf02e2696220081251acdf695327267c796
    Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2225
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit f434058b042dc4023f5662cf5c07ec8d1d4f090f
Author: Steven Sherk <steven.sherk@se-eng.com>
Date:   Tue Jan 29 16:13:35 2013 -0700

    Rename family15tn pci northbridgeops functions.
    
    This is a port of the following
    commit 8a49ac7f808f76821e7d63070420cfd98f707c7c
    
        Rename fam14 pci northbridge ops functions.
    
        Clarify the northbridge ops function names.
    
    original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
        Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    
    Change-Id: Icda3ec58219baa177af3b1dce729c6ad1f744be8
    Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2226
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit e1ea5151def4b352e9f26be8f490983935867569
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Oct 5 23:05:48 2012 +0200

    libpayload: Update README with Git repository URL and directory location
    
    Change-Id: I3e068f5e6c1eb875df0885c0ce43a03082be31a5
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2228
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 58089e859dbaca7026cf61df3343073122a7c0a9
Author: Mike Loptien <mike.loptien@se-eng.com>
Date:   Tue Jan 29 15:45:09 2013 -0700

    Family 14: Update for string portability.
    
    Update function messages to be more portable by using
    the __func__ compiler command instead of hard coded
    function names.
    
    Change-Id: I6327c9769c2544bbc56155a2f89afd767487faf6
    Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2227
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit cc5b3446624cf85e13a8130a524e81360c5f4239
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jan 15 17:02:58 2013 -0800

    Project PIANO aka tianocoreboot
    
    This is a Tiano Core loader payload based on libpayload.  It
    will load a Tiano Core DXE core from an UEFI firmware volume
    stored in CBFS.
    
    Currently Tiano Core dies because it does not find all the UEFI services it needs:
    
    coreboot-4.0-3316-gc5c9ff8-dirty Mon Jan 28 15:37:12 PST 2013 starting...
    [..]
    Tiano Core Loader v1.0
    Copyright (C) 2013 Google Inc. All rights reserved.
    
    Memory Map (5 entries):
      1. 0000000000000000 - 0000000000000fff [10]
      2. 0000000000001000 - 000000000009ffff [01]
      3. 00000000000c0000 - 0000000003ebffff [01]
      4. 0000000003ec0000 - 0000000003ffffff [10]
      5. 00000000ff800000 - 00000000ffffffff [02]
    
    DXE code:  03e80000
    DXE stack: 03e60000
    HOB list:  03d5c000
    
    Found UEFI firmware volume.
      GUID: 8c8ce578-8a3d-4f1c-9935-896185c32dd3
      length: 0x0000000000260000
    
    Found DXE core at 0xffc14e0c
      Section 0: .text     size=000158a0 rva=00000240 in file=000158a0/00000240 flags=60000020
      Section 1: .data     size=00006820 rva=00015ae0 in file=00006820/00015ae0 flags=c0000040
      Section 2: .reloc    size=000010a0 rva=0001c300 in file=000010a0/0001c300 flags=42000040
    
    Jumping to DXE core at 0x3e80000
    InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 3E96708
    HOBLIST address in DXE = 0x3E56010
    Memory Allocation 0x00000003 0x3E80000 - 0x3EBFFFF
    FV Hob            0xFFC14D78 - 0xFFE74D77
    InstallProtocolInterface: D8117CFE-94A6-11D4-9A3A-0090273FC14D 3E95EA0
    InstallProtocolInterface: EE4E5898-3914-4259-9D6E-DC7BD79403CF 3E9630C
    
    Security Arch Protocol not present!!
    
    CPU Arch Protocol not present!!
    
    Metronome Arch Protocol not present!!
    
    Timer Arch Protocol not present!!
    
    Bds Arch Protocol not present!!
    
    Watchdog Timer Arch Protocol not present!!
    
    Runtime Arch Protocol not present!!
    
    Variable Arch Protocol not present!!
    
    Variable Write Arch Protocol not present!!
    
    Capsule Arch Protocol not present!!
    
    Monotonic Counter Arch Protocol not present!!
    
    Reset Arch Protocol not present!!
    
    Real Time Clock Arch Protocol not present!!
    
    ASSERT_EFI_ERROR (Status = Not Found)
    ASSERT /home/reinauer/svn/Tiano/edk2/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c(461): !EFI_ERROR (Status)
    
    Change-Id: I14068e9a28ff67ab1bf03105d56dab2e8be7b230
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2154
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7d3c7f1089f6861de8173cde6c0b481260b08a4f
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Wed Jan 30 14:01:42 2013 +0100

    ASRock E350M1: Remove unused variable `reg8` from `romstage.c`
    
        […]
            CC         romstage.inc
        src/mainboard/asrock/e350m1/romstage.c: In function 'cache_as_ram_main':
        src/mainboard/asrock/e350m1/romstage.c:48:5: warning: unused variable 'reg8' [-Wunused-variable]
    
    This change was already done for AMD Persimmon in the following
    commit.
    
        commit d7a696d0f229abccc95ff411f28d91b9b796ab74
        Author: efdesign98 <efdesign98@gmail.com>
        Date:   Thu Sep 15 15:24:26 2011 -0600
    
            Persimmon updates for AMD F14 rev C0
    
    Change-Id: I8f1ae1a609b87b197583934f0556f66b64e6994d
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2230
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 5a9f45c757b48235d86018bee2d20f9e35d7e1d7
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jan 28 23:42:25 2013 +0800

    cbfstool: Prevent file name to be corrupted by basename().
    
    Calling basename(3) may modify content. We should allocate another buffer to
    prevent corrupting input buffer (full file path names).
    
    Change-Id: Ib4827f887542596feef16e7829b00444220b9922
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2203
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 3414234f5a21b23b5b6cc0d2827ccbb4d9a2ccc8
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jan 29 14:31:33 2013 -0800

    Exynos5250: change all unsigned with no type to 'unsigned int'
    
    At some point we did a lot of cleanup to replace bare 'unsigned'
    with 'unsigned int'. Do that work for this imported code as well.
    
    At some point, we may find we can shrink these 'int's to something
    smaller, thought I very much doubt it's worth the trouble.
    
    Change-Id: Ic3da491c0188c56c836f8b9c4c8f26a31b4b3573
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2223
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 88e4691ed9f580b468005fd3ffec148b6e00e9ae
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jan 29 14:16:35 2013 -0800

    Exynos5250: add debug prints to DDR3 startup code.
    
    It can be handy to have debug prints as DRAM is started up, so that
    in the case of failure (does that ever happen?) you've got some
    idea where it failed.
    
    This patch adds some DEBUG_SPEW prints to the DDR3 code. I am doing this
    as its own CL because we may find we want to revert it. That's unlikely
    but it is not impossible if we skew the timing in some way.
    
    This code works for some trivial DRAM tests.
    
    Change-Id: I57e8d2a2d8df6b8ec8cd0d414681fc513e9999e3
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2222
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 770996fd86a2dfd44b0985b898af56c9dc10244b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jan 29 11:52:05 2013 -0800

    Exynos5250: make vendor enums in the timing array more debuggable.
    
    The timing array is crucial to proper operation of DRAM.
    
    Getting a valid pointer to it is hence very important. Unfortunately,
    the constants chosen for the vendor were '1', and '2', (this in a
    32-bit word) which in a debug print makes it almost impossible to tell
    if you've got a misaligned pointer. Note: coreboot people did not
    choose them :-)
    
    So, give them values which are extremely unlikely to occur elsewhere
    in the array (or in memory, for that matter).
    
    Given the frequency with which this check occurs, i.e. once, I would
    much prefer strings but I expect I'd get shouted down on that
    one. Constants in this case are an almost useless optimization but
    we'll go with them for now. Note no space is saved by not using
    strings: there's an entire function somewhere devoted to mapping the
    enum to a string!
    
    Debug prints of pointers to structs in this array are now far more
    useful than they were.
    
    See snarky comment in the code (left there to make sure nobody gets
    tempted to get fancy again). Comment now less snarky.
    
    This is tested on google snow to the point that the DRAM works.
    
    Change-Id: I30bc44719f321f791fd82ded60e29393399d9e3d
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2221
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 657ea6a13db5ad34dac80be8e77cc5406f0fe33b
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jan 28 23:00:47 2013 +0800

    cbfstool: Change "locate" output to prefix "0x".
    
    Currently "cbfstool locate" outputs a hex number without "0x" prefix.
    This makes extra step (prefix 0x, and then generate another temp file) in build
    process, and may be a problem when we want to allow changing its output format
    (ex, using decimal). Adding the "0x" in cbfstool itself should be better.
    
    Change-Id: I639bb8f192a756883c9c4b2d11af6bc166c7811d
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2201
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 4505cebdad4637762ae1ae10dcb43eb4f2b3784f
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jan 28 22:40:10 2013 +0800

    cbfstool: Remove unused header files.
    
    cbfs-mk*.c does not work with real files / command line so header files with
    file I/O and getopt can be removed.
    
    Change-Id: I9d93152982fd4abdc98017c983dd240b81c965f5
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2200
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 90b4ce27759c2cd63586481d2bafeeac61e5ab70
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jan 28 09:01:26 2013 -0800

    armv7: Clean up the mmu setup a bit
    
    The previous incarnation did not use all of mmu_setup, which meant
    we did not carefully disable things before (possibly) changing them.
    
    This code is tested and works, and it's a bit of a simplification.
    
    Change-Id: I0560f9b8e25f31cd90e34304d6ec987fc5c87699
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2204
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 1fb9bfa0f90c73c73bf0b9b7d9d5a2af6d7fe530
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Jan 28 12:24:54 2013 -0800

    armv7: nuke global_data.h and remove some references to gd struct
    
    This begins to remove references to global data which u-boot used.
    There are still many commented out references to gd-> and bd-> which
    we'll fix once we're happy with the replacements.
    
    Change-Id: Ie1b40a997e28a118f8f3ad96a2f9a2462d32fbe3
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2210
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4a484203d011c6fb3dd6f0edb2fadb3f2b07220c
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Jan 28 12:11:27 2013 -0800

    armv7: Clean out weak symbols and unnecessary #ifdef's in cache files
    
    This just removes unused code. If for some reason we don't want to
    initialize cache, then the CPU or mainboard specific init routines
    don't need to call these.
    
    Change-Id: Ieb7393b6cbc103e490753da4ed27114156466ded
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2209
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 6d1708dd46db22f1d10de7262baf6f40a9439600
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Jan 23 11:49:17 2013 -0700

    AMD/Persimmon: DP0 is connected to a LVDS connector
    
    This change is required in order to use a LVDS panel
    attached to the LVDS connector.
    
    Change-Id: Id97c233f964151b6515bd46c797425d0e6690cbd
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2188
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit d173962c6e951486a7c234e269333073584b77ac
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Mon Jan 28 14:23:49 2013 +0800

    cbfstool: Store global variables into struct.
    
    cbfstool.c uses lots of global variables for command line options and all named
    as "rom*". This may be confusing when other global variables also start with
    rom, ex:	int size = rom_size + romsize;
    (rom_size is from command line and romsize is the size of last loaded ROM image).
    
    If we pack all rom_* into a struct it may be more clear, ex:
    	do_something(param.cbfs_name, param.size, &romsize);
    
    Change-Id: I5a298f4d67e712f90e998bcb70f2a68b8c0db6ac
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2195
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dd678a2e16743629e883287e11a53ad359fe7970
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Wed Jul 4 07:39:07 2012 +0400

    msrtool: Decoding for most of Intel Core 2 MSRs
    
    Added bits/bitfields descriptions and decoding values
    into intel_core2_later.c file, which describe
    MSRs for Intel processors, based on later Core 2
    architecture.
    
    Change-Id: If577c8ed944afe34f86944cc03a780fba6b3dbba
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1171
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d1de45e095c53887fa30ebaf6807846d0ef470cd
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Jan 23 13:45:23 2013 +0100

    ioapic: Factor out counting code to `ioapic_interrupt_count`
    
    No need to keep duplicate variants of counting ioapic interrupts.
    
    Change-Id: I512860297309c46e05cc5379bf61479878817b1e
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2185
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit dfff8a163164d28f81ee9d057fb49c8ed3204c6a
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Jan 20 11:30:14 2013 +0100

    AMD boards, ASRock E350M1: Remove whitespace in front of comma in DSDT
    
        commit 585a4006976e903599b7128200a29b5729777818
        Author: zbao <fishbaozi@gmail.com>
        Date:   Thu Apr 12 11:27:26 2012 +0800
    
            Leverage the Pstate table created by AGESA.
    
    … introduced unneeded whitespace in front of a comma.
    
    Revert that part of the above commit. In the file for AMD Dinar
    tabs and spaces are mixed, but leave that alone for the beginning.
    
    Change-Id: I279cd0cb0be8c79258034733773f2ae1c2207cce
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2187
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 70f39871a92c065ee52be9d25aaf7a3e874fc1a3
Author: Olivier Langlois <olivier@olivierlanglois.net>
Date:   Fri Jan 25 00:49:46 2013 -0500

    inteltool: Add support for Atom N455 (0x106c0) in CPU MSRs dump
    
    reference for Atom MSRs are from
    Intel 64 and IA-32 Architectures Software Developer's Manual
    Volume 3C: System Programming Guide, Part 3
    Order Number 326019, January 2013, Table 35-4, 35-5
    
    Has been successfully tested on the targeted cpu.
    
    Change-Id: If94279caeab27121c63ec43c258dc962c167ad51
    Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2192
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 658e4d3ea900c9925d1e5dbbc99f08a9a6fc0323
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jan 17 12:29:51 2013 -0800

    libpayload: use $(DOTCONFIG) instead of .config
    
    When overriding the DOTCONFIG variable, make install
    will fail in libpayload.
    
    Change-Id: I332be3a4ca2620a32a6f5fbe683e6c71f0d6a9e9
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2178
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 336b8b171289ef80d465e0726eb7674cafe78a31
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Jan 23 18:10:04 2013 +0100

    AGESA: Kconfig: Drop useless depends statement
    
    `depends on FOO` in
    
            if FOO
              ... depends on FOO
            endif
    
    is useless.
    
    Introduced in
    
            commit 4b508341bcf11687be98d20f8178b5cc542a0842
            Author: efdesign98 <efdesign98@gmail.com>
            Date:   Wed Jul 13 17:16:13 2011 -0700
    
                Add AMD Family 10 support to cpu folder
    
    and probably copied later on in the following commit.
    
            commit d3e990c6e5124f30b394f5dbd4902ea8bf341b07
            Author: Kerry Sheh <shekairui@gmail.com>
            Date:   Tue Feb 7 20:31:35 2012 +0800
    
                AGESA F15: AGESA family15 model 00-0fh cpu wrapper
    
    Change-Id: I67cf231e3047a07cb6f0eeb5f77be368674a0603
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2186
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Hengelein <ilendir@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit be0e92568f115488e0555ec67a27a6b93d212a4e
Author: Aladyshev Konstantin <aladyshev@nicevt.ru>
Date:   Tue Dec 18 22:29:20 2012 +0400

    clear_ioapic: Fix reading of number of interrupts for IO-APICs
    
    Apply the same fix for `setup_ioapic` as done in the following commit.
    
    commit 23c046b6f16805ff0131460189967bf261d704de Author: Nico Huber <nico.huber@secunet.com> Date: Mon Sep 24 10:48:43 2012 +0200
    
    	Fix reading of number of interrupts for IO-APICs
    
    	The number read from the io-apic register represents the index of the
    	highest interrupt redirection entry, i.e. the number of interrupts
    	minus one.
    
    	Change-Id: I54c992e4ff400de24bb9fef5d82251078f92c588
    	Signed-off-by: Nico Huber <nico.huber@secunet.com>
    	Reviewed-on: http://review.coreboot.org/1624
    	Tested-by: build bot (Jenkins)
    	Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    Change-Id: I7b730d016a514c95c3b32aee6f31bd3d7b2c08cb
    Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/2043
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d5c998be99709c92f200b3b08aed2ca3fee2d519
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Wed Jan 16 17:14:24 2013 -0700

    Add MMCONF resource to AMD fam14 PCI_DOMAIN.
    
    The coreboot resource allocator doesn't respect resources
    claimed in the APIC_CLUSTER. Move the MMCONF resource to the
    PCI_DOMAIN to prevent overlap with PCI devices.
    
    Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2167
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com>

commit 5e732b8bf0fde8a304758e8845f3100a09037f2b
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Jan 22 11:58:13 2013 +0100

    util/runfw/googlesnow.c: Remove trailing whitespace
    
        $ git stripspace < util/runfw/googlesnow.c > /tmp/bla
        $ mv /tmp/bla util/runfw/googlesnow.c
    
    Introduced with original commit.
    
        commit b867281a07addd1eb00f964ff4f8727664e13e19
        Author: Ronald G. Minnich <rminnich@gmail.com>
        Date:   Wed Jan 16 11:59:34 2013 -0600
    
            Utility to run the snow bios in user mode
    
    Change-Id: I146c07a918ef99e8ae3c0dd72cf28fae22312e43
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2183
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8a49ac7f808f76821e7d63070420cfd98f707c7c
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Wed Jan 16 17:02:20 2013 -0700

    Rename fam14 pci northbridge ops functions.
    
    Clarify the northbridge ops function names.
    
    Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2166
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 73e86a88d223a3c8f0b572c43aa39269df5bff62
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jan 17 16:28:30 2013 -0700

    F15tn: Fix all warnings, enable warnings as errors
    
    Enable 'all warnings being treated as errors' in thatcher and parmer.
    
    Fixed the following warnings on parmer / thatcher:
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
     In function 'GetGlobalCpuFeatureListAddress':
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
     warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
     In function 'SaveDeviceContext':
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
     warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
     warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:
     In function 'GetPstateGatherDataAddressAtPost':
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10:
     warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    
    src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:
     In function 'MemNInitNBDataTN':
    src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32:
     warning: assignment from incompatible pointer type [enabled by default]
    src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23:
     warning: assignment from incompatible pointer type [enabled by default]
    
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
     In function 'GetGlobalCpuFeatureListAddress':
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
     warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
     In function 'SaveDeviceContext':
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
     warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
     warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
    
    In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0:
    src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
     warning: "TOP_MEM" redefined [enabled by default]
    src/include/cpu/amd/mtrr.h:31:0:
     note: this is the location of the previous definition
    src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
     warning: "TOP_MEM2" redefined [enabled by default]
    src/include/cpu/amd/mtrr.h:34:0:
     note: this is the location of the previous definition
    In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0:
    src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0:
     warning: "LOCAL_APIC_ADDR" redefined [enabled by default]
    src/include/cpu/x86/lapic_def.h:9:0: note:
     this is the location of the previous definition
    
    In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0,
                     from src/mainboard/amd/parmer/mainboard.c:28:
    src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
     warning: "TOP_MEM" redefined [enabled by default]
    src/include/cpu/amd/mtrr.h:31:0:
     note: this is the location of the previous definition
    src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
     warning: "TOP_MEM2" redefined [enabled by default]
    src/include/cpu/amd/mtrr.h:34:0: note:
     this is the location of the previous definition
    
    Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2171
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2edf77cc29ca069f04c60784b6217239e19ce54e
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Tue Jan 22 11:46:34 2013 +0100

    src/lib/timestamp.c: Fix spelling of tim*e*stamp
    
    Change-Id: I96d41882c92e577ce816264c493376d2f2d950f6
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2181
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 80e351695f7d685f9d97933c1797b460d82422b5
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Mon Jan 21 19:33:22 2013 -0700

    Hudson: Legacy free question is hudson only
    
    The "system is legacy free" question accidentally escaped
    from the hudson Kconfig where it was intended to stay and
    went coreboot-wide.  This puts it back inside the boundries
    of the hudson southbridge where it belongs.
    
    I also commented the endif statements to make it easier to
    tell where things belong.
    
    Change-Id: I49f7a5eadb96d40c6101a93bc390e644617a5654
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2179
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 35934415c4d36e094f4c53f155cb9efa3aef977e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Jan 21 20:02:15 2013 -0800

    armv7: add ARM-encoded bootblock_exit() stub
    
    This replaces the call() function with a stub which is compiled
    separately using -marm. See http://review.coreboot.org/#/c/2175/
    for details.
    
    Change-Id: I7f8c45b5e63ec97b0a82294488129d1c97ec0cbf
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2180
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f5726ea544af904061b754fb6e369e477e93f0a5
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Fri Jan 18 12:55:40 2013 -0700

    Hudson: Cleanup - change SB800 references to hudson
    
    Go through southbridge/amd/agesa/hudson, thatcher and parmer
    mainboard directories and change all references to sb800 to
    reference hudson instead.
    
    This is just cleanup and should make no functional difference.
    
    Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2177
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 2892023fd422794bb82658dde3e8d489af2bdd55
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Thu Jan 17 12:04:08 2013 -0700

    AGESA F15tn: Move callouts into northbridge wrapper
    
    There are currently too many things in the mainboard directories that
    are really more suited to being in the northbridge / southbridge
    wrappers.  This is a start at moving some of those functions down
    into the wrappers.
    
    Move the bios callback functions into the northbridge/amd/agesa/family15tn
    directory from the mainboard directories.  These can still be overridden
    by any mainboard just by updating the pointer in the callback table to
    point to a customized version of the function.
    
    Change-Id: Icefaa014f4a4abbe51870aee7aa2fa1164e324c1
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2169
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit e4cd00cacb4b1ab374c575b972fa2662ec739642
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Tue Jan 15 13:17:30 2013 -0700

    Save and restore F15TN graphics command register
    
    In the AGESA routine GfxInitSview() called in the S3save path,
    the IO Space bit was getting cleared from the command register.
    This kept seabios from initializing the video bios.  If the vbios
    was loaded by coreboot, this routine was skipped, allowing seabios
    to initialize vbios as well.  I have modified the routine to save
    and restore the command register instead of clearing the IO Space
    bit.
    
    Change-Id: I756b0606adbc47da96780308c911852e39f547c7
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2172
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit eac220f8b5f0fc20f17d82ea270bd948a9b94c37
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Wed Jan 16 09:07:30 2013 -0700

    Hudson: Changes to support agesa/hudson for legacy free
    
    Add Kconfig option for Legacy free and hook it into the parmer
    AGESA initialization as well as the FADT code. This should really
    be done inside the southbridge wrapper and not in the mainboard,
    but for now the code to attach it to is inside the mainboard.
    
    Update Kconfig for parmer and thatcher to default to legacy free.
    
    Change-Id: Ib899bd02ddc5506caae4aca2c589cc2526638cb8
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2157
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 0fbaf18ed4839910801905253b49c077cc1f346f
Author: Martin Roth <martin@se-eng.com>
Date:   Thu Jan 10 16:40:59 2013 -0700

    Hudson: Changes to agesa/hudson FADT for ACPI 3.0
    
    Update the southbridge/amd/agesa/hudson FADT generation for ACPI
    3.0 compliance similar to what was done for cimx/SB800/fadt.c in
    commit 9aa4389.
    
        commit 9aa43892e6899b719fe7f4754901a0eae379a934
        Author: Martin Roth <martin@se-eng.com>
        Date:   Fri May 25 12:23:32 2012 -0600
    
            Update SB800 CIMX FADT
    
    According to the datasheet, PMA_CNT_BLK is no longer available
    and PM2_CNT_BLK should not be used.  Setup for these has been
    removed from the table and .h file.
    
    Change-Id: Ied8eb1f26b4aa364d051ec5f7ed6f482bb440957
    Signed-off-by: Martin Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2140
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 931df3a96bce9e3bc6f0d1058c301c49bee63747
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Wed Jan 16 17:50:32 2013 -0700

    F15tn / Hudson: Change SATA NumOfPorts register setting
    
    The Number of Ports register says that it should be set to the maximum
    number of ports supported by the silicon.  AGESA was setting this to be
    the number of enabled ports.  If port 1 was the only port with a drive,
    this value got set to 0, indicating 1 port.  This causes SeaBIOS to only
    look at port 0 and quit, never finding the drive on port 1.
    
    Dave Frodin: I also verified that this patch allows a SATA drive plugged
    into port 2 to be detected without a device in port 1.
    
    Change-Id: I5d49e351864449520e3957bbb07edf0f3ec2fd47
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2165
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit c89d3daf32476f02b0bea7dc84572adfad55fc3d
Author: Martin Roth <martin.roth@se-eng.com>
Date:   Wed Jan 16 19:18:09 2013 -0700

    Parmer / Thatcher: devicetree.cb cleanup and whitespace
    
    Re-formatting and cleaning up the devicetree.cb files for
    parmer and thatcher.
    
    Change-Id: Ic458e59701c1f2593b0a035b96cac60df476ee82
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2164
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>

commit 2d8815197e7a8f7fa8c7e7dd6127937093369c7c
Author: Martin Roth <martin@se-eng.com>
Date:   Thu Jan 10 12:41:40 2013 -0700

    F15tn: Modify devicetree to fix S3 resume
    
    The way that devicetree.cb was configured for the family 15tn boards
    was doing... interesting things to the video device initialization.
    This was causing S3 resume to fail.
    
    There is a disconnect between how the devicetree should be configured
    if there are multiple HT links on the CPU and how it's configured if
    there's only one HT link.  These platforms were set up as if they
    had multiple HT links, which was causing duplicate instances of
    devices in the device list.
    
    The scan for the IO Hub was removed from the northbridge code which
    isn't a problem for F15tn devices.
    
    Change-Id: I3556b43027746e36b07de7cb1bece4d1b37a3c34
    Signed-off-by: Martin Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2160
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit b867281a07addd1eb00f964ff4f8727664e13e19
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jan 16 11:59:34 2013 -0600

    Utility to run the snow bios in user mode
    
    This program lets you test run a snow coreboot image in user mode
    on a properly equipped arm system (usually an ARM chromebook).
    This is a real time saver as you don't have to flash each time.
    We've found and fixed some nasty bugs with this one.
    
    Anyway, the instructions on how to use this are in the binary.
    
    Change-Id: Ib555ef51fd7e930905a2ee5cbfda1cc6f068278e
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2159
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit db5b893569f0b0c17e8faf1905f7da2450984432
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Jan 18 15:53:22 2013 -0800

    Add more information to the cbfstool print
    
    Show what's in a stage or payload. This will let people better understand
    what's in a stage or payload.
    
    Change-Id: If6d9a877b4aedd5cece76774e41f0daadb20c008
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2176
    Tested-by: build bot (Jenkins)

commit 211a5d56db2ecf580b722fab132d908a6ba84dde
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 17 20:52:21 2013 -0800

    armv7/snow: get to romstage
    
    This patch does a few things to get us into romstage:
    - Add romstage as a stage (a later patch adds it as a binary, which
      is probably wrong). The Makefile magic is complex enough that we
      let it build the XIP file for now, but we no longer use it.
    
    - Replace findstage with loadstage. Loadstage will find a stage,
      load the code to memory, and zero the remaining part of memory.
      Now we can link the romstage to go anywhere!
    
    - Eliminate magic offsets from code/ldscripts and centralize Kconfig
      variables in src/cpu/samsung/exynos5250/Kconfig.
    
    - Tidy up code and serial output
    
    Change-Id: Iae4d2f9e7f429cb1df15d49daf9a08b88d75d79d
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2174
    Tested-by: build bot (Jenkins)

commit f572e1e5fca59215461bb9ba3de56882b762b345
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Jan 16 09:47:54 2013 -0800

    Update gcov patch in documentation
    
    .. to reflect the recent changes w.r.t avoiding
    trouble with the coreboot pre-commit hooks.
    
    and fix two whitespace errors.
    
    Change-Id: I6c94e95dd439940cf3b44231c8aab5126e9d45c7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2158
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>

commit 929f9f171944082240c04507b3f6ac1b0a2c6b1e
Author: Gabe Black <gabeblack@chromium.com>
Date:   Thu Jan 17 22:26:36 2013 -0800

    armv7: add a wrapper for romstage's main() for ARM ISA
    
    This adds a wrapper around main() in romstage which is compiled using
    -marm. This assumes that the bootblock branches to romstage in ARM
    mode.
    
    The long-term idea is to enforce ABI compatibility when handing off to
    the next stage by using shims which are which are compiled in a pre-
    determiend manner and leave the main portions of each stage up to
    whatever the compiler wants. So it will eventually look like this:
    1. bootblock_main (ARM/Thumb)
    2. bootblock_exit (ARM)
    3. romstage_entry (ARM)
    4. romstage_main (ARM/Thumb)
    
    (credit to Gabe Black for writing the patch, I'm just uploading it)
    
    Change-Id: I4fdb8d2c6c2c0a7178bcb9154c378ddce0567309
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Gabe Black <gabeblack@chromium.org>
    Reviewed-on: http://review.coreboot.org/2175
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fba42a793a67d8910b4ab7fdfb386bcda9896d13
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 17 15:07:35 2013 -0800

    Snow bootblock (bloated/debug version)
    
    This is the bloated Snow bootblock which includes:
    - SPI driver
    - UART, including requisite I2C, Maxim PMIC, and clock config code.
    - Adjustments for magic offsets (id section, stack pointer address)
    
    This is just a temporary solution until we have romstage loading.
    Once that happens, we'll rip out all but the code necessary for
    copying SPI ROM content into SRAM.
    
    Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2170
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1c706dc85830a1d91c7ff7c99ac48efd8d085613
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jan 17 11:14:17 2013 -0800

    Fix the stack setup code so we can use an arbitrary 32-bit value
    
    We've had obscure errors as the size of the bootblock changes.
    This fix allows us to use a 32-bit constant. Please test on
    real hardware before you ack.
    
    Change-Id: Ic3d9f4763554bd6104ae9c4ce5bbacd17b40872c
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2168
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit e2851f2812ddf39b362e2abba76eeec0cd705dee
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 16 15:00:07 2013 -0800

    make main() in snow's romstage.c our romstage entry point
    
    Our earlier attempt was jumping straight from asm to the old u-boot
    board_init_f in lowlevel_init_c.c. We are getting ready to transition
    to using a real bootblock for ARM, so add romstage.c to the files
    compiled and we'll make main() our entry point.
    
    This also updates romstage.ld to place main() (*(.text.startup)) at
    the beginning of romstage.
    
    Change-Id: Ifc77a6bfba27d915c4cad62c6c8040665294628a
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2163
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 88c4939c1b6cb2097a9877bb298d2ee6b8580f62
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Mon Jan 14 16:08:10 2013 -0800

    make crossgcc: compile all required toolchains
    
    The ARMv7 toolchain is now also needed for abuild (at least
    if you want to be able to compile ARM images)
    
    Change-Id: If1253203a2198f7dea632ba45540222ba3361932
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2147
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 018724ec1b102435afc7a6374e49e30091f4a2a8
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 16 14:58:48 2013 -0800

    remove argument in snow's romstage main()
    
    We don't pass any arguments into romstage on ARM.
    
    Change-Id: I018f28a57fc486c9240345cf0f4043b79027d864
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2162
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 694719aff0a782782fd1c0a0d6635f7af1729ba1
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Jan 11 11:34:06 2013 -0800

    bootblock_cpu_init() stub for exynos5250
    
    This adds a stub for bootblock_cpu_init() for exynos5250. It will
    eventually contain code to copy ROM content from SPI to SRAM.
    
    Change-Id: I26ee62a1e701013f38f76f200579faa680530860
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2138
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0b23d47ffd1c87cb41df9e3e1b73cdfddd425dcd
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Jan 14 20:58:50 2013 -0800

    armv7: Place reset vector + CBFS header + bootblock dynamically
    
    This replaces hard-coded bootblock offsets using the new scheme.
    The assembler will place the initial branch instruction after BL1,
    skip 2 aligned chunks, and place the remaining bootblock code after.
    
    It will also leave an anchor string, currently 0xdeadbeef which
    cbfstool will find. Once found, cbfstool will place the master CBFS
    header at the next aligned offset.
    
    Here is how it looks:
    
                 0x0000 |--------------|
                        |     BL1      |
                 0x2000 |--------------|
                        |    branch    |
        0x2000 + align  |--------------|
                        |  CBFS header |
    0x2000 + align * 2  |--------------|
                        |   bootblock  |
                        |--------------|
    
    TODO: The option for alignment passed into cbfstool has always been
    64. Can we set it to 16 instead?
    
    Change-Id: Icbe817cbd8a37f11990aaf060aab77d2dc113cb1
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2148
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3d7344a7a1fcf09406460da59b61baff564bbbd3
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Jan 8 21:05:06 2013 -0800

    ARM bootblock approach
    
    This lays out the groundwork for using a proper bootblock on ARM.
    Currently we bypass the bootblock entirely and go straight to
    romstage. However we want to utilize CBFS to maximize flexibility
    of placing code without relying on a lot of magic numbers which
    will break depending on the SoC in use.
    
    Change-Id: I9cc2a8191d2db38b27b6363ba673e5a360de9684
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2118
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 09574d5c3c920d2959336a25064f9651df39e30e
Author: Martin Roth <martin@se-eng.com>
Date:   Mon Jan 14 15:46:38 2013 -0700

    Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITS
    
    Bits were being shifted off the end of the mask accidentally.
    This results in all masks being 32 bits wide instead of 48.
    
    Change-Id: I5f4d1b6a323df1aa4568ff4491f82447b8a2f839
    Signed-off-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2146
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit a12eaccc0bbfd6f2b47fd5eb38574852a64ec749
Author: David Hendricks <dhendrix@chromium.org>
Date:   Tue Jan 15 16:09:08 2013 -0800

    use a relative path for #line 3
    
    The current path doesn't make much sense (unless you're Sven)
    and may also incur a very long access penalty if /home happens
    to be on a network mounted filesystem.
    
    Change-Id: I8cfceb3cf237757ce9ea8f1953bce5a72691838a
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2153
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9382bd65d4ebee690fe7ee6602d418144ed92d54
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Jan 16 00:26:41 2013 +0100

    armv7: delete unneeded ptrace.h
    
    ... and delete traces in source files.
    
    Change-Id: Ie0f70a479f1eadadc654a41fa3c426d1d4ac2f2b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2152
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 09e16dc21597d20f215c822d63f8409271baacca
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jan 14 10:20:15 2013 -0800

    libpayload: Style fixes
    
    Change-Id: Ic3164fbffd8da6bd9d506d80e425ad89efc0f1af
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-on: http://review.coreboot.org/2144
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Martin Roth <martin.roth@se-eng.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 816e9d1f0e1d317e360e26a43dfb6b7d36c2a514
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jan 14 10:25:43 2013 -0800

    Support for Celeron 1007U
    
    Change-Id: I6b96b0e387dc3e6985eb1476fea612772a2288bc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2145
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>

commit 850793f6d0f272012584b416c5cbb0313a07f542
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Jan 13 17:22:42 2013 -0600

    Make the pre-commit-hook happy about the code in libgcov.c
    
    Make the comments match what pre-commit-hook wants.
    
    Change-Id: Ib99a6583f97221df3638bd3b7723f51d5f9c223c
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2143
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d37ab454d4ea702df276a66d4e0ea9f73d4f6fe0
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 18 16:23:28 2012 -0800

    Implement GCC code coverage analysis
    
    In order to provide some insight on what code is executed during
    coreboot's run time and how well our test scenarios work, this
    adds code coverage support to coreboot's ram stage. This should
    be easily adaptable for payloads, and maybe even romstage.
    
    See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
    more information.
    
    To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
    support") in Kconfig, and recompile coreboot. coreboot will then
    store its code coverage information into CBMEM, if possible.
    Then, run "cbmem -CV" as root on the target system running the
    instrumented coreboot binary. This will create a whole bunch of
    .gcda files that contain coverage information. Tar them up, copy
    them to your build system machine, and untar them. Then you can
    use your favorite coverage utility (gcov, lcov, ...) to visualize
    code coverage.
    
    For a sneak peak of what will expect you, please take a look
    at http://www.coreboot.org/~stepan/coreboot-coverage/
    
    Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2052
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6e21f43008bcf74e64755ca896149943b1cc4229
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 11 11:02:58 2013 -0800

    No random directories
    
    Please, don't just add random directories for a single file because
    it seems convenient. There already is a chromeos directory, that should
    be used.
    
    Change-Id: I625292cac4cbffe31ff3e3d952b11cd82e4b151e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2137
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6a01563d06dea446f4f537b2fa2d760b1cb7cd24
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jan 11 15:07:50 2013 -0800

    Move init.S to a proper filename
    
    Also, remove unnecessary junk and prepare for future build changes.
    
    Change-Id: I143777ec7e67ea4d6fed00084aafcb94c7866b4d
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2141
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 8d05322b68471b782cd239acd3a4ac4241eddab3
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 11 10:46:55 2013 -0800

    Fix console.c with serial support disabled
    
    During the ARM port, disabling serial console became broken.
    This patch fixes it.
    
    Change-Id: I40460596073918a08c19bb9c991cada341cca940
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2136
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b8ad2244686a801a96326d8075526d9b701ad982
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 11 10:41:42 2013 -0800

    cbmem: replace pointer type by uint64_t
    
    Since coreboot is compiled into 32bit code, and userspace
    might be 32 or 64bit, putting a pointer into the coreboot
    table is not viable. Instead, use a uint64_t, which is always
    big enough for a pointer, even if we decide to move to a 64bit
    coreboot at some point.
    
    Change-Id: Ic974cdcbc9b95126dd1e07125f3e9dce104545f5
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2135
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ea22796edaa5c51271ea98590d22eea3976cadba
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 10 15:07:59 2013 -0800

    armv7: Add temporary build script for CrOS devs
    
    This build script will:
    - Build coreboot.rom
    - Download BL1, extract and place it if necessary
    - Do a partial flash via Servo, using some flashrom trickery to
      make the process fast.
    
    This probably should not be submitted, unless the intention is to
    back it out eventually.
    
    Credit goes to Hung-Te for writing the original version.
    
    Change-Id: Ia7a4bea6077416fc06768a5de5ee07edc973ede2
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2134
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit eb5e252ce16acd80e5374a351d49e9d90cfed982
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 10 15:05:22 2013 -0800

    exynos5250: Hacked up lowlevel_init_c
    
    This is the first lowlevel init routine that gets called in romstage.
    It's fugly and needs a lot of clean-up, but does the job for now.
    
    Change-Id: Id54bf4f1c3753bcbed5f6b5eeb4b48bc3b41ce93
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2133
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b9fb213f85b9a6c76253c21504c6bfe838670de7
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 10 15:00:23 2013 -0800

    exynos5250: Temporarily remove intermediate rule in Makefile
    
    This cannot be used until we get the BL1 mess sorted out.
    
    Change-Id: I2490addb31256e27caa89ebb5b1501296e6903bd
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2132
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 105da50df4fe6073575a2eb6247d916746b6143e
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Sat Jan 5 12:17:46 2013 +0800

    AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITS
    
    The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these
    bits will cause exception. So be carefull when spread this change.
    
    The supermicro/h8scm needs more work. Currently it is set as it was.
    We need to check if the F10 and F15 have different value.
    
    Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1661
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 8a5ee9ce04cb88a57cf0a0d8a405c9865c99c01a
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 10 11:44:58 2013 -0800

    armv7: replace magic constant for romstage location
    
    This replaces 0x02023400 with an SoC-specific Kconfig variable.
    
    Change-Id: I21482d54a1e1fa6c4437c030ddae2b0bb3331551
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2130
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d6b0889febfce600fe56fa2fe4785a19fb84174a
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 10 11:32:31 2013 -0800

    add a few entries to .gitignore
    
    - Development friendly files (tags, clang_complete)
    - Cross-compile stuff (xgcc, tarballs)
    
    This patch was originally written by Stefan.
    
    Change-Id: I4229414c94ee04a4f38a748369c4ac90fda57aea
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
    Reviewed-on: http://review.coreboot.org/2128
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1dcb697a24973be03453aded2923816e2f6aca62
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Jan 10 12:13:21 2013 -0800

    armv7: add *(.data) back into .romdata section
    
    This doesn't seem to be strictly required (so far), but makes sense.
    
    Change-Id: I18416c427ff886507ae09c7fc1a018baf94af24a
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2131
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c82ec0ed33eddfff8dfb20de81376a329bc7f51e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 9 16:14:00 2013 -0800

    armv7: update board_init_f function signature
    
    We don't pass arguments when we jump out of assembly code.
    
    Change-Id: Iccf3a6f713e260b08f9ff47e8b542b9e96369166
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2122
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9ad1f56951df3d3877b9ae588909b1cb059c1cd7
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 9 17:45:19 2013 -0800

    armv7: dynamically calculate the branch offset in cbfstool
    
    This tidies up the ARMV7 case when creating cbfs:
    - Calculate the offset using the size of the master header and offsets
      rather than using a magic constant.
    - Re-order some assignments so things happen in a logical order.
    
    Change-Id: Id9cdbc3389c8bb504fa99436c9771936cc4c1c23
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2125
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8bc10b74dc36cdefdfb5a1c4457d44d9ec32fa15
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 9 16:12:23 2013 -0800

    armv7: delete some unused files
    
    Change-Id: I4601b97cbd7dbfb6ee742b3920d2aac4ac49b958
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2121
    Tested-by: build bot (Jenkins)
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>

commit 4868a1179dc1c70ed10cc56cdbc7bfd4fb5fef24
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 9 16:22:12 2013 -0800

    snow: add max77686 driver in romstage and ramstage
    
    Change-Id: Id3e20b1ab5d85cfd22e2dae2750f32007b7f8f74
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2123
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5f6d857deaac61b53cfa4e8cbc0abaa63e14fd9b
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 9 18:06:41 2013 -0800

    exynos5250: clean-ups for clock_init
    
    This does some clean-up for the exynos5250 clock_init.c:
    - No global data.
    - Remove some unused #includes
    - Hard-code the memory type for Elpida DRAM. This will need to be
      fixed eventually (or the system will be unstable), but is good
      enough for early bring-up and until we finish other re-factoring.
    
    Change-Id: Icd2cf8ba35058cbd1131666db311dfb77ef1a160
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2127
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 27094b0afe25caf38e323d5f350be7d89aace366
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 9 17:42:02 2013 -0800

    exynos5250: un-comment a lot of code which was left out earlier
    
    Turns out initializing power rails is necessary, even for getting
    serial output.
    
    Change-Id: I3042c1001ae43b1e793ee6cb90bb79b8db0f8fd1
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2126
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1d5390ecc85f7d0fc25d1a5cbe62ae6fa1abf5e2
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 9 16:26:26 2013 -0800

    size optimizations for max77686
    
    This contains some size optimizations for the Maxim MAX77686 driver:
    - change max77686_para.vol_{min,div} from u32 to u16 (currently their
      max value is 50000 so it should be fine)
    - remove max77686_para.regnum which takes 4 bytes for each and is not
      used
    
    (Patch was originally written by Hung-Te Lin, I'm just uploading it)
    
    Change-Id: I24044427c49467e99380d1f60ebc59e69c285b22
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2124
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 92dd172a573a7eff4774030fdfe5eb9625d59aa0
Author: Martin Roth <martin@se-eng.com>
Date:   Tue Jan 8 13:36:14 2013 -0700

    Fix 2 infinite loops if IMC doesn't respond
    
    ACPI code:
    The ACPI code is not currently being compiled in by default, but
    assuming that it will be at some point, I'm fixing the loop that
    waits for the IMC to respond after sending it a command.  The
    loop now exits after 500ms, similar to the function in agesa.
    
    Agesa Code:
    a 16 bit variable will always be less than 100000.  Change to
    be a 32 bit variable.
    
    Change-Id: I9430ef900a22d056871b744f3b1511abdfea516e
    Signed-off-by: Martin Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2119
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 238780c8da866c0f8a80a4c0004bc81d2a060a8d
Author: Martin Roth <martin@se-eng.com>
Date:   Tue Jan 8 13:46:50 2013 -0700

    Fix typo in SB800 Kconfig for IMC position
    
    The cimx/sb800 IMC Firmware location Kconfig option has
    a typo which would could set it to the wrong location.
    
    Change-Id: I38016bebd1bfe6ad6d3f1c02cb1960712fbf4ab2
    Signed-off-by: Martin Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2120
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 597ff87574b11dc1163eb152e0941a2cbce5341b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jan 7 13:21:22 2013 -0800

    qemu-x86: Implement more features
    
    This patch switches the Qemu target to use (pseudo) Cache As RAM
    and enables some ACPI code. This allows to use the CBMEM console
    and timestamp code with coreboot in Qemu. Right now, the ACPI code
    is commented out because leaving it in breaks IDE.
    
    Change-Id: Ie20f3ecc194004f354ae3437b9cf9175382cadf8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2113
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c01990789f533316e10c5fc3b5ca08ae866b8033
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Mon Jan 7 16:26:10 2013 -0800

    cbmem utility: Find actual CBMEM area
    
    ... without the need for a coreboot table entry for each of them.
    
    Change-Id: I2917710fb9d00c4533d81331a362bf0c40a30353
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2117
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d7144dcd578215e345b10df5a6cdac7bd44ac3ad
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jan 7 15:25:37 2013 -0800

    cbmem utility: unify debug output
    
    ... and indent it to make output more comprehensible.
    
    Change-Id: If321f3233b31be14b2723175b781e5dd60dd72b6
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2116
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 062730d7cb35c8cc2cc07e15695eb62f2b647f4a
Author: zbao <fishbaozi@gmail.com>
Date:   Tue Jan 8 10:10:16 2013 +0800

    cbfstool: index is replaced by strchr.
    
    From index(3):
    CONFORMING TO 4.3BSD; marked as LEGACY in POSIX.1-2001. POSIX.1-2008
    removes the specifications of index() and rindex(), recommending
    strchr(3) and strrchr(3) instead.
    
    Change-Id: I3899b9ca9196dbbf2d147a38dacd7e742a3873fe
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2112
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 19f8756f0008cf74a472177642cc44f00c05934f
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Mon Jan 7 13:37:12 2013 -0800

    cbmem utility: Add option to dump cbmem console
    
    This adds an option to the cbmem utility to dump the cbmem console.
    To keep the utility backwards compatible, specifying -c disables
    printing of time stamps. To print both console and time stamps, run
    the utility with -ct
    
    Change-Id: Idd2dbf32c3c44f857c2f41e6c817c5ab13155d6f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2114
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>

commit 1665bb3896e49f84a28e24176734f447f3a0899b
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Mon Jan 7 13:39:43 2013 -0800

    cbmem utility: drop obsolete python based implementation
    
    The first version of the cbmem utility was written in python,
    but it had issues with 64bit systems and other little hick ups.
    Since the C version has much fewer dependencies (no python needed
    on target system), and it works in all corner cases, drop the
    python version.
    
    Change-Id: Ida3d6c9bb46f6d826f45538e4ceaa4fc1e771ff5
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2115
    Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
    Tested-by: build bot (Jenkins)

commit 2f25d9963ee6ba57db67a0410fcd932f4be18373
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 4 16:29:29 2013 -0800

    ARMv7: drop __ASSEMBLY__
    
    We moved to using __ASSEMBLER__ years ago since it is set by as.
    
    Change-Id: I60103ba23ebe87be1d0bc63beed0ef5b05eed4f2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2111
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 9bcab0c72bea6188ebf735ce08ba269ef5f9a272
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 4 16:04:34 2013 -0800

    Update 3rdparty mark to latest repository
    
    Change-Id: I59fca4427345c7e677138b944613a1554d5a8331
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2110
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 6d47cbe75859eaca4d56dd371d9dee6bd75dd23d
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 4 15:02:25 2013 -0800

    ARMv7: drop __KERNEL__
    
    It's a bad Linux heritage.. We have no userland in firmware.
    
    Change-Id: Ib19e5ba713078ca37514571213d19f418417b964
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2108
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9da7570b07abd99123afc0e95a72a6bb0dcbddf5
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 4 13:51:36 2013 -0800

    cbfstool: Fix warnings on OS X
    
    Most hton and noth functions are already available
    through the system headers we include on OS X, causing
    the compiler to warn about duplicate definitions.
    
    Change-Id: Id81852dfc028cf0c48155048c54d431436889c0e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2106
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 2485df3897d4254cbec6fd24a768c38149c69a36
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jan 4 13:50:00 2013 -0800

    Flatten the tree
    
    It makes no sense to have directories with one file.
    
    Change-Id: I65ba93dda5e6a4bcc5a7cc049c1378ebf5d6abcd
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2105
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit fa60de996d7c9676cf219c90e3cff602e148468d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jan 4 22:17:38 2013 +0100

    Revert "armv7: pass bootblock offset from Kconfig into cbfstool"
    
    This reverts commit ec8d35fe911ab35a5f40fd5b452f5463857b244a
    
    We are almost certain that this is not necessary.
    
    Change-Id: I70e94f883be95655da00a0b127ed9ffd7c81c63b
    Reviewed-on: http://review.coreboot.org/2104
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 853f4698a8ef9366178b83b0c42a3f662dc45c95
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 4 12:19:23 2013 -0800

    ARMv7: Make ABI compatible to reference toolchain
    
    Our reference toolchain uses -mabi=aapcs whereas we started
    forcing -mabi=aapcs-linux. Drop this to prevent ABI incompatibility.
    
    Also drop -fno-common since that's set in the top level Makefile.inc
    already.
    
    Change-Id: I4afdcf5da9a5d86c2f9e5de5c7d523ccd2f5f1e0
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2103
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3a8badc26519cd900d4f01c87c212973a1aea00c
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 4 12:10:28 2013 -0800

    ARMv7: drop libgcc copy
    
    We accidently checked in some files from libgcc as well as
    a Makefile from u-boot and a duplicate implementation of div0.
    
    Drop all those files to reduce the confusion.
    
    Change-Id: I8ff6eabbced6f663813f8cc55f19c81839d03477
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2102
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 31c36137f9519380df0c92ce1a5d2949eb083b91
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 4 10:11:59 2013 -0800

    Clean up ARMv7 architecture Kconfig
    
    There was a misuse of bool that would cause the dcache policy to not be
    set up correctly, but instead present options "y" and "n" in the Kconfig
    menu.
    
    Also, TINY_BOOTBLOCK was removed a while ago, everything is
    TINY_BOOTBLOCK now. Hence remove the option.
    
    Change-Id: I5c28ac828955c69614c7bdaf106f79db51e68723
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2101
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c4077d44297c95100cc9eb19df1ab3b16261942f
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 4 10:07:28 2013 -0800

    Make PCIe config options depend on PCIe support
    
    Change-Id: I42452a044dc75e35876fcea1736481e538eed663
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2100
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9027845d65e5e05a45894eb176070fd99e2e073c
Author: Aladyshev Konstantin <aladyshev@nicevt.ru>
Date:   Tue Dec 18 22:44:01 2012 +0400

    rd890: clear IO-APIC before setup
    
    Add function "clear_ioapic" before "setup_ioapic" for RD890 northbridge
    like it is done for SB700 and SB800 chipsets ("amd/cimx/sb{7,8}00").
    
    No functionality change is noticed.
    
    Change-Id: I1fd87692d8bf35c166141c9b7a6a1e748c19a636
    Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/2045
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 05cbce672e4a41bc55fc09b65aacd0872a756a5b
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Jan 3 14:30:33 2013 -0800

    cbmem utility: Use mmap instead of fseek/fread
    
    The kernel on Ubuntu 12.04LTS does not allow to use
    fseek/fread to read the coreboot table at the end of
    memory but will instead abort cbmem with a "Bad Address"
    error.
    
    Whether that is a security feature (some variation of
    CONFIG_STRICT_DEVMEM) or a kernel bug is not  yet clear,
    however using mmap works nicely.
    
    Change-Id: I796b4cd2096fcdcc65c1361ba990cd467f13877e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2097
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 3d4762d450f63c32038b4c9c422dc99c98fdee9a
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Fri Jan 4 13:07:49 2013 +0800

    Tyan s8226: change lapic of lapic_cluster 0 to 0x10
    
    There are two CPUs on s8226 and each CPU has 8 cores.
    CPU 0 takes lapic from 0x10 to 0x17 and CPU 1 takes from 0x20 to 0x27.
    So the first core's lapic is 0x10 rather than 0x20.
    
    Change-Id: I925114d44f2f4974eb62c3832d8c9139a2a06c96
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/2099
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 086842a13e50d2c870ddf749c036f8c321d2915f
Author: Hung-Te Lin <hungte@chromium.org>
Date:   Fri Jan 4 12:33:03 2013 +0800

    Change "VERSION*" to more determined name "CBFS_HEADER_VERSION*".
    
    The 'VERSION' in CBFS header file is confusing and may conflict when being used
    in libpayload.
    
    Change-Id: I24cce0cd73540e38d96f222df0a65414b16f6260
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-on: http://review.coreboot.org/2098
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 858b65028e02d4e2460a9f6033aec570006b9d0b
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Dec 31 17:56:22 2012 -0800

    cleanup some exynos5250 uart code
    
    This just cleans out some unused headers and tidies up the early
    serial code.
    
    TODO: Clean-up or replace FDT code, make "base_port" easier to
    configure.
    
    A bit of cleanup based on earlier patches.
    
    Change-Id: Ie77ee6d4935346e0053c09252055662f1a45d5f5
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2084
    Tested-by: build bot (Jenkins)

commit 801467f30ad08a69fa4a1ce84b5aeddabecd1185
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Dec 31 17:55:29 2012 -0800

    enable early serial console on exynos5250
    
    Change-Id: Ib16308c72b86860e80caec96202c42991a7b1d1a
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2085
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6a503b6a0f08bf4236c4c37d75c67182a7af4b02
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Dec 31 17:28:43 2012 -0800

    make early serial console support more generic
    
    This patch makes pre-RAM serial init more generic, particularly for
    platforms which do not necessarily need cache-as-RAM in order to use
    the serial console and do not have a standard 8250 serial port.
    
    This adds a Kconfig variable to set romstage-* for very early serial
    console init. The current method assumes that cache-as-RAM should
    enable this, so to maintain compatibility selecting CACHE_AS_RAM will
    also select EARLY_SERIAL_CONSOLE.
    
    The UART code structure needs some rework, but the use of ROMCC,
    romstage, and then ramstage makes things complex.
    
    uart.h now includes all .h files for all uarts. All 2 of them.
    This is actually a simplifying change.
    
    Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2086
    Tested-by: build bot (Jenkins)

commit 10c90d31264b5698320a1ac2666823532d110258
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Dec 27 13:30:55 2012 -0800

    update CFLAGS for armv7
    
    This updates $CFLAGS used for armv7. Most of them were just added
    to be consistent with what u-boot does. The important ones here
    are -march=armv7-a and -mthumb (to allow 16-bit Thumb instructions).
    
    I removed the hard float support because it got errors and
    coreboot should never use floats anyway. We're still having trouble
    with enums but I want to see how far it gets with this patch.
    
    Also, put the flags in a form that makes diffs easier to read. It's
    almost impossible otherwise.
    
    Finally, move some flags to the architecture Makefile, and
    rely on the fact that some are set for all architectures.
    
    Depends-On: I6f730d017391f9ec4401cdfd34931c869df10a9e
    Change-Id: Ia8a1ae22959933e06f7b996d1832cea40819f1ff
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2075
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 72a2eaf4d5364d5c5b7632b75d62c84f7bf490c8
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Dec 19 16:32:47 2012 +0100

    Rename mainboard_smi.c to smihandler.c
    
    This mirrors the naming convention of handlers in
    northbridge and southbridge.
    
    Change-Id: I45d97c569991c955f0ae54ce909d8c267e9a5173
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2058
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 64b364d1ec85f97fe948ba41cf8e7a3f43503829
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jan 3 08:26:09 2013 -0800

    Add the push default to 'make gitconfig'
    
    It's too easy to forget this and it's kind of important, so Just Add It.
    
    Change-Id: Ic7ab7658425a98d5d435bfef46f89cc6a56c7284
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2096
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ec8d35fe911ab35a5f40fd5b452f5463857b244a
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 2 17:47:11 2013 -0800

    armv7: pass bootblock offset from Kconfig into cbfstool
    
    This replaces a somewhat useless calculation used earlier (which
    always evaluated to 0) with an offset to specify the location
    of the Coreboot bootblock.
    
    Change-Id: Ib85aaccf138cebeb6bf8aedf82308861206dff48
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2094
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4c2245eb67b0eabf18fc9b6788bc05d962ef5e0e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 2 17:41:51 2013 -0800

    snow: Stuff to support building image with BL1
    
    This patch does two things which will take effect in follow-up
    patches:
    1. Add an intermediate Makefile rule for dd'ing BL1 into the
       coreboot.rom pre-image. This is modeled after a similar hack
       for the bd82x6x southbridge.
    2. Add a Kconfig variable, BOOTBLOCK_OFFSET, which will be used to
       pass the bootblock offset into cbfstool.
    
    Change-Id: I89da255dc903c387b754b06a11bb3439035ead87
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2093
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 454856b274ed81babdcea4b4ed5fb922fe0caf89
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Jan 2 17:29:00 2013 -0800

    add user-specified offset when creating armv7 cbfs image
    
    The "offs" provided on the command-line was not taken into account
    when creating an image for armv7...
    
    Change-Id: I1781bd636f60c00581f3bd1d54506f0f50bb8ad0
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2092
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 45256b3bfc18c2b1183238738d3f97474583b949
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Dec 27 14:06:05 2012 -0800

    Add (hacked-up) s3c24x0_i2c files
    
    These are needed for communicating with the PMIC on Snow. We'll
    tidy them up as we go along...
    
    Change-Id: I197f59927eae0ad66191862d052de2a8873fb22f
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2078
    Tested-by: build bot (Jenkins)
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>

commit d3c7530908463537c38d84d47d0c29a3bc5dac63
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Dec 27 15:11:27 2012 -0800

    import SPL files for board_i2c_{claim,release}_bus()
    
    This imports SPL (second phase loader) files from U-Boot. Most of the
    content of these files will eventually go away since they're fairly
    U-Boot specific. For now they are here to make Jenkins happy.
    
    Change-Id: Ib3a365ecb9dc304b20f7c1c06665aad2c0c53e69
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2081
    Tested-by: build bot (Jenkins)
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>

commit 8583ac390a23a09c4bf75b3b9a9f2294d0523d87
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Dec 27 15:23:57 2012 -0800

    armv7: create init.S for early ARMv7 init
    
    The old start.S file did a lot of work and had AP-specific #ifndef's.
    The new init.S will eventually contain only bare minimum generic ARM
    code for use by the bootblock. Processor-specific stuff and things
    that take place later in the boot process should go elsewhere.
    
    Change-Id: I7db0a77ee4bbad1ddecb193ea125d8941a50532b
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2083
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1e0e55615f86bb9237fa8f4d81158cbf25c65565
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jan 2 15:43:56 2013 -0800

    cbmem utility: support command line options
    
    The tool could print much more useful information than
    just time stamps, for example the cbmem console on systems
    that don't have a kernel patched to support /sys/firmware/log.
    
    Hence, add command line option parsing to make adding such
    features easier in the future.
    
    Change-Id: Ib2b2584970f8a4e4187da803fcc5a95469f23a6a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2091
    Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
    Tested-by: build bot (Jenkins)

commit 2c3f2609ca30f6303cec9639bacf1eb40aeee213
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Dec 19 11:22:07 2012 -0800

    Fix strcpy()
    
    'nough said. It was broken since 2006.
    
    Change-Id: I312ac07eee65d6bb8567851dd38064c7f51b3bd2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2062
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit f50fbe82ad0837ae7b30d7e2a5570ffc0dcc3950
Author: Aladyshev Konstantin <aladyshev@nicevt.ru>
Date:   Wed Dec 19 09:31:01 2012 +0400

    AGESA: Use `Flag=AGESA_SUCCESS` instead of `TRUE` in DMI related functions
    
    Success return value in DMI functions GetDmiInfoMain(..) and GetType4Type7Info(...) of AGESA vendorcode is "Flag = TRUE".
    
    This results in a failure of init late function:
    
        "agesawrapper_amdinitlate failed: 1"
    
    It happens because TRUE = 1 = AGESA_UNSUPPORTED.
    
    Replacing TRUE with AGESA_SUCCESS (= 0) fixes this problem.
    
    Only family f15tn does not have such bug.
    
    This patch just replaces TRUE with AGESA_SUCCESS, but maybe all DMI functions should be copied from Trinity family?
    
    Tested on Supermicro H8QGI board with 4 AMD Opteron 6234 processors (f15).
    
    Change-Id: I51bf91333c088a825b92d4a44d1ebe4380c8026c
    Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2070
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit c855dce8250b6c1820f682fb4a009d37e6d59826
Author: Aladyshev Konstantin <aladyshev@nicevt.ru>
Date:   Wed Dec 19 05:53:53 2012 +0400

    Supermicro H8QGI: Pass callout pointer to AmdReadEventLog function
    
    I have issues when AmdReadEventLog function tries to use BiosCallouts interface.
    So it is necessary to provide callout pointer to this function.
    
    Change-Id: I4080e5f07d5d28c41688b2a7deff944b7a0f7bf7
    Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/2064
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>

commit 34746a9c48165f89f80fb664d46b646ca9e44779
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Thu Dec 20 18:42:00 2012 +0100

    rs780: Implement `rs780_internal_gfx_disable` and add .disable pcie_ops
    
    That code will be used to disable the internal GFX card and enable the
    external PCIe card.
    
    The following lines from function `rs780_internal_gfx_enable()` are
    taken and reversed.
    
    	/* Disable external GFX and enable internal GFX. */
    	l_dword = pci_read_config32(nb_dev, 0x8c);
    	l_dword &= ~(1<<0);
    	l_dword |= 1<<1;
    	pci_write_config32(nb_dev, 0x8c, l_dword);
    
    It has been tested on the M4A785T-M with the following card inside the
    PCIe 16x slot:
    
      02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2)
    
    Change-Id: I7bd412b987fde98c97464175e2c7a384a8f0fb84
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-on: http://review.coreboot.org/2065
    Tested-by: build bot (Jenkins)

commit 9a0e3e2fc205381746875bee5296777b608bea54
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Thu Dec 20 18:45:53 2012 +0100

    M4A785T-M: Add support for external GFX.
    
    This commit enables the external graphics card.
    In order to work, the internal graphic card has to be
      disabled, that is done in src/device/device.c through:
      vga_onboard->ops->disable(vga_onboard);
      which calls the RS780 disable operation introduced in the following
      commit: "rs780: add .disable pcie_ops"
    
    This commit was tested with and without the following card:
      02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2)
    
    Thanks Aladyshev for the pointer(in the #coreboot IRC channel on Freenode servers):
      Dec 20 19:43:32 <Aladyshev>	If you list your internal card in devicetree.cb,
      coreboot will distinguish external and internal VGA and choose external one
    
    Change-Id: I92e59dffd158db096a6e99d1ef6e2e248fef933c
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/2067
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6c6b2e8cba863cb39c82ee269c84a32f085c1a19
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Thu Dec 27 15:23:03 2012 -0700

    Add AMD Hudson blobs by CONFIG_REQUIRES_BLOBS dependency
    
    If a 3rd party blob option is selected, make sure that it makes the
    user select CONFIG_USE_BLOBS as otherwise the build will fail.
    
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Change-Id: I04429f23137946525c8577dd9c979bd4a0d17cdc
    Reviewed-on: http://review.coreboot.org/2080
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6c212ac483e208f74acc19c537ddb0643056a762
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Dec 27 15:22:27 2012 -0800

    remove obsolete include paths from INCLUDES
    
    Change-Id: I621fd49b1f1b96ef388c61ff1abc2130ad2163a5
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2082
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f4c35083d0e9c2413eff900ac031dd47753ad847
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Dec 27 14:15:51 2012 -0800

    import i2c header from u-boot
    
    This just imports a header. We may wish to modify the i2c interface
    and/or unify it with the smbus interface we currently have.
    
    Change-Id: I314f3aef62be936456c6c3e164a3db2c473b8792
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2079
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e293440faaf882dbee4c85b8287fe9e21d91f70f
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Dec 27 13:33:36 2012 -0800

    corrections for MAX77686 config variable
    
    Fix some minor discrepancies which prevented the MAX77676 from
    getting compiled in properly.
    
    Change-Id: Ib29136da6c15a4bdb24926a91729431c507cd209
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2076
    Tested-by: build bot (Jenkins)
    Reviewed-by: Hung-Te Lin <hungte@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f1dfb2eb94f86a2168776d9ea5b098d25e5b369c
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Dec 27 13:50:32 2012 -0800

    move iRAM config variable to exynos5250 Kconfig
    
    Since these don't seem very generic and depend on the BL1, let's
    move them to the CPU-specific Kconfig.
    
    Change-Id: I33059b7db30d35a1853918a580f312e50a3499fa
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2077
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 37a85163700f7183c786bab1004ff47cc90e9d9e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Dec 17 20:41:32 2012 -0800

    Simplify romstage.ld for armv7
    
    This is still a work-in-progress, but it seems to work better than
    before and is less complicated...
    
    Change-Id: I6f730d017391f9ec4401cdfd34931c869df10a9e
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2041
    Tested-by: build bot (Jenkins)

commit 32675175efe5ae2101bcdf23e862c51f8f3306d1
Author: Aladyshev Konstantin <aladyshev@nicevt.ru>
Date:   Tue Dec 18 21:52:46 2012 +0400

    Supermicro H8QGI: Add onboard VGA to devicetree.cb
    
    Supermicro H8QGI has integrated Matrox G200 16MB DDR2 graphics.
    List it in devicetree.cb to mark it as onboard VGA to coreboot.
    This change makes menuconfig option "Use onboard VGA as primary video device" work.
    
    Change-Id: Ia6b9f60e3ae705689f22babd544ad6e628a85df1
    Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/2042
    Tested-by: build bot (Jenkins)
    Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit c94e8cf2e178c99290c6cd15a144874a3078bede
Author: Aladyshev Konstantin <aladyshev@nicevt.ru>
Date:   Tue Dec 18 23:01:14 2012 +0400

    Supermicro H8QGI: fix bus_sp5100[] clear in get_bus_conf.c
    
    Fix little mistake in get_bus_conf code
    
    Change-Id: I8c09e501082caa0a20266b007c0744630a356de0
    Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/2046
    Tested-by: build bot (Jenkins)
    Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3d63b0a9656d5982dd0e9eef652c6cc1e8f8eaa3
Author: Aladyshev Konstantin <aladyshev@nicevt.ru>
Date:   Wed Dec 19 00:58:35 2012 +0400

    BiosCallOuts: Replace REQUIRED_CALLOUTS define with flexible variable
    
    Size of BiosCallouts[] struct can be calculated as:
    
            CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
    
    There is no longer need for REQUIRED_CALLOUTS define.
    
    Originally that change was done for AMD Persimmon in
    
            commit d7a696d0f229abccc95ff411f28d91b9b796ab74
            Author: efdesign98 <efdesign98@gmail.com>
            Date:   Thu Sep 15 15:24:26 2011 -0600
    
                Persimmon updates for AMD F14 rev C0
    
    without deleting the define. This was ported to some of the other
    boards and for some the define was not removed.
    
    The AMD Inagua, Parmer and Thatcher boards were already adapted but
    the define was left in. So just remove it for those.
    
    Tested on Supermicro H8QGI.
    
    Change-Id: Ia09795579a1170fa20ab94a30feb1af6821153d2
    Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/2049
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit b01097e0fe03b7dc81eadd898ff380b57f291852
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Dec 14 15:58:15 2012 +0800

    USBDEBUG: Enable the EHCI in AMD Southbridge
    
    Since SB800, USB2.0 debug port is dev 0x12, func 2.
    
    Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1880
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit ceb82da99f9b9bc0629b6e3689dd19c988f4cd0b
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Dec 20 14:24:08 2012 -0800

    add a return type to test function used by xcompile
    
    This fixes a minor bug that could cause testcc to fail unexpectedly.
    
    Change-Id: Ib75d343104b6937682c05acf5232596aac83f105
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/2068
    Tested-by: build bot (Jenkins)

commit ec3daf7e08b4c42b45fc2c84b92820af6688e11b
Author: Aladyshev Konstantin <aladyshev@nicevt.ru>
Date:   Tue Dec 18 23:15:55 2012 +0400

    Supermicro H8QGI: Fix routing from 16 to 55 in ACPI table
    
    H8QGI board has 2 IO-APICS with 56 IRQ’s:
    
    IOAPIC[0]: GSI  0-23   - SB700 southbridge
    IOAPIC[1]: GSI 24-55   - RD890 northbridge
    
    `gDefaultApicDeviceInfoTable[]` structure in northbridge code
    
        vendorcode/amd/cimx/rd890/nbIoApic.c
    
    has IO-APIC interrupt mapping for HT and IOMMU set to last 31
    IRQ pin (24+31=55).
    
        CONST APIC_DEVICE_INFO gDefaultApicDeviceInfoTable[] = {
        // Group  Swizzling   Port Int Pin
          {0,     0,          31},   //HT
          {0,     0,          31},   //IOMMU
        […]
    
    Also the same value (55) can be found in original Supermicro BIOS ACPI DSDT.
    
    Change-Id: Ie26da1f773716d1b7f5f5f884050ae799afc0b7e
    Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/2047
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7299c139c508f64f1bfb3dd35bbe33688eada45c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Dec 14 11:45:08 2012 -0800

    PDcurses: Delete automatically created (and unused) files
    
    Change-Id: Iefe0872d36c3a5d8ef42e62325838b7f09b389d2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2034
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 69e3de33935f8c9808770c3197f536a2c34395b4
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Dec 20 09:14:09 2012 +0100

    libpayload: Another usb fix
    
    Change-Id: I91b18fadbf17562f8b48e233631653f2a18c037c
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/2063
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit e09f7ef00af02234a9e12724765c71ee29be70ec
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 18 14:27:50 2012 -0800

    Add back dummy free()
    
    GNU CC coverage needs free() and it's highly desirable to leave
    the code as genuine as possible.
    
    Change-Id: I4c821b9d211ef7a8e7168dc5e3116730693999c6
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2051
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 5fa7ea419bf619bb8a2e3bcb48037726947417d9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Dec 19 19:08:45 2012 +0100

    libpayload: fix USB
    
    A "far" modifier sneaked into the USB driver, but gcc
    doesn't understand it.
    
    Change-Id: I5c67bd55eabce467e1aa107c95c1db2518af7b0e
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2059
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit ebb89e3a8ccdffdb2057b4ae8bea1df9352b3f54
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Dec 19 19:55:21 2012 +0100

    No need to contact AMD for firmware anymore
    
    We ship it in the 3rdparty repository.
    
    Change-Id: Ida52bc7e813f8468910c4ea7838ebb863c52b88a
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2060
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 7a33442159a43ffc8fd27f36975e72f82fde64e2
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Dec 19 10:58:08 2012 +0100

    Remove colors from build system output
    
    While "payload none" is undesirable for instant flashing,
    assume that it was a conscious user choice.
    
    (more immediate: jenkins isn't happy with escape sequences)
    
    Change-Id: I9958b34a037b4d10bb7dba893335a63917623a70
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2055
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c62b69cd02f863fd1319401735bd2cb50fe856ae
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Wed Dec 19 13:49:20 2012 +0400

    libpayload: improved UHCI TD debugging
    
    Improved USB debugging for EHCI by enhacing dump_td
    to dump all chain information
    
    Change-Id: I8c667b43e09c39ff12aafbd779474efd652bd80f
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/2054
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit cf7b63ff65270d83540828cfbd2314b5d82dcb9d
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Wed Dec 19 14:10:05 2012 +0400

    libpayload: improving OHCI TD/ED debugging
    
    Improving USB debugging for OHCI by enhacing dump_td
    and adding dump_ed function to dump all chain information
    
    Change-Id: Ia8b2a9b53e79b1f280fd12ea0d9233fc875e0b57
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/2056
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit ea9a1f60177bad3e8c63f030f55dec87d0dd245c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 18 14:25:56 2012 -0800

    Get stdint.h in sync between ARMv7 and x86
    
    - add s8, s16, s32 types to x86
    
    Change-Id: Ib9c260fc4f72029492f2d935dbb822cc3ff83cc4
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2050
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 5056b6e612569b202c96a8a54da90879f118b7d5
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Sat Dec 15 13:24:02 2012 -0700

    libpayload: Check if serial console h/w is present before using
    
    The serial_io_havechar() and serial_io_getchar() functions will
    always see keystrokes available if the serial hardware isn't
    actually there. We will still output chars to non-existant
    hardware to allow virtual hardware to capture them.
    
    Change-Id: I04e85157b6b7a185448abab352b5417a798a397a
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2040
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 6bf11cf50c2b682f8c09a53af774588123b250b6
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Tue Dec 11 13:08:07 2012 -0700

    libpayload: Use usb_debug() to show USB messages
    
    Previously printf()'s were used to show USB messages
    which results in lots of USB information being shown
    when it isn't needed. This will now use the usb_debug()
    printing funtion that already exists in usb.h.
    
    Change-Id: I2199814de3327417417eb2e26a660f4a5557cb9f
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2044
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 8024b655507441646b2158fc61532364cbe65972
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Mon Dec 17 14:40:47 2012 -0700

    libpayload: Update configs/defconfig file
    
    Several settings have been added to the config without any
    changes to the default settings file.
    
    Change-Id: Iaf9259d77fb3c4645fc68bc0108de79c0298f0a1
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2039
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c5f4926cb92c3030e67202faa828c9539e20a01f
Author: Martin Roth <martin@se-eng.com>
Date:   Fri Dec 14 19:17:55 2012 -0700

    Fix a compare against undefined variable in acpi.c
    
    Initialize the pointer fadt to NULL to prevent a later comparison
    (if (fadt == NULL)) when the pointer had the *possibility* of never
    having been initialized.
    
    Change-Id: Ib2a544c190b609ab8c23147dc69dca5f4ac7f38c
    Signed-off-by: Martin Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2037
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 9f0431726353a5eaa259776ab43e57163b74605e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Dec 14 13:06:49 2012 -0800

    libpayload: add kconfig.h
    
    This implements the linux kernel's macros to handle
    boolean CONFIG_ variables more easily.
    
    Change-Id: I595f9db652d019fe72e231111258ec609bec9d4e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2036
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8af0d03fd49f9c88db98ef7b3c2d95bf1cd0f319
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Dec 14 13:05:21 2012 -0800

    libpayload: Initial ARMv7 port
    
    This compiles, but it's not tested yet.
    
    Change-Id: I2f73a814649aa36c39af3e77cefd8a968671f5c0
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2035
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f6935a006a6ffe57413877093035cdc1a020e7bd
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Dec 14 11:42:57 2012 -0800

    libpayload: rename i386 to x86
    
    Change-Id: Ia9170bd3d04e76dbf9321ca7ea4be23b5e468d21
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2033
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9aaf7d17bbb8140ad9091d2435bdffa0d241fb56
Author: Martin Roth <martin@se-eng.com>
Date:   Fri Dec 14 12:42:28 2012 -0700

    Fix broken scan-build
    
    Adding support for the multiple architectures broke the scan-build
    option.  The new CC setting needed to be wrapped and not run again
    when doing the scan-build second pass.
    
    Change-Id: Ieb418f51d44803308040926a4154fb5fdc3ba67f
    Signed-off-by: Martin Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/2031
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bb71c91db18ce60a6589ff563c1a23d8dd1e7e7f
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Dec 14 15:43:12 2012 +0800

    AMD S3: Rename generated s3.rom for make clean
    
    Add prefix coreboot_ to let make clean find it and delete it.
    
    Change-Id: Ieba9c0e7ca3d2afec311d64159b22746ba5825c4
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2029
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a182cbdd62f9f5b2aa00611fb12a05c6340a0d1c
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Dec 14 15:44:59 2012 +0800

    cbfstool: Align the column of build hint message.
    
    Change-Id: Ic217450411d7fa4e6c3a053be62d7c948dc7145e
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/2030
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9915b37f10828874dcc699bfb0298303fbc356c8
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Fri Nov 30 17:15:36 2012 -0700

    coreinfo: Build libpayload from coreinfo makefile
    
    Build libpayload and install it in the coreinfo directory.
    Allows coreinfo to be built with a single make command.
    
    Change-Id: I56982265555aae16e482b0a0040989c1f5317423
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1995
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 0b97f2978f389a51953da11224a525b470ae82b4
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Nov 29 10:18:53 2012 -0700

    libpayload: increase the default heap size
    
    Coreinfo uses the default heap size and will blow up
    if the USB keyboard is used.
    
    Change-Id: I2ffae330ec34167b2ccfbd4c428e3e8306230f44
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1980
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 15a2c8f82769c67684d0a6eac05be48487599dfc
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Dec 5 17:22:47 2012 -0700

    coreinfo: changes to get the USB keyboard working
    
    A call to usb_initialize() was needed. Also needed to set several
    curses flags. One to prevent keystrokes echoing to the display,
    and one to allow extended keystrokes (like the KEY_F(n)) to be
    seen when calling getch();
    
    Change-Id: I495b42055a54603e4efb92b2845051434d88432d
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1983
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit e899e518d88f2f48927fba9006d02ea9e1e5a797
Author: Martin Roth <martin@se-eng.com>
Date:   Wed Dec 5 16:07:11 2012 -0700

    SB800: Add IMC ROM and fan control.
    
    Add configuration for AMD's IMC ROM and fan registers for cimx/sb800
    platforms.
    
    - Allows user to add the IMC rom to the build and to configure the
      location of the "signature" between the allowed positions.
    - Allows for no fan control, manual setup of SB800 Fan registers, or
      setup of the IMC fan configuration registers.
    - Register configuration is done through devicetree.cb. No files need
      to be added for new platform configuration.
    - Initial setup is for Persimmon, but may be extended to any cimx/sb800
      platform.
    
    Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae
    Signed-off-by: Martin Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1977
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit a17fd056d4b4fb373f7821ccca74a80de14fc618
Author: Martin Roth <martin@se-eng.com>
Date:   Wed Dec 5 16:09:35 2012 -0700

    Rename generated hudson_romsig.bin for make clean
    
    The file generated when the IMC or XHCI binaries are included in the rom
    was named $(obj)/hudson_romsig.bin.  The problem with this is that it
    doesn't get deleted when the user does a make clean.
    changing the name to coreboot_hudson_romsig.bin makes this happen.
    
    Change-Id: I19a40042fbf0f7b5633d7b35339c05ed90d3243b
    Signed-off-by: Martin Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1978
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3aef7b4f63b3870e3699d5408d0fb8917c5eb135
Author: Martin Roth <martin@se-eng.com>
Date:   Wed Dec 5 15:50:32 2012 -0700

    Fix SPI BAR special case in lpc_set_resources
    
    There was already a special case for the SPI base address in
    lpc_set_resources for southbridge/amd/cimx/sb800 and
    southbridge/amd/agesa/hudson, but it needed to be modified
    to keep from killing the IMC rom during initialization.  As
    soon as the BAR is disabled by setting the new base address,
    the IMC dies.  The fix is to make sure it's still enabled
    when setting the new base address instead of setting the new
    address then re-enabling it.
    
    Change the name SPIROM_BASE_ADDRESS to SPIROM_BASE_ADDRESS_REGISTER
    to more accurately describe what we're using.
    
    Change-Id: I216d75b722c4332c239d487111a9880eabf59e91
    Signed-off-by: Martin Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1975
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3316cf2ff80f379b609115f375f73ef4b9e7d8f4
Author: Martin Roth <martin@se-eng.com>
Date:   Wed Dec 5 16:22:54 2012 -0700

    Claim the SPI bus before writes if the IMC ROM is present
    
    The SB800 and Hudson now support adding the IMC ROM which runs from the same
    chip as coreboot.  When the IMC is running, write or erase commands sent to
    the spi bus will fail, and the IMC will die.  To fix this, we send a request
    to the IMC to stop fetching from the SPI rom while we write to it. This
    process (in one form or another) is required for writes to the SPI bus while
    the IMC is running.
    
    Because the IMC can take up to 500ms to respond every time we claim the
    bus, this patch tries to keep the number of times we need to do that to a
    minimum.  We only need to claim the bus on writes, and using a counter for
    the semaphore allows us to call in once to claim the bus at the beginning
    of a number of transactions and it will stay claimed until we release it
    at the end of the transactions.
    
    Claim() - takes up to 500ms hit
        claim() - no delay
            erase()
        release()
        claim() - no delay
            write()
        release()
    Release()
    
    Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed
    Signed-off-by: Martin Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1976
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cf5aaaf1d25429fa6270c7d91a3e072dcf989079
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 11 17:35:30 2012 -0800

    cbfstool: Catch failing parse_elf_to_payload()
    
    Otherwise cbfstool will segfault if you try to add an x86
    payload to an ARM image.
    
    Change-Id: Ie468005ce9325a4f17c4f206c59f48e39d9338df
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2028
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 935a942e4abddb84e7e1ae60f8386a814d56db67
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 11 15:23:45 2012 -0800

    Fix ARMv7 payload handling
    
    cbfstool was called with the wrong parameters
    
    Change-Id: I405d0fd7c84b46da3c98a36fd19ef0034dc175cf
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2022
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0cc9f41f469980b8393c05c31e3884630b7679cd
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 11 16:07:16 2012 -0800

    Fix maxim max77686 driver
    
    With driver-y going away, the current driver code didn't get
    compiled in with upstream.
    
    Change-Id: I9bff45a35c995888a482bdc22a1573f6bfb88211
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2027
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a7198b34ccf120df2a9e5b9f104812e96916ad08
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 11 16:00:47 2012 -0800

    Add support for Google Parrot Chromebook
    
    AKA Acer C7 Chromebook
    
    See http://www.google.com/intl/en/chrome/devices/acer-c7-chromebook.html
    for more information. Thank you to Sage Electronic Engineering, LLC for
    making this possible! http://www.se-eng.com/
    
    Change-Id: Ic4e4d50045a82cbb82e1dea3cd5a04525a648612
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2026
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0e81b62638bbc7ee1731034dd041f9756a5bd0fb
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 11 15:59:08 2012 -0800

    Update 3rdparty to it's HEAD
    
    Change-Id: I51137bfb3a25e24028b8a05a39339cc67c784980
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2025
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d8a5fd2321eb31ad976bf4d59195b47ac636489a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 11 15:51:47 2012 -0800

    Add support for ENE932 EC w/ Compal firmware
    
    Change-Id: I19b03139e7edfee6ff3e0bcef735bb36bfadc354
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2024
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f89e6b22c0c42983f94316d29cf4f2f73a6d2b84
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Dec 10 16:13:43 2012 -0800

    Add minimal mainboard support for snow
    
    This is the minimal set of sources that allow the board to build.
    These need to be filled in with actual code. But if we get these in upstream
    we can stop working against a WIP patch.
    
    Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2018
    Tested-by: build bot (Jenkins)

commit 3600e960b603a610064c6024c275e149944df1ca
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 11 12:49:32 2012 -0800

    Fix UART8250 console prototypes
    
    and disable IO mapped UARTs on ARMV7 per default
    
    Change-Id: I712c4677cbc8519323970556718f9bb6327d83c8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2021
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit de48f0fd4213f8d0e2c71cbd3929e629fd76eb96
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 11 11:20:35 2012 -0800

    Fix up Maxim MAX77686 driver
    
    ... to fit into the naming convention
    
    Change-Id: I4a7d81c4d6674d001fc831df863bd2343f6c636f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2020
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 0dbb329b7d3edf9c9ac426e31109bdc14b1b7bf2
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Dec 10 21:27:02 2012 -0800

    Remove un-needed i2c.h include
    
    When we need i2c for this cpu we will use the coreboot
    smbus code.
    
    Change-Id: I4ba4cc9ae10e5ca830d621ee9c8d9f7bd2129e2f
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2019
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ae06e61ee388c02f4c446cb6af65980070de87ce
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Dec 10 14:51:09 2012 -0800

    Correct the location of the include file
    
    The max include file is in src/drivers/power.
    
    Change-Id: I2e663b472cade17fc50edbb449c0e54fd4a991eb
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2017
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 84de16e299ed4e68be9fc2bd49fe2de132b239f0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Dec 10 13:57:43 2012 -0800

    Removed an unneeded include file
    
    This file builds fine without including arch/types.h
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Change-Id: Icd38cf429576a2a1a33ebca84389526feddfc169
    Reviewed-on: http://review.coreboot.org/2015
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 593f577ffab9663fdf95fc7cc0b5f5bc623b52ae
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Dec 7 15:50:40 2012 +0100

    libpayload: Fix use of virtual pointers in sysinfo
    
    In I4c456f5, I falsely identified struct cb_string.string as a pointer
    which it is not. So we don't need phys_to_virt() here.
    
    Change-Id: I3e2b6226ae2b0672dfc6e0fa4f6990e14e1b7089
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1987
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c95f2f5615963deb911684b321c3e14dd2edd4d9
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Dec 7 15:45:10 2012 +0100

    libpayload: Fix renaming of REG_CLASS_DEV to REG_SUBCLASS
    
    REG_CLASS_DEV was renamed to REG_SUBCLASS.
    
    Change-Id: I4af476b953b544f680337d815889564f016563eb
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1986
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1224626e3b6eef255b9faac60a18807acebc1f3d
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sat Dec 8 23:10:08 2012 +0100

    Revert "armv7: use __cpu_to_le32 for endianness of reset vector instruction"
    
    This reverts commit 67ce04ea9a9c7e30dd96b9f36a938b51655e8a44
    
    Change-Id: I2781c9275c03bcabf0211e1b6cd1aa8f13005ae0
    Reviewed-on: http://review.coreboot.org/2014
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 198d23c119bdf375ffa7ef57b6172755d6490213
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Dec 8 08:02:44 2012 +0100

    crossgcc: Normalize library directories
    
    Various of the build scripts used upstream can't cope with
    multilib library paths (eg. lib64), so move things to a place
    where they can find them, if such paths are used.
    
    Change-Id: I0dd9bba9a9eadd92d8704157e868fb37c715ee91
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/2013
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5d01b765e35d8468f396e55c63754491b3af1587
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Fri Nov 30 17:04:58 2012 -0700

    coreinfo: Make better calls to libpayload build scripts
    
    Set LPGCC and LPAS so that CC and AS are maintained.
    Clean up the makefile order to check for .config to be easier to
    read.
    Use objcopy instead of strip and keep the debug symbols file.
    
    Change-Id: I95d6b7a0e3a99a142d3fd6e2ecc61de1d4412402
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1994
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bb9490a4b0fbc1a46de84708d9c59f5028c194ae
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Fri Nov 30 16:22:51 2012 -0700

    Clean up libpayload lpgcc and lpas scripts.
    
    lpgcc and lpas are called by payload Makefiles to properly
    build and link with libpayload.
    
    Made lpas use the proper crosscompile AS, as lpgcc does with CC.
    Added V=1 support to help users debug the build.
    Fix basename $CC and $AS expansion.
    
    Change-Id: Ia4dc8ba53ba7565521a79f1520155f3307b09f85
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1993
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit da1ef02e904536446f0fb06f024ac1faede39d10
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Dec 7 17:24:06 2012 -0800

    stddef.h: move to generic code
    
    stddef.h should be fairly generic across all platforms we'd want to
    support, so let's move it to generic code.
    
    Change-Id: I580c9c9b54f62fadd9ea97115933e16ea0b13ada
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2007
    Tested-by: build bot (Jenkins)

commit 52db0b984523047da19ca3b41558b9dbf45abad7
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Dec 7 17:15:04 2012 -0800

    WIP: Initial ARMv7 architecture implementation in coreboot
    
    The first ARMv7 CPU we're going to support is the Exynos 5250
    used in the Google Snow ChromeBook.
    
    Change-Id: I4de8433bbc6202eb8fef2556a11186a3376d411b
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2004
    Tested-by: build bot (Jenkins)

commit 509f77277cfccdae897f0d369672ce0818ecdf88
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Dec 7 17:31:37 2012 -0800

    WIP: Add support for non-8250 built-in UARTs
    
    Change-Id: I5b412678bb8993633b3a610315d298cb20c705f3
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2011
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bb626346ea32479cab9801c183317a383c07196f
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Dec 7 17:26:41 2012 -0800

    cbfs_core.h: support for ARMv7 CBFS master header
    
    Change-Id: I59626200b4a92d90b46625f8dcc2ed28e6376e46
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2008
    Tested-by: build bot (Jenkins)

commit 9fe20cb3814df88f181648860102a9da249a4da1
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Dec 7 17:18:43 2012 -0800

    WIP: Initial support for Samsung Exynos 5250 ARM CPU
    
    Samsung SoC files, including Exynos5 (a Cortex-A15
    implementation). Since this is an SoC we'll forego the x86-style
    {north,south}bridge and cpu distinction. We may try to split some
    stuff out before the final version if prudent.
    
    Change-Id: Ie068e9dc3dd836c83d90e282b10d5202e7a4ba9b
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/2005
    Tested-by: build bot (Jenkins)

commit 747127d50545c1fbd0dcc10baacc742d3151ddfe
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Mon Dec 3 22:16:29 2012 -0700

    Limit SPI device debug prints with CONFIG_DEBUG_SPI_FLASH
    
    Fix debug printks which were not using CONFIG_DEBUG_SPI_FLASH,
    which would cause long delays durring boot when SPI devices
    were written.
    
    Change-Id: I99fc3d5f847fdf4bb98e2a0342ea418ab7d5fc54
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1965
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 91f1423cac0460ab79492a9c167765359b9dd3e2
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Dec 7 16:55:12 2012 -0800

    Fix Yabel compilation on non-x86 platforms
    
    Mostly preventing inb/outb being used on non-x86
    
    Change-Id: I0434df4ce477c262337672867dc6ce398ff95279
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2002
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4c4dd93be7fc7d7ae0d5802fe15f8e5e533a6872
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Dec 7 17:28:02 2012 -0800

    Only include libgcc wrappers on x86
    
    ARM does not need them, and they're causing trouble
    
    Change-Id: I6c70a52c68fdcdbf211217d30c96e1c2877c7f90
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2009
    Tested-by: build bot (Jenkins)

commit bca9b9d53e9d742d313f028f34aa4b153f7de469
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Dec 7 17:01:21 2012 -0800

    Makefile cosmetics
    
    align architectures
    
    Change-Id: Ie3fe29d830d45e76c183411c04598e82b4b3a010
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2003
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 2110c97a63c3122a1ae84d109cecb91b1fc7cd24
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sat Dec 8 00:50:44 2012 +0100

    Allow PCI option rom execution only on systems with PCI support
    
    ... on all other systems it will fail terribly ;-)
    
    Change-Id: I7f8d10b71b2dbc798b28aee7c36872685c793fd8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2001
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 10099070caaae79348673adf23ce441a566e70fd
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sat Dec 8 00:38:40 2012 +0100

    abuild: Select correct cross compiler for ARMV7 architecture
    
    Change-Id: Ia0dce25a4271299757654ba46baafe6a6673c6d2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/2000
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 16bd789a735015470b431a1f3c9b5cce0ac23e87
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Dec 7 23:57:01 2012 +0100

    buildgcc: Clean up PATH handling
    
    This puts our installed binaries first in the search path, which is what we
    really want.
    
    ... and remove some dead code
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I91725af6b0fc486bd943d8e25cdce8d3e2503b3c
    Reviewed-on: http://review.coreboot.org/1998
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit a348d901c7536023033d23189c15896340a0a23d
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Dec 7 23:50:01 2012 +0100

    buildgcc: drop hack to build gcc trunk versions
    
    The focus of the script is to create a supported cross toolchain,
    and with GOLD and LTO being released features, we don't need this
    anymore.
    
    Change-Id: Ieb7752ce6e143d93414aba5887190f853cbd5a4b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1997
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 969cd931f8461ad3ee9015f8595e5d7872f45b94
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Dec 7 13:13:53 2012 +0100

    buildgcc: Remove mingw32 hacks
    
    After patching them to be more flexible, an even better approach was found:
    With this change libgcc isn't built at all on mingw32 platforms, so the
    system headers aren't necessary anymore.
    
    Now x86_64-pc-mingw32 builds, too.
    
    Change-Id: Ic1406588669d87aee1bcf40ff67af77f2a6ac283
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1985
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Raymond Danks <ray.danks@se-eng.com>

commit 17b24d3fefa16486a0433f68bdd6c68f22b73379
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Dec 7 13:13:26 2012 -0800

    abuild: produce valid junit files
    
    If no valid cross compiler is found, the junit file produced
    by abuild is invalid, missing the closing </testcase> tag.
    This breaks proper reporting in Jenkins of our ARM board at
    this moment.
    
    Change-Id: I94bfc7f334d33ceeb53451a7c5125058c1f33bd4
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1992
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit 1b0c3526751b750e3cbfaf317e1eaf8d39fe3ba8
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Dec 5 17:26:03 2012 -0700

    coreinfo: change the foreground/background colors
    
    The default curses library changed from tinycurses to
    PDCurses. PDCurses fails to fill the entire active screen with
    the assigned background colors when it writes 'blank' chars.
    This will allow the menues to look better until I resolve that.
    
    Change-Id: I70b5331d16dd0abaa1f0b02b725571844b7ac15e
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1984
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit cbf3d407b8d943395f67d023795effe8f307b8c9
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Dec 5 08:20:12 2012 -0700

    Add function to map vendor/device to generic VBIOS IDs
    
    Change-Id: I4d7c4ec2b91c97eacf96770c150c2b9a61309053
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1982
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0a90861ff2308cf03928dbe5b7c4d3dfde82ceb4
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Tue Nov 27 16:02:41 2012 -0700

    libpayload: Don't let USB/PC/serial keyboards overwrite each other
    
    Change-Id: I75c0066cf737e0cecac056487215622e2b3d4467
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1981
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 67ce04ea9a9c7e30dd96b9f36a938b51655e8a44
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Dec 6 18:21:21 2012 -0800

    armv7: use __cpu_to_le32 for endianness of reset vector instruction
    
    Change-Id: Ic8f35d7172f6afa933c24774177ed65e6dc579a0
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/1979
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c2d5a1651ef00542345adc4f91a096d8d04000a8
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Dec 6 14:25:27 2012 -0800

    Disable CMOS_POST and IO_POST on non-PC80 systems
    
    Because they use outb instructions, they are bound to fail
    on non-PC80 systems like ARM.
    
    Change-Id: I679ac6c0964c06c369cc90556529bb6f629d56f9
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1974
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)

commit fecd26f208cfa4d90748d32dc35d34e5e9a8bda4
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Dec 6 12:14:49 2012 +0100

    crossgcc: Generalize matching for the mingw case
    
    With this change, i686-pc-mingw32 is acceptable, too.
    
    Change-Id: I924f7ece84e77dc751e5e0318bac1ebc72d39d21
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1972
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 399486e8fb8f5b402f1833e496dbed11aa0ac669
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Dec 6 13:54:29 2012 -0800

    Unify assembler function handling
    
    Instead of adding regparm(0) to each assembler function called
    by coreboot, add an asmlinkage macro (like the Linux kernel does)
    that can be different per architecture (and that is  empty on ARM
    right now)
    
    Change-Id: I7ad10c463f6c552f1201f77ae24ed354ac48e2d9
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1973
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c269a9b51cac8e6e24cd98b46543b89e1b836bf8
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Thu Dec 6 11:30:33 2012 +0800

    driver/spi: Add support of MX25L3235D
    
    Tested on Thatcher.
    
    Change-Id: I648171ba0d03be1e984c182f6d0f082241e3f51c
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1971
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cb0895470ed92fd31f5d17a0bae92a34ae8122af
Author: Stefan Reinauer <reinauer@google.com>
Date:   Wed Dec 5 17:42:43 2012 -0800

    Fix xcompile (again)
    
    After cherry-picking change 1679 it became apparent that there was a small
    typo in my last xcompile change. With this patch applied, I can now compile
    the first few files in the tree before GCC dies with
    
    In file included from src/arch/armv7/lib/romstage_console.c:23:0:
    src/include/uart.h:31:6: error: redundant redeclaration of 'uart_init' [-Werror=redundant-decls]
    
    Now for some fun...
    
    Change-Id: Idbb07f609e4a240238964cc16714639f5ef09914
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1970
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit e42133f33e94a5c55aa98d2a6432e10108232846
Author: Stefan Reinauer <reinauer@google.com>
Date:   Wed Dec 5 17:12:10 2012 -0800

    Fix xcompile for ARMv7 and our cross toolchain
    
    The naming of architectures is highly inconsistent between
    the different components of the toolchain. In binutils, the
    file architecture is elf32-littlearch. In GCC it's armv7a-eabi.
    This patch adds support for different BFD / GCC names
    
    Change-Id: Ib644f71e8d8b4964adec73eed23921d3838e8aa7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1969
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 6edb729cee4ebeb06aa4db54e682cc0a39ac9fa1
Author: Stefan Reinauer <reinauer@google.com>
Date:   Wed Dec 5 17:09:01 2012 -0800

    Drop ARCH_ARM in favor of ARCH_ARMV7
    
    The ARM architecture is really many architectures, and most
    of them need their own toolchain. After discussing with Ron
    and David, we decided that we're going to call the architecture
    of our ARM board armv7.. This patch cleans out the remainders
    of ARCH_ARM in the tree and moves on to consistent ARMv7 naming.
    As of now, we only support little endian ARMv7 CPUs. We can
    fix that for big endian if/when it comes our way.
    
    Change-Id: Id70c7ef615f600e4d09961d811e7ac974fce4811
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1968
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4266b92db06eae5c6aa3c8cc8eb2b873f40ecbba
Author: Stefan Reinauer <reinauer@google.com>
Date:   Wed Dec 5 16:18:32 2012 -0800

    crossgcc: Fix buildgcc on Mac OS X
    
    Once again, the compiler we use on Mac OS X had trouble compiling GCC.
    Switch to llvm-gcc because that one works with Xcode 4.5.2 and gcc 4.7.2.
    Also drop the -W flags not known to Xcode from the iasl Makefile, and
    drop the --remove-destination option from the copy, because that does not
    exist on Darwin.
    
    Change-Id: I9f978f65b5ae7edee2ecdcab337772e7a692bd9b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1967
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0f5caa26cb0b25ae452a14aedc71f5c137850a4e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Nov 30 19:16:50 2012 -0800

    Conditionally include mc146818rtc in console.c
    
    get_option() is used to get a config option (debug loglevel) from
    CMOS. However, not all machines have CMOS, so define a dummy inline
    function that will return an error code so the caller (console_init())
    will use the default loglevel.
    
    Change-Id: I6adf371d79164178f40a83f7608289a6a7673357
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/1962
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dab4238d102724c3d050e6bcf05887813dee5949
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Dec 4 15:48:05 2012 -0800

    crossgcc: Add support for building armv7a toolchain
    
    !#%$@ autotools don't support all the platforms gcc and binutils
    support. If you try to update to the latest autoconf, it will complain
    that you have to use the older one. If I had a penny for every time
    autotools broke portability...
    
    Change-Id: I479b6c5f64f1def8dca889884e6a2b0e2ffc1fb8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1966
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 9b926651413f051e63fcd473a534d205b31589a6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Dec 1 18:45:00 2012 +0200

    Drop TINY_BOOTBLOCK
    
    Change-Id: I38ea2ed2be4d9240ec8cb6d5dc5b3cc578cdaefb
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1963
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit efb7940867453c489df89ecadd173f0c41dea42e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Nov 27 13:20:43 2012 -0800

    Add include files for samsung s5p-common
    
    These are from u-boot but have been cleaned up somewhat to remove
    references to linux include files.
    
    Change-Id: I5fe3954a11d8c4aa792620ef5e1a5ee8932b8578
    Signed-off-by: Hung-Ti Lin <hungte@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/1930
    Tested-by: build bot (Jenkins)

commit 8d7115560d469f901d7d8ccb242d0b437e7394aa
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Nov 30 12:34:04 2012 -0800

    Rename devices -> device
    
    to match src/include/device
    
    Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1960
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 4b6be985aae8bff84ae442e7be7669e93694fa1e
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Nov 30 13:56:31 2012 -0800

    Change TARGET_I386 to ARCH_X86
    
    This renames TARGET_I386 to ARCH_X86 to make it more uniform with
    other parts of the codebase, e.g. cbfs_core.h from cbfstool.
    
    Change-Id: I1babcc941245ed1dde0478a21828766759373a42
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/1961
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit 0a92f89f5dfa559eb012015235209e53e87e128d
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Nov 30 12:20:45 2012 -0800

    fix #if for target architecture in libpayload
    
    This bug was introduced when we copied cbfs_core.h from cbfsutil
    to libpayload.
    
    Change-Id: I9b5d00d0dbdb969644ce46ad6ac2a84b366b5cd7
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/1958
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Tested-by: build bot (Jenkins)

commit 1e753294c4c7bbc825a413ab62c47878104f984f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Nov 30 12:23:45 2012 -0800

    Drop boot directory
    
    It only has two files, move them to src/lib
    
    Change-Id: I17943db4c455aa3a934db1cf56e56e89c009679f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1959
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 179206a1acb1659ffe018378494abc269771e9dd
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Nov 30 12:19:59 2012 -0800

    src/lib/Makefile.inc: Add license header
    
    Change-Id: If8bce4ebde9101ac9087fcbd43adc0e08c26352d
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-on: http://review.coreboot.org/1957
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 859e808709c352210eb1ad92bf805e3c36c06ec5
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Nov 30 12:03:46 2012 -0800

    Make set_boot_successful depend on PC80_SYSTEM
    
    Set_boot_successful depends on CMOS parts that non-PC80
    platforms do not have. For now, make the current path
    depend on CONFIG_PC80_SYSTEM, and make the alternative
    empty.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Change-Id: I68cf63367c8054d09a7a22303e7c04fb35ad0153
    Reviewed-on: http://review.coreboot.org/1954
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 3d6eb29099162b0b632032c6a42b97cf263ce00e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Nov 30 12:02:32 2012 -0800

    Only compile PC80 drivers when CONFIG_PC80_SYSTEM is set
    
    Change-Id: Iac2f3ebf68c9c1df296fc81d10ee97053a9d5469
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1956
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0a9775941df33c73a58001484c7455eda830fa02
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Nov 30 11:21:05 2012 -0800

    cbfstool: Clean up messages
    
    The output of cbfstool is a little inconsistent in some places.
    This patch fixes it.
    
    Change-Id: Ieb643cb769ebfa2a307bd286ae2c46f75ac5e1c1
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1955
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7f934f5ee00978634c72740c2d1e997f2ac72e7f
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 15 14:53:02 2012 +0100

    build system: Treat cmos.default as text file
    
    It's a more easily maintainable format than a 128 byte binary blob
    
    Change-Id: Ic9b9f53cd025b5f89a21971930fabf6592f95d67
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1867
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8ff97b2973329ee7e3b50471a10f63bbbe13b0ee
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Sun Oct 28 18:19:38 2012 +0800

    Supermicro h8scm: add agesa version of supermicro
    
    Supermicro h8scm has a C32 CPU socket, the details of this board is:
    http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm
    We are planning to replace legacy C32 code with agesa and the h8scm_fam10 do not support
    family 15 CPU, so we update this mainboard with this patch.
    
    This code supports memory at 800M Hz of f10 CPU, bu f15 CPU does not has this limitation.
    If you want to change the frequency of memory, please edit the macros
    "BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT" and "BLDCFG_MEMORY_CLOCK_SELECT"
    in src/mainboard/supermicro/h8scm/buildOpts.c
    
    Change-Id: I9ca9e70d7f3e82c07e7d36695bf31008db152afb
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1510
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit e7d6f02ca4934319b11ad99fdd92c3e4cf2234be
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Wed Oct 24 11:22:38 2012 +0800

    AMD SB800: Interrupt routine for PCI slots on Persimmon
    
    Set the correct device number in the pcie interrupt routine in ACPI asl.
    The device number is decided by which address pin is connected to IDSEL.
    Table 3-1: IDSEL Generation
    Primary Address AD[15::11] Secondary Address AD[31::16]
    0 0000 0000 0000 0000 0001
    0 0001 0000 0000 0000 0010
    0 0010 0000 0000 0000 0100
    0 0011 0000 0000 0000 1000
    0 0100 0000 0000 0001 0000
    0 0101 0000 0000 0010 0000
    0 0110 0000 0000 0100 0000
    0 0111 0000 0000 1000 0000
    0 1000 0000 0001 0000 0000
    0 1001 0000 0010 0000 0000
    0 1010 0000 0100 0000 0000
    0 1011 0000 1000 0000 0000
    0 1100 0001 0000 0000 0000
    0 1101 0010 0000 0000 0000
    0 1110 0100 0000 0000 0000
    0 1111 1000 0000 0000 0000
    1 xxxx 0000 0000 0000 0000
    On persimmon, PCI slot 0's IDSEL is connected to AD19, so the device number is 3.
    Slot 1's IDSEL is connected to AD20, so the device number is 4.
    
    Change-Id: Ic0fb7ac1c87ec306bf314e4d2b8c2bdc9031081b
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1610
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit fbb5b4035f541968e158c54347071d3a2c33eb67
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Fri Nov 16 14:16:02 2012 -0700

    Persimmon: Disable the unused PCI clocks
    
    Change-Id: I4b735fe4e6441f99236e43b34695fdac95b8888a
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1875
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 7bcffa511dee2782702cc2920580d15b34073e1c
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Wed Nov 28 11:36:52 2012 +0800

    AMD S3: Leverage the public SPI routine
    
    Remove the old, unflexible code for storing S3 data in SPI flash.
    Refer to flashrom. Tested on Parmer.
    
    Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1920
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 78a1667cbc0a26c09079c81aa7b8f4387c5f3774
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Nov 29 16:28:21 2012 -0800

    Create a a new configuration variable for PCI
    
    Not all architectures have PCI. This new config variable allows control
    of whether PCI support is configued in. It is selected for ARCH_X86.
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/1947
    Tested-by: build bot (Jenkins)

commit 3665ace13de68e798de31499197cc600d2426967
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Oct 8 15:03:35 2012 +0200

    libpayload: Remove unused FLAG_USED from memory allocator
    
    The FLAG_USED bit in the memory allocator's header type was never
    read. This removes it to save one bit for the region size so we can
    have heaps of up to 32MiB.
    
    Change-Id: Ibd78e67d79e872d6df426516667c795fd52326d5
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1942
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0227dec291ac825aae514b7841bb39a936bcec77
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Nov 9 18:12:21 2012 +0100

    libpayload: Fix lookup by label in CMOS layouts
    
    The condition to compare the labels was twisted.
    
    Change-Id: I34a665aa87e2ff0480eda0f249bbbea8a8fe68d8
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1941
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 48e21ec430cf83f540bf189b1dfa372938cc9b36
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Nov 14 08:08:50 2012 +0200

    Add mainboard hook to bootblock
    
    Change allows to override default bootblock_mainboard_init() with
    mainboard-specific code.
    
    If the default bootblock_mainboard_init() handler is replaced, with
    one from file BOOTBLOCK_MAINBOARD_INIT, one needs to take care the
    replacement calls all the necessary bootblock_x_init() functions.
    
    Change-Id: Ie8c667cdba7cafe9ed2d4b19ab2bd21d941ad4ca
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1845
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f90224845d5a916863c3b060a58fd82ff8d6bec0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Nov 14 08:01:44 2012 +0200

    Refactor bootblock initialisation
    
    Makes it a bit easier to implement mainboard-specific behaviour
    while executing the bootblock.
    
    Change-Id: I04e87f89efb4fad1c0e20b62ea6a50329a286205
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1844
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 90ca3b6bd7d7849898fe2363a9e6d0e002c95943
Author: David Hendricks <dhendrix@chromium.org>
Date:   Fri Nov 16 14:48:22 2012 -0800

    Add multi-architecture support to cbfstool
    
    This is an initial re-factoring of CBFS code to enable multiple
    architectures. To achieve a clean solution, an additional field
    describing the architecture has to be added to the master header.
    Hence we also increase the version number in the master header.
    
    Change-Id: Icda681673221f8c27efbc46f16c2c5682b16a265
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/1944
    Tested-by: build bot (Jenkins)

commit 11a20b614e708582ebd7607d39487938f35f2550
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Nov 29 15:19:43 2012 -0800

    Lumpy: Need byteorder.h in romstage
    
    Not sure why this never triggered an error before.
    
    Change-Id: I85d8b3b862492df04163a5f751c7ea4288406860
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1946
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 421288d6e6924bfb814ba06050be048b891719a9
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Nov 28 20:19:23 2012 -0800

    Make libgcc wrappers arch-specific, add ARMv7
    
    Change-Id: Ia0bbd3bec6588219ce24951c0bcebefc6b6ec80e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/1940
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 5367e47ef1d53cd2effafc0b4832af15bdc8fd21
Author: David Hendricks <dhendrix@chromium.org>
Date:   Wed Nov 28 20:16:28 2012 -0800

    Add dummy Kconfig options for armv7
    
    This adds a dummy config for ARMV7 for developing various
    follow-up patches which rely on ARCH_ARMV7.
    
    Change-Id: Id913054d916f41607d10ebc02aaf74082e14b554
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/1939
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit f2e13b0b198455b83d2162a27704ad7a61eca286
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Nov 28 10:44:12 2012 -0800

    Add the maxim MAX77686 power controller.
    
    Create a new directory in drivers for power controllers.
    Add the MAXIM MAX77686 power control support.
    
    Accessing this controller requires I2C support.
    Note that this will not build until the I2C usage is changed for
    coreboot. I'm putting it in mainly because we need it soon
    and I want to see if the new directory is acceptable.
    
    Change-Id: I6c2a6d2165f33b41d2c8e4813222b21d2385e879
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    SIgned-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/1938
    Tested-by: build bot (Jenkins)

commit 6d1fcd5e0bccea7f813706fce84c815c2782a356
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Wed Nov 28 16:13:40 2012 +0800

    crossgcc: Only build iasl in acpica.
    
    Other acpica's modules are not needed.
    
    Change-Id: I16846caa922aded8db7c1d9e64c007fb2772ff98
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1935
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

commit 98243281e70192612e275133644f8df173badef5
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Aug 23 19:16:01 2012 +0300

    Drop empty mainboard.c
    
    Change-Id: Idcf9349d96297b8cb0ea1e68769e02659ac16ab8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1933
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 897aeeba4bd7ddb483e550d1d6e820186dfa4bcf
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Aug 23 12:20:35 2012 +0300

    Drop empty mainboard_ops
    
    Change-Id: I24866142eebcb8fdbc7e21f5b2f364a8d1b264b3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1932
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e773c92ef44be12108c61ce342b0d48ad6c6ddd6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Nov 15 07:05:43 2012 +0200

    Make mainboard_ops and mainboard.c file optional
    
    This provides weak empty declaration for mainboard_ops.
    The struct chip_operations is not defined for __PRE_RAM__ so
    the declaration is also moved upwards in the output.
    
    Change-Id: I101f0b8b9f0a55fb51a7c6475d53cc588c84026d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1931
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 95efb565b6581c98df9064aeaa6b63dc3dfad2f6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Oct 8 09:33:38 2012 +0200

    pirq_route_irqs is private
    
    Change-Id: I120913dac3150a72c2e66c74872ee00074ee0267
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1936
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 23547ddb94476a2f65cf76c11b019ca86419cc35
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Nov 28 10:03:59 2012 -0800

    Minor changes to .h files for samsung ARM part
    
    With these changes we have a mostly compiling target.
    
    I'm still removing and pruning .h files, but hopefully later today I'll do
    the last few .h commits and move on to .c
    
    Change-Id: Ia82d787496184e028f37d7b67336d61fda75aa94
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/1937
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5079a0d32f2824445cf593dfbcb65598eaa97dee
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Nov 27 11:32:38 2012 -0800

    Remove assembly coded log2 function
    
    As we move to supporting other systems we need to get rid of assembly
    where we can. The log2 function in src/lib is identical to the assembly
    one (tested for all 32-bit signed integers :-) and takes about 10 ns
    to run as opposed to 5ns for the non-portable assembly version. While speed
    is good, I think we can spare the 15 ns or so we add to boot time
    by using the C version only.
    
    Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/1928
    Tested-by: build bot (Jenkins)

commit acf443191bd035c26ee89c3ca56f065a5111901b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Nov 27 10:48:56 2012 -0800

    add .h files for common exynos 5
    
    Change-Id: I48497adc29a1b8ca11d1e0a5d879cab5b6b55dcd
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/1926
    Tested-by: build bot (Jenkins)

commit 6e3728bb12688e8de300c04d5e7a688bc99a2d15
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Nov 27 10:36:06 2012 -0800

    Add .h files for samsung exynos 5250
    
    Per a conversation with Stefan, these chip-dependent files are moved
    to the src tree, in the manner of other chips (north and southbridge).
    
    Change-Id: I12645ba05eb241eda200ed06cb633541a6a98119
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Reviewed-on: http://review.coreboot.org/1925
    Tested-by: build bot (Jenkins)

commit bbc880eee702fc175d4a3c3e87b682c26c38f940
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Nov 20 18:20:56 2012 +0100

    amdk8/amdfam10: Use CAR_GLOBAL for sysinfo
    
    This gets rid of the somewhat unstructured placement of AMD's
    sysinfo structure in CAR.
    We used to carve out some CAR space using a Kconfig variable,
    and then put sysinfo there manually (by "virtue" of pointer magic).
    
    Now it's a variable with the CAR_GLOBAL qualifier, and build
    system magic.
    
    For this, the following steps were done (but must happen together
    since the intermediates won't build):
    - Add new CAR_GLOBAL sysinfo_car
    - point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR
    - remove DCACHE_RAM_GLOBAL_VAR_SIZE
      - from CAR setup (no need to reserve the space)
      - commented out code (that was commented out for years)
      - only copy sizeof(sysinfo) into RAM after ram init, where
        before it copied the whole GLOBAL_VAR area.
      - from Kconfig
    
    Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1887
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 721265b87ac1e70dea72c5b1ae7f5878214557cf
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 27 14:47:49 2012 -0800

    Drop driver-y from GM45/ICH9/RK9
    
    This broke because those components were not yet
    committed when the patch to drop the driver class
    was made.
    
    Change-Id: I29948223503a6c4b196eafa169c064cd26da1be1
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1934
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e135ac5a7ea69b6edcb89345019212f5de412b1e
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Nov 20 11:53:47 2012 +0100

    Remove AMD special case for LAPIC based udelay()
    
    - Optionally override FSB clock detection in generic
      LAPIC code with constant value.
    - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz
    - compile LAPIC code for romstage, too
    - Remove #include ".../apic_timer.c" in AMD based mainboards
    - Remove custom udelay implementation from intel northbridges' romstages
    
    Future work:
    - remove the compile time special case
      (requires some cpuid based switching)
    - drop northbridge udelay implementations (i945, i5000) if
      not required anymore (eg. can SMM use the LAPIC timer?)
    
    Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1618
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bdc1816b2379bdf569ac6746172bba41e1307917
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 27 12:44:18 2012 -0800

    Fix technexion tim5690 board VGA handler
    
    When dropping ramstage.a, unused functions with unresolved
    symbols are not silently dropped anymore. This makes the
    tim5690 compilation fail.
    This fix makes sure we don't compile in the int15 handler code
    when we don't set CONFIG_VGA_ROM_RUN
    
    Change-Id: If6872c983d9fd811eb33259421f94b551f3b9b34
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1929
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 23023a5691c0e3086933706c1cb2a79602ecffa0
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Tue Nov 13 07:09:12 2012 -0700

    Enable the FCH GPP port prior to device enumeration
    
    Change-Id: Ib4401897570f9e4d31c18d05144b5deb6f4523bc
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1873
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 8247583058fc1607ccde26be7cdb1a1be4691122
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Nov 15 16:24:30 2012 -0800

    Drop duplicate files that prevent building without ramstage.a
    
    When dropping ramstage.a duplicate symbols in ramstage
    will start breaking the build. Hence drop all the duplicate
    functions implemented by mainboards that have those functions
    in generic or component code already.
    
    Change-Id: I5cf8245c67b6f0f348388db54256d28f47017a61
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1865
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit f33e395213f0516a9256f33ede4c6bba3babb0e9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Nov 25 17:10:47 2012 +0100

    build system: Split linking into multiple steps
    
    After collecting dependencies for ramstage, add an intermediate step
    in which object files are linked per directory. The results are then
    linked into the final binary.
    
    This reduces the maximum command line length and might also help with
    future use of LTO linking.
    
    Also adapt the lint test for build dir handling, since printall
    doesn't provide individual object files for ramstage anymore.
    
    Change-Id: Ie40febd8c1eaf4609944eedeab46d870639e53df
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1911
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 79f9010e80a04f2e0fb0cca5759e3215dff79aff
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Nov 25 14:31:08 2012 +0100

    build system: Add hook to postprocess classes (object lists)
    
    This will be used to minimize the ramstage class, to avoid command
    line lengths to exceed the limit on mingw, esp. after we got rid
    of ramstage.a
    
    Change-Id: I80582d04476545c275e8d1d08fb52a99f58cebcc
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1910
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6999217ab6e4c8ed4c7f19a5578c36b01ad883ed
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Nov 25 17:31:25 2012 +0100

    build system: Eliminate special case for c_start
    
    c_start.o has a special case in the build system, which we can
    eliminate, somewhat simplifying the build.
    
    To ensure that the entry point is at the beginning, introduce a
    new section .textfirst that is placed appropriately. In principle
    the ENTRY() definition in the linker script should be enough, but
    better be safe.
    
    Change-Id: I9737f7f5731e12ceb2119eb432b0e09832bc53fa
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1909
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 23f38cd05c05ed1876febfa59b652cd7171027ca
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Nov 16 14:50:32 2012 +0100

    Get rid of drivers class
    
    The use of ramstage.a required the build system to handle some
    object files in a special way, which were put in the drivers
    class.
    
    These object files didn't provide any symbols that were used
    directly (but only via linker magic), and so the linker never
    considered them for inclusion.
    
    With ramstage.a gone, we can drop this special class, too.
    
    Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1872
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 18607f717eb125f49431da3843c19fcb25f1ee81
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Oct 7 22:11:07 2012 +0200

    Drop ramstage.a
    
    ramstage.a has two issues:
    1. duplicate source filenames don't survive the ar(1)
       treatment properly (so files aren't considered)
    2. ld doesn't resolve symbols if it isn't forced to, in
       particular no overrides of weak symbols
    
    Downside: The resulting binaries get slightly larger.
    Link time optimizations should fix that, as would tighter
    rules in the build system (to not compile unused code in
    the first place).
    
    Change-Id: Iaae771ec8f92b42069237acd3b79c14e5bf9c03d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1566
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b6f765e7c85539b270dba407ff40846c3688ed60
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Oct 7 22:04:52 2012 +0200

    Provide weak empty declarations of all chip_ops used on a board
    
    sconfig creates empty defaults for all chip_ops, which can be overridden
    by drivers simply by providing a concrete implementation.
    
    Change-Id: Ib37515f0b0747bdbf4da780d28690a1e719944b2
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1567
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 28b900afbd6bcf817654f6cfab90bea8af43f5bd
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Nov 27 10:19:59 2012 +0100

    libpayload: Add _ and + to USB HID keymap
    
    Slightly more complete keymap
    
    Change-Id: I4fef6b8f75ab07cb20a3a8ccd7eaad81c9fe719f
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1922
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e3abd3bfbb2459d0bea16df984f54a279ad5b7c0
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Sep 7 10:40:36 2012 +0200

    roda/rk886ex: Correct COMB irq reading / reduce warnings
    
    The calculation of COMB's irq reading was wrong by the 4-bit shift.
    Also, the asl compiler warned about the splitting in lo/hi bytes which
    seems unnecessary.
    
    Change-Id: Ia5101d5a19f68c2da827d7e37a18922f959604c7
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1923
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f5e0fd888d4c33b5d5cd55f9ffa43407a416ade1
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Nov 27 12:26:52 2012 +0100

    roda/rk9: Fix for VGABIOS changes
    
    Forgot to update the rk9 for the unified VGABIOS handling.
    
    This applies to rk9 what is done for other boards in commits
    	3c84261e84318708c9c16ee5df5c2549c609dd0a
    	d5d340695b84ef6351818236dc514cd9734e87b1
    
    Change-Id: I892b7d81927e277778c1c5251d27416fa79c9868
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1924
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b8117b062266eda6b8ac9a8b60881a99f0323a48
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Tue Nov 27 18:08:53 2012 +0800

    SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)
    
    For SST chips, the Write-Status-Register instruction must be
    executed immediately after the execution of the
    Enable-Write-Status-Register instruction, instead of Write-Enable.
    
    Change-Id: I4b3473cd671829def3bd1641ececcf8d9dad4a56
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1919
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1a5301dd3373e7def334fc34787f79073f49029a
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 22 14:19:43 2012 +0100

    abuild: only rebuild boards if requested or after a broken build
    
    That used to be the behaviour, and it's quite useful to incrementally
    fix bugs across the tree.
    
    Change-Id: I3e30cbdcf01631bc29f892054caa3babb0969beb
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1888
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 536b53ea6daf23d7c09a35f5633f06e604a64e20
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Tue Nov 27 17:07:22 2012 +0800

    xcompile: Add missing XGCCPATH
    
    XGCCPATH is missing in new xcompile.
    
    Change-Id: I177f54189be445404a4a61419064d3c414b8a30c
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1921
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 021b7033fb578258844bf8ecad9f2d34b16b674b
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Nov 6 11:05:38 2012 +0100

    roda/rk9: New mainboard
    
    Roda RK9 is a notebook based on the GM45/ICH9 platform using DDR3 memory.
    http://roda-computer.com/products/notebooks/rk9/
    
    Tested with various Linux versions, known to work:
    - 2x4GB RAM
    - IGD
    - HD Audio
    - UHCI, EHCI
    - AHCI
    - NIC
    - PCI
    - PS/2 keyboard
    - serial console
    - ACPI lid switch
    - ACPI battery/AC events
    - power off, reboot
    
    Change-Id: I7299dccbff2eea3544363fdd4f49f05aa3dae7bc
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1691
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e72a8a3047c535bda03aecce2eca134608d1a93c
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Nov 6 11:05:09 2012 +0100

    intel/i82801ix: new southbridge, ICH9
    
    Add support for ICH9 southbridge
    
    Change-Id: I70612431101bf48d9dcc96ee1b37d257c9ad2ee2
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1690
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2efc8808b8bfaee0a0e8f3ee387ecd9a3f049705
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Nov 6 11:03:53 2012 +0100

    intel/gm45: new northbridge
    
    The code supports DDR3 boards only. RAM init for DDR2 is sufficiently
    different that it requires separate code, and we have no boards to
    test that.
    
    Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1689
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit acd7d952514485dbc41fa04b0d16be4002e31019
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Jul 25 10:33:05 2012 +0200

    Add initialization hook for chips
    
    Add an init() function to the chip_operations which will be called
    before bus enumeration. This allows to disable unused devices before
    they get enumerated.
    
    Change-Id: I63dd9cbfc7b5995ccafb7bf7a81dc71fc67906a0
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1623
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e820e5cb3aed810fa9ba6047ce9b8bf352335e32
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Nov 26 14:33:09 2012 -0800

     Make xcompile support multiple architectures
    
    With this change the the xcompile script now creates environment variables
    for more than one architecture.
    
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Signed-off-by: Hung-Te Lin <hungte@chromium.org>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    
    Change-Id: I349a1fd1d865ef16979f1dfd6aeca12b1ee2eed6
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/1915
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 534c8a013ff57c2b7dc15f55dea0cf4dbf3ce7bd
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Nov 26 15:07:39 2012 -0800

    Conditionally #include mc1468181rtc if CMOS_POST is enabled
    
    This will omit the mc1468181rtc header if it is not needed. Currently
    it contains a lot of inlined functions which depend on architecture-
    specific IO.
    
    Change-Id: I4ef1bc1362c159e0c780c3eade01af04f029f949
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/1916
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 6b908d08ab4c256b6a8d4f7d863fe9eb65ea6fe3
Author: David Hendricks <dhendrix@chromium.org>
Date:   Mon Nov 5 12:34:09 2012 -0800

    Make POST codes written to IO port optional
    
    This adds more configurability to POST codes. The current assumption
    is that POST codes should be written to an IO port (e.g. LPC) if POST
    codes are enabled. This changes the assumption so that POST codes can
    be written to the serial console without being written to an IO port.
    
    This enables POST codes by default using "default y" to avoid
    changing current behavior.
    
    Change-Id: I3db91c358ccb1557096983c4d07f70b2e872c4b3
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/1685
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d5d340695b84ef6351818236dc514cd9734e87b1
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 22 15:37:47 2012 +0100

    Remove duplicate VGA BIOS interrupt handlers
    
    Some boards have two instances of the int15 handler that supports
    the onboard VGA BIOS, for YABEL and realmode.
    These are now similar enough that they can be deduplicated.
    
    Due to minor differences this requires manual effort.
    
    Change-Id: I03ae314cb90dd65d96591ce448504aa961cbeb88
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1893
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3c84261e84318708c9c16ee5df5c2549c609dd0a
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 22 15:30:05 2012 +0100

    yabel: Use X86_* instead of the more verbose M.x86.REG_*
    
    Makes it more similar to what realmode looks like.
    
    Change-Id: I4407431f2d979c43dd186114d67ed11845907afe
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1892
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 199b09cb7a3c590ccbf8d705c98cfde101378f20
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 22 12:46:12 2012 +0100

    x86 realmode: Use x86emu register file + defines
    
    By using the (global) register file as defined by x86emu,
    we can use the same register access for YABEL and realmode
    interrupt handlers.
    
    - the x86 realmode interrupt handlers changed in signature
    - to access registers, use X86_$REGNAME now (eg. X86_EAX)
    - x86_exception_handler still uses struct eregs *regs to
      avoid spilling the x86emu register file stuff everywhere
    
    Coccinelle script that handled most of this commit:
      @ inthandler @
      identifier FUNC, regs;
      @@
      int FUNC(
      -struct eregs *regs
      +void
       )
      { ... }
    
      @ depends on inthandler @
      identifier regs;
      @@
      -regs->eax
      +X86_EAX
    
      @ depends on inthandler @
      identifier regs;
      @@
      -regs->ebx
      +X86_EBX
    
      @ depends on inthandler @
      identifier regs;
      @@
      -regs->ecx
      +X86_ECX
    
      @ depends on inthandler @
      identifier regs;
      @@
      -regs->edx
      +X86_EDX
    
      @ depends on inthandler @
      identifier regs;
      @@
      -regs->esi
      +X86_ESI
    
      @ depends on inthandler @
      identifier regs;
      @@
      -regs->edi
      +X86_EDI
    
      @ depends on inthandler @
      identifier regs;
      @@
      -regs->eflags
      +X86_EFLAGS
    
      @ depends on inthandler @
      identifier regs;
      @@
      -regs->vector
      +M.x86.intno
    
    Change-Id: I60cc2c36646fe4b7f97457b1e297e3df086daa36
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1891
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 503af721a1f2c831fb360d1c1b2af38e0866fc35
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 22 10:48:18 2012 +0100

    x86 realmode: Adapt to x86emu/YABEL style return codes
    
    realmode int handlers must return the same codes as the YABEL
    int handlers now: 1 for "interrupt handled", 0 for "not handled"
    (ie. error).
    
    Change-Id: Idc01cf64e2c97150fc4643671a0bc4cca2ae6668
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1890
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3e77eb6d1e0a3ff9c0a32504a5221dc57b10506c
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 22 10:39:16 2012 +0100

    x86emu: Move realmode handler into own directory
    
    It's really a feature in parallel to YABEL/x86emu. Reflect this in
    the directory structure.
    
    Change-Id: Ie88e4fa6bfef13d23c55b2db3faacbd90f8cc30b
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1889
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6b11c8be4572f9b96804509e5bd9170a8cec162d
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Thu Nov 15 21:14:36 2012 +0100

    crossgcc: update to acpica-20121114
    
    Update acpica to release 20121114 and
    update patches/ to build with this version of acpica.
    Correct the creation of crossgcc-build.log
    Bump CROSSGCC_VERSION.
    
    Change-Id: I269454ebc3c78b5852e4a67e55bb5642edad191d
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/1861
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0c2364c17ca40a4c726d98f3d2861d27ec02fed5
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Nov 22 17:21:57 2012 +0100

    libpayload: Fix interrupt-queue cleanup for OHCI
    
    We have to free TDs more carefully if they have been processed by the
    controller yet. The current code tries to force the controller to post
    them back to the done queue, but that seems wrong. We can't be sure,
    when they get written back. This resulted in leaking TDs with an invalid
    reference to a freed interrupt queue.
    
    The new approach: Mark the interrupt queue to be destroyed and handle
    the freeing later, when the controller posted the last TD to the done
    queue.
    
    Change-Id: I79d80a9dc89e1ca79dc125c4bbccbf23664227b3
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1905
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b9917c20683258b5736a05fd384f7b52e53e02f9
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Nov 22 15:45:48 2012 +0100

    libpayload: Rework connection state detection for OHCI
    
    The connection state detection in the OHCI root hub driver was broken if
    you used more than one device per root hub.
    
    Change-Id: Ica5c735426beac45ef6f591ce68a72d8283a00f5
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1904
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit be58fee28e9f0c4d8f196added0105a101512acc
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Nov 22 11:12:13 2012 +0100

    libpayload: Handle errors in UHCI interrupt queues
    
    If somethings goes wrong during an interrupt transfer, drop the
    transfer.
    
    Change-Id: I450c08a7a0bf23fbee74237e0355d4a726ace114
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1901
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 8c4d2f36a339ba34c532e29696f2c5b70fb04957
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Nov 20 17:49:00 2012 +0100

    libpayload: Handle underruns in UHCI interrupt queues
    
    If usb_poll() isn't called fast enough, the UHCI controller marks an
    underrun interrupt queue as done (terminating the queue at the head).
    We can recover from this situation, when usb_poll() gets called again,
    and the queue is processed.
    
    Change-Id: Id56c9df44d6dbd53cd30ad89dfb5bf5977799829
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1898
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ce407e470d36bd446e7e1f02884c97a98423d5c4
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Nov 20 17:27:46 2012 +0100

    libpayload: Implement correct interrupt-queue linking for UHCI
    
    The linking of interrupt queues into UHCI controller's framelist (in
    uhci_create_intr_queue()) was incomplete. The implementation of
    uhci_destroy_intr_queue() was even worse, looking like it wanted to
    clean up more than uhci_create_intr_queue() did.
    
    This patch follows the simple approach that we used for OHCI and EHCI:
    Each slot in the framelist holds only one interrupt queue. Therefore, we
    have to look for free slots each time we want to link an interrupt queue
    into the framelist. In return, we have a much simpler structured
    framelist.
    
    With this, USB devices using interrupt transfers (e.g. keyboards) can be
    detached cleanly from UHCI controllers. Also, more than one of such
    devices can be attached without further risk.
    
    Change-Id: I07b81a3b6f2cb3ff69515c973b3ae6321ad969aa
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1897
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cd587f110bec55ff24a73a775a8c757332715f3f
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Nov 23 13:18:13 2012 +0100

    libpayload: Make USB HID support multiple keyboards
    
    The USB HID driver had some static variables with keyboard state. This
    moves them to the driver's instance, so multiple attached keyboards
    don't effect each other.
    
    Change-Id: I3f1ccfdea95062b443cebe510abf2f72fdeb1916
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1907
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit af169f4dd515f52e26c4c476c3340a710db69887
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Nov 22 11:14:03 2012 +0100

    libpayload: ehci: Prevent some race conditions
    
    Prevent race conditions, when an interrupt-queue underrun occurred and
    the controller is currently working on our queue head or a transfer is
    still in progress.
    
    Change-Id: Ia14f80a08071306ee5d1349780be081bfacb206a
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1902
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit b2db28babe0e64e08b1a754b65dd7e437f8d82a9
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Nov 22 11:18:19 2012 +0100

    libpayload: Detach devices behind removed USB hubs
    
    When a USB hub got removed, we should also remove all devices that
    were attached to it.
    
    Change-Id: I73c0da1b7570f1af9726925ca222781b3d752557
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1903
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit ef88e102bb4895753c8ba67e01ee26fdfe3fa712
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Nov 21 16:25:55 2012 +0100

    libpayload: More compliant error recovery in USB MSC
    
    If an endpoint gets stalled by an MSC device, after successful
    transmission of a command (CBW), we should still ask for the status
    (CSW). Otherwise, the driver and the device get desynchronized on the
    command tags.
    
    Change-Id: I53167f22c43b3a237cb4539b3affe37799378b93
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1900
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 86c686a76e7565b26355a9937fe397e23536512c
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Nov 21 16:22:26 2012 +0100

    libpayload: Reduce error output from EHCI
    
    Stalled transfers are not fatal, so don't spew on the console on every
    tiny failure.
    
    Change-Id: I175c1e83a6af09c1abbd43d045ed6dbf0c79f871
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1899
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit e8a71d34cd78207814623c0690f1941e3b296818
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Nov 23 11:52:18 2012 +0100

    libpayload: Fix random warnings
    
    dump_td() is orphaned but looks useful => commented out.
    
    The delay identifier shadowed the global one => renamed to total_delay.
    
    Change-Id: I4f3766a07db9194b2552ebf9302bd7ef8a66371f
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1895
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 4f83d1b0c6a2e1632d6ff60b1d8bce7fa16b7f24
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Nov 23 11:58:57 2012 +0100

    libpayload: ehci: Fix warnings about discarded volatile
    
    We can trust free() and memset() to work correctly on volatile
    references, so cast volatile pointers to (void *) when calling them.
    
    Change-Id: Ieff7f78133b72f303349cca0a0ca3bbf37ec52bb
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1896
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit ba22e4c3fde49b48bd711da6ad972738468ed181
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Nov 23 11:34:20 2012 +0100

    libpayload: Fix some missing-prototype warnings
    
    usb_controller_initialize() is not declared in any header file nor
    called from outside of usbinit.c, so make it static.
    
    set_configuration() looks like beeing non-static on purpose (like the
    other helpers around it in usb.c), so put a prototype into usb.h.
    
    Change-Id: I08d93b3769d8398bb43462d9afdfeec81fef93ec
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1894
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7a32e88f12efcc424a8e33de0f33f82356d73531
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Nov 22 17:37:32 2012 +0100

    libpayload: Fix memalign() for fragmented alignment regions
    
    Found a bug in the memory allocator ;-)
    
    If the total free space in an alignment region is large enough for an
    allocation but fragmented, such that there is no contiguous, sufficient
    large, free space in the region, memalign() was looking at the same
    region again and again in an endless loop. The advancing to the next
    region was just missing.
    
    Change-Id: I3fad833804675ee495577ca2749b007f46b5ff69
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1906
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 0a3f2393aefd8fceea075e3108d581aadec292ab
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Nov 20 12:04:32 2012 +0100

    crossgcc: properly test for flex
    
    This is no GNU tool, so testing for "GNU" in the version string
    is bound to fail.
    We now accept everything that returns success on "flex --version"
    and then hope for the best.
    
    I tested both cases
    
    Change-Id: If325f613fde1648847b998b7e8e5782d0f22b484
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1884
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 73be43a139f15dfa526b0eeefb5539b35cc0902f
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Fri Nov 16 14:16:33 2012 -0700

    Persimmon: Disable the unused GPP PCIe clocks
    
    Change-Id: I4128af7912bec090bbd48acc1b20d0452e7a4a28
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1876
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 8ada1526df06cb50a82305e840a5181a3c65575f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Nov 16 13:34:48 2012 -0800

    Unify use of bool config variables
    
    e.g.
    -#if CONFIG_LOGICAL_CPUS == 1
    +#if CONFIG_LOGICAL_CPUS
    
    This will make it easier to switch over to use the config_enabled()
    macro later on.
    
    Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1874
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 82ecf4c582fdab341d88bd80ae3e9a629619c263
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Nov 15 15:53:30 2012 -0800

    secondary.S: Fix dropping ramstage.a
    
    This unused code was not silently dropped as before.
    
    Change-Id: Ic76c58e233869a60c3a8a27c2efc2182b3a4442d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1863
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 40f36e0d8d15a275d0109eac778e3b99bf4e0173
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Nov 15 16:03:27 2012 -0800

    Make sure only one udelay function is available
    
    The Agesa wrapper and UDELAY_TIMER2 define their own timer functions,
    so don't shove in UDELAY_IO
    
    Change-Id: Ibe3345e825e0c074d5f531dba1198cd6e7b0a42d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1864
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0d8267464d093dfddda56e8095c455a8ee96d3e5
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 15 14:55:52 2012 +0100

    siemens/sitemp_g1p1: Drop copy of cmos checksum calculation
    
    This code used a special case for checksum calculation to
    prevent the century byte from messing things up, since
    writes "sometimes" didn't happen.
    
    That should be stable now, so the special case isn't necessary.
    Downside: On century rollovers (ie. 1999-12-31, 2099-12-31)
    CMOS will be reset to the defaults.
    
    Change-Id: Ibe589a1ec953b7b3ba39be30cebd9fc2b27326ae
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1870
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d8e6d4085ffd10d399551a2ec75a57fd1f594fec
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 15 14:57:27 2012 +0100

    bootblock: Guard CMOS rewrite in disable/enable RTC
    
    This ensures that there's only one disable/enable cycle for
    the entire rewrite instead for every single byte.
    
    Change-Id: Ic06e6dcb08976d158ff784660838c0fbad875176
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1869
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f943901777990554e3f5fb27b63613f6cd95c958
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 15 14:54:05 2012 +0100

    mc146818rtc: disable RTC before writing to nvram
    
    In principle this isn't necessary. However there's a byte (or several)
    outside the first 14 bytes that are part of the RTC, and require
    locking (century/altCentury).
    
    Since their location is mostly unknown, guard writes properly.
    
    Change-Id: I847cd4efa92722e8504d29feaf7dbfa5c5244b4e
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1868
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4b62ebe961846b5b07aa57dacc24878a30ea9cc9
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Nov 16 15:05:11 2012 +0100

    Add nvramcui
    
    nvramcui is a small libpayload based utility that provides
    an interactive CMOS editor for pre-boot environments.
    
    Change-Id: I514b8a7682f89d242d1b31b6907cc6bff34da4bf
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1871
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1fc2bda92b9994e1b39e505c94987109762bd587
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 15 14:51:54 2012 +0100

    build system: use strip_quotes on cbfs-files
    
    If they come from the build system, file names might be guarded in
    quotes, which confuses make. Drop them here.
    
    Change-Id: Ice0d3c4bc2c45a3f121a85e1b9f5f6420c5761d5
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1866
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1a2a6eebc5668df21f054b2dae14167bda400617
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Mar 18 20:19:28 2012 +0200

    Cleanup sconfig
    
    Fix side-effects of name translation, treat original name as const.
    
    Change-Id: Iae26be8cefe7db11eeb8e62fce6f3b8bc9c1f4ed
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/799
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e4d40b4d6ea52dfb9bb2fc96a91714f4009b8dee
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Nov 14 08:00:20 2012 +0200

    Drop no-op bootblock.c
    
    Deletes unused file:
       src/northbridge/amd/agesa/family15tn/bootblock.c
    
    Change-Id: Ic29553e008839407755d25bf125d599fa1f6131c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1843
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6446626c1e575bf77a795f92ceead167e731990c
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sat Nov 17 00:07:24 2012 +0100

    Use new system agent binaries
    
    Change-Id: I716564c4ea3b8e298cdeb82dc68e68474ed595cc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1879
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 17b77ab6aa4833f6b369a12dd9da87c8104f482c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Nov 15 11:31:38 2012 -0800

    buildgcc: Print error if flex is missing
    
    flex is needed by acpica. This patch makes the build fail early
    instead of after gcc has been compiled, if flex is not there.
    
    Change-Id: Idfd71bdf704ab25de655f1a72c266c5220b15048
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1860
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a47bd91ccaf14626cab51a74b998d93f3d8af18c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Nov 15 15:15:15 2012 -0800

    Fix PIRQ routing abstraction
    
    intel_irq_routing_table is a local structure that should not be used
    globally, because it might not be there on all mainboards.
    
    Instead, the API has to be corrected to allow passing a PIRQ table in
    where needed.
    
    Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1862
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 56cd70bba2906cb99b84d593d90f7653b0ce1e0b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 13 17:33:08 2012 -0800

    Fix Kconfig GENERATE_*_TABLE usage
    
    Some boards selected GENERATE_ instead of HAVE_
    
    Change-Id: I450c22d7b044f0c88c21692246d452d516a68a83
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1841
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 95a6396ae3df6dfa778ac67a73af6fae4501517a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 13 17:00:01 2012 -0800

    Clean up Kconfig
    
    - move VGA handling options into devices/Kconfig
    - make Devices a top level menu
    - move some  options "closer" to the code they control
    
    Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1840
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 84833448026bfd5c5ef634d937d30017138f22b4
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 13 15:04:12 2012 -0800

    Drop Kconfig.deprecated_options
    
    Both remaining options, DRIVERS_PS2_KEYBOARD and ID_SECTION_OFFSET
    are not likely to go away any time soon, so let's not keep them
    in Kconfig.deprecated_options but move them close to the code they
    control.
    
    Change-Id: I310b877c5b3d5a3444056641c4aee07a48c4c4be
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1839
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fccf4166ddbe1a41ee4f6e327c31dc3e21144a5c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 13 14:54:46 2012 -0800

    Drop unused Kconfig variable PCIE_TUNING
    
    It's only mentioned in Kconfig and never set nor used.
    
    Change-Id: Icc0ac56ae7b325a9e93ed5cdce9dc4b7bab43140
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1838
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fa2fc339c51649b106bf78703cbc17694abcee23
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 13 14:52:04 2012 -0800

    Drop Kconfig variable BOARD_HAS_HARD_RESET
    
    hard_reset was indeed consolidated and moved into the southbridge
    code a while ago, but the config variable was still kept alife, with
    some duplicate code.
    
    Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1837
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 55db955bcdad90c9ebd8b755ae417234d46d731a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 13 14:41:52 2012 -0800

    Drop unneeded BOARD_HAS_FADT option
    
    Change-Id: Iaaeee87d70cf052bc7980007cdf1f7dda88b3623
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1836
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4dfdebadb6731bc291e30560cbd2f107a3c94b75
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 13 14:06:38 2012 -0800

    Reduce number of per-mainboard changes
    
    - Add mainboard_smi.c from arch/x86/Makefile if it's there
    - Add mainboard's chromeos.c from the chromeos Makefile
    
    Change-Id: I3f80e2cb368f88d2a38036895a19f3576dd9553b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1835
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bf5a7dc3121fa75d40099662b67c9795a2c61983
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 13 11:32:56 2012 -0800

    Drop CONFIG_HAVE_BUS_CONFIG, clean up Kconfig
    
    This patch is the beginning of a Kconfig cleanup series
    - drop CONFIG_HAVE_BUS_CONFIG and add get_bus_conf.c if it
      exists in the mainboard directory
    - drop duplicate ACPI_SSDTX_NUM from mainboard Kconfig
      if it only defines the defaul value of 0
    - Add mptable.c, fadt.c, reset.c and ssdtX.asl when they
      exist, not based on some Kconfig magic
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: Ia14a7116dad6a724af7e531920fee9a51fd0b200
    Reviewed-on: http://review.coreboot.org/1832
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 425973cf42ad5c298dd2f501d8b9437c60ae9b6f
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Nov 13 17:11:01 2012 +0100

    libpayload: Always use virtual pointers in struct sysinfo_t
    
    We had mixed virtual and physical pointers in struct sysinfo_t. Some
    being virtual by accident which led to problems when we tried to
    reinitialize lib_sysinfo after relocating FILO (to get intentionally
    virtual pointers valid again). I guess this didn't cause much trouble
    before, as lib_get_sysinfo() was always called with physical addresses
    being equal to their virtual counterparts.
    
    For FILO, two possibilities seem practical: Either, have all pointers in
    struct sysinfo_t physical, so relocation doesn't hurt. Or, have all
    pointers virtual and call lib_get_sysinfo() again after relocation.
    
    This patch goes the latter way, changing the following pointers for
    situations where virtual pointers differ from physical:
      .extra_version
      .build
      .compile_time
      .compile_by
      .compile_host
      .compile_domain
      .compiler
      .linker
      .assembler
      .cb_version
      .vdat_addr
      .tstamp_table
      .cbmem_cons
      .mrc_cache
    We could also just correct the accidentally virtual pointers. But, IMO,
    this would lower the risk of future confusion.
    
    Note 1: Looks like .version gets never set.
    
    Note 2: .option_table and .framebuffer were virtual pointers but treated
            like physical ones. Even in FILO, this led to no problems as
            they were set before relocation.
    
    Change-Id: I4c456f56f049d9f8fc40e62520b1d8ec3dad48f8
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1855
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dd5979ab4330d8677ad250ec4afcd7cb10c83cbc
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Nov 12 16:59:24 2012 +0100

    libpayload: Use #ifdef for CONFIG_* checks
    
    Libpayload uses the linux kernel's config style, where CONFIG_* defines
    don't get written for unset tristates.
    
    Change-Id: I3f832cf86bca9a1e153d96af4bf6434a19eba2f6
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1847
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ff73306ec2612f11d408bf9d708153bb45975ad3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Nov 14 08:09:02 2012 +0200

    Use mainboard hook for HP DL165
    
    The board incorrectly overrides the southbridge hook, so use the
    new mainboard hook instead. This change also activates the actual
    southbridge hook to enable decode of complete 4 MB flash memory region.
    
    Change-Id: I02c6fe89ae9ad4a7403f024fac875ebd88a8e142
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1831
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c1928e2872aa0ae84043b33bdc863ff712f79871
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 13 17:36:17 2012 -0800

    ms9652: fix misuse of LIFT_BSP_APIC_ID
    
    It's a bool, not a number
    
    Change-Id: I70d52c6af6703101dbd534970ec65275902a283d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1842
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f173035ddc338fe6e26bf3e6cef0c006eca47f7d
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Nov 13 14:52:56 2012 +0100

    mainboard/siemens/sitemp_g1p1: Fix YABEL usage
    
    The board was broken for use with CONFIG_PCI_OPTION_ROM_RUN_YABEL.
    
    Change-Id: Ia57d630143386fe637af83b9e7345d0d3750b089
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1854
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit db4bb435e8f9947ce005dacd84da7d7c5a5474cd
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Nov 13 14:51:16 2012 +0100

    Make YABEL's version of mainboard_interrupt_handlers() usable
    
    YABEL's version of mainboard_interrupt_handlers() was hidden behind an
    inline stub. This fixes it.
    
    Change-Id: Ie53424a8ce074e93a720c0ef94cb39994cacd023
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1853
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d172497dee39a169d9088a92ec1ff25ecc24a710
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Nov 13 14:45:38 2012 +0100

    mainboard/siemens/sitemp_g1p1: Fix CMOS checksum algorithm here, too
    
    Some time ago our CMOS checksum algorithm was changed under the topic:
        Fix our CMOS checksum algorithm so it matches what /dev/nvram expects
    
    Here is another copy of the algorithm that had to be updated.
    
    Change-Id: I58659c7b8a89c89c76efdff405ee0620e7302277
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1852
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6e711c6a97a9d4122615018121d0d2a37b642ed1
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Nov 12 16:20:32 2012 +0100

    libpayload: Add init() function to hci_t and rework uhci_reset()
    
    uhci_reset() differs in semantics compared to the other HCI's reset()
    implementations. uhci_reset() does some initialization work after a
    controller reset. So move the initialization part to a new function,
    uhci_reinit(), which get's exported through a new entry in hci_t:
    hci_t.init().
    
    Warning: This breaks code that relies on the current, special,
    counterintuitive behaviour of uhci_reset(). If one wants a working host
    controller after calling hci_t.reset(), he should call hci_t.init()
    afterwards.
    
    Change-Id: Ia7ce80865d12d11157645ce251f77f349f8e3c34
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1851
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit aaa212d17d0070850f1dd2195129788acc978a9f
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Nov 12 16:19:21 2012 +0100

    libpayload: Do not call ohci_reset() from ohci_init()
    
    When ohci_reset() was implemented, OHCI controllers stopped working
    since the stub ohci_reset() is called at the end of ohci_init().
    This is fixed by removing the call. To prevent further problems the call
    to the xhci_reset() stub is removed, too.
    
    Change-Id: If89825c8e6caf40f7f4fe078e8b2e90054a54ba2
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1850
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d633dda995c78f4f2d57d369c1e2baa591c0433a
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Nov 12 15:35:44 2012 +0100

    libpayload: Free usb host controller instance after shutdown
    
    All shutdown() implementations but ehci_shutdown() free the hci_t
    structure. This seems correct and the reference to the hci_t shouldn't
    be used after shutdown(), so do it in ehci_shutdown(), too.
    
    Change-Id: Ie3506d769e73007735f3211710734a5f0107e43a
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1849
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a482701451391b86b9d48ef5cf2a41f95f421484
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Nov 12 15:12:35 2012 +0100

    libpayload: Document USB host controller setup functions
    
    The semantics of the controller functions, start(), stop(), reset() and
    shutdown(), are not self-explanatory which let to some confusion. At
    least the reset() functions of the different host controller drivers
    were implemented following different interpretations. Let's make the
    intended behaviour of these functions clear.
    
    The stated inconsistencies will be addressed in following commits.
    
    Change-Id: Id2e300f65c21039218b6ba3f87c0fcd4f0dda0a8
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1848
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 45b94bc15fe14685c42d3175cdf364e49606ce54
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Oct 9 12:52:05 2012 +0200

    libpayload: Export device count in storage interface
    
    FILO can use this as offset to enumerate AHCI and its own IDE
    devices together.
    
    Change-Id: I57380e7bd1df6db5c882427e9a34d068f4348fb2
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1846
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f6659cac3b764e8a2f4ced7b7058240f06734a20
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Thu Nov 8 14:21:46 2012 +0800

    nvramtool: fsync for mingw.
    
    Change-Id: Ifdec69ca46ba8cbd3eb154d8f4af4b3cafa8019d
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1805
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 431a8160194a1c43c340fbf14ad4e94319bd159e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 13 13:01:31 2012 -0800

    Move HAVE_SMI_HANDLER from mainboards to chipsets
    
    Change-Id: Ibb6606fe3996e377181872a4544600f2d58c5439
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1834
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c5334635caca830600525f9c914465c0c17ec4fc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 13 12:49:59 2012 -0800

    VIA chipsets: fix compilation without real mode code
    
    The VIA chipsets CX700, VT8623 and VX800 required to be
    configured with real mode option rom code enabled. This
    patch fixes the issue and drops some unneeded header files.
    
    Change-Id: I0d8a3f8f99c2eacec7666f08f85b99f09c06af84
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1833
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 13c2c025a46291cc6f06cb55dde9a4d54a4b37fe
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 15 15:28:21 2012 -0700

    Tell CBMEM code about ACPI GNVS section
    
    We moved GNVS to it's own section, but forgot to tell the cbmem code
    about it. This is purely cosmetical, but add it anyways.
    
    Change-Id: Icb3788c0325ea79cc1efff4a876412d07da7936e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1782
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4b85d9b434f6150745e469bd8c04671f4307de33
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 10 12:11:55 2012 -0700

    SMM: Fix save state searching for GSMI
    
    The search for save state was comparing the entire RAX
    value when it needs to just operate on the bottom byte
    so it can find the GSMI command in bits 7:0 but not the
    extended command code in bits 15:8.
    
    Change-Id: I526c60e6b3732fa3680a17a4bed2a2ef23ccf94f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1774
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 38109d558aaf763eb3708e747d848d7ea23d8345
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 3 19:20:37 2012 -0700

    SMM: Save the GNVS pointer when creating APCI tables
    
    At boot time when the ACPI tables are created and the location
    of GNVS is determined then save that address for resume time.
    
    This also sets the values of USB charging in S3/S5 to the expected
    default values for Stout/Butterfly that were not set correctly.
    
    Change-Id: I9b94b868aa6e81aced06c0262cc2697ad4faf1e6
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1768
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7978e3a3839b69c5b65de8dd8f35b4ffb8e27d93
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 3 19:11:26 2012 -0700

    SMM: Pass the ACPI GNVS pointer via state save map
    
    Instead of hijacking some random memory addresses to
    relay the GNVS pointer to SMM we can use EBX register
    during the write to APM_CNT register when the SMI is
    triggered.
    
    Change-Id: I79a89512c40353d72ad058cbf2e6a23a696945da
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1766
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7f3d442abb2a8ff6f6728527ab7665fd79fd60cd
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 3 19:01:57 2012 -0700

    SMM: Avoid use of global variables in SMI handler
    
    Using global variables with the TSEG is a bad idea because
    they are not relocated properly right now.  Instead make
    the variables static and add accessor functions for the
    rest of SMM to use.
    
    At the same time drop the tcg/smi1 pointers as they are
    not setup or ever used.  (the debug output is added back
    in a subsequent commit)
    
    Change-Id: If0b2d47df4e482ead71bf713c1ef748da840073b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1764
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d396a77b4d144a89a98240541945111280106de6
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 3 18:22:16 2012 -0700

    SMM: Extract function for finding save state node
    
    This is currently used by the ELOG GSMI interface but is a
    good way to pass data to SMM so move the current searching code
    to a separate function and make it a bit more versatile with the
    checks it does to find a match so it can be used in other
    situations.
    
    Change-Id: I5b6f92169f77c7707448ec38684cdd53c02fe0a5
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1763
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 11290c49b0e7f8c13e0128b0e2005b5466b49f5d
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 3 19:07:05 2012 -0700

    SMM: Restore GNVS pointer in the resume path
    
    The SMM GNVS pointer is normally updated only when the
    ACPI tables are created, which does not happen in the
    resume path.
    
    In order to restore this pointer it needs to be available
    at resume time.  The method used to locate it at creation
    time cannot be used again as that magic signature is
    overwritten with the address itself.  So a new CBMEM ID
    is added to store the 32bit address so it can be found
    again easily.
    
    A new function is defined to save this pointer in CBMEM
    which needs to be called when the ACPI tables are created
    in each mainboard when write_acpi_tables() is called.
    
    The cpu_index variable had to be renamed due to a conflict
    when cpu/cpu.h is added for the smm_setup_structures()
    prototype.
    
    Change-Id: Ic764ff54525e12b617c1dd8d6a3e5c4f547c3e6b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1765
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 313ec9d15bb8c56fc76eb40be920552cb231465e
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Fri Nov 2 14:26:44 2012 -0600

    Sandybridge: Set PEG clock gating
    
    If the PEI System Agent doesn't run PCIe initialization, the PEG
    clock gating will not be setup. Add the PEG clock gating when
    pei_data->pcie_init is 0.
    
    Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1827
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7e8c8e92bb7c754a759b7f3bf955f6fd95d44d86
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Sep 4 10:59:29 2012 -0700

    Add PCIe init and NMode flag to PEI data structure
    
    The IvyBridge reference code does some slow and
    extensive PCIe init that we do not need on Link.
    Hence, add a flag to disable/enable running that
    init code from coreboot.
    
    NMode was used during bringup. We'll switch
    the setting back to auto, to let MRC decide the right thing.
    
    Change-Id: Ia989bb9ea079aadfeb41dc3029b7c2c623e84760
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1826
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e8179b51380cf0922466c33a9a0998a65f246a84
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Jul 11 10:40:45 2012 -0700

    Add ddr3lv_support flag to pei_data structure
    
    This will enable DDR3 1.35V support for memory training in
    the reference code.  It requires the board to be setup for
    1.35V with whatever board-specific GPIOs are available.
    
    Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1825
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 53508fedf8bbd49b10f39a18b3bad6b25b71242e
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Wed Jul 11 16:30:28 2012 -0600

    pei_data.h: Fix comment
    
    I added a comment to the pei_data.h to remind users about
    how the OC pins are mapped.
    
    Change-Id: I4d74eb69fc78816a69e61260c2c9b2b3e58cafec
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1824
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 48a4a7f24453e8fd0672146d78d7790539c6a2f8
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Thu Jun 7 18:47:13 2012 -0700

    Provide MRC with a console printing callback function
    
    Let memory initialization code use the coreboot romstage console. This
    simplifies the code and makes sure that all output is available in
    /sys/firmware/log.
    
    The pei_data structure is modified to allow passing the console output
    function pointer. Romstage console_tx_byte() is used for this purpose.
    
    Change-Id: I722cfcb9ff0cf527c12cb6cac09d77ef17b588e0
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1823
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a42e2f4daaa9537eeea41f68eae1ef16265f4010
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 15 13:18:06 2012 -0700

    Add spinlock to serialize Intel microcode updates
    
    Updating microcode on several threads in a core at once
    can be harmful. Hence add a spinlock to make sure that
    does not happen.
    
    Change-Id: I0c9526b6194202ae7ab5c66361fe04ce137372cc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1778
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0a405bafc5d56dd1646020929021d062244dd6e7
Author: Bill Richardson <wfrichar@chromium.org>
Date:   Tue Jun 26 16:33:45 2012 -0700

    cros: Inform U-Boot via fake gpio when VGA Option ROM is loaded
    
    This prepares the way for vboot to inform coreboot when it needs the VGA
    Option ROM loaded. Coreboot can't always know when it's needed (with
    keyboard-based dev-mode, coreboot can't tell if we're in dev-mode or not).
    By the time we get to U-Boot, it's too late, so we need two extra bits - one
    for vboot to tell coreboot to load the Option ROM and another for coreboot
    to let vboot know it's been done.
    
    This change sets up the communication, but doesn't act on it just yet.
    
    Even with this CL we always load the VGA Option ROM, so there's nothing to
    test. There should be no user-visible change.
    
    Change-Id: Ic4e9673a3707b6605064f4879bb3e74d4412322f
    Signed-off-by: Bill Richardson <wfrichar@chromium.org>
    Reviewed-on: http://review.coreboot.org/1822
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6b3d09e7874f2953ab08b5d79caefd68375ca22c
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Aug 28 14:37:57 2012 -0700

    Export optionrom status on Stumpy/Lumpy
    
    ChromeOS' top of the tree u-boot expects coreboot to export information
    about option ROM status (started/not started). Stumpy and Lumpy were
    left behind and are not exporting this information. This CL fixes the
    problem.
    
    Change-Id: Id90035bd76ab177e4fc269efc2b74f15f641c77d
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1713
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c64947b6b1889aa92e32238e5c1a1b2ceb54943e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Oct 1 13:31:25 2012 -0700

    Make EmeraldLake2 work again
    
    Fix GPIO exporting for new Vboot for oprom-matters GPIO
    and to make the power button static.
    
    Change-Id: Ic042c428a1d43512228c686121fa057d876606e1
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1761
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 75dbc389ec62d9ec85178eb5364850c7f9a77997
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 15 15:19:43 2012 -0700

    Clean up stack checking code
    
    Several small improvements of the stack checking code:
    - move the CPU0 stack check right before jumping to the payload
      and out of hardwaremain (that file is too crowded anyways)
    - fix prototype in lib.h
    - print size of used stack
    - use checkstack function both on CPU0 and CPU1-x
    - print amount of stack used per core
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Test: Boot coreboot on Link, see the following output:
         ...
         CPU1: stack: 00156000 - 00157000, lowest used address 00156c68,
               stack used: 920 bytes
         CPU2: stack: 00155000 - 00156000, lowest used address 00155c68,
               stack used: 920 bytes
         CPU3: stack: 00154000 - 00155000, lowest used address 00154c68,
               stack used: 920 bytes
         ...
         Jumping to boot code at 1110008
         CPU0: stack: 00157000 - 00158000, lowest used address 00157af8,
               stack used: 1288 bytes
    
    Change-Id: I7b83eeee0186559a0a62daa12e3f7782990fd2df
    Reviewed-on: http://review.coreboot.org/1787
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4221a195745837b05725d7ffeda415516ac44a7f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 15 15:23:20 2012 -0700

    Add method for delaying adding of timestamps
    
    In hardwaremain() we can't add timestamps before we actually
    reinitialized the cbmem area. Hence we kept the timestamps in
    an array and added them later. This is ugly and intrusive and
    helped hiding a bug that prevented any timestamps to be logged
    in hardwaremain() when coming out of an S3 resume.
    
    The problem is solved by moving the logic to keep a few timestamps
    around into the timestamp code. This also gets rid of a lot of ugly
    ifdefs in hardwaremain.c
    
    Change-Id: I945fc4c77e990f620c18cbd054ccd87e746706ef
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1785
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7004b7c9e61640f1e7e7bf9043bf7b2a8603d956
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Oct 31 17:30:13 2012 -0700

    Add Kconfig option to lock/unlock ME firmware during build
    
    For reasons of security and testing we want to be able to
    enable/disable ME section locking through a config option.
    
    Change-Id: I341c577cdae86be62c0e3d32bbd6b3333c004a5f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1798
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1bfbbc0d8f68b43af7ccda1dde796ed15950c508
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 7 14:00:07 2012 -0700

    clean up lapic_cpu_init.c
    
    - drop changelog and add license header instead
    - 80+ character fixes
    - make stacks array static because it's not used externally
    - rename copy_secondary_start_to_1m_below()
    
    Change-Id: I8b461bea21ee0ddd85ea3a3a923d1e15167f54f0
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1821
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8b93059eccedc528443c06eb86c58bd320dca203
Author: Ronald G. Minnich <rminnich@chromium.org>
Date:   Tue Jun 5 14:41:27 2012 -0700

    Pass the CPU index as a parameter to startup.
    
    This addition is in support of future multicore support in
    coreboot. It also will allow us to remove some asssembly code.
    
    The CPU "index" -- i.e., its order in the sequence in which
    cores are brought up, NOT its APIC id -- is passed into the
    secondary start. We modify the function to specify regparm(0).
    We also take this opportunity to do some cleanup:
    indexes become unsigned ints, not unsigned longs, for example.
    
    Build and boot on a multicore system, with pcserial enabled.
    
    Capture the output. Observe that the messages
    Initializing CPU #0
    Initializing CPU #1
    Initializing CPU #2
    Initializing CPU #3
    appear exactly as they do prior to this change.
    
    Change-Id: I5854d8d957c414f75fdd63fb017d2249330f955d
    Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/1820
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 455f4b432835828e82531adf967b9c7d8fc812dc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Nov 12 15:17:24 2012 -0800

    Fix CONFIG_MAX_CPU set to 1 CPU build problem
    
    There are some function dependancies that didn't work
    when MAX_CPU was set to 1 and the build would fail.
    
    Change-Id: I033a42056f7b48a40316e03772ed89ad9cb013fe
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1819
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 000bf83c934880490d6b1b4c16465cbe7f4f377c
Author: Ronald G. Minnich <rminnich@chromium.org>
Date:   Wed Jun 6 13:00:24 2012 -0700

    Support better tracking of AP stack usage.
    
    This change allows us to figure out how much of the AP stacks we are
    using, as well as to catch any case of an AP overrunning its stack.
    Also, the stack is poisoned, which is a good way to catch programming
    errors -- code should never count on auto variables being zerod.
    
    The stack bases are recorded in a new array, stacks. At the end,
    when all APs are initialized, the stacks are walked and the
    lowest level of the stack that is reached is printed.
    
    Build and boot and look for output like this:
    
    CPU1: stack allocated from 00148000 to 00148ff4:\
    	lowest stack address was 00148c4c
    CPU2: stack allocated from 00147000 to 00147ff4:\
    	lowest stack address was 00147c4c
    CPU3: stack allocated from 00146000 to 00146ff4:\
    	lowest stack address was 00146c4c
    
    Note that we used only about 1K of stack, even though in this
    case we allocated 4K (and in the main branch, we allocate 32K!)
    
    Change-Id: I99b7b9086848496feb3ecd207f64203fa69fadf5
    Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/1818
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 5b635795cc6b104e4d30218817c9b0dc80e4c1c3
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Aug 16 14:05:42 2012 -0700

    SandyBridge/IvyBridge: Add IFD and ME firmware automatically
    
    Right now coreboot's build process produces images that are
    not booting on actual hardware because they are smaller than
    the actual flash device and also don't have an IFD nor an ME
    firmware in them. In order to produce bootable images, you
    needed a wrapper script / extra step until now. With this
    change, the resulting coreboot.rom is actually bootable.
    
    Change-Id: I82714069fb004d4badc41698747a704bd9fed4da
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1771
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cd986c049c28f06e88dd27d361f03b2ad61ddfba
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Aug 28 16:32:09 2012 -0700

    libpayload: Use EXTRA_CFLAGS for additional GCC options
    
    -CFLAGS = $(INCLUDES) -O2 -pipe -g
    +CFLAGS = $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe
    
    Change-Id: Icb228d173312a974746e72b6bbae059103b837fc
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1723
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c7fe280a29c4408aa557a7101616decb1142980e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Sep 19 11:10:15 2012 -0700

    vboot: Add option to skip TPM resume on S3 resume
    
    Change-Id: Ie4a98cc8af0dbcf09c7ace79668949ace5938c12
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1752
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6866c08129b20504cd66f88afb232073249c8725
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Oct 31 22:39:06 2012 -0500

    mmio pci config: Remove register constraints
    
    The currently encoded register constraints fails compilation
    for SMM code or any code that compiles with -fPIC. The reason
    is that the ebx register is used for GOT base register.
    
    I don't believe the comment eluding to register constraints for AMD
    processors still applies. Therefore remove mmio_conf.h, and use the
    mmio methods in io.h.
    
    Change-Id: I391e5c2088ebc760b3a6ed6c37b65bbecab40a5c
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/1801
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 632175802e3d6c3265aa6f511a5aa400d00953d1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 29 16:52:36 2012 -0700

    cbfstool: Rework to use getopt style parameters
    
    - Adding more and more optional and non-optional parameters
      bloated cbfstool and made the code hard to read with a lot
      of parsing in the actual cbfs handling functions. This change
      switches over to use getopt style options for everything but
      command and cbfs file name.
    - This allows us to simplify the coreboot Makefiles a bit
    - Also, add guards to include files
    - Fix some 80+ character lines
    - Add more detailed error reporting
    - Free memory we're allocating
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Change-Id: Ia9137942deb8d26bbb30068e6de72466afe9b0a7
    Reviewed-on: http://review.coreboot.org/1800
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e5a0a5d6df99eb78fbf6469eff35e6d415ec2d54
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Sep 19 10:51:48 2012 -0700

    Initial IGD OpRegion implementation
    
    Change-Id: I9e57c5792409830895a1147799acab95d910a336
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1757
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2e200cde9a58a64f3df5f1c69dcdd57ef9452c3d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Oct 30 14:02:45 2012 -0700

    cbfstool: Update LZMA encoder to LZMA SDK 9.12
    
    This removes almost all C++ code (except the wrapper)
    
    Change-Id: I0f84070e3b6dc57c98d49a53150a140479b3221f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1799
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a5b70676385d6b5da3d18f81042de4a1bb4cf0da
Author: Aaron Durbin <adurbin@chromium.org>
Date:   Wed Oct 31 21:46:35 2012 -0500

    romcc_io: add pci_or_configX functions.
    
    Some of the modules use their own rolled pci_or_configX functions.
    Therefore, make them first class so everyone can use them without
    copying them.
    
    Change-Id: I9a4d3364c832548dbfe18139c27cce2d60c3316d
    Signed-off-by: Aaron Durbin <adurbin@chromium.org>
    Reviewed-on: http://review.coreboot.org/1797
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f75dd09a7f9e46c0c811b9918c9cde7d9d105e6c
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Nov 12 15:48:21 2012 +0800

    x86/Makefile.inc: Test if the strings are equal by single equal sign
    
    Double equal sign like "test a == b" works. It really does, except NetBSD.
    But I haven't found any clue in the manual for the command test about "==".
    
    Change-Id: I37254cfeb688fd1092f2e549d24f8eb270f02fd8
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1817
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 7c6b6bb593e5dae8de5623ee882bac5f28665f29
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Fri Oct 19 10:57:18 2012 -0700

    cbmem compilation needs to use the hardened toolchain
    
    The appropriate compiler (provided by the build system) is used to
    ensure proper toolchain options are used.
    
    cbmem.c is being modified to suppress pointer to integer typecast
    warnings.
    
    Change-Id: Ibab2faacbd7bdfcf617ce9ea4296ebe7d7b64562
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1791
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit feadfb77766c748e8487575ea914fcf68603c1d5
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 6 18:39:41 2012 -0800

    If cmos is invalid, always set the rtc date and time
    
    If cmos is invalid for any reason, always set the date and time
    before marking RTC valid.
    
    Change-Id: Ib9d154802f75221d58bf28ba9c813f2529904596
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1790
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dd76bc0e01f1701602b052eab6197488118df923
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Oct 16 14:23:55 2012 -0600

    Remove duplicate defines from mc146818rtc.c
    
    Remove the duplicate #defines and use what is set in mc146818rtc.h.
    
    Change-Id: Ic471e03c68b591d19c0646fdbea78374af11c8b8
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1789
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ad6779138238dc34e8f9da47730229b5891b5fe1
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Mon Oct 15 14:30:28 2012 -0700

    Avoid using hardcoded values in MRC cache code
    
    The MRC cache code, as implemented, in some cases uses configuration
    settings for MRC cache region, and in some cases - the values read
    from FMAP. These do not necessarily match, the code should use FMAP
    across the board.
    
    This change also refactors mrccache.c to limit number of iterations
    through the cache area and number of fmap area searches.
    
    Change-Id: Idb9cb70ead4baa3601aa244afc326d5be0d06446
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1788
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 08067ba9cbf9904f6637775fe64c8b43229896b6
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 15 13:47:04 2012 -0700

    ivybridge: Catch unknown CPU revisions
    
    Adding an entry for 0x306a0 will make sure that all
    CPUs with CPUIDs 0x306aX will execute the driver (analog to
    Sandybridge behavior)
    
    Change-Id: I0353f3a48ecfd41274fdf6ee302c7d34482f1b5b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1783
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bdc64c6e94bef2efbf4ec7239d1bfafc66dd8ec7
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 15 13:41:56 2012 -0700

    Store timestamps before resuming from suspend
    
    in the resume case, timestamps were collected in RAM stage
    but not stored in CBMEM. This leads to only a single time stamp
    covering 200ms being available for all of ram stage.
    
    Change-Id: Ibf0bb92caf5e032c12fe4e1b9b84b3624d499511
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1781
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9c03957b363f9206b1eacecf9911cc28ae492306
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 15 13:39:00 2012 -0700

    Reduce default stack size to 4K
    
    coreboot uses about 2K of stack on the BSP, and about 1K of stack on the
    APs. No reason to use an overdimensonal stack of 32k per core/thread.
    
    Change-Id: I734c240b992d40e1e35db3df5437c36da0a755cf
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1780
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2a6f390d11daa41e7a85aa1bdbf837fe22854bfc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 15 13:38:09 2012 -0700

    Add dependency for CONFIG_AP_IN_SIPI_WAIT
    
    Change-Id: Ia20c138dae1fc1382abe74303e1117472c513d1d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1779
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d4bc0679540842d78712b41707c2da9f3d7ae204
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Oct 11 13:04:14 2012 -0700

    SPI: Add early romstage SPI driver using hardware sequencing
    
    This is a basic romstage driver that can be used for the
    MRC cache code on systems where we do not have the MRC cache
    stored in a flash region that is memory mapped.
    
    It uses the hardware sequencing interface to avoid having
    to know anything about the flash chip itself.
    
    BUG=chrome-os-partner:15031
    BRANCH=stout
    TEST=manual: this was tested with debug code added to romstage
    that attempted to read the MRC cache at offset 0x3e0000.
    
    SPI READ offset=003e0000 size=64 buffer=ff7fba00
    SPI ADDR 0x003e0000
    SPI HSFC 0x3f00
    SPI READ: 0=4443524d
    SPI READ: 1=00000bb0
    SPI READ: 2=00008e24
    SPI READ: 3=00000000
    SPI READ: 4=001c8bbb
    SPI READ: 5=0c206466
    SPI READ: 6=0a043220
    SPI READ: 7=000058b4
    SPI READ: 8=00000000
    SPI READ: 9=00000000
    SPI READ: 10=00100000
    SPI READ: 11=00100005
    SPI READ: 12=20202025
    SPI READ: 13=000e0001
    SPI READ: 14=00000000
    SPI READ: 15=00000000
    
    Change-Id: I5f78f53111f912ff5dda52bbf90fdc1824b82681
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1777
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 215f27856399b1e4cfe30268fad61bf821af3c19
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 10 14:34:49 2012 -0700

    ELOG: Support for non-memory mapped flash
    
    If the event log is stored in flash that is not memory
    mapped then it must use the SPI controller to read from
    the flash device instead of relying on memory accesses.
    
    In addition a new CBMEM ID is added to keep an resident
    copy of the ELOG around if needed.  The use of CBMEM for
    this is guarded by a new CONFIG_ELOG_CBMEM config option.
    This CBMEM buffer is created and filled late in the process
    when the SMBIOS table is being created because CBMEM is
    not functional when ELOG is first initialized.
    
    The downside to using CBMEM is that events added via the
    SMI handler at runtime are not reflected in the CBMEM copy
    because I don't want to let the SMM handler write to memory
    outside the TSEG region.
    
    In reality the only time we add runtime events is at kernel
    shutdown so the impact is limited.
    
    Test:
    1) Test with CONFIG_ELOG_CBMEM enabled to ensure the event
    log is operational and SMBIOS points to address in CBMEM.
    The test should involve at least on reboot to ensure that the
    kernel is able to write events as well.
    
    > mosys -l smbios info log | grep ^address
    address              | 0xacedd000
    
    > mosys eventlog list
    0 | 2012-10-10 14:02:46 | Log area cleared | 4096
    1 | 2012-10-10 14:02:46 | System boot | 478
    2 | 2012-10-10 14:02:46 | System Reset
    3 | 2012-10-10 14:03:33 | Kernel Event | Clean Shutdown
    4 | 2012-10-10 14:03:34 | System boot | 479
    5 | 2012-10-10 14:03:34 | System Reset
    
    2) Test with CONFIG_ELOG_CBMEM disabled to ensure the event
    log is operational and SMBIOS points to memory mapped flash.
    The test should involve at least on reboot to ensure that the
    kernel is able to write events as well.
    
    > mosys -l smbios info log | grep ^address
    address              | 0xffbf0000
    
    > mosys eventlog list
    0 | 2012-10-10 14:33:17 | Log area cleared | 4096
    1 | 2012-10-10 14:33:18 | System boot | 480
    2 | 2012-10-10 14:33:18 | System Reset
    3 | 2012-10-10 14:33:35 | Kernel Event | Clean Shutdown
    4 | 2012-10-10 14:33:36 | System boot | 481
    5 | 2012-10-10 14:33:36 | System Reset
    
    Change-Id: I87755d5291ce209c1e647792227c433dc966615d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1776
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 23b0053586974e0db70349a272d8cc09167fb4cb
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 10 14:21:23 2012 -0700

    SPI: Fix and enable Fast Read support
    
    - Fix handling of 5-byte Fast Read command in the ICH SPI
    driver.  This fix is ported from the U-boot driver.
    - Allow CONFIG_SPI_FLASH_NO_FAST_READ to be overridden by
    defining a name for the bool in Kconfig and removing the
    forced select in southbridge config
    - Fix use of CONFIG_SPI_FLASH_NO_FAST_READ in SPI drivers
    to use #if instead of #ifdef
    - Relocate flash functions in SMM so they are usable.
    This really only needs to happen for read function pointer
    since it uses a global function rather than a static one from
    the chip, but it is good to ensure the rest are set up
    correctly as well.
    
    Change-Id: Ic1bb0764cb111f96dd8a389d83b39fe8f5e72fbd
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1775
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a571c70c14a86d242be39fc12610b2519499379f
Author: Han Shen <shenhan@google.com>
Date:   Tue Oct 16 10:42:25 2012 -0700

    Fix gcc-4.7 building problem.
    
    Applied function attribute to function definition to avoid 'conflicting type' warning.
    
    Function declaration is in src/include/cpu.h
      void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0)));
    
    But function definition in lapic_cpu_init.c is missing the "__attribute__" part.
    
    Change-Id: Idb7cd00fda5a2d486893f9866920929c685d266e
    Signed-off-by: Han Shen <shenhan@google.com>
    Reviewed-on: http://review.coreboot.org/1784
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 4a17d29fe8003fd2c47cde0672ddf1066aa61f6a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Sep 27 12:42:15 2012 -0700

    ifdtool: Dump more registers from FD
    
    Only thing not decoded now are the PCH straps
    
    ifdtool -d path/to/image.bin
    File path/to/image.bin is 4096 bytes
    Found Flash Descriptor signature at 0x00000010
    FLMAP0:    0x02040003
      NR:      2
      FRBA:    0x40
      NC:      1
      FCBA:    0x30
    FLMAP1:    0x12100206
      ISL:     0x12
      FPSBA:   0x100
      NM:      2
      FMBA:    0x60
    FLMAP2:    0x00210120
      PSL:     0x2101
      FMSBA:   0x200
    FLUMAP1:   0x000004df
      Intel ME VSCC Table Length (VTL):        4
      Intel ME VSCC Table Base Address (VTBA): 0x000df0
    
    ME VSCC table:
      JID0:  0x001740ef
        SPI Componend Device ID 1:          0x17
        SPI Componend Device ID 0:          0x40
        SPI Componend Vendor ID:            0xef
      VSCC0: 0x20052005
        Lower Erase Opcode:                 0x20
        Lower Write Enable on Write Status: 0x50
        Lower Write Status Required:        No
        Lower Write Granularity:            64 bytes
        Lower Block / Sector Erase Size:    4KB
        Upper Erase Opcode:                 0x20
        Upper Write Enable on Write Status: 0x50
        Upper Write Status Required:        No
        Upper Write Granularity:            64 bytes
        Upper Block / Sector Erase Size:    4KB
      JID1:  0x001720c2
        SPI Componend Device ID 1:          0x17
        SPI Componend Device ID 0:          0x20
        SPI Componend Vendor ID:            0xc2
      VSCC1: 0x20052005
        Lower Erase Opcode:                 0x20
        Lower Write Enable on Write Status: 0x50
        Lower Write Status Required:        No
        Lower Write Granularity:            64 bytes
        Lower Block / Sector Erase Size:    4KB
        Upper Erase Opcode:                 0x20
        Upper Write Enable on Write Status: 0x50
        Upper Write Status Required:        No
        Upper Write Granularity:            64 bytes
        Upper Block / Sector Erase Size:    4KB
    
    OEM Section:
    00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    
    Found Region Section
    FLREG0:    0x00000000
      Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
    FLREG1:    0x07ff0180
      Flash Region 1 (BIOS): 00180000 - 007fffff
    FLREG2:    0x017f0001
      Flash Region 2 (Intel ME): 00001000 - 0017ffff
    FLREG3:    0x00001fff
      Flash Region 3 (GbE): 00fff000 - 00000fff (unused)
    FLREG4:    0x00001fff
      Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
    
    Found Component Section
    FLCOMP     0x64900024
      Dual Output Fast Read Support:       supported
      Read ID/Read Status Clock Frequency: 50MHz
      Write/Erase Clock Frequency:         50MHz
      Fast Read Clock Frequency:           50MHz
      Fast Read Support:                   supported
      Read Clock Frequency:                20MHz
      Component 2 Density:                 8MB
      Component 1 Density:                 8MB
    FLILL      0x000060c7
      Invalid Instruction 3: 0x00
      Invalid Instruction 2: 0x00
      Invalid Instruction 1: 0x60
      Invalid Instruction 0: 0xc7
    FLPB       0x00000000
      Flash Partition Boundary Address: 0x000000
    
    Found PCH Strap Section
    PCHSTRP0:  0x0820d602
    PCHSTRP1:  0x0000010f
    PCHSTRP2:  0x00560000
    PCHSTRP3:  0x00000000
    PCHSTRP4:  0x00c8e000
    PCHSTRP5:  0x00000000
    PCHSTRP6:  0x00000000
    PCHSTRP7:  0xc0001ae0
    PCHSTRP8:  0x00000000
    PCHSTRP9:  0x30000580
    PCHSTRP10: 0x00410044
    PCHSTRP11: 0x99000097
    PCHSTRP12: 0x00000000
    PCHSTRP13: 0x00000000
    PCHSTRP14: 0x00000000
    PCHSTRP15: 0x0000033e
    PCHSTRP16: 0x00000000
    PCHSTRP17: 0x00000002
    
    Found Master Section
    FLMSTR1:   0x0a0b0000 (Host CPU/BIOS)
      Platform Data Region Write Access: disabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      disabled
      Host CPU/BIOS Region Write Access: enabled
      Flash Descriptor Write Access:     disabled
      Platform Data Region Read Access:  disabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       disabled
      Host CPU/BIOS Region Read Access:  enabled
      Flash Descriptor Read Access:      enabled
      Requester ID:                      0x0000
    
    FLMSTR2:   0x0c0d0000 (Intel ME)
      Platform Data Region Write Access: disabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      enabled
      Host CPU/BIOS Region Write Access: disabled
      Flash Descriptor Write Access:     disabled
      Platform Data Region Read Access:  disabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       enabled
      Host CPU/BIOS Region Read Access:  disabled
      Flash Descriptor Read Access:      enabled
      Requester ID:                      0x0000
    
    FLMSTR3:   0x08080118 (GbE)
      Platform Data Region Write Access: disabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      disabled
      Host CPU/BIOS Region Write Access: disabled
      Flash Descriptor Write Access:     disabled
      Platform Data Region Read Access:  disabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       disabled
      Host CPU/BIOS Region Read Access:  disabled
      Flash Descriptor Read Access:      disabled
      Requester ID:                      0x0118
    
    Found Processor Strap Section
    ????:      0x00000000
    ????:      0xffffffff
    ????:      0xffffffff
    ????:      0xffffffff
    
    Change-Id: I68a613df2fd80e097cdea46fbad104d7c73ac9ad
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1756
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 4adc8cdd185f46cd62f3bd17188761d3b0b1d87d
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Wed Oct 31 16:24:37 2012 -0600

    Add bd82x6x mainboards ASPM overrides.
    
    The Intel PCH can override the ASPM settings via the MPC2 register.
    Add a chip override for F0-F7. Mainboards may implement this as
    needed.
    
    This also fixes the final PM setup being done too early. It was
    being done prior to the PCIe ASPM setup, which happens in the
    bridge scan.
    
    Change-Id: Idf2d2374899873fc6b1a2b00abdb683ea9f5bd6b
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1796
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2a700ec16322561ad487e6ef1ae8878f9a7e4357
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Oct 8 15:26:54 2012 -0700

    SPI: Configure Software Sequence SPI Freq to match descriptor
    
    Right now the SPI bus is getting set to 20mhz for transactions
    initiated with the software sequence interface.
    
    In order to be able to do reasonable fastread/write/erase we
    can bump this up to a higher value at boot before it gets
    locked at 20mhz.
    
    To do this read out the speed set in the SPI descriptor for
    hardware sequencing and apply it to software sequencing.
    
    Change-Id: I79aa2fe7f30f734785d61955ed81329fc654f4a4
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/1773
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 924342bb2b9e429d66a693503c9f944655da4bb8
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Oct 8 14:30:06 2012 -0700

    SPI: Add Fast Read to the OPMENU for locked down SPI
    
    The chips we are using do not use BE52 (block erase 0x52)
    so we can use that opcode menu location to enable fast read.
    
    Change-Id: I18f3e0e5e462b052358654faa0c82103b23a9f61
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/1772
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fb8632ab58de871ef3a25b5e57c7a2e95f04a0d8
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Sep 30 04:47:48 2012 -0700

    oprom: Ensure that mode information is valid before putting it in the tables.
    
    At least when CONFIG_CHROMEOS is turned on, it's possible for
    CONFIG_FRAMEBUFFER_KEEP_VESA_MODE to be set but for there not to be any valid
    information to put into the framebuffer coreboot table. That means that what's
    put in there is junk, probably all zeroes from the uninitialized global
    variable the mode information is stored in (mode_info).
    
    When a payload uses libpayload and turns on the coreboot framebuffer console,
    that console will attempt to scroll at some point and decrease the cursor's y
    coordinate until it is less than the number of rows claimed by the console.
    The number of rows is computed by taking the vertical resolution of the
    framebuffer and dividing it by the height of the font. Because the mode
    information was all zeroes, the coreboot table info is all zeroes, and that
    means that the number of rows the console claims is zero. You can't get the
    unsigned y coordinate of the cursor to be less than zero, so libpayload gets
    stuck in an infinite loop.
    
    The solution this change implements is to add a new function,
    vbe_mode_info_valid, which simply returns whether or not mode_info has anything
    in it. If not, the framebuffer coreboot table is not created, and libpayload
    doesn't get stuck.
    
    Change-Id: I08f3ec628e4453f0cfe9e15c4d8dfd40327f91c9
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1758
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 04c5bae39054aedbff1865d9dd2633260c23ece3
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Aug 13 09:37:42 2012 -0700

    Define post codes for OS boot and resume
    
    And move the pre-hardwaremain post code to 0x79
    so it comes before hardwaremain at 0x80.
    
    Emit these codes from ACPI OS resume vector as well
    as the finalize step in bd82x6x southbridge.
    
    Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1702
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2c485180a8613695b4886299efca4276fd17be31
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sun Nov 11 18:19:22 2012 -0800

    Updated submodule reference
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: Ibe0e295293aa0f771063f9c0d1d1e6b69f60007a
    Reviewed-on: http://review.coreboot.org/1816
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6d18fd09c380d6195999c69ffa29310c4429f4f1
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Thu Sep 27 19:24:07 2012 -0700

    Utility to dump boot timing table
    
    Coreboot and u-boot create a table of timestamps which allows to see
    the boot process performance. The util/cbmem/cbmem.py script allows to
    access the table after ChromeOS boots up and display its contents on
    the console. The problem is that shipping images do not include Python
    interpreter, so there is no way to access the table on a production
    machine.
    
    This change introduces a utility which is a Linux app displaying the
    timestamp table. Conceivably the output of this utility might be
    included in one of the ChromeOS :/system sections, so it was attempted
    to write this procedure 'fail safe', namely reporting errors and not
    continuing processing if something goes wrong.
    
    Including of coreboot/src .h files will allow to keep the firmware
    timestamp implementation and this utility in sync in the future.
    
    Test:
        . build the utility (run 'make' while in chroot in  util/cbmem)
        . copy `cbmem' and 'cbmem.py' to the target
        . run both utilities (limiting cbmem.py output to 25 lines or so)
        . observe that the generated tables are identical (modulo rounding
          up of int division, resulting in 1 ns discrepancies in some
          cases)
    
          localhost var # ./cbmem
          18 entries total:
    
             1:62,080
             2:64,569 (2,489)
             3:82,520 (17,951)
             4:82,695 (174)
             8:84,384 (1,688)
             9:131,731 (47,347)
            10:131,821 (89)
            30:131,849 (27)
            40:132,618 (769)
            50:134,594 (1,975)
            60:134,729 (134)
            70:363,440 (228,710)
            75:363,453 (13)
            80:368,165 (4,711)
            90:370,018 (1,852)
            99:488,217 (118,199)
          1000:491,324 (3,107)
          1100:760,475 (269,150)
    
          localhost var # ./cbmem.py | head -25
    
          time base 4249800, total entries 18
          1:62,080
          2:64,569  (2,489)
          3:82,520  (17,951)
          4:82,695  (174)
          8:84,384  (1,688)
          9:131,731  (47,347)
          10:131,821  (89)
          30:131,849  (27)
          40:132,618  (769)
          50:134,594  (1,975)
          60:134,729  (134)
          70:363,440  (228,710)
          75:363,453  (13)
          80:368,165  (4,711)
          90:370,018  (1,852)
          99:488,217  (118,199)
          1000:491,324  (3,107)
          1100:760,475  (269,150)
    
    Change-Id: I013e594d4afe323106d88e7938dd40b17760621c
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1759
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 043d4e1be1f72647d8f7cfa8d99736d7ed351c3b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 1 13:50:30 2012 -0700

    Pass correct sleep type to mainboard sleep handler
    
    The sleep type is 5 for S3 and 7 for S5.
    
    Change-Id: I7ffdb3d27b6994ac4a12a343caf4d7abb82fe6ca
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1760
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 836db26b1cd5ebf712f0e847e6f3db87f1204fa2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 3 19:23:11 2012 -0700

    ACPI: Zero pstate/cstate control values in FADT
    
    If these values are non-zero then the kernel will issue
    an SMI for each core (cstate) and package (pstate).
    
    Since we don't do anything with these SMI callbacks we
    can avoid taking the extra SMIs at boot time by zeroing
    these fields.
    
    Change-Id: I3bc5fe0a9f45141d46884cb77ecdfaeaa45d2439
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1769
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f5a11aa82f66a77a4b79b602604a8516ca187c3b
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Thu Oct 25 14:01:37 2012 -0600

    Initialize the VMX MSR
    
    The VMX MSR may come up with random values and needs to be
    initialized to zero. This was done incorrectly in finalize_smm.
    It must be done on a per core basis in the general CPU init.
    This touches all Sandybridge and Ivybridge configs.
    
    Change-Id: I015352d0f8e2ebe55ac0a5e9c5bbff83bd2ff86b
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1794
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5986edadff53075f4bb5fe419514962c96f9faf6
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Thu Oct 25 09:37:19 2012 -0600

    Revert "Remove code that enables/disables VMX in coreboot on chromebooks."
    
    The MSR for VMX can start with a random value and needs to be
    cleared by coreboot. I am reverting this change, as
    it handles almost everything and doing a follow-on change to fix
    the improper clearing of the MSR.
    
    Change-Id: Ibad7a27b03f199241c52c1ebdd2b6d4e81a18a4e
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1793
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bb9dff55560e2f1834ec9bb41d4929ed3c749818
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 15 13:45:11 2012 -0700

    sandybridge: Correct reporting of cores and threads
    
    The reporting of cores and threads in the system was a bit
    ambiguous. This patch makes it clearer.
    
    Change-Id: Ia05838a53f696fbaf78a1762fc6f4bf348d4ff0e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1786
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cb6fd30155f404eaaeed4252400d248059825f0d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Oct 23 15:56:16 2012 -0700

    cbfstool: Remove unused cmd_t
    
    Change-Id: Ib1c05828258b9dc7107920ae6cb25bc92ffa86d1
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1795
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 20848ee288a74a2320411b33fa19dce78133c890
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 22 16:04:13 2012 -0700

    cbfstool: add add-flat-binary command to add raw executables
    
    Example:
    cbfstool image-link.bin add-flat-binary u-boot.bin fallback/payload \
    	0x100000 0x100020
    will add u-boot.bin as fallback/payload with a load address of 0x100000
    and an entry-point of 0x10002.
    
    Change-Id: I6cd04a65eee9f66162f822e168b0e96dbf75a2a7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1792
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4bb0731a7beaada481371fb19117cdf9f62f5f23
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Oct 5 11:43:39 2012 -0700

    libpayload: Add an option to skip console initialization on startup.
    
    A payload may want to decide whether it uses certain input/output consoles,
    or that it wants support for outputing to a particular device but not to use
    that device as a console. This change adds a config option which skips the
    call to console_init in start_main.
    
    Change-Id: I32b224d4d0bd3a239b402ecb09ee907d53225735
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1732
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit d94512edee3fa0ebf426cd6f3b526d9fe1f078ad
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Oct 1 18:05:50 2012 -0700

    libpayload: Add CB_ prefixes to some constants in coreboot_tables.h.
    
    This makes their names more consistent with other constants in this header,
    avoids name collisions, and makes it more obvious where the names came from.
    
    Change-Id: I7b8bd4ada0fbaf049f35759a907281265f5bb2e6
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1729
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 025667f0eceaf7988b291fc3adfbee2916c23a4e
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Oct 1 17:54:03 2012 -0700

    libpayload: Change "GPIOs" into flags.
    
    Some constants which were used to interpret the contents of the coreboot
    tables were moved to the appropriate libpayload header file. The constant which
    describes the maximum length of a GPIO name was renamed to have a CB_ prefix.
    That makes it more obvious what sort of GPIO name it describes, and reduces the
    change of a name collision. It also makes it more consistent with other names
    in that header, although some other exceptions still exist.
    
    Change-Id: I6c0082b3198d34e8a78507fbfac343ee8facf0dc
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1728
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 2fef58eaba93ede5a177afc3538f80a90f4a433e
Author: Anton Kochkov <a.kochkov@securitycode.ru>
Date:   Fri Nov 9 14:06:05 2012 +0100

    [PATCH] libpayload: Implement EHCI reset function
    
    Added ehci_reset() function to do a full reset of
    the host controller
    
    Change-Id: Ia48db8462ebbb8f260813eb6ba8349d002c4678b
    Signed-off-by: Anton Kochkov <a.kochkov@securitycode.ru>
    Reviewed-on: http://review.coreboot.org/1814
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a1ea82283d868af3681c3575722753f0789b941d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Aug 15 16:28:48 2012 -0700

    Make coreboot use the offset parameter in cbfstool create
    
    On Sandybridge and Ivybridge systems the firmware image has to
    store a lot more than just coreboot, including:
    - a firmware descriptor
    - Intel Management Engine firmware
    - MRC cache information
    This option allows to limit the size of the CBFS portion in
    the firmware image.
    
    Change-Id: Ib87fd16fff2a6811cf898d611c966b90c939c50f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1770
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0a1c2d62faed99edb5ffb53c2058cc6847568be0
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Thu Sep 27 18:42:57 2012 -0700

    Prevent inclusion of tsc.h when not needed
    
    src/include/timestamp.h is an interface describing timestamp storage
    in coreboot. Exporting this interface is complicated by inclusion of
    tsc.h which is needed only for the API and is not used in structure
    definitions. Including this dependency only when needed fixes the
    problem.
    
    Change-Id: Ie6b1460b1dab0f5b5781cb5a9fa89a1a52aa9f17
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1753
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 9d81c19a88dc550353922de2122d4d6e82173151
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Sep 19 10:49:12 2012 -0700

    PCH: Add register descriptions used by IGD OpRegion
    
    These bits are used by the IGD OpRegion code
    
    Change-Id: I89a11fc5021d51e0c1675ba56f6a3bc3b79bb8aa
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1751
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 0acdcf614c9966112add57226e7473bccd86dd64
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Sep 19 10:32:25 2012 -0700

    Add IGD Opregion variables to NVS
    
    In order to support Intel's IGD Opregion standard, we need
    an additional set of flags shared between firmware, ACPI, SMM, and the
    graphics driver.
    
    Change-Id: I1a9b8dff5e5ee8d501b6672bc3bcca39ea65572e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1750
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4c8027abdd3492bc0507906ea3109c0420159ae0
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Sep 7 10:53:56 2012 -0700

    Make register/value lists const
    
    These can be stored in the code segment, since it's never changed.
    
    Change-Id: I8b3827838e08e6cc30678aad36c39249fbca0c38
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1749
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fa66eaefc2c1ef11e97ae638125f42c3044fe024
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Sep 6 12:13:43 2012 -0700

    Get rid of hard coded strings in ACPI tables
    
    (cosmetical)
    
    Change-Id: I3e01d8fbf2d71abcfcbe47efedd2184566c91df7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1748
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bceaf7fea0e8201653e62e0f6f18fb845baea219
Author: Martin Roth <martin@se-eng.com>
Date:   Fri Sep 7 15:02:35 2012 -0600

    Add Gigadevice SPI rom support
    
    Add support for GigaDevice SPI ROMS.
    The GD25Q64B device has been tested, the other rom devices added to the
    file have not.
    
    Change-Id: If35676ca6b90329f15667ebb32efa0d1a159ae91
    Signed-off-by: Martin Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1747
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 39f6bb64d1cfaf8abd8d9efd2df8536e003ad9fc
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Sep 10 10:03:46 2012 -0700

    ELOG: Add EC events to elog header
    
    These events were initially for Chrome EC but they can be
    applied to any EC.
    
    Change-Id: I0eba9dbe8bde506e7f9ce18c7793399d40e6ab3b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1746
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 312ee0ca7096cdb35fe53e4b5e3285509e93bc68
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sun Sep 9 20:12:32 2012 -0700

    SPI: re-init SMM SPI driver after lockdown
    
    If the driver is initialized before the lockdown then it will
    fail to work after the lockdown bit is set.
    
    Change-Id: Idc05d33d8d726bf29cb3c9b1b4604522bd64170a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1745
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8e7d7fd4bf3bf0a0387af7616d739ec4aba9b1f0
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Oct 5 23:43:37 2012 -0700

    libpayload: Add a function to retrieve the rows and cols of the video console.
    
    This is useful if you need to put some text in a particular place on the
    screen, for instance in the middle.
    
    Change-Id: I3dae6b62ca1917c5020ffa3e8115ea7e8e5c0643
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1734
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dd9e4e58cdd0a684e301f1b16b2f92e20e0b3418
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Oct 5 23:35:04 2012 -0700

    libpayload: Separate video initialization and the video console.
    
    It's possible to want to display text on the display without using it as a
    console. This change separates the initialization of the video code from
    setting up the video console by pulling out everything but installing the
    console into a new function called video_init.
    
    Change-Id: Ie07654ca13f79489c0e9b3a4998b96f598ab8513
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1733
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a54b6a61433600fe80d215dc8f8489fab44d0bfd
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Sep 29 00:21:27 2012 -0700

    libpayload: Add support for the CBMEM in memory console.
    
    Change-Id: I1489b5306ef1ca078686fed4dba2d242f70ad941
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1727
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 87abeff334c2a90e743434c4549da3cfce4d144a
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Aug 14 16:32:30 2012 -0700

    Change flashmap base to reflect new FMAP in U-boot
    
    The RO_FMAP base moved from 0x5f0000 to 0x610000.
    
    Also update Kconfig default and add a descripton so
    the default can be changed by boards.
    
    Change-Id: I0caad0ce6e6f19750dbbf042a5a489b558f62b96
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1705
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3c53d33c780f67666e9f8645fd87035d42bfb947
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Sep 26 17:33:39 2012 -0700

    ifdtool: Add locking/unlocking and dumping of access permissions
    
    ifdtool will now dump access permissions of system comonents to
    certain IFD sections:
    
    Found Master Section
    FLMSTR1:   0xffff0000 (Host CPU/BIOS)
      Platform Data Region Write Access: enabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      enabled
      Host CPU/BIOS Region Write Access: enabled
      Flash Descriptor Write Access:     enabled
      Platform Data Region Read Access:  enabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       enabled
      Host CPU/BIOS Region Read Access:  enabled
      Flash Descriptor Read Access:      enabled
      Requester ID:                      0x0000
    
    FLMSTR2:   0x0c0d0000 (Intel ME)
      Platform Data Region Write Access: disabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      enabled
      Host CPU/BIOS Region Write Access: disabled
      Flash Descriptor Write Access:     disabled
      Platform Data Region Read Access:  disabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       enabled
      Host CPU/BIOS Region Read Access:  disabled
      Flash Descriptor Read Access:      enabled
      Requester ID:                      0x0000
    
    FLMSTR3:   0x08080118 (GbE)
      Platform Data Region Write Access: disabled
      GbE Region Write Access:           enabled
      Intel ME Region Write Access:      disabled
      Host CPU/BIOS Region Write Access: disabled
      Flash Descriptor Write Access:     disabled
      Platform Data Region Read Access:  disabled
      GbE Region Read Access:            enabled
      Intel ME Region Read Access:       disabled
      Host CPU/BIOS Region Read Access:  disabled
      Flash Descriptor Read Access:      disabled
      Requester ID:                      0x0118
    
    Also, ifdtool -u /path/to/image will unlock the host's
    access to the firmware descriptor and ME region.
    ifdtool -l /path/to/image will lock down the host's
    access to the firmware descriptor and ME region.
    
    Change-Id: I3e081b80a9bcb398772416f143b794bf307b1c36
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1755
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 0e6d0edccea45c4dd8e3d7af25b3667330433699
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Nov 9 19:55:04 2012 +0800

    mc146818rtc: Remove the hyphen to build on NetBSD and Darwin
    
    http://netbsd.gw.com/cgi-bin/man-cgi?date++NetBSD-current
    The NetBSD manual tells us the date in NetBSD doesn't take any flags
    to enable or disable padding in the format.
    
    By default, date pads numeric fields with zeroes. This will convert the
    number to octal one. So add "0x" to convert it to BCD directly.
    
    Change-Id: Icd44312acf01b8232f1da1fbaa70630d09007b40
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1804
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 094920ddd327149e1f513bca413e536806b69f9e
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Nov 9 18:15:54 2012 +0800

    mc146818rtc: Update the Day of Week in CMOS in the right way.
    
    The range of weekday in CMOS is 01-07, while the Sunday is 1, and
    Saturday is 7. The comand date in coreutils defines
      %u   day of week (1..7); 1 is Monday
      %w   day of week (0..6); 0 is Sunday
    There are 1 day offset for each week day. So we use "%w" and plus 1
    before we update the weekday in CMOS.
    
    Change-Id: I3fab4e95f04924ff0ba10a7012b57da1d3f0d1a5
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1802
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 2799e3f75034125bb248978803ceb30de0f6abd6
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Nov 9 18:12:15 2012 +0800

    Makefile.inc: Delete trailing space in build.h
    
    Change-Id: I0c5ed84a405dc9e98e8912ccf1a2f83c4c601fc7
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1803
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 7a12a32670e063fe109206571324560e991acb4a
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Nov 9 02:15:40 2012 +0100

    Fix abuild output in Jenkins
    
    Ignore the harmless broken pipe messages from "yes"
    
    Building amd/pistachio; i386: ok, using i386-elf-gcc
    Using payload /srv/jenkins/payloads/seabios/bios.bin.elf
      Creating config file... (blobs, ccache) yes: standard output: Broken pipe
    yes: write error
    ok;  Compiling image on 4 cpus in parallel .. ok. (took 10s)
    
    Change-Id: Ic53e246aac3ab6d7ea7a006a8dfac1c3f85797bc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1813
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 5e93b37310abe92ba101a32fe66c9e02f8d887e9
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Sep 25 13:30:48 2012 -0700

    Fix Segmentation Fault in ifdtool
    
    If a section is bigger than the FD file it is injected into, and the FD
    lies about the size of the FD file, ifdtool would crash because reading
    in the section writes beyound the FD file in memory.
    
    Change-Id: Idcfac2b1e2b5907fad34799e44a8abfd89190fcc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1754
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 6604ceb6a06745af1a4f4ce5d28b08b8a7bb57de
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Nov 7 14:35:07 2012 +0100

    mainboard/roda/rk886ex: Disable CHECK_SLFRCS_ON_RESUME
    
    This makes resume from S3 work again. The check is new and fails on
    other boards, too.
    
    Change-Id: I0ada569e4ba649b9ac82768b0888e16104c621e8
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1809
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d0b860aada4c2016c5928c5847d8226cbd0840fc
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Mon Aug 27 11:19:55 2012 -0700

    Add utility for parsing/modifying DTD array
    
    Detailed timing descriptor (DTD) is an 18 byte array describing video
    mode (screen resolution, display properties, etc.) in Intel Option
    ROM. Option ROM can support multiple video modes, specific mode is
    picked by the BIOS through the appropriate Option ROM callback
    function.
    
    The new utility allows to interpret the 18 byte hex DTD dump, and/or
    modify certain values, and generate a new DTD.
    
    To parse the DTD contents just pass the 18 bytes to the utility in the
    command line. To modify the existing contents and generate a new dump
    precede the 18 bytes with '-m' and follow prompts.
    
    Change-Id: Ib00bdaf42c350b98b5a48d08e6bb347b5ec25a8b
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1711
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0af03d24f816ae1e7f1610cf40d6a23c32dbd470
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Mar 19 03:06:46 2012 -0700

    Refactor the endianness conversion functions and header files.
    
    The endianness of an architecture is now set up automatically using Kconfig
    and some common code. The available conversion functions were also expanded
    to go to or from a particular endianness. Those use the abbreviation le or be
    for little or big endian.
    
    Built for Stumpy and saw coreinfo cbfs support work which uses network
    byte order. Used the functions which convert to little endian to implement an
    AHCI driver. The source arch is also little endian, so they were effectively
    (and successfully) inert.
    
    Change-Id: I3a2d2403855b3e0e93fa34f45e8e542b3e5afeac
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1719
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d3890cc16de538c44ed1419a1df54bde560d1787
Author: Gabe Black <gabeblack@google.com>
Date:   Sun Mar 11 01:57:53 2012 -0800

    Update libpayloads understanding of the coreboot tables.
    
    Give it somewhere to put the new info in sysinfo, and tell it how to parse
    the new tables which it doesn't yet understand.
    
    Change-Id: I01d3318138696e6407553c27c1814f79e3fbc4f8
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1718
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1fc346179262f4d4b0ce2f97970f775407a39a1c
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sun Sep 9 19:14:45 2012 -0700

    Log unexpected post code from the previous boot
    
    Read out the post code from the previous boot and
    log it if the code is not one of the expected values.
    
    Test:
    1) interrupt the boot of the system, this is easiest
    with warm reset button when servo is attached
    2) check the event log with mosys
    
    65 | 2012-09-09 12:32:11 | Last post code in previous boot | 0x9d
    
    Change-Id: Id418f4c0cf005a3e97b8c63de67cb9a09bc57384
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1744
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b6e97b19ae6a68556838c9801c7824302d72151f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sun Sep 9 19:09:56 2012 -0700

    Add support for storing POST codes in CMOS
    
    This will use 3 bytes of CMOS to keep track of the POST
    code for the current boot while also leaving a record of
    the previous boot.
    
    The active bank is switched early in the bootblock.
    
    Test:
    1) clear cmos
    2) reboot
    3) use "mosys nvram dump" to verify that the first byte
    contains 0x80 and the second byte contains 0xF8
    4) powerd_suspend and then resume
    5) use "mosys nvram dump" to verify that the first byte
    contains 0x81 and the second byte contains 0xFD
    
    Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1743
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 31409617a46c5ac6ef1a893d3c478f76ce4d7d3d
Author: Stefan Reinauer <reinauer@google.com>
Date:   Wed Aug 22 17:01:08 2012 -0700

    x86 memcpy: Copy 4 bytes at once
    
    This is a slight improvement over the rep movsb loop
    
    Change-Id: Id71d9bfe5330b154a5c62fac85ce3955ae89b057
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1742
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4b1610d766aa1ea0c825b39600fe8a3eb6d2a6be
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Sep 5 10:52:44 2012 -0700

    RTC: Don't clear pending interrupt in resume path
    
    The linux kernel relies on the RTC reporting pending interrupts if
    the RTC alarm was used to wake the system.  If we clear these flags
    here then the rtc-cmos driver in the kernel will think that no
    interrupts are pending and will not re-start the timerqueue to
    handle the alarm timerqueue node.
    
    This flag doesn't exist in SMM but the rtc code is compiled there.
    Since rtc_init() is not called by SMM it is guarded with an ifdef.
    
    I performed several thousand suspend/resume cycles without seeing
    an issue where hwclock was unable to read from /dev/rtc.  There
    still is a potential kernel issue where the timerqueue can stall
    but this makes that much less likely to happen on resume.
    
    Change-Id: I5a343da4ce5c4c8ec4783b4e503869ccfa5077f0
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1741
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2558c736a06c416e41bb35c2e6439f457e541f61
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Sep 4 11:11:58 2012 -0700

    smi: make tseg_relocate check pointer offset
    
    In case tseg_relocate() is called again on a pointer we should not
    relocate it again.
    
    Change-Id: Ida1f9c20dc94b448c773b14d8864afe585369119
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1740
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5c88c6f2d797b7fbcbf844a79356fcc833eb5338
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Sep 1 14:00:23 2012 -0700

    elog: add extended management engine event
    
    We are seeing ME disabled and ME error events on some devices
    and this extended info can help with debug.
    
    Also fix a potential issue where if the log does manage to get
    completely full it will never try to shrink it because the only
    call to shrink the log happens after a successful event write.
    Add a check at elog init time to shrink the log size.
    
    Change-Id: Ib81dc231f6a004b341900374e6c07962cc292031
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1739
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3beb6db6dda7795639d2bb8ec1a1aa3106a4c301
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Sep 1 13:44:17 2012 -0700

    spi: fix erase in SMM while SPIBAR is locked
    
    The handling of write enable was not entirely correct,
    the opcode needs to be skipped when the controller is
    locked down.
    
    Addresses were not getting set properly for erase commands
    which seemed to mostly work when the previous command had
    set an address.
    
    Tested by adding events to the event log at runtime on a
    freslhy flashed device (with locked down SPI controller)
    until the log log shrink happens to ensure it does not hang:
    
    hexdump -C elog.event.kernel_clean
    00000000  01 00 00 00 ad de 00 00  00 00
    
    for x in $(seq 1 232); do
     cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog
    done
    
    mosys eventlog list | tail -6
    154 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
    155 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
    156 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
    157 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
    158 | 2012-09-01 13:54:43 | Log area cleared | 1030
    159 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
    
    Change-Id: I3a50dae54422a9ff37daefce3632f8bcbe4eb89f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1717
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 00ba25decb105c4efd6e23ad985833e1d5d8b75d
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Fri Aug 31 11:15:37 2012 -0700

    Get more informative output from cbmem.py
    
    This is a cosmetic change which formats timestamp information
    retrieved by cbmem.py.
    
    Instead of printing timestamps in a single line, print them one per
    line and add time (in us) elapsed since the previous timestamp.
    
         time base 4149594, total entries 18
         1:56,928
         2:58,851  (1,923)
         3:175,230  (116,378)
         4:175,340  (109)
         8:177,199  (1,859)
         9:214,368  (37,168)
         10:214,450  (81)
         30:214,462  (11)
         40:215,205  (743)
         50:217,180  (1,974)
         60:217,312  (132)
         70:436,984  (219,671)
         75:436,993  (8)
         80:441,424  (4,431)
         90:442,487  (1,062)
         99:553,777  (111,289)
         1000:556,513  (2,736)
         1100:824,621  (268,107)
    
    Change-Id: I0d25cafe766c10377017697e6b206276e1a92992
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1716
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f27d36c361abef8fcbb377a8949067290770571a
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Wed Aug 29 15:03:09 2012 -0700

    Fix cbmem to work on 64 bit platforms
    
    For some reason which I fail to understand, specifying endiannes using
    '@' (which means 'native' and should be the same as '<' on x86
    platforms) causes cbmem.py to crash the machine on 64 bit systems.
    
    What happens is that the addresses read from various table headers'
    struct representations do not make sense, when bogus address gets
    passed to get_phys_mem, the crash happens while that function is
    executed.
    
    dlaurie@ found out that replacing "@" with "<" in fact fixes the
    issue. After some investigation I am just submitting this fix without
    much understanding of the root cause.
    
    Change-Id: Iaba9bc72a3f6b1d0407a5f1e3b459ccf5063969d
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1715
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 01c3de9bb45e09edfe715ec2934805b5ea2edd2f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Aug 29 09:28:52 2012 -0700

    Make option rom init more verbose
    
    When bringing up VGA by running the option rom it's sometimes
    useful to get more information about the mode that gets set,
    or the reason why the mode could not be set or a picture could
    not be displayed. Also prefix the output from VBE mode setting
    with VBE:
    
      Copying VGA ROM Image from fff0fd78 to 0xc0000, 0x10000 bytes
      Real mode stub @00000600: 867 bytes
      Calling Option ROM...
      int15_handler: INT15 function 5fac!
      ... Option ROM returned.
      VBE: Getting information about VESA mode 4161
      VBE: resolution:  1280x1024@16
      VBE: framebuffer: d0000000
      VBE: Setting VESA mode 4161
      VGA Option ROM has been loaded
    
    Change-Id: I2be11f095dc62ed3c99e0d4272ad9d6521608a44
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1714
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a90bd527d9c450974a7c3a45be026331927823cc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Aug 15 16:05:50 2012 -0700

    cbfstool: add offset parameter to create command
    
    CBFS allows coreboot rom images that are only partially covered
    by the filesystem itself. The intention of this feature was to
    allow EC / ME / IMC firmware to be inserted easily at the beginning
    of the image. However, this was never implemented in cbfstool.
    
    This patch implements an additional parameter for cbfstool.
    
    If you call cbfstool like this:
    cbfstool coreboot.rom create 8192K bootblock.bin 64 0x700000
    it will now create an 8M image with CBFS covering the last 1M of
    that image.
    
    Test:
         cbfstool coreboot.rom create 8192K bootblock.bin 64 0x700000
         creates an 8M image that is 7M of 0xff and 1M of CBFS.
    
    Change-Id: I5c016b4bf32433f160b43f4df2dd768276f4c70b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1708
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 86bf3f518f445f686bb7405f052a0a93cddba16a
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Aug 15 13:14:58 2012 -0700

    ELOG: Find flash base in FMAP if possible
    
    Now that we have FMAP support in coreboot use it to find the
    offset in flash for ELOG to use.
    
    If coreboot has elog configured with a smaller size then use
    that over the FMAP size.  This is because I set aside a 16KB
    region in the FMAP but we only use 4KB of it to keep the impact
    to boot/resume speed to a minimum.
    
    FMAP: Found "FMAP" version 1.0 at ffe10000.
    FMAP: base = 0 size = 800000 #areas = 32
    FMAP: area RW_ELOG found
    FMAP:   offset: 3f0000
    FMAP:   size:   16384 bytes
    FMAP: No valid base address, using 0xff800000
    ELOG: base=0x003f0000 base_ptr=0xffbf0000
    ELOG: MEM @0x00190ad8 FLASH @0xffbf0000
    ELOG: areas are 4096 bytes, full threshold 3072, shrink size 1024
    
    Change-Id: I3d826812c0f259d61f41b42797c58dd179f9f1c8
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1706
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f1c76ef60547e3dd38d3554dba227351112d843a
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Aug 27 13:51:23 2012 -0700

    ELOG: Don't disable SPI controller lockdown
    
    Now that WREN prefix is handled properly ELOG is able to write
    when the SPI controller is locked down.
    
    To test, ensure that runtime SPI write via ELOG is successful by
    checking the event log for a kernel shutdown reason code:
    
    5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown
    6 | 2012-08-27 11:09:50 | System boot | 26
    7 | 2012-08-27 11:09:50 | System Reset
    
    Change-Id: If6d0dced7cb0f5ca7038b3d758f31b856826d30b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1712
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit a2f1b953401d071b45eb51bc21ab174759fcc13f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Aug 27 11:10:43 2012 -0700

    SPI: opmenu special case for WREN as atomic prefix
    
    The code that attempts to use the opmenu needs to have a special
    case for write enable now that it is handled as an atomic prefix
    and not as a standalone opcode.
    
    To test, ensure that runtime SPI write via ELOG is successful by
    checking the event log for a kernel shutdown reason code:
    
    5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown
    6 | 2012-08-27 11:09:50 | System boot | 26
    7 | 2012-08-27 11:09:50 | System Reset
    
    Change-Id: I527638ef3e2a5ab100192c5be6e6b3b40916295a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1710
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit 5c103aa8ae56c0758a3e8af11dc70fb62f833f7e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Aug 16 16:06:03 2012 -0700

    RTC: Write build date in BCD when clearing RTC CMOS
    
    Check the RTC on boot after RTC battery failure and ensure
    that the reported build date matches what is reported:
    
    > grep ^rtc /proc/driver/rtc
    rtc_time        : 01:00:21
    rtc_date        : 2012-08-16
    
    Change-Id: If23f436796754c68ae6244ef7633ff4fa0a93603
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1709
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit 93ded5905c36d34c4e4f132623c854bbd895b8c9
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Nov 1 15:44:10 2012 -0700

    libpayload: Turn the "debug" #define into the usb_debug static inline function.
    
    The "debug" macro used internally in the libpayload USB subsystem was very
    generically named and would leak into consumers of the library that included
    usb.h directly or indirectly. This change turns that #define from a macro into
    a static inline function to move away from the preprocessor, and also renames
    it to usb_debug so it's less likely to collide with something unrelated.
    
    Change-Id: I18717df111aa9671495f8a2a5bdb2c6311fa7acf
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1738
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 8670b9b81aba6bf51510e337d4f7208d2b4ea320
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Oct 31 15:55:16 2012 -0700

    libpayload: Take usb_poll out of usb_initialize.
    
    While it might be slightly more convenient to not have to call usb_poll
    manually after calling usb_initialize, you'll still likely want to call it
    before trying to use a USB device since one have have been hotplugged since
    you last looked. By not calling usb_poll, usb_initialize completes quickly and
    can be called unconditionally without a long delay. The delay can be put off
    until later when we're sure it's necessary.
    
    Change-Id: Ib8b1bdea996702c42d1b7021f492d9f8e174d304
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1737
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 1b33c31cf30ab250f598ed4b3fc4e3cea4c89071
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Oct 8 01:58:37 2012 -0700

    libpayload: Make usb_initialize more efficient and fix style problems.
    
    The usb_initialize function would scan for USB host controllers by brute force
    iterating over all possible busses, devices, and functions. This change makes
    it recursively scan busses only if it finds them on the other side of a bridge,
    and only scan for functions beyond function 0 if the device claims to be
    multifunction.
    
    This change also takes the opportunity to clean up some style problems
    throughout the file.
    
    Change-Id: I0f5e8b9a454a42a76d30bccca898c8e1af770b2b
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1736
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 78e15a31f2fd7dedf36898790c2fe3fdc03d287b
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Oct 8 01:56:54 2012 -0700

    libpayload: Add definitions for more config space registers.
    
    Change-Id: I02cf353ce7c955cb11ca11c0d5b8aa630cf15fdb
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1735
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e88e1ab864c636c020e124846f908439c1080d16
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Oct 2 00:32:59 2012 -0700

    libpayload: Add the format attribute to functions in stdio.h.
    
    gcc recognizes the format function attribute which tells the compiler to expect
    the format string to look a certain way and for its arguments to be of
    appropriate types. This helps to prevent errors like the one that was recently
    fixed in libpayload's assert.
    
    Change-Id: I284ae8bff32f72cfd2d1a250d126c729b38a5730
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1731
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5c27e82073ec6bb96a672b18c2c66773ae887ebf
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Oct 2 00:28:33 2012 -0700

    libpayload: Fix the format string of the assert macro.
    
    The assert macro in libpayload was using a format string which printed the
    line number with %s. The line number came from the __LINE__ predefined macro
    which resolves to an integer constant.
    
    Change-Id: I0e00d42a1569802137cf440af3061d7f397fdd27
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1730
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3b84086e3dc5ff9e50a1ea847fd7dac2e687d471
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Sep 27 17:42:23 2012 -0700

    libpayload: Add faster, architecture specific versions of memset and memcpy.
    
    Change-Id: I0f3a82de860fd3afa10a557b37fb90fe6b06ae90
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1726
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit c324794cb09d0c6495992c9f6cece6e4c67f8c9f
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Sep 27 17:39:41 2012 -0700

    libpayload: Make the symbols in memory.c weak so they can be overridden.
    
    The implementations for various stdlib functions in libc/memory.c are very
    generic and should work under just about any circumstances. They are
    unfortunately also very slow. This change makes them weak symbols so that
    faster versions can be defined on a per architecture basis which will
    automatically take the place of the slow versions.
    
    Change-Id: Ia1ac90d9dcd45962b2a15f61ecc74b0a4676048d
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1725
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 5ab20054d3c6e637fbcde46a08d2a3c0891bf658
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Aug 28 16:38:34 2012 -0700

    Update the way serial info is read from the coreboot tables.
    
    This information is now stored in a structure instead of in a few seperate
    fields. libpayload hadn't been updated to reflect the new layout or to consume
    the new information intelligently.
    
    Change-Id: Ice3486ffcdcdbe1f16f9c84515120c591d8dc882
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1724
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 54c800a50c2c052ce13e29bedc608e180fddc70b
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Aug 28 16:31:09 2012 -0700

    Move the definition of ipchksum into its own header file.
    
    Change-Id: Ifb7c18f9ca566bd50ca138ffd8af951375089537
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1722
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit b9edbbd7bf799a194fc76bf9a514e4547fe97d26
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Apr 17 15:59:56 2012 -0700

    Discard .note sections when linking.
    
    These end up being loaded at 0 otherwise and overwrite some coreboot tables.
    
    Built and booted on Stumpy. Saw that the coreboot tables were no longer
    overwritten.
    
    Change-Id: Ia9f521d976d0ad544a8205323ae0ddfa8d253d29
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1721
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit accc6a5e046b66c84b01556e93a71800afe8ea68
Author: Gabe Black <gabeblack@google.com>
Date:   Tue Apr 17 15:35:00 2012 -0700

    Include stdint.h in libpayload's rdtsc.h.
    
    This file uses uint*_t types but hadn't included stdint.h itself.
    
    Change-Id: Ib883f62951bae1ece5134c6bd0f4799a80740e8e
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/1720
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 746d17434797a7ce9009dae4689f8d08ad5a841a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Aug 15 16:02:52 2012 -0700

    cbfstool: respect dependencies when building locally
    
    cbfstool was not looking at any dependencies when building
    by running make in util/cbfstool. By fixing this it's not
    required to make clean every time you edit a file in there.
    
    Change-Id: I544fd54d4b9dd3b277996c21ade56dc086b84800
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1707
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit b1c8f81b25cd77056f653b9a7d5f24e65e40e655
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Aug 13 09:41:54 2012 -0700

    SMI: Change order of SMI_EN and PM1_EN init
    
    This appears to fix an infrequent resume hang on Ivybridge.
    
    Tested on 2 devices with 15k suspend/resume cycles each
    
    Change-Id: I53618bc7966824413f1720a2be3cbd2550e29473
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1704
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit 4dceba25af5ae025fb2592f478a0f29c0eca7fb5
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Aug 13 09:40:02 2012 -0700

    EC: Prepare to read and log last post code from previous boot
    
    (elog portion, support in EC code pending)
    
    - Use a new EC command to read the last post code
    from the previous boot
    - If the post code is not well-known final boot
    or resume code then log it
    
    Change-Id: Id6249e9a182243eb87c777edd56f48de72125e77
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1703
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit 357bb2daf09090192c09ddde501a7e07337614e1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Aug 9 13:44:38 2012 -0700

    SandyBridge/IvyBridge: Use flash map to find MRC cache
    
    Until now, the MRC cache position and size was hard coded in Kconfig.
    However, on ChromeOS devices, it should be determined by reading the
    FMAP.
    
    This patch provides a minimalistic FMAP parser (libflashmap was too
    complex and OS centered) to allow reading the in-ROM flash map and
    look for sections.
    
    This will also be needed on some partner devices where coreboot will
    have to find the VPD in order to set up the device's mac address
    correctly.
    
    The MRC cache implementation demonstrates how to use the FMAP parser.
    
    Change-Id: I34964b72587443a6ca4f27407d778af8728565f8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1701
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit a60ca36c4282c3998d4fc38d55e3dc668017b3ef
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Aug 9 11:09:44 2012 -0700

    Strip quotes from $(objcbfs)
    
    Otherwise object paths will look like build/cbfs/"fallback"/...
    
    Change-Id: I3e60f90f7490e71b0da075d3ea8fc847abc07938
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1700
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit c6b9f926cc28d8b00b66a95cde394bf3657b44bb
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Aug 9 11:00:14 2012 -0700

    Add missing newline in error message
    
    This is purely cosmetic. All error messages in the Sandybridge raminit
    code printed a newline at the end.
    
    Change-Id: I880d291928291d487039850a2a3d53a1101124ba
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1699
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit 4959cea9ce40326ebb6bca08f94861d788aeb629
Author: Vincent Palatin <vpalatin@chromium.org>
Date:   Wed Aug 8 18:28:09 2012 -0700

    rtc: add explicit dependency on build.h
    
    build.h is generated at build time,
    with highly parallel builds, we might try to compile the rtc driver too
    early.
    
    Change-Id: I9a2681484d58b67ed3061669fbdf52ac5ad14dab
    Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
    Reviewed-on: http://review.coreboot.org/1698
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit fa90fd4f2f4aab4da25bb0c89cb408de36443a25
Author: Vincent Palatin <vpalatin@chromium.org>
Date:   Tue Aug 7 17:03:40 2012 -0700

    rtc: erase CMOS memory after power failure
    
    When a power failure happens on the RTC rail, the CMOS memory (including
    the RTC registers) is filled with garbage.
    So, we erase the full first bank (112 bytes) and we reset the RTC date
    to the build date.
    
    To test, disconnect the CMOS battery to produce an RTC power
    failure, then boot the machine and observe the RTC date is the build
    date using "cat /sys/class/rtc/rtc0/date"
    
    Change-Id: I684bb3ad5079f96825555d4ed84dc0f7914e9884
    Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
    Reviewed-on: http://review.coreboot.org/1697
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit becacec022602ae1ab876c58d8ae69092327b9fe
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Wed Oct 31 15:39:51 2012 +0800

    AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU
    
    Each G34 socket has two node. Previous lapic algorithm is written for
    the CPU which has one node per socket. I test the code on h8qgi with
    4 family 15 CPUs(8 cores per CPU). The topology is:
    socket 0 --> Node 0, Node 1
    socket 2 --> Node 2, Node 3
    socket 1 --> Node 4, Node 5
    socket 3 --> Node 6, Node 7
    Each node has 4 cores.
    I change the code according to this topology.
    
    Change-Id: I45f242e0dfc61bd9b18afc952d7a0ad6a0fc3855
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1659
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit cf81b8294b95c13b27aa9f53ca8e958699b4290c
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Aug 8 13:43:55 2012 -0700

    CMOS: Move MRC seed offset into upper bank
    
    This will allow the lower bank to be cleared without impacting the
    ability to suspend/resume.
    
    Change-Id: Iaec3c9e7e40c334053c814eaddd1f614df245a73
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1696
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit fc1b9ee4aa19e698b07aaa050949b791aa119847
Author: Vincent Palatin <vpalatin@chromium.org>
Date:   Tue Aug 7 16:05:14 2012 -0700

    rtc: force mc146818 register D to a correct value
    
    On Panther Point PCH (and maybe cougar point), when some of the register
    D reserved bits are set, the RTC starts misbehaving (e.g. incrementing
    the year byte every second).
    There are probably undocumented features implemented behind those bits.
    Let's reset register D to a known state to ensure we get the expected
    RTC behavior.
    
    Change-Id: I7e2c2a2c6130a974bccb3d760b41eaa579a58b67
    Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
    Reviewed-on: http://review.coreboot.org/1695
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit 6f4297677c130cd181b107ed496874f7b21ee343
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Aug 7 14:49:01 2012 -0700

    Fix CONFIG_ use in i8254.c
    
    We always define CONFIG_ variables, even if they're not set.
    Hence, remove the check whether CONFIG_UDELAY_TIMER2 is defined
    
    Change-Id: Iefdf2389941f2cc63ae4f13ac6b213da4c96b201
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1694
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit 52095f58540bf70c0a469ec17aa67518390f43f2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Aug 7 13:14:20 2012 -0700

    Add POST code for "All devices initialized"
    
    Right now we only had a post code for "All devices enabled" which
    was emitted at the wrong time (after the device initialize stage
    rather than the device enable stage)
    
    Change-Id: Iee82bff020de844c7095703f8d6521953003032c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1693
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit b6e1237978f6aee4516263980f6bcf002d98ef20
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 31 14:52:04 2012 -0700

    Move global variable check to Makefile
    
    Our linker script for romstage checks for global variables and
    makes the build fail if there are any (on non-AMD systems).
    This is great, but having the build fail without any indication
    which variables are global is not very useful.
    
    Moving the check to the Makefile allows us to let the linking stage
    succeed and reveil which variable names end up in the data and bss
    sections of the binary.
    
    To test, add "int foo;" as the first line in src/mainboard/samsung/lumpy/romstage.c
    and build coreboot for Lumpy. See the build break the following
    way:
    
        LINK       cbfs/fallback/romstage_null.debug
        Forbidden global variables in romstage:
        00006a84 B foo
    
    Change-Id: I3c8780888f46a6577ffd36bcea317997b4f84f6f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1692
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit d16d576524d3b9346b72b30c5b50cec4712e4cb0
Author: Sameer Nanda <snanda@chromium.org>
Date:   Wed Jul 25 16:11:40 2012 -0700

    Leave power control registers unlocked
    
    To allow easy experimentation with thermals, leave power control
    registers unlocked.
    
    Change-Id: Ia53065f3f220c2faed58e7d53e60c3f169ae58ec
    Signed-off-by: Sameer Nanda <snanda@chromium.org>
    Reviewed-on: http://review.coreboot.org/1688
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit b578627f5101d57103a66ade89863821254af89e
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Tue Nov 6 13:37:08 2012 -0700

    Fix whitespace issue with help message in Kconfig file
    
    Every line of text after a 'help' label in a Kconfig
    file must have the same whitespace preceding it, otherwise
    it's no longer considered help text.
    
    Change-Id: I97093bee72b295b315d78d4c26d7186bf1017fda
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1687
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 6f05c2eb5963069977fcb4adce26ebbd5f1123bf
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Sun Oct 28 18:16:19 2012 +0800

    AMD rd890 late.c: Don't enable PCIe ports after PCIe init.
    
    PCIE devices are detected and initialized by the AMD PCIe init functions,
    which is in cimx rd890. The parameters are read from devicetree.cb before PCIe init.
    Now, all bridges and devices are trained on the device 0.0 enable.
    After PCIe init, the PCIe ports with devices are on and the PCIe ports
    without devices are off. so resources may be allocated correctly
    during the rest of the PCI scan.
    
    But if the devicetree was being used to enable/disable devices after initialization,
    the problems would arise. Take a look at the serial log:
    
    do_pci_scan_bridge for PCI: 00:02.0
    PCI: pci_scan_bus for bus 01
    PCI: pci_scan_bus returning with max=001
    do_pci_scan_bridge returns max 1
    do_pci_scan_bridge for PCI: 00:03.0
    PCI: pci_scan_bus for bus 02
    PCI: pci_scan_bus returning with max=002
    do_pci_scan_bridge returns max 2
    do_pci_scan_bridge for PCI: 00:04.0
    PCI: pci_scan_bus for bus 03
    PCI: pci_scan_bus returning with max=003
    do_pci_scan_bridge returns max 3
    
    PCI bridge 02.0, 03.0 and 04.0 are not inserted devices, but these bridges
    are still scanned. This is not correct.
    
    Change-Id: I87dac5f062c6926081970ed0c5f26a7e3f447395
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1640
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit fa678bb87f2137d653dfd126da3d47902a048083
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Sun Oct 28 18:06:40 2012 +0800

    AMD agesa family15: PCI domain should scan bus from 0x18.0
    
    There are four mainboards using agesa family15 code:
    Supermicro h8scm and h8qgi, Tyan s8226 and AMD dinar.
    All of these boards' PCI domain starts from 0x18.0. Take h8scm as
    an example, PCI devices from 0.0 to 0x14.5 is under 0x18.0.
    Now, the PCI domain's scan bus function stats from 0.0. This would
    result to the PCI devices be scanned twice. Because when the function
    run to device 18.0, it would scan from 0.0 again.
    This issue would result to 2 problems:
    1) PCI device may be assigned two different PCI address.
       If this happenned on VGA device, coreboot maybe not load
       vga bios correctly.
    2) coreboot initializes rd890's IO APIC twice.
    So this patch scans from 0x18.0 and could resolve the problems above.
    
    Change-Id: I90fbdf695413fd24c7a5e3e9b426dc7ca6e128b1
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1639
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3b590ffeb4a10f4a394e242974488cbe29299a16
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Sep 11 15:21:01 2012 +0200

    acpi: Add support for DMAR tables (Intel IOMMU support)
    
    Adds lowlevel handling of DMAR tables for use by mainboards'
    ACPI code. Not much automagic (yet).
    
    Change-Id: Ia86e950dfcc5b9994202ec0e2f6d9a2912c74ad8
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1654
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a93c3fe7f05f5ab440f377360e5149f7234abb73
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Oct 9 22:28:56 2012 +0300

    Drop redundant CHIP_NAME in mainboard.c
    
    Compose the name from Kconfig strings instead.
    
    As the field is for debug print use only, a minor change in the output
    should do no harm. The strings no longer include word "Mainboard".
    
    Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1635
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d635068ffaf97d5d94f3e2b2ccee409ed44b0b41
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri May 18 12:47:02 2012 +0200

    smsc/lpc47n227: Make early_serial usable
    
    This is the smallest possible change to make early_serial.c
    compile when included from romstage.c.
    
    early_serial could be reworked to be built as separate unit
    (romstage-y), but that should be done for all SuperIOs,
    not some individual outlier.
    
    Change-Id: I90ee66b43c9677b86b1b5d6fcc8febfbe58d80dd
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1686
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 68d7c7aa8ba8a8bc17b3cebf1b7086cf8a4fa94d
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Oct 2 11:46:11 2012 +0200

    cpu/intel/model_1067x: Add proper c-state/p-state/thermal support
    
    Change-Id: I853454e8f5617fb7af5dddd7288bdeeacc7b1b8e
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1663
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bf10bc3e44ae0d85a9db189c7c84e380a1ec8aa7
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 1 15:32:32 2012 +0100

    intel/socket_BGA956: enable speedstep, CAR, MMX, SSE
    
    All of these capabilities exist on all CPUs supported on
    this socket.
    
    Change-Id: I54f34e48e34bb6ab5b9954ab7ece8c2c3a1a8e67
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1664
    Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7d54eb8e23407e472380558d961d2df255600ae1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Oct 10 23:14:28 2012 +0300

    Add name field for device
    
    The constant field "name" in chip_operations is common to multiple
    different devices within a chip and cannot reflect the actual device
    as found on the platform.
    
    The intention is that a driver sets dev->name as part of the device
    enumeration sequence with the detected hardware type and revision.
    The field is for debug print use only.
    
    Change-Id: Ib7bf90ba3c618ad0cb715d80d6a937ceaae0adcf
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1634
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a74af56dc1694fbeb8575825122d1081a30fe959
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Oct 2 11:11:42 2012 +0200

    Overhaul speedstep code
    
    This adds proper support for turbo and super-low-frequency modes.
    Calculation of the p-states has been rewritten and moved into an
    extra file speedstep.c so it can be used for non-acpi stuff like
    EMTTM table generation.
    
    It has been tested with a Core2Duo T9400 (Penryn) and a Core Duo T2300
    (Yonah) processor.
    
    Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1658
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 252d39bb154d560257edcc61e4e2cd89f4614477
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Sep 14 12:52:32 2012 +0200

    Fix some indentation flaws and break very long lines
    
    Change-Id: I3efef6bc8f519382ffdd92eb10b4bcd1a4361ba9
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1657
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 73097097426edd10dd1032393f1eb2bf7d320112
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Fri Nov 2 18:14:30 2012 +0800

    remove enable_cache() of 3 mainboards
    
    Because enable cache is added at the end of disable_cache_as_ram,
    ( http://review.coreboot.org/#/c/1662/2/src/cpu/amd/agesa/cache_as_ram.inc )
    enable_cache() should be removed. The 3 mainboards are: amd parmer,
    amd thatcher and tyan s8226
    
    Change-Id: If870ca07d2e97b9e860a2e2315f551251c7a4ed2
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1669
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit 75a26f875b0ebe549305b14bccb32206128ce163
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Oct 31 08:51:01 2012 -0600

    Persimmon: disable the unconnected Full-Speed USB port
    
    Change-Id: Ia3824059a38412896ed2be0c8714018b2291c9f8
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1660
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit f3b86b3136960c954467a917a0df066b1c35c2aa
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Thu Nov 1 18:51:15 2012 +0800

    AMD agesa: add enable cache at the end of disable_cache_as_ram
    
    add this code according to src/include/cpu/x86/cache.h ,line 92,
    functin enable_cache()
    
    Change-Id: Ida96a98397eeed98dd61ca979e8c5a33bf00f9e5
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1662
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit ad874e3477ba391d8fe02b0cab6334be67e2e303
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Sep 6 17:46:30 2012 +0200

    Correct FSB reading in speedstep ACPI
    
    We parsed the MSR the wrong way, and didn't support some valid values.
    
    Change-Id: Ia42e3de05dd76b6830aaa310ec82031d36def3a0
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1656
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 336db54a00daab2d6b49a51eb87fe71bff934166
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Thu Nov 1 23:03:46 2012 +0100

    crossgcc: build expat and python in silence
    
    Don't let expat and/or python show the compile process on stdout.
    Instead direct this output to crossgcc-build.log.
    
    Fix the logfile path for python.
    
    Change-Id: I431dabf6955d7eef3e54c96d0fb11b92d1cee96d
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/1667
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1e0ddf6f1fc5a99325155626c02351c388b91101
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Nov 2 17:26:33 2012 +0100

    Fix some issues with new "reference" toolchain
    
    Unfortunately the reference tool chain was updated
    without ever even testing it on an abuild run. This
    broke a number of ports.
    
    This change gets coreboot at least compiling again
    for all supported systems.
    
    Change-Id: I92c7cbc834de6d792fdab86b75df339e2874c52e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1670
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 335ad93965f9c796e105ebd0e004d7185354ffb2
Author: David Hendricks <dhendrix@chromium.org>
Date:   Thu Nov 1 10:46:29 2012 -0700

    add .gitreview
    
    This adds a .gitreview file for use with the git-review tool. More
    information is available at the URL below:
    https://labsconsole.wikimedia.org/wiki/Git-review
    
    Change-Id: I723d78bf7dd81c5756e684d5b166210246fe2daf
    Signed-off-by: David Hendricks <dhendrix@chromium.org>
    Reviewed-on: http://review.coreboot.org/1665
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 41392df0d1e22aeaa694d5e8b6f58db198da423c
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Oct 1 15:53:14 2012 +0200

    Merge cpu/intel/acpi.h into cpu/intel/speedstep.h
    
    We had only some MSR definitions in there, which are used in speedstep
    related code. I think speedstep.h is the better and less confusing place
    for these.
    
    Change-Id: I1eddea72c1e2d3b2f651468b08b3c6f88b713149
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1655
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bef3d347e8a21049d72407246a5d4ec1339b5601
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Sat Oct 13 13:15:04 2012 +0200

    Add support for socket LGA775
    
    Change-Id: Ia7ef3a4cbc3638a9c9a48b297e392e4e655b6e6b
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1581
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 335450d0a1f7befe4ca649d7e23dcf8ed15bf314
Author: Kostr <aladyshev@nicevt.ru>
Date:   Mon Oct 8 22:04:53 2012 +0400

    Fix ExecuteFinalHltInstruction function in f15h family code
    
    Current ExecuteFinalHltInstruction function doesn't work well.
    (at least in configuration
    Supermicro board with Orochi AMD Opteron processors (model OS6234WKTCGGU))
    
    System reboots when trying to halt core 2,4,6,8 or 10
    (OS6234WKTCGGU is 12 core processor)
    Based on this information, i think that code doesn't really work with
    f15 compute unit (CU) system.
    
    Replacing ExecuteFinalHltInstruction function with
    analogous function from f15tn family code fix this problem.
    Both functions written from the same cahalt.asm file, but f15tn version
    seems more completed
    
    Change-Id: I3942abcdf21f1b86a44c01cc477714e44a40b9cf
    Signed-off-by: Kostr <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/1569
    Tested-by: build bot (Jenkins)
    Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 80adfdf8a9dde4b81fc0d0ffacf04835c4eaa883
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Wed Oct 24 11:20:44 2012 +0800

    AMD SB800: PCIE slots on Persimmon
    
    Enable the PCIE bridge which is connected to the PCIE slot.
    
    Change-Id: I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1098
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 9ead80f8700b37779ca6536b423fa5ee9544efd2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Aug 28 07:49:49 2012 +0300

    Drop get_smbios_data from chip_operations
    
    We only want to add data once per device. Using the one in
    chip_operations is not very usable anyway, as different
    devices under the same chip directory would need to output
    entirely different sets of data.
    
    Change-Id: I96690c4c699667343ebef44a7f3de1f974cf6d6d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1492
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Tested-by: build bot (Jenkins)

commit 23c046b6f16805ff0131460189967bf261d704de
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Sep 24 10:48:43 2012 +0200

    Fix reading of number of interrupts for IO-APICs
    
    The number read from the io-apic register represents the index of the
    highest interrupt redirection entry, i.e. the number of interrupts
    minus one.
    
    Change-Id: I54c992e4ff400de24bb9fef5d82251078f92c588
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1624
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f4ff56f6173df256589dfdaee4cd1e7cafd0202c
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Oct 27 14:20:10 2012 +0200

    Hide all _ROM_RUN Kconfig options if the payload is SeaBIOS
    
    The options are shown regardless of payload if CONFIG_EXPERT is set.
    
    Change-Id: I12c81ce41a0e300e852481424eadc83f281863bf
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/1638
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit be0ede412edb631892312d3972c8439fa7053203
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Oct 27 14:17:04 2012 +0200

    Run option ROMs in coreboot by default only if the payload is not SeaBIOS
    
    Change-Id: I29fb86ff3a3187b720ce5ef246c4eeee696ab5cd
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/1637
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b6fa47c639c38bf87cd9df4ec158ba3eeb9d5d70
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Oct 27 13:45:51 2012 +0200

    Clarify that _ROM_RUN Kconfig options control if ROMs are run by coreboot
    
    Also clarify that enabling these options is generally not desirable if
    using SeaBIOS as payload since the option ROMs are run by SeaBIOS with
    more complete BIOS interrupt services available than coreboot.
    
    Change-Id: Ic4a45c351a4933aedad08d70a088eab04ca35b05
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/1636
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 892d8d2c58f6758d8ffa7166aaa96b0a319ae2db
Author: Ricardo Martins <rasmartins@gmail.com>
Date:   Mon Aug 6 05:40:07 2012 +0100

    IEI PM-LX2-800-R10: Added preliminary mainboard support
    
    Details for this board are available at
    http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050662496936266123&id=09034367569861123956
    
    Support for the IT8888 PCI to ISA bridge will be added in a later
    patch.
    
    Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae
    Signed-off-by: Ricardo Martins <rasmartins@gmail.com>
    Reviewed-on: http://review.coreboot.org/1152
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit aa5eae629f40f4337f68b516f67c5c783ab65495
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon Sep 24 10:58:41 2012 +0200

    inteltool: Add output of 64bit registers in PMBASE
    
    Output values of 64bit registers and fix settings for GPE0_EN for
    ICH9/10.
    
    Change-Id: I8ca6b32500331707670972b38466345f581844cd
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1625
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 1f6bd94fa8e683f83887f6847295d45a4d4f3731
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Aug 30 15:36:57 2012 +0200

    libpayload: New AHCI, ATA and ATAPI drivers
    
    This adds a new interface for storage devices. A driver for ATA and
    ATAPI drives on AHCI host controllers comes along.
    
    The interface is very simple and was designed to match FILO's needs.
    It consists of three functions:
    
      void storage_initialize(void);
      Initializes controllers. Should be called once at startup.
    
      storage_poll_t storage_probe(size_t dev_num);
         with typedef enum {
                POLL_NO_DEVICE      = -2,
                POLL_ERROR          = -1,
                POLL_NO_MEDIUM      =  0,
                POLL_MEDIUM_PRESENT =  1,
              } storage_poll_t;
      Looks for a drive with number dev_num (drives are counted from
      zero) and polls for a medium in the drive if appropriate.
    
      int storage_read_blocks512(size_t dev_num,
                                 u64 start, size_t count,
                                 unsigned char *buf);
      Reads count blocks of 512 bytes from block start of drive dev_num
      into buf.
    
    Change-Id: I1c85796b7f8e379ff3817a61b1837636b57e182b
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1622
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 7baadac40364cdbf20c2add19f2aac678d3b603a
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Oct 7 14:57:15 2012 +0200

    Take care of NULL chip_ops->name
    
    Change-Id: Ic44915cdb07e0d87962eff0744acefce2a4845a2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1626
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 0524e4b53e91596340f6c9ecfb893b19d6118a64
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Fri Oct 26 23:35:34 2012 +0200

    Reorder entries in .gitignore
    
    Change-Id: I7fcf190ef92b06b857d8b85c3d27da9cdee071b1
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1633
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 468e17b3929bf025767b9aa3d7933674bc68a67b
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Fri Oct 26 23:32:31 2012 +0200

    Add docs and util files to .gitignore
    
    This adds...
    - generated documentation files
    - all kinds of stuff in the util subdirectories
    
    Change-Id: I47ab6d239aae725f54413f03424f40002ac5a275
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1572
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 573d37da02b6899dba1ab70c643e76219fd83df2
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Fri Oct 26 01:56:56 2012 +0200

    crossgcc: update to Python 2.7.3
    
    Change-Id: I9db10e8c7dcd693cc4ab935c587da02dd7eb2bc5
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/1621
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 296a015b8a99e611f68ee9836c8fb9dd054e325d
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Fri Oct 26 01:48:04 2012 +0200

    crossgcc: update to expat 2.1.0
    
    Change-Id: Id0b736d402b33138e27b18c74e5ed8ffab0bcccb
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/1620
    Tested-by: build bot (Jenkins)

commit 95c607feadf6325c90842fec8fa64a2b32208295
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date:   Fri Oct 26 19:02:44 2012 +0200

    iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned
    
    The PCI registers should be accessed aligned and 0x62 is not 32bit
    aligned therefore this patch changes it to a 16bit access.
    
    Change-Id: I00725a4569f471eedb061834f626911b42e734fb
    Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
    Reviewed-on: http://review.coreboot.org/1631
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 3e9155dddf4a439703f7b762648eb820307dbfe4
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date:   Fri Oct 26 19:03:14 2012 +0200

    northbridge/sch: move the \n so it reads a little better
    
    Without this, the output of "Setting up ACPI…" continues right
    after the output of stepping.
    
    Change-Id: I2ad7cc3e55884ff509600b01274258b8e8250981
    Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
    Reviewed-on: http://review.coreboot.org/1632
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 6997b4bcefe85155afc5f3be054b0c9a293fe256
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date:   Fri Oct 26 19:02:10 2012 +0200

    iwave/iWRainbowG6: remove USE_DCACHE_RAM
    
    This is not available as a config option anymore.
    
    Change-Id: Icac173d62928423a08671321ec21d4af82c5cded
    Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
    Reviewed-on: http://review.coreboot.org/1630
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 59e3e0299112070e51c4dabc8f616344e291956f
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date:   Fri Oct 26 19:01:45 2012 +0200

    northbridge/sch: read the size of main memory from the proper register
    
    I don't know if the size main memory supposed to be in PCI(0,0) reg 0x9c
    but it is not written there. The size of memory is written in
    src/northbridge/intel/sch/raminit.c to SCH port(2, 8, 4) (look for
    "Setting up TOM").
    
    Change-Id: Iea04a5185bda56f61d1c382533d5a0dac429ebbd
    Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
    Reviewed-on: http://review.coreboot.org/1629
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 50dd47bb58bee2ed159c1c5f6eb51dd583094f26
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date:   Fri Oct 26 19:01:17 2012 +0200

    northbridge/sch: Read the GPU memory from the correct PCI device
    
    The GGC register which contains the size of memory that is used for GPU
    is in PCI device 2,0 and not 0,0. It is set to to 4MiB in
    src/mainboard/iwave/iWRainbowG6/romstage.c.
    
    Change-Id: Ie9f1cc60544ecd9cad770f34c83c33564a6129d4
    Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
    Reviewed-on: http://review.coreboot.org/1628
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 66fa9e2865dc68fd3d89714138c8e0d27ff16819
Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Date:   Fri Oct 26 19:00:22 2012 +0200

    northbridge/sch: don't overwrite hightables with GPU / TSEG memory
    
    Without this, the hightables are placed just before the end of memory.
    However we might have the GPU memory located at the exact same spot,
    that is in the last 4 MiB. So without this patch, this area won't remain
    marked as "CONFIGURATION TABLES" within coreboot's memory table but
    becomes "RESERVED" because it is part of the PCI(2,0) device.
    
    Change-Id: Ibd111c167c2f6ac03b0ba68581a74ecbd2c9c160
    Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
    Reviewed-on: http://review.coreboot.org/1627
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit cd02793dffe147030e78a9f609611f7615dda3a6
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Fri Oct 26 01:22:41 2012 +0200

    crossgcc: update mingw w32api's download URL
    
    Correct the download URL of mingw's w32api.
    
    Change-Id: I98fb43c121399c23f6693ade5cd3b42bc9463724
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/1619
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 04ceed6a0f0a0856be6975af266850bab03cc3c6
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Tue Oct 23 19:41:25 2012 +0800

    buildgcc: redirect error output to /dev/null
    
    Change-Id: I7cd63248eb8abb711cecce41e3f8a282b34aa126
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1548
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 908b043da03024bd362adb46bd0ca7b4c1a23a86
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Thu Oct 25 03:00:59 2012 +0200

    crossgcc: update to mingwrt 3.20-2
    
    This patch updates crossgcc to download and compile mingwrt 3.20-2
    
    Change-Id: Ic5ed2df4c3643e469a62c51643d3fc756eb3e615
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/1617
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 655a65c13924efecb4b9e0773581f103604332ff
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Thu Oct 25 02:15:01 2012 +0200

    crossgcc: update to binutils 2.23
    
    This patch updates crossgcc to download and compile binutils 2.23
    
    Change-Id: I75a24ce6fb9f6ac7ae53671314c410b9b0d80aa8
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/1615
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 7962fc7684131666227ee4846f07b1fe4a5b8b22
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Thu Oct 25 02:14:09 2012 +0200

    crossgcc: update to MPC 1.0.1
    
    This patch updates crossgcc to download and compile MPC 1.0.1
    
    Change-Id: I7a2a21afc8c26e4fb7b6553c7fd98cc054d01570
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/1614
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 27efb4cd3fcae3baeb6f8906ab092f82562e44e1
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Thu Oct 25 02:12:46 2012 +0200

    crossgcc: update to MPFR 3.1.1
    
    This patch updates crossgcc to download and compile MPFR 3.1.1
    
    Change-Id: I6c479db5d6d632dcc2201c3771b43e2b663877e1
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/1613
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit fedb63a988fcbdc6315246cbf7bda33e3f01eb2b
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Thu Oct 25 02:06:57 2012 +0200

    crossgcc: update to GDB 7.5
    
    This patch updates crossgcc to download and build GDB 7.5
    
    Change-Id: I38fc3591396f072ead399b22f516ec765480ea40
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/1612
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 1cfee0bc104946c09b206ded9a958495e4fd4168
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Thu Oct 25 02:03:53 2012 +0200

    crossgcc: update to gcc 4.7.2
    
    Update crossgcc to use gcc 4.7.2.
    This requires a minor change to util/crossgcc/buildgcc as well.
    
    Tested on hardware with asus/p2b and lenovo/x60.
    
    Change-Id: Ia3921844670ca99741e5715def14dd969f305ab7
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/1609
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit cbd631284d2e5f1d5cbff14812baca7f357d1edf
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Tue Oct 23 19:49:36 2012 +0200

    crossgcc: fix compilation of acpica
    
    Compilation of acpica-20120420 is broken (and old, but I'll take care
    of that in a future patch),
    let's fix that ("Building IASL 20120420 ... failed").
    
    Change-Id: If5fd5cd93d748f78b7c059323f9f810666e32cc7
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/1607
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 1d1a68b754e57d2dd5454c426831927dc1c3ead4
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Wed Oct 24 11:13:47 2012 +0800

    Trinity: Initialize the pointer prior to using it
    
    Change-Id: I2f10909a626fb64c7f95663ddd79a3b899f73bc4
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1606
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit def50b061d58e6f8d322dcbee931ac28005716da
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Tue Oct 23 11:48:36 2012 +0800

    kconfig: Some terms or curses libraries treat backspace as 0x08
    
    Change-Id: Ie4e4a2f0d68643a8f46d24ee7bd1b953e9fe14a5
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1605
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 545167252d564ed13a669f62a29a5a2640c55a43
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Oct 22 16:41:42 2012 +0800

    build: build coreboot on mingw.
    
    regex, pdcurses, wsock(for itohl) are seperated libraries. mmap and unmmap are
    ported from git.
    
    Issues:
    1. The length of command line is limited. That makes the Thather can not be built
      because too many obj.o need to be built.
    
    Change-Id: I1d60ec5c7720c1e712e246c4cd12e4b718fed05f
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1604
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c31cdd8662e770fb17a9c78e2fc508967c4795f2
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Oct 22 16:39:24 2012 +0800

    cbfstool: Add -mno-ms-bitfields on (mingw)
    
    The default gcc on mingw will process the __attribute__ ((packed)) in
    a different way other than non-win system.
    
    Change-Id: Iac9f4476c922472d0b447f1c3ef60e8e13bd902f
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1603
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0fd93d62d232d22e4bbeeb272fb909f615076d2c
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Oct 22 16:36:03 2012 +0800

    Makefile: No need to mkdir when distclean
    
    make distclean causes error on mingw:
    -------
    rm: cannot lstat `build/util': Permission denied
    make: *** [distclean] Error 1
    -------
    Guess, When the distclean is made by multi-process, the mkdir
    in the Makefile will execute when build is removed. That causes
    conflicts.
    
    Change-Id: Ia41ecc5d1db2fa9d3328c81ac1d33fa94779492d
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1602
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 50ad0950ae5c931e7e36460db009dd1692b3c4b8
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Oct 22 16:29:37 2012 +0800

    gitconfig: Create .git/hooks before copying files.
    
    Change-Id: Id5564bf7a12b3ea9a5e60bd9522466157ace8c65
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1601
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit eb825725ce9e9765b5370008d65829f2aa1aa550
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Fri Oct 19 21:02:39 2012 +0800

    change conflicted typedef in src/vendorcode/amd/agesa/f15/Porting.h
    
    src/vendorcode/amd/agesa/f15/Porting.h has some conflicted typedef with
    src/include/cpu/amd/common/cbtypes.h. These conflicted defines can lead to errors.
    
    Change-Id: Idad0794018bf0bd0e4e52a5aa062a12766d56c8e
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1592
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fba86bfaa8a308ed6ca3daa66e27f1c10dd4c016
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Fri Oct 12 10:36:49 2012 +0200

    inteltool: improve the libpci test in the Makefile
    
    Use the verbatim variable method to define and export test code and
    the actual libpci test from flashrom. This improves readability and
    will work with stricter compiler (settings).
    
    Change-Id: Iace7d53b0b992c4fde596ce1d606ad715d6dfc2a
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1575
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1a00cf063273d2f19afbc848dd1a204b7687578e
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Sat Oct 13 06:23:52 2012 +0200

    inteltool: add support for 946GZ and 946PL
    
    Change-Id: Ied0ff16c16d8c2f04b55fe6b0a6ee38966d3c424
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1576
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 04c06005eb891e98fc733e85f625e13a16a86860
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Sat Oct 13 02:19:30 2012 +0200

    inteltool: new definitions and cleanup
    
     - Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[].
     - Refine some names and macros.
     - Clean up some whitespace errors.
    
     - Add IDs and names of 5, 6 and 7 Series southbridges and the three
       latest Core CPU families with integrated memory controllers but do
       not implement any pretty printing routines for them yet.
    
       The first generation Core family is already supported, although it
       was wrongly named after the PCH and used the wrong ID. Also, the BAR
       values have been mangled to 32b instead of 64b. Both errors have been
       fixed and most basic support for the other two generations was added.
    
    Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1574
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 9b48ef27331f2adc23a15f135ee99f6e619f55af
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Oct 16 02:25:07 2012 +0200

    Update SeaBIOS stable to the release-1.7.1 commit
    
    Change-Id: I0dffe89c31e45914f795d9ad8efb787b5fdbb7a8
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/1583
    Tested-by: build bot (Jenkins)

commit f450b8619ebcd8dee94d175b2710f07e9884696d
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Sat Oct 13 02:33:35 2012 +0200

    inteltool: remove bashism from Makefile
    
    &> is a bashism to redirect both outward streams (stdout and stderr), but
    with other shells this introduces a race condition with the rm command
    after it, because the compiler execution is done in the background/
    in parallel. Found and tested with dash.
    
    Change-Id: I08516494828c9f7af168f954f2df027372657867
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1573
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bernhard Urban <lewurm@gmail.com>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 36156ffa1e86c10456c3ce915705c5a71b8cd708
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Sep 28 16:18:58 2012 +0800

    crossgcc: Allow the non-gnu tar and patch work on XxxBSD
    
    For BSD, patch and tar are not default GNU. Add a work around
    to let the non-gun patch and tar work.
    
    Change-Id: I0a9d0bb0e535aa5e0dde146db330c3c8d7b4d8cb
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1502
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d357e6283631ce8e3279ef825f677482f1056e50
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Sep 24 20:47:03 2012 +0200

    libpayload: CMOS access was implemented in a backward way
    
    Instead of having the highlevel functions make use of the lowlevel
    functions, it implemented the lowlevel stuff in terms of highlevel.
    
    Change-Id: I530bfe3cbc6f57a6294d86fbf1739e06467a2318
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1539
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c31e3ac2583bb39bb48f255f7fb4dd9df44cd365
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Oct 7 15:05:42 2012 +0200

    abuild: allow building with no payload
    
    Change-Id: I167f0bb57bb40f0426182c0abe868bdad58eb120
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1563
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1b97bdc42a91746906b99a37ad15ba0a0039e4a3
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Wed Oct 10 09:07:28 2012 +0200

    bachmann/ot200: Fix wrong IRQ number for PIRQD
    
    The used FPGA on the device triggers PIRQD for the membrane
    keyboard. The used linux driver for the keyboard uses the fixed
    IRQ number of 7. In order not to touch the linux driver and be
    compatible with proprietary BIOS change the irq_table in
    coreboot.
    
    Change-Id: If5bc929eb48bb1eafd401941ebb7d34cf5862c35
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/1571
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 2feddbded844c71f0ff5cdfb02a9ccad2d0a4423
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Tue Oct 9 15:13:25 2012 -0600

    iei/kino-780am2: Turn on PCIe bridge to 2nd ethernet controller.
    
    Change-Id: I35fa94bafcf7c835081b57acf031a2fb334d353d
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1570
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 9aeb69447d3839675b2cac51c3e95a4724fd9b0d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Oct 5 21:54:38 2012 +0200

    hpet: common ACPI generation
    
    HPET's min ticks (minimum time between events to avoid
    losing interrupts) is chipset specific, so move it to
    Kconfig.
    
    Via also has a special base address, so move it as well.
    
    Apart from these (and the base address was already #defined),
    the table is very uniform.
    
    Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1562
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

commit ec2c18ee6068ef6adf6f5be437d7047c91773654
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Mon Oct 8 03:00:08 2012 +0200

    Increment revision of SeaBIOS to remove bashism
    
    This enables building with dash again(?) by using exactly one patch of
    SeaBIOS more/newer than previously, which has also the sole purpose of
    removing bashism and is a single line change. *sigh*
    
    Change-Id: Ib036894d8b9886f74d6eb0853f1fc0ce1aa39d54
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1568
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit aada2e127b43a81483064281cadc4d5fafcc3272
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Oct 7 15:08:32 2012 +0200

    Every chip must have chip_operations
    
    Forcing this rule, chip_ops can be added in the static devicetree
    regardless of the existence of the chip.h files.
    
    Change-Id: Iec1c23484e85cab3f80a34f2b082088f38ac4de9
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1472
    Tested-by: build bot (Jenkins)

commit 9c9eb8cbc9deadf2b342236f71d1c9da59a97644
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Oct 7 14:57:15 2012 +0200

    Take care of NULL chip_ops->name
    
    Change-Id: I62b1c497d23ec2241efb963e7834728085824016
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1565
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit e5fe3acb5a1d5f14b9e84cf03f4e67e34e267ba7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Oct 7 14:56:22 2012 +0200

    Fix typo in mPGA603 socket
    
    Change-Id: I7a49d5fc13fb605a47c3c1662758ebd5935e7780
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1564
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 02790369ff72d9d2ed5b65eee28f9cde56f3d541
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Aug 24 21:54:10 2012 +0300

    Remove chip.h files without config structure
    
    Also deletes files not included in build:
        src/southbridge/amd/cimx/sb700/chip_name.c
        src/southbridge/amd/cimx/sb800/chip_name.c
        src/southbridge/amd/cimx/sb900/chip_name.c
    
    Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1473
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 1f0d379a7e87b12b2b6a4af7833f633b08ef7184
Author: Kostr <aladyshev@nicevt.ru>
Date:   Sat Oct 6 13:27:58 2012 +0400

    Revert order in VGA device choice
    
    Before change "Simplify VGA card discovery"
    (http://review.coreboot.org/#/c/1255/)
    coreboot was setting up VGA for the last found VGA device.
    After this change it setting up VGA for the first found.
    This change broke compatibility to my Supermicro H8QGI board.
    Revert order back to old to save compatibility for this board
    (and maybe any other boards)
    
    Change-Id: Id5f2be60f95298059651c26133806e2694ff60aa
    Signed-off-by: Kostr <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/1561
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ee00e7bd7378bf229c33389d52793ee8c40017ee
Author: Kostr <aladyshev@nicevt.ru>
Date:   Wed Sep 26 22:11:20 2012 +0400

    Mainboard: Fix IO-HUB link number in Dinar mainboard
    
    According to file "northbridge.c" in family 15h code
    IO-HUB should be placed on link_lsit[0] in devicetree.cb.
    This hack in "northbridge.c" was made to satisfy both f10 and f15 cpu's.
    
    Change-Id: I4754235bd38239460347b0dc4a82cd4e58ae7cd0
    Signed-off-by: Kostr <aladyshev@nicevt.ru>
    Reviewed-on: http://review.coreboot.org/1540
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 9b757dccdca1ca4a14fdc8351600652d798dc715
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Sep 28 20:14:38 2012 +0800

    lint: Get absolute path in compare_output
    
    The classes in $(top)/Makefile uses $(abspath) to get the path.
    The $(abspath) can not resolve symlink. If the coreboot is located
    in a symlink directory, the run_printall produces the absolute
    path while the $PWD just produces the path with symlink. Use
    `pwd -P` to get the abs path.
    
    Change-Id: Icf6b364d030c14a9c78991767b17dafc701baf3c
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1551
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4bb7a8d68fd55a59ae908bb662a7a488a9ad35c9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Aug 17 15:57:36 2012 +0200

    Provide access to smaller registers in eregs
    
    This is in preparation for sharing interrupt handlers
    between YABEL and x86emu.
    
    Change-Id: Iff92c1d899b8ada20972731944341805a49b6326
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1560
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 89bbcf4c9b8849687f86a8a31c3bdd02818953f9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Sep 23 18:41:03 2012 +0200

    Use mainboard_interrupt_handlers everywhere
    
    The previous commit provides a mainboard_interrupt_handlers
    implementation YABEL with identical semantics to the
    x86emu one, so let's use it in both cases.
    
    This eliminates the need for the int15_install()
    indirection, so let's drop that, too.
    
    Generated using the following coccinelle patch and
    manual cleanups (empty #if/#endif):
      @@
      type T;
      identifier FUNCARR;
      expression INT, HANDLER;
      @@
      -typedef T yabel_handleIntFunc;
      -extern yabel_handleIntFunc FUNCARR[256];
      -FUNCARR[INT] = HANDLER;
      +mainboard_interrupt_handlers(INT, &HANDLER);
    
      @@
      @@
      -void int15_install(void)
      -{
      -mainboard_interrupt_handlers(0x15, &int15_handler);
      -}
    
      @@
      @@
      -void int15_install(void)
      -{
      -mainboard_interrupt_handlers(0x15, &int15_handler); ... mainboard_interrupt_handlers(0x15, &int15_handler);
      -}
    
      @@
      @@
      -int15_install();
      +mainboard_interrupt_handlers(0x15, &int15_handler);
    
    Change-Id: I70fd780d7ebf1564a2ff7d7148411673f6de113c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1559
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f3a163a1274de16771ed84d51119457ba3a2881d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Aug 16 15:39:35 2012 +0200

    YABEL: Common API to register interrupt handlers
    
    Provide (mostly) the same API for registering
    interrupt handlers as with x86emu.
    
    Change-Id: I1364b08d9043039550786a1758508ae088813aa3
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1558
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1ee8b45740a2c888742cb5917ca71cd0ed86cec2
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Fri Sep 7 19:20:02 2012 +0800

    add tyan s8226: add a new mainboard
    
    our code supports tyan s8226 now, which has two cpus on the board
    the cpu socket is C32. The details of tyan s8226 is:
    http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=679&SKU=600000190
    the test result of this mainboard is:
    1) boot Ubunbu 11.10, kernel 3.0.9. there is no err and warnings in
    dmesg.
    2) boot windows7 x64 successfully.
    3) use fwts to test the bios, there are 268 pass and 14 failed
    4) pcie and usb slots are ok.
    5) all network interfaces are ok.
    
    Change-Id: I7d8534f20b4f3c16322a5c5ba2e3fba4b4f3e608
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1495
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 684b8ab309d26d90aa161c43f55e331b9788fdb2
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Sep 28 20:13:19 2012 +0800

    lint: Stop searching when one GNUmake is found
    
    After make 3.81 is copied to /usr/local/bin, the old make 3.80, which
    doesn't work for coreboot, will replace $MAKE with gnumake. That is not
    we want.
    
    Change-Id: I87fbe95c70228a22f2c233ff071df29639b63726
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1550
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 70c660fd1473b8c6ca7b71276b9552ee2205c99a
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Aug 23 02:32:58 2012 -0500

    pirq_routing: Allow routing with more than 4 PIRQ links
    
    pirq_routing_irqs assumed that only four links are available for PIRQ
    routing, INTA to INTD. Some chipsets provide more, up to INTH.
    When pirq_routing_irqs found a link number greater than 4 in the pirq table,
    it would not assign that IRQ. This is a shame, as it limits the flexibility
    of routing IRQs.
    Make the maximum number of links a Kconfig variable, and modify the code to
    respect it. This works beatifully on the VX900, which provides 8 routable
    interrupts.
    While we're at it, also refactor pirq_routing_irqs, and add some much
    needed comments.
    Rename pirq_routing_irqs to pirq_route_irqs to demistify the role of this
    function.
    The copyrights added were determined from git log filename.
    
    Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/1482
    Tested-by: build bot (Jenkins)

commit 93a8b27cbed8a288ee6a65436ec22ad5a67fdbd0
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Wed Sep 26 22:31:04 2012 +0400

    libpayload: Set 8bits per char for serial port
    
    Previously we assume that hardware using 8 bits
    per char by default, but on Asrock A53 Pro
    this is not true (7 bit per char by default).
    Forcing use 8n1 now.
    
    Change-Id: Ib701725d2ec6dacd7862016b2045270956b27029
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1541
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 89397fc342c7bf9005e68e28ab898c81b7fc2a66
Author: Andriy Gapon <avg@FreeBSD.org>
Date:   Wed Oct 3 08:19:34 2012 +0200

    superiotool: Fix for FreeBSD
    
    Makefile still used SVNDEF on FreeBSD.
    
    Change-Id: I45c7fbc66c33e82a2146ef7df87b63bc7edea4cd
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1554
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit d2cb7ea1ff2bef2e4b54d12a295abf2fd76ebd9a
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Oct 3 08:23:56 2012 +0200

    libpayload: UHCI driver contained too much magic
    
    The handling of finalize in uhci_bulk was confusing, and so its
    behaviour changed.
    If set, the driver is supposed to add a trailing empty packet iff
    the last packet is of maximum packet size. This helps the device to
    decide if the transfer is completed simply by waiting for a packet
    that isn't full length.
    
    Change-Id: I162e8c1e034924d0de6fdcb971c94cf3a5ea31eb
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1555
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 16c7ad79219ae48cae0cae6498c6df6cc1dc8e2b
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Sep 21 18:11:59 2012 +0200

    buildsystem: ensure directory exists before use
    
    In some cases we request mktemp to create a temporary file in
    $(obj)/mainboard/... before it exists.
    Let's make sure the directory exists
    
    Change-Id: I51f0065c30b1f25eb501a6fd5edefb3f4c15d0ab
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1532
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 14b248b4a2562ed6434a41a8546e83aee3471083
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sat Sep 22 14:52:24 2012 +0200

    Fix compilation without CONFIG_WRITE_HIGH_TABLES.
    
    Without that fix we have:
          CC         boot/hardwaremain.ramstage.o
      src/boot/hardwaremain.c: In function 'hardwaremain':
      src/boot/hardwaremain.c:136:6: error: 'cbmem_post_handling' undeclared (first use in this function)
      src/boot/hardwaremain.c:136:6: note: each undeclared identifier is reported only once for each function it appears in
      src/boot/hardwaremain.c:137:3: error: implicit declaration of function 'cbmem_post_handling' [-Werror=implicit-function-declaration]
      cc1: all warnings being treated as errors
      make: *** [build/boot/hardwaremain.ramstage.o] Error 1
    When compiling without CONFIG_WRITE_HIGH_TABLES
    
    Change-Id: Ie45f684a6db0ab55ef469bfcef57e539ae7e994c
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/1533
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit efcb8de12e5c0757a5b3784a43a54046aaff460f
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Tue Oct 2 00:04:29 2012 +0400

    libpayload: fix for UHCI bulk transactions
    
    Fixed masking to run QH shedule.
    Fixed final zero filled TD generation for
    UHCI bulk transaction.
    
    Change-Id: I9c6ea34d132368922f2eeeaa7aadbbb6aac3e2b8
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1553
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 86aa7c45a544c1b599ad78d8a7a84884521dd48f
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Sep 28 16:06:44 2012 +0800

    build.h: Re-run hostname if it doesn't take '-s' option.
    
    Cygwin's hostname comes from coreutils, which does not support all
    the options that some other hostname implementations provide.
    
    Change-Id: Ia6bd9157c351f440ad225046638a6bf3f9cfba11
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1546
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b13e94c2c654bdf71ade141475f1e9f343979be2
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Sep 28 16:02:35 2012 +0800

    nvramtool: uname in NetBSD doesnt take "-o"
    
    see the Netbsd manual:
    http://netbsd.gw.com/cgi-bin/man-cgi?uname++NetBSD-current
    Error output needs to be redirected.
    
    Change-Id: I1853a0162e14be0ee9d7971466499af6c72b2427
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1545
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f78c7007c25bfc7d7fe9aeb42c70751bb7e74900
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Wed Sep 26 15:11:48 2012 +0200

    libpayload: fix fetching integers from CMOS as string
    
    %ull -> %llu
    
    Change-Id: I330f681d713be7eb444870f81330cf6e9869a4fa
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1542
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 82c06bd2d5093f9d26c9da4fa1d65828972c4c9b
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Sep 28 15:58:05 2012 +0800

    nvramtool: Require no hw access for integrated Makefile
    
    The Makefile.inc is integraged into coreboot Makefile. It doesn't
    need to access to HW like cmos. It doesn't include cmos-hw-unix.c,
    which is only for individual tools running seperatedly.
    
    Change-Id: Ib00b5c3da63acb4120cb23eb7d661c5bc75d7c86
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1544
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8d7369261ed012482e8b4f13849c566763944fee
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Sep 28 16:10:01 2012 +0800

    AMD Hudson: Printf the high address as unsigned integer
    
    Some 32 bit machines print integer higher than 0x80000000
    as negative number.
    
    Change-Id: Ieb512ed2a7499ce7e91e45e4075d4f119780b57d
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1547
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 533bca80ed6d2b1f1947f10926b5a7415b1c3359
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Fri Sep 28 19:38:37 2012 +0800

    lint: Add template for mktemp to meet BSD requirements
    
    Change-Id: I86cecf6aee1fcb682cb32bd0f03e014fd1afe594
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1549
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 82867d3ed0f42267038b3a34009c6dd5b5be696c
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Wed Sep 26 15:26:05 2012 +0200

    libpayload: Don't leave temporary files behind
    
    For some reason the rm -f didn't quite work on my system,
    but sending gcc output to /dev/null does.
    
    Change-Id: I7ece9aa9abe564bbc646ae53df1d3cd0c5aa84a2
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1543
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 08ed5a86978ba3934a0c25b2e6e8077112e8f1b2
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Sep 24 20:06:27 2012 +0200

    libpayload: Extend CMOS access library
    
    libpayload already contained a number of functions for convenient
    access to CMOS configuration. Add functions to support iteration
    over available enum fields.
    
    Change-Id: If95f45d7223d2e19c42f1d8680c12d23f6890a01
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1538
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 72cee54fd60a14506b3d8062991b19e601ade647
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Sep 24 20:56:13 2012 +0200

    HAVE_HIGH_TABLES is gone
    
    ... but no-one told intel/sch.
    
    Change-Id: I68eaae6910bd6fc579c35b5bc038b9597cd1b3e7
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1537
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 80d2526c727e09c15d234b9a999555dea038709c
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Sep 24 20:52:42 2012 +0200

    abuild: abort if payload.sh failed
    
    With this chance it becomes practical to have payload.sh build/update
    the payload, and abort abuild if something bad happened.
    
    Change-Id: Iee25de2e8b62153c477b8e5d32e097b59797523c
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1536
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5c63761c378b14edf290c3f72e70a1d1d2709aae
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Sep 20 13:26:42 2012 +0200

    nvramtool: Read/write binary data as binary
    
    Only relevant on windows (and nvramtool currently fails there), but
    it doesn't hurt.
    
    Change-Id: I5d6420c1f9dc49cf3af31e75088e51a90f729e01
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1535
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cf329ffac87e6006d1c970b8b5800355048526a4
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Sep 24 14:05:22 2012 +0800

    AMD hudson: Round the float pointing number to integer
    
    Try
    sh> printf %d 0x005500AA | LC_ALL=C awk '{printf("%c%c%c%c", \
        $1 % 256, $1/256 % 256, $1/65536 % 256, $1/16777216);}' | \
        od -Ax -t x
    On Linux with gawk, we get
       000000 005500aa
       000004
    On FreeBSD with nongnu-awk, we get
       000000 000055aa
       000002
    
    In awk, all the numbers are floating point number. So division doesn't
    round the result from 0.75 (3/4) to 0.
    And, There is a fact that, for the FreeBSD awk,
    sh> awk 'BEGIN {printf("%c", 0.75)}';
    produces nothing, instead of 0.
    
    Here we need to convert the floating point number to
    integer by int(X), which is an awk built-in function, instead of GNU
    extension.
    
    Change-Id: I3470d5f13e7ea59a978d5575a54c0d56368dc78d
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1529
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 1d668973645895faedff890ab96d1db9a187dcc2
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Thu Sep 20 10:22:52 2012 +0200

    Fix disconnect handling on UHCI root ports
    
    Change-Id: I03b72cd1c6ed0df09c08f2a687d4f17fa3cf6afc
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1531
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit f6c808090af3f4c93b8c0bca61308fd68111b045
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Thu Sep 20 10:24:01 2012 +0200

    UHCI: use proper pointer size
    
    We used sizeof(listp*) at a place where sizeof(listp) is more appropriate:
    While these are pointers, they're part of the UHCI design, and don't depend
    on ISA details.
    
    Change-Id: I4d3cb571c9a407103bc81fc171a8e73b68f7c7a1
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1530
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 5b209c07186ee2b20185f00836dd61ead8be3e73
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Thu Sep 20 16:09:51 2012 +0800

    crossgcc: Change the term color back (trivial)
    
    Change-Id: I6a7852eef32a3440c9d29e45420cb21d2db8c404
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1528
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a7f374fb68156ea0ee984438f3a0f2f63910733e
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Fri Sep 7 19:16:58 2012 +0800

    cimx sb700: change Platform.h to remove some warnings
    
    TRACE has redefined warnings in src/southbridge/amd/cimx/sb700/Platform.h,
    so we do some changes to remove such warnings.
    
    Change-Id: I24979e08b83434f91a8fa37cd9f16303fa0b298d
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1499
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 128c7d73151a539ebf8d1cbd6ea22d4661aa2a3d
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Fri Sep 7 19:03:24 2012 +0800

    agesa fam15 northbridge: change lapic_id to accommodate two CPUs
    
    According to http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c;hb=HEAD#l273 line 273,
    adjust apic id to accommodate two CPUs.
    The Tyan S8226 has two CPU sockets, and the current code just finds one CPU's cores.
    we adjust apic_id in cpu_bus_scan so as to find all CPUs.
    
    Change-Id: Ib3263fc6f5508f744b81e8e388fde9ccd9b51851
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1498
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 1fb49dfa5ea50475da501168717fc8c53e918075
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Fri Sep 7 18:35:17 2012 +0800

    C32 legacy code: change CONFIG_CPU_AMD_SOCKET_C32 to CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA
    
    Currently the C32 has some legacy boards which use the old C32 code. We need to seperate them.
    CONFIG_CPU_AMD_SOCKET_C32 was used in legacy code before.
    But it is not a good idea, so we change the code as follows:
    So we use CONFIG_CPU_AMD_SOCKET_C32 to identify mainboard which uses agesa code,
    and use  CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA to identify mainboard which uses legacy code.
    
    Change-Id: If6114bf8912e78b7732f25a1adfb2e4d8eb10ee4
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1497
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit fec5b647fc05484f8d8703f118f84e958b85329e
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Sep 17 15:39:44 2012 +0800

    AMD Hudson: use awk to calulate instead of expr
    
    Command expr in some systems only take 32bit as integer, which
    value is at 0x7FFFFFFF ~ -0x80000000. Use awk as alternate way to
    calculate.
    And some system doesnt take hex value in Makefile, even in awk instruction.
    
    Change-Id: Ie35d6a5b96eea4192bd9cab857af4d4dcb37b9ed
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1527
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 615304c667dc690aeecfdd655adf8073aafc3cad
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Sep 17 16:38:22 2012 +0800

    lint: Dont highlight the matching text in grep
    
    Sometimes we like to make grep auto-highlight the match text by
    setting the GREP_OPTIONS. This will make the compare_output
    in lint-002 catch the difference between 2 strings which text are
    same but color are different. Override the GREP_OPTIONS.
    
    Change-Id: Ia257214fe5149e084e8eac3fb551a494eaa46ae6
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1526
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a59a9f79435e0fa294d73c27053d59696d9e3d97
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Fri Sep 14 16:29:10 2012 +0200

    Set SMBIOS mainboard version based on i2c eeprom
    
    In the field there are different hardware revisions and some
    of them have problems with UDMA as a resistor is missing. We can
    detect this situation in coreboot and e.g. the linux kernel
    can take this knowledge and disable UDMA.
    
    Change-Id: Ib75cad7acedbc1dc65378bb9bfc3f353cbe21427
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/1512
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ea8011b21d695ac81aca3f2d3df1dc48b4bb2470
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Fri Sep 14 16:28:44 2012 +0200

    Add i2c eeprom to device tree
    
    This eeprom is used to store some device relevant informations
    like hardware revision.
    
    Change-Id: I32bda9d5412bc5a96da0edb5ef0b6d1ba4caa2d8
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/1511
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b3a18acb569f439dff565092d48d6517525490f6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Sep 13 22:13:33 2012 +0200

    Isolate Kconfig host compiler options
    
    This reverts commit 645f2dd5d97ffbaa80da7fbd776a08a76eb758e3.
    
    Instead of adding a special case to nvramtool to avoid it
    picking up Kconfig's regex.h, have the host compiler only
    consider util/kconfig for includes (ie. -Iutil/kconfig)
    for kconfig related object files.
    
    Change-Id: Ie4f97ce38cb3e911f6e6c1e5b6f86f6998d93f69
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1509
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 4adb19bd79df5982a58340529ee1cf423cefe8c2
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Tue Aug 21 16:56:12 2012 -0600

    Mahogany_Fam10: Fixes an apparent ACPI VGA resource collision.
    
    Without this change 64 bit versions of Windows will BSOD.
    
    Change-Id: If39627a179c24184b6c956b3a50f692f8a034d2f
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1476
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 73ab60a9d40601c2309aee38b9cb5d85a9cf6c23
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Sep 11 15:07:14 2012 +0200

    Fix ramstage location in trace scripts
    
    The ramstage location has been changed. Reflect this in the script.
    
    Change-Id: I76c9b38a8ffe2188e94146e845d23536625c0979
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/1504
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 4b14e82e134bfcebfc2d7846a6a83fb9eefffd57
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Sep 11 15:06:17 2012 +0200

    Fix tracing compilation on SMM enabled targets.
    
    Disallow tracing while in SMM.
    
    Change-Id: Icde17629bb06a615cc48f017fd0cd1f7b720e62d
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/1503
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 01a42ba25483809726ad29baecddad9bc429504d
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Sep 11 15:40:05 2012 +0200

    Fix VT8237S USB IRQ routing
    
    The M2V-MX SE DSDT has been a copy from Asus A8V-E SE, which has VT8237R.
    But the stuble change in USB interrupt routing went undetected, although
    I had some USB troubles on the FOSDEM with low speed devices.
    
    Change-Id: Ie724df440e0963f6955b3de57e4687f3ddc7f6ef
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/1505
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 645f2dd5d97ffbaa80da7fbd776a08a76eb758e3
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Tue Sep 11 12:10:09 2012 +0800

    nvramtool: Set build flags for FreeBSD
    
    Set HOSTCFLAGS as nil to make the nvramtool include the regex.h
    in system. Otherwise it will include the regex.h in kconfig, which
    will cause building error in FreeBSD.
    
    Change-Id: I95292e23e1716da1260842be9597119a4e26c8ed
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1500
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Tested-by: build bot (Jenkins)

commit 534e61c4e6eb10deeaaebd0ead88ffe36c439927
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Tue Sep 11 12:13:39 2012 +0800

    nvramtool: Remove the building warning on older gcc
    
    Some older gcc requires the default entry in switch, otherwise
    build warning "enumeration value not handled in switch" will come
    up.
    
    Change-Id: Ic8ea9960e4aca599e0ea62ec345122c9df57e766
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1501
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cf8bcfc9dd0dd4093ab9ce65be8bbdb242959f15
Author: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Date:   Fri Sep 7 19:18:16 2012 +0800

    superio winbond w83627dhg: add a function which is used on tyan s8226
    
    this function is used on serial output of tyan s8226
    
    Change-Id: I5f7fa535b922b224e381886f1bea64623fa549ef
    Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
    Reviewed-on: http://review.coreboot.org/1494
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 87b5aa9e671896f82f9c1e75edbbe363e0a6fe89
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Aug 22 11:10:41 2012 -0600

    IEI/KINO: Fixes an apparent ACPI VGA resource collision.
    
    Without this change 64 bit versions of Windows will BSOD.
    
    Change-Id: Ica4b79d798a269399341868b1c793ce745aa93fc
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1480
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e54995a11653344e2e1d0cdbaff2bb65131a4c48
Author: Stefan Tauner <stefan.tauner@gmx.at>
Date:   Thu Sep 6 10:38:49 2012 +0200

    superiotool: Add support for Fintek F81865F/F-I register dump.
    
    Datasheet: http://www.fintek.com.tw/files/productfiles/F81865_V028P.pdf
    
    The code was done by Juha Tuomala <Juha.Tuomala@iki.fi> but he refused
    to sign it off, or commit it for review. I'll commit it anyway with my sign-off
    because it does not exceed threshold of originality for any copyright.
    
    Change-Id: Id86267f5add539b99229f20bbe339bfb5eb20f8b
    Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
    Reviewed-on: http://review.coreboot.org/1496
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e644bada0262b36605fdb992f449deece0ca0f9d
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Aug 7 19:38:32 2012 -0500

    VIA Nano: Add support for VIA Nano CPUs
    
    Add code to do the following for the VIA Nano CPUs
    - Update microcode
    - Set maximum frequency
    - Initialize power states
    - Set up cache
    
    Attempting to change the voltage or frequency of the CPU without
    applying the microcode update will hang the CPU, so we only do
    transitions if we can verify the microcode has been updated.
    
    The microcode is updated directly from CBFS. No microcode is
    included in ramstage. The microcode is not included in this
    commit.
    
    To get the microcode, run bios_extract on the manufacturer supplied
    BIOS, and look for the file marked "P6 Microcode". Include this
    file in CBFS.
    You can have the build system include this file automatically by
    selecting Expert Mode, then look under
    'Chipset' -> 'Include CPU microcode in CBFS' ->
    Include external microcode file (check)
    'Path and filename of CPU microcode' should contain the location of
    the microcode file previously extracted.
    
    Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/1257
    Tested-by: build bot (Jenkins)

commit 00b579a4478431dbfcef154ec80f5aa7d08d6529
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Jul 20 00:11:21 2012 -0500

    buildsystem: Make CPU microcode updating more configurable
    
    This patch aims to improve the microcode in CBFS handling that was
    brought by the last patches from Stefan and the Chromium team.
    
    Choices in Kconfig
      - 1) Generate microcode from tree (default)
      - 2) Include external microcode file
      - 3) Do not put microcode in CBFS
    
    The idea is to give the user full control over including non-free
    blobs in the final ROM image.
    
    MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode
    is handled by a special class, cpu_microcode, as such:
    
    cpu_microcode-y += microcode_file.c
    
    MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is
    needed by intel microcode updating. Once all intel cpus are converted to
    cbfs updating, this variable can go away.
    
    These files are then compiled and assembled into a binary CBFS file.
    The advantage of doing it this way versus the current method is that
      1) The rule is CPU-agnostic
      2) Gives user more control over if and how to include microcode blobs
      3) The rules for building the microcode binary are kept in
       src/cpu/Makefile.inc, and thus would not clobber the other makefiles,
       which are already overloaded and very difficult to navigate.
    
    Change-Id: I38d0c9851691aa112e93031860e94895857ebb76
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/1245
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit eb1d39bac4d3638d41fc38274ae7a133d7b5c6f2
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Aug 27 17:45:01 2012 +0800

    AMD S3: The offset of the nv storage depends on config.h
    
    Change-Id: Ic8410fb706dce677c7218d19030d84b64cda7b7f
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1485
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 83a6dbd006a3afec979d8bb7316834fcb54e003b
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Aug 22 19:12:49 2012 -0500

    ioapic driver: typedef the ioapic_config struct (TRIVIAL)
    
    I use the ioapic_config in my VX900 branch.
    Typing:
    struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info;
    
    is clumsy at best, so just create a typedef to mahe this more elegant:
    ioapic_config_t config = (ioapic_config_t*)ioapic->chip_info;
    
    Change-Id: I407899845cfbd847ba6309dd0cf9ef836a607c8e
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/1481
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 87213b655eaa09522366f92088f94913024b6ef9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Aug 27 20:00:33 2012 +0300

    Fix AMD UMA for RS780
    
    In commit 6b5eb1cc2d1702ff10cd02249d3d861c094f9118 setup of
    UMA memory region was moved to happen at a later state and
    this broke UMA with RS780 southbridge.
    
    Share the TOP_MEM and UMA settings before any of the PCI or CPU
    scanning takes place.
    
    Change-Id: I9cae1fc2948cbccede58d099faf1dfe49e9df303
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1488
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 71c7a3fdc34b013c05d7de08728dfae4064d1946
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Tue Aug 28 12:02:26 2012 +0800

    AMD hudson: Complete the missing rule
    
    Forgot to change the code back after debugging.
    
    Change-Id: Iaf58d65c14d53ca77958080faf6ab85d60992226
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1491
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit d2245bbeb8c2efe1a2a527137dace895fcf33913
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Aug 27 09:09:23 2012 +0300

    Drop unused ISA Pnp definitions
    
    These declarations were never or no longer used.
    
    Change-Id: Icdbfc0838d5021ea02ab031b643b3fe6361b39b4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1489
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 3780597cc31422dd54e385cdb508ab30467fdd51
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Tue Aug 21 16:51:33 2012 -0600

    SB700/SP5100: This configures the HPET clock period.
    
    Prior to this change the setting would be zeroes and
    would cause a BSOD in 64 bit versions of Windows.
    
    Change-Id: I2d422ef9667457af53f9fd055799e489ed2b25db
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1475
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit cc6019879d7f7f7d4a9d9dba358349f0752af583
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Aug 27 18:40:44 2012 +0800

    AMD Hudson: Move the combining firmware from Python to sh.
    
    Maybe sooner or later python is not a default tools to build coreboot.
    Most of the work is done by awk now. GNU extension of gawk is not used, isn't?
    echo, expr, printf, cat, awk, test, mv are the external tools.
    If XHCI, IMC or GEC firmware is not available and not defined, this script can skip
    integrating them.
    
    Change-Id: I9944b22b0b755672a46d472c355d138abafd6393
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1417
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit a5de94128b5e56d138dfd7bdc4a77f1add810f89
Author: Zheng Bao <fishbaozi@gmail.com>
Date:   Mon Aug 27 16:58:39 2012 +0800

    gitconfig: Match the Change-Id line more exactly
    
    Change-Id: I5ac267770bc5b43dd1435e75ab0fcbde0d88b664
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1487
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Tested-by: build bot (Jenkins)

commit 0a78f91fa378879ee0bd202aca3c839eed6c24be
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 31 23:47:09 2012 +0300

    Intel model_106cx: change CAR to HT-capable
    
    There are hyper-threading Atom CPUs, those would not enable L2
    cache with model_6ex CAR code. Switch to code that can handle
    different number of threads and cores.
    
    Change-Id: I57328c231f8998f45f7b0d26c63b24585f8476dd
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1384
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: James Laird <jhl@mafipulation.org>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit c33f1e9261adbe3921d305274e34ddab9101bc4e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Aug 7 17:12:11 2012 +0300

    AMD northbridges: factor out CPU allocation
    
    Factor CPU allocation out of AMD northbridge codes. As CPU topology
    information is required for generation of certain ACPI tables, make
    this code globally available.
    
    For AMDK8 and AMDFAM10 northbridge, there is a possible case of
    BSP CPU with lapicid!=0. We do not want to leave the lapic 0 from
    devicetree unused, so always use that node for BSP CPU.
    
    Change-Id: I8b1e73ed5b20b314f71dfd69a7b781ac05aea120
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1418
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit cd9fc1aa5f483818385c4a6c98afee4c8f49ad8e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 6 19:02:56 2012 +0300

    AMD northbridges: rewrite CPU allocation
    
    Use of alloc_find_dev() prevents creation of a device duplicates
    for device_path and is SMP safe.
    
    Reduce scope of variables to make the code more readable and in
    preparation for refactoring the allocation out of northbridge.c.
    
    Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1186
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 8c0279088266beccdc8953ecf2dd340fa27ed768
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Aug 20 11:19:00 2012 +0200

    MPTABLE: check for fixed IRQ entries on all pins
    
    Don't derive the IRQ pin from the function number. Especially onboard
    chipset devices don't follow that rule. Instead check and add all
    fixed IRQ entries.
    
    Change-Id: I46c88bad39104c1d9b4154f180f8b3c42df28262
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1461
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 651339bb5d3114a83b2ae4bf5d1da87636e7dadc
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Aug 25 00:21:44 2012 +0300

    Fix mptable build troubles
    
    A missing mptable.c file got passed jenkins, got merged
    and broke the build. Hopefully finally fix this.
    
    Deletes unused files:
       src/mainboard/asus/dsbf/mptable.c
       src/mainboard/supermicro/x7db8/mptable.c
    
    Change-Id: Ie81f5a6c4c69ab381f86a243bc8874395e69ee26
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1486
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 1c36eada27697e1feafda6db162f7d4854b64ff6
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Thu Jun 28 08:30:15 2012 +0400

    libpayload: add controller type in usbdev_hc
    
    Add controller type (UHCI, OHCI, EHCI or XHCI)
    into usbdev_hc (hci_t) struct, so now we know
    which type selected controller have. It needed
    to access controller specific data, if access
    usb tree outside of libpayload (e.g. in payload
    intself)
    
    Change-Id: I7df947bbb56a50d0d792ccd4d3a6b021ee95e2ea
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1145
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 79b0574698f34abbb4a7924d4e40ea2b2b2cecf3
Author: zbao <fishbaozi@gmail.com>
Date:   Tue Aug 21 16:25:41 2012 +0800

    crossgcc: Update GDB patch version to 7.4.1
    
    libgen.h dont have to be included.
    
    Change-Id: I46a6a23a310b20784de956a577f1ab3c7931e34d
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1470
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5be2060e097135a23632dd32521f21d0294166fc
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Aug 20 11:21:00 2012 +0200

    LUMPY: Add information to generate MPTABLE from devicetree.cb
    
    Change-Id: If68888e87c5197328c59dafce1301eefe000e28e
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1462
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit fee73df07ac0d17f319486f977585c7945e0d069
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Aug 21 11:37:11 2012 +0300

    Auto-declare chip_operations
    
    The name is derived directly from the device path.
    
    Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1471
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 0d5d70b79a3824bfa46a7035d901cb0e7672e3fe
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Aug 21 17:08:03 2012 -0500

    mptable: bring sanity back to mptable generation (TRIVIAL)
    
    Remove extra semicolon
    Capitalize beginning of printk sentence
    Fix detection of multiple ISA-carrying  IOAPICs
    Fix whitespace issue
    
    Change-Id: I114119b1daf3b472955c0dd00bdc449401789525
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/1474
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 0013bbfa98586394015d28dce1be8e0f70d47d60
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Tue Aug 14 11:01:53 2012 -0600

    Support use of the compression option when adding payloads to cbfs.
    
    Change-Id: Ie77e8e1628d34f1a9e7a57e994bf2882c5e55e25
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1452
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0690eb2d908deb28f46a629f225c010a20f4c821
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Tue Aug 14 10:59:17 2012 -0600

    Change to allow coreboot to use "add-payload" instead of "add" for payload images.
    
    The current code does some argument manipulation to detect when a stage is being
    added to cbfs. This same manipulation needs to be done when adding a payload.
    
    Change-Id: Ief4c4a81446c9437923cbbb1ce3fa90729317587
    Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1451
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 64c40ddeec6f3f125683bb5a280255bb2d321f98
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Aug 20 11:17:52 2012 +0200

    Don't write automatic IRQ entries for disabled devices
    
    Change-Id: Ib3dae4f0957a2e0057c0dffb5eb9904af20dcd40
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1460
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 7ecfa3073375c8a3797afeaf9dff831e929fb2e2
Author: zbao <fishbaozi@gmail.com>
Date:   Wed Aug 15 18:15:37 2012 +0800

    AMD S3: Add a document about S3 on AMD platform
    
    See the document. Need review. Everything should be in Authentic
    English.
    
    Change-Id: Idc528b8c6b0d5afe08fc4f4387b7bff30698f677
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1400
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit de415ebdd62eced24823edc3d0d2805c8c3fac3b
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Aug 15 06:45:18 2012 -0500

    coreboot: Dump memory around problem area when encountering exception
    
    When we encounter an x86 exception, we print the problem address, dump the
    registers and die. This may not be sufficient information for debug. Also
    dump the memory around the problem instruction. This has proven useful in
    identifying memory issues, and DRAM burst reordering problems.
    
    Change-Id: I6411344e89f946e16d11217d7dbd73812c45d54c
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/1454
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 811d661f3aabaed97e3367dbb45a96244432b3f8
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Aug 15 06:36:00 2012 -0500

    coreinfo: fix build error (TRIVIAL)
    
    Changes to libpayload, and lack of maintenance to coreinfo, and it no
    longer builds. Fix that.
    
    Change-Id: I03497880671f42b5aeb6db08ddf6ce2acd243a18
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/1453
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 2efabba46886d89c4b8593c39cd036ff849620d9
Author: zbao <fishbaozi@gmail.com>
Date:   Wed Aug 8 19:25:04 2012 +0800

    buildgcc: Remove the warning options unsupported by cygwin
    
    My cygwin hostcc doesn't support
    -Wempty-body -Waddress -Wmissing-field-initializers
    
    Change-Id: I879e05f3bd396b36b327f204252e820552b6e12e
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1426
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 844e01357b6a045cb6d0d20aa806181b88be8129
Author: zbao <fishbaozi@gmail.com>
Date:   Wed Aug 8 18:45:07 2012 +0800

    buildgcc: Update the toolchain patches version
    
    acpica 20120420, acpica-unix-20110922_no_unused_variables.patch is not
    used anymore.
    binutils 2.22.
    
    Change-Id: I58459bd2eba2ad752fc033e51ee0892e2e069a02
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1424
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 7598beac6386ddc88e96f717ac46c707b768ed01
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Aug 9 15:08:20 2012 +0800

    AMD Hudson: Enable HD audio
    
    Something about HD audio was scrubbed. Take it back.
    
    Change-Id: I0be96fd103f3ebd4e8c7ef09a184b71aa34ee3fd
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1427
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit f2c3254870550c8ab2c164ca6a54523af1a83ff6
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Aug 10 15:44:02 2012 +0800

    gitconfig: upate commit-msg if newer one is available
    
    Change-Id: Iea010bf6f456a5ce5d8906821c95a7de4b577085
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1429
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9de0fee935e4045c540a7e2d6b35b4552bd8c411
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Aug 5 12:12:05 2012 +0300

    Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU
    
    The search loop for UMA resource was only used to check for the highest
    RAM address below 4GB. The cached values from BSP CPU can now be used
    for the replication.
    
    Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1388
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit dbc4739a0dcaffde1d0f2edbc6878e88b77ebd77
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Aug 5 12:11:40 2012 +0300

    AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution
    
    Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed
    to AP CPUs and factor out the debugging info from setup_uma_memory().
    
    Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1387
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 7874e9dcfc710402a692c4f36bae78d453b27ccc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jul 25 16:15:25 2012 -0700

    Sandybridge: Fix integer overrun in romstage udelay()
    
    This was broken, fixing according to related patch for i945
    
    Change-Id: I925cd205ee5beb918181740a7b981a4209688ac6
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1412
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0db6820b10c3452764ab62173c3b75cefbf6c215
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Aug 7 14:44:51 2012 -0700

    Synchronize rdtsc instructions
    
    The CPU can arbitrarily reorder calls to rdtsc, significantly
    reducing the precision of timing using the CPUs time stamp counter.
    Unfortunately the method of synchronizing rdtsc is different
    on AMD and Intel CPUs. There is a generic method, using the cpuid
    instruction, but that uses up a lot of registers, and is very slow.
    Hence, use the correct lfence/mfence instructions (for CPUs that
    we know support it)
    
    Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1422
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 4c29d7f27d315ab93c811fb86ba246151dc84da3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Aug 2 09:49:11 2012 +0300

    Do not allow modifying memory table directly
    
    Adding ranges directly into coreboot memory table raised issues
    as those methods bypassed the MTRR setup. Such regions are now
    added as resources, so declare the functions again as static.
    
    Change-Id: If78613da40eabc5c99c49dbe2d6047cb22a71b69
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1415
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit cf8e4660846eb414d38dc4bb380006806430e902
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Aug 2 11:52:22 2012 +0300

    Cleanup coreboot memory table includes
    
    The includes removed here were previously required for
    struct lb_memory and lb_add_memory_range().
    
    Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1391
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit a675d494082e689a0766ee98948779da13ea2d07
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Aug 7 14:50:47 2012 -0700

    Fix SMBIOS generation
    
    Dropping mainboard's chip.h broke execution of the mainboard's enable
    function and the addition of mainboard specific smbios tables.
    
    The former was fixed by Kyosti in http://review.coreboot.org/1374
    This patch fixes the breakage in static.c and also backs out a small
    portion of Kyosti's patch (because it's not needed anymore)
    
    Change-Id: I6fdea9cbb8c6041663bd36f68f1cae4b435c1f9b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1421
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 6a73bf668849d5c8940f04197cf6087dcc45ce77
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Aug 7 21:17:33 2012 -0500

    gitignore: Ignore KDE backup files
    
    KDE editors love to create tons of backup files every time a file is
    edited. This makes it very hard to get useful information from git status
    and very easy to commit the wrong stuff. Add those to the gitignore list.
    
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Change-Id: I2fbb907f21d85d6994caa8bbe32c4e9814b5f4b4
    Reviewed-on: http://review.coreboot.org/1423
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 1c5071d1753b759f1f3c58fca93eaa7a0aabb804
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Aug 2 09:48:38 2012 +0300

    Drop HAVE_MAINBOARD_RESOURCES
    
    These existed to provide a hook to add reserved memory regions
    in the coreboot memory table. Reserved memory are now
    added as resources.
    
    Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1414
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 62673c0290790da8eaee6a4d3f951ec29d0e6fa9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Aug 2 09:44:03 2012 +0300

    Siemens SiteMP: drop add_mainboard_resources()
    
    Use of lb_add_memory_region() is reduntant with the MMCONF
    resource being set as reserved.
    
    Change-Id: I747ea34823692b6966b2e50d22aea1fb89c73c25
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1394
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 7bdf85bfdb4e2c5efe47d8474f42f42c152c8882
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jul 7 13:42:03 2012 +0300

    Move cpus_ready_for_init() to AMD K8
    
    The function is a noop for all but amd/serengeti_cheetah.
    
    Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1184
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 9ca1c0af64eeec013e3b4997fb86d334101c7f47
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jul 25 16:10:36 2012 -0700

    Sandy/Ivy Bridge and Cougar/Panther Point: Fix names
    
    The names were set at various times during development, but
    the way the code works, you might end up with the wrong name
    being displayed in the logs. Instead of doing magic, just
    display both names for each component
    
    Change-Id: I1f8ce44d156442f5f7d717e1a2b47ed1218d4527
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1413
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b98d07813d39321e09a18233a565a5fe22944537
Author: Dylan Reid <dgreid@chromium.org>
Date:   Fri Apr 27 11:37:33 2012 -0700

    bd82x6x: Add beep commands
    
    Move beep commands to board-specific area as they need to be different for
    different codecs.
    
    Change-Id: I2a1ac938c49827cc816a95df10793a7e234942bf
    Signed-off-by: Dylan Reid <dgreid@chromium.org>
    Reviewed-on: http://review.coreboot.org/1410
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c02cadaee1c909c116b54502eadeade725011767
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Aug 2 09:46:38 2012 +0300

    AMD RS690: mark MMCONF resource as reserved MEM
    
    Use IORESOURCE_RESERVE to exclude the region from system RAM table.
    
    Change-Id: I61b51022165e1304a41554f67af75b3089d892af
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1393
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit ffb6bddea274e2476327efe59661a62cf904de40
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Aug 3 16:06:08 2012 +0800

    AMD f15: Change multiply ONE_MB to bit shifting (Propagation)
    
    Apply the change
    http://review.coreboot.org/1263
    to family15 northbridge.
    
    Change-Id: If1109f20ffd833a716e092c5e4f6f16ee6b968c7
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    [km: rebased]
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1405
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 366f0fc30a6b0439cfa2867b3d435975512bd9b8
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Aug 3 16:58:53 2012 +0800

    AMD SB: Call the rtc update if needed (Propagation)
    
    Apply the change
    http://review.coreboot.org/1390
    to all the AMD southbridge.
    
    Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1406
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit cc3b18843f5db9ccdb2c8cd609897e2560f47a92
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Aug 2 09:44:14 2012 +0300

    Technexion TIM5690: drop add_mainboard_resources()
    
    Move the POST display to take place just before jumping
    the payload, a bit later than before.
    
    Change-Id: Ie1d1ff24dc6c1640e25681be7dc5740943c7f112
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1396
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit f85398c3ab2073fe7c4abdaa74d1adc9945d2fd2
Author: zbao <fishbaozi@gmail.com>
Date:   Sun Aug 5 11:46:23 2012 +0800

    AMD S3: Remove the hardcoded volatile position
    
    Change-Id: I4bcf3f3435f0ba487955d14ed1b010fd94b9f625
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1408
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

commit 695cc769e6dfdabc4891342f0b949d948d42cf3c
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Aug 3 17:12:45 2012 +0800

    AMD Thatcher: Add BIOS callback hook for getting VBIOS Image
    
    Apply the change
    http://review.coreboot.org/1351
    to thatcher.
    
    Change-Id: I33e7ad0cad2ae06f5934c60939d60a18444aa24e
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1407
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f88204e02b2ece82a76544070f37a4e2e2bd0f11
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Aug 3 13:20:57 2012 -0500

    Add a capability for mainboard-specific posting.
    
    Some mainboards have really nice capabilities for posting, beyond
    simple POST cards. Further, some can not use a POST card. This
    change defines a weak symbol (mainboard_post) that can be overridden
    by a real mainboard_post function.
    
    If, for example, you'd like to do something fancy before the payload starts,
    you can add this to mainboard.c:
    
    void mainboard_post(u8 value)
    {
    	switch(value){
    		case POST_TIME_TO_PARTY: some_fancy_lights();
    		break;
    	}
    }
    
    Maybe the post function should be an entry in the device. We're beginning to over-use
    weak symbols.
    
    BUG=None
    
    TEST=Build and boot a google chromebook. Observe that it still works. Use it to drive
    some pretty lights.
    
    Change-Id: I3512d2ec34a66c747287191851c3f68b6a7cc1b2
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/1397
    Tested-by: build bot (Jenkins)

commit 16b022a15c78780e212e57c8284494ccf2d40d23
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 17 16:42:51 2012 -0700

    Perform additional programming requirements for SATA
    
    In accordance to PCH EDS 14.1.35.1
    
    Change-Id: I2e6cec6d4f49f404e33a171a8fbd6e4880327896
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1411
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 57879c9bd1775ad7089e3ab93dd260deec87e95c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 31 16:47:25 2012 -0700

    Make the device tree available in the rom stage
    
    We thought about two ways to do this change. The way we decided to try
    was to
    1. drop all ops from devices in romstage
    2. constify all devices in romstage (make them read-only) so we can
       compile static.c into romstage
    3. the device tree "devices" can be used to read configuration from
       the device tree (and nothing else, really)
    4. the device tree devices are accessed through struct device * in
       romstage only. device_t stays the typedef to int in romstage
    5. Use the same static.c file in ramstage and romstage
    
    We declare structs as follows:
    ROMSTAGE_CONST struct bus dev_root_links[];
    ROMSTAGE_CONST is const in romstage and empty in ramstage; This
    forces all of the device tree into the text area.
    
    So a struct looks like this:
    static ROMSTAGE_CONST struct device _dev21 = {
     #ifndef __PRE_RAM__
            .ops = 0,
     #endif
            .bus = &_dev7_links[0],
            .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
            .enabled = 0,
            .on_mainboard = 1,
            .subsystem_vendor = 0x1ae0,
            .subsystem_device = 0xc000,
            .link_list = NULL,
            .sibling = &_dev22,
     #ifndef __PRE_RAM__
            .chip_ops = &southbridge_intel_bd82x6x_ops,
     #endif
            .chip_info = &southbridge_intel_bd82x6x_info_10,
            .next=&_dev22
    };
    
    Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727
    Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1398
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 15dc3ccaab5a431b1a0b99aaba9d61457b219343
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Aug 3 15:56:21 2012 +0800

    AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation)
    
    Apply the change
    http://review.coreboot.org/1265
    to all the AMD northbridge.
    
    Change-Id: Idf3994c1e9ec76cd19db9f740d825cf24059884f
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1404
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 49bb26a469c4e0dc4fd2414c11c9926046199730
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Aug 3 15:44:42 2012 +0800

    AMD NB: Limit the device field to 5 bits. (Propagation)
    
    Apply the change
    http://review.coreboot.org/1264
    to all the AMD northbridge.
    
    Change-Id: Ied74d6f579d2c0350288e2619d7810f8d44fa574
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1403
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9bf356fc53a2af90ad74550182dcd1b040e594df
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Aug 3 15:09:09 2012 +0800

    SuperIO LPC47N217: Remove warnings
    
    Change-Id: Id5756f1bb748ae7bec0bcdc21804f5338e850baa
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1402
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 15945445ebaaf127443571652d072bb215ab048a
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Aug 3 11:47:53 2012 +0800

    AMD Parmer: Remove warning.
    
    Change-Id: I4ba2d480fa6df5ee741d887d26524b32c1901d73
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1399
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 125d7c72a662c8df1d21ee026e3ffbbdb8844b42
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Aug 2 09:43:48 2012 +0300

    VIA Epia-N: drop add_mainboard_resources()
    
    The board had HAVE_MAINBOARD_RESOURCES=0 so this was never
    called. Drop unnecessary includes too.
    
    Change-Id: Ia7bddf29a16966c052b5cabbb47029299e6dbd12
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1392
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit df0fbc7455bb7e7a6081c539c9c94d68168e72d6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 4 12:02:58 2012 +0300

    Intel CPUs: Fix counting of CPU cores
    
    Detection for a hyper-threading CPU was not compatible with multicore
    CPUs. When using CPUID eax==4, also need to set ecx=0.
    
    CAR init tested on real hardware with hyper-threading model_f25 and
    under qemu 0.15.1 with multicore CPU.
    
    Change-Id: I28ac8790f94652e4ba8ff88fe7812c812f967608
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1172
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 15cf0adc3edaf184d98a3b3c228e0858ff7b24d3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 27 19:22:26 2012 +0300

    Fix mainboard level enable_dev()
    
    Commit 188e3c2ff06a82f61d7d71e610b32b1a250c0a45 dropped mainboard
    out of the static device tree. This left dev_root->chip_ops unset,
    and mainboard_ops.enable_dev() was no longer called.
    
    Change-Id: I6d447c8049a66041b8bb36ec9aac3e7e0d20a99b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1374
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a1e6a9c25a1d897fbb06f634bbee6e7983a95524
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Aug 2 19:02:26 2012 +0800

    RTC: Add a routine to check if the CMOS date is valid
    
    If the CMOS is cleared or someone writes some random date/time
    on purpose, the CMOS date register has a invalid date. This will
    hurts some OS, like Windows 7, which hangs at MS logo forever.
    When we detect that, we need to write a reasonable date in CMOS.
    
    Alexandru Gagniuc:
    Hmm, it would be interesting to use the date the coreboot image
    was built and set that as the default date. At least until time
    travel is invented.
    
    Change-Id: Ic1c7a2d60e711265686441c77bdf7891a7efb42e
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1389
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d462736dfbedba7daec0c9812470a88a535b7c43
Author: zbao <fishbaozi@gmail.com>
Date:   Mon Jul 23 19:49:40 2012 +0800

    Limit the device field to 5 bits.
    
    The field device in PCI_ADDRESS only takes 5 bits. So if the device number is
    more than 32, it will truncated to 5 bits. Before this patch, other pci devices
    will be incorrectly probed as processor node.
    
    Change-Id: I64dcd4f4fda7b7080a9905dce580feb829584b94
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1264
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit ef180e2a2ccd60a2be6cd3b2ddd4bdf450761f01
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Aug 2 19:03:44 2012 +0800

    AMD hudson: Call the rtc update if needed.
    
    Parmer and thather hang at windows 7 booting process. Setting the
    valid date in CMOS can fix that.
    
    Change-Id: I5e427cfb42430ebebdb4c1e48bd25860c0fec45f
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1390
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ea71e81920dbb9fa8bc73dd67f080fa090411463
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Aug 2 18:36:36 2012 +0800

    AMD Thatcher Board based on trinity
    
    Thatcher features: Family 15 trinity FP2. Hudson.
    close to Parmer.
    This board and parmer both need to revert the change
    http://review.coreboot.org/#/c/1359/, and add thatcher's own
    chip.h,otherwise the mainboard_enable can not be called.
    
    Change-Id: I54e1cfca845fbcea1d3aad5eff08d760d0d215c9
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1382
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 170d19c2ad516c146762b8cf597ededa467495fc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jul 26 15:48:17 2012 -0700

    x86emu: fix jump_near_IMM to handle DATA: flag correctly
    
    Before (data flag ignored -> broken):
    66                  DATA:
    e944f1              JMP       1ff6
    
    After (fixed):
    66                  DATA:
    e944f1ffff          JMP       00001ff8
    
    This subtle difference in the length of decoded instruction meant
    that the VBE call jumped to the routine setting AX=0x14F (VBE Failed)
    instead of the routine that set AX=0x4F (VBE success).
    
    The ability to run the same code in vm86 significantly aided the
    debugging of this issue. Those X.org developers who would like to drop
    vm86 better take special care towards _all_ vesa bugs, as those will
    expose further issues.
    
    Imported from:
    http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=cc2c73ddcb4370a7c3ad439cda4da825156c26c9
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: Id08ead9b17468cf19ede45508e5dcc50e45b5acf
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Tested-by: Luc Verhaegen <libv@skynet.be>
    Reviewed-by: Adam Jackson <ajax@redhat.com>
    Signed-off-by: Keith Packard <keithp@keithp.com>
    Reviewed-on: http://review.coreboot.org/1365
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3b69578cd2a138b8fa1260a0dd1fa943cba113cd
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jul 26 16:25:53 2012 -0700

    x86emu: Fix more mis-decoding of the data prefix
    
    cc2c73ddcb4370a7c3ad439cda4da825156c26c9's three-cent titanium tax
    doesn't go too far enough.  Fix the rest of the call and jmp
    instructions to handle the data prefix correctly.
    
    Reference: Intel 64 and IA-32 Architectures Software Developer's Manual
    Volume 2A: Instruction Set Reference, A-M
    
    http://www.intel.com/Assets/PDF/manual/253666.pdf
    
    Imported from:
    http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=bb18f277156c08be028a6e12d8987fb1593e9168
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I83e6245d9748ee86722cfb7d8ac65258c35c013c
    Reviewed-by: Julien Cristau <jcristau@debian.org>
    Signed-off-by: Adam Jackson <ajax@redhat.com>
    Reviewed-on: http://review.coreboot.org/1366
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b25374cec558cacadafb9e10d8816508c5a8ecc4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Aug 1 08:05:22 2012 +0300

    Remove uma_memory_base from build if no GFXUMA
    
    This patch validates the previous "drop uma_memory_base" patches;
    there are no more references to uma_memory_base when GFXUMA is not
    selected.
    
    Change-Id: I735b5e765b0c5cb4af1b4a7470cfe1af2bda7d38
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1385
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 6b5eb1cc2d1702ff10cd02249d3d861c094f9118
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 19 19:26:43 2012 +0300

    AMD and GFXUMA: move setup_uma_memory() to northbridge
    
    UMA region can be determined at any time after the amount
    of RAM is known and before the uma_resource() call.
    
    Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1379
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 30f04645c1dc25a34d1e274a360a8a97f1d07f92
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 20 08:31:37 2012 +0300

    AMD Agesa and GFXUMA: drop use of uma_memory_base
    
    Without GFXUMA, variables were not referenced anywhere.
    Fail builds on Family10 if GFXUMA is selected, because the northbridge
    code does not set UMA base or size.
    
    Change-Id: I15b91cf6241e9a890398eed03824b753828a0a51
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1247
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit f803ac4a4550b6f767b67117731446d75db85a68
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 20 08:24:49 2012 +0300

    AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_base
    
    The code in rs690 or rs780 is always used with K8 or AMDFAM10
    northbridge. Without GFXUMA, both of these set the same static value
    indirectly using the variable uma_memory_base.
    
    Make the register setting with immediate value, to remove the obscure
    use of variable uma_memory_base.
    
    Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1246
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit bbf249649336801517f77d1f76aafeaf20d96180
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jul 26 15:40:06 2012 -0700

    x86emu: Respect the LEA 67h address size prefix
    
    From
    http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=f57bc0ede8e018c7e264b917927c42a018cd1d5a
    
    Change-Id: Ibdcaa27e936464cec512edb46447aa6284a34975
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Christian Zander <chzander@nvidia.com>
    Signed-off-by: Aaron Plattner <aplattner@nvidia.com>
    Tested-by: Tiago Vignatti <tiago.vignatti@nokia.com>
    Signed-off-by: Keith Packard <keithp@keithp.com>
    Reviewed-on: http://review.coreboot.org/1364
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9fd183efde9b78ba2f2bf1c1922a3968650b3b05
Author: zbao <fishbaozi@gmail.com>
Date:   Wed Aug 1 18:23:49 2012 +0800

    AMD F15tn northbridge: Remove the misleading 0x100 from the limitk.
    
    I dont known if missed something, but why an extra 0x100 was added to limit?
    My board would get the wrong memory table entry 7f000000-7fffffff as RAM, which
    is higher than TOM.
    coreboot memory table:
    0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
    1. 0000000000001000-000000000009ffff: RAM
    2. 00000000000c0000-000000005e13efff: RAM
    3. 000000005e13f000-000000005effffff: CONFIGURATION TABLES
    4. 000000005f000000-000000007effffff: RESERVED
    5. 000000007f000000-000000007fffffff: RAM
    6. 00000000a0000000-00000000afffffff: RESERVED
    
    Ronald G. Minnich:
     I think someone who wrote the code was trying to round up the
    next 0x100 boundary and did it incorrectly.
    Here is code that would do it correctly:
    limitk = ((resource_t)((d.mask + 0x00000ff) & 0x1fffff00)) << 9 ;
    
    Zheng:
     Plus 0xFF is correct, but the d.mask take bit 0 as enable it.
    This bit should be clear when we try to calculate the limitk.
    
    Change-Id: I3848ed5f23001e5bd61a19833650fe13df26eef3
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1265
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9edd8e46f5863d6729b7042279737c483143f8ed
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Jul 29 10:34:59 2012 +0300

    AMD and GFXUMA : drop redundant use of lb_add_memory_range()
    
    See commit 505414a6cfb2aeef455b5144e4b96fc27f19eb39.
    
    Change-Id: Icc04af9726ae54141581aecc84c40e8aac54591d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1378
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 5e29f00c5598942b3f57813f90fbbb73f82e969b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 18 14:38:54 2012 +0300

    Intel and GFXUMA: drop redundant use of lb_add_memory_range()
    
    Use of uma_resource() in northbridge code created a memory
    resource marked as reserved. Such resources are removed
    from system memory in write_coreboot_table().
    
    Change-Id: I14bfd560140d8d30ec156562f23072bfae747bde
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1238
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 7f189cc74eb0358149f892c32a9bfa7b831c83a3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 27 13:12:03 2012 +0300

    Intel Sandybridge and UMA: use mmio_resource()
    
    With SandyBridge northbridge code, uma_memory_size was reset to
    zero before variable MTRRs were set. This means MTRR setup routine
    did not previously create a un-cacheable hole for uma.
    
    Keep the behaviour that way, mmio_resource() has a prerequisuite that
    the new region does not overlap with any cacheable ram_resource().
    
    The result is not optimal setup in the number of used MTRRs, but
    continue with this approach until MTRR algorithm is improved.
    
    Change-Id: I63c8df19ad6b6350d46a3eca3055abf684b8b114
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1373
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 1ec5e744c63938aa75e80e8d7548d05e998660a2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 26 23:51:20 2012 +0300

    Intel Sandybridge: add reserved memory as resources
    
    Reserved memory resources will get removed from memory table at
    the end of write_coreboot_table(),
    
    Change-Id: I02711b4be4f25054bd3361295d8d4dc996b2eb3e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1372
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 51676b14e8cfd5bbabf487f659f11704f17f6d0f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jul 29 19:18:03 2012 +0200

    Revert "Use broadcast SIPI to startup siblings"
    
    This reverts commit 042c1461fb777e583e5de48edf9326e47ee5595f.
    
    It turned out that sending IPIs via broadcast doesn't work on
    Sandybridge. We tried to come up with a solution, but didn't
    found any so far. So revert the code for now until we have
    a working solution.
    
    Change-Id: I7dd1cba5a4c1e4b0af366b20e8263b1f6f4b9714
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1381
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a2701c60052df5544930a8dce8f01768834fdf28
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jul 29 17:42:52 2012 +0200

    Revert "remove CONFIG_SERIAL_CPU_INIT"
    
    This reverts commit 78efc4c36c68b51b3e73acdb721a12ec23ed0369.
    
    The broadcast patch was reverted, so this commit should also
    be reverted. The reason for reverting the broadcast patch:
    
    It turned out that sending IPIs via broadcast doesn't work on
    Sandybridge. We tried to come up with a solution, but didn't
    found any so far. So revert the code for now until we have
    a working solution.
    
    Change-Id: I05c27dec55fa681f455215be56dcbc5f22808193
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1380
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1068087c64006a1af0d6dc04b2de6c3dbb7107a0
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jul 25 14:19:45 2012 +0200

    USBDEBUG: retry harder for slow devices
    
    Some usb debug devices don't respond fast enough. The linux kernel
    (which uses almost the same usbdebug code) added a bit more
    retry code, so let's copy that. Even if it might look stupid,
    i pass the DBG_LOOPS argument through all functions to keep
    the code at least a bit in sync with the linux kernel code.
    
    Change-Id: I7c4b63b8bf1d2270fd6b8c8aa835e2cb324820bd
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1375
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4141993536039e0d45caeacb745a89d388f0724b
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sat Jul 28 08:52:44 2012 +0200

    bd82x6x: Fix CONFIG_USBDEBUG
    
    Compilation fails with set_debug_port undeclared in ramstage and
    smm code. Fix that by adding usb_debug.c to the appropriate stages.
    
    Change-Id: I2a037d3c5fab76ae6ea65c3a7f4d4e7561bb6d34
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1376
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d4ee8082f15bf695b8687fb2a26f3b49a9956a40
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sat Jul 28 09:28:56 2012 +0200

    sandybridge: reinitialize usbdebug after MRC
    
    MRC messes with USB devices, so we have to reinitialize
    USB debug after MRC has finished.
    
    Change-Id: I45c0a687cebd69d0a31235bb870f8c455f42d4f2
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1377
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

commit 4b80cd45c3810663700a174a3514220305887b0e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jul 26 15:02:49 2012 -0700

    x86emu: Fix BSF and BSR instructions
    
    Patch courtesy of Michael Yaroslavtsev.
    Synced from Xorg
    http://cgit.freedesktop.org/xorg/xserver/commit/?id=66fa87292ef26bd0f464481287f3af992cd5741c
    
    Change-Id: I266f910d4a535eab4e2ad77f2540f2f1495bed61
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1360
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6ff1d36a4762365cdbc109d0c07778bfdd56dbaf
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 27 08:42:20 2012 +0300

    Intel and GFXUMA: fix MTRR and use uma_resource()
    
    Commit 2d42b340034ff005693482ef9ca34ce3e0f08371 changed the
    variable MTRR setup and removed compensation of uma_memory_size in
    the cacheable memory resources.
    
    Since the cacheable region size was no longer divisible by a large
    power of 2, like 256 MB, this caused excessive use of MTRRs.
    As first symptoms, slow boot with grub and poor user response.
    
    As a solution, register the actual top of low ram with ram_resource(),
    and do not subtract the UMA/TSEG regions from it.
    
    TSEG may require further work as the original did not appear exactly
    right to begin with. To have UMA as un-cacheable, use uma_resource().
    
    Change-Id: I4ca99b5c2ca4e474296590b3d0c6ef5d09550d80
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1239
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Tested-by: build bot (Jenkins)

commit 26e441f5bc381ec0fc476e4f78b4925a400c558c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jul 26 15:20:13 2012 -0700

    x86emu: fix comment for BTS instruction
    
    Change-Id: Iacce58945f66213e75c7aac89541e785e80664cb
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1363
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 911f446d32283676dee7546be4015dac25fe463b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jul 26 15:15:38 2012 -0700

    x86emu: Add an RDTSC implementation to the x86 emulator
    
    This instruction is being used in some debug VBIOSes.  This implementation
    doesn't even try to be accurate.  Instead, it just increments the counter by a
    fixed amount every time an rdtsc instruction in encountered, to avoid divides
    by zero.
    
    Imported from:
    http://cgit.freedesktop.org/xorg/xserver/commit/?id=c4b7e9d1c16797c3e4b1200b40aceab5696a7fb8
    
    Change-Id: I8fba1a060c57ccb7bbd44aa321dd349bc56bf574
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1362
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 08ef498d0bfd5d3cfaf70cdad1a8780d9dd2143e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 27 08:40:46 2012 +0300

    Intel 82810 and 82830: always room for PCI memory
    
    No need for the test, tomk is at most 1GB on these chipsets.
    Even if there was no room, adjusting the memory resource would not
    not divert accesses in the hardware from DRAM to PCI.
    
    Change-Id: I2213b8d9d2e6ab8da8fd3e8081cc62bb05b6b316
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1369
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit b5f5652e0f023cd89c1c21d7dc6dfb86cae9e727
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 27 08:40:14 2012 +0300

    Intel i945 and sch: no memory over 4GB
    
    No need for the test, tomk is top of low memory and always below 4GB.
    
    Change-Id: Ifc8f29268b761aa9b07b578673236a673f0c70b5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1368
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit ecf1ed49c72168c3d5b613a5d5198b5dd22777b4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 27 08:37:12 2012 +0300

    Allocators for different memory regions types
    
    Hide some details of the resource allocator from rest of the world.
    These should come in handy when fixing some aspects of MTRR setup.
    
    Change-Id: I8acad98f25e56cd8bae64fb52539d81ce94f9c73
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1367
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 19e99f5cf1659bc3731774087de3208b4a52fd2a
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jul 27 09:51:32 2012 +0200

    libpayload: Fix typo
    
    Change-Id: I8708703e497053aa1251f06402bd8ea59bd9d24e
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1370
    Tested-by: build bot (Jenkins)
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

commit 48fcb53c5d507ab421a5a5461722b610b6e40233
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jul 26 15:04:24 2012 -0700

    x86emu: Use NULL instead of 0 when assigning pointer
    
    Change-Id: Ie79b9aa79d45dd10c2e5be7f58eed970c243060a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1361
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d51f974e7bf9da57953b234e8600520c57c629ed
Author: zbao <fishbaozi@gmail.com>
Date:   Mon Jul 23 12:11:59 2012 +0800

    Re-run the git-describe if it fails at first try.
    
    Old rev (1.6.6, in my case) git-describe doesn't take the --dirty and says error.
    Remove the --dirty at second try.
    
    Change-Id: Id6c6f9889ab20fb7c2b238f8c0bbe20134757369
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1261
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 188e3c2ff06a82f61d7d71e610b32b1a250c0a45
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jul 26 12:46:48 2012 -0700

    Drop mainboard chip.h
    
    mainboard_config never worked right, at least not since we've had sconfig.
    Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that
    tried to use it anyways.
    
    Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1359
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit efff733ad83acf8502561a9cadc9202c6974e510
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Jul 26 19:48:23 2012 +0200

    Refactor driver structs
    
    Our driver infrastructure became more flexible recently.
    Make use of it.
    These are the low hanging fruits (files with 5 device
    variants or more), but there are still lots of files
    with less potential for deduplication.
    
    Change-Id: If6b7be5046581f81485a511b150f99b029b95c3b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1358
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 8730bf8aad995bf105454ac1a93dee4c7b5565d5
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 28 12:22:28 2012 -0700

    bd82x6x: Use CMOS variable if available for power-on on power failure
    
    We used a hard coded value for some reason. Don't do that, but use CMOS
    instead.
    
    Modelled after http://review.coreboot.org/#/c/443 to get bd82x6x in
    sync.
    
    Change-Id: I36d715310157b9f9074f2a1c80710f85833020b4
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1324
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7dc2864be7fcc342bab0c167997803f5faf147a1
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Jul 13 19:06:22 2012 +0200

    amd/lx: Move configuration from source to Kconfig
    
    LX has two values that are usually automatically derived but can
    be overridden, that were so far defined in each board's romstage.
    
    These values, along with the toggle to enable override are now
    part of LX's Kconfig. For boards that gave values but requested
    autogeneration, the values are removed.
    
    Further improvements: Figure out the various fields in PLLMSRlo
    and make them sensible Kconfig options (instead of the hex value
    it is now)
    
    Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1227
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1b3207ee617c24fd283e654359c20c88d95a69c8
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Jul 18 15:33:45 2012 -0700

    CTDP: Only do TDP down/nominal change from TNP0
    
    Otherwise there is a flurry of TDP changes with suspend/resume
    as the kernel powers devices off on suspend and brings them
    back online in resume.
    
    This also adds a mutex around the TDP operations since it is
    split across two methods and can't just rely on being Serialized.
    
    Change-Id: I7757d3ddad34ac985a9c8ce2fc202e2b2dcb2527
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1348
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8de884424cb65bdba80a5602e76a4e40b11b154f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 16 12:47:45 2012 -0700

    ELOG: Fix reporting of developer/recovery modes
    
    Recent changes in EC/Vboot/U-boot have completely broken
    the logging of developer and recovery modes.
    
    Recovery mode may not be in VBNV, so if that is zero and
    yet we are in recovery mode then assume it is there because
    the button/key was pressed.
    
    Since there may not be any actual developer mode switch
    we look if option rom is loaded and the system is not
    in recovery mode and consider that as developer mode.
    
    Change-Id: I70104877b24de477217e1ff5b3a019aef22343ec
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1346
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c1c9435863dd4bb22d06de486527d58b8a9e0170
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Jul 13 10:11:54 2012 -0700

    Log event for abnormal management engine status
    
    This will log if the ME is disabled or has an error.
    
    1) disable ME via EC console: gpioset PCH_HDA_SDO 1
    2) boot the device
    3) read eventlog with "mosys eventlog list"
    71 | 2012-07-13 10:10:55 | Management Engine | Disabled
    
    Change-Id: I9f6ee452d2aea76e6a5ea2cd50a50ff36245692a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1345
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 55864eff9218259335a776a139424c4d178cf14e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 16 12:27:42 2012 -0700

    ACPI: Add support for runtime config TDP down
    
    The required power MSRs are mirrored in MCHBAR so
    it is possible to configure TDP at runtime via ASL.
    
    This adds the required fields and a set of methods to
    configure "TDP down" and "TDP nominal".  It explicitly
    does not support "TDP up" at the moment.
    
    PSSS: method is added to assist in searching the _PSS
    table for the appropriate entry that corresponds to the
    desired max non-turbo ratio.
    
    STND: Set TDP Down from Nominal.  This will limit CPU to
    the TDP down configuration by sequencing the required
    changes in the right order.
    
    STDN: Set TDP Nominal from Down.  This will set the CPU
    back to nominal configuration by sequencing the required
    changes in the correct (reverse) order.
    
    This does not introduce any functional changes and must
    be paired with additional changes to be useful.
    
    The current configured TDP can be checked to see that
    the transition to/from a desired level is successful.
    
    > mmio_read8 0xfed15f50
    0x00  # TDP-Nominal
    
    > mmio_read8 0xfed15f50
    0x01  # TDP-Down
    
    Change-Id: I31a2f30cc9d134cc5eee980ae9288ae45e71c6e6
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1344
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 556321167f3a3b4f4b934d114aca759387fddfaa
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 16 12:19:00 2012 -0700

    CPU: Add option to set TCC activation offset
    
    The default TCC activation offset is 0, which means TCC
    activation starts at Tj_max.  For devices with limited
    cooling ability it may be desired to lower TCC activation.
    
    This adds an option that can be declared in the devicetree
    to set the TCC activation to a non-zero value.
    
    Enable tcc_offset=15 in devicetree.cb and build/boot
    the BIOS and check that the value is set in the MSR:
    
    > and $(shr $(rdmsr 0 0x1a2) 24) 0xf
    0xf
    
    Change-Id: I88f6857b40fd354f70fa9d5d9c1d8ceaea6dfcd1
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1343
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d6aca0b7b14780a03c83e283f940f56c474a77dd
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 16 12:14:49 2012 -0700

    ACPI: Add a method to notify OS to re-read _PPC
    
    Split this behavior out from PNOT() so the OS can
    update _PPC limit without re-reading C-state tables.
    
    Change-Id: I81b9111a4866f6b9916f74ac57a3caefaa77c565
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1342
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0eefa005030a70f5c691155b931bb778ad1fb2ae
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 16 12:11:53 2012 -0700

    ACPI: Add function to write _PPC using NVS
    
    The existing NVS variable for PPCM will be used to
    select a dynamic max P-state.
    
    By itself this does not change existing behavior because
    the NVS PPCM variable is initialized to zero.
    
    PPCM can be tested by building and booting a modified BIOS
    that sets gnvs->ppcm to a value greater than 1 and checking
    from the OS that the P-state is limited to that value.
    
    Change-Id: Ia7b3bbc6b84c1aa42349bb236abee5cc92486561
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1341
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 10d31aba76a0a0fd3fd79d32698c2634a4293add
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 16 11:28:52 2012 -0700

    NVS: Add a temp sensor ID and an ACPI Method to set it
    
    This will allow various teams to select which thermal sensor
    will control the thermal zones.
    
    Also add a method to notify the thermalzones of a change
    so these threshold/sensor methods take effect.
    
    Needs a modified BIOS that uses the NVS TMPS value in
    the thermalzone to read a different sensor.
    
    Then, use a kernel driver that contains the following:
    
    /* Adjust temperature sensor id to 2 */
    union acpi_object param;
    struct acpi_object_list input;
    param.type = ACPI_TYPE_INTEGER
    param.integer.value = 2
    input.count = 1;
    input.pointer = &param;
    acpi_evaluate_object(NULL, "\\TMPU", &input, NULL);
    
    And ensure that the temperature sensor that is being
    monitored switches to ID 2.
    
    Change-Id: I6319741358ba31eb8a3dc635d64f3f0acf683386
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1340
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 708f731fd76c3698b598b35469ae2fb20f08ae51
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jul 10 15:15:41 2012 -0700

    ME: Move ME v8 lockdown to finalize step
    
    The ME device was being sent EOP and the PCI device hidden during
    coreboot so it was not available in the SMI finalize step.
    
    This also flips the PCI vendor/device dword around for the match.
    
    Boot on Panther Point with serial and SMI debugging enabled and see
    that ME EOP message is sent and the device is hidden at end of
    U-boot and before the kernel loads.
    
    Finalizing Coreboot
    
    SMI# #0
    ME: mkhi_end_of_post
    ME: END OF POST message successful (0)
    PM1_STS: TMROF
    PM1_EN: 120
    
    Starting kernel ...
    
    Change-Id: I230038c62c50db2a1c94078c0a2a67bdc232440e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1338
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a0bec1745560492ec56d6149bcf3d3d0dcf3ccda
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Fri Jul 13 14:14:34 2012 -0600

    Reserve bd82x6x LPC decode ranges in the resource allocator
    
    The LPC bus normally allocates the range for legacy devices,
    0-0x1000. Some devices on LPC are above that range and need to
    be accounted for. Check the decode range settings for addresses
    > 0x1000 and reserve them.
    
    Change-Id: Idba800d7cee3185296f29dd237ba306f3de8de55
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1337
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1bb79bcf893d5abee14de4569e9230454116bfea
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 17:30:19 2012 -0700

    ELOG: Log run-time SMI southbridge events
    
    Events are logged for SMIs that trigger ACPI sleeps state
    entry and when the power button press triggers an SMI such
    as at the developer/recovery screens.
    
    Generate ACPI sleep state events and power button
    events and verify they show up in the log:
    
    153 | 2012-06-23 17:12:59 | ACPI Enter | S5
    184 | 2012-06-23 17:15:50 | ACPI Enter | S3
    216 | 2012-06-23 17:28:58 | Power Button
    
    Change-Id: Iba134d619780e459bce189d36d57844997ffb009
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1320
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cfb64bda83f5f47762845b8b6666783bae82ec34
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 16 16:16:31 2012 -0700

    SATA: Add option to configure gen3 transmitter
    
    Unfortunately the drive strength values are very much board
    specific and different between mobile and desktop so we don't
    try to do any fancy detection here but let it be specified
    directly in the devicetree.
    
    Change-Id: I66674bff0de04ecd088fb09afad1cf801a374df2
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/1347
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0920915bca2391ed318eeb12ddad8b7cb4a52905
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 17:25:29 2012 -0700

    ELOG: Support GSMI in CPT/PPT southbridge SMI handler
    
    In order to support the GSMI interface the SMI handler needs
    to find and use the state save area from the same CPU that
    initiated the SMI.  In this case it is a synchronous SMI
    resulting form an IO write to port 0xB2.
    
    To find the right CPU state save area iterate over the region
    until the "IO Misc Info" field reports the expected value and
    then proceed to use that state save area.
    
    This is needed because the coreboot SMI handler only executes on
    one core, and that core is non-deterministic.  It is likely that
    the core executing the C SMM handler is not the same one that
    actually did the IO write to 0xB2 and generated the SMI.
    
    The GSMI parameter buffer is passed as a pointer to EBX in the
    tate save area, and the GSMI command is extracted from EAX before
    it is used as the return value.
    
    This interface is tested by enabling CONFIG_GOOGLE_GSMI in the
    kernel and generating events and verifying that they end up
    in the event log.
    
    159 | 2012-06-23 16:22:45 | Kernl Event | Clean Shutdown
    184 | 2012-06-23 17:14:05 | Kernl Event | Oops
    185 | 2012-06-23 17:14:05 | Kernl Event | Panic
    
    Change-Id: Ic121ea69e9f50c88467c435e095c3e3629989806
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1317
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 38bd80d5a7320dc1b9277c00f18539cc4f878776
Author: zbao <fishbaozi@gmail.com>
Date:   Mon Jul 23 19:57:43 2012 +0800

    Add correct bios callout into read event routine
    
    Read event routine didn't get the correct BIOS callout. So it could not get
    the heap address. Then it would creat many warning in serial port.
    
    Change-Id: Ia35601bda1579c7f726ed767d7be78713ac185d2
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1266
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 035f1d2f14166aff3cd7d38b4174acc4945ba704
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jul 26 11:32:50 2012 +0200

    ibase/mb899: Rename NIC BIOS disable driver and hook up
    
    The board has a marvell NIC, but the driver to disable NIC BIOS was adapted
    from a Realtek 8168 driver. Rename to reflect the change.
    
    Also hook up as driver, so coreboot can actually find it.
    
    Change-Id: Ibdfd6074eb28ba537d68552a3346b06493cef2a6
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1355
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fce22e80d84f68b0421405e048d3f2f7c67025f3
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jul 26 11:34:57 2012 +0200

    Remove copies of rtl8168.c
    
    One copy was slightly different, but all the differences were commented out
    
    Change-Id: I3cc7b5621c681a1eb286f9b16ef3ebdce03abb6b
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1356
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 82704c63b98202fe2a24032697369cd190202d3f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jul 26 14:31:40 2012 +0200

    USBDEBUG: buffer up to 8 bytes
    
    EHCI debug allows to send message with 8 bytes length, but
    we're only sending one byte in each transaction. Buffer up
    to 8 bytes to speed up debug output.
    
    Change-Id: I9dbb406833c4966c3afbd610e1b13a8fa3d62f39
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1357
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit 0b7b7b6334de592b82d36ee47bc25b1b72043681
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 10 17:13:04 2012 -0700

    Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs
    
    On SandyBridge systems configured to work with Panther Point the CPU
    would wrongly be described as IvyBridge. Fix this issue and drop an
    unneeded Kconfig variable at the same time.
    
    Change-Id: I501a4fa00613e589cd315cfee61b2f9561dfcb4d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1335
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c65a36eb0f097ca13cdab8a787ce5cf35f49a64f
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 10 17:02:21 2012 -0700

    Enable Microcode in CBFS for all SandyBridge/IvyBridge systems
    
    Change-Id: Idee4facc18e0be60906d2a2f0e99bd39de8d7247
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1332
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 79bbbd9db36d93a8a8a1b9d27ef32a69991e6b30
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 16:48:38 2012 -0700

    ELOG: Add support for SMM and kernel GSMI driver
    
    The linux kernel contains an SMI driver that was written by
    me (Duncan) and upstreamed a couple years ago called GSMI.
    This driver will format a parameter buffer and pass pointers
    to this parameter buffer to the SMI handler.  It uses this to
    generate events for kernel shutdown reasons:  Clean, Panic, Oops,
    etc.
    
    This function expects to be passed pointers into the SMM state
    save area that correspond to the prameter buffer and the return
    code, which are typically EAX and EBX.
    
    The format of the parameter buffer is defined in the kernel
    driver so we implement the same interface here in order to be
    compatible.
    
    GSMI_CMD_HANDSHAKE: this is an early call that it does to try
    and detect what kind of BIOS is running.
    
    GSMI_CMD_SET_EVENT_LOG: this contains a parameter buffer that
    has event type and data.  The kernel-specific events are
    translated here and raw events are passed through as well which
    allows any run-time event to be added for testing.
    
    GSMI_CMD_CLEAR_EVENT_LOG: this command clears the event log.
    
    First the gsmi driver must be enabled in the kernel with
    CONFIG_GOOGLE_GSMI and then events can be added via sysfs
    and events are automatically generated for various kernel
    shutdown reasons.
    
    These can be seen in the event log as the 'Kernel Event' type:
    
    169 | 2012-06-23 15:03:04 | Kernl Event | Clean Shutdown
    181 | 2012-06-23 16:26:32 | Kernl Event | Oops
    181 | 2012-06-23 16:26:32 | Kernl Event | Panic
    
    Change-Id: Ic0a3916401f0d9811e4aa8b2c560657dccc920c1
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1316
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 62f1ad98c42f18308cda9351a427bb7af8d7dbca
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 24 14:53:15 2012 -0700

    SMM: Fix state table for Intel Core2 CPUs
    
    When fixing the SMM state table for SandyBridge/IvyBridge CPUs
    the wrong table was used for older 64bit capable CPUs.
    
    Change-Id: Ia7dff21aa3f0e5aa61575634fc839777de6bef10
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1353
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 54cba3b4ad743340de7462e0e5dcec76ee73baed
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 17:02:29 2012 -0700

    SMM: Skip locking SPI registers in finalize step
    
    This is a temporary workaround so the SPI bus can be accessed
    at runtime in SMM code until the SPI opcode menu is used
    properly.
    
    Change-Id: I93d188c55b66d8dce49fa91a1de53ee195944b30
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1318
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 800e950d646d687aa4231e8eced06a0615ba7344
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 17:06:47 2012 -0700

    ELOG: Log boot-time events found in southbridge
    
    This is called from the SMI handler install because those
    setup functions clear many of these registers.
    
    Ensure that these events show up in the log as appropriate.
    Example log output:
    
    159 | 2012-06-23 14:31:54 | SUS Power Fail
    160 | 2012-06-23 14:31:54 | System Reset
    161 | 2012-06-23 14:31:54 | ACPI Wake | S5
    
    Change-Id: I48c423c10ee7e6c2829bcc95f6cfabb4979c25a9
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1319
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 27e5aacc522a4ce97ffd8d57a93042d9703d70fe
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 17:33:30 2012 -0700

    ELOG: Log events for Chrome OS developer/recovery mode
    
    If a Chrome OS device is in developer mode log an event.
    When the device is in recovery mode also log an event
    and provide the recovery reason.
    
    Enable developer mode and trigger recovery mode and
    verify that the events are logged:
    
    238 | 2012-06-23 17:31:56 | Chrome OS Developer Mode
    239 | 2012-06-23 17:31:56 | Chrome OS Recovery Mode | User Requested from Developer Screen
    
    Change-Id: I14d41f44e04fd91340569617c7314da7e35a154f
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1321
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c0f2cfb0ac55eb476387b703cb561868f989c16e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 10 17:16:10 2012 -0700

    Fix comment to reference IvyBridge, too
    
    On both SandyBridge and IvyBridge BCLK is fixed at 100MHz. Have the
    comment reflect that.
    
    Change-Id: Ia81c3501dc3e68cf3143c3bc864dfbf88901f9f9
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1336
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6d29c7352f4d410f75e740f3dd13de813107f1bd
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jul 23 16:12:52 2012 -0700

    Include SandyBridge Microcode when IvyBridge is enabled
    
    .. in case the system has pluggable CPUs or might come in different SKUs.
    
    Change-Id: I7a7cd95b4de5dd78370355f448688e8d000434c1
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1333
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dcc17ae3702b942ef67ebe194d6e9e560de127ef
Author: zbao <fishbaozi@gmail.com>
Date:   Tue Jul 24 19:03:03 2012 +0800

    AMD parmer: Set correct azalia code verb table
    
    Change-Id: I0b10080deb971cdefa4d3916fabd40f5a81b11f4
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1352
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3726670edf1b6fef826b9f009d3be84af8d18805
Author: zbao <fishbaozi@gmail.com>
Date:   Tue Jul 24 17:59:43 2012 +0800

    AMD family15tn: Add BIOS callback hook for getting VBIOS Image
    
    This is for GfxInitSview(GnbSview.c). It would create warning message if it
    could not get VBIOS image.
    
    Change-Id: I3b2726f612b4b7a237644a4b63b56efad52b7ab5
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1351
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a36d8b38a673f8792df0e36c94ef571b08b229b5
Author: zbao <fishbaozi@gmail.com>
Date:   Tue Jul 24 17:58:30 2012 +0800

    AMD Family 15tn: Set the default return value as AGESA_SUCCESS instead of TRUE
    
    The default return value should be AGESA_SUCCESS, which is zero. If it was set as TRUE,
    the AGESA wrapper would think it was AGESA_UNSUPPORTED. That would make no sense. And it
    would produce ASSERT warning in AGESA wrapper.
    
    On my parmer board, with Engine sample processor, it can not create the correct DMI table.
    Routine initlate will return AGESS_ERROR.
    ------Serial message---------
    ASSERTION FAILED: file 'src/mainboard/amd/parmer/agesawrapper.c',  line 427
    DmiTable:100123c3, AcpiPstatein: 10010126, AcpiSrat:0,AcpiSlit:0, Mce:100111ba, Cmc:1001127c,Alib:1001ccd4, AcpiIvrs:0 in agesawrapper_amdinitlate
    agesawrapper_amdinitlate failed: 5
    -----------------------------
    I believe the processor with acceptable name string will create the right DMI.
    
    Change-Id: Ie86955cf9affffc964a7c9f4a2c63077ef2030de
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1350
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 19a185448a40461d0df53e907a80ed1814695e5e
Author: zbao <fishbaozi@gmail.com>
Date:   Tue Jul 24 17:56:48 2012 +0800

    AMD Family15tn: Set the mask of MTRR to 0000FFFXX0000800
    
    Remove the warning message from linux dmesg,
    mtrr: your BIOS has configured as incorrect mask, fixing it.
    
    Change-Id: I355509db12ab10c33b7c1c23e2c7c4783f30e67e
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1349
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 405cfe219a77895692aa50a1e8416c2607402c39
Author: zbao <fishbaozi@gmail.com>
Date:   Mon Jul 23 19:44:29 2012 +0800

    Change multiply ONE_MB to bit shifting.
    
    2048 * ONE_MB will cause warning,
    src/northbridge/amd/agesa/family15tn/northbridge.c:667:50: warning: integer overflow in expression [-Woverflow]
    I guess it will change the data type to signed integer.
    I think the bit shifting is better.
    
    Change-Id: I823f7ead1f7d622bf653cb3bf2ae2343f5e76805
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1263
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ace7a6aadd9bc07de1e7570ef973ad25bdae577e
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 15:29:59 2012 -0700

    SMM: rename tseg_fixup to tseg_relocate and export
    
    This function is exported so it can be used in other
    places that need similar relocation due to TSEG.
    
    Change-Id: I68b78ca32d58d1a414965404e38d71977c3da347
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1310
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0aa5b0923a1e11a4db659ecb4706eb69b4a9e606
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 10 17:06:22 2012 -0700

    Fix date output in Microcode update
    
    Date and time are mixed up:
    microcode: updated to revision 0x12 date=2012-12-04
    should be
    microcode: updated to revision 0x12 date=2012-04-12
    
    Change-Id: I85f9100f31d88bb831bef07131f361c92c7ef34e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1334
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit e6f459ca4b24d0f6dc07c2dd6a5278543c0c745d
Author: Kimarie Hoot <kimarie.hoot@se-eng.com>
Date:   Sat Jul 14 08:26:08 2012 -0600

    CougarPoint/PantherPoint: Add HM77 device ID to table
    
    Change-Id: Ic5aada423d8e61abbebfcaaf5cb02ede80dfae02
    Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1339
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit ac3aa096c9c2845cfcab7f7fbe50cc56f92a7264
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Wed Jul 25 13:42:40 2012 +0200

    Extend smbios api to allow runtime change of mainboard serial and version
    
    This patch extends the current smbios api to allow changing mainboard
    serial and version during coreboot runtime. This is helpful if you
    have an EEPROM etc. to access these informations and want to add
    some quirks for broken hardware revision for the linux kernel.
    This could be done via DMI_MATCH marco.
    
    Change-Id: I1924a56073084e965a23e47873d9f8542070423c
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/1232
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 594473d75aad888ca4eb7d74adb926a4ffcb7963
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Jul 25 08:55:53 2012 +0200

    Remove useless semicolon
    
    Change-Id: Idc4d5737f5b49108987ca7fe90410d4e80b723f2
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1354
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-by: Mathias Krause <minipli@googlemail.com>
    Tested-by: build bot (Jenkins)

commit be1ef2329e21a2d9bc1b83e23769346832de2d81
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 13 13:12:19 2012 -0700

    chromeos: Pass pointer to ChromeOS ACPI structure instead of VB Shared Data
    
    coreboot used to pass some information to u-boot in the coreboot table
    and other information in a modified flat device tree. Since the FDT code
    was never upstreamed and removed from our tree, u-boot was changed to
    get the information it needs from the coreboot table alone. However,
    in the process of this change only the vboot shared data structure was
    passed on by coreboot, so when u-boot tried to update the ChromeOS
    specific ACPI entries, it would accidently overwrite the vboot data.
    This patch passes on the ChromeOS specific ACPI data structure instead
    of the vboot shared data. Another change to u-boot will teach it how
    to get to the vboot shared data from there.
    
    Change-Id: Ifbb64eafc0d9967887b4cdeebf97d0c4ce019290
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1282
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d59d62484db7020c12438d2e7e308c81e46a4c9e
Author: zbao <fishbaozi@gmail.com>
Date:   Mon Jul 23 19:41:03 2012 +0800

    sync the northbridge.c with other family.
    
    Change-Id: Ice4d0202590fca0169dcda2770ca6add166b5c13
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1262
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8d32b89fa4ea30aa57b578d79bc656c9e6545795
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 10 13:24:29 2012 -0700

    Fix LAPIC timer on Ivy Bridge systems
    
    The LAPIC timer is running at BCLK (100MHz) on Sandy Bridge and Ivy
    Bridge systems. However, the current timer code assumed that the clock
    would run at 200MHz instead. This made all delays twice as long as
    needed.
    
    Change-Id: I41b1186daee11cfd9a25b3a9d5ebdeeb271293c7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1330
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit f4d362339f4d96657be1dc5956c34278d1089eba
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 16:37:45 2012 -0700

    ELOG: Add support for a monotonic boot counter in CMOS
    
    This maintains a 32bit monotonically increasing boot counter
    that is stored in CMOS and logged on every non-S3 boot when
    the event log is initialized.
    
    In CMOS the count is prefixed with a 16bit signature and
    appended with a 16bit checksum.
    
    This counter is incremented in sandybridge early_init which is
    called by romstage.  It is incremented early in order notice
    when reboots happen after memory init.
    
    The counter is then logged when ELOG is initialized and will
    store the boot count as part of a 'System boot; event.
    
    Reboot a few times and look for 'System boot' events in the
    event log and check that they are increasing.  Also verify
    that the counter does NOT increase when resuming from S3.
    
    171 | 2012-06-23 16:02:55 | System boot | 285
    176 | 2012-06-23 16:26:00 | System boot | 286
    182 | 2012-06-23 16:27:04 | System boot | 287
    189 | 2012-06-23 16:31:10 | System boot | 288
    
    Change-Id: I23faeafcf155edfd10aa6882598b3883575f8a33
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1315
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 472ec9cd7ecb3d283bc05941c7dbb54a10813614
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 16:13:42 2012 -0700

    ELOG: Add support for generating SMBIOS type15 table
    
    This standared SMBIOS 0able describes the location and format
    of the event log to the OS and applications.  In this case the
    pointer is a 32bit physical address pointer to the log in
    memory mapped flash.
    
    Look for SMBIOS type15 entry with 'dmidecode -t 15'
    
    Handle 0x0004, DMI type 15, 23 bytes
    System Event Log
            Area Length: 4095 bytes
            Header Start Offset: 0x0000
            Header Length: 8 bytes
            Data Start Offset: 0x0008
            Access Method: Memory-mapped physical 32-bit address
            Access Address: 0xFFB6F000
            Status: Valid, Not Full
            Change Token: 0x00000000
            Header Format: OEM-specific
            Supported Log Type Descriptors: 0
    
    Change-Id: I1e7729e604000f197e26e69991a2867e869197a6
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1314
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 696262bd99fb7e4177dbce533ae50a287871d830
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jun 18 14:38:40 2012 -0700

    More descriptive error messages in Sandybridge raminit code
    
    MRC returns specific error codes; print the according error
    message if we know what it means.
    
    Change-Id: Iaaf1512b9d577d4291fccfb94d879043ab5b11b5
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1289
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0c32c9795b1cb2270f677e55ba38e7d293e723ee
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 10 13:26:59 2012 -0700

    bd82x6x: Drop unneeded pci_dev_t
    
    This was introduced when porting the SPI driver over from u-boot but it
    is not needed. Hence drop the extra typedef and use device_t instead.
    
    Change-Id: I3ab797a8e482d1c9aa1d004e488e99aeaffcdd8b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1331
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 9c4c6ab0c895a35d6bad33ecb2cb7f40eea98001
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Jun 29 15:38:02 2012 -0700

    ELOG: Fix boot count increment for non-wake case
    
    The count was only incrementing for a wake from S5 and
    it was not incrementing in the normal reboot case.
    
    Change-Id: I73bc6db6bd02e6c4677f7e44a5c098c6dcb51747
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/1328
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fe7b5d2fa6705a2b553244dda0452ca55c5730a2
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 20:14:07 2012 -0700

    Ivybridge: fix workaround and enable PAIR
    
    MCHBAR 0x5f10[7:0] should be set to 0x30 for ivybridge
    and 0x20 for sandybridge.  Move this code to ramstage
    and set it per-chipset.
    
    Power Aware Interrupt Routing is supported in ivybridge,
    enable it and set fixed priority.
    
    Boot on ivybridge device and read MCHBAR 0x5f10:
    
    mmio_read8 0xfed15f10
    0x30
    
    And verify PAIR is enabled (bit4=1):
    
    mmio_read8 0xfed15418
    0x24
    
    Change-Id: If017d5ce2bd5ab5092c86f657434f2b645ee6613
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1303
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 22935e1f43c2b0873dfa9b5f176df5616ce7a041
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 9 09:58:35 2012 -0700

    CPU: Set flex ratio to nominal TDP ratio in bootblock
    
    CPUs with configurable TDP will run the TSC at the max non-turbo
    ratio for the maximum TDP value, which can cause issues if another
    TDP is desired.  To deal with this we set the flex ratio to the
    nominal TDP ratio early in the boot and then configure the Soft
    Reset Data registers so the PCH can tell the CPU what frequency
    to run at after a reset.
    
    This is done very early in the bootblock because it is necessary
    to reset the system after setting a flex ratio.
    
    The end result is that the TSC will now increment at the max
    non-turbo frequency for the nominal TDP.
    
    On some system with 1.8GHz CPU ensure that the kernel
    detects the CPU speed as ~1800mhz rather than ~2300mhz:
    
    > dmesg | grep "MHz processor"
    [    0.004000] Detected 1795.801 MHz processor.
    
    Change-Id: I8436dced9199003b6423186a2b041e3f7b84ab8c
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/1329
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 51cb26d92a2ddac8d71fe0e5970ed208110add71
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 15:22:43 2012 -0700

    SMM: Fix state save map for sandybridge and TSEG
    
    There are enough differences that it is worth defining the
    proper map for the sandybridge/ivybridge CPUs.  The state
    save map was not being addressed properly for TSEG and
    needs to use the right offset instead of pointing in ASEG.
    
    To do this properly add a required southbridge export to
    return the TSEG base and use that where appropriate.
    
    Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1309
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 181bbdd51cb4ec318e8b44c1ca652310bf6abb22
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 16:53:57 2012 -0700

    SMM: Add option for SPI driver to be available in SMM
    
    - add Kconfig option for CONFIG_SPI_FLASH_SMM
    - compile subsystem and chip drivers for smm if enabled
    - change mdelay(1) to udelay(500) since mdelay is not defined
      in SMM and a 1ms delay is worth avoiding
    - make flash chip structure non-const so the probe function
      pointers can be relocated for use in TSEG
    - Make SMM PCI access possible in southbridge SPI code
    
    Change-Id: Icfcbbe8e4e56658769d46af0b5bf6c79a6432641
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1313
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f5e9ac48c65bba2876d1dd7f103cd15c5e33c7df
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 13:33:32 2012 -0700

    SMM: Add support for malloc in SMM if using TSEG
    
    This is used by the SPI driver and ELOG.
    
    It requires SMM TSEG and a _heap/_eheap region defined in the
    linker script.  The first time malloc is called in SMM the
    start and end pointers to the heap region will be relocated
    for the TSEG region.
    
    Enable SPI flash and ELOG in SMM and successfully
    allocate memory.  The allocated addresses are verified
    to be sure they are within the TSEG heap region:
    
    smm.elf:00014000 B _eheap
    smm.elf:00010000 B _heap
    TSEG base is 0xad000000
    
    Memory allocated in ELOG:
    ELOG: MEM @0xad018030
    
    Change-Id: I5cca38e4888d597cbbfcd9983cd6a7ae3600c2a3
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1312
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7d2b81c18d891a11420088c37cb17bb1c8d73ba9
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 16:08:47 2012 -0700

    ELOG: Add support for flash based event log
    
    This is based around the SMBIOS event log specification but
    expanded with OEM event types to support more specific and
    relevant system events.
    
    It requires flash storage and a minimum 4K block (or flash block
    size) that should be allocated in the FMAP.
    
    A copy of the event log is maintained in memory for convenience
    and speed and the in-memory copy is written to flash at specific
    points.
    
    The log is automatically shunk when it reaches a configurable
    full threshold in order to not get stuck with a full log that
    needs OS help to clear.
    
    ELOG implements the specification published here:
    http://code.google.com/p/firmware-event-log/wiki/FirmwareEventLogDesign
    
    And is similar to what we use in other firmware at Google.
    This implementation does not support double-buffered flash
    regions.  This is done because speed is valued over the log
    reliability and it keeps the code simpler for the first version.
    
    This is a large commit and by itself it just provides a new
    driver that is made available to coreboot.  Without additional
    patches it is not very useful, but the end result is an event
    log that will contain entries like this:
    
    171 | 2012-06-23 16:02:55 | System boot | 285
    172 | 2012-06-23 16:02:55 | EC Event | Power Button
    173 | 2012-06-23 16:02:55 | SUS Power Fail
    174 | 2012-06-23 16:02:55 | System Reset
    175 | 2012-06-23 16:02:55 | ACPI Wake | S5
    
    Change-Id: I985524c67f525c8a268eccbd856c1a4c2a426889
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1311
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d2e00b92ce0d3b60b7467ff51d3184d9c57dcb10
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 15:09:34 2012 -0700

    SMM: Add heap region and move C handler higher in region
    
    In order to support SPI and ELOG drivers the SMM region
    needs to be able to be larger than the previous allocation
    below 0x7400.  Now that we have support for 4M TSEG we do
    not need to live in this region.
    
    This change adds a 16KB heap region abofe the save state area
    at TSEG+64KB and moves the C handler above this.
    
    The heap region is then available for malloc and the C handler
    can grow to support flash and event log features.
    
    While updating the memory map comment in assembly stub I also
    added a pause instruction to the cpu spin lock as this was
    added to the C code in latest upstream rebase.
    
    Dump sympbols from smm.elf binary to see the new regions:
    
    00010000 B _heap
    00014000 B _eheap
    00014000 T _smm_c_handler_start
    0001b240 T _smm_c_handler_end
    
    Change-Id: I45f0ab4df1fdef3b626f877094a58587476ac634
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1308
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4e4320f524a4695b5987e6bbffcfc48af89dac26
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 25 09:53:58 2012 -0700

    CPU: Update ivybridge PP1 current limit value
    
    The BWG says ivybridge current limit for PP1 is 50A.
    
    Verify the PP1 current limit value on link device:
    
    > echo $(( ( $(rdmsr 0 0x602) & 0x1fff ) >> 3 ))
    50
    
    Change-Id: I946269d21ef605f2525fe03993f569d69128294b
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1305
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 77dbbac7e710c279c8208a5e5f5e766ef4565524
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 25 09:51:59 2012 -0700

    CPU: Add basic support for Nominal Configurable TDP
    
    Ivybridge B0+ CPUs are capable of supporting multiple TDP levels.
    This complicates the default case because now the registers that
    were reporting max non-turbo ratio are reporting that value for
    the highest possible TDP level.
    
    For now this change just forces everything to use the Nominal TDP
    values instead of the higher (or lower) levels.
    
    - When building P-state tables, determine the P[1] (max non turbo)
    ratio based on the Nominal ratio if available.
    - Set the turbo activation ratio to the Nominal max ratio.
    - Mirror the power level settings in new MCHBAR register after
    they are written, which happens after BIOS_RESET_CPL is set.
    - Set the current ratio to Nominal ratio at boot.
    
    1) Verify that P-state table is generated properly with
    P[0]=1801MHz (ratio 0x1C) and P[1]=1800MHz (ratio 0x12)
    
    PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00
    PSS: 1800MHz power 17000 control 0x1200 status 0x1200
    
    2) Verify power limits in MCHBAR match PKG_POWER_LIMIT:
    
    > rdmsr 0 0x610
    0x800080aa00dc8088
    > mmio_read32 0xfed159a4
    0x000080aa
    > mmio_read32 0xfed159a0
    0x00dc8088
    
    3) Verify turbo activation ratio is set to nominal ratio:
    
    > rdmsr 0 0x64c
    0x0000000000000012
    
    4) Check that proper ratio was set at boot on one core only:
    
    > grep 'frequency set to' /sys/firmware/log
    model_x06ax: frequency set to 1800
    model_x06ax: frequency set to 1800
    model_x06ax: frequency set to 1800
    model_x06ax: frequency set to 1800
    
    Change-Id: I592e60a7740f31b140986a8269dca91b4adbb270
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1304
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b91a0f2b83ac7816dc28cac8d3ae13a7d5576864
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Jun 15 15:34:24 2012 -0700

    Rename cache_lbmem() to cache_ramstage()
    
    ... and don't require it to specify a cache type.
    This function is only used on romcc boards, and should go away
    (because all boards should be switched to CAR)
    
    Change-Id: Ic32ca3be1afffc773c72c140e88b338d48a0c8ca
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1288
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9764d4c690bbe4a54429e47a2094230da5fb88f5
Author: Ronald G. Minnich <rminnich@chromium.org>
Date:   Tue Jun 12 16:29:32 2012 -0700

    Implement stack overflow checking for the BSP
    
    Previous patches implemented stack overflow checking for the APs.
    This patch builds on the BSP stack poisoning patch to implement
    stack overflow checking for the BSP, and also prints out maximum
    stack usage. It reveals that our 32K stack is ridiculously oversized,
    especially now that the lzma decoder doesn't use a giant 16K on-stack
    array.
    
    Break the stack checking out into a separate function, which
    we will later use for the APs.
    
    CPU0: stack from 00180000 to 00188000:Lowest stack address 00187ad8
    
    To test failure, change the DEADBEEF stack poison value in c_start.S
    to something else. Then we should get an error like this:
    Stack overrun on BSP.Increase stack from current 32768 bytes
    CPU0: stack from 00180000 to 00188000:Lowest stack address 00180000
    
    Separate the act of loading from the act of starting the payload. This
    allows us better error management and reporting of stack use. Now we
    see:
    CPU0: stack from 00180000 to 00188000:Lowest stack address 00187ad8
    
    Tested for both success and failure on Link. At the same time, feel free
    to carefully check my manipulation of _estack.
    
    Change-Id: Ibb09738b15ec6a5510ac81e45dd82756bfa5aac2
    Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/1286
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9842ad8ac5256d1800490c392b8cf7e4edd21ddc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 13 16:31:50 2012 -0700

    Fix automatic ME detection in finalize
    
    The ME needs to be talked to through the PCIe memory mapped config
    space.
    
    Change-Id: Ic2c5a572a126722a08a82d95df13d11507586c6b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1284
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a306ad701e88089749deba9f1e48ed6e05bca5cc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 13 13:17:03 2012 -0700

    ChromeOS: Remove board specific acpi_get_vdat_info()
    
    The function acpi_get_vdat_info() was moved to the ChromeOS
    vendor code, and is no longer required to be present for each
    board. Hence, remove it.
    
    Change-Id: I3dc8dbb6119ceffa057373bad7c0058ac0d40eb8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1283
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 998f3a27be2a16ae0bc1f193a805b680208d63ab
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jun 11 15:15:46 2012 -0700

    Cougar/Panther Point: Compile in ME7 and ME8 code at the same time
    
    In the short term there might be devices with Sandy Bridge CPUs
    on mainboards with Panther Point PCHes. While this configuration
    option is perfectly valid, coreboot currently ties Sandy Bridge to
    Cougar Point and Ivy Bridge to Panther Point. One occurence is in
    the ME handling code.
    
    To make coreboot most flexible, compile both ME handlers into
    coreboot and decide at runtime which one to use.
    
    Change-Id: Icffe2930873f67c99c3f73e37e7a967f4f002b88
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1280
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 49058c0adf348342ea23711f018997816da4056b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jun 11 14:13:09 2012 -0700

    Fix ME hash functions on Panther Point/Cougar Point
    
    - On Cougar Point there may have been stack corruption during the
      ME hash verification
    - On Panther Point the ME firmware hash was not passed on to the
      OS
    
    Change-Id: I73fc10db63ecff939833fb856a6da1e394155043
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1279
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 999e94cb7a428751cf11be6859dbf29f954bbdc3
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Jun 19 04:20:20 2012 +0000

    Config changes to support microcode in CBFS
    
    Nothing is yet enabled, this is just a config skeleton change.
    
    The MICROCODE_INCLUDE_PATH definition is going to be used by the
    Makefile building the microcode blob for CBFS inclusion.
    
    Change-Id: I7868db3cfd4b181500e361706e5f4dc08ca1c87d
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1292
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 48c6bae1f2cc1dc1996c36986b7a87273f48b64e
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Mon Jul 2 22:31:22 2012 -0600

    Add BAR address debug information to Oxford PCIe serial driver
    
    The Oxford PCIE Serial card has a hardcoded address at setup,
    which may be moved during PCI Init. The driver re-initializes
    after PCI init. Add a debug print for the new BAR address.
    
    Initializing Oxford OXPCIe952
    OXPCIe952: Class=70002 Revision ID=0
    OXPCIe952: 2 UARTs detected.
    OXPCIe952: Uart Bar: 0xe0800000
    
    Change-Id: I1858d3eba09749cba3c3869060d00e621dca112a
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1327
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 39fea6e2a87aa79e6b156c96f0b2ba3ae9a35ba2
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Jun 19 08:34:51 2012 -0700

    Add microcode blob processing
    
    When microcode storage in CBFS is enabled, the make system is supposed
    to generate the microcode blob and place it into the generated ROM
    image as a CBFS component.
    
    The microcode source representation does not change: it is still an
    array of 32 bit constants. This new addition compiles the array into a
    separate object file and then strips all sections but data.
    
    The raw data section is then included into CBFS as a file named
    'microcode_blob.bin' of type 0x53, which is assigned to microcode
    storage.
    
    Change-Id: I84ae040be52f520b106e3471c7e391e64d7847d9
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1295
    Tested-by: build bot (Jenkins)

commit 537b4e09e644107ed644cd88f8a7fd488406b9a2
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Jun 19 12:56:57 2012 -0700

    Add code to read Intel microcode from CBFS
    
    When CONFIG_MICROCODE_IN_CBFS is enabled, find the microcode blob in
    CBFS and pass it to intel_update_microcode() instead of using the
    compiled in array.
    
    CBFS accesses in pre-RAM and 'normal' environments are provided
    through different API.
    
    Change-Id: I35c1480edf87e550a7b88c4aadf079cf3ff86b5d
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1296
    Tested-by: build bot (Jenkins)

commit ef6b08cc486e5d97103211dfeb3d629552a92e43
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Fri Jun 15 23:03:15 2012 -0600

    Add PCIe port disable debug message
    
    The PCIe device enable function prints when it disables a device.
    The PCIe ports(bridges) use a different routine that didn't print
    the message. Add it to be consistent and to provide better debug
    output.
    
    Change-Id: I8462c48e7f4930db68703f0bfb710c01c9643a98
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1326
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit d81744ea86b8f73bc404841e51aa1cf8d45ee9fb
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jun 25 14:12:58 2012 -0700

    Make MAX_PHYSICAL_CPUS invisible on non-AMD boards
    
    It's only used on AMD based boards. Hence drop it, so we don't
    accidently start using it by mistake instead of MAX_CPUS
    
    Change-Id: Id8f522f24283129874d56e70bd00df92abe9c3cf
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1325
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9d3e832c727a01350430f08253f1ea0eb51bf73d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 28 12:18:41 2012 -0700

    bd82x6x: Support power-on-after-power-fail better
    
    Changing CMOS value for power-on-after-power-fail was only honored
    after reboot, which is counter intuitive (set from "enable" to
    "disable",
    power-off, replug device -> device turns on; and similar cases).
    
    Modelled after http://review.coreboot.org/#/c/444
    
    Change-Id: I2b8461dff1ae085c1ea4b4926084268b4da90321
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1323
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit df0c8222398f3e0f4334777fb14c6a344c069813
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Jun 19 05:25:41 2012 +0000

    Rename microcode include file to be model agnostic
    
    In preparation to support CBFS hosted microcode blobs, this change
    renames the wrapper include file containing the microcode to be
    independent of CPU model.
    
    Change-Id: If1a4963a52e5037a3a3495b90708ffc08b23f4c1
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1294
    Tested-by: build bot (Jenkins)

commit 8bdbddfeeaec5f0eb16a1d77af6ec860a62f4e01
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Jun 19 04:56:24 2012 +0000

    Fix function generating GPIO state based vector
    
    The function was too eager shifting stuff around, this change corrects
    the problem.
    
    Change-Id: I4c13dbe86cb627835dae05bb74af9867c28e143d
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1291
    Tested-by: build bot (Jenkins)

commit 6097e193fc708942931fd60ad40d40e95550ecb0
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jun 11 15:38:15 2012 -0700

    Make ACPI code detect Sandy/Ivy Bridge dynamically
    
    On systems with socketed CPUs we want to be able to
    drop in a Sandy Bridge or Ivy Bridge CPU without recompiling the
    firmware. Hence, detect the north bridge dynamically. In order
    for this to work, we need Ivy Bridge MRC and coreboot configured
    for Ivy Bridge.
    
    Change-Id: I635bef2c61d47d36a3fdd87f8ecb6e69097ba969
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1281
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3a8cad3c146265ec614ac8623cf6db94d0ab2ed3
Author: Ronald G. Minnich <rminnich@chromium.org>
Date:   Tue Jun 5 15:13:21 2012 -0700

    Shrink the stack sizes we need in coreboot
    
    We accomplish this goal by getting rid of the huge auto array in the
    ram stage. This will in turn let us reduce CONFIG_STACK_SIZE.
    
    We have to leave it on the stack in CAR as that's the simple way to
    keep it private. It does not matter then as there is only one core
    that is active.
    
    Change-Id: Ie37a057ccae088b7f3bb4aab6de2713e64d96df6
    Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/1271
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3f6a4d71647ebd7484c1c40be4c909d3c183e4fa
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Jun 28 13:03:40 2012 -0700

    Add specific power management init code for PantherPoint
    
    There are enough subtle differences in the magic values that
    it is easier to make a separate function.
    
    This fixes a reset hang with pantherpoint chipset.
    
    Change-Id: I02b03cb37e5fd5ee2fd62067644f0a62dc2cd26a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1322
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit afcaac2db512c5868db81e2dc038b5ae19ec8b71
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jun 18 15:43:50 2012 -0700

    Drop (empty) sandybridge_late_initialization()
    
    The function is empty (a left-over from i945) and should be removed.
    
    Change-Id: I91e573b5e37cb9133ea1037aef7e6daf3c292864
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1290
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b405857befbc20dd0be39c1cb6293cea4974fb39
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jun 25 10:39:21 2012 -0700

    Remove CMOS Extended range enable from romstage
    
    This enable step has been moved to the bd82x6x bootblock.
    
    For Samsung Stumpy and Lumpy mainboards and the
    Intel EmeraldLake2 reference board.
    
    Change-Id: I5ce54f57b8e1dd732c8a5ae71d7511703de91a0e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1307
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 8e515d36b467a1457bab8947ccf4ddf61a85ac8f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 15:43:41 2012 -0700

    RTC: Enable extended CMOS in the bootblock
    
    This makes it available early in romstage without having to
    worry when the different romstagse enable it.
    
    Check for extended CMOS to be enabled in early romstage.
    
    This is used by a later commit which uses the extended
    CMOS region for stoage.
    
    Change-Id: I9e026d48499c63d6503c2b020d4cc3047126fa93
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1306
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9a380abaa2c96c9e937327a43e13d700c722df6d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Jun 22 13:16:11 2012 -0700

    bd82x6x: Convert all PCI ID lists to new scheme
    
    - Convert all PCI ID lists to new scheme
    - Unify code (variable names)
    - add missing PCI IDs for Panther Point PCIe root ports.
    
    Change-Id: I6357f6ebce7ddffe45a3ec642b0c594147f6134c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1301
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit baae2d2761bee15e80f37e8e8ee400c7504a987c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 21 16:05:21 2012 -0700

    Add support for HM70 and NM70 LPC bridge
    
    This lets the SPI driver and the LPC driver know about HM70 and NM70.
    
    Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1300
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b5dfcae09728d38d8049e348a2b7654087b3a734
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Fri Jul 20 10:21:29 2012 +0200

    cs5536: add smbus support in ramstage
    
    With this patch it is possible to use the smbus in ramstage. The
    biggest part of the patch is a simple code split into a general
    part (smbus.h) and the concrete users (early_smbus.c and cs5536.c).
    After the switch from romstage to ramstage the smb base address
    has changed, but that is no problem as the new base address is
    stored in bar0 of the ISA bridge. It could also be read via msr,
    but via PCI it is simpler. I used the following patch as
    reference on how to readout the new base address:
    http://lists.laptop.org/pipermail/commits-kernel/2006-November/000178.html
    
    Change-Id: I9f86a1e474368c62f9ed3a95edfb3e63117aa156
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/1243
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fa418e3c66ca1728f41bd5811a77dcb14253441c
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Wed Jun 13 20:48:36 2012 -0600

    Add uartmem_init prototype.
    
    The oxpcie ramstage code calls uartmem_init after the PCI memory
    allocation, but hte function was static and didn't have a prototype.
    
    Change-Id: Iabc1a3d248aeaed29aaaa22504defac97c572326
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1285
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c8c836f58e9bbfbddda800fd98c2de42642af1a5
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Sat Jun 23 13:22:25 2012 -0700

    RTC: Add defines for standard clock offsets
    
    ELOG reads from RTC to build timestamp structure,
    the resulting timestamp is decoded when printing events.
    
    Change-Id: If26552074f18de5095b967b875a0ac1d815a5b31
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1302
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 542e9628aed98aa08674b47a69647c402fa0833e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jun 18 11:26:25 2012 -0700

    Print PCI ID of PCH during boot up
    
    Right now, if we have an unknown PCH, coreboot will print something like
    this:
    
    PCH type: Unknown rev id 4
    
    Instead, it should also print the PCI ID of the device, so we can add it
    to the list of known PCHes.
    
    Change-Id: Ib0b96e287c36d2895d1287b1734ca13d75e7985a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1287
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a9f670a7605de204578be88067d51c832becb652
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jun 18 16:02:20 2012 -0700

    ifdtool: Use perror for file write errors
    
    The "Error while writing." error messages did not output a new line
    which made the output look weird. With this patch, it should look like
    this:
    
    $ ifdtool -x 3rdparty/mainboard/google/parrot/descriptor.bin
    File 3rdparty/mainboard/google/parrot/descriptor.bin is 4096 bytes
    Found Flash Descriptor signature at 0x00000010
    Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
    Flash Region 1 (BIOS): 00200000 - 007fffff
    Error while writing: Bad address
    Flash Region 2 (Intel ME): 00001000 - 001fffff
    Error while writing: Bad address
    Flash Region 3 (GbE): 00fff000 - 00000fff (unused)
    Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
    
    Change-Id: I784ff72d0673f167dbf0bd10921406abd685ce72
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1299
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit c6643870829d613d136dac82ae0cd4ab3cbf53c2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jun 18 15:48:34 2012 -0700

    Drop leading spaces from CPU name string
    
    This is as per Intel's suggestion on how to display their name strings.
    
    Change-Id: Ie82341305e58baa8041e50a61a11b395fa7d9582
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1298
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit b38e0c3509d15d2be88bf194b637064bb1e80075
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Jun 20 14:38:53 2012 -0700

    Properly identify ACPI C3 states in _CST table.
    
    Dump and disassemble ACPI tables and look in _CST.
    
    In the last entry the state was getting set to 0:
    
    Package (0x04)
    {
      ResourceTemplate ()
      {
        Register (FFixedHW,
                  0x01,               // Bit Width
                  0x02,               // Bit Offset
                  0x0000000000000030, // Address
                  0x01,               // Access Size
                  )
      },
      0x00000000,                     // State
      0x0000005A,                     // Latency
      0x000000C8                      // Power
    }
    
    Now it is properly identifed as state 3:
    
    Package (0x04)
    {
      ResourceTemplate ()
      {
        Register (FFixedHW,
                  0x01,               // Bit Width
                  0x02,               // Bit Offset
                  0x0000000000000030, // Address
                  0x01,               // Access Size
                  )
      },
      0x00000003,                     // State
      0x0000005A,                     // Latency
      0x000000C8                      // Power
    }
    
    Change-Id: Ie0a68606c5a43ac5fb5ba7bb9a3fef933ad67b64
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/1297
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 52e61183cc98d132754970112592e0ebe1605d42
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 6 13:42:09 2012 -0700

    Remove unused free() function
    
    Since coreboot is running very short, we don't free memory.
    Hence, drop (dummy) free()
    
    Change-Id: I6e2737f07c6b9f73ebfad7d124b97a57cb7454a3
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1274
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fe5539c0419ca5076f050f1b5b2711b346e07e98
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Jun 19 04:48:28 2012 +0000

    Add standard header to prevent multiple inclusion
    
    This include file needs to be prevented from being included multiple
    times.
    
    Change-Id: I42e0cbe38d332b919f22e331eaf7a0251929e1dc
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1293
    Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Tested-by: build bot (Jenkins)

commit 2198c583b258d5f8bb20a1f5411391a4ee4d4c83
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 7 15:38:44 2012 -0700

    Move GGL0001 ACPI code to generic ChromeOS code
    
    The only difference in this code on all our platforms is the array
    describing the GPIOs. Hence, only keep that array in the mainboard
    ChromeOS directory and move everything else to generic ChromeOS ACPI
    code.
    
    Change-Id: I9fc75842af64530c1255bea1c5f803c5316d6da6
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1278
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 48214899c3e74d590ad45f1b8e98f745f2c6b2d0
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 6 13:24:32 2012 -0700

    Fix MRC cache update delays
    
    When no valid MRC cache area is found, the mrc_cache data structure
    was used without prior initialization. This sometimes caused a long
    delay when booting because compute_ip_checksum would checksum up to
    4GB of memory.
    
    Change-Id: I6a0ca1aa618838bbc3d042be425700fc34b427f2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1277
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 305b19dd7a8394132216f51acf2bc073c7c42397
Author: Ronald G. Minnich <rminnich@chromium.org>
Date:   Tue Jun 5 14:08:10 2012 -0700

    Remove code that enables/disables VMX in coreboot on chromebooks.
    
    There are several reasons for this:
    1. It's a core setting, not a platform setting, which is bizarre. But,
    we disable vmx via an SMI, and that only happens on core 0.
    Hence, the code did not correctly make the same settings on all cores-
    one had them disabled, the others were in an unknown state.
    When (e.g.) kvm started on a vmx-enabled core, then moved to a
    vmx-disabled core, the processor would reset *very* quickly.
    Changing this would be messy.
    
    2. On the CPU on link, there is something about trying to set the lock
    bit that is getting a GPF.
    
    3. It's the wrong place and time to set it. Once controlled, they can't
    be changed in the kernel. The kernel is what should control this
    feature, not the BIOS, as we have learned time and time again. If
    somebody is in as root and can start a VM, you have a lot more to
    worry about than someone starting a guest virtual machine.
    
    Change-Id: I4f36093f1b68207251584066ccb9a6bcfeec767e
    Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/1276
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 28190ce4de4667ab79e415441f791dba04022f0b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 6 13:43:52 2012 -0700

    malloc/memalign: Remove unneeded linker check
    
    This check got in the code when some Linux distros shipped broken linkers
    around 1999.
    Since then, the code around that check was changed, and it does not make
    sense anymore to have this check.
    
    Change-Id: I37c6b690d72f55c18ba4c34e8541a6a441e5e67a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1275
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5f3aca39d33183ff7d74116e6d2ef2b164fdea23
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 6 13:40:12 2012 -0700

    SPI flash layer: remove unused function spi_flash_free()
    
    We don't ever free memory in coreboot, hence drop spi_flash_free() and
    spi_free_slave()
    
    Change-Id: I0ca3f78574ceb4516e7d33c06ab1a58abfb3b0ec
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1273
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 00671887398a8266f65278318e570cb2a0cf079c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 6 13:46:26 2012 -0700

    MTRR: drop repetetive debug message
    
    It's not really useful anymore I guess, and it makes the log files
    harder to read. Hence dropping it.
    
    Change-Id: If4c3e8b40ae491ca527ef62f8145206960f6579d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1272
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 79431f5f09fa9505303e37d6b1c393dce20b4e23
Author: Ronald G. Minnich <rminnich@chromium.org>
Date:   Thu May 31 16:02:26 2012 -0700

    Make memalign print useful messages on failure
    
    Brevity is the soul of wit, except for error messages;
    then it's a sign of witlessness. I can say this because
    this error message may be my fault, although it is lost
    in the 20th century code base so who knows.
    
    Anyway, when memalign dies, it's not a bad idea to have
    a lot of information about what went wrong. So instead
    of the terse single bit of "something failed" this patch
    changes things to be a bit more useful.
    
    Change-Id: I8851502297e0ae9773912839ebfdf4f9574c8087
    Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/1270
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 496f4a0c836ab4cc1e2261eee6aea111c6ca8cfa
Author: Walter Murphy <wmurphy@google.com>
Date:   Mon Apr 23 11:08:03 2012 -0700

    SandyBridge: Add another PCI device ID for northbridge
    
    Change-Id: I153579561f7eed6d4befd74ff39e1a5e778d0e46
    Signed-off-by: Walter Murphy <wmurphy@google.com>
    Reviewed-on: http://review.coreboot.org/1269
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit da83a5f18e252e4b8e6259fd7c91e67ca25ee6cd
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri May 25 10:04:17 2012 -0700

    Fixes to enable RC6 on IvyBridge
    
    - The unneeded poll on non-MT force-wake bit was timing out
    and causing the gma_pm_init_pre_vbios() function to exit
    early so it was not preparing PM registers properly.
    I changed the gtt_poll() calls to not return on timeout
    unless it can't proceed so we don't see half-initialized
    registers.
    
    - RC6+ (Deep Render Standby) is not working reliably so we
    can just enable RC6 in the BIOS and let the kernel decide
    if it wants to enable RC6+ later.
    
    This Kernel message is new in kernel 3.4:
    [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off
    
    Change-Id: I69d005ba56be8c7684a4ea1133a1d761f7c07acc
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/1268
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ac2ec34fd28dad54269774b3881bc7aebfb40229
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Jul 10 15:19:23 2012 -0700

    Re-initialize Local APIC timer on APs
    
    In order to be able to use udelay in code running on AP cores
    the timer has to be initialized on the according local APICs
    or the system will just hang when udelay is used.
    
    Change-Id: I776bc96aa6d876ff2582d0c05cbc9c7611cb06b5
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1267
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 505414a6cfb2aeef455b5144e4b96fc27f19eb39
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 10 14:26:43 2012 +0300

    AMD and GFXUMA: drop redundant use of lb_add_memory_range()
    
    Use of uma_resource() in AMD northbridge code created a memory
    resource marked as reserved. Such resources are removed
    from system memory in write_coreboot_table().
    
    Change-Id: Ib5e49e851d6622d8ece9d6d612e245b3962b9167
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1233
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit ce6e9fed2e1e0e5a493d1133caf5c6b9f713b7fc
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jul 20 12:37:06 2012 +0200

    i945: Disable IGD if plugin VGA is preferred
    
    It's shut down, but UMA memory is not reclaimed. A later extension
    could optionally do the magic register dance that allows initialization
    of IGD as secondary graphics device.
    
    Change-Id: I2a92bb71755005b886a8e1825325c678a9991bf2
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1252
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a555e55d15298da56f6752d01e4f8a04ae1a4eb8
Author: Jukka Rantala <jukka.rantala@gmail.com>
Date:   Fri Jul 20 02:10:16 2012 +0300

    AMD CPUs: Updated CPU list in powernow_acpi.c
    
    Updated P state table to make frequency scaling work.
    Added these CPUs: http://support.amd.com/us/Processor_TechDocs/30430.pdf
    Also wrote a Python script for parsing AMD docs,
    but not sure where to put it: http://pastebin.com/1dSvkXwc
    
    Change-Id: I8f08111b73b9be551f3f59d2acb15051ccf36c1e
    Signed-off-by: Jukka Rantala <jukka.rantala@gmail.com>
    Reviewed-on: http://review.coreboot.org/1244
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 557ecf2d31acef9ddcf7e0c9b47961c0ad36f57e
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jul 20 12:16:17 2012 +0200

    Simplify VGA card discovery
    
    We were handling vga, vga_first, vga_last, vga_onboard just to determine
    an onboard chip and the first plugin card.
    We were also traversing the devices manually instead of using the utility
    functions we have, for the chance that there are non-VGA cards we need to
    cope with (but why would they require VGA-style handling?)
    
    Change-Id: I8aa73aefa102725a64287f78a59de3d5dda1c7f2
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1255
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 323a9236954cd847ad36c9b48b97fe9f74c49ea4
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Jul 19 16:39:01 2012 +0800

    Mainboard Parmer based on Trinity
    
    Parmer has.
    1. Trinity, Socket FS1R2.
    2. Hudson A75.
    Ubuntu has been validated on Parmer. S3 is supported.
    
    Change-Id: I1a6932d0ca9f7abe78dc24d3bc238a4b5a48281b
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1158
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6db7f348ea35e25b880edb73e4c322a361c1a8c9
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Jul 19 16:38:12 2012 +0800

    Trinity wrapper code improvement.
    
    Set the default location of hudson firmware to 3rdparty.
    Move UMA code from mainboard to northbridge.
    
    Change-Id: I11afea0c7fd04aa84a629dc762704c42baf002df
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1241
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 59b36f1026090ea9b39ca2bc8386c8addf1b03d6
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Sat Jul 21 07:29:48 2012 +0400

    msrtool: Factor out cpuid() from target probe functions into main()
    
    Almost all probe functions called cpuid(). Those calls are replaced
    by a single cpuid() call in main() and a new parameter to the target
    probe functions with the cpuid() result.
    
    The vendor_t and struct cpuid_t definitions are moved closer to the
    top of msrtool.h and the vendor_t enum is reformatted to simplify
    addition of further values.
    
    Change-Id: Icd615636207499cfa46b8b99bf819ef8ca2d97c0
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/1259
    Tested-by: build bot (Jenkins)

commit c7fc4422a0039b6fd6c44bd98050ec648ee0312a
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Sat Jul 21 06:36:47 2012 +0400

    inteltool: Add support for H65 Express chipset
    
    Added few MCH and DMI registers for H65E.
    Description of them can be found at
    "2nd Generation Intel Core Processors
    Family datasheet"
    
    Change-Id: If4fee35bb5a09b04ea0684be9cbd3c1e9084b934
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1258
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 8bacc40fc7bd07365c2992b260ddbd45cd6e4518
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jul 19 16:16:59 2012 +0200

    Fix udelay() implementation for i945 romstage
    
    Work around 32-bit overflow with 64-bit multiplication. Calculate
    correct CPU frequency.
    
    Change-Id: I86d78f2d70b9f9c62fd4e1e0d765e92e4de83f67
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1254
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5869fa2e631d5d2483a4ee0445e6496120b42f02
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jul 20 12:29:33 2012 +0200

    Allow shutting down internal graphics if plugin graphics are preferred
    
    VGA is this part-legacy thing that can cause trouble...
    
    For this, introduce device_t->disable(dev) method, in which a driver
    can take care to deregister the device if necessary.
    
    Change-Id: I3fecec07f402e530458b79eda30b2c274101fefa
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1251
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c4b2a1b6de9671a7e6672de5fb99068d05eba269
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jul 20 13:44:50 2012 +0200

    Allow YABEL to fake write accesses to config space
    
    A new Kconfig option tells YABEL to succeed on write accesses
    on other devices' config space without performing the actual
    write.
    This is enough for some basic bus modification done by some
    Option ROMs.
    
    Change-Id: Iab04f3a5c350b96654da4ba26858037f4c4b5c0a
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1249
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bcdbe90296bad7fdf56416e9713789194fb83aa3
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jul 20 11:55:19 2012 +0200

    Drop VGA_BRIDGE_SETUP config option
    
    It defaults to true, and isn't disabled anywhere in the tree.
    I also couldn't think of a case where it's actually useful.
    
    Change-Id: I126a47625d5294f3cfff225629f2a948a83c9b7e
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1250
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 116327ee064c06e4304313be1f379593aa289572
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jul 20 12:47:06 2012 +0200

    sconfig: typo fix
    
    eliminate printf format warning.
    
    Change-Id: I51f75a259d28c5de788f57c3d720b76ca638e330
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1248
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit cda9f93965c941719874764affc621b78ba145f5
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 18 10:05:01 2012 +0300

    Intel SCH northbridge: fix resource index
    
    Change-Id: If131ac9df89080faccd8ed952d6fc019483b5b2e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1237
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 552c45cf1f670012523171cf20cb7564c225b2b2
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jul 19 09:22:59 2012 +0200

    Finally update 3rdparty
    
    Change-Id: Ic85c1411cd8ccb6b3b96459738fbf8d7d9a2ca77
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1242
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 7a6bdd213a3232531e8f890c47d8b5960f9aaa56
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Jul 19 12:44:17 2012 +0800

    Add missing quote.
    
    Remove the menuconfig warning which comes up every time.
    src/mainboard/asus/Kconfig:85:warning: multi-line strings not supported
    
    Change-Id: I0ec0a0b625a33edd1d9b250a26aa3e0f42142eca
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1240
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 07284633d8acbc123d675e305822b8d86ba5deaf
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Jul 16 23:00:04 2012 +0300

    AMD northbridges: drop dead code
    
    Change-Id: I03949722ac3a127319a0ad3f812d77ba7b8f139f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1187
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 41c229c02944834a55fc0b17bed5950facc9eae6
Author: Mathias Krause <minipli@googlemail.com>
Date:   Tue Jul 17 21:17:15 2012 +0200

    cbfstool: signed vs. unsigned fixes
    
    Use the right data types to fix compiler warnings.
    
    Change-Id: Id23739421ba9e4a35599355fac9a17300ae4bda9
    Signed-off-by: Mathias Krause <minipli@googlemail.com>
    Reviewed-on: http://review.coreboot.org/1236
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 5c581c4d6c2c32bcfe67acaafd9aa513a8cad328
Author: Mathias Krause <minipli@googlemail.com>
Date:   Tue Jul 17 21:11:59 2012 +0200

    cbfstool: provide a prototype for remove_file_from_cbfs
    
    To complement commit e1bb49e (Add a "remove" command to cbfstool) and
    fix a compiler warning provide a prototype for remove_file_from_cbfs.
    
    Change-Id: Ied8eac956de5fed3f9d82ce1e911ee1fec52db15
    Signed-off-by: Mathias Krause <minipli@googlemail.com>
    Reviewed-on: http://review.coreboot.org/1235
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit d2567c8d92cb2c816dc9e8078740aad93d14dc32
Author: Mathias Krause <minipli@googlemail.com>
Date:   Tue Jul 17 20:52:17 2012 +0200

    cbfstool: make endian detection code more robust
    
    Accessing the memory of a char array through a uint32_t pointer breaks
    strict-aliasing rules as it dereferences memory with lower alignment
    requirements than the type of the pointer requires. It's no problem on
    x86 as the architecture is able to handle unaligned memory access but
    other architectures are not.
    
    Fix this by doing the test the other way around -- accessing the first
    byte of a uint32_t variable though a uint8_t pointer.
    
    Change-Id: Id340b406597014232741c98a4fd0b7c159f164c2
    Signed-off-by: Mathias Krause <minipli@googlemail.com>
    Reviewed-on: http://review.coreboot.org/1234
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 117198662778778d132ee6077c1f39635adbadd9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Jul 6 17:27:37 2012 +0300

    Drop invalid device ops on Agesa northbridge
    
    One could not pass a device of type APIC to PCI resource functions.
    The correct CPU model specific cpu->ops is set at later time in
    cpu_initialize().
    
    Change-Id: Ifa274185e4db3080433c1f07e3a48f2b55c0514f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1180
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit de3dde46fd3efaba65656509d4221f29a66257a3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 10 13:10:24 2012 +0300

    AMD: Fix GFXUMA with 4GB or more RAM
    
    Northbridge code incorrectly adjusted the last cacheable memory
    resource to accomodate room for UMA framebuffer. If system had
    4GB or more memory that last resource is not below 4GB and not
    the one where UMA is located.
    
    There are three consequences:
    
    The last entry in coreboot memory table is reduced by uma_memory_size.
    
    Due the incorrect code in northbridge code state.tomk,
    end of last resource below 4GB, had not been adjusted.
    Incrementing that by uma_memory_size diverts a region
    possibly claimed for MMIO to RAM, as TOP_MEM is written.
    
    Since the UMA framebuffer did not have IORESOURCE_CACHEABLE,
    it was ignored from the MTRR setup and not set uncacheable.
    
    The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs,
    should be copied from BSP to all APs instead of deriving the data
    separately for each Logical CPU.
    
    Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1217
    Tested-by: build bot (Jenkins)
    Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2354515f2e9ebf46fca2dc0e3c434940aaac6e9b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 12 01:18:31 2012 +0300

    AMD MTRR: fix rounding and renames
    
    Use state.tomk to refer TOP_MEM, largest RAM address below 4GB.
    Use state.tom2k to refer TOP_MEM2, largest RAM address above 4GB.
    
    When setting either TOP_MEM or TOP_MEM2, any RAM resource found
    must fit below the set value. Thus, round register value upwards,
    not downwards.
    
    Change-Id: I436c1b3234c911680ce8b095052f8d71f40113e2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1216
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2d42b340034ff005693482ef9ca34ce3e0f08371
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 12 00:18:22 2012 +0300

    Check for IORESOURCE_UMA_FB in MTRR setup
    
    If northbridge called uma_resource() a resource of this type
    should be found when walking the resources list.
    
    For now, be rude and don't even try to combine it with
    neighboring regions. As the type is un-cacheable it is
    dominant over other MTRR setups claiming the same region.
    
    Change-Id: I57805e7e7da0709f8ed78d8df62c2abf22172a06
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1215
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0b08515c2b60c8ff67c04e65d27dabba8ac0025b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 11 23:14:49 2012 +0300

    Change uma_resource() to use new type IORESOURCE_UMA_FB.
    
    MTRR setup code can detect this and mark it as UC/WT/WC as suitable
    for the specific hardware.
    
    Change-Id: Ib7a3d450fc7c19e3ca72767dfb350412dd35c971
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1214
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ba589e3630b0e3259b1f3d54434589e76ec48398
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 11 08:03:13 2012 +0300

    Move setup_uma_memory() to K8 northbridge
    
    These boards had identical UMA code:
      amd/dbm690t
      amd/pistachio
      technexion/tim5690
      technexion/tim8690
    
    The ones below had whitespace or debug level change
    compared to the one above:
      kontron/kt690
      siemens/sitemp_g1p1
    
    These boards use AMDFAM10 guidelines in code:
      asrock/939a785gmh
      amd/mahogany
    
    Change-Id: Id7c3f48035727f5847f2d7c3a6e87a3d15582003
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1210
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 231f2614021967c9645d9e5b83dbea2089600be3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 11 08:02:57 2012 +0300

    Move setup_uma_memory() to AMDFAM10 northbridge
    
    Following boards had identical code:
      advansus/a785e-i
      amd/bimini_fam10
      amd/mahogany_fam10
      asus/m5a88-v
      avalue/eax-785e
      gigabyte/ma78gm
      iei/kino-780am2-fam10
      jetway/pa78vm5
    
    Following boards had identical code:
      amd/tilapia_fam10
      asus/m4a78-em
      asus/m4a785-m
      gigabyte/ma785gm
      gigabyte/ma785gmt
    
    In between the two, only whitespace difference.
    
    Change-Id: Iaa48cc7b0038ebcc81be49219b4fc87670aa9941
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1209
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 55fff930ce01aff16dfd24cf0d446a3a181dd6f7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 11 08:02:39 2012 +0300

    Move setup_uma_memory() to Agesa Family14 northbridge
    
    Following boards had identical code:
      amd/inagua
      amd/persimmon
    
    The following had only whitespace or debug level changes
    compared to ones above.
      amd/union_station
      amd/south_station
      asrock/e350m1
    
    Change-Id: I11ee46e06e1dd510cba551166189ebcaa144464b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1208
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d4821fc702767626cbf58940d4a08f6688b354a4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 11 08:02:24 2012 +0300

    Move setup_uma_memory() to Agesa Family12 northbridge
    
    Change-Id: Ieaf284c207f0cd4b2f6b804c52f949c16435d823
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1207
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 03548aa6b849e94037aa2c2da0ef36d27267d554
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 11 08:01:35 2012 +0300

    Move setup_uma_memory() to Agesa Family15 northbridge
    
    Change-Id: I5705623f5067823fae5986b3bcde58504a463508
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1206
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cc55b9b9199657834a946ea2de059c3fab3e3b10
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 11 07:55:21 2012 +0300

    Define global uma_memory variables
    
    Use of the uma_memory_base and _size variables is very scattered.
    Implementation of setup_uma_memory() will appear in each northbridge.
    
    It should be possible to do this setup entirely in northbridge
    code and get rid of the globals in a follow-up.
    
    Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1204
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 63f8c088307c5296809d9499b3b7cbaedb2a4440
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 10 13:27:26 2012 +0300

    Add global uma_resource()
    
    Like ram_resource(), but reserved and not cacheable.
    
    Switch all AMD northbridges to use this one.
    
    Change-Id: I88515c6a0f59f80fd8607c390d0d4a2a35d805f2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1203
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d4220691c58934420ad196d4a0903dc88388ae85
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jul 12 20:05:22 2012 +0200

    i5000: Fix resource allocation
    
    The current code didn't reserve static resource the right way.
    Also reduce TOLM to 0xd0000000, because those boards have so many PCI
    devices that 0xe0000000 isn't sufficient.
    
    Change-Id: Ia75a81905eea1a096aed464b63ac154e044bc99c
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1220
    Tested-by: build bot (Jenkins)

commit f8878845f9cb9d30663a8bb3a3edeb1413a42388
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jul 12 11:21:51 2012 -0700

    Poison the stack to uncover programming errors
    
    Code can easily make the mistake of using uninitialized
    values or, in assembly, mistakenly dereferencing stack pointers
    when an address is desired.
    
    Set the stack to a non-zero value which is also (by testing)
    a pointer which will crash coreboot if used. This poisoning
    has uncovered at least one bug.
    
    Change-Id: I4affb9a14b96611e8bf83cb82636e47913025a5d
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/1221
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 2d0d83c3dd41a95f5c27a2c7ecf0a3a8cdd5d0be
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jul 11 21:47:11 2012 +0200

    Add ASUS DSBF mainboard
    
    Change-Id: Iad38b92ca3a582e5aec07b92c994bfbe78b09855
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1223
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6fa1d3a218332230826a5a5ebd676017b30b5930
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Jun 25 21:35:45 2012 +0200

    Supermicro X7DB8: Use autogeneration of mptable
    
    And fix the wrong indenting of devicetree.cb while at it.
    
    Change-Id: Idbb19fb5d7155f44675098e79920caf65191c239
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1222
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 246e84bc0d04e3e670ca815eca32bcfa3be7e2c2
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Jul 13 18:47:03 2012 +0800

    AGESA F15 wrapper for Hudson.
    
    Hudson code has been integrated from CIMx to AGESA. This patch is about the wrapper.
    
    Change-Id: I63d951982140b82a3a77a97eb3d55fc75fc0caa3
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1157
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 22b7a55a4db9d9bfa69113a8e25e86f21ce8ab6e
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Jul 13 19:00:46 2012 +0800

    Remove useless file from building.
    
    Change-Id: I09c695347c04d7db9add2cbb687d59c829175cfc
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1224
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2b108a43687fbf36c601236ef198ea543bc27c1a
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jul 13 12:02:44 2012 +0200

    sconfig: fix up shipped code
    
    The lex compile wasn't current (or something) and so INTA wasn't lexed
    properly.
    
    Change-Id: I5a760430788792f54c4e1e0d419b8dd525079d15
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1226
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 86f992c38a2b64619d924adf66d77f4fe8494b81
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Fri Jul 13 11:36:08 2012 +0200

    Add preliminary support for Bachmann electronic OT200
    
    Linux boots fine :)
    
    Change-Id: Ifda06e5220666534b87f528deae16d8b956c32b3
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/1225
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 42b808e889b32344977fa067120ea02fa803e9a4
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Wed Jul 11 09:31:12 2012 +0200

    msrtool: add support for cs5536 LPC_SERIRQ (0x5140004e)
    
    This register is helpful for porting new mainboards based on
    cs5536 southbridge.
    
    Change-Id: Iff3adc2c2fbc672c8541096756f95b3322f6ab19
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/1211
    Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0fa50a1990fcdfca6a9f75a68f8e4ed22ddd6949
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jun 21 22:19:48 2012 +0200

    MPTAPLE: generate from devicetree.cb
    
    This patch adds support for autogenerating the MPTABLE from
    devicetree.cb. This is done by a write_smp_table() declared
    weak in mpspec.c. If the mainboard doesn't provide it's own
    function, this generic implementation is called.
    
    Syntax in devicetree.cb:
    
    ioapic_irq <APICID> <INTA|INTB|INTC|INTD> <INTPIN>
    
    The ioapic_irq directive can be used in pci and pci_domain
    devices. If there's no directive, the autogen code traverses
    the tree back to the pci_domain and stops at the first device
    which such a directive, and use that information to generate the
    entry according to PCI IRQ routing rules.
    
    Change-Id: I4df5b198e8430f939d477c14c798414e398a2027
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1138
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6591470ae0c9639b1ef591ede96eee4a930f35e2
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jul 11 21:45:46 2012 +0200

    IOAPIC: hook up driver in Kconfig
    
    Missed to add the driver to Kconfig and Makefile.inc.
    
    Change-Id: I64b02abc5de2f6483f610436ebb38a7ca433f9b6
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1219
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ffc1fb35aab659127156d4aa28c1cbd6d5793b19
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jul 11 14:40:19 2012 +0300

    Drop Kconfig VAR_MTRR_HOLE option
    
    All but one board use the default value of enabled. Disabling
    this can only increase the number of MTRR registers used.
    
    Change-Id: I7d28adc31b9fae2301e4ff78fcb96486f81d5ec2
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1213
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit db2c400ab852a2aae09d812b20e520ca371da35b
Author: Anton Kochkov <a.kochkov@securitycode.ru>
Date:   Fri Jul 6 11:54:17 2012 +0400

    libpayload: Add reset function for OHCI USB driver
    
    Implemented OHCI reset function ohci_reset() in ohci.c
    for libpayload's USB driver.
    
    Change-Id: Id6518cbe00a21202757b34926bad171909740e97
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1177
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 25962837baaa18c58635cd4eb82bba49a89b003b
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Tue Jul 10 10:14:17 2012 -0500

    Lenovo X60: correct SDHCI write protect polarity
    
    Change-Id: I916deffe2c692042f7e54c936902e77770ee69df
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/1205
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 21856eec594c076d5c848b1c716baffaeded3af2
Author: Guenter Roeck <linux@roeck-us.net>
Date:   Fri Jun 29 12:24:57 2012 -0700

    superiotool: Dump data registers for Nuvoton chips
    
    Add support to dump all data registers for Nuvoton chips (NCT6775F, NCT6776F,
    and NCT6779D). Register contents will be dumped if the -e option is provided on
    the command line.
    
    Change-Id: I2b425b48c1f28a10ff3c1ca1d7f21c501eff74ad
    Signed-off-by: Guenter Roeck <linux@roeck-us.net>
    Reviewed-on: http://review.coreboot.org/1150
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a89da0969efe52ca4474867966152cbe6c92ca21
Author: Guenter Roeck <linux@roeck-us.net>
Date:   Fri Jun 29 12:23:50 2012 -0700

    superiotool: Add support for function to dump superio chip data registers
    
    Add new function dump_data() to dump a bank of superio data registers.
    
    Change-Id: I13a58d87c14d319cfcdea1ec1d54c2b110d90f9f
    Signed-off-by: Guenter Roeck <linux@roeck-us.net>
    Reviewed-on: http://review.coreboot.org/1149
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 975ffc2e0f5e796384bebf6fce19b47dc2077f6a
Author: Guenter Roeck <linux@roeck-us.net>
Date:   Fri Jun 29 12:22:51 2012 -0700

    superiotool: Add support for NCT6775F(A/B) and NCT6779D
    
    Change-Id: I66667fcb58f6885460021f4a2024d6ba56b95f11
    Signed-off-by: Guenter Roeck <linux@roeck-us.net>
    Reviewed-on: http://review.coreboot.org/1148
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6f73a5bf7000ffa1c11e9f195760ebce948159b3
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jul 11 21:41:06 2012 +0200

    Fix stack assignment during CPU initialization
    
    There are two errors in the code. The first one is a missing
    $ sign in mov _stack, %esp. Thanks to Ronald G Minnich for
    catching that bug.
    
    The second bug is the 'incl %eax', which shouldn't be there, as
    there's no secondary CPU with index 0. CPU0 uses always the stack
    below _estack.
    
    Change-Id: Id267a654ba95b0e898eeaaafb2403b438250a563
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1212
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit bc8c996608e68cb30d968796b0359a922ec66828
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 10 10:19:40 2012 +0300

    Fix APIC cpu_index
    
    If a CPU was pre-allocated, cpu_path is not copied and thus
    index would not be updated. This breaks cpu_index() and AMD
    model_fxx is possibly broken without this patch.
    
    Change-Id: I77483181cf0bca31423c655942c022bffab3c7ea
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1199
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit a5650a4b4ac85722d772083761ffea32557774b4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jul 7 17:15:51 2012 +0300

    Use dev_lock for alloc_find_dev()
    
    If threads called alloc_find_dev() with same device_path
    simultaneously, two device nodes could be allocated.
    This bug is not triggered by current code.
    
    Change-Id: Ifc87021c8d6f422901c5de5dd17392e3e2309afa
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1188
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit da09be6328505ac4473aff48b8ef27b9986bfa22
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Jul 10 10:17:32 2012 +0300

    Drop start_cpu_lock
    
    Function alloc_find_dev() is serialized.
    
    Change-Id: I40d27d1adca629f1f7ce2f09c1cb2fd04b76eb9a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1198
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 54c07a675bada869cbe423a348af0dd041dcf7c3
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Wed Jul 4 07:35:45 2012 +0400

    msrtool: Add Intel Nehalem CPUs support
    
    Added Intel processors based on Nehalem
    architecture support, with decoding MSRs.
    
    Change-Id: I576d5eac2542c0b62852bf05e42bc98b134c7eae
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1170
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ffbbecc9eed9705d7fdb9f6825ab7ccd9224fb09
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Wed Jul 4 07:31:37 2012 +0400

    msrtool: Fix Intel CPUs detection
    
    Added vendor check in sys.c file and fixed models checking
    in intel targets files.
    
    Change-Id: I1ce52bbce431dea79e903d6bc7a12e5b9ad061be
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1169
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e1e6a91ce0738400fa1615179de88ebc0df29f66
Author: Raymond Danks <ray.danks@se-eng.com>
Date:   Mon Jul 9 13:29:17 2012 -0600

    mkelfimage: pkgdata directory created but never used
    
    Remove superfluous pkg* definitions and installation of a target
    directory directory that is never used.
    
    Change-Id: I2addf3f316230cdd428def5889fd3beb7c40f422
    Signed-off-by: Raymond Danks <ray.danks@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1195
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 356a600907be10f5805f5fba5a40a30f97c9a0a7
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Jul 6 12:24:23 2012 +0200

    servengines/pilot superio: add attribute unused
    
    Not all users use both functions, so add __attribute__((unused))
    to prevent compiler errors.
    
    Change-Id: I8485bb9150b04d1f9fdc231152a43bcd6fc713a7
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1193
    Tested-by: build bot (Jenkins)

commit 6d03876affc54ff675219ed5da2f29f962d8135c
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Jul 9 08:52:53 2012 +0200

    SMBIOS: Add Type 38 (IPMI) data structure
    
    Change-Id: I9b9a1c7b1cc4aaba7a4791f898653b6fe41d4fcb
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1192
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 34d86f0c6178cf057a58891c1c90e48a189795af
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Jul 6 08:58:11 2012 +0200

    i5000: reset system if raminit fails
    
    Don't stop if RAM init fails at first try. It's better to restart
    and try again instead of failing on the first try if the second
    try would have worked.
    
    Change-Id: Ib5660265d5b10a01588f2e4022dac2ee34f2c6d0
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1191
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 7435baa5c5cb1511e8a9533965bd07e94a536203
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jul 8 18:32:23 2012 +0200

    Add basic ipmi support
    
    Implements support code for talking to IPMI hardware that uses
    a KCS style interface.
    
    Change-Id: I9895cc1bf29676115b167081b63b8a430e23eee5
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1190
    Tested-by: build bot (Jenkins)

commit f5062437dc6fae2932568a3038e6771b0dc8d820
Author: Ricardo Martins <rasmartins@gmail.com>
Date:   Fri Jul 6 17:41:29 2012 +0100

    IEI PM-LX-800-R11: Removed bogus Kconfig option
    
    The Kconfig file for this board contains a bogus option called
    CORE_GLIU, this change removes it.
    
    Change-Id: I4ea069bdd76be53085ebc9c0fb3dd71ffb2a12e1
    Signed-off-by: Ricardo Martins <rasmartins@gmail.com>
    Reviewed-on: http://review.coreboot.org/1179
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 56dfc7c6843f22d4491bc8b79a2afca72dd40e60
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jul 5 22:53:57 2012 +0200

    inteltool: fixup intel 5000 chipset pci ids
    
    Change-Id: I2cd1dac0dd9a5da1000a3ffa3e1c8ee4c5c8ba43
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1175
    Tested-by: build bot (Jenkins)

commit 7b4837957544b96b98d12e3287379089d6b5f07b
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jul 5 17:17:45 2012 +0200

    i5000: Add PCI ids for all i5000 flavours
    
    Change-Id: I48be647e3f38038830200bcc64429cbf86990ad7
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1174
    Tested-by: build bot (Jenkins)

commit 0ca02553e1bb6675be8d5d1f2cc831585e0803f2
Author: Ricardo Martins <rasmartins@gmail.com>
Date:   Wed Jul 4 03:09:49 2012 +0100

    IEI PM-LX-800-R11: Added preliminary mainboard support
    
    Details for this board are available at
    http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=08142307826854456110
    
    Most of the functionality provided by the original BIOS is
    implemented.
    
    Change-Id: Id9eb10a2f9e49377ea587bddadbba7d76223a715
    Signed-off-by: Ricardo Martins <rasmartins@gmail.com>
    Reviewed-on: http://review.coreboot.org/1168
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6444bd4547802cc27e8830161341e68b1dcf0ba1
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jul 6 11:31:39 2012 +0200

    i945: Reset IGD on boot
    
    This is mostly necessary for reboot, but it doesn't hurt the boot process.
    On reboot explicitely reset the integrated graphics, otherwise the VGABIOS
    might not be able to reinitialize it properly, and you either have a still
    of the last pre-reboot image, garbage or an empty screen, but no text-mode.
    
    Change-Id: Ic3d6932fbaf720d88daaac7e4b09c3c0b9f0b0e2
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1178
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 3397ceff7b8a2453e4f045f32f2aaa5be1b2166d
Author: Guenter Roeck <linux@roeck-us.net>
Date:   Fri Jun 29 12:25:46 2012 -0700

    superiotool: Add support for git-based version number
    
    The superiotool Makefile extracts a version string from SVN. This does not work
    with a git repository, and results in an empty version string. Use the output of
    'git describe' as version string instead.
    
    Change-Id: Idf92c02753b28ef5bcdd3b6df4a08d79ae974434
    Signed-off-by: Guenter Roeck <linux@roeck-us.net>
    Reviewed-on: http://review.coreboot.org/1151
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 97de28da8af758b85c644b3dc151aeb743e13412
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jul 2 09:41:10 2012 -0700

    PCI Type2 config must die
    
    PCI Type 2 config was a strange and never-used config mechanism.
    It is unlikely that in the 13 years of coreboot's existence that
    type 2 was ever used; it just made life complicated for everyone.
    It lived long enough in coreboot to be replaced by mmioconf.
    Prior to making the device tree visible in romstage we want to
    get rid of type2.
    
    Delete two files we don't need any more (yay!).
    Replace two functions with one: pci_config_default, which returns
    a pointer to the default config method. At some future time this
    may change to mmio but for now it is old type1 style.
    
    Change-Id: Icc4ccf379a89bfca8be43f305b68ab45d88bf0ab
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/1159
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 63539bb9d7fe9ae55a364cadfcbd79ecb98a9412
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 5 06:31:15 2012 +0300

    Only copy real-mode section of SIPI vector
    
    The SIPI vector copy can use a static location below 1MB, aligned
    to 4kB. Jump out of the copy once in protected mode.
    
    Change-Id: I6299aa3448270663941cf2c4113efee74bcc7993
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1165
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 9a663f3e97fff9cfc3eb9ed2c6e843a68bcabf90
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jul 5 06:30:29 2012 +0300

    Fix the CPU index parameter passed to secondary_cpu_init().
    
    Count 0,1,2,3,... instead of 0,2,3,4,...
    
    Change-Id: I3c6b85e5e71b32deac5470809e1618d28f19c00f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1173
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 5458b9d90a246833de55e0814f0c323a0cf6e471
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Jun 30 11:41:08 2012 +0300

    Intel cpus: Extend cache to cover complete Flash Device
    
    CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set
    in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup
    would not cover the bottom 4 MB when ramstage is decompressed.
    
    Verify CACHE_ROM_SIZE is power of two.
    One may set CACHE_ROM_SIZE==0 to disable this cache.
    
    Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1146
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit ae7d6ef8b7ef5ca9c04d8d929332d18d563f723e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 28 21:50:43 2012 +0300

    Intel model_106cx: change CAR to model_6ex
    
    Diff between model_106cx and model_6ex CAR codes suggests currently
    used model_106cx CAR is not optimal - destination RAM and source ROM
    of ramstage copy_and_run are only partly set cacheable.
    
    It appears variable MTRR setting for XIP cache is left enabled on
    model_106cx code, where it should have extended to cover all of Flash.
    
    Introduces untested functional change on boards:
      intel/d945gclf
      iwave/iWRainbowG6
    
    Deletes file:
      model_106cx/cache_as_ram.inc
    
    Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/642
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 4dcc5737cd431b729a1011c24012d6ee1a481b90
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 28 12:16:12 2012 +0300

    Intel cpus: delete dead CAR code and whitespace fixes
    
    A diff from model_6fx to model_106cx suggests there is little
    CORE2 specific code that was once considered useful to have.
    In its current status however, sockets supporting model_6fx use
    model_6ex CAR init, so that specific code is actually
    never used.
    
    Deletes file:
        model_6fx/cache_as_ram.inc
    
    Change-Id: I6c0204446fa98207e31f91895e1cf30fde42382c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/640
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit aa03af74f177ba6d13b54b34d96cceec609e889f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Jun 22 11:04:22 2012 +0200

    Add generic IOAPIC driver
    
    Used for automatic generation of IOAPIC interrupt entries.
    
    Change-Id: Ia746f01906c840800956ce551306f864e440b6ec
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1137
    Tested-by: build bot (Jenkins)

commit c7fb2ae67b0dc3c2c38f8ef630a3a72374440032
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Jun 28 21:26:41 2012 +0300

    Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR
    
    Default CPU_ADDR_BITS is 36.
    
    For Atom (model_106cx) use 32. This model is known to
    fail execution-in-place (XIP) with the default 36.
    
    Pentium M should use 32, but doesn't even with this patch.
    Some Xeon and CORE(2) models should use 38 or 40.
    
    Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/639
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 89f04a6d68cbb8faf9d90089cc76ee38bdf932ad
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jul 3 22:15:42 2012 +0200

    Supermicro X7DB8: add w83793 Hardware monitor
    
    used for fan control and thermal management on that board.
    
    Change-Id: I4e5c986ab6174b7a356d682e21732c46181af211
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1167
    Tested-by: build bot (Jenkins)

commit ca68297cda83030f417175ef3f256babe9ccf398
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jul 3 21:33:47 2012 +0200

    Add Nuvoton W83793 hardware monitor driver
    
    Change-Id: I3ecb5c8666eea247bf4c31aaf9426bd9ef66bf68
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1166
    Tested-by: build bot (Jenkins)

commit 87ed6173e279ed6feb029a220f7098b2fa6504b6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Jul 3 18:07:04 2012 +0200

    Fix AMD S3 block generator on Cygwin
    
    awk on Cygwin created the UTF-8 value for the 0xff code point,
    which makes it two bytes wide. This broke the build.
    
    Change-Id: I4937ae7ce1136ba7a76d05b42f9dd2771203175d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1164
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit a645abbf54f965e596c58e8eb2c84d733e19b737
Author: Christian Gmeiner <christian.gmeiner@gmail.com>
Date:   Tue Jul 3 10:11:51 2012 +0200

    SMBIOS: move serial number and version out to Kconf
    
    With this change it is possible to define serial number
    and version of the mainboard. These informations are used
    in SMBIOS tables.
    
    Change-Id: I1634882270f6cb94e00aceb7832e7fd14adc186b
    Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
    Reviewed-on: http://review.coreboot.org/1163
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9b4c92ad80d691e9e2a4e5a84ad035fbe8e8d977
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jul 2 09:46:42 2012 -0700

    Fix the error message for romstage when .bss or .data are non-zero
    
    The error message from romstage is annoying and misleading:
    "Do not use global variables in romstage"
    
    Because it can occur even when global variables are not used
    in some circumstances, but also because it gives you only a rough
    idea where to look. This change sucks but sucks less. We still don't
    know which file the problem is in but at least we know if it is data
    or bss.
    
    Replace the error message with something that provides more information
    and less guessing on the part of the script:
    ".bss is non-zero size in romstage which is not allowed -- global variable?"
    or
    ".data is non-zero size in romstage which is not allowed -- global variable?"
    
    To test: build coreboot as normal. It builds.
    Add
    char d[32];
    to romstage.c and get the first error message; add
    int x = 32;
    to romstage.c and get the second.
    
    Change-Id: I300ec05bdb4b30d7ef3f5112e6cc09b1fafe8263
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/1160
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2c08f6ade4ac904e9eb762c71f95daa372be0072
Author: zbao <fishbaozi@gmail.com>
Date:   Mon Jul 2 15:32:58 2012 +0800

    AGESA F15 wrapper for Trinity
    
    The wrapper for Trinity. Support S3. Parme is a example board.
    
    Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1156
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7d94cf93eec15dfb8eef9cd044fe39319d4ee9bc
Author: zbao <fishbaozi@gmail.com>
Date:   Mon Jul 2 14:19:14 2012 +0800

    AGESA F15tn: AMD family15 AGESA code for Trinity
    
    AMD AGESA code for trinity.
    
    Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1155
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 78efc4c36c68b51b3e73acdb721a12ec23ed0369
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jun 26 09:11:55 2012 +0200

    remove CONFIG_SERIAL_CPU_INIT
    
    The new broadcast code doesn't support serial init - if a CPU
    needs serial init, this should be handled in the model specific CPU
    init code.
    
    Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1140
    Tested-by: build bot (Jenkins)

commit 042c1461fb777e583e5de48edf9326e47ee5595f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 17 10:32:55 2012 +0200

    Use broadcast SIPI to startup siblings
    
    The current code for initializing AP cpus has several shortcomings:
    
    - it assumes APIC IDs are sequential
    - it uses only the BSP for determining the AP count, which is bad if
      there's more than one physical CPU, and CPUs are of different type
    
    Note that the new code call cpu->ops->init() in parallel, and therefore
    some CPU code needs to be changed to address that. One example are old
    Intel HT enabled CPUs which can't do microcode update in parallel.
    
    Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1139
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9ed1456eff73d1a268eabb84176dd2a2107bf2d7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Jun 27 16:14:49 2012 +0300

    Intel CPUs: execute microcode update only once per core
    
    Early HT-enabled CPUs do not serialize microcode updates within a core.
    Solve this by running microcode updates on the thread with the smallest
    lapic ID of a core only.
    
    Also set MTRRs once per core only.
    
    Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/1142
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ac6e3172ff7c1c11da59c488b239d08af1248503
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Wed Jun 27 07:16:03 2012 +0400

    libpayload: OHCI driver correct PCI BAR reading
    
    Correct registers base (PCI BAR) reading to be
    more specification friendly. Registers base
    only in [31-12] bits, all other proposed to be 0
    but that not true for some motherboards. So
    adding mask to use only valid bits.
    
    Change-Id: I2e9a4997e016dab812ccfe654e966bc91d42a625
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1143
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8fef6625050fc7973dab8c6d2ca317057bd978b2
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Thu Jun 28 08:19:41 2012 +0400

    libpayload: use correct types in UHCI driver
    
    As we using 16-bit reading and writing in UHCI drive,
    so all variables related to that must be 16-bit too.
    
    Change-Id: Ib1abb03d054c167512e21f24f3c3da688c7fd01f
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1144
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f03dff7ab1829b5662099fc41eb89346aa2f2a55
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 24 10:02:22 2012 +0200

    X60/T60: fix mptable LINT entries
    
    They used MP_IRQ_TRIGGER_LEVEL, but it should be MP_IRQ_TRIGGER_EDGE.
    While at it, uses mptable_lintsrc() instead.
    
    Change-Id: Ie71311b8bf865889cf0d8808467df98af4b0132d
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1136
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 72f35a62be1e9ebc5903056cdb210ea176e2cc8a
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 14:56:46 2012 +0200

    Add Supermicro X7DB8 motherboard
    
    This adds basic supported for the Supermicro X7DB8. Basic means that
    almost all onboard peripherals are working. Known problems are:
    
    - mptable needs to be written dynamically. If you plan to use Add on
    cards, modify mptable.c according to your needs. A patch to add generic
    mptable autogeneration based on devicetree is coming up.
    
    Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/493
    Tested-by: build bot (Jenkins)

commit 1f20da7c3350bf8a0830c579f28fddc74af3f074
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 14:54:08 2012 +0200

    i3100: add smbus_write_byte()
    
    Required for Supermicro X7DB8, which needs the FBDIMM clock generator
    setup during romstage.
    
    Change-Id: I30ca8354087e851487aee0614595782131d4d9bc
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1116
    Tested-by: build bot (Jenkins)

commit e4cece0d6f3bfa7254600e6fd4b5245733a02d44
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Fri Jun 22 15:56:37 2012 +0200

    Add an option for Waiting for gdb connection if the gdb stub configuration is chosen.
    
    Here's a quick demonstration on how to use it(tested on M4A785T-M).
      (gdb) file ./build/cbfs/fallback/coreboot_ram.debug
      Reading symbols from [...]/build/cbfs/fallback/coreboot_ram.debug...done.
      (gdb) set remotebaud 115200
      (gdb) target remote /dev/ttyUSB0
      Remote debugging using /dev/ttyUSB0
      _text () at src/arch/x86/lib/c_start.S:85
      85		call	hardwaremain
    
    Change-Id: Ia49cbecc41deb061433bc39f5b81715da49edc98
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/1134
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bf00abf2adb4d91c190ab20925533879eaab9453
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Jun 22 11:07:25 2012 -0700

    romcc: fix up attribute((unused)) detection
    
    The length was not accounted for correctly.
    
    Change-Id: If34f288ba9dee1cd19d60da1b9f3647b9593ac1f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1135
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit df28d9fe170b2d22f71045806e5fe6f3242c6de9
Author: Nico Huber <nico.huber@secunet.com>
Date:   Tue Jun 19 10:27:00 2012 +0200

    libpayload: Adjust timeouts and delays in OHCI driver
    
    This sets the timeout for control and bulk transfers to 2s per
    transfer descriptor (like we set it in the EHCI driver). It also adds
    delays around the disabling of control and bulk list access to
    overcome some race conditions.
    
    Change-Id: Ia2d1db890fca51c7d9477de163d55030e0c5a04a
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1127
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit efb479c08bc1b03838c6493324d11d6164c78861
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Jun 22 08:53:36 2012 +0200

    ROMCC: fix unused attribute lookup
    
    commit 57cd1dd29679918afa650c2a7e82a474765f357d added this attribute,
    but with wrong length, so it actually never matched.
    
    Change-Id: Ibcc7816b5fa895faa66710cc29de38f129be6a2b
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1133
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit d8a6680073179e1f7a357ee02e3d9d5103b78eb4
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jun 21 11:21:23 2012 +0200

    libpayload: Add check for failure in usb_attach_device()
    
    This adds a simple check if a device is really configured before
    returning it's address to the usb hub driver who wants to attach it.
    
    Change-Id: I6fea140217c3e7468cc48ef7c3cbf2be8d11f47a
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1131
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 445a3a04d8cb388786bbe8f997bf2034521dea09
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jun 21 10:52:49 2012 +0200

    libpayload: Shutdown reasonably if we can't init usb msc device
    
    This lets the init of usb mass storage return if the device
    configuration is unusable. Also add some checks for proper shutdown so
    we don't free/remove an uninitialized device.
    
    Change-Id: I6daf9b38e632b6e381bcd5a7717f0f1a3150b64a
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1130
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 57cd1dd29679918afa650c2a7e82a474765f357d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 21 17:21:08 2012 -0700

    Teach romcc about attribute((unused))
    
    This makes it easier to use the same code on romcc and gcc.
    Specifying attribute((unused)) on romcc does nothing.
    
    Change-Id: If9a6900cad12900e499c4b8c91586511eb801987
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1132
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 274c63e367aacbd50fb35f25da896fead08a6c3d
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Jun 20 14:58:21 2012 +0200

    libpayload: Add support for interrupt transfers in OHCI
    
    This adds support for usb interrupt transfers to the OHCI driver.
    Basically this enables support for HID keyboard devices.
    
    For each interrupt transfer endpoint, two queues of transfer
    descriptors (TDs) are maintained: the first with initialized TDs
    is linked to the periodic schedule of the host controller (HC), the
    second holds processed TDs which will be polled by the usb class
    driver. The HC moves processed TDs from its schedule to a done queue.
    We periodically fetch all TDs from the done queue, to put them on the
    queue associated with the endpoint, where they can be polled from.
    Fully processed TDs (i.e. which have gone throuch all of this) will be
    reinitialized and put on the first queue again.
    
    Change-Id: Iaab72c04087b36c9f0f6e539e31b47060c190015
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1128
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 542fe85da956c62e46da1d9cfeb79c3d06b75427
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Jun 20 11:37:17 2012 +0200

    libpayload: Fix initialization of OHCI driver
    
    This fixes some memory corruption, leaking and padding issues within
    the initialization of the OHCI driver.
    
    Change-Id: If6891f2a53e339d32c4324f4c9e0b1ed07596a60
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1126
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 9951adeffd02c0226c5dd9dcbddbab9d86e28ee4
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Jun 20 10:08:06 2012 +0200

    libpayload: Implement correct done queue processing for OHCI
    
    This adds correct processing of the done queue of the OHCI host
    controller (HC). We will always process the done queue after a control
    or bulk transfer. Unfortunately, it's hard to tell when the HC will
    write out the done queue, so we have do free the transfer descriptors
    later and have to allocate them one by one.
    
    To distinguish different types of TDs (e.g. async vs. interrupt
    transfers) on the done queue, they are flagged in the lsb of there
    .config field. We can utilize this bit for our own purpose, as it's
    reserved and the host controller won't interpret it and preserves its
    state.
    
    Change-Id: I3b2271ae6221cdd50fc0f94582afdfe52bf7e797
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1125
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit ac8d5508541874b60aae6363f50e56f7df40b27f
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed Jun 13 15:49:09 2012 +0200

    libpayload: Correct interchanged parameters in OHCI driver
    
    In ohci_private.h some invocations of a MASK macro were called with
    its parameters interchanged. This fixes it with the hope not to break
    anything nasty.
    
    Change-Id: I56cb483b208442b497dbd32ce993cc53d1fba1e5
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1122
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 79e1f2fa010173a81b891044085bf6a0a3a672fb
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Jun 1 09:50:11 2012 +0200

    libpayload: Detach unresponsive usb mass storage devices
    
    This enables logical detachment of unresponsive usb devices (i.e.
    devices not responding to control transfers) in the usb mass storage
    driver. Without the detection of unresponsive devices we wait way too
    long for the device to become ready.
    
    Change-Id: I8b8cf327f49dde25afaca4d3066f16ea86b99d3d
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1121
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3ca35cae354305003bcc5d14549a247247726e61
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jun 14 13:27:39 2012 +0200

    libpayload: Add dummy queue heads to EHCI interrupt frame list
    
    This introduces a dummy queue head in the interrupt frame list of the
    EHCI host controller. It's a workaround for broken controllers which
    follow pointers from this list even if the terminate bit is set.
    Fortunately, they do honor the bit in queue heads and having an empty
    QH in the list doesn't violate the standard.
    
    The linux kernel has a similar workaround for AMD SB700, SB800, and
    Hudson-2/3 platforms. We observed this bug with an AMD SB600.
    
    Change-Id: Ibbb66dea5fddc89c7995a24d746bedf6bfa887be
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1124
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 0d120f8ee25cfeb0c87024aff8c1f81d0b64bbb4
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jun 14 13:08:36 2012 +0200

    libpayload: Add interrupt-queue underrun recovery to EHCI
    
    If the queue of an interrupt transfer runs out, we have to reset
    the queue head. This also introduces the use of a spare transfer
    descriptor (TD) in interrupt queues, which assures, that a processed
    TD  won't be reused until the host controller has written it back
    from his overlay.
    
    Change-Id: Id0eeb2808b77f1c187f164eb34bd66f8f399938b
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1123
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit cef86927e846409f7c4018d6c1f9ad1d89b9269b
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri Jun 1 08:54:29 2012 +0200

    libpayload: Adjust timeout in EHCI driver
    
    Tested with a bunch of usb flash sticks. The slowest non-TUR (test
    unit ready) turn around took about 1.3s, so this commit increases the
    timeout to 2s.
    
    Change-Id: Iec64b5cc48d51912b2bdeeebb5885399a71311b2
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1120
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dab6bfe97d3588b73f7a3f7b9411cfa0e221f916
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 16:25:55 2012 +0200

    i3100: Enable second IOAPIC for PCI-X
    
    i3100/i5000 have a second IOAPIC which handles IRQs for PCI-X.
    Add code to enable it.
    
    Change-Id: Ib447628f501b152c8adc9c7c89bd09b5615b9e5a
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1118
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2e33a65a8c115a46fdf6101ac57fd89602d1b264
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Wed Jun 20 04:03:37 2012 +0400

    libpayload: reg_base reading for USB EHCI driver
    
    Added reading registers base address for USB EHCI driver
    in ehci_init() function.
    
    Change-Id: I59443ca9823588d70822b4f14486caf217a5ac26
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1106
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 904a0ec9d0ae4f4af8bcb13363d6766a6feace6a
Author: Nico Huber <nico.huber@secunet.com>
Date:   Thu Jun 14 16:03:01 2012 +0200

    Don't use 64-bit constant 0x100000000 in linker scripts
    
    The constant value 0x100000000 is used in linker scripts to calculate
    offsets from the end of 32-bit-addressed memory. There is nothing
    wrong with it, but 32-bit versions of ld do the calculation wrong.
    
    Change-Id: I4e27c6fd0c864b4d98f686588bf78c7aa48bcba8
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1129
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 14546853274bb21a760230ef5570d03bcb43430f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 16:59:15 2012 +0200

    i5000: fix another typo
    
    As Mathias Krause pointed out, using movw/outw on %al is clearly invalid.
    Let's do another typo fix...
    
    Change-Id: Ib95832a11097f599a236ab30c64c26ef429a1699
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1119
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit 43b9f32d20a41d108d936b776ddfec9d47ad364a
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon May 21 14:05:41 2012 +0200

    libpayload: Better error detection in USB mass storage
    
    This implements status transport (CSW) more closely to the standard
    (usbmassbulk_10).
    
    Change-Id: Ife516316e054d4e87ebe698dc487eeb9ebcfd38d
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1072
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 421303a25aef04bb3d5431a4e6f4f6215bc772fe
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Wed Jun 20 03:57:18 2012 +0400

    libpayload: Fix detach_contoller in the USB driver
    
    Fixed usb controllers linked list walking in
    detach_controller() function
    
    Change-Id: Ia97c7ec814f75d2b1bfe185f160fb4cd32aa6fdb
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/1105
    Tested-by: build bot (Jenkins)
    Reviewed-by: Nico Huber <nico.huber@secunet.com>

commit 39b47d2b03c714ee49b96ba65e5d67ece5c33b7a
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 15:36:53 2012 +0200

    i5000: fix typos
    
    Peter and Ron pointed out two typos. They have no side effects, but
    it's still worth to fix them.
    
    Change-Id: I9aecccdbc72beb2623fbe558a06e4f1b050f6e74
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1117
    Tested-by: build bot (Jenkins)

commit 69eab16ce619c865988b892b857805598ca1779f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 10:38:21 2012 +0200

    mptable: realign comments with code
    
    Change-Id: I4bc90334c7220512607cd5e777ce1f8cc595e2f0
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1115
    Tested-by: build bot (Jenkins)

commit 2f8c4f829e7eab2563dfb9d17d8c93d9070f7c45
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 10:23:31 2012 +0200

    mptable: initialize apic/bus arrays with ARRAY_SIZE
    
    and increase the busses size to 32, as 16 isn't enough one some
    systems (i5000 for example)
    
    Change-Id: Ie09f451dd82ac25b0de85fd47807136e01da737b
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1114
    Tested-by: build bot (Jenkins)

commit 2fcc166fb89f85fc91bf5270a0d0973feb077cab
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 09:58:21 2012 +0200

    mptable: pretty print PCI INT entries
    
    make it more readable by adding INT defines and a left shift.
    
    Change-Id: I7db4d8c71ab4d705833019aa4cc2f11cef7d4fee
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1113
    Tested-by: build bot (Jenkins)

commit 4fbcaecf9a457d80eaf131a858617756c4f62376
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 10:01:47 2012 +0200

    mptable: Fix BUS type determination
    
    Change-Id: I7268b35671f6629601fa3b2a589054b8c5da5d78
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1112
    Tested-by: build bot (Jenkins)

commit b00c9a22577876724123468b9668d50d60bfff03
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 09:24:45 2012 +0200

    mptable: reindent code to comply with coreboot coding style
    
    Change-Id: Iee27c535f56ebedaceea542c2919cde68006827c
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1111
    Tested-by: build bot (Jenkins)

commit 09a180230a947e5d869323cd14e57820e967eae8
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 09:22:17 2012 +0200

    mptable: Fix 'mptable.c:1019:12: warning: ‘c’ may be used uninitialized in this function'
    
    Change-Id: Icf6968f5bcbbe28c3a2a1d6ee7c1fd0be583f182
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1110
    Tested-by: build bot (Jenkins)

commit 57f524fd62ab9b76dd4850e907dcbd338eb7706f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 09:14:08 2012 +0200

    mptable: remove unused variable
    
    Change-Id: I1ff7e040b5aafcdb05a3669158ae94551981e747
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1109
    Tested-by: build bot (Jenkins)

commit 9b860165bac4153517f46d655e5f67a25326214b
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 08:57:11 2012 +0200

    mptable: print ioapic entries
    
    Print IOAPIC entry based on actual data, instead of giving the user
    the feeling that the generated ioapic entry has any relation to reality.
    If the IOAPIC entry in the MPTABLE is incorrect, the user will notice
    it anyways. But adding a static entry (which might be also incorrect)
    is even worse.
    
    Change-Id: I6d0012324a9e6c7d22436ada36cbd3a4f7166f5c
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1108
    Tested-by: build bot (Jenkins)

commit 0b879f838f294f3908fa86ed75bd53b9fe1ea3d4
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 20 08:54:51 2012 +0200

    mptable: rename LAPIC_ADDR to LOCAL_APIC_ADDR
    
    It was renamed in coreboot, so have mptable generate correct code.
    
    Change-Id: I9579209f9f47b756d8ccab63b6f942d22d53d79d
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1107
    Tested-by: build bot (Jenkins)

commit edac28ce65e48d6b2a0a2421d046a4fe4b2bf589
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jun 19 18:00:01 2012 +0200

    Enable Intel PECI on Model 6fx CPUs
    
    Those CPUs support the PECI (Platform Environment Control
    Interface), so enable it. This interface is commonly used
    for tasks like fan control.
    
    Change-Id: Id2dadc4821de8cc0b579e77235aa36892e57fd02
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1104
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 1a7a7e610e0fbc54fcc802bedbb31673dffff449
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 17 14:23:35 2012 +0200

    i5000: enforce hard reset
    
    Not doing a hard reset leaves the BOFL0 register cleared, which
    prevents the BSP selection from working. To make sure we start
    with known values, use the SPAD0 register for soft reset detection.
    If there's a value other than 0, do a hard reset.
    
    Change-Id: I390e3208084cfd32d73cce439ddf2bc9d4436a62
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1103
    Tested-by: build bot (Jenkins)

commit ec6f043c253355483bd065c39adc91bad2647ee9
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Thu Jun 14 14:19:09 2012 +0200

    llshell: fix build without romcc
    
    Without that fix we have:
          LINK       cbfs/fallback/romstage_null.debug
      build/generated/crt0.romstage.o: In function `ramtest':
      romstage.c:(.rom.text+0x53f): undefined reference to `.Lhlt'
      collect2: ld returned 1 exit status
      make: *** [build/cbfs/"fallback"/romstage_null.debug] Error 1
    On the M4A785T-M which doesn't have CONFIG_ROMCC.
    
    Change-Id: I49eded1d18e996afe9441b85dae04ae30c760dd6
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/1101
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 9aa43892e6899b719fe7f4754901a0eae379a934
Author: Martin Roth <martin@se-eng.com>
Date:   Fri May 25 12:23:32 2012 -0600

    Update SB800 CIMX FADT
    
     - Add #define to allow the FADT PM Profile to be overridden.
     - Change the location of the PMA_CNT_BLOCK_ADDRESS to match
       current documentation.
     - cst_cnt should be 0 if smi_cmd == 0
     - add a couple of default access sizes.
     - Add a couple of #define values for unsupported C2 & C3 entries.
     - Add PM Profile override value into amd/persimmon platform.
       This does not use the #defines in acpi.h so that the files that
       include this don't all need to start including acpi.h.
    
    Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094
    Signed-off-by: Martin L Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1055
    Tested-by: build bot (Jenkins)
    Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 0860e723cb40b82a9f7cc2652891499e0161d89e
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 10 19:03:36 2012 +0200

    udelay: add missing bus frequency
    
    commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency
    detection on Sandybridge") reworked the udelay code, but didn't add
    the 333MHz FSB entry used on Model 15 Xeons.
    
    Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/1099
    Tested-by: build bot (Jenkins)

commit bb1c42b92037dc3dbbb639a1140dd284e978c595
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon May 21 14:23:03 2012 +0200

    libpayload: Add timeouts in the UHCI USB driver
    
    We should always have some timeout when we wait for the hardware. This adds
    missing timeouts to the UHCI driver.
    
    Change-Id: Ic37b95ce12ff3ff5efe3e7ca346090946f6ee7de
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1073
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c43e736c0ccd26fbfea11c19d5140ea1cc30d90d
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon May 21 13:59:43 2012 +0200

    libpayload: Fix an integer overflow in USB mass storage
    
    Change-Id: I3d618497016478ea727c520e866d27dbc3ebf9af
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1070
    Reviewed-by: Mathias Krause <minipli@googlemail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0421dc84dfba3b4eaa045b595320d6468b3206ef
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon May 21 14:53:43 2012 +0200

    libpayload: Add timeouts in the EHCI USB driver
    
    We should always have some timeout when we wait for the hardware. This adds
    missing timeouts to the EHCI driver.
    
    Change-Id: I13ba532a6daf47510b16b8fdbe572a21f1d8b09c
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1077
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit afe86c0b74cc7f5dcaefc34155daf299e8377353
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon May 21 14:46:26 2012 +0200

    libpayload: Add timeouts in the OHCI USB driver
    
    We should always have some timeout when we wait for the hardware. This adds
    missing timeouts and a more standard compliant port reset to the OHCI driver.
    
    Change-Id: I2cfcb1039fd12f291e88dcb8b74d41cb5bb2315e
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1076
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5e3428ea2093e028c7f976b69032b1882e10e6ca
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon May 21 14:41:49 2012 +0200

    libpayload: Remove orphaned delay from OHCI USB driver
    
    This removes a synthetic delay of 5ms from every OHCI USB command.  A delay
    here seems to be of no use and first tests have shown no glitches.
    
    Change-Id: Ie72b2d49e6734345708f04f3f7b86bacc7926108
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1075
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 62eb5b3837c51228898288cb7347dce81c563842
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri May 25 10:09:13 2012 +0200

    libpayload: Add support for interrupt transfers in EHCI
    
    This adds support for usb interrupt transfers in the EHCI driver. Split
    transactions are supported, so this enables support for HID keyboards
    devices over hubs in high-speed mode.
    
    Change-Id: I9eb08f12b12c67ece10814952cb8651278b02f9d
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1083
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4842dfe6f77c21f7074ca79b0ce3f882f08f92b2
Author: Nico Huber <nico.huber@secunet.com>
Date:   Fri May 25 09:59:19 2012 +0200

    libpayload: Free intr queue structure in usb_hid_destroy
    
    The call to destroy_intr_queue was missing in usb_hid_destroy.
    
    Change-Id: I51ccc6a79bc005819317263be24a56c51acd5f55
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1082
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1ab6075320f5dc10afd934b100c8116a88ac12fc
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed May 23 09:21:54 2012 +0200

    libpayload: Add support for split transactions in EHCI
    
    With split transactions, the EHCI host controller can handle full- and
    low-speed devices on hubs in high-speed mode. This adds support for split
    transactions for control and bulk transfers.
    
    Change-Id: I30fa1ce25757f33b1e6ed34207949c9255f05d49
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1081
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d5d024f3e5f0eb88e459b3a449337c3cd2a49104
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon May 21 16:20:59 2012 +0200

    libpayload: Bring USB hub driver to a working state
    
    This adds proper device attachment and detachment detection and port enable-
    ment to the USB hub driver. Support for split transactions is still missing,
    so this works only with USB2.0 devices on hubs in USB2.0 mode and USB1.1
    devices on hubs in USB1.1 mode.
    
    Change-Id: I80bf03f3117116a60382b87a4f84366370649915
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1080
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c95da25ac6993a4cbccb23e60576ce0c0f350af1
Author: Raymond Danks <ray.danks@se-eng.com>
Date:   Wed May 30 16:03:48 2012 -0600

    Improve parsing of --cpu parameter in abuild script.
    
    * -c "" need never be tested if getopt params are handled; fail abuild script when getopt parsing fails
    * use expr to resolve numeric test fails with -c max
    * cpus variable may be being passed in the environment.  Don't overwrite MAKEFLAGS if it is not.
    
    Change-Id: I96236ef719a1a9f942b8e15bfcf015d60068e58a
    Signed-off-by: Raymond Danks <ray.danks@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1068
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bdca15337bc9337f399b43290dc74cb598c5ec4d
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon May 21 14:01:52 2012 +0200

    libpayload: Remove orphaned delay from USB mass storage
    
    This removes a synthetic delay of 10ms from every mass storage command.
    A delay here seems to be of no use and first tests have only shown a
    huge speed increase.
    
    Change-Id: Ida7423229373ec521d4326c5467a3f518b76149c
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1071
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7250f0365d87d18e789f8fc5c203a7657aa75544
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed May 30 14:50:53 2012 +0200

    Enable CONFIG_GFXUMA for roda/rk886ex
    
    Without GFXUMA beeing set, MTRR initialization runs out of variable MTRRs.
    
    Change-Id: I5d1aa0d5fa2d72f17a0d88cae3fad880b489828c
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1086
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 14f61424d04b881c2b03c84b3098c8a35611dd78
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon May 21 14:38:08 2012 +0200

    libpayload: Disable some buggy debugging code
    
    This disables some debugging code in the OHCI USB driver which causes
    reboots under rare circumstances.
    
    Change-Id: Ic274c162846137ee00638ffbc59ccf1d8130586f
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1074
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e28a61550c5f33d7636ee8f03f6bb7307475fb3e
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Tue May 29 14:28:26 2012 +0200

    libpayload: fix OHCI IN commands
    
    Due to operator precedence incomming USB commands were missing some
    flags.
    
    Change-Id: I87ef51590c9db7a6cbc7304e1ccac29895f8a51e
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/1084
    Reviewed-by: Mathias Krause <minipli@googlemail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7b7b5666f0d286989402c2372cafb4e02e130dae
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Tue May 29 16:19:19 2012 +0200

    libpayload: fix UHCI timeout
    
    UHCI commands should have a timeout of 30ms, not 30s!
    
    Change-Id: Iebcf338317164eb1e683e1de850ffab5022ca3a1
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/1085
    Reviewed-by: Mathias Krause <minipli@googlemail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5c4e7aa9e5914293877ef98e007d46732666cfaf
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon May 21 14:56:21 2012 +0200

    libpayload: Correct port power settings for EHCI root hub
    
    Enable power on EHCI root hub ports only if the controller supports it.
    Wait 20ms for the power to become stable.
    
    Change-Id: I8897756ed2bfcb88408fe5e9f9e3f8af5dd900ac
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1078
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5f595cb6ebd8edddb1e253353753bf1c5433395e
Author: Nico Huber <nico.huber@secunet.com>
Date:   Mon May 21 16:19:05 2012 +0200

    libpayload: Add clear_feature() function to USB framework
    
    This function will be used by the USB hub driver.
    
    Change-Id: I4d1d2e94f4442cbb636ae989e8ffd543181c4357
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1079
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cefec0ea8c436f36a2fd71b58364d4a65f52948a
Author: Nico Huber <nico.huber@secunet.com>
Date:   Wed May 16 15:04:27 2012 +0200

    libpayload: Fix b0b4a52b70f0d7c09241f0f718a179fc55d85179
    
    The removal of bitfields came with some glitches in the UHCI driver. This
    fixes it.
    
    Change-Id: Iba8ea3b56b03c526eca7b6388c019568e00be6f5
    Signed-off-by: Nico Huber <nico.huber@secunet.com>
    Reviewed-on: http://review.coreboot.org/1069
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ee8a9f6c5548729cd1e464ccbecfca7a08fcc9a2
Author: zbao <fishbaozi@gmail.com>
Date:   Tue May 29 14:59:38 2012 +0800

    Initializer of a static member in union.
    
    It is just me or does anybody have the same build error without
    this patch?
    ------
    src/arch/x86/boot/acpigen.c: In function 'acpigen_write_empty_PTC':
    src/arch/x86/boot/acpigen.c:347:3: error: unknown field 'resv'
    specified in initializer
    src/arch/x86/boot/acpigen.c:347:3: warning: missing braces around
     initializer
    src/arch/x86/boot/acpigen.c:347:3:warning: (near initialization
     for 'addr.<anonymous>')
    -------
    
    Anyway, I believe at least this will cause warnings.
    "resv" is a member of a union, not of acpi_addr_t. So it should be
    wrapped by a brace in the initializer.
    
    Change-Id: I72624386816c987d5bb2d3a3a64c7c58eb9af389
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/1056
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 2dbfcb750fca720fcd415f8cd032eb1cf888ce46
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 30 16:26:30 2012 +0200

    sconfig: Some fixes
    
    clang complained about a missing include and wrong fprintf use.
    
    Change-Id: Idc023b653e694147c624d5f8f9ed3b797c462e9f
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1067
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7c2d058d61f53d5b739fbde8e1c63b59776e9c0b
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sat May 26 00:13:22 2012 +0200

    Fix the location of "Setting variable MTRR" printk.
    
    Without that fix the debugging is harder because the person debugging
      coreboot will see the following twice(note the repeated MTRR number):
        Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
        [...]
        Setting variable MTRR 1, base: 4096MB, range:  512MB, type WB
        Setting variable MTRR 1, base: 4608MB, range:  256MB, type WB
        Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC
      instead of the following twice:
        Setting variable MTRR 0, base:    0MB, range: 4096MB, type WB
        [...]
        Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC
    
    Thanks to kmalkki on #coreboot's Freenode IRC channel for the idea:
      May 25 23:57:17 <kmalkki>	I would add (move) that "Setting variable MTRR..." debug at the end of set_var_mtrrs()
    
    Change-Id: I9f4b7110ba34d017a58d8cc5fb06a7b1c3d0c8aa
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/1058
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

commit 3b3a1a1ee65087d5b894e964f5bc4615c07389ae
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue May 15 14:18:59 2012 -0700

    Provide functions to access arbitrary GPIO pins and vectors
    
    This change adds utility functions which allow to read any GPIO pin,
    as well as a vector of GPIO pin values.
    
    As presented, these functions will be available to Sandy Bridge and
    Ivy Bridge systems only.
    
    There is no error checking: trying to read GPIO pin number which
    exceeds actual number of pins will return zero, trying to read GPIO
    which is not actually configured as such will return unpredictable
    value.
    
    When reading a GPIO pin vector, the pin numbers are passed in an
    array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a
    three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass
    pointer to array of {4, 2, 15, -1}.
    
    Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1049
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 691c9f0dab96c1d5f4bbccb0991feb39e8986746
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 23 11:18:35 2012 -0700

    Add support for Panther Point to SPI driver
    
    Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1048
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 68b5da0e680b9066afa3bbff9e1ef99d2c7df720
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Mar 11 20:15:21 2012 +0100

    Use ld manually when compiling with clang
    
    clang does its own linking, incompatible to our
    binutils-centric linker magic.
    
    Change-Id: I243597adcb6bc3f7343c3431d7473610c327353d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/785
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bb31f3a24ac0cf5bcc9f5342733de7fbc09299e2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri May 11 16:30:54 2012 -0700

    Drop config variable CPU_MODEL_INDEX
    
    It's only used in the ACPI generator for Sandybridge/Ivybridge CPUs
    and the code can easily be changed to not rely on any Kconfig magic.
    
    Change-Id: Ie2f92edfe8908f7eb2fda3088f77ad22f491ddcf
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1047
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 14b23a6ca60728520ddac91cdbe840919618d7b8
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 22 15:24:51 2012 -0700

    Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled
    
    Right now coreboot compilation fails when SPI flash debugging is
    enabled. Fix it by using the right set of memory functions.
    
    Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1044
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 71695d8a28f6081dc63a06203f68a5365aa9af97
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Thu May 17 17:21:27 2012 -0700

    Fix full reset for Ivy Bridge platforms
    
    Experiments have shown that writing plain value of 6 at byte io
    address of 0xcf9 causes the systems to reset and reboot reliably.
    
    Change-Id: Ie900e4b4014cded868647372b027918b7ff72578
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/1050
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 984f9540c0ac2fe25d6057134b86aeca4a091803
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 23 14:20:18 2012 -0700

    ChromeOS: Remove remnants of FDT support
    
    Originally, on ChromeBooks, coreboot would provide a modified
    u-boot device tree (FDT) to u-boot in CBMEM. However, u-boot
    can now create all the information it needs from the coreboot
    table and add it to its device tree itself. This means we can
    drop this (anyways unused) code.
    
    Change-Id: I4ab20bbb8525e7349b18764aa202bbe81958d06a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1052
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 88fc0b9e8da89cd41350ca0ac54297f2ebf3bf10
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 23 14:16:47 2012 -0700

    Sandybridge: Remove remnants of FDT support from MRC cache code
    
    Originally, ChromeBooks would get the offset of the MRC cache
    from an entry in the u-boot device tree. Not everyone wants to
    use u-boot on Sandybridge systems, however.
    Since the new code (based on Kconfig) is now fully working, we
    can drop the u-boot device tree remnants.
    
    Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1051
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6e901fd3d267fafe97bb8404702919ce5e21a0e1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 23 11:21:10 2012 -0700

    Sandybridge: Fix MRC cache calculation
    
    The MRC region is described by Kconfig variables, no further math
    or parsing is required at this point.
    
    Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1046
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 206c890f6a497eef212f12077d15f0832824095b
Author: Motiejus Jakštys <desired.mta@gmail.com>
Date:   Tue May 1 21:47:16 2012 +0100

    Enable USE_OPTION_TABLE for ThinkPad X60
    
    Without this option bluetooth configuration value in nvram is not
    consulted properly.
    
    It also enables built-in volume control (read-only).
    
    Tested on: ThinkPad X60s, 1702.
    
    Change-Id: I2fc6bb527c6e086a083e63922d1253eda7d4a36d
    Signed-off-by: Motiejus Jakštys <desired.mta@gmail.com>
    Reviewed-on: http://review.coreboot.org/985
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit bfff6dea2b1190e3e6476ab4c7379fe0f56d3680
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 15 13:28:07 2012 -0700

    Implement %zu / %zd in printk
    
    The SPI drivers from u-boot make heavy use of %zu/%zd (size_t/ssize_t).
    Implement this in our printk implementation so we get useful output.
    
    Change-Id: I91798ff4f28b9c3cd4db204c7ec503596d247dcd
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1043
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 56c7dc797246bf4e82879de23436783bbbe54b77
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 15 12:36:57 2012 -0700

    Move subsystem IDs to devicetree.cb
    
    A while back coreboot was changed to read the subsystem IDs from
    devicetree.cb to allow each onboard PCI device to have its own
    subsystem id. When we originally branched, this was not the case,
    and the sandybridge/ivybridge mainboards have not been updated yet.
    Also, drop the subsystem ID from Emerald Lake 2, since it's not a
    Google device.
    
    Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1042
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5649b08e20413f21308951b72c583e926fe2d1f1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 23 11:03:29 2012 -0700

    Reduce default verbosity of SPI flash drivers
    
    Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled.
    
    Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1045
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8ea5a34833dd8acf21fd9756b4bcbb37333a42b9
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 14 13:52:32 2012 -0700

    Fix printk types in SPI flash drivers
    
    - use %zu instead of %zd for size_t (%zd is for ssize_t)
    - use %x instead of %lx for u32
    - break some long lines to avoid commit hook trouble
    
    Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1041
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 872e74dda256e0a81644b8e7f06110e0e1652ceb
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Fri May 25 12:20:10 2012 -0600

    Fix typo on Persimmon #if CONFIG_HAVE_ACPI_RESUME
    
    Stupid typo: APCI instead of ACPI in Persimmon.
    
    Change-Id: I6fd7f091cf1f5c4c0e1b57c21553dab93b545eab
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1054
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 9981cad80173510a2070ab884cf63c9cca51e69b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 24 13:36:30 2012 -0700

    nvramtool: use C99 PRIx64 / PRId64 for uint64_t variables
    
    In printf/printk, using %lld or %ld for uint64_t will warn on either
    64bit or 32bit machines.  However, C99 defines PRIx64 / PRId64 to
    provide the right modifiers for printing uint64_t variables. Use them
    instead.
    
    Change-Id: I68df5d069a1e99d1a75885173ddfd7815197afea
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1053
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0e740d3952c978babe7f6b7b8110113170b02c08
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 14 13:21:08 2012 -0700

    Fix size_t for certain versions of GCC
    
    When compiling coreboot with the latest ChromeOS toolchain, GCC
    complains that some printk calls use %zu in connection with size_t
    types since it resolves the typedefs to long unsigned int.
    
    The problem is solved by using the GCC built-in __SIZE_TYPE__ if it
    exists and define __SIZE_TYPE__ to long unsigned int otherwise.
    
    Change-Id: I449c3d385b5633a05e57204704e981de6e017b86
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1040
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1b1309f289d6fc9f6ec348686665d25218535030
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri May 11 15:53:43 2012 -0700

    Add EM100 mode to Intel Firmware Descriptor tool
    
    To avoid having two copies for every firmware descriptor (one for
    EM100 use and one for real SPI flash use), add an EM100 mode to
    ifdtool that allows to "dumb down" a fast image to the settings
    required for the EM100 to work.
    
    Change-Id: I0ed989f0a49316bc63d8627cb5d4bd988ae7a103
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1039
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 89ba15a0c176f8c6966938cba290da8a8bd9d714
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri May 11 12:58:11 2012 -0700

    chromeos: Fix compilation of coreboot-utils package
    
    The ChromeOS build system provides a set of CXXFLAGS, however those do
    not contain -DCOMPACT. This breaks the compilation of cbfstool in
    coreboot-utils.
    
    This fix overrides CXXFLAGS so that coreboot-utils compiles again.
    
    Change-Id: If9495bdd815fe2cdaeba5386afa953558742467b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/1038
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f0269127760f1081c3df47aa93b5946d6af411df
Author: Steve Goodrich <steve.goodrich@se-eng.com>
Date:   Fri May 18 11:18:47 2012 -0600

    Converted the FRAMEBUFFER_VESA_MODE to a choice.
    
    Being a diligent soul, I changed the "enter a numeric value for the
    mode you want" option to a choice of common modes.  New modes can be
    added quite easily.
    
    Change-Id: I8cf4572c2d36ced6549541ec173c0c02d8eaca4a
    Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1036
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 92ff934e0bfd9b850c2335ee5439f04325b85347
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon May 21 20:10:04 2012 +0200

    abuild: Disable abuild-level parallelism for now
    
    It still failed because make touches files it isn't
    supposed to touch.
    
    Change-Id: I5a6ceaa9d5da212c1e34b121cf39fa9d27964747
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1037
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 2f00ce3d964e56e2bf3f45033451f0e44c69d78d
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Sat Apr 21 23:47:56 2012 +0530

    cbtypes.h: Unify cbtypes.h used in AMD board's code
    
    Remove all the repeated sections of code in cbtypes.h and place it
    in a common location. Add include dir in vendor code's Makefile.
    
    Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/912
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit ad422c0a7a90093fd14b386cf8f0802fce64b2cb
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue May 15 16:08:24 2012 -0600

    Fix Persimmon build without S3.
    
    In the heap function, only check for S3 check when it is built in
    with CONFIG_HAVE_ACPI_RESUME.
    
    Change-Id: I439275a4e1b7b446b499bcf90c925785a14b980d
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1034
    Tested-by: build bot (Jenkins)
    Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ba3711cc24adbef23e65d398dd651143d21666a4
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Sat May 12 09:56:45 2012 -0600

    Fix fadt legacy free setting.
    
    The fadt legacy free logic was backwards.
    
    Change-Id: Ieb21ef335f7514ced70248d0bf8668ddb73cf59f
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1030
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 762aa3e19992f061696f692645c7f5aa99bddb39
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Fri May 11 13:23:45 2012 -0600

    Change the name of the romstage bootblock.ld
    
    The bootblock.ld linkerscript is used by romstage. Name it
    accordingly to avoid confusion.
    
    Change-Id: I7ca9147bb821fe6f83224d170f5fe25654ef250f
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1031
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 49fe74bd693d02211ce6c34225ab142de988c59f
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Mon May 14 16:20:26 2012 -0600

    Fix Cygwin bootblock generation
    
    Cygwin is case insensitive, so bootblock.s and bootblock.S in the
    same directory cause a build failure. This changes bootblock.S
    to bootblock_inc.S, as it is generated from bootblock_inc.
    crt0.S and crt0.S also had this problem. This changes crt0.S to
    crt0.romstage.S.
    
    Change-Id: I29d230a93b0743e34f11228f9034880ceaf7ab7b
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1032
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit c2dff7fd44aa7d89d93e1c480109e1fc2362494c
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Mon May 14 21:06:10 2012 -0600

    Pass IASL to SeaBIOS
    
    Use the coreboot IASL for building SeaBIOS.
    
    Change-Id: Ia6c802b090d53b7fbbc8ddb6edad3de6b822ff41
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1033
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 20959ba21baf0e56aea505d090e79df37fa9e695
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 12 23:30:36 2012 +0200

    SPI driver: style fix
    
    lint tests for labels to start at BOL, no spaces before them.
    
    Change-Id: Icf6ce533f26998a81b4be46d17e2d0b6b868904d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1029
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5fb2b5cdacb1c76f4661cb34d7159fd266998d10
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 12 23:25:23 2012 +0200

    crossgcc: Test for m4 and bison
    
    Happened way too often that crossgcc failed
    because m4 or bison wasn't installed already.
    
    Change-Id: Ibcca2183edd5db20608015e3898f8fff9a6d11e8
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1026
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6e61ad347c829088f25d42a88f055d1f999d71c1
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 12 23:19:30 2012 +0200

    crossgcc: update sources
    
    Update GNU project versions, download GNU project tarballs
    using ftpmirror.gnu.org (http, picking close servers).
    
    Update ACPICA tarballs, ignore https certificates for all
    downloads. Not very useful, but breaks ACPICA download.
    
    Change-Id: I4aa8b08836346d031793a006b20b741d86e48988
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1025
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Raymond Danks <ray.danks@se-eng.com>

commit 64d9a7784e1db8a8af7621ecb71492d8d5c9cb67
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue May 1 15:14:46 2012 +0200

    abuild: Move configuration handling together
    
    Handling user options was spread out across the code.
    Collect as much as possible in the getopt loop.
    
    Change-Id: I4979a14988da000c008e155023b960535b529b41
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1028
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2ea8e8685666248d945be63a79977568815c2bf2
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Jan 10 21:59:08 2012 +0100

    abuild: Remove abuild.info hack
    
    abuild used to allow boards to override certain environment
    variables using a file called abuild.info.
    This isn't used, this isn't needed. Drop it.
    
    Change-Id: Ic93748f602bf0c354ff1f3be25a050e1cb469256
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1027
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7c9ef4f52ca5d02fe52f1b0673bc0536c84ae359
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Thu May 10 11:02:32 2012 -0600

    Add legacy free setting and override to fadt.c
    
    The FADT iapc_boot_arch indicates the available information
    for accessing legacy devices. By default, the setting supports
    legacy. LEGACY_FREE and/or the iapc_boot_arch field may be
    customized.
    
    Change-Id: I5679741e1f8db923d3c00b57f6a5d813550f3a5e
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1024
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit b547c4fc990c166e2b488196b1af56691852c976
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Wed May 9 15:34:49 2012 -0600

    Merge sb800 fadt fixes from South Station mainboard to southbridge fadt.
    
    The South Station recieved updates that fix a number of fadt problems.
    South Station now uses the southbridge fadt.
    
    Change-Id: Ib990a69a359a4b7eae3431bb4323acd537acda1d
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1021
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit bb11e60cb2f40da2a5a59dfacda4d46119ddda24
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 10 12:15:18 2012 -0700

    Hook up MRC cache update
    
    Requirements:
      - must be in ramstage (locking flash while executing code from there
        might not work)
      - must be after cbmem is reinitialized (so the mrc cache copy of the
        current run can be found)
    
    Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1002
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1244f4b52fe423eeac2621672aa1786232f2ca0b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 10 11:31:40 2012 -0700

    Rework Sandybridge MRC cache handling
    
    - Separate Sandybridge from ChromeOS a bit
      The Sandybridge code depends on chromeos features a whole lot.
      As a first step, provide a code path to look up the MRC cache
      without depending on u-boot.
    
    - Move mrc cache handling to separate file
      This enables us to handle the MRC cache from ramstage,
      where we can write the flash safely (eg. to update the
      cache).
      Also teach it to lookup the current MRC cache from CBMEM,
      as the original data block isn't available anymore.
    
    After all the preparations, finally write to the SPI
    as necessary. It's a simple round robin wear levelling
    that erases the entire MRC cache region when it's full
    and starts from the beginning.
    
    Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1001
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1c56d9b1029b344b92bc1cd1acb2fe52ce0c0e2d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu May 10 11:27:32 2012 -0700

    Add SPI flash driver
    
    This driver is taken from u-boot and adapted to match
    coreboot. It still contains some hacks and is ICH specific
    at places.
    
    Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/997
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 43105d6a5a4898386e35c4fdccdf643b95faef98
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Nov 5 14:44:41 2011 +0100

    abuild: Build boards in parallel if possible
    
    Determine if xargs -P works. If yes, use that to build multiple
    boards in parallel, instead of relying on make -j X, when doing
    a full abuild run (instead of single boards).
    
    make -j X isn't able to make use of several cores at various
    serialization points in our build process, so this change results
    in a >25% speed up for a full abuild run in my tests.
    
    Change-Id: Id484a4211c84a3a24115278e0fbe92345f346596
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/409
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a495335de44eead583fc98455191d3da74ccd984
Author: Martin Roth <martin@se-eng.com>
Date:   Mon May 7 16:45:29 2012 -0600

    CIMx: Allow #define LEGACY_FREE overrides
    
    For legacy free AMD systems, the #define LEGACY_FREE cannot
    currently be overridden.  This patch allows the platform_cfg.h
    to override that.  (I know we want to get away from that, but
    for now...)
    
    Also allow BIOS_SIZE to be overridden on SB700 cimx based
    platforms.
    
    Change-Id: I570115248bcbc686062bfb66acb56208240b847a
    Signed-off-by: Martin L Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1018
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 923d200d1656df8ae1d8c79c6f0e1cf014d2ad1f
Author: Alec Ari <neotheuser@ymail.com>
Date:   Wed May 9 19:12:27 2012 -0500

    Unmark source files as executables
    
    Change source file modes from 755 to 644
    
    The following files have been grepped for changes:
    
    *.c
    *.h
    *Kconfig*
    *Makefile*
    
    Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c
    Signed-off-by: Alec Ari <neotheuser@ymail.com>
    Reviewed-on: http://review.coreboot.org/1023
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5db1f4666ebb07c4e987da24bf8e53ba8d538b1f
Author: Alec Ari <neotheuser@ymail.com>
Date:   Wed May 9 19:08:19 2012 -0500

    Integrate MA785GM-US2H to Kconfig
    
    MA785GM-US2H was left out of Kconfig. This
    allows the option to select the board.
    
    Change-Id: I9efea96c21dcd0754ab51824b410435b0b5300c2
    Signed-off-by: Alec Ari <neotheuser@ymail.com>
    Reviewed-on: http://review.coreboot.org/1022
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit eb129bbcb654d90c331b7898222d64f769c08437
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 9 21:07:17 2012 +0200

    Update SeaBIOS URL
    
    We have a http accessible SeaBIOS mirror at review.coreboot.org.
    Use it.
    
    Change-Id: Icce8e4f9ca1fa69966c82423b2b27057f15b30d2
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1020
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 76cfcbc312a8f58b78e710e629172fead8240130
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue May 8 23:22:34 2012 -0600

    Move fadt.c to the cimx sb800 southbridge directory to be shared.
    
    The fadt.c is the same across all the platforms using the sb800
    cimx southbridge wrapper.
    
    Change-Id: Ifbbfc238732aa46aef96297eaa188b77d27151f3
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/1019
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7b860ed45e44dc0428f82affe32db1201043eef6
Author: Martin Roth <martin@se-eng.com>
Date:   Sat Apr 28 10:25:20 2012 -0600

    Add simple PMIO & PMIO2 read/write routines to CIMX wrapper
    
    These are the PMIO & PMIO2 read & write routines from
    src/southbridge/amd/sb800/sb800.c & sb800.h for use in the cimx
    tree.  Currently most platforms using CIMX are calling WritePMIO()
    directly from the src/vendorcode/amd/cimx/sbX00 directories
    instead of using a wrapper function.
    These functions only do byte reads & writes.
    
    Change-Id: I881a6e2d4ddbba3dbdf4dd33e06313fe88b3682a
    Signed-off-by: Martin L Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/981
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4781800a66452ebfa2838dab89462dc0afd842e8
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 16:19:31 2012 -0700

    Don't loop infinitely long on serial comm failures
    
    If serial uart (8250/16x50) takes abnormally long to respond, give
    up on logging to serial console and instead let the system boot.
    
    Also reference bit in LSR register with correct name.
    
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    
    Ported from 9dd3ef165a1bf1bc404056d3e54337de1a15ac90 to
    uart8250mem.c:
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: Iaca4f57389c887110e6406d45053935891c96838
    Reviewed-on: http://review.coreboot.org/826
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit 564e90f57185274130aba7b157a7dca1941dcfef
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri May 4 15:37:18 2012 -0700

    Add a tool to work on i915 hardware in user mode
    
    This is the beginning of a tool that transforms the i9x5 code to user
    mode code. Consider this a very early stage although it does produce
    two programs. Requires spatch 1.0 or greater.
    
    To try it out, assuming you have an up-to-date spatch,
       sh transform
       make
       make broken
    
    Please don't fall to the temptation to auto-magicize this process.
    It's primitive for a reason. That said, suggestions welcome of course.
    
    Change-Id: I0188e36637b198b06c17f6d3c714d990e88bd57d
    Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
    Reviewed-on: http://review.coreboot.org/1003
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 44a89b34f85492c48a19db1b9b2c2c44ab29c9ae
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue May 1 12:10:45 2012 +0200

    Fix build with CMOS support on various platforms
    
    When bringing in nvramtool as build_opt_tbl replacement,
    various platforms where left in the cold that don't
    provide direct IO support from userland (or at least not
    in a way we support).
    
    Build nvramtool without CMOS support when done as part of
    a coreboot build. We don't need to touch CMOS in this case.
    
    Change-Id: Icc88d1d32f10384867a5d44b065f9aa119bb0d50
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/983
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit f8f00629e3b5e129a5962fed1b886034f45e844a
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 5 15:50:17 2012 +0200

    Some more #if cleanup
    
    Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO
    find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} +
    (manual tweak since it hit a false positive)
    
    Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO
    find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} +
    
    Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1006
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c0e16e7024fbeb11975f0834a5d5d6c0d9f2e34e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 5 15:11:22 2012 +0200

    Add config_enabled() from Linux
    
    This change is taken from Linux. It allows to check for Kconfig
    definitions in the preprocessor and source code using the same
    idiom.
    
    Long term plan is to remove our Kconfig hack to #define values to 0,
    and this helps.
    
    This includes a tiny modification to the macros to fix romcc support.
    
    Change-Id: I0fddbea8c8ca215cf226acf39cb329b0ba0445a5
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1005
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e166782f397f7db2c4446c5e120fa30afbde7bdd
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 5 15:29:32 2012 +0200

    Clean up #ifs
    
    Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
    find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
    
    Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
    find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
    
    Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
    find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
    
    Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
    find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
    
    (and some manual changes to fix false positives)
    
    Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/1004
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Martin Roth <martin@se-eng.com>

commit fe4221848f86ab97d2c439299826d97e48542404
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 2 16:33:18 2012 -0700

    Make CBFS output more consistent
    
    - Prefix all CBFS output messages with CBFS:
    - Add an option DEBUG_CBFS that is off by default. Without DEBUG_CBFS
      enabled, the code will no longer print all the files it walks for
      every file lookup.
    - Add DEBUG() macro next to LOG() and ERROR() to specify which messages
      should only be visible with DEBUG_CBFS printed.
    - Actually print a message when the file we're looking for was found. :)
    
    old:
    Searching for fallback/coreboot_ram
    Check cmos_layout.bin
    Check pci8086,0106.rom
    Check fallback/romstage
    Check fallback/coreboot_ram
    
    Change-Id: I2d731fae17a5f6ca51d435cfb7a58d6e017efa24
    Stage: loading fallback/coreboot_ram @ 0x100000 (540672 bytes), entry @ 0x100000
    Stage: done loading.
    new:
    CBFS: Looking for 'fallback/coreboot_ram'
    CBFS: found.
    CBFS: loading stage fallback/coreboot_ram @ 0x100000 (507904 bytes), entry @ 0x100000
    CBFS: stage loaded.
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/993
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 872eb793930258ac224e159aa789ab8bff74bf5f
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Oct 7 14:25:01 2011 +0200

    siemens/sitemp_g1p1: Drop debug code
    
    Change-Id: I40a4201b468131ba67e48ab68d62ca5413f2e2e8
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/1000
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2e2a68bbc84bb2c2574bd77c3442e0de4e0259a5
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu May 3 11:34:20 2012 +0200

    roda/rk886ex: Expose VGA devices in devicetree
    
    Otherwise set_subsystem isn't called for these (as they're not
    marked on_mainboard)
    
    Change-Id: I08e781735c59e4aa61009d2afa165d782f5a849e
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/998
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e204e2ae87ca734332178a4314c6d4e15c9b86d0
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu May 3 11:55:17 2012 +0200

    lint: Avoid downloading blobs repository
    
    The stable lint test "build-dir-handling" ran the build system
    in a way that made it download the blobs repository. Since this
    is part of the pre-commit hook, this might have kicked in with
    users desiring not to have them.
    
    Change-Id: I44a00137352c5966ff7fe2a030673276f6803908
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/999
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8a36634388c33b2d688ecd13fbe39a01e5de3135
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 2 16:39:56 2012 -0700

    Don't pre-enable SATA AHCI in romstage.c
    
    In a recent commit the SATA code of Panther Point / Cougar Point was
    changed to enable AHCI mode depending on the device tree settings rather
    than a hard code hidden in romstage.c. However, Emerald Lake 2 was not
    fixed up accordingly.
    
    Change-Id: I6c93f386509361e1ab5565b0e4d0e84f0ba282a2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/995
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d4bacf962c9e6185e7259eb4f7830bffca197e71
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 2 16:38:47 2012 -0700

    Print some useful debugging information in PSS table creation
    
    Change-Id: I1ec7a7e54513671331ac12f08d5f59161b72b0fd
    Example:
    PSS: 1900MHz power 35000 control 0x1300 status 0x1300
    PSS: 1600MHz power 28468 control 0x1000 status 0x1000
    PSS: 1400MHz power 24291 control 0xe00 status 0xe00
    PSS: 1200MHz power 20340 control 0xc00 status 0xc00
    PSS: 1000MHz power 16569 control 0xa00 status 0xa00
    PSS: 800MHz power 12937 control 0x800 status 0x800
    PSS: 1900MHz power 35000 control 0x1300 status 0x1300
    PSS: 1600MHz power 28468 control 0x1000 status 0x1000
    PSS: 1400MHz power 24291 control 0xe00 status 0xe00
    PSS: 1200MHz power 20340 control 0xc00 status 0xc00
    PSS: 1000MHz power 16569 control 0xa00 status 0xa00
    PSS: 800MHz power 12937 control 0x800 status 0x800
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/994
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6870f0cc290c3aa106ccfc84ae62902b27eee4dc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 2 16:30:53 2012 -0700

    Make creation of CBMEM_ID_RESUME_SCRATCH depending on Agesa
    
    The CBMEM_ID_RESUME_SCRATCH area is only used by Agesa code, on one
    particular board (AMD Persimmon). Make the creation of that section
    depending on Agesa so it does consume space on non-Agesa systems.
    
    Change-Id: I2a1a4f76991ef936ea68cf75928b20b7ed132b84
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/992
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f125d80135bad0f7736f20daae16073fff8e84f4
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 2 16:29:51 2012 -0700

    Add missing newline to printk in Sandybridge init code
    
    Change-Id: I9217a75ec1a0abb898c45752d990231ce98e5fb2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/991
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cabc8042a265eb309c230aed72851cfd37c3ff4c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 2 16:27:26 2012 -0700

    Tell CBMEM pretty printer about MRC cache
    
    Sandybridge memory initialization produces some amount of training data
    that has to be kept around in CBMEM. Add a descriptive name to the CBMEM
    pretty printer to prevent it from just printing the hex value.
    
    Change-Id: I587c0bc3dfcf389ba298d445d2594eef73bc69a8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/990
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3b5a9edcb2153d9a9530dcd50b5eb2f844faef5d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 2 16:41:55 2012 -0700

    Fix register corruption during Intel Microcode update
    
    Another bug in the Intel microcode update code that existed since we switched
    to LinuxBIOSv2 in 2004:
    
    The inline assembly code that reads the CPU revision from an MSR after running
    cpuid(1) trashes registers EBX and ECX. Only ECX was mentioned in the clobber
    list. C code running after this function could silently access completely wrong
    data, which resulted in the wrong date being printed on microcode updates (and
    potentially other issues happening until the C code writes to EBX again)
    
    Change-Id: Ida733fa1747565ec9824d3a37d08b1a73cd8355f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/996
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8bec7fbc0f59926a487dcbeeb78402016752bdfc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 1 17:04:51 2012 -0700

    ChromeOS: drop unused debug header description
    
    No part of ChromeOS seems to use the debug header description, so drop
    it to make sure it does not get copied around wrongly.
    
    Change-Id: Icb0baedbf6112f11289b2ddd9618a955a424ddf7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/989
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit adc05c14c7497a8139f73a219f2cbc61fe5f1803
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 1 16:35:03 2012 -0700

    Make Intel i5000 specific options only appear on i5000 systems
    
    Change-Id: If183611b0b62d9321a5a12311c4cb3b344b04b36
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/986
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 252111d4333f87523e0feb0df1d4f4078a4d8b9a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 1 16:53:22 2012 -0700

    Don't include console.h in microcode.c when compiling with ROMCC
    
    If microcode.c is built by romcc, this indicates that we are running
    microcode updates in the bootblock (e.g. before enabling cache as ram).
    In this case we did not enable any consoles yet, so we don't output
    anything.
    
    This patch removes inclusion of the unnecessary console/console.h for
    that case, which was breaking with certain configurations.
    
    Change-Id: Iebb57794d7b1e84cac253d249d47b88de4dd28a3
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/988
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cafedcf5c8161f0d427293ecacbf3a9e918e41f3
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 1 16:37:18 2012 -0700

    Strip quotes from Sandybridge MRC blob
    
    This fixes my build when specifying an absolute path to the binary.
    
    Change-Id: I95fb3960be70f78146c6afeb9cc777dccdca6b5b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/987
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7a3f36a228eeb30acb9f3adde2798e9f401849d2
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Wed Apr 18 15:47:32 2012 -0700

    Sandybridge: Display platform information early
    
    It is important to have the system configuration reported as early as
    possible to have a better idea what exact chipset the platform is
    running with.
    
    This change adds code to have an early coreboot module report the CPU
    and PCH information. CPU info includes the 32 bit feature information
    word, the symbolic processor brand string, and information about some
    features support, as obtained through CPUID instructions.
    
    The PCH information includes the symbolic device name and PCI device
    version.
    
    Change-Id: If6c21ad5ffb76d7d57d89f4f87d04bdd7192480a
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/975
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4aca5d7e66178c11c15d29fb439622c93680c06c
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Apr 27 10:58:22 2012 -0700

    Fix issue with PCIe power management setup
    
    The current early PM setup that attempts to configure dynamic clock
    gating relies on PCIe functions to be enabled that may not be.
    Instead of reading port 0 or 4 directly to determine the link width
    use the register that refelects the soft strapping options as this
    will always be available.
    
    Also add a clear register assignment and break for port 0 in the
    switch statement instead of falling through to port 4 as that could
    end up setting the slot power limit based on port 4 values instead
    of based on port 0.
    register 0xE1=0x3f and all other root ports should have 0xE1=0x03.
    
    When port 0 and 4 are disabled they will have 0xE1=0x3C before
    being disabled by the pch enable handler.
    
    LUMPY default:
    
      00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
      00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
    
      pci_read8 0 0x1c 0 0xe1
      0x3f
    
      pci_read8 0 0x1c 3 0xe1
      0x03
    
    LUMPY with PCIe port coalesce enabled:
      00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
      00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
    
      pci_read8 0 0x1c 0 0xe1
      0x3f
    
      pci_read8 0 0x1c 1 0xe1
      0x03
    
    Change-Id: I33a37b0ec0c8e570cf5d9dda2c06e0225fee135c
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/980
    Tested-by: build bot (Jenkins)

commit b9fe01c881c40ea185a54b13c4ed0d604e6d36f0
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Apr 27 10:30:51 2012 -0700

    Add an option to enable PCIe root port coalescing
    
    Background: The PCI spec (3.0-3.2.2.3.4) requires that PCI devices
    implement function 0.  The Linux Kernel therefore will not enumerate
    a PCI device if it does not present a valid config space at function 0.
    
    If a board does not have anything connected to root port 0 and it is
    desired to disable the unused ports in order to save power then this
    will cause the other downstream PCIe devices to go missing as they
    will not be enumerated.
    
    Intel chipsets provide a way to map root port numbers to different PCI
    function numbers, thereby avoiding this issue and allowing root port 0
    to be turned off.
    
    This change adds a new chip config option 'pcie_port_coalesce' that
    will collapse the enabled root ports into a linear map starting at
    zero.  This option defaults to disabled as it can have a confusing
    effect on the system as the declared static devicetree may not match
    what is seen at runtime.  This option is also forced on if the static
    devicetree disables port 0.
    
    When each root port is processed in the early enable stage it looks
    for a lower numbered root port that has been disabled and then swaps
    the two assigned function numbers.
    
    However the mapping register is write-once so it has to keep track of
    the proposed mapping changes until all ports have been processed
    before writing out the final map value.  At this point it also updates
    the function numbers in the static device tree so they are consistent
    with the new layout.
    
    There are a few other closely related fixes in this change:
    
    1) There is a power savings opportunity if an entire bank of ports
    (0-3 or 4-7) are disabled.  This was checking the chipset revision to
    look for CougarPoint B1+ stepping and that was not passing on
    PantherPoint where this should always be applied.  To fix this I added
    a function to determine the chipset type based on comparing the upper
    byte of the device ID.
    
    2) Apply the same chipset type check fix to the IOBP programming.
    
    3) There is another power savings opportunity to enable dynamic clock
    gating on shared PCIe resources which only applies to ports 0 and 4.
    However if 0 or 4 is disabled then the later check to enable this
    would fail as that device is already hidden.
    
    LUMPY current:
    
      00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
      00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
      01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01)
      02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B
    
    LUMPY with PCIe port coalesce enabled:
    
      00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
      00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
      01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01)
      02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B
    
    Change-Id: I828aa407fdc9c156c1c42eda8e2d893c0aa66eef
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/979
    Tested-by: build bot (Jenkins)

commit c3230368849da3eaaffbd370fb80e344b5c266f0
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Apr 27 09:55:45 2012 -0700

    Update PCIe Root Port _PRT to handle re-mapped functions
    
    The chipset enforces static-defined interrupt swizzling on PCIe root
    ports so if a port is remapped to a different function it needs to
    still report the proper interrupt map to the OS instead of assuming
    that function number is equivalent to root port number.
    
    This change also includes an update to the PCH function disable
    register which was incorrect for CPT/PPT and would cause unpredictable
    behavior if used.
    
    The kernel command line was changed to add 'nomsi' in order to force
    PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure
    that the mapping is correct.
    
    LUMPY current:
    
      00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
      00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
    
      16:   41518   0   0   0   IO-APIC-fasteoi   i915, ahci, ath9k
      19:     720   0   0   0   IO-APIC-fasteoi   ehci_hcd:usb2, eth0
    
    LUMPY with PCIe port coalesce enabled:
    
      00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
      00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
    
      16:   38988   0   0   0   IO-APIC-fasteoi   i915, ahci, ath9k
      19:     347   0   0   0   IO-APIC-fasteoi   ehci_hcd:usb2, eth0
    
    Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/978
    Tested-by: build bot (Jenkins)

commit 2c41c4027f50673826a6c0ec2f1b066e748f5c6d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 1 11:13:52 2012 -0700

    Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boards
    
    CONFIG_MAX_PHYSICAL_CPUS is defined by quite a number of
    mainboards whithout any code actually using the variable.
    Hence, drop MAX_PHYSICAL_CPUS from Kconfig for those boards.
    
    In the long run we should drop CONFIG_MAX_PHYSICAL_CPUS use
    completely and make the code dynamic or depend on CONFIG_MAX_CPUS
    instead.
    
    Change-Id: I37dcc74d245ddba5186b96bd82220dacb6f4d323
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/984
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 816d081760d4cccf0db0c952728f5ec6926d6c85
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Apr 30 16:42:07 2012 -0700

    Fix SATA port map to only enable port 0
    
    The sata controller comes up in legacy/normal mode and
    is currently put into AHCI mode in romstage.
    
    If that is removed and the controller is left alone until the
    ramstage driver (like we do on Stumpy/Lumpy) then the resource
    allocator will have configured the device for IDE mode with an
    IO address in BAR5.  Then when the ramstage driver puts the
    controller into AHCI mode it will not have the correct resources
    to do the rest of the AHCI setup.
    
    So the controller mode needs to be changed in the enable stage
    rather than in the init phase.  This same register contains
    the port map and it is a R/WO (write once) field so the configured
    port map must be written at the same time.  For non-AHCI mode
    the devicetree map was ignored before but it is used now.
    
    Since the port map register is now written at enable step it
    does not need to be written again during init.
    
    With this change the sata port map can be reduced to just port 0
    and then U-boot does not have to probe all available ports.
    
    Change-Id: I977952cd88797ab4cea79202e832ecbb5c37e0bd
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/977
    Tested-by: build bot (Jenkins)

commit 8508cff0359dcd99d319407f15e5034ff896a716
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Apr 12 16:02:43 2012 -0700

    Update Ivybridge GT power meter tables
    
    - New table for GT1
    - Updates to GT2 17W table
    - New table for GT2 35W SKU
    - New table for GT2 Other
    
    This also includes a workaround to poll on a different register
    when deasserting force wake.  On some SKUs the kernel is hanging
    when bringing up graphics unless this register is also polled.
    
    Change-Id: I2badf62b464e901cfb0eaf4fc196f59111c71564
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/974
    Tested-by: build bot (Jenkins)

commit dd585b8825a513d5e304cd3b04da7aeb847b9e8b
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Apr 9 12:05:18 2012 -0700

    Update ivybridge graphics initialization
    
    - Add config options to set backlight registers
    - Update powermeter weight tables for IvyBridge GT1 and
    add a new table for GT2 SKU
    - Fix a few registers used during GPU PM init sequence
    
    Change-Id: I1500bc07e3ba1bc10c77e7856089e716489dc07a
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/973
    Tested-by: build bot (Jenkins)

commit c908fc762cfb3dea096b2805c8cbe9a831b11585
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Apr 30 16:33:44 2012 -0700

    Fix TPM driver to work with multiple vendor TPMs
    
    Port u-boot patch for low-level driver:
    - Fix bug in traversal of vendor name list.
    - Sending "command ready" needs additional logic to handle
    TPMs that need that bit set twice: once to empty the read
    FIFOs and once to actualy set command ready.
    
    Change-Id: I57c280266b2e966c5b90e4f9e968426a33b93cf1
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/972
    Tested-by: build bot (Jenkins)

commit 95be1d6f469a552657bc6a63ccdb27a7654f810f
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Apr 9 12:31:43 2012 -0700

    Don't disable ACPI in the S3 resume path
    
    The OS does not re-execute the APMC 'enable ACPI' SMI
    on resume so this has the potential to leave things
    in an unknown state.
    
    Change-Id: Iaf0fcb99f699e9e0ecacaab3f529026782a95151
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/971
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7b508ddecb25d60945f088914f739ee5b3c2c175
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Apr 9 12:30:43 2012 -0700

    Only send ME Dram Init Done message on Sandybridge
    
    This is done inside the SystemAgent binary on Ivybridge.
    
    Change-Id: I8fb0f593a65a4803e160b284c21b9d5021e2e4a0
    Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
    Reviewed-on: http://review.coreboot.org/970
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0ff99b70f5c5b6797507d3f152c5d452e1210110
Author: Vincent Palatin <vpalatin@chromium.org>
Date:   Wed Mar 28 16:10:29 2012 -0700

    Modify DMI init for IvyBridge
    
    The ASPM setting for the Direct Media Interface should no longer be done on
    Ivybridge/PantherPoint based systems.
    
    Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c
    Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
    Reviewed-on: http://review.coreboot.org/969
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 459b7777fe871c5c9bd6636b1b13efc784129e31
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Sat Apr 7 02:11:36 2012 +0000

    add new LPC controller device ID value
    
    This adds the PCI device id of the LPC controller identifying the
    QPRJ/QS stepping of the Panther Point southbridge.
    
    Change-Id: Idcaa7dbd30224e3690ea469c6cb74f75de287631
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/968
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8049fc91ded9d780b9f6d5c40bc43ad3242b7a3b
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Apr 24 12:53:19 2012 -0700

    Allow device ID arrays in the PCI driver structure
    
    Many PCI devices share the very same driver despite having different
    PCI device IDs, which causes a lot of copy and paste of driver
    definitions.
    
    This change introduces a way to specify the array of acceptable
    device IDs in a single driver entry. As an example the Intel
    {Sandy|Ivy} Bridge SATA driver is being modified to use a single
    driver structure for all different SATA controller flavors, a few
    more Ivy Bridge IDs are being added as well.
    
    BUG=none
    TEST=manual
      . modified coreboot brought up an Ivy Bridge platform all the
        way to Linux login screen.
    
    Change-Id: I761c5611b93ef946053783f7a755e6c456dd6991
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/982
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 599e204efc5a55eb388a2ff11afb0e2196c21875
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Mar 30 14:33:02 2012 -0700

    Clean up Emerald Lake 2 mainboard directory
    
    Change-Id: I4a64a56dda22050a31232807096e15565a665377
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/967
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8172d0be978d74eaaf103b592b505385db105f67
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Mar 28 13:19:15 2012 -0700

    Allow more CPU cores on Emerald Lake 2 CRB
    
    The Emerald Lake 2 CRB can potentially have more
    than 8 CPU cores, so update the number of max cores
    accordingly.
    
    Change-Id: Ia42ed8a84916f66dfbfdf2a72cbbed5cea61899b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/966
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f40a2590acf4db45fa89098b9e406e45ffaffc0c
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Mar 29 18:04:56 2012 -0700

    Set up ChromeOS dev mode, recovery, and write protect GPIOs on Emerald Lake 2.
    
    The Emerald Lake 2 CRB wasn't designed with ChromeOS in mind, so there aren't
    any actual developer mode, recovery mode, or write protect switches, let alone
    GPIOs to read them from. Instead, I've commandeered signals connected to GPIOs
    which are for other things but which aren't used by hardware or, for instance,
    the EC to do something Coreboot doesn't control.
    
    The recovery mode switch is connected to GPIO 22 and is called BIOS_REC on the
    schematic. The name is at least very reminiscent of the right thing even if
    it's supposed to be used for something else. There's a jumper on the board
    labelled J8G1 which can force the line to ground, and if not, there's a switch
    on the front of the case which toggles its value. "RECOVER" is for recovery
    mode and "KEEP" is for normal mode.
    
    The developer mode switch is connected to GPIO 57 and is called SV_DET on the
    schematic. It's connected to a jumper labelled J8E2 on the board and, as far as
    I can tell, can't be controlled in any other way. When the jumper is in place
    and the pins are shorted, developer mode is selected. When the jumper is
    removed, normal mode is selected.
    
    The write protect is connected to GPIO 48 which is called BIOS_RESP on the
    schematic. It's connected to a jumper labelled J8E3 which, like j8E2, seems to
    be the only way to control the line it's on. When the jumper is in place,
    write protect is "disabled", and when it's in place it's "enabled" even though
    there's no functional difference.
    
    The input for the recovery mode switch was chosen because of the name it
    already had on the CRB, BIOS recovery, and because there's a switch to control
    it on the front of the case which makes it easy to get at. The jumpers for
    developer mode and recovery mode were chosen because there weren't very many
    options available, and of those these were next to each other which should
    make them easier to find and work with. It might be a good idea to wire toggle
    switches up to the pins of those jumpers so they'll be easy to identify, can
    be labelled, and would be easier to work with than little jumpers in the
    middle of the motherboard.
    
    Change-Id: Ib2c3dc05077dacfbede596dae143ed81a99dbebd
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/965
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e6063fee5c954d5acd80fd51e11aeac31e83d13d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Apr 30 14:57:51 2012 -0700

    Fix Sandybridge/Ivybridge mainboards according to code review
    
    This fixes a few cosmetics with the following three boards:
    
     - Intel Emerald Lake 2
     - Samsung ChromeBook
     - Samsung ChromeBox
    
    The following issues were fixed:
    
     - rely on include path in ASL code instead of specifying relative
       paths
     - use updated ALIGN_CURRENT in acpi_tables.c
     - use preprocessor defines instead of hard coded values where possible
    
    Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/963
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Tested-by: build bot (Jenkins)

commit a1155b47ca42ad1813c36e1d6de6e8116ae13845
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Apr 30 23:56:58 2012 +0200

    Move VSA support from x86 to Geode
    
    Instead of the special case in the generic Makefile.inc,
    use cbfs-files in the CPU directories.
    
    Change-Id: I71d9c8dff906c9a516ac0dd09a315f8956075592
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/962
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 0909d86760aab4f58fd711183ce1b586b493b5e6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Apr 30 23:53:56 2012 +0200

    Support adding stages with cbfs-files
    
    stages have special cbfstool syntax, which we need to support.
    
    Change-Id: I119255246af818f010acfc7ec2091a6184e74eb3
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/961
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 843005c7694cd9866b293267e2b57e87c6cb490d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Apr 30 23:15:17 2012 +0200

    Add vsa processor to cbfs-files
    
    Change-Id: I548e86084acc51b0471160d37439385f524224cf
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/960
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 943ddcee53b02b5df649762a75327349ca8890f9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Apr 30 22:56:30 2012 +0200

    Make geode_lx use the vsa from blobs repository
    
    ... or fail if repository is not enabled.
    
    Change-Id: I0a1e6d6fed852ec7edf96ace8346ae6b23838a56
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/959
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 5fe7a209f5cc6a713014b5d20b33a907ab3fb8c1
Author: Gabe Black <gabeblack@google.com>
Date:   Thu Mar 29 17:58:52 2012 -0700

    Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.
    
    This sets up the SMI and SCI inputs on the PCH for Emerald Lake 2 based on my
    best interpretation of the schematic. It may not be correct, but it doesn't
    seem to cause any problems either.
    
    Change-Id: I21238b3853a92893ec7f08baa2a3ebd35c49dd97
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/964
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bea842114514d88d5499d42597d8d692d29af1c2
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Apr 30 22:55:28 2012 +0200

    abuild: Add option to use binary files
    
    abuild -B enables the use of the blob repository.
    
    Change-Id: I2dd823d3b024ad249d72d668657bf6a6e92145cf
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/958
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 7e9b9d893c08e5cf92a4620df476238008511ecd
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Apr 30 21:06:10 2012 +0200

    Add Kconfig options to handle the blobs repository
    
    One option to allow using the repo (defaults to no),
    one to let boards state that they require it in the
    current configuration.
    
    The build system checks out the repo if allowed, and
    fails if the repo is requested by the configuration
    but not desired by the user.
    
    Change-Id: If71d80b329cf528aa467fcb0b4d9d7c7434aab27
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/957
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 1db6e2aa197bd8f8ed702f77d6a1e09267af71ee
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Apr 30 20:11:34 2012 +0200

    Add 3rdparty as submodule
    
    The build system will make sure only to fetch this if
    desired by the user.
    
    Change-Id: Ie3c1b44f67ba2595cae001234e29e36cf855a3e4
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/956
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e1ae4b212fd11fa9ae838afa2c045855a128e496
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 23:20:58 2012 +0200

    Add support for Sandybridge base Samsung ChromeBox
    
    Change-Id: Ic93ad2749834c8f7a2ca1651d343561f2a496312
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-on: http://review.coreboot.org/953
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 155e9b5533131f4b944ebb7e5714a871a1294dda
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 23:19:58 2012 +0200

    Add support for Sandybridge based Samsung ChromeBook
    
    Change-Id: I8bf439bc903c1ec105016866753c7cb9ccfe5974
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/952
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6651da3bcd51ad6ea918c21564eb505b76c8c7aa
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 23:16:30 2012 +0200

    Add support for Intel Emerald Lake 2 CRB
    
    This adds support for Intel's Emerald Lake 2 board.
    
    Change-Id: Ifaeeac9d52fe655324ee29df5f7187b89b35f73a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/951
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c31384e62c98baf2fb847d55bb31a82f492ce265
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 23:13:39 2012 +0200

    Fix up Sandybridge C state generation code
    
    This code fixes the sandybridge C state generation code to work with
    the current version of the ACPI code generator.
    
    Change-Id: I56ae1185dc0694c06976236523fdcbe5c1795b01
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/950
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f69b46805c875c81af850af5567a18a934ce28bc
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 23:12:08 2012 +0200

    acpigen: make acpigen_write_CST_package_entry non-static
    
    It's used by Sandybridge specific C state generation code.
    
    Change-Id: Ia6f1e14e748841a9646fd93d0a18f9e8f2a55e29
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/949
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6ea86b19f34ec2a54b355e10a8f4e6e84ffa74ce
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 22:54:10 2012 +0200

    Sandybridge: Temporarily disable MRC cache finding code
    
    This code is still using libfdt which was denied for inclusion
    in coreboot, so it won't compile as is.
    Without MRC cache, waking from suspend won't work, and cold boots are
    significantly slower (adds around 300-400ms per channel IIRC).
    A rework of this code is currently in the works, but will take a little bit
    more time (and should not hold back the mainboards being merged)
    
    Change-Id: Ifb9e7d7b86c1f52378803a748810da0d51b58384
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/948
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 35555167c2e13e114a8bd8d9be5e1e0ad07b3484
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 21:51:49 2012 +0200

    acpi: Add defines for functional fixed hardware
    
    Change-Id: I9c5148eb315e2f478cb753d9918144a19e417379
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/945
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

commit 39205c67027a0753370dad80f67c1f2ebf4bf459
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 21:49:28 2012 +0200

    acpigen: Add support for generating T state tables
    
    Change-Id: I58050591198bb06de5f0ca58ca3a02f1cfa95069
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/944
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

commit 4cc8c70c3297a99449ca731a7ea34d3fbe32d614
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 21:34:16 2012 +0200

    Rework ACPI CST table generation
    
    ... in order to unify the Sandybridge and Lenovo implementations
    currently used in the tree.
    
    - use acpi_addr_t in acpigen_write_register()
    - use acpi_cstate_t for cstate tables (and fix up
      the x60 and t60)
    - drop cst_entry from acpigen.h
    
    Change-Id: Icb87418d44d355f607c4a67300107b40f40b3b3f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/943
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

commit a403c687b16170966fa955ce55072edec84b5187
Author: Martin Roth <martin@se-eng.com>
Date:   Fri Apr 27 13:54:36 2012 -0600

    Add default map_oprom_vendev() for AMD Family 14h processors.
    
    AMD supplies their video bios for the Family 14h processor line
    with Vendor ID: 1002, Device ID: 9802.  This rom should work for
    Device IDs 9802-9809.  This patch maps all those device IDs to
    0x9802 so coreboot will be able to load the vbios.  If a vbios
    rom using the ACTUAL Device ID is loaded, this function will not
    be called.
    This file should contain of all Family 14h Graphics PCI IDs so
    that they don't need to be overridden on a per mainboard basis.
    
    Change-Id: If3d4a744b3c400dea9444a61f05382af2b2d0237
    Signed-off-by: Martin L Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/955
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit f3005f515b11d7101f34f606a22860b347fd5017
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Sun Apr 29 11:52:09 2012 -0600

    Update SeaBIOS stable to the version 1.7.0 tag.
    
    Change-Id: Id3a2dd29e07ed11755468e89f8e80efdef5e2b2f
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/954
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 40aa9bce7d502f7b8a5c6cbccfd4686d3bcd44a2
Author: Martin Roth <martin@se-eng.com>
Date:   Fri Apr 27 11:48:32 2012 -0600

    Update amd/south_station/fadt.c with various fixes
    
    This is a model fadt.c that I would like to use for updating
    several other AMD platforms with after acceptance.
    
    - Updated to match ACPI 3.0b specification and added comments
      to reflect that.
    - Since smi_cmd is 0, remove commands that rely on it:
      acpi_enable, acpi_disable, & pstate_cnt
      Add comments to that effect.
    - Changed preferred_pm_profile to SOHO Server (platform
      specific)
    - The southstation platform is legacy free - Updated
      iapc_boot_arch and flags to reflect that.
    - Added reset_register flag so that operating systems
      will actually use the reset_reg.  This is important
      on legacy free systems.
    - Updated Generic Address Structures to use access_size
      name in the updated acpi.h.  Added access sizes to
      the structures where reasonable.
    - Removed 64-bit x_firmware_ctl pointer to facs.  This was
      causing a fwts failure and windows-64 BSOD.
    - Added bit width for pm2_cnt_blk and modified gpe0_blk bit
      to match the hardware.
    
    Change-Id: Icf1a982aa122636d1088c8b80f53d04732b54c49
    Signed-off-by: Martin L Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/942
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit a2937145799999fb482cff2d2faf4925f335005d
Author: Raymond Danks <ray.danks@se-eng.com>
Date:   Fri Apr 27 08:46:55 2012 -0600

    nvramtool: Allow build under Cygwin
    
    To build under Cygwin, nvramtool depends upon the package ioperm:
    http://openwince.sourceforge.net/ioperm/
    
    for sys/io.h and sys/perm.h.  This change causes the nvramtool make to correctly include and link against these headers and libraries.
    
    Change-Id: If6cd9d324de7bc19830e0018844f42761b28ddd3
    Signed-off-by: Raymond Danks <ray.danks@se-eng.com>
    Reviewed-on: http://review.coreboot.org/940
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 61e7c289d45f0113925e9d59e7d0e415a049bd1d
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 21:53:12 2012 +0200

    ChromeOS: Add missing prototype for  acpi_get_vdat_info()
    
    Change-Id: I4bd9b52cfc24a8ff73be05ee535b9e16c0d9bd79
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/946
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 5b73d4d1bbfa79d4672fa96822f5337860a8ee29
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 21:55:05 2012 +0200

    acpigen: make acpigen_write_len_f() non static
    
    since it is used in CPU specific ACPI generation code
    
    Change-Id: I2559658f43c89dc5b4dc8230dea8847d2802990c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/947
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 51b8f05ab3082d8dae5077ff01753d29546f8ce6
Author: Raymond Danks <ray.danks@se-eng.com>
Date:   Fri Apr 27 08:51:02 2012 -0600

    ectool: Allow build under Cygwin
    
    To build under Cygwin, ectool depends upon the package ioperm:
    http://openwince.sourceforge.net/ioperm/
    
    for sys/io.h and sys/perm.h.  This change causes the ectool make to correctly include and link against these headers and libraries.
    
    Change-Id: I7d54ab5110c2bb1fd21dfa48d56031f3f29cd54e
    Signed-off-by: Raymond Danks <ray.danks@se-eng.com>
    Reviewed-on: http://review.coreboot.org/941
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e9dfdd9dbdbe91cb5754671592ae3d1fc0916f3c
Author: Martin Roth <martin@se-eng.com>
Date:   Thu Apr 26 16:04:18 2012 -0600

    Reverse Vendor ID & Device ID for map_oprom_vendev()
    
    - When calling map_oprom_vendev() the vendor ID and device ID
      are joined into a 32 bit value.  They were reversed from the
      order that I would have expected - Device ID as the high 16 bits
      and the Vendor ID as the low 16.  This patch reverses them so
      so that the the dword comparison in map_oprom_vendev() matches
      what's entered into Kconfig for vendor,device.
    - Change files calling map_oprom_vendev()
    
    Change-Id: I5b84db3cb1a359a7533409fde7d05fbc6ba3fcc4
    Signed-off-by: Martin L Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/938
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 0e672b52d46f05aec066e7625c097e69baa62a23
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 00:34:54 2012 +0200

    coreboot_table.c: Add missing include files
    
    If compiling coreboot with ChromeOS support, two
    more include files are required.
    
    Change-Id: I7e042e250e4a89e7dd4bab58443824d503c3f709
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/931
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 16401b8f6de12b00831746bc48e72010796180b8
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 01:05:11 2012 +0200

    SMM: Add udelay on Sandybridge systems
    
    Cougar Point southbridge does udelay in SMM, hence add it on Sandybridge
    systems.
    
    Change-Id: I6e5520ca27e7c6eaae632992fb68612067bc1e30
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/937
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 80529abdfb41f2470ac744ccdd235cac9c3ce4e4
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 01:02:26 2012 +0200

    Cougar Point southbridge: Add includes and drop post_code()
    
    post_code() was added in our internal tree by duplicating code. It's not of
    much use at this point, since the code is quite well tested, so avoid bloating
    the bootblock (since compiled with ROMCC).
    Also add some missing include files that didn't seem to be needed with an
    older version of coreboot.
    
    Change-Id: Id62b838728a247e8bcadb4f1db17269be0d4f3f4
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/936
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit adc7bb06cdda7c52aa884db137144b2eb7869a48
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 00:48:58 2012 +0200

    ChromeOS: add missing string.h in gnvs.c
    
    string.h is required to build with the reference toolchain.
    
    Change-Id: I9fd8d2ea8fc676d3502989cbcc7aefe3b2d738b6
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/935
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b5866f2fb65cd703b29bcb8d97b8ddf079a77eda
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 00:47:21 2012 +0200

    SMSC MEC1308: Fix ACPI code to work with newer IASL versions
    
    Newer versions of IASL didn't like our IO constructs. Use
    FixedIO instead, it's also shorter.
    
    Change-Id: I9364d993ecb71ffd84c0313ca1e2f870af59eb24
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/934
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bf34e94095dfdbd032d50c0067ee91182db88118
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 00:44:04 2012 +0200

    SMM: unify mainboard APM command handlers
    
    rename from mainboard_apm_cnt to mainboard_smi_apmc to match the function
    naming scheme of the other handlers. Add prototype for mainboard_smi_sleep
    (mainboard specific S3 sleep handlers in SMM) that is required by Sandybridge.
    
    Change-Id: Ib479397e460e33772d90d9d41dba267e4e7e3008
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/933
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ac8209a4b351f0a241d68f09851593625a0f146a
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 00:39:17 2012 +0200

    cpu/cpu.h: add ROMCC guards
    
    In order to use the generic microcode update code in the bootblock, cpu/cpu.h
    needs ROMCC guards. Also, delete the unused struct device declaration and move
    the struct bus declaration to where it's used.
    
    Change-Id: I0cc731c555593946e931a680ec93994932530599
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/932
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ae5e11d7cd7484343d277fb454fb19fdff34730d
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 27 02:31:28 2012 +0200

    Move top level pc80 directory to drivers/
    
    There is no reason for this to be a top level directory.
    Some stuff from lib/ should also be moved to drivers/
    
    Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/939
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit aee1869fcf6c5eb1616f8c5c5a446c2b2de693e8
Author: Martin Roth <martin@se-eng.com>
Date:   Thu Apr 26 15:54:15 2012 -0600

    Updates to x86/include/arch/acpi.h for use in fadt.c
    
    - Added a union to identify the byte that was reserved in the
      Generic Address Structure from ACPI 2.0 to ACPI 2.0b as the
      Access Size byte for ACPI 2.0c to ACPI 5.0
    - Added various #defines for use in the FADT
    - Added a couple of comments for the #endifs
    
    Change-Id: I294ddfd89fcb0ad88bb6e52d911f807d84671e82
    Signed-off-by: Martin L Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/930
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 31109452c2cf1d8ec11db6df30329b101ae808f6
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 26 02:04:53 2012 +0200

    microcode: print date of microcode and unify output
    
    Most subsystems print their name with a colon, and then the
    message. Do the same thing for the microcode update code.
    
    Also, each microcode update has a date header. Print the
    date from that header to make it easier to determine whether
    you're running the latest microcode.
    
    Change-Id: Ic22947c4b9f0502d4091d975e1f1ab42f70aa1aa
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/929
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 3f8989ebbce4305541c6df569d283f76029ae724
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 25 22:58:23 2012 +0200

    Revamp Intel microcode update code
    
    - add GPLv2 + copyright header after talking to Ron
    - "bits" in struct microcode served no real purpose but
      getting its address taken. Hence drop it
    - use asm volatile instead of __asm__ volatile
    - drop superfluous wrmsr (that seems to be harmless but
      is still wrong) in read_microcode_rev
    - use u32 instead of unsigned int where appropriate
    - make code usable both in bootblock and in ramstage
    - drop ROMCC style print_debug statements
    - drop microcode update copy in Sandybridge bootblock
    
    Change-Id: Iec4d5c7bfac210194caf577e8d72446e6dfb4b86
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/928
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 05e740fc40e409dcf8d592f4bbeaf87dc92140c5
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Mar 31 12:52:21 2012 +0200

    Replace cache control magic numbers with symbols
    
    Instead of opaque numbers like (1<<29), use
    symbols like CR0_NoWriteThrough.
    
    Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/833
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8919729307028746cf7bc527ca511183fe3b401b
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sat Apr 14 14:30:49 2012 +0200

    ASUS M4A785T-M mainboard: fix screen flickering issues
    
    Without that fix the screen flickered with resolutions superior
      to 832x624 because the cpu_ht_freq was 0 (so it ran at 200Mhz).
    
    Change-Id: I1056d76b1d77f6177594ed9d03ecc5ae7b3c2c13
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/900
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1e9c1b3e1d054350ddbbdf0d4ff2c307b488dab2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Apr 19 14:43:47 2012 +0300

    Makefile: rename romstage linking filenames
    
    Move final build results under $(objcbfs).
    Move intermediate files under $(objgenerated).
    Remove use of sed -i.
    
    Change-Id: Ie035a1544848b26514a197c340f470201065b8d5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/859
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 38f2e9cfe3597db5bc418be2c8c1b87dffa98ca7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Apr 19 14:22:43 2012 +0300

    Makefile: rename coreboot_ap linking filenames
    
       $(obj)/coreboot_ap -> $(objcbfs)/coreboot_ap.elf
    
    It is really a ramstage for AP CPU and not a romstage, it is not
    enabled for any mainboard by default, and it doesn't compile
    even if enabled.
    
    Change-Id: Ifb9c5cb6df65309660b000876cf6a9a3da9b6839
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/840
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6b07b8df927947d19d9a7b9d66d279df2de69c0d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Apr 19 12:21:36 2012 +0300

    Makefile: rename ramstage linking filenames
    
    Move final build results under $(objcbfs).
    Move intermediate files under $(objgenerated).
    
    Change-Id: I0046f68938be81b8efa525aa50b39328ca02ecb6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/839
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f775b8c8dfd4f50ab76415e51b2a5c3afe47a74f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Apr 19 12:14:53 2012 +0300

    Makefile: rename bootblock linking filenames
    
    Move final build results under $(objcbfs).
    Move intermediate files under $(objgenerated).
    
    Change-Id: I0365304e1b0ed02a5a3ec720b0cf3e303eaefa7c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/838
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f526889e8bcc36ccd9673bdebd9bb45fbb97e267
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Apr 20 15:31:16 2012 +0200

    rk886: Add ACPI support for LID switch
    
    Change-Id: Ib5a34491531228db9a9232322bd573fded27ee67
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/924
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3294a0f1ca19b32301df72cea1015924102924ec
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Apr 24 16:01:24 2012 +0200

    Make timestamp collection conditional in hardwaremain.c
    
    Otherwise it breaks 486 boards without RDTSC, ending with
    exception 6.
    
    It ends like this on bifferboard:
    
    Jumping to image.
    Unexpected Exception: 6 @ 10:001007e3 - Halting
    Code: 0 eflags: 00000016
    eax: 001001fe ebx: 00100118 ecx: 00000000 edx: 00108e00
    edi: 0010aaf8 esi: 00000000 ebp: 00117ff4 esp: 00117fd8
    
    Please keep in mind 486, dont use rdtsc/cpuid in generic code, or if you do make sure make it non-default option.
    
    Change that broke it: http://review.coreboot.org/#/c/749/7/src/boot/hardwaremain.c
    
    Change-Id: I974b25377c20a11430b35b24dcc275d8cbfd2b9a
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/925
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 02c204706f1f43dd49e8c9cb5136b6a87117dc72
Author: Alec Ari <neotheuser@ymail.com>
Date:   Mon Apr 23 20:24:24 2012 -0500

    Fix whitespace for ma785gm
    
    Fix tabs and whitespace for
    ma785gm mainboard.c file.
    
    Change-Id: I8c94bf428bc4e78871da8c64f89221af4151e16d
    Signed-off-by: Alec Ari <neotheuser@ymail.com>
    Reviewed-on: http://review.coreboot.org/923
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 8a527cfb49a15a08baffb7fbd6fdc51dbc28e9df
Author: Alec Ari <neotheuser@ymail.com>
Date:   Mon Apr 23 20:12:30 2012 -0500

    Update MA785GM code
    
    This commit adds the following to MA785GM:
    
    Refactor some alignment handling
    Unify Local APIC address definitions
    ACPI: More ../../.. removal
    Remove old AMD fam10 fixme comment
    amd/sb700: Move HAVE_HARD_RESET to southbridge
    
    Change-Id: I85a95bb641375dd61d1f58a2f2f972771d1d9ad9
    Signed-off-by: Alec Ari <neotheuser@ymail.com>
    Reviewed-on: http://review.coreboot.org/922
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 1d89f14355e72d6969c8b8aae56904ebee965d43
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Apr 20 17:11:31 2012 +0300

    Intel 82801dx: compile early_smbus as separate object
    
    Add early_smbus.c for romstage-y list and remove respective
    include on mainboard romstage.c files.
    
    Tested on AOpen board.
    
    Change-Id: I1c7e6cb32e3a9d7cc9b6037dc27e59149d492001
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/909
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0a19ddc36d9df98ab4b29c36359cc5274d4d9f57
Author: Alec Ari <neotheuser@ymail.com>
Date:   Sun Jan 8 14:49:44 2012 -0600

    Add support for MA785GM-US2H
    
    This patch adds coreboot support for the
    GIGABYTE MA785GM-US2H board.
    
    This port now removes all dead code in
    the previous patch set, and also boots Fedora 16
    on x86_64 (Phenom II X4 955 BE)
    
    On-board audio causes spurious interrupts and
    the kernel gets stuck in an infinite loop.
    
    AtomBIOS on RadeonHD video cards does not function
    and causes another infinite loop. radeon.modeset=0
    must be set. acpi=off must also be set.
    
    With those kernel command line options set,
    Fedora 16 makes it to the login screen. USB
    mouse and keyboard don't work though. several
    USB error codes on boot-up. PS/2 should.
    
    Change-Id: I58a7083a023ebf7373b6ded2e9f0adda7ab76dea
    Signed-off-by: Alec Ari <neotheuser@ymail.com>
    Reviewed-on: http://review.coreboot.org/476
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c02cbf1064f18b6b8583d8e43e640e670e634220
Author: Philip Prindeville <philipp@redfish-solutions.com>
Date:   Fri Jan 6 11:54:23 2012 -0700

    alix2: add support for alix6
    
    The Alix6 is very similar to the alix2, differing in having 1 mini-PCIe
    slot (USB 2.0 only), an RFKILL GPIO line going to that slot, and 1 or 2
    SIM sockets.
    
    Change-Id: I19e4e756966e60bb0310c19286654d3d579b8850
    Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
    Reviewed-on: http://review.coreboot.org/521
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit eeb8a06b037ff9fbd0877e6660ec23038b1f7448
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Apr 22 23:52:23 2012 +0200

    Unbreak boards where chipset can select between FSB and serial APIC bus
    
    Commit d4d5e4d3e10da06a83d57a147bd58a733381de18 contains #ifdef instead
    of #if, making the FSB/serial bus selection for APIC always select serial
    bus. The bug is harmless on most chipsets because the bit is often RO,
    but it breaks at least on VIA K8T890.
    
    Change-Id: I89c4855922199eca7f921c3e4eb500656544c8e5
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/921
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 770c44d20ff10fc962760b9a85626bb43c6ba083
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Apr 21 21:11:52 2012 +0200

    Drop build_opt_tbl
    
    It's gone from the build. Drop the code as well.
    
    Change-Id: Ice6fcb39565273360a576bda4826f16088f4666c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/914
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vikram Narayanan <vikram186@gmail.com>

commit 1e6bf092acc311d1359cf892cc6e03d4afb28923
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Sun Apr 22 00:17:04 2012 +0530

    amd: Fix unused variable warning
    
    Comment out the id variable which is used in a commented code
    block.
    
    Change-Id: Ib002d57e5314971f0589d04b7e451ab7d7079f53
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/913
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0db2ae3ac44ceb05e96973e6101d472dbef164a0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Apr 19 12:00:06 2012 +0300

    Makefile: define build result directories
    
    Final build results (.elf, .debug, .map) are to be placed under
    directory $(objcbfs), the default is:
       $(obj)/cbfs/$(CONFIG_CBFS_PREFIX)/
    
    Intermediate build results (.o, .s, .S, .inc, .ld) that do not have
    a clear one-to-one relation to a file under src/ are to be placed
    under directory $(objgenerated), the default is:
       $(obj)/generated
    
    Also defines implicit rules for final build results:
    
      .debug -> .elf and .map
      .elf -> .bin
    
    Change-Id: I448c6b7c9a952e54170df42091d7db438025a795
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/858
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 93b4ed91f6b1027c370da9bdd6d86664dcda671b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 18 21:13:33 2012 +0300

    Intel e7505: build as separate object file
    
    No longer include northbridge files directly in the source for
    mainboard romstage.c and fix includes.
    
    Also make required adjustments to function declarations.
    
    Change-Id: Iafdcc0766ed44c64cc628e5935eef2c6372f5f22
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/906
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 97c064f0346874dcf02d4b2700a7e7c7913b24c9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 18 20:33:35 2012 +0300

    Intel e7505: enable ECC scrubbing
    
    It takes about 3 seconds to scrub 8GiB DDR266 RAM.
    
    After ECC scrub XIP cache is disabled for system stability. There is
    very little to do in romstage after ECC scrub, especially when RAM
    debug messages are turned off. So the delay caused by this is hardly
    noticeable.
    
    Cache for complete ROM is re-enabled before ramstage is decompressed,
    and it has no unstability issues. So the code required to re-enable
    cache for ROM currently already exists in cache-as-ram_ht.inc.
    
    A Kconfig option HW_SCRUBBER enables the scrub to be run on hard
    reboots and power-ons.
    
    Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/905
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a8111cf980e01e9f8706024f06c05840b5fc8bcf
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Sat Apr 14 15:25:13 2012 +0530

    nvramtool: Unify nvramtool and build_opt_tbl
    
    As cmos.layout parsing capabilities are already there in nvramtool,
    use those than using build_opt_tbl.c. Add binary and header file
    generation in nvramtool. Make appropriate changes to Makefile.inc.
    
    Change-Id: Iaf3f5d4f51451aeb33c92800a0c895045f2388cf
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/898
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c3fc4b933708a594d169e40a82d5f29f304d11c9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Apr 14 16:21:39 2012 +0200

    nvramtool: Allow spaces in enumeration names
    
    Change-Id: Id526e74f06fb15d4692d7b6edc8b5863f2d42c50
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/901
    Tested-by: build bot (Jenkins)

commit 26b00e6d3954dcfa00ee4d7c874161b2fbdd2ce2
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Apr 20 19:19:47 2012 +0200

    Refactor some alignment handling
    
    Made using coccinelle:
      @@
      expression E;
      @@
      -(E + 7) & -8
      +ALIGN(E, 8)
    
      @@
      expression E;
      @@
      -(E + 15) & -16
      +ALIGN(E, 16)
    
    Change-Id: I071d2c98cd95580d7de21d256c31b6368a3dc70b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/910
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d6e4d518b1dbfdcfbea7b56113530900ba3e03b1
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Thu Apr 19 23:44:54 2012 -0600

    Revert wbind added to the reset_vector
    
    This change reverts :
    Change Id I4fdb281b2b684ab5fea999aae28ca08dce24da4d
    
    The wbinvd (or invd) should not be needed at the reset vector. It
    causes problems with some CPUs AP init. If there is a problem with
    a specific CPU and it must be done at this location, it should be
    added conditionally.
    
    Change-Id: I85b71b0a07f039359a4fb889aaa05c75fff619be
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/908
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 77e4f7ddda86b08a25feef04f356595370b3f7a7
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 18 19:47:56 2012 +0300

    Intel e7505: refactor only
    
    Drop comments (from e7501 era) which no longer seem to apply with
    e7505. Write the semi-constant D0:F0 table as code. Some register
    settings seem to be in different order compared with vendor BIOS,
    and will be handled by follow-up patches.
    
    Split RCOMP register copy function in two parts.
    Drop some uses of inline and local_mdelay().
    
    Change-Id: I8739d3b2bbad5861118e8b16ccea1dd86991204f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/896
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit d1edb177e8f1467ae9b9fed55fff878a4427171d
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Apr 19 11:57:03 2012 +0800

    Fix the blank in acpi_tables.c
    
    Hope no more blank issue is got from future copy-paste.
    
    Change-Id: I5eb50e8232e339e7039a15054606aaff6b7ebc52
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/907
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a20132b0b26fca4c07de491143fa655859431696
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Apr 19 12:42:51 2012 +0800

    Do not produce temp s3.rom if the board doesn't need it.
    
    S3.rom is useless for all the other boards which don't use flash to
    save sleep/wakeup settings. AGESA-based boards other than persimmon
    haven't been validated the S3 resume. They don't need S3.rom yet.
    
    Change-Id: I12693e9556ca6f8e0d80b2ab2dca5c85bdb97685
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/902
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2132005b2041b24136c09220b73a7cef698b22b2
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Apr 13 13:48:50 2012 +0800

    Fix messy code in ALIB creation
    
    Fix the copy-paste typo in ALIB table creation. ssdt is useless here.
    
    Change-Id: I250066eb5f755275f75c37789ce8760de35b046b
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/885
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 585a4006976e903599b7128200a29b5729777818
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Apr 12 11:27:26 2012 +0800

    Leverage the Pstate table created by AGESA.
    
    The name of processor created by AGESA is P00n, whose P is
    BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts
    from 0. The dsdt should be aligned with that.
    This feature has only been tested on persimmon. The changes on all the
    other boards were propagated.
    
    Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/884
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3f788e1f701ffb65f6f1bf62c91ac0d6fc013fb4
Author: zbao <fishbaozi@gmail.com>
Date:   Wed Apr 18 16:59:53 2012 +0800

    S3: Use old heap during normal boot
    
    During normal boot, the cbmem is uninitialized. So it is illegal to find
    the heap in cbmem.
    
    Change-Id: I8b5e1dbf1124819ed91693a86a6dbe41aea109e5
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/904
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 899608dc5d6be88a91606f63c41c4729d76f5187
Author: zbao <fishbaozi@gmail.com>
Date:   Wed Apr 18 11:28:07 2012 +0800

    Fix the blank in acpi_tables.c
    
    Change-Id: I65d50616e49802b7bb13f02369c4898fa4a238a4
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/903
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 210fa302a3439002f78331e9b0d903bf02a6b6cf
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Apr 12 15:23:58 2012 +0200

    lint: tighten whitespace check some more
    
    Don't test executable files nor object files, even if the former might
    render the test useless on win32 (executable bit isn't well defined there).
    
    Change-Id: Ifb6fc83243289d266f439316c14b6b009f8da5fc
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/890
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 89823fde181608becd82c810bbf2894f547b4c9e
Author: Ron Minnich <rminnich@gmail.com>
Date:   Sat Apr 14 18:22:23 2012 -0700

    Remove this directory. We've determined that for a number of very good reasons
    we want to keep this tree source-only.
    
    Signed-off-by: Ron Minnich <rminnich@gmail.com>

commit 26c7b86907278504eaa79d381b92e2270eab77fc
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Apr 12 22:46:23 2012 +0300

    Intel e7505: handlers for undocumented registers
    
    Makes the code a bit more readable, IMO. There is no clean way
    to implement this as the affected registers are undocumented.
    
    Seems ROMCC cannot handle the enum. Also any of my future changes
    would not be even abuild tested as there is no longer a board with
    ROMCC and this chipset. E7505 chipset is CAR only from now on.
    
    Change-Id: I0e2d8ba0c7ed7cce46d9eafb8d8badf04cf75f7a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/895
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ad8c95f03b16cb658e6c6b4e032974acf85639a8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Apr 12 22:00:03 2012 +0200

    kconfig: Improve 'General setup' menu docs.
    
     - Add documentation for COMPILER_GCC, and COMPILER_LLVM_CLANG.
    
     - SCANBUILD_ENABLE, CCACHE: Amend documentation.
    
     - SCANBUILD_REPORT_LOCATION: Document default dir, names of scan-build dirs.
    
     - INCLUDE_CONFIG_FILE: Add more verbose docs, show how to use it.
    
     - Fix typos/cosmetics/indentation, improve wording on some items.
    
    Change-Id: I6b67b2c777868e4421405caaffe6631e69dddad2
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Reviewed-on: http://review.coreboot.org/893
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e380b0f858bd85724ecd7ffdbabd071986446c43
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Apr 12 15:03:22 2012 +0200

    More portable s3 scratch space creation
    
    echo -n isn't portable. echo -e isn't portable. that bash loop isn't portable.
    So let's try something else.
    
    Change-Id: Ie73aa1c09d90c11a5c4952a332d4c2058390b5db
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/889
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f543c7b6d3e485dd59555de04e2649b19953187c
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Apr 13 13:42:46 2012 +0800

    S3 code in the mainboard.
    
    Persimmon is the demo board. Tested by Linux and Windows 7.
    
    Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/624
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit f72237346d9a0894b4675f0b6915da6fdcccd31e
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Apr 13 13:42:15 2012 +0800

    S3 code in coreboot public folder.
    
    1. Move the Stack to high memory.
    2. Restore the MTRR before Coreboot jump to the wakeup vector.
    
    Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/623
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit caf494c83170e97b192e2174bc461482699a3712
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Apr 13 13:57:14 2012 +0800

    ACPI HEST table.
    
    HEST feature starts from ACPI 4.0.
    
    HEST is one of four kinds of tables of ACPI Platform Error
    Interfaces (APEI). In Windows world, APEI is called Windows Hardware
    Error Architecture (WHEA).
    
    APEI consists of four separate tables:
    1. Error Record Serialization Table (ERST)
    2. BOOT Error Record Table (BERT)
    3. Hardware Error Source Table (HEST)
    4. Error Injection Table (EINJ)
    All these 4 tables have the same header as FADT, MADT, etc. They are
    pointed by RSDP.
    
    For the HEST, it contains the error source. The types of them are
    defined as
    type description
    1. Machine Check Exception (MCE)
    2. Corrected Machine Check (CMC)
    3. NMI Error
    6. PCI Express Root Port AER
    7. PCI Express Device AER
    8. PCI Express Bridge AER
    9. Generic Hardware Error Source
    Error source types 3, 4, and 5 are reserved for legacy reasons and
    must not be used.
    
    Currently AMD board only provide part of "Machine Check
    Exception (MCE)" & Corrected Machine Check (CMC)". we need to provide
    the header of each error source. Other types of Error Sources is in
    TODO list.
    
    Only persimmon is tested. Linux can add HEST feature. The dmesg says,
    
    ACPI: HEST 0000000066fe5010 00198 (v03 CORE COREBOOT 00000000 CORE 00000000)
    ......
    HEST: Table parsing has been initialized.
    
    No more message is got.
    
    Windows can boot with this patch. Havent found a way to test it.
    
    Change-Id: I447e7f57b8e8f0433a145a43d0710910afabf00f
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/888
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 90655c83d03f51105ab561928224a1b50cebe829
Author: Ron Minnich <rminnich@gmail.com>
Date:   Thu Apr 12 04:26:22 2012 -0700

    Add the memory reference code binary for sandybridge chipsets
    
    This binary is required for anyone who wishes to build a
    sandybridge mainboard.
    
    Change-Id: I779ef5e2b77166b81cb05eada37291368e74fbb6
    Signed-off-by: Ron Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/897
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit a4fa81470aac300d5f91ae7b84b73b1773346ea4
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Sat Apr 14 15:51:53 2012 +0530

    cmos.layout: Remove invalid warning
    
    "This file must be in UNIX format" is not valid anymore.
    
    Change-Id: I86169b12e7db159c1d3f380b0434874e9b6f5274
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/899
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6113c1c738e1baf94f07cc86ea7f3911ac5997a0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Apr 12 21:39:27 2012 +0200

    kconfig: Fix 'make gconfig'.
    
    Change-Id: Id2d0735d875b40e131fc2aada27435fdcbacc8cb
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Reviewed-on: http://review.coreboot.org/891
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a85ca490333756c3cb5ad8cd703b684fe9e655d5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Apr 12 22:48:57 2012 +0200

    Bifferboard: Fix MAINBOARD_PART_NUMBER.
    
    Change-Id: I4acbeee8a0d26fae220ac22940b6f924e19af19c
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Reviewed-on: http://review.coreboot.org/894
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 941158fb701ee92e29d462b8d88a9a6eee10c458
Author: Mathias Krause <minipli@googlemail.com>
Date:   Thu Apr 12 21:36:23 2012 +0200

    cbfstool: pretty print cmos layout files
    
    While at it, also make the array static - no need to export this symbol.
    
    Change-Id: I7fdcda2b80150b6f32b5bc3e0957998a4fd43fce
    Signed-off-by: Mathias Krause <minipli@googlemail.com>
    Reviewed-on: http://review.coreboot.org/892
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 3aff1a32087137169fb4165eb2dd11655de27f45
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Apr 11 12:19:03 2012 +0300

    Convert AOpen DXPL Plus mainboard to CAR
    
    Tested on real hardware, mainboard with dual Xeon P4 HT CPUs
    requires cache-as-ram init code with AP SIPI protocol.
    
    Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI.
    
    Change-Id: I415482f3af22df79d82492c49aed83549f29aa56
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/886
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit eb59636cc5875bac98a949f206e5f8c0462be238
Author: Ron Minnich <rminnich@gmail.com>
Date:   Wed Apr 11 10:30:15 2012 -0700

    Add support for aligned allocation
    
    Add a memalign function and have malloc use it. Also,
    change the default alignment for malloc to u64-aligned.
    
    Change-Id: I0788637008f5cb5ac801d8bbdc430ca992c98e81
    Signed-off-by: Ron Minnich <rminnich@gmail.com>
    Reviewed-on: http://review.coreboot.org/887
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit 392562263858011ef898e377477124f5f66b1302
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Apr 5 13:20:50 2012 +0800

    S3 code in vendorcode folder.
    
    Change the ExecuteFinalHltInstruction to assembly code. so we can make
    sure the code can run stackless.
    
    Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/622
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9bcdbf8eaa0c73d130ba555163f89fa1759c8c99
Author: zbao <fishbaozi@gmail.com>
Date:   Thu Apr 5 13:18:49 2012 +0800

    Add Southbridge support for S3.
    
    1. Add some CIMX call for S3.
    2. Detect sleep type.
    
    Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/621
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2c2e78d845cd28eb3b11c87fa3feafaf836cda7a
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 18:54:37 2012 +0100

    Unify IO APIC address specification
    
    Some places still hardcoded the address instead of using IO_APIC_ADDR.
    
    Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/677
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5c1ff9284a7ac382a9ec702fa52f3a173279d566
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Apr 10 19:55:19 2012 +0300

    Intel e7505: cleanups
    
    Fix delay loop comments. Time waited and the comments did not match
    in the origin (e7501), so delays currently "just work".
    
    Move reset detection to main raminit and don't use generic
    sdram_initialize for now, as there are local debug
    functions I need to use. Fix AOpen respectively.
    
    Disable ecc scrub, until I have it fixed for cache-as-ram use.
    
    Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/883
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5bd271b9fa81532f786f42604d94df92f44b605f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Apr 10 16:11:53 2012 +0300

    Intel e7505: renames only
    
    Drop maybe-prefix in registers and tables.
    Have a name in place of PCI_DEV(x,y,z) to avoid confusion.
    
    Change-Id: I88f51b50d7fd83294aa14455a83418630e1bab85
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/882
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 05758bd817f47780aed2b01df93259294105eee5
Author: Ron Minnich <rminnich@gmail.com>
Date:   Wed Apr 11 07:24:52 2012 -0700

    Remove obsolete empy macro definition
    
    In the early days of v2 the (e.g.) #ifdef SMP style was frowned upon in
    some quarters.
    
    Hence, empty definitions of functions were created. This
    particular function, possibly the last remaining example,
    was no longer even being used anywhere.
    
    Signed-off-by: Ron Minnich <rminnich@gmail.com>

commit 14233a08114895cad9e419b9ee67290010e65ea9
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Sun Apr 8 11:32:34 2012 -0500

    Actually return %ebx value from cpuid_ebx()
    
    Change-Id: I75f8f942950cad94439a10e389490ecfdd9272fe
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/880
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f42c377fed076426d1253941361caa4b17df961b
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Sat Apr 7 16:28:26 2012 +0530

    hexdump: fix compiler warning
    
    Fixed "warning: format not a string literal and no format arguments"
    
    Change-Id: If752a37f268c90f782c6e831e5477ea804e48026
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/878
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bernhard Urban <lewurm@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e875328c79ccf7a5ef266b2ab40a6b7c937da71c
Author: Ron Minnich <rminnich@gmail.com>
Date:   Thu Apr 5 20:25:38 2012 -0700

    Remove Dell s1850
    
    It's almost 10 years old. It never worked. It's a soldered in FLASH,
    so mistakes are fatal. It's got no redeeming features.
    
    Remove the dell directory. In 12 years of trying to work with Dell
    we have not had much interest. It's misleading to have it there.
    
    Change-Id: I83ff009bd7a6d5289229ca39608789ae5c33710b
    Reviewed-on: http://review.coreboot.org/876
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d3801f4f6fe985b7c16ada84a457da25f23b87a0
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 15:12:22 2012 -0700

    Add support for SMSC MEC1308/1310 SuperI/O EC
    
    Change-Id: If7921a66bab35f72c8455d5f0befc32a514ab417
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/825
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6626d6a9e3d8c6eb6b8348f6a0736d7971b736db
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 15:10:07 2012 -0700

    Add initial support for SMSC SIO1007 SuperI/O chip
    
    early_serial and some ACPI needed for compilation
    
    Change-Id: I5dd970676488697156e0630392884f31149ac85b
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/824
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8198600b0b71b474ac8ec75248d5dd916a2713ae
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 15:06:04 2012 -0700

    Add support for SMSC LPC47N207 SuperI/O chip
    
    This includes only early serial support for now.
    
    Change-Id: I9a2a439e1d17a989428033fdb4a4b813553dab6d
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/823
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2bdfb48b13ab5c392ef2b1dd9a8bfda6c90b2e18
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Apr 3 16:17:11 2012 -0700

    Fixes and Sandybridge support for lapic cpu init
    
    - preprocessor macros should not use defined(CONFIG_*) but
      just CONFIG_*
    - drop AMD CPU model 14XXX config variable use. Those do not exist.
    - skip some delays on Sandybridge systems
    - Count how long we're waiting for each AP to stop
    - Skip speedstep specific CPU entries
    
    Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/871
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

commit f8c7c2396eb843b17fd32d19bd9e481e088cee57
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Apr 6 04:03:50 2012 +0300

    Fix support for RAM-less multi-processor init
    
    Fix regression after commit:
      7dfe32c5408916b6cb23f1ec48e473e1c728d300
    
    Only align 16-bit entry on platforms that really require it,
    indicated by selecting SIPI_VECTOR_IN_ROM in CPU Kconfig.
    Disable assertion test of AP_SIPI_VECTOR for platforms not
    depending on this feature.
    
    Build of romstage should be fixed to get the vector address from
    bootblock build automatically.
    
    Change-Id: Ide470833c0254df1a9ff708369ab1c095ccfb98d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/875
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 334532eeffac3a26ffbd25bdf4808b87cad2a208
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Apr 5 15:59:33 2012 -0700

    Add Sandybridge/Cougar Point support to SMM relocation handler
    
    Previously this part of smmrelocate.S had to be omitted because
    the CONFIG_ options for those components did not exist yet. Add
    them back.
    
    Change-Id: I6ac94ca804e03062724401a08d1d174adac5e830
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/874
    Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
    Tested-by: build bot (Jenkins)

commit c00dfbc1c8358c1896e70fe147865dab370a5280
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Apr 3 16:24:37 2012 -0700

    Cache 8MB flash instead of 4MB
    
    Also fix the MTRR check to use the total_mtrrs
    variable instead of a hardcoded 8.
    
    Change-Id: I2c5ceb3910cd949f43ecf5b8aff857d6ffe0b1a5
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/873
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6293d307684215a040bef54f1fb8479bfec0755c
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Apr 3 16:07:56 2012 -0700

    Factor out function to find driver for a CPU
    
    This function can be used outside of the normal CPU setup
    
    Change-Id: I810c63b8aff868a6f69d5b992bea1cfae5a5996b
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/868
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 61f4a744c0df43dbce816195b0e8ae12fc7b2479
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Apr 3 16:21:04 2012 -0700

    Add constants for fast path resume copying
    
    cache as ram does not usually cache the ram before it is up. Hence,
    if romstage.c backs up resume memory, the involved memcpy is always
    uncached. This makes resume very slow.
    On Sandybridge we copy the memory later, after enabling caching, and
    that allows us to resume in as little as 250ms.
    
    Change-Id: I31a71ad4468679d39880cf9a8c4e497bb7addf8f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/872
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 5b6404e4195157eac8d97ae5bf30f45612109d57
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Apr 3 16:11:02 2012 -0700

    Fix timer frequency detection on Sandybridge
    
    Change-Id: Ide720bd91cde56a0afdd231d93500c371b1ffbe8
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/870
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit cab72d9b7b4bec1ee9464ed565edf7b192ef5c69
Author: Bernhard Urban <lewurm@gmail.com>
Date:   Thu Apr 5 17:13:27 2012 +0200

    amdfam10: add phenom II as known cpu
    
    Change-Id: I84a0f9e8e7a15c0aac8dc380de3ddf70b1decbd7
    Signed-off-by: Bernhard Urban <lewurm@gmail.com>
    Reviewed-on: http://review.coreboot.org/864
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit deda99783312ee0567465e87d4974bc434b27dcc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Apr 3 16:09:46 2012 -0700

    Invalidate cache before first jump
    
    Some CPUs (Sandybridge) seem to require this, and it does not hurt
    on other CPUs.
    
    Change-Id: I4fdb281b2b684ab5fea999aae28ca08dce24da4d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/869
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit c6b2166d89fcc3e4324a2888784b27109706b7e1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Apr 3 16:02:54 2012 -0700

    smbios: Don't fill out firmware version on ChromeOS
    
    In ChromeOS we potentially have different payloads with
    different versions. Since the user land tools get information
    on which one of them is loaded, leave the string in smbios
    empty so we can fill it out in the payload.
    Also fill out system version number and serial number with
    some constant values.
    
    Change-Id: Id1fed5a54b511c730975fa83347452f1274b8504
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/867
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 31324c64e12135f09590884421cbcbcabec1a62f
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 5 21:22:02 2012 +0200

    Fill out ChromeOS specific coreboot table extensions
    
    ChromeOS uses two extensions to the coreboot table:
    - ChromeOS specific GPIO description for onboard switches
    - position of verified boot area in nvram
    
    Change-Id: I8c389feec54c00faf2770aafbfd2223ac9da1362
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/866
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8c5b58e7c372d0c1666931040e35fef92ad56c4b
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 4 10:38:05 2012 -0700

    Update documentation in smmrelocate.S to mention TSEG
    
    Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/861
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5c55463f500528b69c47a06da22339fa85d70b7e
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 4 00:09:50 2012 +0200

    Add support for Intel Sandybridge CPU
    
    Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/855
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 00636b0daefc3c499990744226a0e1a316d71731
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 4 00:08:51 2012 +0200

    Add support for Intel Sandybridge CPU (northbridge part)
    
    Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/854
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 4dd3853437a3506880e2879e6640d455778f6413
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Apr 5 11:18:23 2012 +0200

    Ignore .exe files in whitespace test
    
    On windows, we sometimes require getopt executables, which end up
    in the source tree. These shouldn't break the whitespace test.
    
    Change-Id: Iaf86e38b94605bebb69a317e00f932eefcf468b9
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/863
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 92cfe183a75c530331c8dd371cc9719f4ba31992
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Apr 5 11:17:01 2012 +0200

    Add getopt implementation to abuild
    
    Similar to buildgcc, abuild requires getopt(1). Provide an
    implementation for platforms without it (Win32)
    
    Change-Id: I2ae4d84e06dd34135c97b18819da2b49a89706ce
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/862
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit fb89dd0a9357f6c633772ac5d0a4b6b1c2d563c0
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 16:28:20 2012 -0700

    Use fast memset in SMM mode, too
    
    ... and always include IP checksumming in romstage.
    It's generally useful and our upcoming port needs it.
    
    Change-Id: I248402d96a23e58354744e053b9d5cca6b74ad3a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/827
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8e073829ec69ee89b3e91f4c040c96988084a526
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 4 00:07:22 2012 +0200

    Add support for Intel Panther Point PCH
    
    Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/853
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit cb91e1525eb0b81f9bc2e24e3404d6a9efc1cce3
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Apr 3 23:28:22 2012 +0200

    Add support for mainboard specific suspend/resume handler
    
    Some mainboards (most likely laptops) will need mainboard specific functions
    called upon a resume from suspend.
    
    Change-Id: If1518a4b016bba776643adaef0ae64ff49f57e51
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/852
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit ec207630a50a61c98816b2a65183a064b230eda6
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 4 00:21:37 2012 +0200

    Move TPM code to romstage
    
    We want to do TPM initialization as early as possible to keep
    the impact on boot time low. Therefore move it to romstage.
    
    Change-Id: I5f2e021e0b11bd70a78ad1f05ec09802d015dd9e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/856
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 15511835b9e60d08ac5eb3c4ff326cec8c43ed6d
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Apr 3 18:53:48 2012 +0200

    Drop verified boot code from acpi.c
    
    We changed our verified boot initialization to run from romstage,
    as that allows faster boot times and does not add as much ChromeOS
    specific code to generic files.
    
    Change-Id: Id4164c26d524ea0ffce34467cf91379a19a4b2f6
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/851
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f13772af9f8957e011dbaf721a3f617bf61881b7
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 4 00:31:14 2012 +0200

    Drop duplicate inclusion of src/vendorcode
    
    Change-Id: I95908bdca51c5ee959ae9f2307d4b6e0e002d04a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/857
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit 3aa067f595115a62afdfc9acc33f08e9c96da850
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Apr 2 13:24:04 2012 -0700

    Add support to run SMM handler in TSEG instead of ASEG
    
    Traditionally coreboot's SMM handler runs in ASEG (0xa0000),
    "behind" the graphics memory. This approach has two issues:
    - It limits the possible size of the SMM handler (and the
      number of CPUs supported in a system)
    - It's not considered a supported path anymore in newer CPUs.
    
    Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Acked-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/842
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 6efbebdb58357b8d1aad43f51c91defd452296f6
Author: Mathias Krause <minipli@googlemail.com>
Date:   Tue Apr 3 21:02:33 2012 +0200

    libpayload: avoid excessive casts in printf.c
    
    struct printf_spec is a purely internal structure. Avoid excessive casts
    when using the write function pointer just to make the compiler happy by
    using the right types in the first place.
    
    Change-Id: Ia4f3c79a5283cb76c8aa5f9d1eee758676303382
    Signed-off-by: Mathias Krause <minipli@googlemail.com>
    Reviewed-on: http://review.coreboot.org/850
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 67997d330dae9c12eb640aa21f7e51b193890461
Author: Mathias Krause <minipli@googlemail.com>
Date:   Tue Apr 3 20:42:01 2012 +0200

    libpayload: minor cleanups
    
    Apply some const correctness to const/non-const strings in libc and
    libpci (what an ugly cast that was).
    
    Remove duplicated NULL test in printf_putstr(), already done in
    print_string() - reduces size of libpayload by a few bytes.
    
    Change-Id: I13f479df13e39d79cab291e9d99d153e1ef43eae
    Signed-off-by: Mathias Krause <minipli@googlemail.com>
    Reviewed-on: http://review.coreboot.org/849
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit f17789c4ff8faf0340946f8ba6c3b35c02e36cee
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Apr 3 11:22:15 2012 -0700

    Don't unconditionally show ChromeOS options
    
    Google ChromeOS specific options were shown in the main menu
    unconditionally, even on non-ChromeOS devices. Instead, hide
    these options unless CONFIG_CHROMEOS is set, and also put them
    in a separate menu.
    
    Change-Id: I75f533ed5046d6df4f7d959a0ca4c2441340ef2f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/848
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit ea37a21acf22a3c63c265e127584b65722f145b5
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Apr 2 13:35:09 2012 -0700

    Add support for Intel Turbo Boost feature
    
    From wikipedia:
    Intel Turbo Boost is a technology implemented by Intel in certain
    versions of their Nehalem- and Sandy Bridge-based CPUs, including Core
    i5 and Core i7 that enables the processor to run above its base
    operating frequency via dynamic control of the CPU's "clock rate".
    It is activated when the operating system requests the highest
    performance state of the processor.
    
    Change-Id: I166ead7c219083006c2b05859eb18749c6fbe832
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/844
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3d7c6770c4e3db539b2b0ef6088977922ef8b924
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Apr 2 13:30:10 2012 -0700

    smbios: add support for onboard devices extended information
    
    Add support for type 41 smbios tables (to be used by board
    specific smbios handlers)
    
    Change-Id: Id6af5e4b1f5c5c78c63759d24fdc7cf8537ae5e6
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/843
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4a2daf6a99dcdcf177bf9e0d630fec8b5b65ca30
Author: Patrick Georgi <Patrick.Georgi@secunet.com>
Date:   Fri Mar 9 12:54:03 2012 +0100

    nvramtool: 64bit safe CBFS handling
    
    Change-Id: I4f23ee04cd6479e55e9467af1b0196936412deb1
    Signed-off-by: Patrick Georgi <Patrick.Georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/846
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3bbd2bfa1c2343c6f28e7a1935c485848340116e
Author: Patrick Georgi <Patrick.Georgi@secunet.com>
Date:   Fri Mar 9 12:30:07 2012 +0100

    Add preprocessing capabilities to the cbfs-files mechanism
    
    It's now possible to generate files that are about to be added to
    CBFS by specifying "sourcefile:method" as real file name.
    
    This makes the build system use the cbfs-files-preprocessor-$(method)
    function to create a file from sourcefile. That generated file is
    then added to CBFS.
    
    The first method to be defined is "nvramtool". It expects a plain text
    specification of the CMOS configuration and emits the binary format
    suitable for cmos.default.
    
    Change-Id: I33a142718fc7238eaf5317b0ed62b4726d9b48f2
    Signed-off-by: Patrick Georgi <Patrick.Georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/847
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 499fc926f8c877ab049f936fb9da7234e123edfb
Author: Patrick Georgi <Patrick.Georgi@secunet.com>
Date:   Fri Mar 9 10:53:52 2012 +0100

    Add nvramtool to coreboot build system
    
    This way we can depend on it during build.
    
    Change-Id: I7e773c6a029e376e3d70d0a8c9e96ffe0c2cf82e
    Signed-off-by: Patrick Georgi <Patrick.Georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/845
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit abdf15f40b1e0838a43a54704ba5277c8210d69f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 28 14:01:34 2012 +0200

    Apply cache-as-ram conditionally on socket mPGA604
    
    The socket mPGA604 is for P4 Xeon which to my knowledge is always
    HT-enabled. I assume the existing usage of car/cache_as_ram.inc
    on socket_mPGA604, namely the Tyan S2735, as broken.
    
    Existing car/cache_as_ram.inc has invalid SIPI vector and it does
    not initialise AP CPU's to activate L2 cache.
    
    Other mPGA604 boards are not affected, as they have not been
    converted to CAR.
    
    Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/607
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit afd141d5043b4e1489c4e4796fc50c43ef9b23e2
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Mar 30 15:32:07 2012 +0800

    S3 code whitespaces changes.
    
    some blank changing is integrated into the previous patches, which hold
    the unsplitted diff hunk.
    
    Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/625
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 01bd79ff697b4a6976e2b03ff15f4853fa561c0d
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Mar 23 11:36:08 2012 +0800

    Add sb800 spi support.
    
    It is for S3, storing the recovring data in the nonvolatile storage,
    i.e., flash.
    
    Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/620
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 971804ed68347f4fe7ca985a3c924b28041a4079
Author: Mathias Krause <minipli@googlemail.com>
Date:   Sun Apr 1 11:32:09 2012 +0200

    x86, oprom: ensure DF is always cleared
    
    The Option ROM might mess with the EFLAGS register and break assumptions
    the C part of coreboot implicitly has, e.g. the state of the direction
    flag.
    
    Prevent Option ROMs from confusing coreboot by restoring the old EFLAGS
    value after the Option ROMs has finished and always clear the direction
    flag before calling the C part of the interrupt handler.
    
    Change-Id: I84663be6681b17f95f48d93f0b730e443336b4a8
    Signed-off-by: Mathias Krause <minipli@googlemail.com>
    Reviewed-on: http://review.coreboot.org/837
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 74a0efe09a203959d5ab4879e4c1cf139c93b410
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 17:10:49 2012 -0700

    [ChromeOS] Don't initialize VGA Option ROM in normal mode
    
    ChromeOS features two different modes: normal mode and developer mode
    (aka jailbreak mode). In developer mode, we need to display a warning
    screen for security reasons.
    
    However, in normal mode we want to boot blazingly fast. Therefore we
    don't run (VGA) option ROMs, unless we have to print something on the
    screen before the kernel is loaded.
    
    Change-Id: I37f63d0b082a48e037e65bde2b380f9b8743ed29
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/829
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 020b22a5c4efd82937706372817fc441c5345d68
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 17:06:43 2012 -0700

    Add EC component for SMSC MEC1308/1310
    
    Change-Id: I92109fb633a1a3090b4b1767dd119b8c8a1b5f81
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/828
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b0dd1d91f49eef80016a60bb09e2c1a8cfcc628e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 15:04:07 2012 -0700

    Add support for ITE IT8772F SuperI/O chip
    
    Change-Id: I8e80c22eb0f3cb68f2457be6b2e7894df60ed632
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/822
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dc8448fd8be4768ef9d5f9b8cbcf28db0a2029be
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 13:52:58 2012 -0700

    Add a helper function to determine the number of enabled CPUs
    
    Change-Id: Ia72926002571e0f250849fa5db048bd8b2e92400
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/821
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit d40393e3903e57496afcfc88ec094ae17f0e9437
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 13:00:46 2012 -0700

    Align: Make sure 1 is treated as unsigned long instead of int
    
    ... and drop duplicate definition in via/epia-n code.
    
    Change-Id: Id79daaaa35c4d412c8c1f621a3638d129681d331
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/820
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 9aea04aa892903009e487ada7f7b911691e68630
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 12:01:06 2012 -0700

    Add Google ChromeOS vendor support
    
    Google's ChromeOS can be booted super fast and safely
    using coreboot. This adds the ChromeOS specific code that
    is required by all ChromeBooks to do this.
    
    Change-Id: Ic03ff090a569a27acbd798ce1e5f89a34897a2f2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/817
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c302d20ed3f67f863e02dce51aeef8aa90ef2742
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Mon Oct 24 14:06:23 2011 -0700

    Force coreboot mconf to create temp files in the output directory
    
    This change partially addresses the problem with attempting to
    generate coreboot image out of tree. The configuration step fails when
    in cheroot, if the destination directory is placed in /tmp.
    
    The problem is that the mconf package tries renaming the temporary
    file created in the local directory into the destination config file.
    If the destination root and the local directory are located on
    different file systems, the rename operation fails.
    
    The proper fix (still upcoming) would be to identify all places where
    mconf creates temp files, and make sure that all temp files get
    created in the destination tree.
    
    This change modifies just one location, which prevents building out of
    tree in the most common case.
    
    Test:
      run the following in the coreboot directory in chroot:
        (coreboot) cp config.lumpy .config
        (coreboot) /bin/rm -rf /tmp/cb
        (coreboot) CROSS_COMPILE=i686-pc-linux-gnu- make obj=/tmp/cb oldconfig
        (coreboot) CROSS_COMPILE=i686-pc-linux-gnu- make obj=/tmp/cb
    
      Observe the build succeed (it was failing during the config phase
      before this change)
    
    Change-Id: If4506e984b8afc192a1689c7b0aa956dd35f66c6
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/815
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e1bb49e2ece1eda6a3d566b48b7a8e50a3469f63
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Jan 27 00:33:47 2012 -0800

    Add a "remove" command to cbfstool
    
    This command removes the first file it finds with the given name by changing
    its type to CBFS_COMPONENT_NULL and setting the first character of its name to
    a null terminator. If the "files" immediately before or after the target file
    are already marked as empty, they're all merged together into one large file.
    
    Change-Id: Idc6b2a4c355c3f039c2ccae81866e3ed6035539b
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-by: Ronald G. Minnich <rminnich@google.com>
    Reviewed-on: http://review.coreboot.org/814
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dd30acdd590f6a39a5d3c4a38e3d949e73b5e2fa
Author: Mathias Krause <minipli@googlemail.com>
Date:   Sat Mar 31 17:23:53 2012 +0200

    Fix issues with x86 memcpy
    
    The x86 memcpy() implementation did not mention its implicit output
    registers ESI, EDI and ECX which might make this code miscompile when
    the compiler uses the value of EDI for the return value *after* the 'rep
    movsb' has completed. That would break the API of memcpy as this would
    return 'dst+len' instead of 'dst'.
    
    Fix this possible bug by removing the wrong comment and listing all
    output registers as such (using dummy stack variables that get optimized
    away).
    
    Also the leading 'cld' is superflous as the ABI mandates the direction
    flag to be cleared all the time when we're in C (see
    <http://gcc.gnu.org/gcc-4.3/changes.html>) and we have no ASM call sites
    that might require it to be cleared explicitly (SMM might come to mind,
    but it clears the DF itself before passing control to the C part of the
    SMI handler).
    
    Last but not least fix the prototype to match the one from <string.h>.
    
    Change-Id: I106422d41180c4ed876078cabb26b45e49f3fa93
    Signed-off-by: Mathias Krause <minipli@googlemail.com>
    Reviewed-on: http://review.coreboot.org/836
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 819c7d4a35b7b11a832d8e52d34b6f5b32e24cc4
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Mar 31 13:08:12 2012 +0200

    Whitespace fixes
    
    Change-Id: I441326ecbda72ec7e99fc99bf40a81aa7e94ee26
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/834
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit 087b24db2d7b4e3f6f6ec238b958835c67f5cd42
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Wed Feb 22 11:46:17 2012 -0700

    Update xcompile to search for x86_64 toolchain.
    
    This adds detection of x86_64 gcc toolchain (which buildgcc can build
    if provided the option).
    
    Change-Id: I8b12f3e705157741279c7347f4847fb50ccc2b0e
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/673
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
    Tested-by: build bot (Jenkins)

commit b9fa1ed5e80b607df59783cdc406d85bcccf63f5
Author: Gabe Black <gabeblack@google.com>
Date:   Mon Mar 5 15:49:32 2012 -0800

    Make libpayload parse the coreboot tables before setting up the consoles
    
    At least one of the console drivers, coreboot fb, uses information in the
    sysinfo structure to set itself up. If that structure hasn't been populated,
    the driver decides that there is no framebuffer and disables itself. Reversing
    the order these are set up fixes that problem.
    
    Change-Id: Idd8b5518980dfdd82fd4359dd0133ab7736fc428
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/816
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cbb648c001167f7762e0f1aa2af906d3a8e34715
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Mar 30 12:11:04 2012 -0700

    Enable -Werror for romcc
    
    ... and remove some dead code.
    
    Change-Id: Id959bdf57af09db2a1f5742555c2dcabca38ac9a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/818
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d086d51b5e550d65ad118db71d23c88429df3262
Author: zbao <zheng.bao@amd.com>
Date:   Fri Mar 23 10:26:28 2012 +0800

    Keep cscope.out when distclean.
    
    It doesnt make sense to delete cscope.out when make
    distclean. Distclean is done all the time, and cscope database is also
    needed all the time. If we need to delete all the untracked files, we
    can use git-clean.
    
    Change-Id: Ic248ccd602ddc88d0b98d5d7f6cbbf530cd82e87
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/831
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a860c683bc257c94f836b444bb7e67039b86f8d2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 28 02:06:45 2012 +0200

    Intel cpus: get MAXPHYADDR at runtime for new CAR
    
    Use CPUID to get MAXPHYADDR and set MTRR masks correctly.
    Also only BSP CPU clears MTRRs and initializes its Local APIC.
    
    Change-Id: I89ee765a17ec7c041284ed402f21d9a969d699bd
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/686
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0078ceb553a1d87ea0a948c3e7e2c59ab4d2e65e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 28 02:02:27 2012 +0200

    Intel cpus: add hyper-threading CPU support to new CAR
    
    This improvement of CAR code starts the sibling CPU processors and
    clears their cache disable bits (CR0.CD) in case a hyper-threading
    CPU is detected.
    
    Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/604
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 05d6ffba0f33926eb74e104a1ab86e474b5dd71b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Feb 16 23:12:04 2012 +0200

    Intel cpus: improve CPU compatibility of new CAR
    
    Most or many Xeons have no MSR 0x11e.
    
    I have previously tested that a HT-enabled P4 (model f25) can
    execute this but will not have cache-as-ram enabled. Should work
    for non-HT P4.
    
    Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/644
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7dfe32c5408916b6cb23f1ec48e473e1c728d300
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 14 10:39:17 2012 +0200

    Add support for RAM-less multi-processor init
    
    For a hyper-threading processor, enabling cache requires that both the
    BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram
    implementation, partial multi-processor initialisation precedes
    raminit and AP CPUs' 16bit entry must be run from ROM.
    
    The AP CPU can only start execute real-mode code at a 4kB aligned
    address below 1MB. The protected mode entry code for AP is identical
    with the BSP code, which is already located at the top of bootblock.
    This patch takes the simplest approach and aligns the bootblock
    16 bit entry at highest possible 4kB boundary below 1MB.
    
    The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR
    used by the CAR code in romstage. Adress is not expected to ever
    change, but if it does, link will fail.
    
    Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/454
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f9d1a42d98b121088b0c242b4d9f5d0eb78d38de
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 28 01:45:44 2012 +0200

    Intel cpus: apply some good programming practices in new CAR
    
    Delete dead CAR code and whitespace fixes.
    
    Replace cryptic 32bit hex values with existing LAPIC definitions.
    
    Do not assume state of direction flag before "rep" instruction.
    
    Do not load immediate values on temporary registers when not needed.
    
    Parameter pushed on stack was not popped (or flushed) after returning
    from call. This is a sort-of memory leak if multiple call's are
    implemented the same way.
    
    Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/643
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 325b92f64a62f355715a45470e41407ce3c39c1e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 28 00:24:15 2012 +0200

    Intel cpus: cache actual size of the Flash ROM device
    
    Cache was enabled for the last 4 MB below 4 GB when ramstage is
    loaded. This does not cover the case of a 8 MB Flash and could
    overlap with some system device placed at high memory.
    
    Use the actual device size for the cache region. Mainboard
    may override this with Kconfig CACHE_ROM_SIZE if necessary.
    
    Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/641
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5a660ca2293cbf4c1ae44a2f37f9f389124eb749
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 28 00:15:30 2012 +0200

    Intel cpus: copy model_6ex CAR code
    
    Copy model_6ex CAR as car/cache_as_ram_ht.inc to be extended
    with hyper-threading CPU support.
    
    Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/606
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d842f1fe24ec5d507f965ccb25112b12a22e9938
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Mar 26 19:03:44 2012 +0300

    Makefile: rename romstage linking filenames
    
     $(obj)/location.txt ->  $(obj)/romstage/base_xip.txt
     $(obj)/romstage/link1st.ld -> $(obj)/romstage/link_null.ld
     $(obj)/romstage/link2nd.ld -> $(obj)/romstage/link_xip.ld
    
    Change-Id: I15cf29b13a846729f19ecefb21819c4e66681155
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/812
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a01ec147e9bd0df0f38a74938640443f7dd2cd6d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Mar 31 10:21:29 2012 +0300

    Makefile: split romstage linking to separate rules
    
    After change it is more clear how romstage is linked twice and with
    what scripts. Also with the change, it is easier to add some
    object of static size that need to be re-compiled for the 2nd link.
    One such object could be md5sum of executable.
    
    Change-Id: Ib34d1876071a51345c5c7319a0ed937868817fd1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/803
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 608d15b6960246e29a221d2b6bb4a94e6d224627
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Mar 31 09:48:11 2012 +0300

    Fix coreboot makefiles not to produce half baked output.
    
    There were cases where output file was generated and modified within
    a recipe. If make was interrupted, it could exit with an output file
    that appears as up-to-date, but was generated with incomplete recipe.
    
    The output file should be created only when successful, in an atomic
    operation. There could be other places in the make system which
    require a similar fix, this needs to be investigated further.
    
    Change-Id: I25c8ee23577a460eace196fd28c23cc67aa72a9a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/830
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5fdc00a52f7baf67d560ede055606d463eec3821
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Mar 31 11:05:52 2012 +0300

    Drop obsolete TINY_BOOTBLOCK
    
    Change-Id: I0cbb5f7fce91fe65fe8daad00fc43e68337783b0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/832
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a7b296d450c5d948b95c1342f726334b4e5a4c68
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Nov 14 12:40:34 2011 -0800

    Fix warnings in coreboot utilities.
    
    - Fix some poor programming practice (breaks of strict aliasing as well
      as not checking the return value of read)
    - Use PRIx64 instead of %llx to prevent compilation warnings with both
      32bit and 64bit compilers
    - Use same compiler command options when linking inteltool and when
      detecting libpci for inteltool
    
    Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/752
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit 8acbc2a8865ca74f0f80c51c6511b9ab4c03d552
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Nov 17 13:03:38 2011 -0800

    use movsl for copying resume memory back
    
    It's not significantly faster, but easier to read and smaller.
    
    Change-Id: Ibab0b478873912d67bf1f07743f628586353368a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/755
    Reviewed-by: Mathias Krause <minipli@googlemail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 77adc5e03cd72ba4091ebf446abc3b19a73ee8fb
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Nov 30 12:45:14 2011 -0800

    Don't unconditionally add support for cardbus and pci-x devices
    
    It's still on by default.
    
    Change-Id: I8b6539eaf2f8d6a4fa975deb14789a00f2090d34
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/756
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dfb098d3592704f64087f2677a5d3dd7f7e5e422
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Nov 17 12:50:54 2011 -0800

    Add DEBUG_TPM option to Debugging menu
    
    instead of having to edit the source code of tpm.c
    
    Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/757
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7b67892be88e3f12de91314ca45a834b4c84c719
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jan 9 22:05:18 2012 -0800

    Make MTRR min hole alignment 64MB
    
    This affects the algorithm when determining when to
    transform a range into a larger range with a hole.
    
    It is needed when for when I switch on an 8MB TSEG
    and cause the memory maps to go crazy.
    
    Also add header defines for the SMRR.
    
    Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/765
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 527fc74a83a7b0fdeebfeb9ddd5890f11f01c102
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Fri Jan 6 15:49:30 2012 -0800

    Fix MB calculation in the reporting of the MTRR hole
    
    Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/763
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 7389fa945f48c6da6e5f39d871c0efd9dfba93a1
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Thu Dec 22 10:59:40 2011 -0800

    MTRR: add alternate allocation method for odd memory maps
    
    With >= 4GB memory installed we get a memory map split in the middle
    due to remap that has boundaries that are inconveniently aligned for
    MTRRs due to the various UMA regions.
    
    0000MB-2780MB  2780MB  RAM     (writeback)
    2780MB-2782MB     2MB  TSEG    (uncached/SMRR)
    2782MB-2784MB     2MB  GFX GTT (uncached)
    2784MB-2816MB    32MB  GFX UMA (uncached)
    2816MB-4096MB  1280MB  EMPTY   (N/A)
    4096MB-5368MB  1272MB  RAM     (writeback)
    5368MB-5376MB     8MB  ME UMA  (uncached)
    
    The default MTRR allocation method of trying to cover everything
    with one MTRR and then carve out a single uncached region does
    not work for the GPU aperture which needs write-combining type,
    and it also has issues trying to cover the uneven boundaries
    in the avaiable variable MTRRs.
    
    My goal was to make a minimal set of changes and avoid modifying
    behavior on existing systems with an algorithm that is not always
    optimal for a typical memory layout.  So the flag 'above4gb=2'
    will change these allocation behaviors:
    
    1) Detect the number of available variable MTRRs rather than
    limiting to hardcoded value.  We need every last MTRR.
    
    2) Don't try to cover all RAM with one MTRR, instead let each
    RAM region get covered independently.
    
    3) Don't assume uma_memory_base is part of the last region
    and increase the size of that region.  In this case the UMA
    region is carved out from the lower memory region and it is
    already declared as part of the ram region.
    
    4) If a memory region can't be covered with MTRRs >= 16MB then
    instead make a larger region and trim it with uncached MTRRs.
    
    Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/761
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 67e6c2aaf4d4194dac824014197cc684af9750f5
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Jan 18 10:05:18 2012 -0800

    Don't re-init EBDA in S3 resume path.
    
    I forgot to implement this the first time around.
    
    It does not seem to cause noticeable problems but
    in heavy suspend/resume testing I saw a suspicious
    crash in the kernel when trying to bring one of the
    CPUs back online.
    
    Change-Id: I950ac260f251e2683693d9bd20a0dd5e041aa26e
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/770
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b4aaaa7632116c2fe466095d0cd3cc1247344ca6
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Jan 17 09:03:11 2012 -0800

    Prepare the BIOS data areas before device init.
    
    Since we do not run option roms in normal mode nothing was
    initializing the BDA/EBDA and yet Linux depends very much
    on it having sane values here.  For the most part the kernel
    tries to work around this not being initialized, but every
    once in awhile (1/300 boots or so) it would end up reading
    something that looked sane from BDA but was not and then
    it would panic.
    
    In this change the EBDA is unconditionally setup before devices
    are initialized.  I'm not set on the location in dev_initialize()
    but there does not seem to be another place to hook it in so
    that it runs just once for ALL platforms regardless of whether
    they use option roms or not. (possibly hardwaremain?)
    
    The EBDA setup code has been moved into its own location in
    arch/x86/lib/ebda.c so it can be compiled in even if the option
    rom code is not.
    
    The low memory size is still set to 1MB which is enough to make
    linux happy without having to hook into each mainboard to get a
    more appropriate value.  The setup_ebda() function takes inputs
    so it could be changed for a mainboard if needed.
    
    OLD/BROKEN would read garbage.  Examples from different boots:
    ebda_addr=0x75e80 lowmem=0x1553400
    ebda_addr=0x5e080 lowmem=0x3e51400
    ebda_addr=0x7aa80 lowmem=0x2f8a800
    
    NEW/FIXED now reads consistent values:
    ebda_addr=0xf6000 lowmem=0x100000
    
    Change-Id: I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/769
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1d0b1d4db4eaf41dc7f6b73410cb2612e8769038
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Nov 17 11:13:36 2011 -0800

    vga_io.c is not needed unless CONFIG_VGA is set
    
    hence disable it.
    
    Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/753
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bb1177e16eb899aeff45e313e322cdb5d8f890f7
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Wed Nov 9 14:11:26 2011 -0800

    Allow components smaller than declared size.
    
    idftool was failing to add the ME blobs into the output image in case
    the blob size does not exactly match the size allocated for it in the
    flashrom structure.
    
    It is difficult to set the field in the structure to exactly match the
    size (for some reason Intel flash tool fails to insert the correct
    size even when given the exact ME blob). On the other hand there is no
    harm in using am ME blob smaller than the allocated size, this change
    modifies the tool building the image to allow for smaller components.
    
    Change-Id: I1b04f90051b91157391943c9bad0eb06dd297431
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/751
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8bb772379f89cfd79be56f85d822798fb063360a
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jan 9 22:11:25 2012 -0800

    Add Kconfig options to enable TSEG and set a size
    
    Future CPUs will require TSEG use for SMM
    
    Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/766
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 689e31d18b0fdefdef2d3b2947355e07b496ce77
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jan 9 22:00:30 2012 -0800

    Make cpuid functions usable when compiled with PIC
    
    This avoids using EBX and instead uses EDI where possible,
    and ESI when necessary to get the EBX value out.
    
    This allows me to enable -fpic for SMM TSEG code.
    
    Also add a new CPUID extended function to query with ECX set.
    
    Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/764
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit 5d3438de41368acc89d80af7b8d235d0d1b19b60
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Jan 7 01:03:42 2012 -0800

    Revamp cbmem.py to use the coreboot tables.
    
    This change makes significant changes to cbmem.py to make it use the
    coreboot tables to find the memory console and timestamp areas instead
    of looking for the in memory table TOC structure. That appears to be
    more robust and gets cbmem.py working again after some unrelated
    changes that affected memory layout.
    
    It also introduces some small infrastructure to make accessing C style
    structures in physical memory easier and more transparent.
    
    Change-Id: I51833055a50c2d76423520ba6e059bf8fc50adea
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/762
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 67aa3d6b878c5deea8d14054cce700ac1d045505
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Dec 15 09:24:40 2011 -0800

    drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
    
    Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/760
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5e02bc6d7ef7f976629a7bfb35429527a77e6321
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Nov 17 13:05:31 2011 -0800

    Make PCI CONF2 support a compile time option
    
    It's not used on any board supported by coreboot but has been
    detected at run time since ages. No new boards (since 2000?)
    are using the CONF2 method, so it is unlikely we ever have to
    turn this on for a board.
    
    Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/758
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit bf729baa2c7b2fbfa03e271c4f3f5707989e43b5
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Nov 4 12:31:58 2011 -0700

    Add more timestamps in coreboot.
    
    This adds a number of timestamps in ramstage and romstage
    so we can figure out where execution time goes.
    
    Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/749
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 10fea924772be63b668d3d8c8879570487bbc109
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Sat Nov 5 02:07:01 2011 +0000

    Fix coreboot makefiles not to produce half baked output.
    
    It looks like the cbfstool utility generates the output file even when
    it fails to generate it properly. This causes make, if started second
    time in a row, after cbfstool failure, to continue beyond the point of
    failure (as the corrupted output file is present in the output tree,
    the second make invocation presumes that it is valid, as it is newer
    than the dependencies).
    
    The output file should be created only when successful, in an atomic
    operation. There could be other places in the make system which
    require a similar fix, this needs to be investigated further.
    
    Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/750
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit cde7801c2e5560ef0c923a41beac4f4cdc3fcbd4
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Wed Oct 19 15:32:39 2011 -0700

    Add timestamps for selfboot and acpi wake
    
    Change-Id: I28224867610b947739d940d25c98399d219f10f4
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/733
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c668af74412cb7cae24957e9a86320be5493434d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Oct 27 21:28:25 2011 +0000

    Make TPM driver work in rom stage.
    
    Change-Id: Ifc827d0cd0159aa3f6752d395974f2812334f262
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/738
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 3008bbadcbbb64dab0472e1724744c37b4094aa9
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Oct 11 14:46:25 2011 -0700

    Add TPM support to coreboot
    
    and initialize the TPM on S3 resume
    
    This patch integrates the TPM driver and runs TPM resume upon an ACPI S3
    resume without including any other parts of vboot.
    
    We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS
    (that are incompatible with coreboot's) and it does a lot more than we
    want it to do.
    
    Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/731
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b89a761a637996e730432a3a8383aaf636abe5c5
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Mar 30 01:01:51 2012 +0200

    Add Google ChromeOS vendorcode directory
    
    ... and hook it up in Kconfig. More code to come.
    
    Change-Id: I24542d8ef97e2bce112c3aface681ceeb1a7c061
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/813
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 00093a81d3f54c72215d9f402c3f88880da89a81
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Nov 2 16:12:34 2011 -0700

    Add an option to keep the ROM cached after romstage
    
    Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/739
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1afe51af83ad0beb3f0ace1085524b327ecff7c6
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Oct 26 22:11:52 2011 +0000

    Add native memset() function on x86
    
    Change-Id: Ia118ebe0a4b59bdcefd78895141a365170f6aed2
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/737
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 0054afa11daa8db78dbe6aa55150238525187596
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Oct 25 23:43:34 2011 +0000

    Add faster, architecture dependent memcpy()
    
    Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/736
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 19e7e7d2e7cb4ff0ae821448355ec8b14e0bd2bf
Author: Gabe Black <gabeblack@google.com>
Date:   Sat Oct 1 04:27:32 2011 -0700

    Add infrastructure for global data in the CAR phase of boot
    
    The cbmem console structure and car global data are put in their own section,
    with the cbmem console coming after the global data. These areas are linked
    to be where CAR is available and at the very bottom of the stack.
    
    There is one shortcoming of this change:
    The section created by this change needs to be stripped out by the Makefile
    since leaving it in confuses cbfstool when it installs the stage in the image.
    I would like to make the tools link those symbols at the right location but
    leave allocation of that space out of the ELF.
    
    Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/727
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4d04a715475a60f627ddeded3385ca04d883a55b
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Oct 5 01:52:08 2011 -0700

    Detect whether the OXPCIE card is really present while in the ROM stage.
    
    Use an int in CAR global data to store whether or not the OXPCIE serial card
    is actually there. Also, time out if the card doesn't show up quickly enough,
    don't continue initialization if it's not there, and don't make the
    initialization routine default to a card if none is found.
    
    Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/728
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1b632aff260695257b78bedc3742652916f2a724
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Oct 4 16:21:17 2011 -0700

    Fix typos in src/console/Kconfig
    
    - cash -> Cache
    - make the new size of the cbmem console buffer the default
    
    Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/726
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 90dcdd43ee83b12ddd1cdafba7613971cbfa2117
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Tue Oct 25 14:15:11 2011 -0700

    Add support for enabling PCIe Common Clock and ASPM
    
    These are guarded by individual Kconfig entries. The deprecated
    CONFIG_PCIE_TUNING defines have been removed in favor of using specific
    config options.
    
    This is the generic half, there is board-specific pieces
    still to come that tune before and after ASPM is enabled.
    
    Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/735
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 22c0468d3927a370b9723e9e78714c2731d33a81
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Mon Oct 3 14:58:57 2011 -0700

    Refactor publishing CBMEM addresses through coreboot table.
    
    We need to provide u-boot access to several different CBMEM
    sections. To do that, a common coreboot table structure is used,
    just different tags match different coreboot table sections.
    
    Also, the code is added to export CBMEM console and MRC cache
    addresses through the same mechanism.
    
    Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/724
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 2e43867a20107014cba1f32137adfee8af35a05d
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Fri Sep 23 09:56:11 2011 -0700

    Add timestamp table pointer to the coreboot table.
    
    This change exports the timestamp table pointer through coreboot
    table to make it possible for u-boot to add timestamps to the
    table.
    
    Inclusion of cbmem.h allows to drop external declarations in
    coreboot_table.c.
    
    Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/716
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit b93f74bb0776c9911f9b5f5d965610a76a0b31cc
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Fri Sep 30 14:21:03 2011 -0700

    Introduce utility for parsing CBMEM contents.
    
    This is a python script which is supposed to run on a target
    which is controlled by coreboot. The script examines top of
    memory looking for the CBMEM signature at addresses aligned at
    128K boundary. Once the script finds the CBMEM, it iterates
    through the CBMEM table of contents and parses two entries: the
    timestamps and the console log.
    
    This submission is just a template to build upon to create a
    utility for displaying CBMEM information while running Linux on
    the target.
    
    BUG=chrome-os-partner:4200
    TEST=manual
    
    See test description of d81e6b8c8d41f2d6 for test procedure.
    
    Change-Id: Id863a8598eaadc2d20d728f9186843e65cbe6f37
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: https://gerrit-int.chromium.org/5942
    Tested-by: Vadim Bendebury <vbendeb@google.com>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/723
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 3e31600e62a260c377ac67b305530a5e93c07051
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Fri Sep 30 12:02:18 2011 -0700

    CBMEM CONSOLE: Enable coreboot CBMEM console.
    
    The appropriate Makefiles are modified to include the required
    source code in compilation.
    
    Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/722
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 1078c67af1228a556b1c5c182e8616271f6b7919
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Fri Sep 30 11:16:49 2011 -0700

    CBMEM CONSOLE: Add code using the new console driver.
    
    The new added code is compiled in when the CBMEM_CONSOLE config
    flag is enabled.
    
    Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/721
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit be25a4ded0957a0ca31f94d32857f1cb03aa42ff
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Fri Sep 30 11:13:06 2011 -0700

    CBMEM CONSOLE: Add CBMEM type for console buffer.
    
    Add CBMEM type for the console buffer section.
    
    Change-Id: I02757c06d71e46af77b02b90b0e6018a37b62406
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/720
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 32da8bed197c5c7efc226dd9cfc3b75bad496f05
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Thu Sep 29 17:27:15 2011 -0700

    CBMEM CONSOLE: Add CBMEM console driver implementation.
    
    The CBMEM console driver saves console output in a CBMEM area, which
    then is made available to Linux applications for perusing.
    
    There are some system limitations which need to be worked around
    to achieve this goal:
    
    - some console traffic is generated before DRAM is initialized,
      leave alone CBMEM initialized.
    
    - after the RAM based stage starts, a lot of traffic is generated
      before CBMEM is initialized.
    
    As a result, the console log lives in three different places -
    the bottom of the cache as RAM space, the CBMEM buffer (where it
    is expected to be) and a static buffer used early in the RAM
    stage.
    
    When execution starts (in the cache as RAM mode), the console
    buffer is allocated at the bottom of the cache as RAM memory
    address range. Once DRAM is initialized, the CBMEM structure is
    initialized, and then the console buffer contents are copied from
    the bottom of the cache as RAM space into the CBMEM area right
    before the cache as RAM mode is disabled. The
    src/lib/cbmem_console.c:cbmemc_reinit() takes care of the
    copying.
    
    At this point the cache as RAM memory is about to be disabled,
    but the ROM stage is still going generating console output. To
    make sure this output is not lost, cbmemc_reinit() saves the new
    buffer address at a fixed location (0x600 was chosen for this),
    and the actual "printing" function checks to see if the RAM is
    already initialized (the stack is in RAM), and if so, gets the
    console buffer pointer from this location instead of using the
    cache as RAM address.
    
    When the RAM stage starts, a static buffer is used to store the
    console output, as the CBMEM buffer location is not known. Then,
    when CBMEM is reinitialized, cbmemc_reinit() again takes care of
    the copying.
    
    In case the allocated buffers are not large enough, the excessive
    data is dropped, and the copying routine adds some text to the
    output buffer to indicate that there has been data lost and how
    many characters were dropped.
    
    Change-Id: I8c126e31db6cb2141f7f4f97c5047f39a8db44fc
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/719
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c34b4631282e03aba5b2c4b247ecc9a783924d0f
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Wed Sep 28 13:51:30 2011 -0700

    CBMEM CONSOLE: Add config option for CBMEM stored console log.
    
    Some experiments have demonstrated that total amount of text
    generated by coreboot console when BIOS_SPEW level is enabled
    exceeds 40KB.
    
    Console output generated before DRAM is initialized can exceed
    2KB. This patch introduces the new configuration option and
    assigns adequate default values to cache based and DRAM based
    console buffers.
    
    BUG=chrome-os-partner:4200
    TEST=manual
    
     . run the following commands in the root directory
    
       cp config.stumpy .config
       make menuconfig
    
     . enable the new option (Console->Send console output to a CBMEM buffer)
     . save the configuration
    
    Observe the following settings added to the config:
    +CONFIG_CONSOLE_CBMEM=y
    +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00
    +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
    
    Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: https://gerrit-int.chromium.org/5855
    Tested-by: Vadim Bendebury <vbendeb@google.com>
    Reviewed-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/718
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit f2f9386b640bddb813c941deccfc9e9c168927d8
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Oct 4 10:44:16 2011 -0700

    Increase CBMEM to accommodate larger console.
    
    This change adds 128K to the memory amount set aside for CBMEM in
    case the CBMEM console is enabled (to keep the CBMEM 128K byte
    aligned). The console buffer size is being set to 64K, which is
    enough to accommodate the most verbose coreboot console and
    u-boot console.
    
    Change-Id: If583013dfb210de5028d69577675095c6fe2f3ab
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/725
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 654f2934653ee5ca4bd43217abbc49a9140c8ad0
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Sep 26 13:24:40 2011 -0700

    Add cmos helper functions for reading/writing a dword
    
    These get used later for saving/restoring the MRC scrambler
    seed values on each boot.
    
    Change-Id: I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/717
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9ec8ed8a40c5c5aff8053693dd2ecd403034605b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Oct 18 15:11:04 2011 -0700

    selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB
    
    This fixes loading SeaBIOS when lower memory is reserved.
    
    Change-Id: Idbdcaf95f3307f97307f304d6d677406d059927d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/732
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e246b31121df3c15022d108390c389f352c40d81
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Sep 23 10:24:49 2011 -0700

    Include arch/acpi.h instead of manually adding acpi_slp_type.
    
    acpi_slp_type is defined in arch/acpi.h, so let's use that instead
    of manually spreading extern u8 acpi_slp_type throughout the code.
    
    Change-Id: Ia5eb420364c15ab5a764bc328bbd201ca9cb7837
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/714
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6f72d6965c7c54df663f2337e6154daf4dd464ff
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Wed Sep 21 16:12:39 2011 -0700

    Add timestamp collecting to coreboot.
    
    This patch adds code to initialize the time stamp collection
    facility in coreboot. It adds a table in the CBMEM section, which
    provides the base timer reading value (all other readings are
    offsets of this one) and an array of timestamp id/timestamp value
    pairs.
    
    Just two values are being added now, this will have to be used
    more extensively and also integrated into payloads to provide more
    comprehensive boot process time measurements.
    
    Also, since the CBMEM area could already contain a section (from the
    previous run, before reset), when processing a section addition
    request we should check if a section already exists and return its
    address, if so.
    
    Change-Id: I7ed9f5c400bc5432f228348b41fd19a67c36d533
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/713
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 9202473d076c02270dfa3e3a9b275d20455c143d
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Wed Sep 21 14:46:43 2011 -0700

    Add a config flag to enable time stamp collection
    
    Add a new flag, make it dependent on EARLY_CBMEM_INIT
    
    Change-Id: Idbebcaf298238f31a73e9eb4a9af7b03e857bc74
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/712
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit e1860604e46780d08ee2dab568cf80bf2d349c16
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Sep 20 17:07:14 2011 -0700

    Initialize CBMEM early.
    
    We want to be able to share data between different phases of firmware
    (rom stage/ram stage/payload). Coreboot CBMEM seems an appropriate
    location for this data, but normally it is not initialized
    until coreboot reaches the ram stage.
    
    This change initializes the CBMEM while still in rom stage in
    case CONFIG_EARLY_CBMEM_INIT is set.
    
    Note that there is a discrepancy in how coreboot determines the
    size of DRAM at rom and ram stages, get_top_of_ram() is used at
    rom stage and is not defined for all platforms. Those platforms
    will have to define this function should they enable the
    CONFIG_EARLY_CBMEM_INIT flag.
    
    Change-Id: I81691d45e28de59496fb227f2cca4e8c15ece717
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/711
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit e6b6aff28ab26d5b2e6fbd76138561765dc58a76
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Sep 20 16:46:46 2011 -0700

    Introduce config option to initialize CBMEM early.
    
    We want to be able to communicate information between rom and ram
    stages of coreboot. This configuration option will be used to
    compile such ability in.
    
    Change-Id: I6736fdc264ecd0b63369b28462d7bb96e4c2b012
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/710
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c9da0157c7b35bb7964b915b9d172249585fa21b
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Mar 25 19:55:43 2012 +0200

    Add bifferboard
    
    This commit adds support for Bifferboard, a 32MB 486 PC
    
    Change-Id: Iad790ebf242ef07bf6298f8e3577783e5e743113
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/810
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ae012486e84c8ae5a738cd1d75f7ba780528c6cb
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Mar 25 19:19:03 2012 +0200

    Add 64KB romchip chip size
    
    This is handy for bifferboard to provide same size as original bootloader.
    
    Change-Id: I179917d8c6354fa55cebdd70918a96cd299c4f3c
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/809
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6b89b4c75f86f9cbb32cccf728c9a623a205963d
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Mar 25 18:16:11 2012 +0200

    Add support for RDC R8610 Southbridge
    
    So far it just setups things right for Bifferboard. We may change it
    in the future to fit other hardware.
    
    Change-Id: I1c4ccff4e47b9cb9e31a738f038fc4f4ebe59087
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/808
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c0c5ac7c906c0123f29938900084233957ce3be0
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Mar 25 18:14:02 2012 +0200

    Add the support for RDC R8610 Northbridge
    
    So far the it just setups the internal resource management for coreboot and
    detects the memory size.
    
    Change-Id: I8506390fa6656abfa40d92b8f6ede9b91fe98680
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/807
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1c89e90d5c5be51c8f2fd5ca0869af2891d81dfb
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Mar 25 15:58:09 2012 +0200

    Add RDC R8610 PCI IDs.
    
    Change-Id: I3f3585f15265aa1377f72ba23accf1adb08cb8ac
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/806
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1dd0dda442c0bdf3e423b8bed69603901645149c
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Mon Mar 19 17:32:33 2012 -0600

    Fix cleaning SeaBIOS from coreboot makefile
    
    The coreboot makefile didn't pass the OUT and CC variables to seabios,
    so the clean didn't clean anything.
    
    Change-Id: Ieaf0c417d6e5dfb9e0a11df70b03d6313919578b
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/801
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin@se-eng.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 6588802fa73d4b45c91e701807ad12d8fcef303e
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Mar 25 20:51:16 2012 +0200

    Disable the GDB stub by default
    
    I would prefer to see the exception dump on serial rather than cryptic
    GDB protocol.
    
    Change-Id: Ib25513d33e6a31da24586fecb00adb5206bb43bd
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/811
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit a01ae624af5a9afa0e8799aa0f8823d6b8137457
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Mar 4 02:24:36 2012 +0200

    Fix possible deadlock on SMP stop_this_cpu
    
    Do not use printk on the running thread after it has been sent
    the INIT IPI, execution may halt with console spinlock held.
    
    Change-Id: I64608935ea740fb827fa0307442f3fb102de7a08
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/776
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 8b28d50cdd1384893ec0565453eea77031aa7ec8
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Mar 9 17:02:37 2012 +0200

    Intel cpus: Fix deadlock on hyper-threading init
    
    Only the BSP CPU was able to start its hyper-threading CPU siblings.
    When an AP CPU attempts this it calls start_cpu() within start_cpu(),
    deadlocking the system with start_cpu_lock.
    
    At the time intel_sibling_init() is run, the BSP CPU is still
    walking the cpu_bus linked list in lapic_cpu_init: start_other_cpus().
    A sibling CPU appended at the end of this list will get started.
    
    Also fail compile with #error if SERIAL_CPU_INIT==0, as microcode
    updates on hyper-threading sibling CPUs must be serialized.
    
    Tested with HT-enabled P4 Xeons on dual-socket604 platform.
    
    Change-Id: I0053f58f49ed604605ce0a55e826d3e1afdc90b6
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/775
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 2172f61ede0ff7764eae39d4b75085c2dee9b610
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Mar 19 19:12:49 2012 +0200

    Makefile: rename linker intermediate variable
    
    Renamed CONFIG_ROMBASE to ROMSTAGE_BASE and removed it from Kconfig.
    Removed no-op calculation in ldscript.
    
    Change-Id: I53d39b60f07db76c8537b3133e59360687b9d4a7
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/802
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit c0ea5436c4d78d15a42d81fc65ed0219e5464f2b
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Mar 7 09:30:03 2012 +0100

    gitconfig: Improve commit-msg hook
    
    There was some corner case where commit-msg failed. Update to
    latest upstream version.
    
    Change-Id: I822d6c3f64728de7356401465e00575ac5af8196
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/798
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bernhard Urban <lewurm@gmail.com>
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit e77b9a0ab79d930e76c8713bd6fb05c2e7dfbd9e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Mar 17 08:09:14 2012 +0100

    Replace ramtest pattern to assist in DIMM configuration
    
    This is developer's testtool. Output from a "rotate ones" -style
    pattern helps figure out how DIMM addresses are encoded or routed
    on a certain mainboard.
    
    Scattered test should cover every data and address lines on the memory
    bus, but is probably limited to the first bank of first DIMM.
    
    Change-Id: I533a7a873bcc434f99e7faed9dc9337d9ab64196
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    [pg: rebase]
    Reviewed-on: http://review.coreboot.org/294
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 8a85bccd8404c705891ae9f3851952ff8bfa1f76
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Nov 22 10:52:43 2011 +0100

    i82801gx: Support power-on-after-power-fail better
    
    Changing CMOS value for power-on-after-power-fail was only honored
    after reboot, which is counter intuitive (set from "enable" to "disable",
    power-off, replug device -> device turns on; and similar cases).
    
    Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/444
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c07466b287b0aaba0fc73decc60bb75fe919fea1
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Nov 22 10:28:46 2011 +0100

    i82801gx: Use CMOS variable if available for power-on on power failure
    
    We used a hard coded value for some reason. Don't do that, but use CMOS
    instead.
    
    Change-Id: Ib83aa07a3e55bed075150354a060317ebc9d5ba7
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/443
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 51615091320a18e39ef2c509ec24e7f80ba71f01
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Mar 11 19:31:03 2012 +0100

    printf: Remove some L modifier uses
    
    We use the L modifier in a non-standard way (for
    long long instead of long double, which we have no
    business with).
    clang complains, to reduce its use, to make
    emulation/qemu-x86 happier.
    Long term, we should consider eliminating public uses
    of 'L' (but internal use in vtxprintf to denote
    long long is fine)
    
    Change-Id: If9a17d9ae9925cdc8736445e7d5eedc59c7028c6
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/781
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ccee6256b48ad619d16c4479a25937fa95b93efc
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Mar 20 16:53:44 2012 -0600

    Fix libpayload alloc() size and gcc pointer optimization problems.
    
    The previous commit was incomplete and missed setting the entire
    alloc area.
    
    There are also additional problems with gcc optimizations of the
    pointer math. The "auto" casting by gcc wouldn't return warnings,
    but it was causing the optimization to be incorrect. We are now
    very explicit in the casting in the pointer math.
    
    Change-Id: I020808c8d1dda544fe862b9efb0e5345eeab5aab
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/804
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 06253cd9a5742078386f355a06c0f13bebbcc5ce
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Feb 25 23:51:12 2012 +0100

    Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 class cpu.
    
    Change-Id: Ic7c4452a1b55bae0cefee118003540ec39ef9fd4
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/683
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 06c04299c1420fa94a1a53cc36c9d91a5e31a22a
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jan 7 19:15:43 2012 +0100

    Another indirection for normal/fallback bootblock
    
    Provide a way to redefine the names of normal and fallback via CBFS.
    This way updates can use some more expressive naming scheme (numbers,
    dates, version numbers) and replace the coreboot-stages file to
    point to the new version (with the current version as new "old").
    
    If coreboot-stages doesn't exist, the default behaviour remains to
    use "normal" and "fallback".
    
    Change-Id: I77c134d79ed95831ad5098b7663c15e95d3b5a2a
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/589
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 7a39446ec236b9eeba7454790fc32fc4240d7e42
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Feb 13 13:38:27 2012 +0200

    Intel cpus: Include CAR from socket
    
    It was not obvious which CAR was compiled in. Also build would fail
    if a socket included two models with both having an include for CAR.
    
    Change-Id: I000c2e24807c3d99347a43d120333c13fbf91af4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/626
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit dd3b227fb9158c2fc84a916cac8de1d2ec103982
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Mar 16 10:31:37 2012 -0700

    Fix AMD Fam15 CBMEM allocation
    
    The Fam15 northbridge.c had hardcoded the CBMEM size. It should use
    the one in cbmem.h instead.
    
    Change-Id: I8a00e05884bdb1d1a4a012433b0adfbb9eb22983
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/796
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 30b46cefb54a8d98393cf4cf08b062f04e2f2ceb
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Mar 16 10:26:39 2012 -0700

    Fix AMD Fam12 CBMEM allocation
    
    The Fam12 northbridge.c had hardcoded the CBMEM size. It should use
    the one in cbmem.h instead.
    
    Change-Id: I1eca18e21fa59ae32e802d8452e42e8b7a3575cf
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/795
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit cc6c615d29e926c74a7994e1bf70e56c0e9b7b6a
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Mar 16 10:19:51 2012 -0700

    Fix AMD Fam10 CBMEM allocation
    
    The Fam10 northbridge.c had hardcoded the CBMEM size. It should use
    the one in cbmem.h instead.
    
    Change-Id: Id6c4128d8f5f6a417f83daa3a39b2bfc8e810f8a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/794
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3ae1c651275a210dab0112825a44abc8c806aa16
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Mar 16 15:54:18 2012 +0200

    AMD Agesa: delete no-op bootblock files
    
    Removes files:
      src/northbridge/amd/agesa/family10/bootblock.c
      src/northbridge/amd/agesa/family12/bootblock.c
      src/northbridge/amd/agesa/family14/bootblock.c
      src/northbridge/amd/agesa/family15/bootblock.c
    
    Change-Id: Ic3617a673b38d065ca272c4de8ef765ecd3f98b1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/793
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d11ca1d08d90fdbe828f4c224e31dfc7d633bcdf
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Mar 16 15:40:56 2012 +0200

    Rename AMD_AGESA to CPU_AMD_AGESA
    
    Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove
    the explicit selects from the mainboards.
    
    Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/792
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f5bb4771dee06c132aa7d15917c69cd34b2a7ec9
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Mar 16 15:15:20 2012 +0200

    Fix AMD Agesa leaking Kconfig
    
    Kconfig leaked XIP_ROM_SIZE to other platforms and also
    defined obsolete option XIP_ROM_BASE.
    
    Alias AMD_AGESA as NORTHBRIDGE_AMD_AGESA.
    Break the circular dependency with family15 Kconfig.
    
    Change-Id: Ic7891012220e1bef758a5a39002b66971d5206e3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/773
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1c93d90fd2c87e778e4d9a57ccfa341fd00d3d80
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Mar 16 21:16:55 2012 +0100

    ROMCC boards have no XIP limit
    
    So set their XIP configuration to ROM_SIZE.
    
    Change-Id: I6c1abccec3b1d7389c85df55343ff0fc68a61eec
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/797
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

commit b58651ba5e25bbe66abe2d93fc46dea8357e854e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Mar 11 19:29:46 2012 +0100

    Use search path when building dependencies
    
    clang is more picky on that.
    
    Change-Id: Iaa8472beb6e275c39037d11e1a72dbb80d46424b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/779
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1a34165e37e8ab7ced6a639441f5df2478246976
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Mar 11 19:42:33 2012 +0100

    xchg is atomic with side-effects
    
    clang doesn't know about the side effect, so we have to tell it
    that it's okay not to care about the result.
    
    Change-Id: Ib11890bff6779e36cf09c178d224695ea16a8ae8
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/783
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fe9210f5d0ba6662ac47d3a9b962665d4d484fee
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Mar 11 20:44:22 2012 +0100

    clang: Don't use mmx nor sse
    
    clang is much more trigger happy than gcc on those.
    
    Change-Id: Ie7c219de3cc26675692eab7361a4ad551f1c65a7
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/786
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit eb5e28ffc61f6698de1e312415804cc8dc675dfe
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Feb 24 16:08:18 2012 +0200

    Intel northbridge I945: Apply un-written naming rules
    
    Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build.
    
    Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time
    which model of I945 the driver is built for.
    
    Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/684
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d4d5e4d3e10da06a83d57a147bd58a733381de18
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Mar 16 19:28:15 2012 +0100

    Via Epia-N and C3: Set ioapic delivery type in Kconfig
    
    The original comment says it's a Via C3 and not Epia requirement
    to deliver IOAPIC interrupts on APIC serial bus.
    
    Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/435
    Tested-by: build bot (Jenkins)

commit 35e1c861f59696e2ff545e89709e5e72ccc79fca
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Feb 25 17:14:20 2012 +0200

    VIA southbridge K8T890: Apply un-written naming rules
    
    Use separate Kconfig option to select a driver directory for
    build and the specific type of southbridge to support.
    
    Change-Id: I9482d4ea0f0234b9b7ff38144e45022ab95cf3f3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/685
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7863015c3eabe94c360ff893723f48af23a47a33
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Mar 5 09:25:12 2012 +0200

    Fix address of IDT in real-mode entry
    
    In a case of CS & 0x0fff != 0x0, lidt memory operand does not point
    to nullidt, this can raise an exception and shutdown the CPU.
    
    When an AP CPU receives 8-bit Start-Up IPI vector yzH, it starts
    execute at physical address 000yz000H. Seems this translates to
    either yz00:0000 or y000:z000 (CS:IP), depending of the CPU model.
    With the change entry16.inc is relocatable as the commentary suggests
    and can be used as ap_sipi_vector on SMP systems.
    
    Change-Id: I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/707
    Tested-by: build bot (Jenkins)
    Reviewed-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5750ed253a6ed45e574a8855a7b7b1abe16eae88
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Thu Mar 15 13:21:41 2012 -0600

    Fix AMD Fam14 cbmen allocation
    
    The Fam14 northbridge.c had hardcoded the cbmem size. It should use
    in cbmem.h instead.
    
    Change-Id: I910329fc98a4cf04dc81ef66f3aa05a1916f5b1d
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/790
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 8d595698bfb1c6dd0d56ccd6bdb38ea112a60095
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Thu Mar 15 12:55:26 2012 -0600

    Clean up whitespace in fam14 northbridge.c
    
    Change-Id: Id7947d7f3c67fdda67861065b1bc7a519b97208f
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/789
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 02bb57824c025d6955d1b6337c0baefcaaa60994
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Sep 16 02:24:03 2011 -0700

    Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available
    
    Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available by
    including byteorder.h
    
    Change-Id: I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/709
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 0f995bc4e84868e436f6e0efe3b639658bc7b539
Author: Martin Roth <martin@se-eng.com>
Date:   Fri Feb 17 13:16:04 2012 -0700

    AGESA family 12 changes to fix torpedo warnings
    
    Fixes the warnings generated in the torpedo mainboard build by AGESA.
    Removing broken tests.
    
    Change-Id: Ib444fa2bf4dd94cadb4ce33040eb5650d1c0325b
    Signed-off-by: Martin L Roth <martin@se-eng.com>
    Reviewed-on: http://review.coreboot.org/667
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5efe10a637a65a61eb1823bcb33ffacb7ea22d55
Author: Frank Vibrans <frank.vibrans@se-eng.com>
Date:   Tue Mar 13 11:02:04 2012 -0600

    Union Station: Fixes to turn on HDMI
    
    This commit includes the changes to enable the HDMI on Union
    Station.  The changes switch the output from the display port
    to the HDMI.
    
    Change-Id: I4e15ff6db7d056f156791ff1406d4bae35ff2767
    Signed-off-by: Frank Vibrans <frank.vibrans@se-eng.com>
    Reviewed-on: http://review.coreboot.org/788
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 2fc955ebc0e39f063935a51574663c9198b16bcc
Author: Frank Vibrans <frank.vibrans@se-eng.com>
Date:   Tue Mar 13 10:57:49 2012 -0600

    Union Station: Remove SIO support
    
    Because the Union Station platform doesn't have an SIO chip,
    this commit removes the Fintek SIO support.
    
    Change-Id: Idba4222ce136821dee2530a72d1630eb5ad613a2
    Signed-off-by: Frank Vibrans <frank.vibrans@se-eng.com>
    Reviewed-on: http://review.coreboot.org/787
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 30cc4800d3e73d7af80faf2acc4d83e8fbeba908
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Mar 11 19:34:12 2012 +0100

    No need to setup include paths with .s files
    
    They're already preprocessed, and clang whines.
    
    Change-Id: I57fe936f84a2fe1aa50ee8510fef606f2ed2ea23
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/782
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit fb5026c40607eb9aa8927c8eeace75d1e32797fc
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Mar 11 19:30:36 2012 +0100

    malloc: size is unsigned, don't test for size < 0
    
    clang complains
    
    Change-Id: Ifadf73cf377c0d1808e20731803e01101bad7e1d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/780
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit 0c245370a16776d156ed58563172e1bc397adc32
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Mar 9 23:03:01 2012 +0100

    mainboard/aopen/Kconfig: remove extra whitespace
    
    Change-Id: I69ee67c35113d98e034bdccf5d00e8452d3d9bd2
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/778
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit c040e476bfe12fb67087b13de86346370c0e1c3e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Mar 9 23:02:09 2012 +0100

    Portability improvement
    
    Makefile.inc uses $( ) syntax on the shell. That's isn't as universal
    as one would like.
    
    Change-Id: I9a8fd511eef7fefc1458d5bae2cd7ef5475b7392
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/777
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bernhard Urban <lewurm@gmail.com>

commit 987e883e6a5a48eb7404c81e1eb5fdcfb1107ef7
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Thu Mar 1 16:12:11 2012 -0700

    Make libpayload alloc() memory pointers volatile
    
    gcc4.6.2 was optimizing the libpayload alloc() function and failing to
    reload a pointer after the memory had been manipulated by a pointer in
    the inlined function setup(). Change the pointer type to volatile
    and now pass it to the setup() function. Also clean up the
    declaration so that it isn't cast a bunch times in the function.
    
    Change-Id: I1637bd7bd5d9cf82ac88925cbfe76d319aa3cd82
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/705
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 32829caf40e12974a11cb470c4da1e9a04971f76
Author: Gabe Black <gabeblack@google.com>
Date:   Wed Oct 5 01:57:03 2011 -0700

    If the memory mapped UART isn't present, leave it out of the cb tables.
    
    This way u-boot won't try to use a UART that isn't plugged in.
    
    Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/729
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit d7a75ece8581d958bbf95ebbecc074e1cf27d791
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Oct 25 17:12:53 2011 +0000

    tell superiotool about the ITE 8772
    
    no dumping yet
    
    Change-Id: I4e687ca816c8d6d1c95255b0abf6a19513e23f86
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/734
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 294edb24b5a79b90db669d372e17741dc30354c0
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Sun Aug 14 13:52:03 2011 -0700

    Increase size of the coreboot table area
    
    Packing a device tree into the coreboot table can easily make
    the table exceed the current limit of 8KB. However, right now
    there is no error handling in place to catch that case.
    
    Increase the maximum memory usable for all tables from 64KB to
    128KB and increase the maximum coreboot table size from 8KB
    to 32KB.
    
    Change-Id: I2025bf070d0adb276c1cd610aa8402b50bdf2525
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/704
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 66ecdc52e1ed09b116fd47a59e0aa8905bffef09
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Aug 15 16:35:10 2011 -0700

    Fix compilation when USE_OPTION_TABLE is not defined.
    
    Change-Id: Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/702
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 05239898f2e7b1d35a2f4882c8c3f2c1a783f592
Author: Vadim Bendebury <vbendeb@chromium.org>
Date:   Tue Aug 16 11:44:35 2011 -0700

    Fix coreboot table size calculations.
    
    The code when reporting the coreboot table size did not account
    for the last added table record. This change fixes the problem.
    
     . rebuild coreboot, program it on the target, restart it
     . look for 'Wrote coreboot table at:' in the console log
     . observe the adequate table size reported
    
     $  grep 'Wrote coreboot table:' /tmp/cb.log
     Wrote coreboot table at: 00000500, 0x10 bytes, checksum c06f
     Wrote coreboot table at: 7f6fc000, 0x1a73 bytes, checksum 3e45
     $
    
    Change-Id: Ic55501a4ae06fab2bcda9aea58e362325f2edccf
    Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
    Reviewed-on: http://review.coreboot.org/703
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit c75bfde967a3d535a8ae94d58ed9cb4d0a827442
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Aug 15 11:26:35 2011 -0700

    Clean up use of CONFIG_ variables in coreboot_table.c
    
    CONFIG_ variables are used inconsistently within the file
    src/arch/x86/boot/coreboot_table.c. #ifdef will do the wrong
    thing if the option is disabled. #if (CONFIG_FOO == 1) is
    not needed.
    
    Change-Id: Ifcac6ceac5fb34b931281beae500023597b3533b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/701
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 526087172dcdceebafcfffb08d47ed1c3447f9a4
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Aug 11 14:51:31 2011 -0700

    Fix dependency problem for uart8250.c as well
    
    If you build in parallel, option_table.h will occasionally not be there yet
    and the build will fail.
    
    Change-Id: I828956ab2e05c48d20c2f7c55616cc8fa19e1227
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/698
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ba9dae27e11102f3bf4477cef70eed3929960104
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Jul 29 15:34:14 2011 -0700

    Fix compilation with CONFIG_USE_OPTION_TABLE enabled
    
    Change-Id: I6c5d973442bc1770702180a8964f1bf6ed6062ed
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/696
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 6f88a6ec7dce8eb12f52afcc0f7fcbaececa06e7
Author: Duncan Laurie <dlaurie@chromium.org>
Date:   Mon Jul 18 10:41:36 2011 -0700

    Add helper function to find a Local APIC by ID in the device tree.
    
    Change-Id: Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7
    Signed-off-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/695
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5807555f9a0afb94ad92535dd2933ee4dbd25088
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed May 11 15:57:07 2011 -0700

    Don't try to compute I/O for empty sub buses.
    
    I am not sure if the sub bus being 0 is a problem, or if the assumption
    there has to be at least one non empty link is just wrong. It certainly
    does not hurt to add a small consistency check in either case.
    
    Change-Id: I098446deef96a8baae26a7ca1ddd96e626a06dc5
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/693
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit dfab0f69ae9af22a96f68364fb1c0d95798a21c9
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 10 12:54:56 2011 -0700

    OXPCIe: Reinitialize UART after pci_dev_set_resources()
    
    ... and only pull in early init code if the OXPCIe is used for console.
    
    Change-Id: I01feca3b9e8376a75c17554ba1bd200d523dff8d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/692
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8907e816265d9821e39bb21333f6212b97e80504
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue May 10 10:46:41 2011 -0700

    move console includes to central console/console.h
    
    Because it's included everywhere anyways.
    
    Change-Id: I99a9e6edac08df57c50ef3a706fdbd395cad0abc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/691
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit a6087d155de715d1268c115c42ab7b0ed244e94b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon May 9 15:19:29 2011 -0700

    Add support for the Startech PEX1XS1PMINI
    
    It has a smaller footprint than the already supported MPEX2S952
    
    Change-Id: Ie36b67f9628882d516ca34ff164f0e8918955a5b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Tested-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-by: Duncan Laurie <dlaurie@google.com>
    Reviewed-on: http://review.coreboot.org/690
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit afaa25776ff2f42293e6ef48fdaddfa8104bbe50
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Oct 6 16:47:51 2011 -0700

    Don't run any Option ROMs stored outside of the system flash
    
    Right now coreboot only executes VGA Option ROMs. However, this is not
    good enough. For security reasons we want to execute only Option ROMs
    stored in our r/o CBFS.
    
    This patch adds a new option to disable execution of arbitrary Option
    ROMs.
    
    Also fix the capitalization of Option ROM in src/devices/Kconfig
    
    Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/730
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit 1025f3afc85be633451c4312ab26d179d47132e5
Author: Gabe Black <gabeblack@google.com>
Date:   Fri Sep 16 02:18:56 2011 -0700

    Add an implementation for the memchr library function
    
    Change-Id: Icded479d246f7cce8a3d2154c69f75178fa513e1
    Signed-off-by: Gabe Black <gabeblack@google.com>
    Reviewed-on: http://review.coreboot.org/708
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Mathias Krause <minipli@googlemail.com>

commit 8ebd11eab999654873010e706b95e5fe5855ea64
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Mar 8 11:06:25 2012 -0800

    Fix lint-stable checkin hooks on MacOS X
    
    - wc adds a number of leading spaces which broke cut
    - sed can't replace spaces with new lines, so use tr for that.
    - make sure directories are created if they're not there.
    
    Change-Id: Ia0db059683abe3d97b0ab6feaece660a1f4e5079
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/774
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)

commit 0a50084e4d7535c5eb86dc3bf18c357eec4aa69a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Sep 23 10:33:58 2011 -0700

    Don't run VGA option ROMs on S3 resume.
    
    This will save us a few 100 ms on resume.
    
    Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/715
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c8feeddf343e8fd0ddd6be7e42101ab4f1866ed0
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 18:43:25 2012 +0100

    Unify Local APIC address definitions
    
    We used several names for that same value, and hardcoded the value
    at some more places.
    
    They're all LOCAL_APIC_ADDR now (except for lapic specific code
    that still uses LAPIC_DEFAULT_BASE).
    
    Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/676
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 91162705a65e87c56d9fc58edfe597140d1b4d53
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Nov 3 15:22:01 2011 +0200

    Add support for A-Open DXPL Plus-U motherboard
    
    This is an old (pre-2005) entry-level server mainboard. The code
    is adapted from mainboard/intel/xe7501devkit.
    
    Featured chips:
     - Dual socket604
     - E7505 northbridge
     - 82801DB southbridge (with EHCI debug port)
     - 82870p2 PCI-X bridge
     - LPC47M102S-MC super-io
     - 512kB FWH flash (flashrom does the job well)
    
    What works:
     - Dual-Xeon P4/HT boot with microcode update
     - RAM: registered ECC DDR266 in dual-channel
     - PCI-X slot interrupts with ACPI and I/O apic
     - On-board PCI-X GbE and SCSI
     - ACPI power-off and wakeup with PME#
    
    Notes :
     - Current ACPI is more or less a mess
     - Interrupts do not route correctly with PIRQ
     - MP-table is not implemented
     - Issues with reboots remain (cold and warm)
     - Many superio devices are disabled by default
     - Audio codec is not investigated
    
    Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/303
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c5fc7db3559e080858461b724251f87be6faa2cd
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Mar 7 15:55:47 2012 +0100

    Move C labels to start-of-line
    
    Also mark the corresponding lint test stable.
    
    Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/772
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 533ec00689d5affb283ea1a07c978972441deeba
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Mar 7 15:49:07 2012 +0100

    lint: test that labels begin at start-of-line
    
    Some attempt at enforcing style
    
    Change-Id: Ibbfb86402ecc57e8db6c3857c8e0193085ed4fc2
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/771
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 51f6a206801aa6c05c2f8a6db12262a6c695e202
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jan 11 12:40:14 2012 -0800

    correctly mark code segments as code in SELF
    
    In bios_log, find that the first segment of the payload is shown
    as code rather than data.
    
    Sample:
           Got a payload
           Loading segment from rom address 0xfff29378
             code (compression=1)
           ...
    
    Change-Id: I82eaad23f08c02f4ed75744affa8835255cf5c17
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/767
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c44de4999fbd15b6ea87dc723af49e8035a82476
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jan 11 14:07:39 2012 -0800

    selfboot: drop dead code
    
    As a left over from elfboot times, selfboot keeps the segments to
    load in the order in which they appeared in the original file as
    well as in the order they will later appear in memory. This is not
    needed in selfboot, so drop the code and structure members that handle
    the in-file order.
    
    Change-Id: I6be7a3a1bdf717fec1ee8e5b3227c63150580b41
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/768
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5ec21580f63180551bae762249c24a1888b625bb
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Mar 3 10:46:26 2012 +0100

    Revert "Use -mno-sse to prevent overzealous gcc optimizations"
    
    AGESA uses SSE intrinsics :-(
    
    This reverts commit 05f4b03fb64999ba373fe61256f358e5371bf8ae
    
    Change-Id: I7c48e07a261eafda2119354d282bd05eac5a14b6
    Reviewed-on: http://review.coreboot.org/706
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit ccf28ba9cb562e74ce17439d88dcc5a10aefeef6
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Thu Jun 23 17:12:08 2011 -0700

    Use -mno-sse to prevent overzealous gcc optimizations
    
    The offending part that made coreboot crash with some toolchains
    was that gcc emits SSE instructions but coreboot did not enable SSE at
    that point.
    
    Since the gain for coreboot using SSE instructions is not measurable,
    let's not use SSE instructions rather than enabling SSE early on.
    One rationale behind this is that other parts of coreboot, like the
    SMM handler would need fixing because the XMM registers are not saved
    on SMM entry. Thus keep it simple.
    
    Change-Id: I14f0942f300085767ece44cec570fb15c761e88d
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/694
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 067d22340c68d21f0dd5a33cf02701bc54005a0d
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Feb 21 17:06:40 2012 -0700

    Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
    
    The logic was backwards on the ECC enable/disable option. Also added better
    debug output when the debug RAM init feature is enabled.
    
    Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/670
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 07408e687ce440bf665cd6d04d65075b20db0215
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Feb 25 19:52:45 2012 +0100

    gitconfig: Add lint-stable as pre-commit hook
    
    When configuring the tree with "make gitconfig", a pre-commit hook
    is installed that runs the stable lint tests.
    If any of these fail, the log is visible (on stdout) and the
    commit is aborted.
    
    Change-Id: Ie2a26e87f466c63b24db8dca8827057a18ac7f3e
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/682
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cb02cb70d8f881f02cb41a4ba722c00c84c07bf6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Feb 25 19:42:59 2012 +0100

    lint: create two classes of tests, stable and dev
    
    We have tests that pass (and should be enforced soonish) and those
    that don't pass yet (and thus shouldn't break the build).
    
    The plan is simple: As soon as a test passes, it's marked stable so
    things remain that way.
    
    "make lint" runs all tests,
    "make lint-stable" runs only those that shouldn't fail.
    
    Change-Id: Iaa85d71141606d9756e29b37c7a34c2a15e573ac
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/681
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9c7467ea63cb73b08b96f2d1eaf2abf37a982842
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Feb 25 15:33:43 2012 +0100

    Fix lint test for build directories
    
    config files are rename()d, which fails across filesystem borders.
    So force temporary config files in current directory.
    
    Change-Id: I583c2ab9a822a6f99f838778aa17ffd2d47eaed1
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/680
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7be482b002804fe4b85b08acbfda4e8f10ddd637
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Jan 10 19:25:23 2012 +0100

    Drop support for BROKEN marker
    
    We used to support marking boards broken. We don't need that anymore.
    
    Change-Id: I9d21fdf22c9a8e0e69488fc7896f2a81bf629201
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/675
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c88ed855d81bc45d2862424b373398af3742631b
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Jan 10 18:45:34 2012 +0100

    Rename vendor identifiers in Kconfig
    
    Board identifiers use them without underscore, too. Unify that.
    
    Change-Id: I146384ef6dbe601ad131dada8224f43e6c18433d
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/674
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 730c0eec43a4be5d2b8d7b2450bd0fdebd4253a4
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Feb 29 21:17:18 2012 +0200

    Fix x86 cpu_phys_address_size
    
    After CPUID, requested feature flag is in edx, not eax.
    
    Change-Id: I9ce27c22186f17cc64986be342d7d1ac78a79898
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/688
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit b99bc43ee0893651ec81e6e3aabecae9d361be98
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Feb 28 17:18:58 2012 -0700

    tint requires more heap space for PDCurses.
    
    tint was failing with the message "initscr(): Unable to create curscr."
    tint uses the initscr() to enable vga windows, which allocates more
    heap space with PDCurses than with tinycurses. Expanding the heap from
    16KB to 64KB resolves the issue.
    
    Change-Id: I1d38651e2b77f55613969c29614fb3b2be38a00c
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/687
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 399fcdd40d24e7f6fed80e5e1493c900be2b3772
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Feb 23 18:42:55 2012 +0200

    AMD southbridge: remove sp5100
    
    Southbridge SP5100 support was compiled with SB700 code, but static
    device info structure would use sp5100/chip.h. To solve this drop
    support for separate chip sp5100 and adjust the relevant Kconfig
    options.
    
    Removes chip directory:
      src/southbridge/amd/sp5100/
    
    Rename Kconfig option
     from: SOUTHBRIDGE_AMD_SP5100
       to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100
    
    Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/679
    Tested-by: build bot (Jenkins)
    Reviewed-by: Zheng Bao <zheng.bao@amd.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 72bf6a1a48cb37497c112673dd17cd9c2c5971b1
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Tue Feb 21 22:29:30 2012 +0100

    asus/m4a785t-m: correct the CPU microcode patch selection
    
    Thanks to ruik on #coreboot Freenode IRC channel for
      explaining to me how to get the cpu revision:
        Feb 21 22:07:32 <ruik>  ruik@ruik:~/coreboot$ cpuid | grep ^00000001
        Feb 21 22:07:32 <ruik>  00000001 00020f32 00020800 00000001 178bfbff
        [..]
        Feb 21 22:07:44 <ruik>  the 20f32 is mine CPUID
    The rest was just looking at the correspondance in
      src/cpu/amd/model_10xxx/update_microcode.c
      like Marc Jones explained(thanks Marc Jones) in the mailing list here:
      http://www.coreboot.org/pipermail/coreboot/2012-February/068332.html
    
    Change-Id: Ie0f004990e6b65456de009a4dcc306498bdb47e9
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/669
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit 4c796ea7c6f4971f2ff19ec707b3452da05c456e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Feb 23 13:54:23 2012 +0200

    Ati video: Apply un-written naming rules
    
    Rename Kconfig to match directory name.
    
    Change-Id: Idebc203bbc9a02599dfc3e65be021aa9e1b23d61
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/678
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 80bd74c21e5dcca3e9aa8543e086405142900664
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Feb 21 17:44:35 2012 +0100

    Revert "Fix multipleVGA cards resource conflict on Windows"
    
    This reverts commit 8660a1aa56caeb31bfaf15464285ca650638515e
    
    This commit has been found to cause problems with vbios and option rom init
    in seabios. It has been found by several people and requires more analysis
    before being recommitted.
    
    Change-Id: Ie5f54e417e7a0d8bd8ca4c0a573976afeaa9e230
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/671
    Tested-by: build bot (Jenkins)
    Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 91bd3068a7c28d429bb7a2581ccee40645c137c9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:16:14 2012 +0100

    ACPI: More ../../.. removal
    
    CPP is ran with src/ as part of its search path, so
    using <northbridge/...> and the like is safe.
    
    Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/649
    Tested-by: build bot (Jenkins)

commit b05bf5bca978a12a5c278bf1fbc90e7f5cff69ae
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:45:56 2012 +0100

    amd/sb600: Move HAVE_HARD_RESET to southbridge
    
    No in-tree board using that chipset has it not selected, so move
    selection from boards to southbridge.
    
    Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/660
    Tested-by: build bot (Jenkins)

commit fff8cdfcdeedb3723bd9dba66e19ae1a56ba9c8f
Author: Marc Jones <marc.jones@se-eng.com>
Date:   Tue Feb 21 17:53:13 2012 -0700

    Remove old AMD fam10 fixme comment
    
    The family10 code had a very slow decompress before the cache settings were
    fixed. This has been fixed for some time. Remove all the old messages from the
    serial stream.
    
    Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    Reviewed-on: http://review.coreboot.org/672
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0864016b0d5d9d7e54f120873282967759886d95
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Fri Feb 17 12:23:26 2012 +0100

    libpayload: fix compile error with enabled USB_DEBUG
    
    Commit c4348d0 ("libpayload: Remove bitfield use from OHCI data
    structures") missed to adapt a debug message. This patch fixes this.
    
    Change-Id: I5f6a4be9c7f6f99cb103926772717e15a3cbca70
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/653
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bernhard Urban <lewurm@gmail.com>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit c877d22a201b6e774b9187400e1ebbf697fa8bdd
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Feb 2 14:50:02 2012 -0700

    Force SB600 bootblock to use I/O for PCI config
    
    If PCI config cycles use MMIO instead of I/O in the SB600 bootblock
    code the cycles will go nowhere since the MMIO feature hasn't been
    configured yet. This change forces the cycles to use I/O and
    configures the southbridge decode range to what is defined by the
    mainboards Kconfig.
    
    Change-Id: I85297237f32f37b3fc1ff5b488cca0a43bcf20fd
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/632
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5257c27cf7f682de332b838e522415ccd1f3559b
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Wed Feb 1 16:15:08 2012 -0700

    Force SB700 bootblock code to use I/O for PCI config cycles.
    
    If PCI config cycles use MMIO instead of I/O in the SB700
    bootblock code the cycles will go nowhere since the MMIO feature
    hasn't been configured yet. This change forces the cycles to use
    I/O and configures the southbridge decode range to what is specified
    by the mainboards Kconfig.
    
    Change-Id: I15a89a27645edf594d14ef20f129f75a315e9672
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/631
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2eacc0eec23fbe3a68eb17e32b2603d4c3353a36
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Feb 2 14:56:23 2012 -0700

    Force SB800 bootblock to use I/O for PCI config
    
    If PCI config cycles use MMIO instead of I/O in the bootblock
    code the cycles will go nowhere since the MMIO feature hasn't been
    configured yet. This change forces the cycles to use I/O.
    
    Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/630
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d8d8c63cf71efbc8fae21e3db8aea87b530111f9
Author: Marc Jones <marcj303@gmail.com>
Date:   Mon Jan 30 19:30:45 2012 -0700

    Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.
    
    The MTRR check for WB TOM2 setting was only checking revF, not extended family
    revisions. All families above revf indicate 0xf in the family field and have
    additional bits in the extended family field.
    
    Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/627
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit dc0bdbab2df7ff8c89b0e1325a60ce994ee6bf43
Author: Martin Roth <Martin@se-eng.com>
Date:   Tue Feb 14 10:50:11 2012 -0700

    Torpedo mainboard changes to fix warnings.
    
    Fixes the warnings generated in the torpedo mainboard build.  Most of these
    changes are similar to fixes already implemented in the persimmon mainboard.
    
    Change-Id: Ib931be51c0e6448c00c8cfeb13073e1f392582a5
    Signed-off-by: Martin L Roth <martin@se-eng.com>
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/634
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit da52aed20d2ee835c6c68f779b2ec1949895af87
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Feb 2 15:08:22 2012 -0700

    Fixes Fam10/SR5650 cpu not recognized message.
    
    Extend the Family10 revisions checked byt the printk message.
    
    Change-Id: Ia94daeefb1aabfb128c577b1e0aa52cf63d5cf44
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/633
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e42d639718cacbca75397bf5a560584ee32ede69
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Feb 2 13:38:50 2012 -0700

    IEI-Kino Fam10 MPtable fix.
    
    Make changes to MPtable to match the ACPI tables.
    
    Change-Id: Icc18c9a25695d01d88d6ee5367064d527cc42bc1
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/629
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3aea95803d2940bf1463e87b2999cf80229f7bf3
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Feb 2 14:07:43 2012 -0700

    IEI Kino Fam10 ACPI table fixes.
    
    Fix the ACPI IRQ routing. Also, fix the SSDT generations and TOM2 fixup.
    
    Change-Id: Ica4a992d11bab63a510238dcd468b9fe80136def
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/628
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a22f78b828ec056aa6104033d0afb9bb4f9688e0
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:44:28 2012 +0100

    nvidia/mcp55: Move HAVE_HARD_RESET to southbridge
    
    No in-tree board using that chipset has it not selected, so move
    selection from boards to southbridge.
    
    Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/659
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 0e992be2b7c44d73a633f5f868ef4865c0721d02
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:52:16 2012 +0100

    amd/sb700: Move HAVE_HARD_RESET to southbridge
    
    No in-tree board using that chipset has it not selected, so move
    selection from boards to southbridge.
    
    Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/661
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit c46f450801124e0df94ec72ac0713180dd888512
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:53:21 2012 +0100

    intel/i82801cx: Move HAVE_HARD_RESET to southbridge
    
    No in-tree board using that chipset has it not selected, so move
    selection from boards to southbridge.
    
    Change-Id: Ifba0b65d81af60774f368d151e935ae1cc768336
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/662
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit e0ddbc7b806d7b0b977db0e28970e8e47f7cff96
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:56:50 2012 +0100

    sis/sis966: Move HAVE_HARD_RESET to southbridge
    
    No in-tree board using that chipset has it not selected, so move
    selection from boards to southbridge.
    
    Change-Id: I9762ef01fc10c453ef643599c1c5dc8ee78081c3
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/663
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 7389378b4ff24f5750e3bb6dda047d5d8050cb56
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:58:00 2012 +0100

    intel/i82801ex: Move HAVE_HARD_RESET to southbridge
    
    No in-tree board using that chipset has it not selected, so move
    selection from boards to southbridge.
    
    Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/664
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 62246f7121d010db7e1fd0cf0fa73de5132cafe9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:58:51 2012 +0100

    intel/sch: Move HAVE_HARD_RESET to southbridge
    
    No in-tree board using that chipset has it not selected, so move
    selection from boards to southbridge.
    
    Change-Id: I521deecf58e5d5de303f1ef2f5ff7e965294de18
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/665
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 024d8d9c221040c1c91b2f503818bc696f279fbd
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 20:03:28 2012 +0100

    amd/sb800: Move HAVE_HARD_RESET to southbridge
    
    No in-tree board using that chipset has it not selected, so move
    selection from boards to southbridge. (cimx/sb800 is a "different"
    chipset)
    
    Change-Id: If7cf2a141a1f2df60f687c51fbd760aa405c8480
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/666
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit c726e03624a7b13595daf90f0d2784f2d4c958a2
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:42:48 2012 +0100

    broadcom/bcm5785: Move HAVE_HARD_RESET to southbridge
    
    No in-tree board using that chipset has it not selected, so move
    selection from boards to southbridge.
    
    Change-Id: Id95660f088c8240606d45abf326cd5eefca30da3
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/658
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit d6a6eefebe970302964435516aa7f6866142df52
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Fri Feb 17 12:02:47 2012 +0100

    libpayload: enforce const correctness for CMOS getter/setter
    
    Input only arguments to {get,set}_option*() should be const to catch
    programming errors early.
    
    Change-Id: I560001a8e9226dfd156a4e529fcad20549236ebd
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/652
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 334328a51f8ec04e6fb4a774198c8f9db7c5ef2d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:01:22 2012 +0100

    Avoid ../../.. paths in ASL files
    
    The current directory is always part of the search path of cpp when
    using #include "..."
    
    Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/648
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit fdcd135b9604332499303736e6fcbb9d025c893f
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 18:58:46 2012 +0100

    Rename i945 ACPI files to not carry an i945_ prefix
    
    In the spirit of the earlier renames.
    
    Change-Id: I458a42c79a164483120169d1822ffa6861cc3aff
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/647
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 632ab1ff6501e87b2b51da88f9dd9ca7b1b90e49
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Fri Feb 17 11:53:28 2012 +0100

    libpayload: fix compiler warning for first_cmos_entry()
    
    The 'name' argument to lookup_cmos_entry() is declared to be 'char *'
    but we pass an empty string ("") which is 'const char[]' so the compiler
    legitimatly warns about discarded qualifiers here. Fix this by passing
    NULL as 'name'.
    
    Minor nitpick: The NULL test in lookup_cmos_entry() is superfluous as our
    implementation of strnlen() can handle NULL pointers gracefully. But for
    an average C hacker it just doesn't feel right not to do so.
    
    Change-Id: I592917d12d8fa840804c0d19e38b844427064fef
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/651
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f01291dd64175b0c03a218f5ee4ad306ad779183
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:39:39 2012 +0100

    nvidia/ck804: Move HAVE_HARD_RESET to southbridge
    
    No in-tree ck804-using board has it not selected, so move
    selection from boards to southbridge.
    
    Change-Id: I3064b406cfd5ad18067c597bd5b5866a720f7e87
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/657
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 472efa604158c193bdcd8f357ca52c41eca53ca5
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 20:44:20 2012 +0100

    Remove whitespace.
    
    Fix issues reported by new lint test.
    
    Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/646
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d13e4167a903c1bd69c9ed708987f016dff13d1d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 20:28:42 2012 +0100

    lint: Add test for whitespace issues in the code
    
    So far it tests for trailing whitespace.
    "Upstream" files (bison/flex's .?_shipped, kconfig, vendorcode) are ignored.
    
    Change-Id: I7af1954d537fd05f06cd210ac130dac87892159b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/645
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 152738f2eb39070100b5a3fcfe7f5828c0a154e3
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:24:03 2012 +0100

    amd/amd8111: Move HAVE_HARD_RESET to southbridge
    
    No in-tree amd8111-using board has it not selected, so move
    selection from boards to southbridge.
    
    Change-Id: Iabbaa4cd2fd367ed6decec7ef5cdcbae3b264d52
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/654
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit 4eee42f1d0d97bffd1152838bc0c57150c440cbe
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:37:58 2012 +0100

    via/cx700: Move HAVE_HARD_RESET to northbridge
    
    No in-tree cx700-using board has it not selected, so move
    selection from boards to northbridge.
    
    Change-Id: Ifa79954a48cf99b5f7e49960eafce805401e571c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/656
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a842aecabcd1e6bdef1e3baac253209f77587dd9
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Feb 16 19:28:51 2012 +0100

    intel/82801dx: Move HAVE_HARD_RESET to southbridge
    
    No in-tree 82801dx-using board has it not selected, so move
    selection from boards to southbridge.
    
    Change-Id: I69671cb6411a6cd9c791059ae9546dff3aff702c
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/655
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 93dd07f3d5ee1726b79e26644ff245fe8b5aaef7
Author: zbao <fishbaozi@gmail.com>
Date:   Fri Feb 17 21:44:09 2012 +0800

    Exit building if romstage.bin is larger than size of XIP
    
    When the romstage.bin becomes bigger than the size of XIP, the
    cbfstool can not allocate the romstage in the CBFS. But it doesn't
    report an error. It will take quite a while to find out the root
    cause.
    
    Change-Id: I5be2a46a8b57934f14c5a0d4596f3bec4251e0aa
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: zbao <fishbaozi@gmail.com>
    Reviewed-on: http://review.coreboot.org/650
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 6d6d18efe859875c5fc35cabb5e977fe6841c771
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Feb 7 20:32:34 2012 +0800

    Mainboard: Add AMD dinar mainboard.
    
    Dinar mainboard is an AMD evaluation board for
    Orochi Platform family15 model 00-0f processor.
    
    The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets.
    16 cores InterLagos Opteron processor are supported.
    Windows 7 are verified on this platform.
    
    Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/564
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3c71a8579b8624c3581dcb7bde075b961a44d76a
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Feb 7 20:31:40 2012 +0800

    SIO: Add smsc sio1036 superio
    
    Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/563
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit c94940cd64911914a771d3fc09da45b884360574
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Feb 7 20:31:40 2012 +0800

    SIO: Add smsc/sch4037 superio support
    
    Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/562
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit ea52223f53278cc0e57f7d266b8656014e2ecab1
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Tue Feb 14 22:38:01 2012 +0100

    M4A785-M,M4A785T-M: fix SSDT tables
    
    This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9
        (AMD Mahogany Fam10 ACPI table fixes.)
    
    Change-Id: I9a9bf955de0a2a7accdbce8561b23596a8641af4
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/636
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 250f655127beaf135717ddb32f0dfcafaeb59b36
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Tue Feb 14 22:11:23 2012 +0100

    M4A785T-M: fix TOM2.
    
    This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9
    (AMD Mahogany Fam10 ACPI table fixes.)
    
    With commit permit to boot without pci=nocrs on the M4A785T-M board.
    
    Before the fix dmesg contained the following:
      [    0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
      (20110112/psargs-359)
      [    0.480085] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
      (20110112/psargs-359)
      [    0.788222] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
      (20110112/psargs-359)
    
    Now it only contains:
      [    0.312102] TOM: 0000000080000000 aka 2048M
    
    Change-Id: I5d517604abe938af19b70d57d92c1f973114c1cd
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/635
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 131c936b45a4f0d3a1aaaf0165faffc8a7cd72c6
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Feb 7 20:31:40 2012 +0800

    SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper
    
    Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/561
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 6811f75457148cc0d3b0cb4832fda712e7797af2
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Feb 7 20:31:40 2012 +0800

    AGESA F15: AGESA family15 model 00-0fh northbridge wrapper
    
    Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/556
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 134d8a94de060a6d09d663167379d895c0af86fc
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Feb 7 20:33:21 2012 +0800

    HWM: Nuvoton W83795G/ADG HWM support
    
    Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans,
    they are controled by a separate W83795G Hardware Monitor chip.
    This patch adds Nuvoton W83795G/ADG HWM support.
    
    Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/569
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit a3f060748b692e50b7e3856ef37a731d3c76451c
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Feb 7 20:32:38 2012 +0800

    Mainboard: Supermicro/h8qgi mainboard update
    
    1. Supermicro H8QGI mainboard update to support both family10 Revison D
       processor and family15 model 00-0fh processor in one binary image.
    2. RD890/SR56X0 IO hub CIMX wrapper support.
    3. SP5100/SB700 southbridge CIMX wrapper support.
    
    Both 8 cores and 16 Cores InterLagos Opteron Processor are
    tested on this platform.
    Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested.
    
    Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/567
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit c55f5a0e07eaa7238b47f12f8c134eab319e8714
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Feb 7 20:32:37 2012 +0800

    SIO: Winbond w83627dhg update
    
    1. Stop include c file.
    2. W83627dhg Pin 89, Pin 90 are multi function pins,
       add support to select them to I2C function.
    
    Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/565
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 6b909f21af1c012a0de6bc817311c8b93683ee39
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Feb 7 20:31:40 2012 +0800

    RD890: AMD RD890/SR56X0 CIMX wrapper
    
    Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0,
    RD890 and 990FX chipsets.
    
    Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/559
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit e41745e5d6106e8d95d36848ee9522bfaa756831
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Feb 7 20:31:40 2012 +0800

    pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids
    
    Change-Id: I13905f5730d08510c8f0f6e652f41a679d618d1b
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/609
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit d3e990c6e5124f30b394f5dbd4902ea8bf341b07
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Feb 7 20:31:35 2012 +0800

    AGESA F15: AGESA family15 model 00-0fh cpu wrapper
    
    Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/555
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 53c1d204ed134017e9a04d68f175bb7f6c6e0915
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Feb 15 15:55:57 2012 +0200

    Intel cpus: use CPU_PHYSMASK_HI define in CAR
    
    Unifies models 6ex, 6fx and 106cx.
    
    Change-Id: I2bb632c7148a7d937f24eb559f7f4e539d227470
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/638
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit adf105fe45d70f4ac255e96b0308c65e2587d785
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Feb 15 15:55:03 2012 +0200

    Intel model_106cx: Use symbolic names for MTRR bits
    
    Change-Id: I6ea5ca631c22fe870224a498b68d77d85798b3f4
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/637
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7916f4cef62bf032af86368a9df45db833d09b79
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Feb 9 16:07:41 2012 +0200

    AMD Geode cpus: apply un-written naming rules
    
    Kconfig directives to select chip drivers for compile literally
    match the chip directory names capitalized and underscored.
    
    Rename directories and Kconfig as follows:
       model_lx  -> geode_lx
       model_gx1 -> geode_gx1
       model_gx2 -> geode_gx2
    
    Change-Id: Ib8bf1e758b88f9efed1cf8b11c76b796388e7147
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/613
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 50759ed4ff438db6f3b093984fbb79d6445ebcb3
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Wed Feb 8 10:32:57 2012 +0100

    libpayload: code cosmetics
    
    Be consistend with coding style at least within a function -- don't mix
    sizeof with plain values.
    
    Change-Id: Iefb5b7fe4f54977f5505fc9cea65c9c4af3e7f3a
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/617
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e13632a939e7dde8d7d44fc73e73a41dae8060c3
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Feb 10 13:32:13 2012 +0200

    Intel cpus: apply un-written naming rules
    
    Kconfig directives to select chip drivers for compile literally
    match the chip directory names capitalized and underscored.
    
    Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x.
    
    Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/618
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9a4114a15a4a63d059923c54ab08d392ca856c03
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Wed Feb 8 10:31:42 2012 +0100

    libpayload: fix possible mem leak in get_option_as_string()
    
    Change-Id: I7c3adbd1b72be81585bbaabb42532fc4cad57f58
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/616
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit bdc8c83614f18ff87e978a0b1d60a27a61ec7c0d
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Feb 10 14:36:27 2012 +0100

    Remove non-existent include
    
    Change-Id: I702d59371b4a57ce22623cbab6e936b653d57edf
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/619
    Tested-by: build bot (Jenkins)

commit 332a7e91c71697b9eb07a7974c1c248bf97e30cd
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Feb 9 21:05:20 2012 +0100

    i5000: halt second BSP
    
    If both FSBs on i5000 are equipped with CPU packages, one CPU
    from each package is elected as BSP. To prevent races between
    both BSPs, hlt the second BSP.
    
    Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/615
    Tested-by: build bot (Jenkins)

commit 6d64adeaa680ea9fde3140e1d3a47d9b9270d3f8
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Dec 2 16:21:35 2011 +0100

    Add Intel Socket LGA771
    
    Change-Id: Iee7d3ff2884d8c43ff1af498160589e551bc9cc8
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/492
    Tested-by: build bot (Jenkins)

commit 12b72624ee876e5855d501a527413d5f96edf65b
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Feb 9 16:51:38 2012 +0200

    VIA cpus: apply un-written naming rules
    
    Rename files and directories:
      model_c3 -> c3
      model_c7 -> c7
    
    Change-Id: If144fc501e8ae44b347ac44fa90c689c33a8e126
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/614
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c466287d4d4062478e3c3c5fc6502cfb5567f249
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 7 23:50:17 2012 +0200

    Remove no-op Makefiles under mainboard directory
    
    Patch removes following files:
    
        src/mainboard/amd/serengeti_cheetah/Makefile.inc
        src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc
        src/mainboard/broadcom/blast/Makefile.inc
        src/mainboard/hp/dl145_g1/Makefile.inc
        src/mainboard/msi/ms9282/Makefile.inc
        src/mainboard/supermicro/h8dme/Makefile.inc
        src/mainboard/tyan/s2881/Makefile.inc
        src/mainboard/tyan/s2892/Makefile.inc
        src/mainboard/via/epia-m700/Makefile.inc
    
    Change-Id: I020776313abff1772be38afc896af51ca5ab6453
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/612
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f31abe31f0dd47a9b99a4cabecd5f414a07418d4
Author: Bernhard Urban <lewurm@gmail.com>
Date:   Wed Feb 1 16:30:30 2012 +0100

    romcc: kill gcc warnings and .gitignore generated files
    
    don't remove calls to `flatten()' and `correct_coalesce_conflicts()',
    since they (probably) have side effects.
    
    Change-Id: I78fc4163b3f5f1f5f3c5153f9559c22e11e8344d
    Signed-off-by: Bernhard Urban <lewurm@gmail.com>
    Reviewed-on: http://review.coreboot.org/605
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9dd3ef165a1bf1bc404056d3e54337de1a15ac90
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 7 20:50:22 2012 +0200

    Don't loop infinitely long on serial comm failures
    
    If serial uart (8250/16x50) takes abnormally long to respond, give
    up on logging to serial console and instead let the system boot.
    
    Also reference bit in LSR register with correct name.
    
    Change-Id: I3796efc3e8690425f04a130af4bc99541b64d335
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/611
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 7f782a8f0b0691df506c1f0a8cb2d435582bbe68
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Feb 7 14:59:07 2012 +0200

    Delete hard-coded driver includes
    
    Driver components are conditionally included in the build using the
    Kconfig options.
    
    Change-Id: I05417ee263a5b82e947600482dfb68f7a3f52d58
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/610
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7627f7f22d06accc9a22b3859cd1813d6f3c99c5
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jan 31 14:48:05 2012 +0100

    libpayload: Remove workaround for bitfield management in EHCI driver
    
    We don't use bitfields anymore.
    
    Change-Id: I25ceec2024f659612871bcfe5f98df3a10789055
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/595
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 2fd524297e5f8cfa1c44c2e96067bc6680f03882
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jan 31 14:42:47 2012 +0100

    libpayload: Force checking all EHCI ports on power-on
    
    EHCI port status reporting isn't very consistent on power-on,
    so just looking for devices on all ports is the safest way to
    find everything.
    
    Change-Id: I26b4305016f0bed1d2c1b5cffc59d5813fa1cbbb
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/594
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 8660a1aa56caeb31bfaf15464285ca650638515e
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Wed Jan 4 20:51:47 2012 +0800

    Fix multipleVGA cards resource conflict on Windows
    
    If multiple VGA-compatible legacy graphic cards decode the IO range
    3B0-3BB, 3C0-3DF and MEM range A00000-BFFFF.
    Windows 7 complain a resource conflict, so only one VGA card can
    works at the same time.
    
    There is a discussion in coreboot mail list before,
    please reference thread: "how to prevent legacy resource conflictwith   multipleVGA cards"
    http://www.coreboot.org/pipermail/coreboot/2010-October/061508.html
    
    Linux using VGA Arbiter module(vgaarb) to resolve this resource conflict,
    Please see the following linux dmesg log, more information can be found in
    Linux source dir Documentation/vgaarbiter.txt.
    But it seems that windows don't dealwith this conflict.
    ~# dmesg | grep -i vgaarb
    [    0.774076] vgaarb: device added: PCI:0000:00:01.0,decodes=io+mem,owns=io+mem
    [    0.776065] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=none,l
    [    0.780051] vgaarb: loaded
    [    0.784049] vgaarb: bridge control possible 0000:01:00.0
    [    0.788050] vgaarb: bridge control possible 0000:00:01.0
    
    For the second legacy graphic device, coreboot already disabled the
    IO and MEM decode in function set_vga_bridge_bits().
    But it will be enabled again in function pci_set_resource(),
    if the second legacy vga-compatible graphic device take any IO/MEM resources.
    
    Following log printed by enable_resources() shows the problem:
    ...snip...
    PCI: 00:00.0 cmd <- 06
    PCI: 00:01.0 subsystem <- 1022/1410
    PCI: 00:01.0 cmd <- 07                <== The first graphic device
    PCI: 00:01.1 subsystem <- 1022/1410
    PCI: 00:01.1 cmd <- 02
    PCI: 00:02.0 bridge ctrl <- 0003
    PCI: 00:02.0 cmd <- 07
    ...snip...
    PCI: 01:00.0 cmd <- 03                <== The second graphic device
    PCI: 01:00.1 cmd <- 02
    PCI: 02:00.0 cmd <- 02
    PCI: 03:00.0 cmd <- 03
    done.
    ...snip...
    
    
    The IO & MEM decoding on the second vga graphic device should be disabled.
    Please reference PCI spec. section 3.10 in detail.
    set_vga_bridge_bits() would do this work for us, it did the right thing,
    but was put to the wrong place, the setting would be overwritten by
    assign_resources() later.
    
    In order to make sure the set_vga_bridge_bits() setting not be
    overwritten by others, moving the call of set_vga_bridge_bits()
    to the end of dev_configure(), instead of at the beginning.
    
    This patch resolved the dual graphic cards resource conflict in windows7,
    multiple vga-compatible graphic cards can work together in windows7.
    
    
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Change-Id: I0de5e3761b51e2723d9c1dc0c39fff692e3a779d
    Reviewed-on: http://review.coreboot.org/489
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit f03360f3f87f9c03a9550c5f4cf3917fdbe56619
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Thu Jan 19 13:25:55 2012 +0800

    Inagua: Indent and wihtespace cleanup
    
    Change-Id: Ie574e08f138c88084c8ce06d0d0acc489013e3d7
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Reviewed-on: http://review.coreboot.org/547
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 19329c90d3fb9334df7ba7d7c41848b098cdeccc
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Thu Jan 19 13:18:36 2012 +0800

    Inagua: mainboard specific GPIO setting
    
    Pcie device connected to Hudson/sb800 southbridge GPP training can works,
    by applying this mainbaind specific GPIO PCIE De-Assert setting.
    
    Change-Id: I563b2e6354a958a28f5d0162e7a4d60aa437fb9b
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Reviewed-on: http://review.coreboot.org/543
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit d0790694b0a66353e5531715648ddaa1a6d577cb
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Thu Jan 19 13:18:37 2012 +0800

    Inagua: Inagua GNB ddi lanes and pcie lanes config update
    
    DDI lanes configuration update to make LVDS works.
    Pcie lanes configuration update to make MiniPcie slot 1 works.
    
    Change-Id: I40aaf28119b946b3a6383ceff7c734c9c3fd313e
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Reviewed-on: http://review.coreboot.org/544
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 9e83175d2902b49f156d5f92361473a8eee4a243
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Thu Jan 19 13:18:37 2012 +0800

    Inagua: devicetree.cb update
    
    Add the slots connection comments to devicetree.cb
    
    Change-Id: I3ccb2641c8d04a6a3c66ac11a562ba3b0dc0578a
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Reviewed-on: http://review.coreboot.org/545
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit aff6dc21499295fedae35e52bc906a22831df323
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sat Jan 21 10:34:22 2012 -0800

    Move SeaBIOS output out of coreboot source tree
    
    Make sure SeaBIOS build files live under $(OUT) instead of
    in the source tree.
    
    Change-Id: I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/552
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3e0bd190262ce9ffe9653583e5ca9af0f63850f1
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jan 31 14:37:59 2012 +0100

    libpayload: Fix EHCI driver
    
    When converting EHCI to not use bitfields, two offsets were converted
    incorrectly.
    
    Change-Id: I0bb4bad0eee42e54ad4fd53d6c35b107e227c41a
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/593
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit c0a6c6b3b946f13f331ad2c2a3ab941cde628098
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Jan 23 14:17:52 2012 -0800

    Add OPROM mapping support to coreboot
    
    This allows to add a PCI ID mapping function for option roms so that the same
    option rom can be used for a series of devices / PCI IDs. Intel and AMD often
    use the same option rom for a number of PCI devices with differend IDs.
    
    A function to implement such a mapping could look like this (or anything else
    appropriate):
    
    /* some vga option roms are used for several chipsets but they only have one
     * PCI ID in their header. If we encounter such an option rom, we need to do
     * the mapping ourselfes
     */
    
    u32 map_oprom_vendev(u32 vendev)
    {
        u32 new_vendev=vendev;
    
        switch(vendev) {
        case 0xa0118086:
            new_vendev=0xa0018086;
            break;
        }
    
        return new_vendev;
    }
    
    Change-Id: I1be7fe113b895075d43ea48fe706b039cef136d2
    Reviewed-on: http://review.coreboot.org/573
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 01f7ab93359ae0fee5784d35effbcbe0b596df18
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Thu Jan 19 13:18:36 2012 +0800

    Inagua: Synchronize AMD/inagua mainboard.
    
    AMD/persimmon mainboard code is derived from AMD/inagua mainbard.
    Persimmom update a lot in the last few month, sync these modification to inagua.
    
    Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Reviewed-on: http://review.coreboot.org/542
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 91be49b2d0635b3d666125790c59b057f956b2c0
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Wed Feb 1 13:59:00 2012 +0800

    SIO: condition compile Nuvoton WPCM450 early_init.c
    
    Compile Nuvoton WPCM450 early_init.c when CONFIG_SUPERIO_NUVOTON_WPCM450
    
    Change-Id: Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/566
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0a5951110812ad83abc6a61db992050a39209b8d
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Jan 16 15:39:57 2012 +0100

    libpayload: Add iterators for CMOS variables
    
    Provide functions that pick the first CMOS variable defined
    in the cmos layout, and from there, the next one.
    
    Change-Id: Ie98146de7f6273089fc6fc0b232a4b94337cf8a3
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/587
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 56f468d29b4beab59f5a751d8d30364962298328
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Jan 16 15:03:11 2012 +0100

    libpayload: Expose options_checksum_valid
    
    options_checksum_valid can be used as a fast test to
    identify invalid CMOS data by checking the checksum.
    
    Change-Id: I44635d4c5d389579ad82435907ba8658e1bd44bb
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/586
    Reviewed-by: Bernhard Urban <lewurm@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit da59f9a8fb83e9d3931ed1d9b49eb8915a318771
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Jan 16 13:47:33 2012 +0100

    libpayload: Provide interpretation of CMOS data structures
    
    Add new functions that allow using string based key/value access to
    CMOS, including support for enums.
    
    Change-Id: Ibe238eff4c5230e5f61004c88221cd34393873aa
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/585
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5febb00640f838dc31035c1e6a999067c28367d9
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Feb 2 15:51:29 2012 +0100

    libpayload: Add access to CMOS images in memory space
    
    Provide access to CMOS images in RAM or CBFS, such as cmos.defaults
    
    Change-Id: Ifa70dea6206d94c0c271caf9ae1152fc76b5d51a
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/584
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b06bd8d9542513d87c62e494d3ca8012264b2878
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Feb 1 11:47:29 2012 +0100

    i3100: configure pci irqs
    
    without it, you can't boot from PCI devices like scsi controllers
    which require an interrupt set. So preconfigure all pci devices.
    
    Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/603
    Tested-by: build bot (Jenkins)

commit 317ca0d75190cdda385cca327991b72f14e9667f
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Jan 16 10:14:24 2012 +0100

    libpayload: Refactor highlevel CMOS access
    
    This will allow using libpayload functions to access CMOS data in
    template files in RAM or CBFS.
    
    Change-Id: I323ed625e657cbdc1fae8c279a82ee578e83ad00
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/583
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 56f2a6d6e534b47cd5fab4b092e0ba887be2a5b4
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Wed Feb 1 14:07:38 2012 +0800

    CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir
    
    AGESA and CIMX build changed from commit 2a830d0b,
    sb800 and sb900 CIMX dir already traversed in vendorcode Makefile.
    
    Change-Id: I5101b22e140725337bf5074b9170e582c8e3bf40
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/602
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3439bba6695577e0bb51d08393e470c4a561adbc
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Wed Feb 1 13:55:13 2012 +0800

    SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code
    
    Support AMD SB700 and SP5100 chipsets.
    
    Change-Id: I0955abf7f48a79483f624b46a61b22711315f888
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/560
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9292d89be84d6abf9257ddb872887d4f53b2a00e
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Jan 31 20:39:37 2012 +0800

    RD890 Northbridge: AMD RD890/SR56X0 Northbridge CIMX code
    
    Change-Id: If9908ffeb5b707a660db38dc44f5118347cbcc06
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/557
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 17670866a0d12839bc2a4c852210ccf11d3cb4b2
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Feb 1 22:06:45 2012 +0100

    Add Intel i5000 Memory Controller Hub
    
    Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/491
    Tested-by: build bot (Jenkins)

commit f61ad93bc99e3a0557346faa1b60d0c227933d36
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jan 31 22:44:53 2012 +0100

    i3100: add sata_ports_implemented option
    
    BIOS needs to set the bit mask which ports are iplemented on the
    board. Without setting this option, seabios fails to boot from
    SATA.
    
    Change-Id: I21de3fde3a9cff7c590226f70fa549274f36e2a8
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/601
    Tested-by: build bot (Jenkins)

commit ab46c15f61844b62ded575d5710fe2da0cae32d8
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jan 31 22:40:50 2012 +0100

    i3100: Add init sequence
    
    i3100 misses the magic SATA init sequence, which makes all
    requests fail. Captured from the vendor BIOS, which writes
    those bits on all configurations.
    
    Change-Id: I293b7d9cd681181311ecaced6d7df9b2706c711f
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/600
    Tested-by: build bot (Jenkins)

commit 7363ca35f06f3a3ac398812812b75118aab8c6bf
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jan 31 22:10:28 2012 +0100

    X86: fix cpu_phys_address_size()
    
    CPUs with CPUID level >= 0x80000008 can return
    the number of physical address bits.
    
    Change-Id: I1c0523b6a091c476af838d173ed9030280360d7f
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/599
    Tested-by: build bot (Jenkins)

commit bba0346ef5406b085d15226ec43db4bbeee0ef92
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jan 31 17:41:12 2012 +0100

    X60/T60: Add option to enable/disable bluetooth
    
    Change-Id: I9761a8a9a7cc708fe95169cb8b79b413b97ee523
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/598
    Tested-by: build bot (Jenkins)

commit 483ec41e6f3947b8e11ed67f7efcfdc3ef035612
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jan 10 14:44:12 2012 +0100

    X60: fix docking
    
    Fix ordering of power/reset/undock procedure to prevent
    crashes seen with the old code. Also call dlpc_init()
    only once.
    
    Change-Id: I27d1f42e845fcccde40e6ca5af4a7762edab5d36
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/597
    Tested-by: build bot (Jenkins)

commit fc4e7333e02b24ab7b4f5ae0e39d3115f41f6ab6
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Jan 27 22:56:25 2012 +0100

    mainboard/lenovo/t60, x60: Disable CHECK_SLFRCS_ON_RESUME
    
    This makes resume from S3 work.
    
    Change-Id: I472baf2fbde46bfac223ce39fc81b8e09849fb7f
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/591
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 751508ab019e0612f715ea481c550d73aa240112
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Jan 27 22:17:09 2012 +0100

    northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option
    
    Originally brought up by Sven Schnelle in March 2011
    http://patchwork.coreboot.org/patch/2801/
    http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html
    
    On some mainboards it may be neccessary to reset early during resume
    from S3 if the SLFRCS register indicates that a memory channel is not
    guaranteed to be in self-refresh.
    
    On other mainboards, such as Lenovo X60 and T60, the check always
    creates false positives, effectively making it impossible to resume.
    
    The SLFRCS register is documented on page 197 of
    
    Mobile Intel® 945 Express Chipset Family Datasheet
    Document Number: 309219-006
    
    which is publically available, and the register indicates if a memory
    channel is guaranteed to be in self-refresh mode (if bit = 1), or that
    a memory channel *may or may not be* in self-refresh mode (if bit = 0).
    
    The register can thus only be used to positively learn that memory is
    in self-refresh. It is not known for sure that memory is *not* in
    self-refresh. The register is reset by the PWROK signal, which *should*
    go low during S3, and go high again when resuming, so it is unsurprising
    that SLFRCS has already been cleared when we read the register.
    
    Sven's measurements of the CKE signal on a ThinkPad shows that memory
    remains in self-refresh indefinitely, until coreboot re-initializes the
    memory controller, even when SLFRCS bits were = 0.
    
    Boards which require a warm reset when SLFRCS bits are cleared must now
    explicitly enable the check in the mainboard Kconfig file.
    
    This commit selects the new option in all existing i945 mainboards.
    A follow-up commit will remove the option for ThinkPads.
    
    Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/590
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 247c7276938f2ac92944112e218e0d541dff04e9
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jan 31 12:33:01 2012 +0100

    X60/T60: fix default baudrate
    
    Value required to get 115200 is actually 0, not 5.
    
    Change-Id: Id1385822bf2213c035c4f378a72168ed6676ad03
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/592
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit c8ac6a5aa3b1012233f515ea328bacaae114c5d9
Author: Philip Prindeville <philipp@redfish-solutions.com>
Date:   Wed Jan 18 00:31:50 2012 -0700

    pcengines: align VENDOR_ and BOARD_ names for PC engines
    
    Coming changes to abuild require that VENDOR_ and BOARD_ names have
    common suffixes.
    
    Change-Id: I44cf759dd3b2d02c525eb325dc9c5c989f172ac5
    Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
    Reviewed-on: http://review.coreboot.org/548
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit cc16cca2be1939a731157b1b62029d99be268dc8
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Wed Jan 25 20:40:40 2012 +0530

    vga: removed inclusion of .c files
    
    Add local vga.h for prototypes.
    
    Change-Id: I5ff627c6420d4b7fd1bc9a537f406ef6d9597522
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/588
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 976f8cc1e29daee35a2f92f97be59a4838949c43
Author: Nils Jacobs <njacobs8@adsltotaal.nl>
Date:   Wed Jan 25 22:26:35 2012 +0100

    Make Geode GX2 VGA setup work.
    
    Add MSR register write for VGA memory setup
    Add missing license
    Add bit explanation
    
    Change-Id: I1cb36eeccd84f0056c829f50d9864047654ce906
    Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
    Reviewed-on: http://review.coreboot.org/580
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit acf2aab54b8264b658209d2697ae8b5e26f1b496
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Tue Jan 24 20:22:20 2012 +0530

    pci_ops_mmconf: Move conditional compilation to Makefile
    
    Moved the conditional compilation out of the source file
    
    Change-Id: Ic4045006f39d70f4a0bc37d1bd5e073ed8477c68
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/578
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 409d17dee7b407729a29c067ab064c78be18841e
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jan 17 15:52:05 2012 +0100

    libpayload: Allow using CBFS functions on images in RAM
    
    Two new functions allow switching the CBFS functions from using RAM
    or ROM, with ROM as default.
    
    Change-Id: I04d67ad622d25c5728ae9a63f5b8a3dc9bbacce6
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/550
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e8689ed974992b35aede9cd831b428ac37d9be76
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Fri Jan 20 13:57:48 2012 +0800

    AGESA F15: AMD family15 AGESA code
    
    AMD AGESA code to support Orochi platform family15 model 00-0fh processores,
    AMD C32, G34, and AM3r2 Sockets are supported.
    
    Change-Id: If79392c104ace25f7e01db794fa205f47746bcad
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/554
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d2b31bda6738e370414622bd750cebf2e28e73de
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Wed Jan 25 17:44:20 2012 +0530

    dumpmmcr: Fix compilation warnings in printf
    
    cf., `man 3 printf`
    
    Change-Id: Ib78937a3e1c1eecf884bde0860594cbdb574f1fe
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/582
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit cda56b00f656140a4719b5282c9f16f087e2a4b1
Author: Dave Frodin <dave.frodin@se-eng.com>
Date:   Thu Jan 19 14:28:32 2012 -0700

    Mahogany Fam10 MPtable fix
    
    Make changes MPtable to match ACPI tables.
    
    Change-Id: I387f301370582fcb5e0d348d793333a919d2f373
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/575
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 52bfa4da600e677151e51193077665d4e66f238c
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Fri Jan 20 13:58:53 2012 +0800

    RD890: pci_ids update
    
    RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX
    chipsets, add their pci device id respectively.
    
    Change-Id: I30c62c5802279ff2ee8da1cae41395e6899339bb
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/558
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 94fa3db36688e8db133aebe14d480b0c4722e4c9
Author: Marc Jones <marcj303@gmail.com>
Date:   Fri Jan 13 14:39:48 2012 -0700

    AMD Mahogany Fam10 ACPI table fixes.
    
    Fix the ACPI IRQ routing. Also. fix the SSDT generations and TOM2 fixup.
    
    Change-Id: I03e6de7bb58440058306c9c9888eb2961748c385
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/574
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 31b680bfb087f8007c6f36d46843151d1ef1246b
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Tue Jan 24 19:17:47 2012 +0530

    pci_ops_conf: Indentation fixes
    
    Indentation fixes in src/arch/x86/lib/pci_ops_conf{1,2}.c
    
    Change-Id: I56e8ff6d2ee3a0b871b40577e10c99dea4b3b1bd
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/576
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 26dd3616b8111c51c56c5da7d7ea6c84be739eaf
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Tue Jan 24 20:18:56 2012 +0530

    pci_ops_mmconf: Indentation fixes
    
    Indentation fixes in src/arch/x86/lib/pci_ops_mmconf.c
    
    Change-Id: If8337bae06295db16ed1c129ab76dea37eb465ae
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/577
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0713ca3f8493ee89103b4826137bd64f59c88933
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Mon Jan 23 01:44:44 2012 +0530

    post code: Replaced hard-coded post code with macro
    
    Added a macro in the post code list, which replaces hard coded
    value in cpu/x86/cache/cache.c
    
    Change-Id: I27cb27827272584a8a17a41c111e2dc155196a97
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/572
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 15370ca0688beff07cfbdf69ef47b0284227ef03
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Sat Jan 21 20:19:14 2012 +0530

    trivial: spelling fixes in comments
    
    Few spelling fixes in entry16.inc
    
    Change-Id: Iad3d18eee3f498171cb766589aaebefdcf0e9767
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/571
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ea07b9fa6cabbf63151438f88db66d0fad1542fe
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Sat Jan 21 15:32:59 2012 +0530

    adm1026: removed prototype
    
    Removed the prototype and restructured the code
    
    Change-Id: I13a648acf7bae30635e0469e301ce5635d9d7a8c
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/570
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c6daaa7497489c578263cc057b2903c04000b01e
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Jan 18 23:28:52 2012 +0100

    Leave SSE and MMX instructions enabled in coreboot
    
    In order to use SSE+MMX optimized payloads we don't want to disable SSE+MMX
    instructions in the CPU after romstage.
    
    Change-Id: I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/553
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 938ae3ed18ac72878e572e4cdc2ff5029fe97d74
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Jan 17 16:51:24 2012 -0700

    Clean up AMD romstage.c serial output
    
    This cleans up the strings in romstage.c, removing the ugly "got past".
    Also, cleaned up comments and some spacing.
    
    Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/539
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0f1dc4eb5bb9941bdb8ff833ec745e1cfeaa9d28
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Apr 22 20:48:21 2011 +0200

    Add subsystem callbacks for VT8237x and VT890 family of chipsets
    
    Change-Id: Id34615f0c229d276d72cdf984cf82ea8cc1a85bb
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/523
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit de64b8b6dbd7059d9e31ede0892ee2a5d6d45e33
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Jan 17 17:34:03 2012 -0700

    Remove duplicated line of code in AMD wrappers.
    
    This line was unnecessary and was duplicated on several mainboards.
    
    Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/541
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2311bd3e91c61eea238486d3690b1346ac5b24d2
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Jan 17 17:30:31 2012 -0700

    Remove old AMD #define
    
    The #define REQUIRED_CALLOUTS is no longer used on these platforms.
    
    Change-Id: I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/540
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c9ea327a4526fccecf9063b5cf272798fa44377b
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Jan 17 15:41:03 2012 -0700

    Clean up AMD romstage.c whitespace indent issues
    
    Change-Id: I1713f1a3b548cb8e8ea5cf57eef95486ceb05ab9
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/538
    Tested-by: build bot (Jenkins)
    Reviewed-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit db89ec975c39e6523336563923ccf8b7397cc313
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Nov 18 11:56:38 2011 +0100

    libpayload: style: compare null-pointers with NULL, not 0
    
    Change-Id: I5efbfb75e2894bc8d8e50c8737cfee9738d15eda
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/551
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 950f20a404df4c270a3f587224f7bc2554c95d6b
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jan 17 13:13:59 2012 +0100

    Add coreboot version to id area
    
    There was no good way to extract the build version from an image.
    
    This change will be mostly backward compatible: The only assumption
    that could break is that the board name string ends directly before
    the 3 dwords that represent .id's "header".
    
    Change-Id: I325491a0c42911d9d6ecd59e21ee1b756c987693
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/537
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit a31bb0779ae5fc932f458cb82126bc87002c83b2
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Wed Jan 18 09:43:52 2012 +0100

    Unify ID_SECTION_OFFSET and mark it deprecated
    
    We used to put the id section at -0x10, with some boards overriding
    this to avoid collisions with romstraps.
    Hardcode the location at -0x80, at the possible expense of some space
    (0x70 bytes).
    This also makes the section easier to find in a binary image.
    
    At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option
    is moved to src/Kconfig.deprecated_options.
    
    Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/549
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 3ad8c54c01ab16b13eb9fe1cec8516aaed94c426
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Dec 2 16:23:06 2011 +0100

    lib: add ram_check_nodie
    
    The current implementation calls die() if memory checking fails.
    This isn't always what we want: one might want to print error registers,
    or do some other error handling. Introduce ram_check_nodie() for that
    reason. It returns 0 if ram check succeeded, otherwise 1.
    
    Change-Id: Ib9a9279120755cf63b5b3ba5e0646492c3c29ac2
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/532
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 5db45b4d4aa318a7f5b9e9a46607762e74fac823
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jan 10 22:33:01 2012 +0100

    W83627HF: remove unused function
    
    When CONFIG_EXPERT is set, compilation fails with:
    
    src/superio/winbond/w83627hf/superio.c:61:13: error: ‘w83627hf_16_bit_addr_qual’ defined but not used [-Werror=unused-function]
    cc1: all warnings being treated as errors
    
    This function isn't used in the code, so just remove it.
    
    Change-Id: I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/533
    Tested-by: build bot (Jenkins)

commit adfbcb79ab719af4435e3fdbb8321cda825e076c
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jan 10 12:01:43 2012 +0100

    MTRR: get physical address size from CPUID
    
    The current code uses static values for the physical address size
    supported by a CPU. This isn't always the right value: I.e. on
    model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
    Xeons from the same family have 38 bits, which results in invalid
    MTRR setup. Fix this by getting the right number from CPUID.
    
    Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/529
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 75fb40e15dbffe4148ab108e11d10fe3a9ed6cbe
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Dec 2 16:26:02 2011 +0100

    Add missing HAVE_HARD_RESET
    
    Change-Id: I6b612dbd3eb6e8cc45f1c7abca85732fb64de98c
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/531
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 784ffb3db694dd2c964d9a4e1c6657a835b2d141
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jan 10 12:16:38 2012 +0100

    i945: fix tsc udelay()
    
    The comparision is the wrong way round: as long as tsc
    is below tsc1, the timeout is not reached
    
    Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/530
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8fa2787a0d74c70ca9497abf1483ab9dd223e642
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 24 13:19:57 2011 +0100

    libpayload: Remove bitfield use from EHCI data structures
    
    We agreed that bitfields are a Bad Idea[tm].
    
    Change-Id: If4c4cb748af340e2721b89fea8e035da0632971f
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/480
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit b0b4a52b70f0d7c09241f0f718a179fc55d85179
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 24 11:55:46 2011 +0100

    libpayload: Remove bitfield use from UHCI data structures
    
    We agreed that bitfields are a Bad Idea[tm].
    
    Change-Id: I1b2bcda28c52ad10bbe9429e04d126b555f7828a
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/478
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit c4348d0a448a59b2d2d5bfaccbfa7504918a445b
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 24 09:12:11 2011 +0100

    libpayload: Remove bitfield use from OHCI data structures
    
    We agreed that bitfields are a Bad Idea[tm].
    
    Change-Id: Ic04f151091c359912835b8b3db488d2d41bd4bbb
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/479
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit ad6331d25f845c661013d16e2290d3916aac1a1c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jul 2 00:35:02 2011 +0200

    Un-perl commit-msg hook
    
    To simplify installation on mingw a bit (even though git remains a pain),
    drop the perl dependency the commit-msg hook introduced to the coreboot
    development environment.
    It's replaced by awk which we use elsewhere already (and is a more lightweight
    utility in any case)
    
    Change-Id: I67adfe1ec43c898735d4bae4819ceb53e83c303b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/78
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit eb84f6a978147fbe543fbe15af254632f215098a
Author: Nils Jacobs <njacobs8@adsltotaal.nl>
Date:   Mon Jan 9 20:27:07 2012 +0100

    Fix Geode GX2 + LX caching for tiny bootblock.
    
    Change-Id: If681a33deb7df752b37c6a8a20482d3c374af936
    Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
    Reviewed-on: http://review.coreboot.org/528
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Philip Prindeville <philipp@redfish-solutions.com>

commit 8d846135ff0779b19eccef0bbb15ddfe366205c6
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Dec 23 10:29:09 2011 +0100

    ACPI: mark empty get_cst_entries() weak
    
    This function prevents the linker from choosing the right
    get_cst_entries(), preventing writing the _CST tables.
    
    Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/496
    Tested-by: build bot (Jenkins)

commit b5d81eb43db54bd807af68744ebefa429c95843a
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Sat Jan 7 10:17:50 2012 -0600

    rs780: correct comment in switching_gpp_configurations()
    
    Change-Id: I6417a92523eea7307d080669fbc4e16ee28c8a6c
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/524
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f61fff92e4ff0de9c7e0efc6a8afaa42c5143822
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Sat Jan 7 16:04:46 2012 +0530

    adm1027: add return statement
    
    Adds a missing return statment which will stop misleading the users
    
    Change-Id: I53741f1136b396e9493ce959b54efc00c9b09764
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/522
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4b7b320ff80c1047503e26fd387ba3d8acd996d9
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jan 8 15:27:18 2012 +0100

    inteltool: Add support for dumping AMB registers
    
    Change-Id: I98615725afdb315caa67b2226224e3eb2a0e4393
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/525
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f91cf9f1eabcac18609806ac99162ebfd8f1e3d0
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Dec 14 07:39:57 2011 +0100

    .gitignore ectool, inteltool, msrtool, nvramtool and superiotool
    
    Change-Id: I06e69d97ef3646f79104ec316ce932cc53894c92
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/485
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 68299ee7a44f1b43cd49a2317324eadb6616e330
Author: Philip Prindeville <philipp@redfish-solutions.com>
Date:   Fri Dec 23 18:45:33 2011 -0700

    Eliminate magic numbers
    
    Use sizeof() on vendor and part# rather than explicit memory length.
    
    Change-Id: I2b7e0e4a8df6448d027cc61867382f161eb990d3
    Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
    Reviewed-on: http://review.coreboot.org/504
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9a7c246767cc541728108aa5c558cd08cbb5471d
Author: Philip Prindeville <philipp@redfish-solutions.com>
Date:   Sat Dec 24 22:12:37 2011 -0700

    Cleanup access to vendor/part # info
    
    Instead of macros to access MAINBOARD record, use convenience functions.
    
    Store pointers to MAINBOARD and HEADER for use outside of CB code.
    
    Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12
    Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
    Reviewed-on: http://review.coreboot.org/502
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d0ac789e212c1bef6582e2ae33118280f287318e
Author: Nils Jacobs <njacobs8@adsltotaal.nl>
Date:   Fri Dec 30 23:00:11 2011 +0100

    Update geode GX2 tree to match LX.
    
    Change-Id: I5b99c531e44ea09990b9da0b97213fb7945f34ee
    Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
    Reviewed-on: http://review.coreboot.org/512
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f3fe3d2140e147b7cb55428a982f14dacd0f8ef7
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Wed Jan 4 19:37:48 2012 -0600

    rs780: use bitwise rather than boolean not
    
    Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/518
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 0786bc6ad89449f810e169c131da2047af9a7048
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Mon Dec 26 22:52:01 2011 +0530

    Indentation: Various indentation fixes
    
    Fixed indentation using indent tool in the src/drivers/i2c tree
    
    Change-Id: I5b396e5753544aff13ac5d16afc59e193a6b1da1
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/506
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 7bfd22e4c62a43663624f0893ee73625a0db4c11
Author: Marc Jones <marcj303@gmail.com>
Date:   Mon Dec 12 22:04:25 2011 -0700

    Fix Fam14 AGESA ACPI table generation
    
    The AGESA wrapper init late call generates the SSDT and other ACPI tables. The
    call was failing without heap space allocated causing the ASSERT messages in
    the output. I think are there may still be other issues in integrating the
    SSDT table with the DSDT, but now it is there to debug.
    
    The changes were made in Persimmon and copied to the other Fam14 mainboards.
    Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/517
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 84e0dfcbf2ea977e15c6dc79d12836b138dabd41
Author: Marc Jones <marcj303@gmail.com>
Date:   Mon Dec 12 21:12:43 2011 -0700

    Clean up AMD Fam14 SSDT
    
    The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now
    include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is
    for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This
    fixes some ACPI errors in Linux and Windows bluescreens.
    
    The Persimmon acpi_tables.c is where the main changes were made and then
    replicated in the other Fam14 boards. Please test the other mainbords if you
    have one.
    
    Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/516
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 522ba28874c0e049c899fc74b906346605b50d0f
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Jan 3 16:02:07 2012 -0700

    Fix Fam14 mainboard whitespace
    
    Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming
    changes
    
    Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/515
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

commit 8bd41cd3b58ceb13b9b6670170bb8a90082a3c1e
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Wed Jan 4 19:43:49 2012 -0600

    rs780: power down GPPSB SB lane pads in correct PCIe core
    
    Change-Id: I059d5b155cae051f31cc2495f8a47d53e01af808
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/519
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit cb34bba5df7b081d5324d8af8c7ba4d5860ec9f8
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Mon Jan 2 19:11:49 2012 -0600

    Add missing EOT marker.
    
    Omitted from commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576
    
    Change-Id: Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Reviewed-on: http://review.coreboot.org/514
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Philip Prindeville <pprindeville@gmail.com>

commit 28f171096bc289f848c03593a6d04c2987c89617
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Thu Dec 22 12:18:26 2011 +0800

    F14 mainboard: mptable update
    
    Add GNB internal graphic interrupt,
    correct southbridge hd audio device interrupt. and remove the
    dead code already commented out.
    
    south_station, union_station, inagua, persimmon and e350m1 mainboard
    are included herein.
    
    Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Reviewed-on: http://review.coreboot.org/451
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit d6ed09b7eca40a29a2cd4a3b6a5f0e4dfeb07641
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Thu Dec 22 12:18:37 2011 +0800

    F14 mainboard: update acpi interrupt routing in pic and apic mode
    
    Add interrupt routing for APU GNB internal Graphic and HD audio device, and
    other pcie bridge device in GNB.
    
    south_station, union_station, inagua, persimmon and e350m1 mainboard
    are included herein.
    
    Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Reviewed-on: http://review.coreboot.org/452
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit a4f06f183b56cbcd00e0559c1d6c493fed4d7894
Author: Nils Jacobs <njacobs8@adsltotaal.nl>
Date:   Fri Dec 30 22:30:27 2011 +0100

    White space and coding style fixes.
    
    Change-Id: I14f39b5666fc18e8183723ec78a40a849d337736
    Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
    Reviewed-on: http://review.coreboot.org/511
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 79cfe7e024877f51c216449f81a5821e8e782d9b
Author: Marc Jones <marcj303@gmail.com>
Date:   Wed Dec 14 15:33:33 2011 -0700

    Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.
    
    I misunderstood how kconfig select works. It needs to be selected with a config option. Moved the select to the correct location.
    
    Change-Id: If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/487
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2b751c6f79b34f7d96598beb10c21b2d84d839d9
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Mon Dec 26 02:08:44 2011 +0530

    trivial:change the value type of POST_PORT in Kconfig from int to hex
    
    trivial change in src/console/Kconfig
    
    Change-Id: Ib6bb4ccfabaa3af18b48a23a51a576b872d807a8
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Reviewed-on: http://review.coreboot.org/505
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 472d9025e57a3afcd8af547df218db134253a56f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Dec 5 20:33:55 2011 +0200

    Sconfig: parse Kconfig options from devicetree.cb
    
    Mainboard and chip Kconfig files have several build options that
    are redundant with information in devicetree.cb. This patch enables
    sconfig to auto-generate equivalent configuration.
    
      sconfig -s
    
    Generates mainboard's static.c file, as before.
    
      sconfig -b
    
    This operation creates mainboard's bootblock init code. By default,
    for every chip listed in mainboard/devicetree.cb, if there is a
    chip/bootblock.c file, the init function is called.
    A mainboard/bootblock.c file can be added to override default
    behaviour.
    
      sconfig -k
    
    This operation generates select -options for component paths.
    
    Change-Id: I808d44af552dbc5e0565d6a0f4f72c7be9f5740e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/472
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f28dbe0c5d299297029afe01bb7329c6c18ae3db
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Dec 5 20:17:17 2011 +0200

    Only BSP CPU writes CMOS in bootblock code
    
    CMOS accesses are not safe for multi-processor and only the BSP CPU
    should count reboots and test CMOS sanity.
    
    A questionable single byte CMOS read access from AP CPUs remains.
    AP CPUs should always select the same romstage prefix as BSP CPU.
    
    Change-Id: I29118e33c07c0080c94abb90f703e38312c72432
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/446
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f42fdabe651ab327a5c76d672781d60bd9124e94
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Nov 18 14:44:16 2011 +0100

    libpayload: remove uhci_reg_maskX
    
    Not that good an idea to start with.
    
    Coccinelle patch:
    @@
    @@
    -void
    (
    -uhci_reg_mask8
    |
    -uhci_reg_mask16
    |
    -uhci_reg_mask32
    )
    - (...) { ... }
    
    @@
    @@
    -void
    (
    -uhci_reg_mask8
    |
    -uhci_reg_mask16
    |
    -uhci_reg_mask32
    )
    - (...);
    
    @@
    expression ctrl, reg, ormask;
    @@
    -uhci_reg_mask32 (ctrl, reg, ~0, ormask)
    +uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) | ormask)
    
    @@
    expression ctrl, reg, ormask;
    @@
    -uhci_reg_mask16 (ctrl, reg, ~0, ormask)
    +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) | ormask)
    
    @@
    expression ctrl, reg, ormask;
    @@
    -uhci_reg_mask8 (ctrl, reg, ~0, ormask)
    +uhci_reg_write8 (ctrl, reg, uhci_reg_read8 (ctrl, reg) | ormask)
    
    @@
    expression ctrl, reg, andmask;
    @@
    -uhci_reg_mask32 (ctrl, reg, andmask, 0)
    +uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) & andmask)
    
    @@
    expression ctrl, reg, andmask;
    @@
    -uhci_reg_mask16 (ctrl, reg, andmask, 0)
    +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask)
    
    @@
    expression ctrl, reg, andmask;
    @@
    -uhci_reg_mask16 (ctrl, reg, andmask, 0)
    +uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask)
    
    Change-Id: Id0eb8327293831e54249d43fd06d50963c793699
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/477
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 44bf6fcbb2ca9cca24038b29afb695db41a629f0
Author: Philip Prindeville <philipp@redfish-solutions.com>
Date:   Fri Dec 23 18:33:05 2011 -0700

    Let lib_get_sysinfo() pass through the success of get_coreboot_info()
    
    The return status of get_coreboot_info() might be handy to a platform
    driver calling lib_get_sysinfo() to test for the presence of coreboot.
    
    Change-Id: I0176c93ee92c9dff733112026ee50f2ca797bdff
    Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
    Reviewed-on: http://review.coreboot.org/503
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7d95b3e52804c3adfaf45453dbff289d8c1ae32e
Author: Philip Prindeville <philipp@redfish-solutions.com>
Date:   Fri Dec 23 17:53:26 2011 -0700

    Fix missing cast back to void *
    
    MEM_RANGE_PTR() also needs to return a pointer to untyped memory.
    
    Change-Id: I0ec64ad7bdb136d5e1a999bff3df6fa66eb29bf1
    Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
    Reviewed-on: http://review.coreboot.org/500
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 965dacebc54c8108bd30afb757466ac9427272fa
Author: Philip Prindeville <philipp@redfish-solutions.com>
Date:   Fri Dec 23 17:36:09 2011 -0700

    Fix missing VM mapping
    
    When processing FORWARD records, we weren't accounting for the pointer
    being in the physical address space and not the virtual space instead.
    
    Change-Id: I35ef637fbec7886d4cfeac5fd650a17eae8d555a
    Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
    Reviewed-on: http://review.coreboot.org/499
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c10cade4042dca08f9c176e93e6457c7a7f4e40a
Author: Philip Prindeville <philipp@redfish-solutions.com>
Date:   Fri Dec 23 17:28:59 2011 -0700

    Use void pointers for untyped memory
    
    To avoid unnecessary casts, we can use untyped pointers when accessing
    individual records.
    
    Change-Id: I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3
    Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
    Reviewed-on: http://review.coreboot.org/498
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fe2f6b075ec0159b5308c90b69213d8c4543fbb6
Author: Philip Prindeville <philipp@redfish-solutions.com>
Date:   Fri Dec 23 17:22:05 2011 -0700

    Use convenience function to checksum
    
    That coreboot uses the IP checksum is an artifact, not a deliberate
    requirement to be compatible with the Internet Protocole suite. Use
    a wrapper to abstract the computation of coreboot's checksum.
    
    Change-Id: I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370
    Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
    Reviewed-on: http://review.coreboot.org/497
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 46404d75e4dc106268e1027a4828d8ea4f17f389
Author: Philip Prindeville <philipp@redfish-solutions.com>
Date:   Fri Dec 23 17:09:02 2011 -0700

    Replace UNPACK_CB64 macro with inline
    
    Having submitted a module based on coreboot to LKML for acceptance,
    it was requested that fewer macros and more inlines be used (because
    of their superior type-checking when performing pointer casts, etc).
    
    This is the first of several changes to make the relevant parts of
    coreboot comply to linux code standards.
    
    Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a
    Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
    Reviewed-on: http://review.coreboot.org/495
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d3cf0c811eccdf7b6801b0680c81d4c485a085cd
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Wed Nov 23 15:04:13 2011 +0800

    south_station: Enable GNB hd audio
    
    Enable HD audio over HDMI.
    Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed.
    
    Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Reviewed-on: http://review.coreboot.org/450
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 374018d827e0967ba828cd4fc31ddeacf0003afd
Author: Marc Jones <marcj303@gmail.com>
Date:   Wed Dec 14 15:59:02 2011 -0700

    Add RS780 defaut graphics ID to AMD Mahogany mainboard.
    
    Added the default ID to the mainboard Kconfig.
    
    Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/488
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 74b659992b3283ac8e0f7aa3d371f93144771451
Author: Christian Ruppert <idl0r@qasl.de>
Date:   Sat Dec 17 21:56:05 2011 +0100

    Respect linker order
    
    Linking fails when using -Wl,--as-needed and/or esp. when forcing --as-needed
    through a compiler specs file.
    A proper compile/link command would look like: $(CC) $(CFLAGS) $(LDFLAGS) -o foo
    $(OBJS) $(LIBS). So the *FLAGS must be passed *before* the objects while the
    libraries/dependencies must be passed *after* the objects.
    For more details see: http://www.gentoo.org/proj/en/qa/asneeded.xml
    
    Change-Id: I5a5b05e1cab8a2d88ce56c92d9b2f991ca1ee6c0
    Signed-off-by: Christian Ruppert <idl0r@qasl.de>
    Reviewed-on: http://review.coreboot.org/494
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1c80cf04fe6ffd9508e9d142b6bff03fd7006f95
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Wed Dec 14 08:40:48 2011 +0100

    kbd: wait longer for self-test on keyboard reset
    
    Some keyboards take pretty long to respond to a reset command, some even
    delay the ACK to the command. To make the keyboard driver more robust,
    increase the timeout for this special command. Also do an interface test
    after the self-test to ensure the keyboard is functioning properly.
    
    Another point is to reenable the keyboard *after* the scancode was set,
    not before. We also set the system bit when enabling the keyboard
    because this seems to be what older operating systems do expect.
    
    One of the problematic keyboards, which will work with this patch
    applied, is the DELL RT7D20. Without the patch an overly optimistic
    operating system, read Linux 2.4, will not recognise the keyboard
    because coreboot didn't fully initialize it.
    
    Change-Id: I28c8e05bdde61f71b7de084c96bc2447c1b9575e
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/486
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f154c01802992dd98227c069937f63373ef35f42
Author: Marc Jones <marcj303@gmail.com>
Date:   Wed Dec 14 11:24:00 2011 -0700

    Persimmon audio codec verb patch.
    
    Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
    data is not required for mainboards that use G-Series HDMI. It is also a setting
    the may be boards specific. This fixes issues with Windows audio on Persimmon.
    
    Change-Id: I067506871e92078d122cf79872363d8937d47e50
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/490
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6eefef9f2c546dd7c5db05878d01233fa95dd54b
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Dec 14 07:32:15 2011 +0100

    .gitignore util/crossgcc/build-* and unpacked source directories
    
    Change-Id: I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/484
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d5992b8dd1e4a7d73e0aaf042f0cb96a5c28533a
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Dec 7 14:30:58 2011 -0800

    Lenovo X60/T60: add first_battery setting
    
    The EC allows to select the order in which batteries are (dis)charged.
    Make this setting available to the user.
    
    Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/475
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 009ad83d5c1791816801216c496ba9b3fe352fb5
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Dec 6 10:31:10 2011 +0100

    asus k8v-x: explicitly set RAM and bus voltages
    
    Change-Id: I9426cafc252ee765d723af569c4a90e090d313d9
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/482
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 36b53bf2445f85cd89711de37e4123f761478afe
Author: Florian Zumbiehl <florz@florz.de>
Date:   Sat Dec 10 19:39:49 2011 +0100

    k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x
    
    Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/481
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 20d9de33ccb71d3cd233f77f244af4e53c8846ca
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Dec 13 23:08:03 2011 +0100

    Fix console output in real mode int10 implementation.
    
    Checking RBIL, int10 AH=0x10 does never output a character.
    The two output functions are AH=0x09 and AH=0x0e.
    
    Change-Id: Id7f4d260b63024748ef771f949e8b60f934bacbc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/483
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit dbde80955845177d15bce31943e22546a8ca399b
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Nov 22 13:07:45 2011 +0100

    libpayload: add set_option() function
    
    It allows to change CMOS values from payloads
    
    Change-Id: I4872fc27476923adafe13504126235b92b30de85
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/445
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a27561c3c9c465ac336fafe1b6ca24d2aabc95e9
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Nov 22 10:27:24 2011 +0100

    Fix CMOS handling for non-USE_OPTION_TABLE configuration
    
    The read_option macro still emitted CMOS_VSTART_*/CMOS_VEND_* symbols,
    which fail without an option table (as no option_table.h defines them).
    
    Discard them by using a macro instead of a static inline function.
    
    Change-Id: I8d001f971681277a344b6788725746491546b607
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/442
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 90ca14d7004a3f53a13bdbe6401171b029baaf3d
Author: Marc Jones <marcj303@gmail.com>
Date:   Wed Nov 23 17:49:19 2011 -0700

    Use MMCONF for all AMD family 10 CPUs.
    
    This fixes problems in AP init when multiple APs are trying to access
    PCI config space. All Fam10 CPUs setup and support MMCONF.
    
    Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/455
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alec Ari <neotheuser@ymail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 403d2d697e01f944d9a15892a1fed1d56da88412
Author: Alec Ari <neotheuser@ymail.com>
Date:   Wed Dec 7 01:50:52 2011 -0600

    Change DSDT Table ID for M4A785T-M board
    
    Change the DSDT Table ID for M4A785T-M
    from M4A785-M to M4A785T-M.
    
    This fixes a small copypasta.
    
    This is an updated patch set.
    
    Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c
    Signed-off-by: Alec Ari <neotheuser@ymail.com>
    Reviewed-on: http://review.coreboot.org/474
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b192df4d97978b3f21676756714a37531a45dc08
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Nov 23 16:33:12 2011 +0200

    Fix ldscript for bootblock .rom section
    
    Allocation size for the section was miscalculated, so the section
    did not honour its upper-bound address.
    
    Also align the section start to 4 bytes, so it starts with code
    instead of pad bytes.
    
    Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/453
    Tested-by: build bot (Jenkins)
    Reviewed-by: Alec Ari <neotheuser@ymail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4c132bbc512fae6fe1cb36b35844e2f4956587ed
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sat Dec 3 11:30:26 2011 +0200

    Fix AMD 8132 and 8151 southbridge builds
    
    Untested, changes ramstage build for boards:
      supermicro/h8qme_fam10
      amd/serengeti_cheetah
      amd/serengeti_cheetah_fam10
    
    AMD 8132 was not built for any mainboard due to a typo.
    
    AMD Serengeti Cheetah:
      Chip 8151 is referenced in devicetree.cb but was not built.
    
    AMD Serengeti Cheetah Family10:
      There are indications the board has 8151, but it is not listed
      in the devicetree.cb. The 8151 chip is not added in the build.
    
    Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/471
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit eafb18be437d00e2e0b2f2cf0bcd370913524f04
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Nov 22 19:44:45 2011 +0200

    Bootblock does not need a unique boot_cpu()
    
    Detection of a CPU being a BSP CPU is not dependent of the existence
    of northbridge and/or southbridge init code in the bootblock.
    
    Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP
    CPU of a hyper-threading CPU and needs to return actual BSP bit from
    MSR.
    
    Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/447
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7519d77f72836d47349c563b398e59d3ea8d8b97
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sun Nov 27 13:43:16 2011 +0100

    RS780: print the vgainfo
    
    With this commit the vgainfo is printed and looks like that on the serial console:
    vgainfo:
      ulBootUpEngineClock:50000
      ulBootUpUMAClock:66700
      ulBootUpSidePortClock:0
      ulMinSidePortClock:0
      ulSystemConfig:0
      ulBootUpReqDisplayVector:0
      ulOtherDisplayMisc:0
      ulDDISlot1Config:0
      ulDDISlot2Config:0
      ucMemoryType:0
      ucUMAChannelNumber:1
      ucDockingPinBit:0
      ucDockingPinPolarity:0
      ulDockingPinCFGInfo:0
      ulCPUCapInfo: 2
      usNumberOfCyclesInPeriod:0
      usMaxNBVoltage:0
      usMinNBVoltage:0
      usBootUpNBVoltage:0
      ulHTLinkFreq:20000
      usMinHTLinkWidth:8
      usMaxHTLinkWidth:8
      usUMASyncStartDelay:100
      usUMADataReturnTime:300
      usLinkStatusZeroTime:600
      ulHighVoltageHTLinkFreq:20000
      ulLowVoltageHTLinkFreq:20000
      usMaxUpStreamHTLinkWidth:8
      usMaxDownStreamHTLinkWidth:8
      usMinUpStreamHTLinkWidth:8
      usMinDownStreamHTLinkWidth:8
    
    Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/456
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6cdf5a9e2e545e18f8878698ec9cae61b6ad964b
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:19:41 2011 +0100

    adding support for the Asus K8V-X
    
    This pulls it all together and adds the real board-specific code.
    
    Confirmed to be working:
    - IDE
    - SATA
    - floppy
    - USB1.1
    - USB2.0
    - PS/2 keyboard
    - PS/2 mouse
    - serial
    - parport
    - sound
    - ethernet
    - PCI slots
    - AGP
    - powernow
    - fan speed monitoring
    - flashrom write
    
    Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/390
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
    Tested-by: build bot (Jenkins)

commit f22a6d0c5edac4456eae50f398b5c6ffe6b9e8fe
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Wed Nov 23 00:23:43 2011 +0100

    Fix Asus A8V-E SE DIMM slot mapping
    
    Fix the DIMM mappings, channel 0 is "B" on board,
    and secondary channel is on 0x51,0x53
    
    Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/449
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b5320573c3a511723b75f93a22a19a0faf8ac4a7
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:19:37 2011 +0100

    make GPIOs and misc configurable via devicetree
    
    Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/387
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 98236ca7844ec36bf1e43a9d689b55fa409f0a4a
Author: Florian Zumbiehl <florz@florz.de>
Date:   Mon Nov 21 03:10:47 2011 +0100

    make INT[EFGH]# of vt8237 configurable as gpio via devicetree
    
    Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/386
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 2138556e2aaa70730a58e6a74dd17ed5bc27bcc1
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:19:40 2011 +0100

    copied asus a8v-e_se to k8v-x
    
    Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/389
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 6a3e8d62f852f2abd377d827c0909aa71c44ca39
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:19:38 2011 +0100

    some black magic for initializing the old version of the k8t800
    
    Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/388
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 1b940fd424bbe50fb8792680e2826b7f59a6d1df
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:19:35 2011 +0100

    implement usb2 termination and dpll delay setting for vt8237r
    
    Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/385
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 28bdd8d9eb7521df60b9cb918320cf2ba9a23e1e
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Dec 2 16:33:30 2011 +0100

    i3100: Add HAVE_HARD_RESET
    
    and remove it from mainboard/intel/mtarvon, as this function
    is implemented in the southbridge code.
    
    Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/469
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 45945cf445e38b9737f7d9d537f0768c2a4e1ee1
Author: QingPei Wang <wangqingpei@gmail.com>
Date:   Tue Nov 22 15:24:12 2011 +0800

    Mirror Fix coreinfo usage of cb_info
    
    fix cb_info.serial.ioport to cb_info.serial.baseaddr
    
    Change-Id: I32f261e4be927555979eb833d0251fce2c6a5c47
    Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
    Reviewed-on: http://review.coreboot.org/441
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 490eb86b48c97d39a05319246ed038bdc8dfdcec
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sun Nov 27 22:04:02 2011 +0100

    M4A785T-M: fix ACPI's P-States Table
    
    Without that fix the linux kernel cannot change the frequency
      of the CPUs with cpufreq.
    
    Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/458
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 96ffc55bfd3fa5500fbe6b315f81462d421fb1f1
Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Date:   Sun Nov 27 15:58:38 2011 +0100

    Add ASUS M4A785T-M mainboard support
    
    This mainboard is very similar to the M4A785-M, but it has
      DDR3 instead of DDR2.
    
    That's why most of the code was copied or included from
      the m4a785-m directory
    
    Notable changes between the two mainboards include:
     * the selection of the last microcode (mc_patch_010000b6.h)
       which made it pass the CPU init.
     * the selection of DDR3 which made it pass the ram init
    
    This change was tested with the Trisquel 5.0 GNU/Linux distribution
      which uses the linux-libre version 2.6.38-12-generic
    
    The mainboard boots fine, however some special care is required for
      the onboard sound CODEC, and the onboard video chip:
      * the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue
        is the same than the ASUS M4A785-M mainboard:
        It causes a flood of interupts which prevents booting
      * The internal video chip currently requires pci=nocrs, else
        the graphics are frozen as soon as the radeon module loads,
        and dmesg would print the following(the card only has 256M,
        and the mainboard was equiped with 2G of RAM):
          [    3.674762] [drm] radeon: 3584M of VRAM memory ready
          [    3.679863] [drm] radeon: 512M of GTT memory ready.
        instead of :
          [   45.876088] [drm] radeon: 256M of VRAM memory ready
          [   45.876089] [drm] radeon: 512M of GTT memory ready.
      * The screen(both VGA and HDMI) flickers at high resolution
      * Sometimes the computer freeze while changing the resolution
        (even the serial console stops responding)
    
    The following peripherals were tested:
     * The ath9k PCI wireless card was tested
     * The SATA hard disk works fine
     * the USB keyboard and mouse work fine
     * htop see 2 cores
     * serial port works under coreboot and GNU/Linux
     * power off and reboot works
    
    CPU frequency cannot be changed yet, this is addressed
      in a new commit.
    
    More detail are available here:
      http://www.coreboot.org/ASUS_M4A785T-M
    
    dmesg is available here:
      http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html
    
    The mailing list thread on the graphic problem is here:
      http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html
    
    Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Reviewed-on: http://review.coreboot.org/457
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 188a9b0a7fa0509a5d03a839073670054f0ed0f6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Dec 2 18:05:46 2011 +0200

    Remove obsolete TINY_BOOTBLOCK
    
    Change-Id: I0edc69dc5f95cc32ee648eb094c9e5387f80db47
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/470
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2a830d0b9807566a5f2c4401cd9fd285661034f1
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Thu Dec 1 17:49:43 2011 +0200

    Change AMD vendorcode build
    
    Apply the normal method of recursively including subdirectories
    for src/vendorcode. Remove redundant references under
    mainboard and northbridge.
    
    Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/468
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2c1f4d2d836bfb5728c692e08bda172a1639ec81
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Nov 28 21:12:11 2011 +0100

    X60/T60: reset baudrate loglevel to sane values
    
    Change-Id: Iaf5861e9db0a41a184da6d2e515e3b9afe0655d6
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/459
    Tested-by: build bot (Jenkins)

commit 0dbfb54a721dd905707a0c152754b78b9dfb69b0
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Tue Nov 22 20:21:06 2011 +0200

    Remove unused code files and cosmetic changes
    
    Following files were no longer used in the build and are deleted:
       src/arch/x86/init/entry.S
       src/arch/x86/init/ldscript.ld
    
    Also fix ugly whitespace in code copyrights and comments.
    
    Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/440
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 912d8919d4496379469cd898391ca08f1a90c225
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:19:04 2011 +0100

    vt8237: add support for setting the power state after loss of power
    
    Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/437
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit fa48b969086216341f77738df4b912859010fcf6
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:18:29 2011 +0100

    k8 raminit: fix bug, improve clock selection, add clock limit for sock754
    
    in amdk8 raminit:
    - fix DDR SPD offset for (CLX - 1) (25 instead of 26)
    - improve clock/CL selection algorithm
    - implement load-dependent clock limiting for socket 754
    
    Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/377
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 85392a8c985b11388efb4a07ef1b1481d9a511e2
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:19:06 2011 +0100

    implement hwmon fan divisor setting for w83697hf
    
    Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/384
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
    Tested-by: build bot (Jenkins)

commit 04a8d6239f43c16a2f8f2d0c9893ddecdc3340a6
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 22 21:32:31 2011 +0100

    k8 raminit: add workaround for erratum #181 on non-fam-f
    
    Disable DRAM controller on non-fam-f CPUs not using fam-f register layout.
    
    Change-Id: I2cc87857452555011d69bfebe9f9c4c17cef8f6c
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/448
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 2a40ebca9c21c527afd683beeec51a5fa5a77588
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Nov 21 08:16:20 2011 +0200

    Fix post_code in 16bit entry
    
    Relocate early post_code() so it gets executed and does not corrupt
    BIST at %eax.
    
    Change-Id: Ieeebcb23f7c327e501b410eaa60d1e49110ee988
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/439
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b9136ed8473e610d5532254984a440c1690d0af9
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Nov 15 21:27:57 2011 +0800

    mainboard: Add AMD unionstation RDK support
    
    AMD unionstation Reference Design Kit is Designed for hd settop box application.
    This platform using family14 APU, SB800 southbridge.
    Vgabios is required, can download vgabios from AMD NDA website.
    Verified Feature:
     HDMI, LAN, mini-pcie slots, sata, usb, analog audio and
     optical fiber digital audio output.
    
    Change-Id: Ib1d1d8c889d6fb29f4298b57dfe5c5c1cea1431c
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Signed-off-by: Kerry She <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/434
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit b79935129a561eb33cdba06a3a0f65d2e350924c
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Nov 15 21:27:07 2011 +0800

    mainboard: Add AMD southstation RDK support
    
    AMD southstation Reference Design Kit is designed for NAS application.
    This platform using family14 RevC0 processor, SB850 southbridge.
    Vgabios and Promise RAID Option ROM is required for hardware RAID support,
    can retrieve from the AMD NDA website.
    Verified feature:
     HDMI, LAN, usb and mini-pcie slot.
     RAID0, RAID1 RAID10 and RAID5 upto 6 sata hard drive with ubuntu server 10.10.
    
    Change-Id: I16e6f5dab8b0d634e186068c81436db77fb4475a
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Signed-off-by: Kerry She <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/433
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 6f7b1589fa82a2cc654e4f35ce2dc0787d84ce0f
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:18:28 2011 +0100

    fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit
    
    Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/376
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit ba9b09b89ad552700a72c74e335c572422898d76
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Nov 11 11:05:42 2011 +0100

    libpayload: Enable colors in PDcurses
    
    PDcurses wants set_blink to determine color count. Not exactly
    obvious.
    
    Change-Id: I8b2a32f0095d5900fa7e01f04f3f1d565dc2bedf
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/432
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 50dadfb1f8f8f9e1a0ea692652ae6b60b29a9f7e
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:17:41 2011 +0100

    compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
    
    make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included
    for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
    
    Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/374
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit be7d8dcf8d2641ca413514e571f77f8aa7984d19
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:17:14 2011 +0100

    support for different location of HT registers in old version of K8T800
    
    Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/373
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 583abc2eb2f1942fa8384c7e9fcfa830322b4c3b
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Nov 10 15:48:37 2011 +0100

    libpayload: Fix handling of CAPS LOCK key on PS/2 keyboards
    
    The PS/2 keyboard driver set and reset the caps LED to show the
    keyboard status. Unfortunately, that configuration happens over
    the same path used to transmit keypresses.
    
    In face of certain error conditions, the keyboard stopped working.
    This change makes keyboard handling more robust.
    
    Change-Id: I0489a9983ea7dab00357220e09398dd1a8538839
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/430
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f5e102d8103982349d1300e50dbce88bf697de9d
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Mon Nov 7 18:31:33 2011 +0100

    Fixed whitespace and indentation
    
    Code style fixes for the hp/dl145_g1 system board code.
    
    Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Reviewed-on: http://review.coreboot.org/428
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c1a75b13c3153d053de30fd9bf8f271527b6783c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Nov 4 21:37:14 2011 +0100

    buildgcc: Add option to use ccache
    
    This mimicks abuild: -y enables ccache.
    
    Change-Id: I3ac1f809729af816efbc64f5789ab430e1a6a6b2
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/400
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4a5c62cf9120e8f1a2b116efe0cbe658315834c7
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:19:02 2011 +0100

    make w83697hf_set_clksel_48() non-static and add a prototype
    
    make w83697hf_set_clksel_48() non-static and add a prototype so as to
    get rid of warnings about it being unused
    
    Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/380
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ab4c218379e09b7cffb1fedca92815a187844795
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Nov 7 13:16:38 2011 -0800

    selfboot: Don't include unneeded ip_checksum.h
    
    Change-Id: I09b888e70f7432f7025b0b851acfb0279553400f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/426
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c6b8b7dcc4cc1c3e4b142d3b5d460b1550ea8a73
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Nov 7 12:56:12 2011 -0800

    selfboot: fix bug in valid_area()
    
    valid_area will accept a region as valid for the payload if only a part
    of coreboot fits in that region. This means if a payload reaches into a
    neighboring RESERVED region, coreboot would not care and happily
    overwrite that region, as long as the payload also writes to some RAM.
    
    Change-Id: Ie263f83be18009b01a31c71e7285c998747d097f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/425
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2e2b84e42063c2947adbba3781c03c5ec44cc68e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Nov 8 09:58:29 2011 -0800

    move function from header file to .c file
    
    http://review.coreboot.org/#change,378 introduced a function in k8x8xx.h
    move this function to ctrl.c and add a prototype to the header file instead.
    
    Change-Id: I0919ffb2030c53669b95f58b649d4a160f660923
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/429
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 36abff1dc8e74beafa47ad83de17416681970916
Author: Marc Jones <marcj303@gmail.com>
Date:   Mon Nov 7 23:26:14 2011 -0700

    Cleanup Persimmon mainboard whitespace.
    
    Change-Id: I389bde86c5583a4fb37a699162b65b475ed94ddc
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/427
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 19436298711a73d51fa54c76f6004703d25488a5
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Nov 7 12:43:03 2011 -0800

    selfboot: cleanup
    
    - move cbfs_load_payload to the end so we can drop the prototype
    - move lb_start and lb_end to the beginning so they can be used
      in other functions.
    - drop two unused function declarations
    - break a 80+ characters line
    - fix a comment
    
    Change-Id: I460aa1e2ccf9d95ac12233af001076f73ab0268e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/424
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit df073cb439b2acbe1d578f94be20ef983193b128
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Tue Oct 4 22:15:51 2011 +0200

    Added RAMINIT_SYSINFO and declared the necessary structs
    
    Using RAMINIT_SYSINFO should be beneficial for this platform.
    It is also more clean/safe to put data in struct mb_sysconf_t.
    It's more consistent with other MB's and I've tested it
    thoroughly on my DL145.
    
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be
    Reviewed-on: http://review.coreboot.org/236
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 355092b7b843e081cf7d9f7dce488ad9ed85cbcf
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Mon Nov 7 17:48:33 2011 +0100

    Add code to set the clock speed for Winbond W83627THF/THG.
    
    Change-Id: I984404dd1df50b3ba423ac610283b9bf8bca5a31
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Reviewed-on: http://review.coreboot.org/412
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Mon Nov 7 10:56:42 2011 -0600

    superiotool: add detection and dump of Infineon SLB9635 TPM
    
    Change-Id: If94ea5f45135a4b65bdd37532851fa0ba864bb73
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/421
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2d7ab4c559ae1da8ebf1107b179e3a136b869beb
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Mon Nov 7 13:05:18 2011 -0600

    buildgcc: don't download python and expat if disabled
    
    Change-Id: I18cb1426e935c46ead30c72685829c20d186f9d8
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/423
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3fd44c36e5d02af9ab0c5356c64b12be303a40bf
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Nov 7 19:01:54 2011 +0100

    abuild: Don't try to use files that don't exist
    
    Collecting per-board abuild.xml is bound to fail if there
    are no such files.
    
    Change-Id: I6bd6b4389beda51654005e0380f0e52f006642db
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/422
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0802ad90ccfb6caa270918b5fc7aa628cf2a0378
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:19:01 2011 +0100

    rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible
    
    Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/379
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 1e1e8593bc9218c62dc187ce965020045ab385ea
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:18:30 2011 +0100

    factor out common config for k8x8xx's dram_enable() and vt8237r_cfg()
    
    Instead of writing to config registers in k8x8xx's dram_enable()
    and reading those back in vt8237r_cfg(), factor out generation of
    the values and reuse that in both places.
    
    Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/378
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7b1d295f62be4c4d59ea8d1ac18e8ef0bedbca6e
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:19:02 2011 +0100

    add support for 1106:3188 (host controller of the old version of k8t800)
    
    Change-Id: Id61678f03e1f7d964f7180a062dd6a689852d4ac
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/401
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 522e9e9746f4d98c5e8a9b83058ca143e9347d0a
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Mon Nov 7 10:43:05 2011 -0600

    Avoid false detection of SMSC FDC37N972 when Infineon TPM is present
    
    Change-Id: Ibfb3af4c5d7675a5d4e27021cbb988c2ce00fd9f
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/420
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 86bb0072b6201875190c5ec78f5415cd51a9e115
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:16:16 2011 +0100

    in vt8237r_enable(), write function enables only to ISA bridge config space
    
    vt8237r_enable() so far wrote the function enable values to the same
    offset in the config space of every one of the vt8237's functions,
    even though the register is located in the ISA bridge only.
    
    Change-Id: I639586dc238132f5b8d2f320b794948718281b9c
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/368
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7e9de01c4758cc1e8adb05d0c443701495e98fe0
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:17:12 2011 +0100

    Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
    
    Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/370
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 643c9e892fab5f73dde566b9ffb73f2f0463d9a7
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Nov 4 21:30:49 2011 +0100

    buildgcc: Explicitely state CC everywhere
    
    This should fix issues with the iasl Makefile on Debian and
    prepares ccache support for buildgcc.
    
    Change-Id: Id9e6b2044b159b19bf013ec5c47b60ca1c2f2991
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/399
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f285e0412509dc3aa192931b6a0832dbdbc74d0a
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Nov 5 14:39:56 2011 +0100

    kconfig: Use more collision resistant temporary filenames
    
    kconfig creates reasonably safe filenames for its temporary files
    except for two of them.
    
    Change-Id: I6861f55ae2a5311e3fb7919333ce9af1e39ce78b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/408
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3db85f3c1b7d6f167a517dbdd3b4d74971ea620c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Nov 5 13:21:14 2011 +0100

    abuild: Write XML/JUnit files per board
    
    Write them per-board and merge them after everything is done.
    This prepares for build parallelization.
    
    Change-Id: Ia4e7ce03473bcf8861fb9ae06e9c1270292401ac
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/407
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f49f7c851477a91587308de9a2553e91ed3c22e2
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Nov 5 12:55:18 2011 +0100

    abuild: Refactor parallelization support
    
    Use MAKEFLAGS to propagate the parallelization configuration to
    the build
    
    Change-Id: If90ed446edd8e6dc679d284ee9db7a24269edd36
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/406
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8e264656457237c462b30531122143d3a33a057e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Nov 5 12:47:13 2011 +0100

    abuild: Avoid race condition when running abuild parallely
    
    By moving the just-created file away, parallel runs of abuild might break.
    
    Change-Id: I03368f00e9b11dad4c80d41279970e28debc7ed5
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/405
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 641dd71376e367fa3d639a87d694705354f2e028
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Nov 1 18:55:59 2011 +0100

    Inline Makefile.bootblock.inc
    
    This was split out when we had separate rules for big bootblock.
    
    Change-Id: Id0a117f6996fb6bdef7bf97e7d80c36f5dec0ad7
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/404
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 65027021ae026498740f40501179516380dd6ad8
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Oct 15 01:03:16 2011 +0200

    Fix typo
    
    Change-Id: I195ea15ddbc725091e32191fac3b84d01b456580
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/410
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 287ca504a5971dd9076227bc09133dc8aad11da1
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Sat Nov 5 23:39:20 2011 +0100

    w83627hf: multiple fixes and enhancements in ASL include
    
    Fix multiple copy&paste errors and some other bugs in
    devtree.asl. Redesign ENCM method to enter configuration mode
    and set LDN by parameter. Reordered and commented some
    statements to make the code a bit more readable. Add an ifdef
    to enable never showing the keyboard controller as disabled,
    which seems to cause bugs at least with some Linux kernels.
    Remove keyboard controller IO regions from PS/2 mouse device
    as e.g. Linux infers them from the keyboard controller device.
    
    Change-Id: I44611339fabe31a8a584a3e6bd225082bfdd0b8e
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/357
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e3e641ca37506d6ccef7ef5020d00c5518532d8d
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Sat Nov 5 22:14:41 2011 +0100

    w83627hf: drop Scope(\_SB) from ASL include
    
    Drop explicit Scope(\_SB) from devtree.asl as it forces the SuperIO
    to appear as child of the root device.
    devtree.asl then needs to be included at a reasonable position inside
    the \_SB device tree.
    
    Change-Id: I72a57eddc5ec5f9763fdf789094a7be042758256
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/298
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4ffbe2dbe7bc8cc20cdca941dfc57390c88b594f
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Nov 5 22:30:56 2011 +0100

    buildgcc: Fix wrapper Makefile
    
    buildgcc moved from building gdb by default (with opt-out) to
    gdb being optional. Adapt Makefile so it works again
    
    Change-Id: I663a8c70db4f7b5d07456fb67a223dbb2de2c133
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/417
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit bbc523146cfe732eef2ed81fee73c93b1c8e3b34
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Nov 4 12:06:06 2011 +0100

    libpayload: Implement usb_exit
    
    So far it was empty and never published. It now exists and shuts down
    all controllers (esp. EHCI which resets the port routers).
    
    Change-Id: I81e355e8a05778d6397675417b085a094a6f48ee
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/397
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 01178bb03b1ae9bf51962ad03f8f73929a48e4b2
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Nov 4 11:57:46 2011 +0100

    libpayload: Tell EHCI to re-enable USB1 controllers
    
    EHCI can take over all ports (and then reroute devices to
    companion controllers if needs be). We do that, and then never
    reset it.
    
    Consequence:
    Systems with only USB1 HC drivers (OHCI/UHCI) never see any devices.
    
    Change-Id: If1d91e9142a6618289b0b3f6b56587ec857158e3
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/396
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 2e768e7f171514924c3b206b7f3fbe6bf20c1c71
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Nov 4 11:50:03 2011 +0100

    libpayload: Drop usb_fatal()
    
    We have fatal(), which is just as good.
    
    Coccinelle script:
      @@
      expression E;
      @@
      -usb_fatal(E)
      +fatal(E)
    
    Change-Id: Iabecbcc7d068cc0f82687bf51d89c2626642cd86
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/395
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit 3cd0ae2c7b21174188ff1df1f98d3d5295cb7684
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Nov 4 13:18:26 2011 +0100

    Revert "add support for 1106:3188 (host controller of the old version of k8t800)" due to dependency issues.
    
    This reverts commit 68c554550f59bd96caace96260ae2e30ed55ceb4
    
    Change-Id: I353bd36b008f489a972c7c656d7ad07416f01387
    Reviewed-on: http://review.coreboot.org/398
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e037f9f17473b0bd21b8ca63b1cb9479652f3b6b
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:17:13 2011 +0100

    add support for writing to SMBus with vt8237
    
    Change-Id: I70fe072f8f3447d0be7b7ac64508a954fe47091d
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/372
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 8c4cf18fc48baa15388e12efa1d2b8da685df7b8
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:19:02 2011 +0100

    add support for 1106:3188 (host controller of the old version of k8t800)
    
    Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/381
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit c4716b4ebfbcc970bf16f4c74e812fbbb8f00124
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Wed Jun 8 15:36:55 2011 +0200

    libpayload: Reduce verbosity in USB stack
    
    The USB stack is pretty noisy. Reduce the output to a sane level.
    
    Change-Id: I250949e5cf74a8c6d43822b2e7487143b2ae1c65
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/393
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 08052011433af37c02ce7db86af56db7154e4d98
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Thu Oct 20 14:06:26 2011 +0200

    libpayload: Put coreboot version into lib_sysinfo
    
    Change-Id: I22319efe90e475c66b9556f734a7a5e54f7c59bc
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/394
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d35906173ddef192d89532719fbdae29ed232f70
Author: Florian Zumbiehl <florz@florz.de>
Date:   Wed Nov 2 09:46:34 2011 +0100

    fix superiotool for NCT6776F
    
    The current code exits config mode of the NCT6776F immediately after
    detection, so the register dump shows all 0xffs. This patch adds code to
    re-enter config mode for the register dump so that the register contents
    can be read.
    
    Change-Id: I4ad0c108b6411a665e31f55dea4b91ca77d1a5f7
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/391
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f8ed90332c5c51f04e4f7a06a5af3ecd58ffa39c
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:17:13 2011 +0100

    simplify IDE cable detection for Asus M2V
    
    Change-Id: If8e4dcf405e24b744ac34f581c5609fcce96fd07
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/371
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1200ec5a532220b3349d97de1b91f860ae2d2de2
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Nov 1 22:39:41 2011 +0100

    buildgcc: Update coreboot reference toolchain to gcc 4.6.2
    
    In addition:
    - drop some unneeded patches
    - make the scripting support depend on SKIPPYTHON not SKIPGDB
      so it is possible to build GDB with and without scripting support
    - rename the repository checkout version of GCC trunk, not X+1
      so we don't have to change it on every version upgrade.
    
    Change-Id: I1b7d5b8921187c1c1d39b04f20bb715ddba72fe8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/367
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2d4fecec5174908db8a6b660f5b6fffd22e20ea4
Author: Florian Zumbiehl <florz@florz.de>
Date:   Tue Nov 1 20:17:11 2011 +0100

    don't scan beyond end of CBFS
    
    Change-Id: I66e535f77e513dbfa5fc906ecf288193af78ae62
    Signed-off-by: Florian Zumbiehl <florz@florz.de>
    Reviewed-on: http://review.coreboot.org/369
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 2c3cd125be1e617a3b113f4898d131e4a10faae7
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Nov 1 21:43:50 2011 +0100

    Add Python scripting to GDB.
    
    This allows GDB to run Python scripts. The Python build is dependant on the GDB
    build flag.
    
    Changes by Stefan Reinauer:
    - update to latest buildgcc script
    - disable GDB per default
    - disable python scripting, if GDB is not enabled
    - bump version number to 1.06
    
    Change-Id: Ie7fc8706deec41c804870415d3c79d225c98cd31
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/153
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit e11835e2995d130890ca9f45cb3e304f2ea3a6a9
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 31 12:54:00 2011 -0700

    libpayload: remove trailing whitespace and run dos2unix
    
    Change-Id: Iffed3602456f5306711c65f06c873c58d4086e11
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/363
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit dd6906328904309e4d93e4bcb04a6cfa3646f29d
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Oct 27 13:08:13 2011 +0200

    libpayload: Fix OHCI some more
    
    OHCI works when USB_DEBUG is disabled, but not, when disabled.
    This is because the controller requires some more time after a
    schedule has finished.
    
    Also improve compliance with the OHCI spec.
    
    Change-Id: I4685cc485ff9c52b489fbaa352ab889671cff876
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/365
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5ff7c13e858a31addf1558731a12cf6c753b576d
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 31 12:56:45 2011 -0700

    remove trailing whitespace
    
    Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/364
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 784544b934d67dc85ccfcf33e04ff148045836ad
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Oct 31 17:07:52 2011 +0100

    Remove XIP_ROM_BASE
    
    The base is now calculated automatically, and all mentions of that
    config option were typical anyway (4GB - XIP_ROM_SIZE).
    
    Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/366
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 36c04e8a5c54b100a505650218419e112ccc266e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 31 12:52:22 2011 -0700

    Run dos2unix on bayou and remove white space at the end of lines.
    
    Change-Id: If13d9a49ece2699885ae3e998173d3d44507b302
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/362
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 1861ff739c6b2173332f9b53240d34e7cb5e051e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Oct 31 12:15:55 2011 +0100

    buildgcc: Fix colors for dash
    
    The previous fix broke buildgcc colors on MacOS X.
    This uses an encoding that should be more universal.
    
    Change-Id: I31ac6090ffb7c04784cf6566823652f229aebbb5
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/361
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0a0d5e8b86ccc8562ba9761bdd263ebf2667d3c6
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Oct 31 14:18:33 2011 +0200

    Add support for E7505 northbridge.
    
    Adapted from northbridge/intel/e7501 with only minor changes.
    This commit provides minimal patch from e7501 and I prefer any
    cosmetic clean-up to be done after initial merge.
    
    Due the incomplete register specifications, it is safer to have
    e7505 as a separate directory in case I improve it to support
    wider range of memory configurations. I have no e7501 to test with.
    
    Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/295
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 20fc631ad2c483fd2bc12e56f3ca8a1572688fb5
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Oct 30 09:57:35 2011 +0100

    Fix usb debug dongle support
    
    - move enable_usbdebug() declaration to usbdebug.h
    - reinitialize debug driver in ramstage, as copying the data
      structure from romstage doesn't work right now. This way of copying
      data from romstage to ramstage is really board/cpu specific, and is
      likely to break often. So don't do it.
    
    Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/355
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 28f6a43755246641186f2c436b158d2dab4243a5
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Oct 29 00:00:19 2011 +0200

    crossgcc: Fix colors with dash
    
    Ubuntu (and probably other distros) have dash as /bin/sh, which
    doesn't display colors by itself. If /usr/bin/printf is found, it's
    used instead of the internal printf to re-enable colors.
    
    Change-Id: I3e6d413cd0c8a46ef91821d8c07e88166de58af4
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/352
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 9438da370fb66292babf5a2f621a67fd4b3699de
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Oct 30 18:06:58 2011 +0100

    Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9
    
    It is meant to be a address and not a dereference. Otherwise MTRR
    is filled with code and not with the address.
    
    This is what I hate at most on the AT&T syntax. Instead of taking
    the address, it was a dereference. Not greatly visible, except
    I wondered why opcode is not 0xb4 but 0xa1 and it took another
    half an our to see it.
    
    Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/358
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)

commit af3dce981db63eb16d127347264a46247ed893bb
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sun Oct 30 20:30:48 2011 +0100

    Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.
    
    Change-Id: I3ccb3860207e1b3ccac4313f7b537c434af5166f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/360
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

commit 54a5aedec69bac62bf9bb5f65e431130507235fb
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Oct 30 13:30:36 2011 +0100

    inteltool: Add Intel i63xx I/O Controller Hub
    
    Change-Id: Iaea7e4d1b206d43661ecb61d2ae517723fb8d008
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/356
    Tested-by: build bot (Jenkins)

commit 4c2bfb6256da0a4ffab94b3e810b9489e63a5c16
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Oct 30 08:49:43 2011 +0100

    remove usbdebug.h include from mainboard/romstage code
    
    No romstage is supposed to use usbdebug functions/defines
    directly, so remove all those includes. The usb code is now
    called and setup from console code.
    
    Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/354
    Tested-by: build bot (Jenkins)

commit 9491b4d5f5649ab6c18ae7f5ff285c09c212495b
Author: Stefan Reinauer <reinauer@google.com>
Date:   Tue Oct 11 22:37:59 2011 -0700

    Update coreboot cross toolchain to gcc 4.6.1
    
    - Tested on Mac OS X 10.7.1
    - Tested on Ubuntu 10.04 LTS (Lucid Lynx)
    - Tested on Ubuntu 11.10 (Oneiric Ocelot)
    
    Please test on Windows and other Linux distributions
    
    Change-Id: I132c01293fc0cff0cfb84556a93c0b8de8e57230
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/250
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 952b421c27c36c9167c212e28df5a07b7976f587
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Oct 29 22:42:22 2011 +0200

    asus/m5a88-v: Fix build
    
    We added some new flag for certain AMD boards after support for
    this board was submitted. Also integrate the mptable refactorings
    that happened in the meantime.
    
    Change-Id: I50cf50f343a740832fd1a14a2a1ef5b903315675
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/353
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 3954b0ad25476ca7a8eba0fc8106333463514514
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Oct 28 22:52:11 2011 +0200

    Fix coreboot updates
    
    The rule to prepare a new coreboot.pre1 was ignored in the
    "update image" scenario because a perfectly fine file exists.
    Mark it phony to fix it.
    
    Change-Id: Ie7f8b36b71015a593958cd6e19602bad6b854320
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/351
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b9da3cd891b21f0916ccf3e333f9ed77219620d2
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Wed Oct 19 02:25:08 2011 +0200

    w83627hf: add method to retrieve wake event source register to ASL include
    
    Add a method WAKS to devtree.asl which returns the wake-up source register
    to simplify retrieving the wake source e.g. in \_WAK.
    
    Change-Id: Ia258f8fc9ff79b18391c55464da73863889e2255
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/297
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cc66d97f505c304e773dea938ac864cd74363292
Author: QingPei Wang <wangqingpei@gmail.com>
Date:   Tue Sep 13 17:54:12 2011 +0800

    Add ASUS M5A88-V mainboard support
    
    it's a AMD 880+800 mainboard. I port the code
    based on the AMD reference code.
    update: 1.use CIMX instead of pmio
              2.fix some whitespace
              3.fix subsystemid of devicetree.cb
    
    Change-Id: I9725ccdbb25365c4007621318efee80b131fec29
    Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
    Reviewed-on: http://review.coreboot.org/205
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 914377efd61be7b473faca0e6bdfca6f3feb5dc5
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Oct 22 09:54:36 2011 +0200

    Get rid of the old romstage-as-bootblock ROM layout
    
    This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and
    all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n.
    
    This might break a couple of boards on runtime, but so far, fixes were
    quite simple.
    There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be
    adapted.
    
    Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/320
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1da104647dc2828a6594bdc7b5ae119923dbcffa
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Oct 28 20:28:03 2011 +0200

    Get rid of AUTO_XIP_ROM_BASE
    
    That value is now generated from a code address and CONFIG_XIP_ROM_SIZE.
    This works as MTRRs are fully specified by their size and any address
    within the range.
    
    Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/348
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0f8590f9ca8026af62efa510a1c717d2d0729e3d
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Oct 28 09:01:54 2011 +0200

    sb600: Implement EHCI workaround
    
    Linux implements it itself, but older Linuxes and other systems
    might not. Without this, the host controller might not respond
    to drivers.
    
    Change-Id: I4ff0e3683c02e7aa00d188428847c64c4c5d589d
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/345
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5ed8cc0d62b25ee0fb014ccd8726836b1a99d87f
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Oct 6 14:36:08 2011 +0200

    siemens/sitemp_g1p1: Add more devices to PIR and MP table
    
    Linux 2.4 is happier that way
    
    Change-Id: I016609ae1e004ec856e8223893352dcdd061b291
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/346
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 481814d1ab3c762f88964124003ae7ab48c8b12d
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 28 16:15:47 2011 +0300

    Clear improper use of CONFIG_CACHE_AS_RAM
    
    Choice between printk/print_ is related to CAR, but really
    depends whether we compiled with GCC or ROMCC.
    
    Change-Id: I9fe831a215736462e8b3f4b96ffe231133ecf79b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/347
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d3edd9abe97af9e405f0695276d430ac16d98796
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Oct 28 21:26:16 2011 +0200

    T60: remove redundant usbdebug_init call()
    
    called from console code, no need to call it here.
    
    Change-Id: I4c34f89c82cc2478db8de4e98584e69d7ab0ca82
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/350
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b15975bf5a4a1b9ed4d83e2c8caf622d71a7e4d5
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 21 12:57:59 2011 -0700

    copy e7501 component to e7505
    
    Change-Id: Ie69a6b6a040a8b0e7693083b3a2d13c327a165b3
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/310
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 94a458626a9f12aa670926d633f445bebc1fb63c
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Oct 25 14:32:21 2011 -0700

    Prevent multiple inclusions of object files and rules
    
    This removes 54 make warnings from the build
    
    Change-Id: I94ac9875526febe2f95334c1c3971641c1d27f8f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/338
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ea5c2b62caec8a2acd5298777b825b799e2b9c15
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Oct 27 18:42:53 2011 +0200

    Fix checksum calculation both in romstage and ramstage.
    
    The earlier fix for CMOS checksums only fixed the function rtc_set_checksum,
    which would fix the checksum, but then coreboot would no longer honor the
    settings because it assumed the checksum is wrong after this.
    This change fixes the remaining functions.
    
    Change-Id: I3f52d074df29fc29ae1d940b3dcec3aa2cfc96a5
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/342
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 113c3497201a28fd58335788da5e206ea8902b90
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Thu Oct 27 20:42:11 2011 +0200

    Add support for AMD IMC controller.
    
    This patch adds support to dump SIO like interface of AMD Embedded Controller
    in the SB7xx and SB8xxx southbridges. Parts of the register interface are
    documented in SBxxx RRG BDG.
    
    Change-Id: Ib2ccaa3dfe33cfa8e7cba19d8ab0798286ad2f92
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/343
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 9bfa1c8c68b2f0c11e516e3f45ff1901a5907ab6
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Fri Oct 14 02:16:48 2011 +0200

    Added smbus block read/write for amd8111
    
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Change-Id: I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc
    Reviewed-on: http://review.coreboot.org/281
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 07b4215e11537bcbef3848bb520fa201fbcc4eda
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Oct 14 23:02:57 2011 +0200

    Move linux 2.6.11 workaround to generic code
    
    Linux 2.6.11 seems to require a certain order in CPUs listed in mptable,
    so enforce it. This was only done on arima/hdama, but now is generic.
    Unfortunately this is somewhat slow.
    
    Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/280
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e572ef6136114c3cac09b061c6888e44d39d36a5
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Oct 27 13:10:14 2011 +0200

    X60/T60: enable AHCI mode
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Change-Id: I2166ae9ee9e7e0e431583249f015d130d15fac61
    Reviewed-on: http://review.coreboot.org/341
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b2f173e168b5a368eab138a22be5524159532c63
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Oct 27 13:05:40 2011 +0200

    i82801gx: Fix port status in AHCI mode
    
    The code used PCI register 0x92 to enable sata ports,
    which is wrong. The ICH7 documentation states:
    
    "This register is only used in systems that do not
    support AHCI. In AHCI enabled systems, bits[3:0] must
    always be set (ICH7R only) / bits[2,0] must always be set
    (Mobile only), and the status of the port is controlled
    through AHCI memory space."
    
    Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write
    0x0f for both variants. This patch makes sata_ahci work on
    my Thinkpad T60 and X60s.
    
    Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/340
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 5e4e2290b653b068b1ca55205efd3fbfcc1fda34
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Oct 25 12:28:40 2011 -0700

    Add -Werror to xcompile's testcc
    
    If -Werror is not specified, tests for certain compiler flags
    will emit a warning, which makes the build break since we compile
    with -Werror.
    
    Change-Id: I7be56530ff9f94e5500bad226c83e47145a808d7
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/336
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit bbfc9c449f61fc553bdea797b2f77af9d9420ccf
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Oct 25 14:15:57 2011 -0700

    Fix libpayload speaker driver
    
    The frequency for the PC speaker has to be specified as
    1193180 / frequency according to http://wiki.osdev.org/PC_Speaker
    
    Change-Id: Iaca9d45807e080efe834611e719b350680b5fb90
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/337
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6eb8bef25e6ab4d44b0f0549a12b05bde943dcae
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Oct 23 16:57:50 2011 +0200

    X60: enable Cx power saving modes
    
    Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/331
    Tested-by: build bot (Jenkins)

commit f02c396f2665396817b78cdfb1f662e26b952a65
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sat Oct 22 13:41:28 2011 +0200

    T60: add _CST table
    
    Used by power management code to enable Cx powersaving modes.
    
    Change-Id: I02c6b10762245bc48f21a341286236e203421de0
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/322
    Tested-by: build bot (Jenkins)

commit d2bc117f7957155da9587de6a4deebb6a101f2c6
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Oct 23 16:36:22 2011 +0200

    T60: enable C4onC3 mode
    
    It is safe to enable this setting on these Boards.
    
    Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/330
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fe40c5067e8698b4322712a4c06b6665ae153170
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Oct 23 15:54:31 2011 +0200

    T60: use ICS954309 clock driver
    
    Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/328
    Tested-by: build bot (Jenkins)

commit f488165a3de4da61626b27d8a1c250a0d303eee0
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Oct 23 15:53:47 2011 +0200

    Add driver for ICS954309 clock generator
    
    Change-Id: Iac7e91cdd995dad1954eaa2d4dd52bffa293fc95
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/327
    Tested-by: build bot (Jenkins)

commit 906f9ae784b8a593319c400cbcc5e555a29b4128
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Oct 23 16:35:01 2011 +0200

    i82801gx: Add setting for C4onC3 mode
    
    If this bit is set, ich7 will enter C4 mode if possible instead of
    C3. See ich7 specification (LPC controller, Power management control
    registers) for more details.
    
    Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/329
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 54600970417fee0e87d3059f6e6ac0a59d829066
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sat Oct 22 13:41:16 2011 +0200

    SPEEDSTEP: write _CST tables
    
    Change-Id: Idb4b57044808918de343d31519768d0986840f01
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/321
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0b86c76cfc13e435b4d5225326a1c71e154299cd
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Oct 21 21:46:47 2011 +0200

    ACPI: Add function for writing _CST tables
    
    Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/312
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d17f3d7019b84123ec2144af6fbb5f4145f0d32c
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Wed Oct 19 02:24:23 2011 +0200

    w83627hf: correct typo in ASL include, correct indexed registers and remove unneccesary _PR0 defs
    
    Correct a typo in devtree.asl which causes AML processors to fail executing
    the DSDT with AE_NO_MEMORY or (in case of acpiexec) Divide By Zero.
    Also removes an superfluous item in the register IndexField and removes
    unneccessary _PR0 definitions which could confuse AML processors.
    
    Change-Id: I02cb9ce4e8f2101cfff8cec4abba7e070fd66364
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/296
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d0ea6789e6e07fc9611be157e178df53ec5500e4
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Oct 25 15:29:47 2011 +0200

    Lenovo H8: Fix h8_set_audio_mute()
    
    Logic is inverted (if argument is true, one would expect that
    mute is enabled) and the wrong bit was used (1 instead 0)
    
    Change-Id: I71133ba639f1fb0d3c3582f16211dd266a11cc64
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/334
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2b1fbbbc897af573af66f48d75862559334f7055
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Oct 25 15:31:26 2011 +0200

    X60/T60: remove superflous h8_set_audio_mute()
    
    muting is handled by h8 code, no need to do it here.
    
    Change-Id: I3f152e99f30701cd032b03105cbe3ae778865305
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/335
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 718afbed824ea802564ed5b766e799e2d051bc74
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Oct 23 15:36:15 2011 +0200

    i82801gx: Add write and read/write block functions
    
    Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/326
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a1e4824f73602a411826b27160a8818049ce0f97
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 21 14:24:57 2011 -0700

    Various fixes to cbfstool.
    
    - add ntohll and htonll (as coreboot parses 64bit fields now)
    - use the same byte swapping code across platforms
    - detect endianess early
    - fix lots of warnings
    - Don't override CFLAGS in Makefile
    
    Change-Id: Iaea02ff7a31ab6a95fd47858d0efd9af764a3e5f
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/313
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3c976791b06c75e8983266b3551f133d89924376
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Oct 23 15:30:29 2011 +0200

    i82801gx: Don't set I/O base address to static value
    
    Doing it this way will break all subsequent smbus calls, because
    the smbus code still uses res->base, which points to the old base
    address. Fix this by allocating a proper resource.
    
    Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/325
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
    Tested-by: build bot (Jenkins)

commit fc204c5a72c41e3e435a3e93b1d7a5e352018221
Author: Thomas Gstädtner <thomas@gstaedtner.net>
Date:   Fri Oct 21 22:01:32 2011 +0200

    FILO: Pass LIBCONFIG_PATH variable to FILOs make
    
    This fixes the build for HEAD/master.
    Current stable will not work, because it is too old for recent corboot.
    
    Change-Id: I9dfd5de472d4f58f07147cb9b9bb0b543f228561
    Signed-off-by: Thomas Gstädtner <thomas@gstaedtner.net>
    Reviewed-on: http://review.coreboot.org/311
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 616da1ee7fc45bed76e420fb5060939ef0d77ea1
Author: Marc Jones <marcj303@gmail.com>
Date:   Fri Oct 7 17:20:30 2011 -0600

    Allow XGCCPATH to be set on the make command line.
    
    The xgcc toolchain may be moved by the user and passed in on the commandline. Updates the Makefile and the xcompile script.
    
    Change-Id: I05797b2cabce39bdd7868c2515f30d34043fc8cc
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/318
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5cfd583c5c2d803dd240768ec343b5a95f42c785
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Sun Sep 18 22:54:51 2011 +0200

    console: support integrated 7-segment displays for POST codes
    
    Add a configuration option POST_PORT which defaults to 0x80 and
    can be redefined by boards which have integrated POST displays
    on another I/O port. Change post.c to output POST codes to this
    port instead of 0x80 hardcoded.
    
    Change-Id: I8f8e820f8c75641b35e7249bf622b63a3604b9f3
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/221
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f3b0500050050e4f103e42fdcf111af232fa874b
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Wed Oct 12 12:06:23 2011 +0800

    SB800: Hide unused gpp ports
    
    Add configure option SB_GPP_UNHIDE_PORTS for mainboard
    to hide/unhide the unused sb800 gpp ports.
    Certain gpp port should be hidden, if no device was detected and
    hotplug feature is disabled for such port.
    Hidden unused ports makes lspci -vvv get more accurate information under Linux.
    Test on avalue/eax-785e mainboard.
    
    Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/207
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d7ecfa7c152da59cf76b5dfd8ff4ef1313a74260
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 21 14:37:52 2011 -0700

    Fix CMOS checksum calculation in libpayload.
    
    Change-Id: I64ea53fa098fbcfc76e0ebd5f049a2ee3d0a1024
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/314
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 1c795ad109bd382ff75e92d83f5721b8ed7c3be1
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 14 12:49:41 2011 -0700

    Add ifdtool, utility to read / modify Intel Firmware Descriptor images
    
    Change-Id: Ie78b97bf573d238d0dff9a663e774deb1b7dea44
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/272
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c31c4de681738fc264333cb12aecdb995b119a94
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 17 08:58:27 2011 -0700

    nvramtool: Fix CMOS checksum to match coreboot (and /dev/nvram)
    
    Change-Id: I28b0dbad36403a31be83581107f40b3ca1332dcc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/287
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d1bc331855caab351a70676b5085787292a45fea
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 22 16:39:19 2011 -0700

    Extend coreboot table entry for serial ports
    
    Add information about memory mapped/io mapped base addresses.
    
    and fix up libpayload to use the same structures
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb
    Reviewed-on: http://review.coreboot.org/261
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b6010b8e70c25f93773bc464457f69fd4bb8a82e
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Fri Oct 21 18:41:44 2011 +0300

    Remove redunancy in Kconfig
    
    Socket Kconfig unconditionally selects CPU_INTEL_CORE.
    
    Change-Id: I5eb7dd17047a2a031dd7345390d7f5f756055e18
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/307
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit cc97c560bbddbaf11b79c6cb3257f41d245e26dc
Author: Thomas Gstädtner <thomas@gstaedtner.net>
Date:   Fri Oct 21 17:40:42 2011 +0200

    FILO: Change FILO Makefile.inc from SVN to GIT
    
    This commit replaces the old svn checkout code for the external FILO
    payload with a git checkout for the new repo on gerrit.
    The stable checkout is implemented similarly to the former SVN variant,
    it checks out a specific commit (same commit as svn r136 which was
    checked out before).
    The HEAD checkout gets the master branch from
    http://review.coreboot.org/p/filo.git
    In future this should probably be changed to a stable tag or repo.
    It is necessary to remove the old svn checkout by hand (or run
    distclean), because I did not include code to remove an existing svn
    FILO checkout.
    
    Change-Id: I08a703f3428ae7b987f7079a4901be4cf6d7e505
    Signed-off-by: Thomas Gstädtner <thomas@gstaedtner.net>
    Reviewed-on: http://review.coreboot.org/308
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit eb7a900f63752517ba6e6378215cdc34bcd1c0dc
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Oct 21 15:45:09 2011 +0200

    libpayload: fix bulk transfers on OHCI controllers
    
    Time for the brown paper bag: OHCI controllers are not happy when
    told to send data, but with obviously wrong addresses. It helps
    to write the addresses into the data structures.
    
    Change-Id: Ic0967dc8939e64af119cfb89400a045a2c077171
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/306
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1465385db027bfe42ce420b551819f6d63a6cc88
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Oct 21 13:56:04 2011 +0200

    sch: strip quotes around cmc.bin filename
    
    This was mentioned several times already, how about we get it in?
    It avoids cbfstool to fail because path/to/"file" doesn't work.
    
    Change-Id: Ia01acbd78f81a5db890fd1573a2f3cbe1450562f
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/305
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 02e75b2b67285111dc41e1a201ba49b20905f18b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Mon Oct 17 09:51:15 2011 -0700

    Use ntohll where appropriate.
    
    also clean out a local copy of ntohl in yabel.
    
    Change-Id: Iffe85a53c9ea25abeb3ac663870eb7eb4874a704
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/288
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 9ea33e9318cfec6fca403b663618cbfbfa9e1e96
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 14 15:11:16 2011 -0700

    Add macros for 64bit byte order swapping
    
    Change-Id: Ic31ccd41ba3e0af7046eafc29221810d4cd196c8
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/275
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b5381105325391553b17c6ec2455233fc27e73b8
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sat Oct 15 17:31:01 2011 +0200

    T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
    
    Those modules have basically the same Super I/O capabilities as
    the Docking station. Unfortunately, the Super I/O in the module
    shares the same I/O address as the Docking station, so we're not
    allowed to connect the LPC Docking Bus if such a module is present.
    
    To be able to detect this device and use it as early console for
    coreboot, we have to initialize the GPIO Controller before, as
    this device is detected via GPIO06.
    
    Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/282
    Tested-by: build bot (Jenkins)

commit 2588db496d8037c9e548a9dd75360a3785b0ae7f
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Oct 17 17:37:45 2011 +0300

    i82801dx: Replace romstage printk's
    
    Patch is required to compile this with romcc.
    
    Change-Id: I5c4c0f5b32e5edeb8c48d8455b3493ca79f8b452
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/291
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 096161a5e44a9104083794c5950ea3cc2108dfb0
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Oct 18 05:10:36 2011 +0200

    asrock/e350m1: Enable the superio ACPI device in devicetree.cb
    
    This makes the power_on_after_fail NVRAM option work correctly.
    
    Change-Id: I96f05f82d7f133b343cf8d4ef09db50a3db7a83d
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/292
    Tested-by: build bot (Jenkins)

commit 939103c622ea9f9be32675643373a0d99aaba2b2
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Wed Oct 19 07:23:51 2011 +0300

    IOAPIC: fix bitmask
    
    APIC ID is bits 27..24, not 19..16.
    
    Change-Id: Ib53a480bf4328901094ca2c4713e8317321962a1
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/299
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 76c44aeea997044b85442681094d2315ceb1087b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 14 12:41:46 2011 -0700

    sconfig: check whether component directory actually exists
    
    and add drivers/generic/generic back (empty), since it is used by many
    devicetree.cb files.
    
    Without this patch typos in component names in devicetree.cb cause
    the component to be silently ignored.
    
    Change-Id: I3cfca2725816f0cd7d72139ae53af815009e8ab4
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/270
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 6a113331339dbddca16a832dca26fa3dd68de48b
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 14 10:29:21 2011 -0700

    Drop eh_frame instead of moving it into the image.
    
    That's what SeaBIOS does, too, and it works just fine.
    
    Change-Id: I3e17c15848aca86f775fc86f4ad906c820625887
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/269
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 5563959b0966284341e27e0b1eab3a7353c81673
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Oct 18 07:58:10 2011 +0200

    I945: replace #if defined() by #if
    
    config.h defines also unset config options (as "0") so #ifdef
    matches both settings, which isn't what we want.
    
    Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/293
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 19fd2112f777054d9cfb4999ed9616d3460eaa76
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Sun Oct 16 18:12:59 2011 +0300

    Append logical PME/GPIO device. Fix MPU device number.
    
    A mainboard may require configuration of the superio pins to fully
    support some features. Things like A20# gate, leds, fans, infra-red
    and bootstrap jumpers may be configured and controlled through the
    logical PME device.
    
    Change-Id: I6e77ff0295806ba3dff339013f73d99c2961388f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/289
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 521d8c25734dcfd38fa2e17a416e587fccb96080
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date:   Mon Oct 17 17:10:03 2011 +0300

    Activate older Xeon P4 microcodes
    
    As new microcode files were included, the table was not updated with
    families 0f25 and 0f26.
    
    Change-Id: I5bb8be9d7c37eb8406dcb48a4b933eab24639bda
    Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Reviewed-on: http://review.coreboot.org/290
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d87dfc0c389563e4bac3c2726adce4f4800aad06
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 14 15:24:03 2011 -0700

    Fix our CMOS checksum algorithm so it matches what /dev/nvram expects
    
    Our cmos checksum is inverted to what the Linux /dev/nvram device expects (and
    BIOSes use). This makes it impossible to use /dev/nvram with coreboot. Fix it!
    
    Change-Id: I239f7e3aca05d3691aee16490dd801df2ccaefd1
    Signed-off-by: Vadim Bendebury <vbendeb@google.com>
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/279
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 1babddb202478c88813ee94911ee5576773e8d96
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 14 15:22:52 2011 -0700

    rework RTC driver output to make it more consistent.
    
    Also add a meaningful define (Not hooked up in Kconfig, that might
    or might not follow)
    
    Change-Id: I9cc4bca0d23d75e6a1d767932ec62e8c68b39d71
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/278
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit fbadc499a6268f5d69d4aa1844153d6ae1e82cf0
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 14 12:44:14 2011 -0700

    cbfstool: improve error messages
    
    If a file can't be added by cbfstool, print the type and name of the file
    in the error message.
    
    Change-Id: I369d6f5be09ec53ee5beea2cfea65a80407f0ba3
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/271
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit a9a8b801911ec7ebd1163c757bcec2635af5a641
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Tue Oct 4 22:34:11 2011 +0200

    Re-worked devicetree.cb for DL145 G1
    
    After a lot of experimentation this commit improves some hardware
    features that were not recognized or incorrectly configured before.
    The only thing not tested is SCSI-option board (I dont have one).
    Misleading errors in comments have been corrected.
    (Note BTW that the DL145 G1 mainboard is identical to AMD Serenade
    which was supported in early versions of coreboot but was dropped
    for some reason.)
    
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Change-Id: Ibbd97fafad22196b1e18d0b257731490339f113e
    Reviewed-on: http://review.coreboot.org/237
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit e2c05da300037e6d92bbb833f945ab05421978e5
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Thu Oct 6 18:43:43 2011 +0200

    Fixes several issues with amd k8 SSDT P-state generation
    
    First issue fixed:
    For multi-socket CPU the current implementation emitted
    Processor objects for cores in the first CPU only. This
    commit fixes the bug by really emitting one Processor
    object for each core. However, the unlikely case of mixed
    CPU models is still not handled correctly.
    
    Second issue fixed:
    One loop was wrong in case a processor in the table declares
    no P-states at all. The rewritten loop is safe. Some possibly
    dangerous array lengths were also fixed.
    
    Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV
    according to the BKDG. The current implementation always set it
    to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS.
    
    Fourth issue: If a processor without PowerNow! support was inserted in a
    system with coreboot configured with SET_FIDVID then the boot process hanged
    mysteriously and very early. Apparently because init_fidvid_ap tampers with
    non-existing registers. This commit fixes the bug by bailing out
    from init_fidvid_ap if PowerNow! capability is missing.
    
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417
    Reviewed-on: http://review.coreboot.org/239
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3128685a918ee9c67a50f9753874b794008c8607
Author: Stefan Reinauer <reinauer@google.com>
Date:   Sat Oct 15 11:23:04 2011 -0700

    SMM: Move wbinvd after pmode jump
    
    According to Rudolf Marek putting a memory instruction between
    the CR0 write and the jmp in protected mode switching might hang the
    machine. Move it after the jmp.
    
    There might be a better solution for this, such as enabling the cache, as
    keeping it disabled does not prevent cache poisoning attacks, so there is no
    real point.
    
    However, Intel docs say that SMM code in ASEG is always running uncached, so
    we might want to consider running SMM out of TSEG instead, as well.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Change-Id: Id396acf3c8a79a9f1abcc557af6e0cce099955ec
    Reviewed-on: http://review.coreboot.org/283
    Reviewed-by: Sven Schnelle <svens@stackframe.org>
    Tested-by: build bot (Jenkins)

commit 1377491ac7a7bb75d6834bf79a219fd8ae1c03cd
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 14 15:19:21 2011 -0700

    use byteorder.h instead of implementing another byte swap function
    
    Change-Id: Id5fe7b597256ddf5d4ef408ec82cd94d84e7a0cd
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/277
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 328a694a3f2055c5e6a88ae51c9a8eefb61fd11c
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Oct 13 17:04:02 2011 -0700

    AMD CPU and chipset fixes for compilation with gcc 4.6
    
    Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/266
    Tested-by: build bot (Jenkins)
    Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

commit ab87254b6130d74f080e2c5ee9abb4570560e6a0
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 14 15:18:29 2011 -0700

    use acpi.h include instead of manually adding acpi_slp_type.
    
    Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/276
    Tested-by: build bot (Jenkins)
    Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

commit 2d172993953ae777aaec13efddfe6ed91209bd02
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 14 14:50:19 2011 -0700

    cbfs_and_run_core() is not part of the API, make it static.
    
    It's only used in cbfs_and_run.c
    
    Change-Id: Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/273
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit f830752c87095e7e5711aed9f13e30477182a4a7
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Fri Oct 14 15:09:25 2011 -0700

    reformat Makefile.bootblock.inc (>80 lines per char)
    
    Change-Id: I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/274
    Tested-by: build bot (Jenkins)
    Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

commit 971ebd8ee6de9ac30b208da53862918e506ac5e7
Author: Stefan Reinauer <reinauer@google.com>
Date:   Thu Oct 13 17:26:43 2011 -0700

    Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6
    
    Change-Id: I672135a9b6e3b641ceb655cb00d40ee760c17edc
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/268
    Tested-by: build bot (Jenkins)
    Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

commit 86fc9848ae781fca8c7013e785f467d602152395
Author: Stefan Reinauer <reinauer@google.com>
Date:   Thu Oct 13 17:26:10 2011 -0700

    Fix compilation of AMD GX2 northbridge code with gcc 4.6
    
    Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/267
    Tested-by: build bot (Jenkins)
    Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

commit 89fcdec9721231a2a6faf96462359bb9a2cdda63
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Oct 13 17:03:04 2011 -0700

    Fix compilation of VIA CN700 northbridge code with gcc 4.6
    
    Change-Id: Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/265
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b9d60c9ac8f878ebd5a69a0f87d9a9406b89c606
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Oct 13 16:53:11 2011 -0700

    fix compilation of intel/sch northbridge code with gcc 4.6
    
    Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/264
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 499af708ca6811843d33e8cc23f01fe7ce08c948
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Oct 13 16:52:27 2011 -0700

    Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6
    
    Change-Id: I347dd84a61244eed145c02a080309d5a34c5394a
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/263
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 513eb5a9568261e5f1fc5b7cb7cbc129cda0f943
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 1 14:04:50 2011 -0700

    Prevent build breakage without consoles enabled
    
    If all console types are disabled, coreboot will fail to compile because
    static code is unused. This patch fixes the issue.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Change-Id: Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2
    Reviewed-on: http://review.coreboot.org/260
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 71496bea9b84b0d4c0d3576932d72f92b4c6881a
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Jun 1 14:01:46 2011 -0700

    Load an IDT with NULL limit
    
    Load an IDT with NULL limit to prevent the 16bit IDT being used
    in protected mode before c_start.S sets up a 32bit IDT when entering
    ram stage.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Change-Id: I8d048c894c863ac4971fcef8f065be6b899e1d3e
    Reviewed-on: http://review.coreboot.org/259
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit d17fe51d9a9402dfdc1b6b633e52a7bf8e757949
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Oct 4 10:34:37 2011 -0700

    Fix compilation of x86emu with gcc 4.6.x
    
    gcc 4.6 complains about unused but set variables in x86emu.
    Particularly some variables are always set but only used in
    debug mode, or when FPU support is enabled.
    
    Change-Id: Ic53bd2303171ab717eb2d2c0ed72744d3eb6989e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/258
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit b6b8871dd3beaf2e39fdb854903466afe041eabc
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Oct 12 14:35:54 2011 -0700

    Fix native x86 option rom initialization
    
    - Intel option roms want an initialized i8259 or they will
      throw an exception 6. This should be done in the southbridge
      code, but that is executed much later than the VGA init, so
      initialize the i8259 in src/devices/oprom/x86.c.
      In the long run this will allow getting rid of some of the
      ugly hacks in some AMD boards' romstage.c
    - Don't overwrite the mode when copying mode info information back
      from 0x600.
    
    Change-Id: Idb01f13dbcd736d8d830b222ffe1ea85799fcd9c
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/257
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit c1efb9038402af268a0a25957ac236d047b21f22
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Oct 12 14:30:59 2011 -0700

    refactor vesa mode setting code and bootsplash code
    
    - adds possibility to set a vesa mode without showing a bootsplash
    - make bootsplash / mode setting code available in real mode.
    
    Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/256
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 216fa4633a583fcc278186e1f927f32332d1e5c5
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Oct 12 14:25:07 2011 -0700

    Refactor option rom initialization code in coreboot.
    
    - move int15 handler out of the generic code into the mainboard directories
      of those mainboards that actually use it.
    - move vbe headers to vbe.h
    - move function prototypes used in native oprom code to x86.h
    
    Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/255
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 491e2a29b9b29565f4023ac7ce32dbb5c284cb6e
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Tue Sep 27 16:26:05 2011 -0700

    Enable/fix compilation of i8254 code in ram stage.
    
    Change-Id: I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/254
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit af2c538ee5b3adae6a51bd0e5c725a6a18688554
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Oct 12 14:05:49 2011 -0700

    Update "STABLE" SeaBIOS selection to release 1.6.3
    
    1.6.3 has a lot of benefits over the previous version, the two
    most important being:
     - working AHCI support
     - compiles with gcc 4.6.x
    
    Change-Id: Ie3a4d8f2624e0aa85e48ca09da53474c085838db
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/253
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit a251dee1eeff3345e6498c6a90607d223acb9ae3
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Oct 13 01:18:29 2011 +0200

    Use default table creator macro for all SSDTs
    
    Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/262
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 8d427ece817bccbb15f4886cb2bf7734c1f4c3a2
Author: Stefan Reinauer <reinauer@chromium.org>
Date:   Wed Oct 12 12:54:08 2011 -0700

    Fix romstage creation with gcc 4.6 and CAR targets
    
    newer gcc versions generate ".section .text" instead of just ".text"
    in their assembler output. This patch makes sure that we don't end up
    with a superfluous ".section" that makes the build fail.
    
    Add -Wno-unused-but-set-variable to CFLAGS if the flag exists.
    
    Change-Id: I7f24c987433cc5886dde2af27498d3331cbda303
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Reviewed-on: http://review.coreboot.org/252
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4e2d542a64304a108b6ff5175966e78769979594
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Oct 6 15:24:08 2011 +0200

    siemens/sitemp_g1p1: Don't mess with virtual wire settings
    
    That function broke SMP on Linux 2.4, now it works.
    
    Change-Id: I4ddd25fef57bed64877959ca96cca68170042bca
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/243
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit c5ae30617a239f5fe13a8c5a7422b73938341fc1
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Oct 6 14:34:22 2011 +0200

    siemens/sitemp_g1p1: Get rid of bus_isa and bus_type
    
    Each variable is essentially unused or incorrect.
    
    Change-Id: I4d2a10c9b45306ac6e6026a31765d3b912fd855c
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/242
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 390a3374ca597ccd127eca0b8950d5051cd0e697
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Oct 7 14:43:27 2011 +0200

    amd/sb600: Enable COM2 at all times in early setup
    
    Otherwise with a coreboot log on COM2 (which doesn't work) the boot
    process takes eons.
    
    Change-Id: I886f98b715c1f384c8693f2977671ff15897b5a5
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/241
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit b0a9c5ccf31514630755e9a5d15204a55a47740f
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Oct 7 23:01:55 2011 +0200

    mptable: Refactor mptable generation some more
    
    The last couple of lines of every mptable function were mostly
    identical. Refactor into common code, a new function mptable_finalize.
    
    Coccinelle script:
      @@
      identifier mc;
      @@
      (
      -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
      -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
      -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
      -return smp_next_mpe_entry(mc);
      +return mptable_finalize(mc);
      |
      -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
      -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
      -return smp_next_mpe_entry(mc);
      +return mptable_finalize(mc);
      )
    
    Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/246
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit c75c79bd0269fec41714fad1899f12e6463d93d8
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Oct 7 22:41:07 2011 +0200

    mptable: Get rid of fixup_virtual_wire
    
    As stated in some code files, fixup_virtual_wire was established
    to avoid touching 200 invocations of the mptable code.
    
    Let Coccinelle do it:
      @@
      type T;
      identifier v;
      @@
      -void fixup_virtual_wire(T v)
      -{ ... }
    
      @@
      expression A;
      identifier v;
      @@
      -v = smp_write_floating_table(A);
      +v = smp_write_floating_table(A, 0);
    
      @@
      expression A;
      identifier v;
      @@
      -v = smp_write_floating_table(A, 0);
      -fixup_virtual_wire(v);
      +v = smp_write_floating_table(A, 1);
    
    Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/245
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 6eb7a5316963cb0285fe86286c47491fd213a36b
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Oct 7 21:42:52 2011 +0200

    mptable: Refactor lintsrc generation
    
    We copied pretty much the same code for generating mptable entries for
    local interrupts (with some notable exceptions).
    This change moves these lines into a generic function "mptable_lintsrc"
    and makes use of it in many places.
    
    The remaining uses of smp_write_lintsrc should be reviewed and replaced
    by mptable_lintsrc calls where possible, and smp_write_lintsrc made static.
    
    This patch was generated using Coccinelle:
      @@
      expression mc;
      expression isa_bus;
      @@
      -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
      -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
      +mptable_lintsrc(mc, isa_bus);
    
      @@
      expression mc;
      expression isa_bus;
      @@
      -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
      -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
      +mptable_lintsrc(mc, isa_bus);
    
      @m@
      identifier mc;
      expression BUS;
      @@
      -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin));
      ...
      -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
      -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
      +mptable_lintsrc(mc, BUS);
    
    Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/244
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3a1fe9dec1d4758fd9c5c52f93c4efb5956f3c33
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Wed Oct 12 22:11:40 2011 +0200

    Make Asus A8V-E SE better ACPI citizen.
    
    Use the SSDT autogen infrastructure to support the automatic reserved resources,
    automatic P-state generation and automatic _CRS PCI0 method.
    
    Change-Id: Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/251
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8ae574c805584997f4fe2a39ec852a7de2a3233c
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Sun Sep 18 22:53:18 2011 +0200

    w83627hf: ASL include containing virtual device tree of the SuperIO
    
    Add a ACPI Source Language snippet to superio/w83627hf which maps the
    SuperIO and most of the logical devices to PnP devices, exposing
    configuration options and chip power management to the OS.
    Written using the Winbond W83627HF/F datasheet.
    
    Change-Id: I1108d29b341ef78fe7f1e574f98b680aada39daf
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/223
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 80311eab8c2cf9b57a354d7d5bc5e7a5f75c238a
Author: Christoph Grenz <christophg+cb@grenz-bonn.de>
Date:   Sun Sep 18 23:20:55 2011 +0200

    amdk8: ASL include for K8 temperature sensor support in ACPI
    
    Add a ACPI Source Language snippet which if included as
    shown in the comments in the file, exposes the 4 possible
    temperature sensors in the CPU as ACPI thermal zones.
    
    Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339
    Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
    Reviewed-on: http://review.coreboot.org/222
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 55437c57a967e73b8a78147c30779a6b7d39872b
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Wed Oct 12 11:42:59 2011 +0800

    SB800 RAID: add kconfig option RAID_MISC_ROM_POSITION
    
    SB800 RAID ROM require to put the misc ROM to specific position,
    this patch enable user to put the RAID misc ROM to the right place
    in the coreboot image.
    
    Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Signed-off-by: Kerry She <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/249
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 0e6344e1cfe0bad409a4a0bfacbaa92a57440aa7
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Wed Oct 12 11:42:59 2011 +0800

    SB800: Sata Enable bus master and enable ahci for AHCI/RAID mode
    
    In order to make sure AHCI/RAID ROM works correctly
    For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should
    enable bus master and the ahci also should be enabled.
    
    Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Signed-off-by: Kerry She <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/248
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 56ed40acb2d76c51c36e2ebbc12cf75b97225ade
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Oct 11 17:27:26 2011 +0800

    avalue/eax-785e: Get SATA Mode from Kconfig option
    
    Change-Id: I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/233
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit d7e856b9cb585777db591afa8d68317271d5aff5
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Oct 11 17:27:06 2011 +0800

    sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODE
    
    Add this option to enable/disable SATA IDE Combined Mode feature
    
    Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/231
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 2c7c37a01615a8435d13bd0a027ecc9b5985d7a8
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Tue Oct 11 17:27:00 2011 +0800

    persimmon: complete the sb800 devicetree
    
    sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
    enable_dev() function. If the devicetree don't have this device,
    then sb_Before_Pci_Init will not get called.
    So the missing sb800 USB3 devicees was add to the mainboard devicetree.
    Because of no physical usb connector connected to USB3, the USB3 device setting was off.
    
    Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/232
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 5f145faff88ac6a0951277142e8b4f8116ae79de
Author: Marc Jones <marcj303@gmail.com>
Date:   Thu Oct 6 16:38:35 2011 -0600

    Don't do a call as the first instruction in libpayload.
    
    Doing a call before the payload has set up its stack is risky. The stack may
    not be in a favorable location. Normally this is not an issue with coreboot
    or other well behaved callers.
    
    Change-Id: Ie6f6748a471324b29ebad045c807dfc9f4b92034
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/240
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 07bf9119310ceece5a6c76907004bc96af1a38cc
Author: Oskar Enoksson <enok@lysator.liu.se>
Date:   Thu Oct 6 18:21:19 2011 +0200

    Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E
    
    AMD K8 rev F and later implements a bit SYSCFG_MSR_TOM2WB to
    mark dram memory above 4GB as WB. However, AMD K8
    rev E and earlier don't implement this bit and therefore need
    MTRR spanning dram memory above 4GB. The current implementation
    of amd_setup_mtrrs never generate MTRR above 4GB.
    This caused memory > 4GB not to be recognized in e.g. Linux on those
    rev E or older platforms. This commit should fix that bug.
    
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Change-Id: Ie568a52a8eb355969c86964d5afc4692e60f69c1
    Reviewed-on: http://review.coreboot.org/238
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 75df1062a1438c40bc94021982fd389848f1d7fc
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Mon Oct 10 19:19:46 2011 +0800

    mainboard: complete the sb800 devicetree even device is off
    
    sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
    enable_dev() function. If the devicetree don't have this device,
    then sb_Before_Pci_Init will not get called.
    
    Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/230
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 4e9c4c8cc25347693a19aef0201ba2065e3d816f
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Mon Oct 10 18:23:49 2011 +0800

    sb800: sata combine mode configure fix
    
    Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to
    configure SataIdeCombinedMode is wrong.
    
    sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller
      0: IDE controller is exposed and Combined Mode is enabled.
         SATA controller has control over Port0 through Port3,
         IDE controller has control over Port4 and Port5
      1: IDE controller is hidden and Combined Mode is disabled,
         SATA controller has full control of all 6 Ports when operating in non-IDE mode
    
    Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/229
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 1386fa747d0914307432d3918706ab1e9e2bfc23
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Mon Oct 10 18:13:51 2011 +0800

    persimmon: sb800 sata mode configure update
    
    persimmon configure sb800 sata mode according to the
    southbridge kconfig selection.
    
    Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/227
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit d4a0e7d0b685387f6b9bf7ac8727d4a5ea7c75bf
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Mon Oct 10 17:17:39 2011 +0800

    sb800: Add sata ahci/raid mode kconfig option
    
    If sb800 sata was configured as ahci or raid mode,
    give the option to add ROM files.
    
    Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/225
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit f8adf7a129e6746a558d6f6e1c29045746c93cde
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Thu Sep 22 18:52:35 2011 +0800

    pci_ids: Add sb800 SATA device raid mode device id
    
    sb800 SATA device have different device id with different configure
    mode, 4392h for RAID mode, 4393h for RAID5 mode
    
    Change-Id: If54f7751f531c94ee725309a2a5c255390935ead
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/226
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit af90275a41169fa16459ce13b729ab2875199aa1
Author: enok71 <enok@lysator.liu.se>
Date:   Wed Sep 28 16:55:59 2011 +0200

    TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platforms
    
    The hp/dl145_g1 motherboard did not work since commit
    1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That commit added
    TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process
    stopped very early (no console output whatsoever). The same symptom was
    reported on other AMDK8 based boards with amd8111 southbridge chips. This
    commit seems to fix the bug. It adds a bootblock.c under
    src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the
    problem was that enum_ht_chains needs to be called before the southbridge
    bootblock.c function, not after.
    
    Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4
    Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
    Reviewed-on: http://review.coreboot.org/235
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 8eb4273290ea577d06282d350e3fe884145c4288
Author: QingPei Wang <wangqingpei@gmail.com>
Date:   Tue Sep 13 18:04:22 2011 +0800

    Add AMD Family 10h PH-E0 support
    
    the patch file comes from
    src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE
    /F10MicrocodePatch010000bf.c
    
    Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802
    Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
    Reviewed-on: http://review.coreboot.org/202
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 62ff00e13f3fb349bb8ce3065f6915448bfd875e
Author: Raymond Danks <raymonddanks@gmail.com>
Date:   Sat Sep 3 21:45:38 2011 -0600

    mkelfImage: Use -fno-stack-protector if supported by gcc
    
    Gcc 4.1 comes with an SSP https://wiki.ubuntu.com/GccSsp
    This is disabled to work around '__stack_chk_fail' symbol not found failures
    http://www.coreboot.org/FAQ/Obsolete#How_do_I_fix_stack_chk_fail_errors.3F
    
    The presence of -fno-stack-protector is tested for automatically by configure.
    
    Change-Id: I28ef158829f5935f985cfd5a5440733685cf479a
    Reported-by: Raymond Danks <raymonddanks@gmail.com>
    Signed-off-by: Raymond Danks <raymonddanks@gmail.com>
    Reviewed-on: http://review.coreboot.org/112
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 03f82bd787833db4c341a129a3329ea0aead6235
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Sep 20 22:36:32 2011 +0200

    Use ACPI text fields consistently with all other boards
    
    LXBIOS and LXB-DSDT are not used in other parts of the tree.
    Make names consistent across the tree.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43
    Reviewed-on: http://review.coreboot.org/224
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 8487229b91560935b5c829f47a7a44a0d91b2ea1
Author: Marc Jones <marcj303@gmail.com>
Date:   Fri Sep 16 17:06:17 2011 -0600

    Persimmon doesn't have HDMI so the GNB HD Audio should be disabled.
    
    Change-Id: Ic960fe09fbed2c8a31c7c9ac2c54f6c88efebed3
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/219
    Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
    Tested-by: build bot (Jenkins)

commit 96be74c7f68ee4fa17a432439a0ecc4a33c66715
Author: Marc Jones <marcj303@gmail.com>
Date:   Fri Sep 16 17:08:01 2011 -0600

    Enable SATA AHCI for faster boot with SeaBIOS.
    
    Change-Id: Ibd87422680350c112eabe1bb73b237031c3e9d6b
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/220
    Tested-by: build bot (Jenkins)
    Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>

commit d7a696d0f229abccc95ff411f28d91b9b796ab74
Author: efdesign98 <efdesign98@gmail.com>
Date:   Thu Sep 15 15:24:26 2011 -0600

    Persimmon updates for AMD F14 rev C0
    
    These are the changes for the AMD Persimmon mainboard
    required to support the update of the AMD Family 14
    cpu to rev C0.  There are many warning fixes; the agesa-
    wrapper.c file has been changed to fix the amdinitlate
    and amdlaterunaptask routines, and more.
    
    Change-Id: I6de43379a2819cea5169db5f21d4841f9a4942a7
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/137
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 83d59b945c677918f9fdb889b95acb2989639dfc
Author: efdesign98 <efdesign98@gmail.com>
Date:   Thu Sep 15 11:24:29 2011 -0600

    Build warning fix for AMD Family 12
    
    This trivial change adds a prototype to an existing
    header file to fix a build warning for the AMD family
    12 cpus.
    
    Change-Id: Ic666bfbef867d17607eaa0f59570aea987a31f93
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/218
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit d91c9b7e3cb9fdaeb9399a21907996130f3120bb
Author: efdesign98 <efdesign98@gmail.com>
Date:   Thu Sep 15 10:59:55 2011 -0600

    AMD Inagua platform updates
    
    These changes update the Inagua platform.  The changes
    include modifying the Kconfig to suggest video bios
    and ahci rom implementations, changing the dimm spd
    code to use the correct bus addresses, cleaning up the
    makefile a bit, and fixing a duplicate definition
    warning associated with the BIOS_SIZE value.
    
    Change-Id: Idab88dda48f08877dbbd2de3136bdf0e54e31247
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/136
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 2c66060169b5e1718406f58d1d7a270aea7b1b73
Author: efdesign98 <efdesign98@gmail.com>
Date:   Fri Aug 19 14:25:48 2011 -0600

    AMD Torpedo platform updates
    
    This update fixes warnings and supports as necessary
    the Agesa infrastructure changes required to support
    the AMD Family 14 cpu update to rev C0.
    
    Change-Id: Ib08b49695b925b81f796bf299141fe6f845fdef8
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/138
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 4d2d5d5b3e661683ab209d068ab7537332fe15f9
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Sep 14 19:34:13 2011 -0600

    AMD Agesa macro expansion fix
    
    This change fixes the use of a macro that was
    previously modified to fix a warning.  The macro
    was used in a manner that doubly incremented a
    pointer.  The pointer increment was removed from
    the macro call and moved elsewhere.  In addition,
    an unused macro was removed from both Family 12
    and Family 14 code.
    
    Change-Id: I577794bbc55d18f21170dda1d0bbdc6d776ce392
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/217
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 3c59158810a6cbf3b8caccb9ff9fbb4bfc669e97
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Sep 14 16:22:31 2011 -0600

    AMD SB800 early console use fix
    
    This change removes printk's that occur before
    console init is called.  In the best case, these
    would cause an extremely slow boot, and in the
    worst case would cause a complete post failure.
    
    Change-Id: I50388e71225e95db602aa45835c39126c1c920a3
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/216
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 0bcfff7908dca812b0544bcd949b6ffd129473f2
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Sep 14 15:52:09 2011 -0600

    AMD Agesa changes to fix F14 boot issues
    
    This collection of changes fixes a buffer addressing
    issue by removing one level of indirection, fixes an
    Agesa HT mailbox retrieval bug, and fixes a buffer
    location-by-signature issue.
    
    Change-Id: Ic8a8cb3f9abddd9ad59343a85dbbee5aa7633be3
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/215
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit 3f5ebd65339cc77619f04f58e77fb272b9ed4484
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Sep 14 13:47:17 2011 -0600

    AMD F14 Northbridge updates
    
    This change is warning and whitespace fixes in the
    northbridge code for AMD Family 14 rev C0 cpu update.
    This does not address warnings in the mainboard,
    Agesa, Cimx, or southbridge code.
    
    Change-Id: I7ee7018a292ebb2343c9b7986dd21227185879dc
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/134
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 99b6674bd25b39f5918a7e38a454632104f5f845
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Sep 14 12:04:16 2011 -0600

    Update to Asrock E350m1 for AMD F14 C0
    
    This updates the E350m1 Agesa wrapper code to fix an
    issue with AmdLateRunApTask.  It now passes the function
    parameter through to the Agesa routine.  There is also
    a change to the platform_cfg.h file that makes the
    definition of BIOS_SIZE dependent on whether or not
    it was defined earlier.
    
    Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/139
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 7b7b2c9ef97c79ed5f6d12b4fc386db08e0691c9
Author: Kerry She <shekairui@gmail.com>
Date:   Thu Sep 8 21:16:19 2011 +0800

    mainboard: add avalue/eax-785 ITX mainboard
    
    It's AM3 Socket, 880M + SB850 chipset, similar with advansus/a785e-i.
    Onboard device UART, VGA, SATA, PCI Slot, 2 X16 PCIe slot, 4 X1 Pcie
    slot, Lan, audio, PS2 keyboard/mouse and USB are verified.
    
    Change-Id: I483363f5ff9fbfc5cda2f0521660751212f3e326
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Signed-off-by: Kerry She <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/208
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 8c69b1d13b12a23d22de19b9de2e161e6064021c
Author: Kerry Sheh <shekairui@gmail.com>
Date:   Wed Sep 14 10:04:19 2011 +0800

    rs780: hide unused gfx ports and gpp ports
    
    Hide the unused gfx ports and gpp ports if they are not configured as hotplug.
    lspci -vvv will get more accurate information under Linux,
    tested on avalue/eax-785e.
    
    Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb
    Signed-off-by: Kerry Sheh <kerry.she@amd.com>
    Signed-off-by: Kerry Sheh <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/206
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit a25828dd0eaec09334ccbe05559d0e121e698b0d
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Sep 2 09:57:01 2011 +0200

    Provide mechanism to local additions to the build
    
    site-local/ is an optional directory for local additions to the build.
    If site-local/Makefile.inc exists it will be parsed and used.
    
    Use it to define VGA option roms, splash screens, extra rules to the
    tree...
    
    Change-Id: I0c6ee43ffa40e6c3f193db081ab551ab75bc7478
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/212
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 14b67f716da16bc132f3e564b0c06c2c9c565753
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Wed Mar 9 11:37:16 2011 +0100

    superiotool: Don't compile with -Werror
    
    Older libpci version have headers using 'long long' which isn't allowed
    in ANSI C. Since we cannot control the libpci version installed in the
    system nor in generall have complete control over system headers, simply
    skip using -Werror in our makefile.
    
    Change-Id: Ibc1e57bef033bf4971f4108d078222dcf168d5e3
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/210
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 9beb5df3c4c35ddefa35742633a7876852065fae
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Mon Jun 27 14:35:00 2011 +0200

    inteltool: fixed 64 bit build
    
    The inline assembly for cpuid() was 32 bit specific. Additionally a
    format string referencing a size_t argument wasn't using the %z length
    modifier.
    
    Change-Id: Iac4a4d5ca81f9bf67bb7b8772013bf6c289e4301
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/211
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 5782fee0e14557963149c47ad07cf1d235196f67
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Wed Mar 9 11:30:55 2011 +0100

    inteltool: Fixed building of position independent executables
    
    When building a position independent executable (PIE) EBX is used
    internally by the compiler to generate position independent address
    references so it cannot be used in the clobber list. Use the already
    existing code for the Darwin plattform for that case, too -- it'll
    preserve the EBX value.
    
    Change-Id: Ief6d4872b8cd990856a0e8227a88bb228782aced
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Reviewed-on: http://review.coreboot.org/209
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit c2300581997be3e52e1fdab49fc0a9c322c4f27c
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jul 12 11:40:29 2011 +0200

    libpayload: Add get_option_from()
    
    This function allows reading the nvram configuration table from
    locations other than the cbtable.
    
    Change-Id: I56c9973a9ea45ad7bf0185b70d11c9ce5d0e0e1b
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/213
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit e169f82edf661ee922215ffe7fc6f413c7fa9181
Author: QingPei Wang <wangqingpei@gmail.com>
Date:   Tue Sep 13 13:35:43 2011 +0800

    Add IT8721F support
    
    only the serial port is tested, keyboard/mouse are gonna
    to be tested later, it may also need some more patches
    to make it work completely.
    
    Change-Id: Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f
    Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
    Reviewed-on: http://review.coreboot.org/204
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 864839a3e8de7a96891fd5752d7a1fe6cbca6ad9
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Sep 13 23:06:12 2011 +0200

    util/crossgcc: Update gdb to 7.3.1
    
    The previous version is no longer available.
    
    Change-Id: I8126617cfe9addeb4778f002398abbcb4c73d2c7
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/214
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Tested-by: build bot (Jenkins)

commit bb41f502444b2d0295809cc882b829d768962990
Author: Ruud Schramp <schramp@holmes.nl>
Date:   Mon Apr 4 07:53:19 2011 +0200

    inteltool: added more device IDs
    
    Change-Id: I6f2272ae4071025e671638e83bade6a96aac658b
    Signed-off-by: Ruud Schramp <schramp@holmes.nl>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/185
    Tested-by: build bot (Jenkins)

commit 4e22a3bc58e1b911387947b2e0e7a73176dd2d83
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Mon Dec 13 22:39:46 2010 +0100

    Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methods
    
    Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
    Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
    uses the same acpi wakeup vector as S3.
    Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink
    the power LED while sleeping.
    acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because
    it is used in both romstage and ramstage after patch 3/3, whereas
    i82371eb_early_pm.c is used only in romstage.
    I used the name acpi_get_sleep_type instead of  acpi_is_wakeup_early
    because I think acpi_is_wakeup_early is a bit misleading as a name since it
    doesn't return a boolean value.
    
    Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the
    added check for acpi_slp_type == 2 (resume from S2) should not
    change behaviour of other boards:
    northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type;
    northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0;
    northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3;
    northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0;
    southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type;
    southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type;
    southbridge/via/vt8237r/vt8237r_lpc.c:238:  acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
    southbridge/via/vt8237r/vt8237r_lpc.c:239:  printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
    
    Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/188
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 78834b794d82c91d2745f8de0e4d3bb14ee6187d
Author: efdesign98 <efdesign98@gmail.com>
Date:   Thu Aug 4 16:18:16 2011 -0600

    Miscellaneous AMD F14 warning fixes
    
    This commit adds in some more fixes to AMD F14 compile
    warnings.  The change in the mtrr.c file is in prep-
    aration for changes yet to com, but it is currently
    innocuous.
    
    Change-Id: I6b204fe0af16a97d982f46f0dfeaccc4b8eb883e
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/133
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 03169d3e1c03e76670ff7a07de7ee4fc6f601d3a
Author: Noe Rubinstein <nrubinstein@proformatique.com>
Date:   Thu May 5 15:44:40 2011 +0200

    Replace while with do; while to avoid repetition
    
    Cosmetic only; replaces some 'while' loops with 'do; while' loops to
    avoid repetition.
    
    Replacement performed by the Ruby expression:
    t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/,
    	"\\1do \\2\n\\1\\3;")
    
    Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd
    Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/183
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit ac624a638d25645f9a9a25ee2e16224aaf921b98
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Aug 9 08:52:14 2011 +0200

    Crank up CPU speed on Intel Core and Core2 CPUs
    
    The CPUs start on their slowest speed, and were left that way by
    coreboot. This change will speed up coreboot a bit, as well as
    systems that don't change the clock for whatever reason.
    
    Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/176
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7981b940a6bd703ae97f6c765c107ea7b4913dec
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 1 22:33:25 2011 +0200

    Report GSE chipset and warn if the code has been compiled for the wrong chipset.
    
    It would be nicer to unify the code so that it does all detection at runtime
    instead of compile time (but that would also significantly increase code size)
    so if someone else wants to give it a shot...
    
    Change-Id: Idc67bdf7a6ff2b78dc8fc67a0da5ae7a4c0a3bf0
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/184
    Tested-by: build bot (Jenkins)

commit 8679e52b9632254c247db31020d09e877071366e
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Sep 2 23:34:15 2011 +0200

    Add support utils for tracing
    
    Following patch adds a userspace util genprof
    which is able to convert the console printed
    traces to gmon.out file used by gprof & friends.
    The log2dress will replace the adresses in logfile
    with a line numbers.
    
    Change-Id: I9f716f3ff2522a24fbc844a1dd5e32ef49b540c5
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/179
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7f0e93060e720149bb59023d608a67cfc21542b1
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Sep 2 23:23:41 2011 +0200

    Add support for the tracing infastructure in coreboot.
    
    The compiler is forced to emmit special functions on every
    entry/exit of the function. Add a compile time option
    to support it. Function entries will be printed in
    the console. The CONFIG_TRACE has more documentation.
    
    Patch for userspace tools will follow.
    
    Change-Id: I2cbeb3f104892b034c8756f86ed05bf71187c3f3
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/178
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit f73535c089564864eb92628c351f76b0c556ab91
Author: Kerry She <shekairui@gmail.com>
Date:   Thu Aug 18 18:58:40 2011 +0800

    AMD F14 Rev C0 update
    
    Add AMD Family14 Rev C0 cpu id
    
    Change-Id: Iacd1c7b20e889da61a2085188766285f27e5c018
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Signed-off-by: Kerry She <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/160
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6209c8299a4bdcdb51cd6bf0c43c571ed575ad96
Author: Kerry She <shekairui@gmail.com>
Date:   Thu Aug 18 18:44:00 2011 +0800

    AMD SB800 southbridge update
    
    This patch enables access to the registers of the hardware monitor
    logical device in the superio via isa ports 0x295/0x296.
    Previously this was not enabled in the SB8xx LPC device.
    This is required for initialisation in init_hwm() in
    src/superio/winbond/w83627hf/superio.c and also by OS-level
    sensor monitoring such as lm-sensors to access temperature,
    fan monitoring and control and voltage registers.
    asrock/e350m1 and advansus/a785e-i mainboard changes are included herein.
    
    Change-Id: I2176885549277b335c0c41b48457d09b9b76b703
    Signed-off-by: Per Hansen <perh52@runbox.com>
    Signed-off-by: Kerry She <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/159
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit feed329a0c006968242aa3065506b5f37f4308d4
Author: Kerry She <shekairui@gmail.com>
Date:   Thu Aug 18 18:03:44 2011 +0800

    AMD F14 southbridge update
    
    This change adds the southbridge related code to support
    the update of the AMD Family14 cpus to the rec C0 level.
    Some of the changes reside in mainboard folders but they
    reference changed files in the southbridge folder so they
    are included herein.
    
    Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Signed-off-by: Kerry She <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/135
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 16d3ec6a58b7a7ba52d4d17299b977e5c3e0557f
Author: Wang Qing Pei <wangqingpei@gmail.com>
Date:   Tue Nov 9 09:17:07 2010 +0100

    Adjust some code/comment of sb700 sata init
    
    The inline comment of sata_init function seems not placed correctly.
    Rearrange it.
    
    Change-Id: I63480da60e51cdc68e64c302ad2d8a6197e288f6
    Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/186
    Tested-by: build bot (Jenkins)

commit f6e37316d0f751844898e92745182be9104d7df2
Author: Wang Qing Pei <wangqingpei@gmail.com>
Date:   Tue Nov 9 09:09:47 2010 +0100

    Disable dev3 on ma78gm-us2h
    
    Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot.
    
    Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa
    Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/187
    Tested-by: build bot (Jenkins)

commit 0e8ee81edbc3215d5f14cc80aef6dc08ee9d9f40
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Aug 28 11:04:23 2011 +0200

    buildgcc: Do not download GDB source code if run with --skip-gdb
    
    Change-Id: Ida3680418fdd3136752d51cc19f3e14111c12131
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/175
    Tested-by: build bot (Jenkins)

commit ebc28095ad2df05771cba3fbb7f4ddebdfd113dd
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Aug 26 21:48:32 2011 +0200

    Add a few more patterns to .gitignore
    
    Change-Id: If7c1c6d9a96dd788bacee72b6e18a435069cad6e
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/172
    Tested-by: build bot (Jenkins)

commit 054849dc6b004e510f3bb4c903cca9064941dc01
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Aug 26 21:57:53 2011 +0200

    Add dirty flag to git describe
    
    git describe knows --dirty, which adds -dirty to the verion number
    if the tree contains uncommited changes. We should add this flag
    to make it obvious that the COREBOOT_VERSION might be misleading.
    This is especially important as this version number is now used
    in the SMBIOS data structures.
    
    Change-Id: If4c608c7455e1bbf0cc530c6299fa00eb0fe4d58
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/173
    Tested-by: build bot (Jenkins)

commit ff31692e088a406d0fd1fd7dfab0a3b03c3ed8ef
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Aug 26 22:18:46 2011 +0200

    X60/T60: remove obsolete dmi.h
    
    Change-Id: Id0e8bcc1b93a629f0620b84a060d7ff99a82de78
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/174
    Tested-by: build bot (Jenkins)

commit 164bcfdd1b0b2cc789203eeb9e3ff842df215a7c
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Aug 14 20:56:34 2011 +0200

    Add automatic SMBIOS table generation
    
    Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/152
    Tested-by: build bot (Jenkins)

commit bc081cdf6d371988b0e280b8a20b451c49d43c77
Author: Alec Ari <neotheuser@ymail.com>
Date:   Sun Aug 21 22:09:53 2011 -0500

    Minor ma785gmt clean-up
    
    Change-Id: I9e889a6c475fb3283fa11f8b3de5baaf54235589
    Signed-off-by: Alec Ari <neotheuser@ymail.com>
    Reviewed-on: http://review.coreboot.org/167
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit e1562bdccb8d89fd795fcb9be8386827b3a92461
Author: Alec Ari <neotheuser@ymail.com>
Date:   Sun Aug 21 21:52:41 2011 -0500

    Fix up various dsdt.asl files
    
    Change-Id: I46eb27847deb3a903ac9af347992a9954e50ff6e
    Signed-off-by: Alec Ari <neotheuser@ymail.com>
    Reviewed-on: http://review.coreboot.org/166
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0e615007ecc6b1fe57fb08fc044ad7f888037f78
Author: Alec Ari <neotheuser@ymail.com>
Date:   Sun Aug 21 22:17:35 2011 -0500

    Remove dead code
    
    Remove dead code, copy and pasted from
    tilapia's mainboard.c file into various
    asus mainboard.c files
    
    Change-Id: Ic715ccaad8ac0210401d4a99ecb11e943f6afe58
    Signed-off-by: Alec Ari <neotheuser@ymail.com>
    Reviewed-on: http://review.coreboot.org/168
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 09377b7d3f62fb62a6e7c11aefdde771a774ea05
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Aug 21 06:24:55 2011 +0200

    buildgcc: Remove all bashisms, making the script run also on BSD
    
    Use sed instead of ${variable:start:length} and ${#variable}
    Use single = in string comparisons
    Use `eval echo '$'$variable` instead of ${!variable}
    Use > file 2>&1 instead of &> file
    Use readlink -f to expand the path of GCC configure
    
    Change-Id: Idc7dfcea3922f55630a6855acdb19e36582708bd
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/165
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 875b9b197f64e845a2c220a1f69a5c1b4000092f
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Aug 21 06:17:05 2011 +0200

    Use git describe to set KERNELVERSION
    
    Change-Id: Id579b19fc38c7ca2b98ad1e87aaec71c070a9178
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/163
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b98dbfb97e7a110ee2fc78b10524a147112e18a4
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Aug 21 06:21:39 2011 +0200

    buildgcc: Fix typo in check for failed iasl build
    
    Change-Id: I3e90b90e807ae775ac66af160a0f8547dcb3597a
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/164
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 6901b561eb39904c0d44c59e71c58952b690d8d8
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Aug 19 13:43:04 2011 +0200

    Lenovo H8: Always clear audio mute
    
    The mute bit is set by ACPI before poweroff/going to suspend.
    So clear it after resume, to have working volume control
    even if the ACPI doesn't clear it on resume.
    
    OSPM should control Audio mute with ec bit 0x30:6, so it is
    safe to clear this bit even if the user has audio muted.
    
    Change-Id: I18bebe532bf21cfb61b3d294a396bf15012f9f1a
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/162
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit b09e748f87c1a4a0b2ea2603fb5135afce006daa
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Aug 18 11:36:03 2011 +0200

    libpayload: export get_cbfs_header()
    
    Keep in sync with coreboot's version.
    
    Change-Id: I8a253446bd3b2ce9d05c6076a3f49f0260ecd5f9
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/158
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 8d0b86c9abc61414b06a60b28868739e077ffa87
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Jul 11 18:36:16 2011 +0200

    X60: use EC events 0x50/0x58 instead of GPIO GPE for Docking/Undocking
    
    Change-Id: I674e5166f5fb7ba299e6f1231f30434a5bf731c5
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/161
    Tested-by: build bot (Jenkins)

commit d819853f857f68dfd3661607d77ae5ccc7461e3b
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Aug 17 18:10:11 2011 +0200

    export get_cbfs_header()
    
    Change-Id: I4b6afcee3d0d169e03165a7fb48cfaef2e8253e2
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/157
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c643fdd157bbd54d15276b212d1f3d0bf64cd3f9
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jul 26 12:51:59 2011 +0200

    libpayload: Some more compatibility (for flashrom)
    
    libpci defines an arbitrary set of PCI vendor IDs, flashrom uses the
    Intel definition. Add it.
    
    flashrom also requires inttypes.h, so add the OpenBSD version
    
    Change-Id: I9bffd8193f635c375ac4d6b6eae8d3d876b95f5f
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/154
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8bbdb61113ad7f6814b198c01236411e4a3b7482
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Aug 16 15:47:15 2011 +0200

    libpayload: EHCI registers are volatile
    
    Some gcc versions seem to honor volatile at different places in a
    struct declaration.
    
    Change-Id: I0df2a3fb2eff4cee8cc1b8ac15d9cd9b86178752
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/155
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 4b8f779278fdb85e4207bd1f06c0f90ea81c8069
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Thu Aug 11 14:48:28 2011 -0500

    crossgcc: invoke buildgcc with bash, instead of relying on #!/bin/bash
    
    Change-Id: I09192e57e2535b2f8f98cabeb755f10c5520c499
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/151
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit f44bb4f4c13c225db8a83460432fa38568365016
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Thu Aug 11 14:44:55 2011 -0500

    buildgcc: improve portability
    
    `cp --remove-destination` isn't as portable as `rm -f` and `cp`.
    
    Change-Id: Ib05bfc121f7a0b467f8104920e14fbd02191585f
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/150
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 2aac3f6c51d6eb13da97f801d00bb73a2cdd4fdd
Author: Marc Jones <marcj303@gmail.com>
Date:   Mon Aug 8 16:07:50 2011 -0600

    Add iasl to buldgcc and rev the version.
    
    Change-Id: If9144cdf088f16bc3974a1784a442a1fd12ac75b
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/147
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 1a2b318625684142d6f1081a9abc057de1804d8a
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Aug 3 09:14:59 2011 -0500

    Do not compile nuvoton superio for all board
    
    The nuvoton WPCM450 code is compiled for all boards regardless of
    whether or not they use it. Compile it only for boards needing it.
    
    Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Reviewed-on: http://review.coreboot.org/129
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry She <shekairui@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 9f6cbde8901401d8381f2b2da677450119620f77
Author: efdesign98 <efdesign98@gmail.com>
Date:   Thu Aug 4 15:07:45 2011 -0600

    AMD Family 14 Agesa warning fix
    
    This change fixes one Agesa warning.  Originally this commit
    included some changes that I later deemed unnecessary.
    
    Change-Id: I31ad13bb92509228b89921561c340c95e5136370
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/132
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit ebbfbd59115c1a8ccf380041aecd6e903dcf925a
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Fri Aug 5 14:43:08 2011 -0500

    ms7135: add ACPI support
    
    Change-Id: I64a74d3dc0ea2d006ed4b25657d531fb243c2993
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/140
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 84cbce2364cf3e40f24ba37b2f72a711a2e50f58
Author: efdesign98 <efdesign98@gmail.com>
Date:   Thu Aug 4 12:09:17 2011 -0600

    Update AMD F14 Agesa to support Rev C0 cpus
    
    This change updates the AMD Agesa code to support the Family 14
    rev C0 cpus.  It also fixes (again) a ton of warnings, although
    not all of them are gone.  The warning fixes affect code in the
    Family 12 tree as well, so there are some small changes therein.
    This code has been tested on a Persimmon and passes Abuild.
    This is the first (and largest) of a number of commits to complete
    the upgrade.
    
    Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/131
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 0df0e14fb5b613e76ff022359c55d5df5633b40f
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Mon Aug 1 14:24:02 2011 -0500

    Add voltage control of southbridge and RAM on ms7135
    
    Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/126
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e089a3f68ddbbaaceb25d00322b3e7ccc27a48a8
Author: Keith Hui <buurin@gmail.com>
Date:   Tue Aug 2 22:28:14 2011 -0400

    northbridge/intel/i440bx: Registered SDRAM modules support and fixes
    
    Adds support for initializing registered SDRAM modules on
    Intel 440BX northbridge.
    
    Drops unneeded romcc-inspired programming tricks.
    
    Only set nbxecc flags (see 440BX datasheet, page 3-16) when
    a non-ECC module has been detected in a row via SPD; also
    drops an unneeded intermediate variable used in setting them.
    
    Boot tested on ASUS P2B-LS with regular and registered ECC
    SDRAM under Linux and memtest86+.
    
    Change-Id: Idc99d49567cca55f819d6b0e98952b1c3256498a
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Reviewed-on: http://review.coreboot.org/128
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 6de1ee4a3021cec992a63dbe20c4c1805e266e95
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jul 21 15:43:14 2011 +0200

    libpayload: Add liblzma, libcbfs
    
    Add cbfs core from coreboot into libpayload, and to support lzma decode,
    add coreboot's lzma code, too. Carl-Daniel agreed to relicense the
    lzmadecode wrapper as BSD-l, solving licensing problems.
    
    Change-Id: Id28990fe7e951d99447e265a4880d70a8f208dd2
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/115
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit b88351537bcee4b888a80b8afeb2f7e65767e666
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jul 21 15:11:40 2011 +0200

    split CBFS support into shared core and extended functions
    
    The core is data structures and basic file finding capabilities,
    while option ROM handling, and loading stages and payloads is
    "extended".
    
    The core is rewritten to be BSD-l (its header already was), so
    can be copied to libpayload verbatim.
    It's also more robust in finding files in corrupted images, eg.
    after partial erase or update.
    
    Change-Id: Ic6923debf8bdf3c67c75746d3b31f3addab3dd74
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/114
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3b77b723ca209199c8a224702812441e2196d452
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jul 7 15:41:53 2011 +0200

    libpayload: Add PDCurses and ncurses' libform/libmenu
    
    PDCurses provides an alternative implementation of the curses library
    standard in addition to tinycurses.
    Where tinycurses is really tiny, PDCurses is more complete and provides
    virtually unlimited windows and the full API.
    The PDCurses code is brought in "vanilla", with all local changes
    residing in curses/pdcurses-backend/
    
    In addition to a curses library, this change also provides libpanel (as
    part of the PDCurses code), and libform and libmenu which were derived
    from ncurses-5.9.
    As they rely on ncurses internals (and PDCurses is not ncurses), more
    changes were required for these libraries to work.
    
    The build system is extended to install the right set of header files
    depending on the selected curses implementation.
    
    Change-Id: I9e5b920f94b6510da01da2f656196a993170d1c5
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/106
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 1ac19e28eed4f6c53a4f295eb55500c65fc80f8d
Author: Keith Hui <buurin@gmail.com>
Date:   Wed Jul 27 23:06:16 2011 -0400

    cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
    
    Bring from coreboot v1 support for initializing L2 cache on Slot 1
    Pentium II/III CPUs, code names Klamath, Deschutes and Katmai.
    
    Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with
    Pentium III 600MHz, Katmai core.
    
    Also add missing include of model_68x in slot_1, to address a
    similar problem fixed for model_6bx by r5945.
    
    Also change Deschutes CPU init sequence to match Katmai.
    
    Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Reviewed-on: http://review.coreboot.org/122
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 8e9f156f482be2739926ef2ec82d2140384e6de9
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Wed Aug 3 13:56:24 2011 -0500

    Remove debugging code, or convert it to be selected by kconfig
    
    Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/130
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c2ffc6739cd94d996e8c11669031c101455eab90
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Mon Aug 1 14:15:28 2011 -0500

    Use preferred style of fixed-width integer types
    
    Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/125
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit ce37765772ebe0e58d3da81a35131d23e9f05137
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jul 23 23:29:44 2011 +0200

    crossgcc: update w32api
    
    crossgcc also needs lzma support as w32api is distributed in .tar.lzma
    
    Change-Id: Ia1938fa30262fe0c8bd655a08f9dc731a02e46ba
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/120
    Tested-by: build bot (Jenkins)

commit 68df804282f154d2401f43252259962144f957cb
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Jul 17 11:36:10 2011 +0200

    buildgcc: Break if parts of the toolchain are missing
    
    We test for the presence of a couple of tools and even print an error.
    But the tool didn't stop there.
    
    Change-Id: I40dcf7894408ea7b24d5f68c76df4b7541f469bd
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/111
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3ddb6b85f17d4adc832c319fcba25f7857d70ccd
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Jul 20 19:59:22 2011 -0600

    Add xhcbios and ahcibios rom handling
    
    This change adds xhci and ahci bios rom handling that
    is similar to the vgabios rom handling in the arch/x86
    Makefile.inc to the Persimmon and Torpedo mainboards.
    It also adds the basis for AHCI BIOS rom handling to
    the Persimmon Kconfig.
    
    Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/109
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 95b6611c18adc8aee9381ebdaf94e99e116db417
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Jul 20 13:23:04 2011 -0600

    Add the SuperMicro H8QGI platform
    
    This set adds support for the SuperMicro H8QGI mainboard.
    It is a publicly available 4 socket board using AMD Family
    10 cpus and AMD SR5650 and SB700 bridges.
    
    Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/108
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry She <shekairui@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 3cab93ce8ee8943a9e700535d36e0ceaab87b82e
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Jul 20 20:11:46 2011 -0600

    Add SSE3 dependent code
    
    This change separates out changes that were initially found
    in the commit for XHCI and AHCI changes to "arch/x86/Makefile.
    inc".  It also corrects a comment.  The SSE3 dependent code
    adds a pair of CR4 access functions and a blob of code that
    re-sets CR4.OSFXSR and CR4.OSXMMEXCPT.
    
    Change-Id: Id97256978da81589d97dcae97981a049101b5258
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/113
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 00c8c4a31632150fa711493f39e727da950ebe9f
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Jul 20 12:37:58 2011 -0600

    Update AMD SR5650 and SB700
    
    This updates the code for the AMD SR5650 and SB700 southbridges.
    Among other things, it changes the romstage.c files by replacing a
    .C file include with a pair of .H file includes.  The .C file is
    now added to the romstage in the SB700 or SR5650 Makefile.inc.
    file to the romstage and ramstage elements.  This particular change
    affects all mainboards that use the SB700, and their changes are
    include herein.  These mainboards are:
      Advansus a785e,
      AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
      Asrock 939a785gmh,
      Asus m4a78-em, m4a785-m,
      Gigabyte ma785gm,
      Iei Kino-780am2-fam10
      Jetway pa78vm5
      Supermicro h8scm_fam10
    The nuvoton/wpcm450 earlysetup interface is changed because the file
    is no longer included in the mainboard romstage.c files.
    
    Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/107
    Tested-by: build bot (Jenkins)
    Reviewed-by: Kerry She <shekairui@gmail.com>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 09ea8ea1a74d56a37755cec52077555b91f9e5b4
Author: Tadas Slotkus <devtadas@gmail.com>
Date:   Fri Jul 15 03:41:11 2011 +0300

    Libpayload: default DESTDIR for 'make install'
    
    If you would try download FILO via svn, then you probably
    get error message about libpayload install. This enables
    manually installing libpayload in legacy style :)
    
    Change-Id: I9f52be939303c5913611f21477d681e11d286382
    Signed-off-by: Tadas Slotkus <devtadas@gmail.com>
    Reviewed-on: http://review.coreboot.org/102
    Tested-by: build bot (Jenkins)
    Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit dd3e690220fd762c8ec603de673fcaea002f8a3d
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jul 12 15:50:54 2011 +0200

    libpayload: Provide dummy getenv()
    
    Change-Id: I419fcb16e0b10dee9195072e0e6befa6c9e61a69
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/105
    Tested-by: build bot (Jenkins)
    Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4b508341bcf11687be98d20f8178b5cc542a0842
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Jul 13 17:16:13 2011 -0700

    Add AMD Family 10 support to cpu folder
    
    This change adds the AMD Family 10 cpu support to the
    cpu folder.  It also updates the makefiles of the Families
    12 and 14 to take advantage of a pair of shared files that
    are moved to the cpu/agesa folder.
    
    Change-Id: Ibd3a50ea7a3028bd6a2d2583f021506b73e2fce2
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/97
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit b58640c5ef26ea49db8d94fa4962de3354bd2af2
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Jul 13 17:49:25 2011 -0700

    Add AMD Family 10 cpu support to northbridge folder
    
    This change adds the AMD Family 10 cpu support to the northbridge
    folder.  The northbridge/amd/agesa Kconfig and Makefile.inc are
    changed as well.
    
    Change-Id: Id76e9fa388c79ac469a673aaedaa4f1bfd7619d9
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/98
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit ca8a68d26b28ec7cb54804be1126e1253d554e49
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Jul 17 11:32:51 2011 +0200

    Fix coreboot revision detection
    
    Neither do we publish coreboot via svn, nor is git-svn a useful indicator
    anymore.  Instead, fetch a shortened commit id.
    
    Change-Id: I1b990384553209a7d39ecf7f5e8a2db7c7e34d0b
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/110
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 4c514aedd831a309b04e0092b85bb2c55d278b9d
Author: Steven A. Falco <sfalco@coincident.com>
Date:   Fri Jul 15 21:44:35 2011 -0400

    port_enable and port_reset must change atomically.
    
    I have observed two separate EHCI host bridges that do not tolerate
    using C bit-fields to directly manipulate the portsc_t register.  The
    reason for this is that the EHCI spec says that port_enable must go
    to 0 at the time that port_reset goes to 1.  Naturally this cannot be
    done using direct bit-field manipulation.  Instead, we use a temporary
    variable, change the bit-fields there, then atomically write the new
    value back to the hardware.
    
    Signed-off-by: Steven A. Falco <sfalco@coincident.com>
    Change-Id: If138faee43e0293efa203b86f7893fdf1e811269
    Reviewed-on: http://review.coreboot.org/101
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 43358a5e24da920b7ab8fb285c48f6f6f5955897
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Wed Jun 29 23:59:13 2011 +0200

    Workaround the errata #181.
    
    We use LDTSTOP# to trigger the FID/VID change on K8M890, because the
    FID/VID SMAF is blocked by not yet configured internal VGA.
    The memory controller is enabled later, nor the workaround makes any
    harm to non-affected CPUs.
    
    This update unbreaks compilation by declaring the tmp variable.
    
    Change-Id: Icf5d126b8c8cd9ece6af41d3129315a777c8cef2
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
    Reviewed-on: http://review.coreboot.org/69
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit f7b30808f38eb236622902bfd93626dab4dbbb61
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jul 12 15:02:04 2011 +0200

    libpayload: Improve compatibility
    
    Define INT_MAX, EOF and make sure size_t is available.
    
    Change-Id: I1b4b717d2545ea8312ec52339300307a5bd68f8a
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/104
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 229f7cb6d660ad4063c9f65e3fabfff80583f281
Author: efdesign98 <efdesign98@gmail.com>
Date:   Wed Jul 13 16:43:39 2011 -0700

    Add the AMD Family10 Agesa code
    
    This change officially adds the Agesa code for the AMD Family 10
    cpus.  This code supports the G34 and C32 sockets.
    
    Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/95
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 25f23f17bcb2bac9fb5af0f5d6d1d8c1c9ea16ff
Author: Steven A. Falco <sfalco@coincident.com>
Date:   Wed Jul 13 21:59:31 2011 -0400

    Print a warning when an unknow USB controller type is detected.
    
    The Intel E6XX Atom processor reports an unknown USB controller type (in
    addition to the standard EHCI and OHCI ones).  Add a default case to
    print a warning when an unknown controller type is detected.
    
    Change-Id: I885d0ccec4c46fd212cceac599290e9bf85edbbb
    Signed-off-by: Steven A. Falco <sfalco@coincident.com>
    Reviewed-on: http://review.coreboot.org/100
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 4edbe004b8b8c97900573218974191d2a2b77f1c
Author: Scott Duplichan <scott@notabs.org>
Date:   Wed Jul 13 17:34:16 2011 -0600

    Move AMD SB800 early clock setup.
    
    Move the AMD SB800 early clock setup code that is needed for early
    serial port operation from mainboard/romstage.c to sb800/bootblock.c.
    This prevents code duplication and simplifies porting.
    
    Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/96
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 9229af963df17257d87efd9a83bba9fe6021046c
Author: Steven A. Falco <sfalco@coincident.com>
Date:   Wed Jul 13 21:01:26 2011 -0400

    EHCI driver missing bus_address assignment.
    
    Other USB drivers set the bus_address field.  EHCI should do this too.
    
    Signed-off-by: Steven A. Falco <sfalco@coincident.com>
    Change-Id: Ic4274c6744951ef7fa0cb135caf8b9f177d8bcaf
    Reviewed-on: http://review.coreboot.org/99
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 5a91692466d501bde8fab5f9b0dee0a83444ee51
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Jul 12 23:02:03 2011 -0600

    Set SB800 ROM decode size based on kconfig.
    
    Change-Id: I46ea26b5534064fe1c7e2ce2b2f12cacf18a4d4d
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/94
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 2a561a18deeed436b27cb99cba4b15a4351435a1
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Jul 2 16:41:38 2011 +0200

    Enable SMI on M2V-MX SE
    
    Finally the SMI routines are in good shape on AMD, lets enable this and later
    implement ACPI on/off SMI commands.
    
    Change-Id: I9848a7be908780353eead30c16fd2df8ea48f77e
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/83
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b5b3b3bf8ca3eb5be974b50c05e60d03432173d7
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Jul 2 16:36:17 2011 +0200

    Make AMD SMM SMP aware
    
    Move the SMM MSR init to a code run per CPU. Introduce global SMM_BASE define,
    later all 0xa0000 could be changed to use it. Remove the unnecessary test if
    the smm_init routine is called once (it is called by BSP only) and also remove
    if lock bit is set becuase this bit is cleared by INIT it seems.
    Add the defines for fam10h and famfh to respective files, we do not have any
    shared AMD MSR header file.
    
    Tested on M2V-MX SE with dualcore CPU.
    
    Change-Id: I1b2bf157d1cc79c566c9089689a9bfd9310f5683
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/82
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a68555f48d06b4c8d55f7e4ca208805bec3d5512
Author: Kevin O'Connor <kevin@koconnor.net>
Date:   Sat Jul 9 20:22:21 2011 -0400

    Do full flush on uart8250 only at end of printk.
    
    The previous code does a full flush of the uart after every character.
    Unfortunately, this can cause transmission delays on some serial
    ports.
    
    This patch changes the code so that it does a flush at the end of
    every printk instead of at the end of every character.  This reduces
    the time it takes to transmit serial messages (up to 9% on my Asrock
    e350m1 board).  It also makes the transmission time more consistent
    which is important when performing timing tests via serial
    transmissions.
    
    Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70
    Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
    Reviewed-on: http://review.coreboot.org/90
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 537cacfa04c9dc56cd608012a73d95ab342d2f81
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jul 7 12:02:10 2011 +0200

    libpayload: Add qsort()
    
    It's taken from OpenBSD and thus appropriately licensed (and reasonably
    tested).
    
    Change-Id: I5767600c9865d39e56c220b52e045f3501875b98
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/88
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 40d99bc781fe71cf67090d27695b98cf6c2e9a45
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Jul 11 15:22:42 2011 +0200

    T60: enable GPIO before using GPIO I/O port range
    
    Change-Id: I39369e6f8a39f53f58a4b7fbe357637a79f5b596
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/93
    Tested-by: build bot (Jenkins)

commit 14c93ec269548d2b02da41e561355d14c840776f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Jul 11 14:58:48 2011 +0200

    T60: dont use X60 USB init flag
    
    ec byte 0x03, bit 2 seems to be only used on the X60s for USB switch
    initialization. Don't touch it on T60.
    
    Change-Id: Icb89a514757a0e06ccea200fde62a778fa8c268e
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/92
    Reviewed-by: Peter Stuge <peter@stuge.se>
    Tested-by: build bot (Jenkins)

commit 7d6f0bf10efbb3139c56e1e124370b1a29edc6ea
Author: Scott Duplichan <scott@notabs.org>
Date:   Sat Jul 9 20:14:20 2011 -0500

    ASRock E350M1: ACPI-related BSOD fix
    
    On installing/starting Windows (tested with Win7 Ultimate)
    the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error.
    
    From Scott Duplichan:
    To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT
    must be corrected. The attached patch does this. It uses the older
    patching method, and not the (possibly preferred) AML generation
    method. To simplify the patching operation, I moved the AML item
    'TOM1' to the start of the SSDT. The patch also includes code to
    confirm the AML variable TOM1 is at the expected offset before patching.
    
    Also tested & working with Linux.
    
    Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Reviewed-on: http://review.coreboot.org/91
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 1fe6c64ba136697a14fbefa6b0b70b1e8fe1fa0f
Author: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Date:   Fri Jul 8 22:41:12 2011 +0000

    Fix memory size reporting on AMD family 14h systems for >= 4GB
    
    Applying Scott Duplichan's fix for memory >=4GB
    
    Adjusted it to the new directory structure (agesa_wrapper was renamed to
    just agesa).
    
    Boot-tested and confirmed to work, on my board Linux can now access the
    whole RAM.
    
    Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
    Reviewed-on: http://review.coreboot.org/48
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 559290836b71462c5150963dbdfa33727500b710
Author: Patrick Georgi <Patrick.Georgi@secunet.com>
Date:   Thu Mar 10 14:53:54 2011 +0100

    libpayload: Don't declare mouse support in tinycurses
    
    Change-Id: Id1ff3d85617e3ec063ce332cf13920dfbbb7cf26
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/87
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c3c827cf864b10d5086177602f0157b9596bc380
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri May 27 15:31:52 2011 +0200

    libpayload: Provide atol(), malloc.h
    
    Change-Id: I807ca061115146a6851eef481eb881b279fba8e1
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/86
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 163e220c5d9a8f52bd4f195c9dc456233fa23d11
Author: Patrick Georgi <Patrick.Georgi@secunet.com>
Date:   Fri Mar 11 09:34:23 2011 +0100

    libpayload: Implement strlcpy
    
    Change-Id: Ibd339957690afe2cded46895c3088eba87f0ffd1
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/85
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 23b6c8f7caa09ed714bce9b6572b6067ae0498c6
Author: Patrick Georgi <Patrick.Georgi@secunet.com>
Date:   Tue Mar 15 12:34:04 2011 +0100

    libpayload: fix wborder()
    
    wborder didn't provide default characters to draw a border.
    
    Change-Id: Ib746ed16be341598fd9fa1f1b7577606d1abd9e5
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Reviewed-on: http://review.coreboot.org/84
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit a71ce0daa6ff6460d02b70a6436ce4d92da3009f
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jul 2 16:21:31 2011 +0200

    Fix lint-002-build-dir-handling
    
    That lint test requires some Kconfig defaults and uses allyesconfig
    for that. Unfortunately that also draws in ccache and scanbuild support,
    which significantly change the behaviour of the toplevel Makefile.
    Notably, the ccache support breaks if no ccache is installed.
    
    Change-Id: I17cbb7974be33fc077e5cbd5fb616a5b00a47d97
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/80
    Tested-by: build bot (Jenkins)

commit 61cd5bfae493607a434df91fc582ab1ffd36b3cc
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jun 23 19:12:25 2011 +0200

    T60: handle EC events in SMM if ACPI is disabled
    
    Change-Id: I6f9e90015cafef3da896453ef8e3588434ae3554
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/89
    Tested-by: build bot (Jenkins)

commit a78d57296861e98bc5f5875c3ee0ef813403c860
Author: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Date:   Tue Jun 7 15:03:14 2011 +0200

    Run 'git fetch' in SeaBIOS only when really needed
    
    This allows coreboot to compile without Internet connectivity
    
    Change-Id: I969471e44e417f127fdc8744e868211500acee3e
    Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
    Reviewed-on: http://review.coreboot.org/11
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 7f76290e2d085da8975a8a011f93e50a5460645b
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Jul 2 16:03:24 2011 +0200

    Small SMM fixups
    
    Align the spinlock to the 4 byte boundary (CPU will guarantee atomicity of XCHG).
    While at it add the PAUSE instruction to spinlock loop to hint the CPU we are just
    spinlocking. The rep nop could not be used because "as" complains that rep is used
    without string instructions.
    
    Change-Id: I325cd83de3a6557b1bee6758bc151bc81e874f8c
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/81
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit c0458e63d080223c7ee31367b8259f41a8f03405
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Jul 2 00:29:09 2011 +0200

    Fixes to the libpayload build system
    
    - its Makefile is part of the libpayload project
    - fix conversion bug in powerpc's Makefile.inc
    
    Change-Id: I84f2da092c3733ea7d0f232cb3768078cf13dfd5
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/79
    Tested-by: build bot (Jenkins)
    Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

commit ba48281faf75858481ed44181d68d5a8597834a4
Author: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Date:   Sat Jul 2 00:57:07 2011 +0300

    whitespace-only changes in acpi.c, replaced spaces with tabs
    
    Change-Id: Ibd598813bec0c93d77afbce8aee330498afbe5f6
    Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
    Reviewed-on: http://review.coreboot.org/74
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 9f52ea4c3cbde9c2bab06a7023d2722dc5e19c30
Author: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Date:   Sat Jul 2 00:44:39 2011 +0300

    added a config option for ACPI debugging
    
    Change-Id: Ie6296f5652196c6258aa6902d84dd86c17e224cb
    Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
    Reviewed-on: http://review.coreboot.org/36
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 3bda0443bad79db3aff190b792ed2976467091aa
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Jun 30 15:48:57 2011 +0200

    Relicense Makefile to match libpayload
    
    libpayload's license is more liberal than coreboot's. If we are to
    use the coreboot build system for libpayload (bringing a couple of
    new features to libpayload), we should adopt it for this shared part
    even if not strictly necessary.
    
    Change-Id: I1349616861e193b3e01407debbec3d82e09e72c2
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/70
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
    Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>

commit 3b81b9dfef1ddbc40f57196341a990249d3eaeb2
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Jun 30 19:55:31 2011 +0200

    Add local copy of commit-msg hook
    
    To avoid using untrusted network to download code, copy the
    relevant file to the repo and adapt "make gitconfig" to copy
    from there.
    
    Change-Id: I21f0b58d59250aa5d795cf289267ad93bd8d74db
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/73
    Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
    Tested-by: build bot (Jenkins)

commit 7f96583f0f6b9829f73fb8afbb6f367323446030
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Apr 21 18:57:16 2011 +0200

    Reduce warnings/errors in libpayload when using picky compiler options
    
    The new build system uses quite a few more -W flags for the compiler by
    default than the old one. And that's for the better.
    
    Change-Id: Ia8e3d28fb35c56760c2bd0983046c7067e8c5dd6
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/72
    Tested-by: build bot (Jenkins)
    Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

commit b3db79e9965cb290615a02b324648bc64f805660
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Apr 21 18:48:50 2011 +0200

    Use coreboot build system for libpayload, too.
    
    This change makes building coreboot related projects more unified.
    
    Change-Id: I0f1181e2fffde1e03675523f7dc9eef3119052c3
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Reviewed-on: http://review.coreboot.org/71
    Tested-by: build bot (Jenkins)
    Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

commit 23b215272d4d136efcac5f3b5712d2a1d76a91d9
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Wed Jun 29 23:47:20 2011 +0200

    Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP and
    for the transmit clock driving control. Unfortunately this is not enough
    to make the HT1000 work reliably, therefore blacklist this for now in CPU
    HT code. If ever anyone figure out what is wrong, it could be removed. The
    downgrading now makes the board work on HT800, which is certainly better than
    not at all with a HT1000 CPU.
    
    Change-Id: I949bfd9b0b48ee12bd0234c2fb1deaaa773bd235
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Reviewed-on: http://review.coreboot.org/68
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 0d21cd36b781076409d370935faf6081d970f644
Author: Mark Norman <mpnorman@gmail.com>
Date:   Tue Jun 14 22:20:37 2011 +0930

    Added support for Aaeon PFM-540I RevB PC104 SBC
    
    The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU.
    More infomation about the board available at www.aaeon.com.
    
    Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd
    Signed-off-by: Mark Norman <mpnorman@gmail.com>
    Reviewed-on: http://review.coreboot.org/30
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 811787abd5ec0c944a77ad1dda8817c95948b0c4
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 29 15:05:28 2011 +0200

    i82801gx: read RTC status register to prevent IRQ storm
    
    My Thinkpad appeared dead. After investigation, it turned out
    that the RTC Alarm was triggering an RTC PM1 SMI, but the SMI
    handler didn't read the status register, so it was triggered again.
    
    This is a really nasty situation, as it means you have to dissemble
    your Notebook just to unplug the RTC battery.
    
    Change-Id: I5ac611e8a72deb5f38c86486dbe0693804935723
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/67
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 55bf2e49d66af779e3e514db1bd716b354329559
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Jun 28 14:30:05 2011 -0600

    Libpayload needs to clear the bss region.
    
    Libpayload shouldn't count on coreboot or other payloads to clear memory. This fixes problems with payloads being loaded after or on top of each other.
    
    Change-Id: I30303d47e465e8921f47acab667c7998ba79fca7
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/66
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 3e706b63c03b4d1d64a21f4c26eaa12fc88cb1f8
Author: Kerry She <shekairui@gmail.com>
Date:   Fri Jun 24 22:52:15 2011 +0800

    amd southbirdge sb800 wrapper, pci bridge fix
    
    sb800 pci bridge SHOULD enabled by default according to the chipset document,
    but actually not enabled on some mainboard.
    enable sb800 pci bridge when told to enable in devicetree.cb.
    tested on ibase persimmon mainboard.
    
    Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3
    Signed-off-by: Kerry She <shekairui@gmail.com>
    Reviewed-on: http://review.coreboot.org/63
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 770b877796c1b4632b00191458dbc153226c6bee
Author: efdesign98 <efdesign98@gmail.com>
Date:   Mon Jun 20 21:48:37 2011 -0700

    Add the AMD Torpedo mainboard
    
    The Torpedo mainboard is the reference platform for
    the AMD Family 12 cpus and the AMD Hudson-2 (SB900)
    southbridge.
    
    Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/54
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7c0c64e1033b4edf9a488e8e31948726ee17465e
Author: efdesign98 <efdesign98@gmail.com>
Date:   Mon Jun 20 19:56:06 2011 -0700

    Addition of Family12/SB900 wrapper code
    
    This change adds the wrapper code for the AMD Family12
    cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
    northbridge and southbridge folders respectively.
    
    Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/53
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 7c634ae8c18d1e311b5b96f09b5e6af23e57eaf7
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Mon Jun 20 23:14:22 2011 +0400

    msrtool: added support for Intel CPUs
    
    Change-Id: I05f54471665aa99335a88d097c6de20174f91dc6
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Reviewed-on: http://review.coreboot.org/50
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 180f81e9a98047839e5887ed45966cb0be22e6c2
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jun 28 08:06:18 2011 +0200

    SMM: add guard and include types.h in cpu/x86/smm.h
    
    Change-Id: I002845cf7a37cd6885456131826ae0ba681823ef
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/64
    Tested-by: build bot (Jenkins)

commit edcf9f4fe6ca55b642400d1af097613038a56fdf
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jun 28 08:05:26 2011 +0200

    X60: remove pci config register save/restore
    
    SMM code already makes sure this register is saved and restored,
    so we don't have to do it.
    
    Change-Id: I078e1227de4436fba9c5fb3879a564c981cb0f9a
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/65
    Tested-by: build bot (Jenkins)

commit 1866e9ca78d410566840398f9cb8d0309693ba0b
Author: Mark Norman <mpnorman@gmail.com>
Date:   Sat Jun 18 10:24:36 2011 +0930

    Add SMSC SCH3114 superio register descriptions to superiotool.
    
    This has been tested on a Aaeon PFM-540I RevB PC104 SBC.
    
    Change-Id: Ie02875a1fa2d90d7cc843ce745f727312f7b7aec
    Signed-off-by: Mark Norman <mpnorman@gmail.com>
    Reviewed-on: http://review.coreboot.org/43
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d8b60a0f2d6b0f2fad071328aaa211a63c57c191
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jun 23 13:43:52 2011 +0200

    T60: undock on external power loss
    
    If power is unplugged/lost, we should undock the docking station.
    The power loss can also be caused by the fact that the user removed
    the thinkpad from the docking station without pressing the Undock button/hotkey
    first. Without undocking it on this event, the thinkpad LPC switch will still
    connect the Docking connector, which causes crashes when docking it again.
    
    Change-Id: I9ed783e491827bde20264868eab2b3a79c232922
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/62
    Tested-by: build bot (Jenkins)

commit f8aa185c6f85337d1fa2c517c0a1143095815983
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jun 23 13:41:55 2011 +0200

    T60: enable userspace EC events
    
    EC events 0x50-0x5f are never triggered by the EC. Instead they
    can be generated by writing the wanted events to register 0x2a.
    
    Change-Id: Ifd7ce991ee094cb16e8425ed670b6b45cffe3907
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/61
    Tested-by: build bot (Jenkins)

commit 8c17a63118d4d73f50f422bc5cf1a9b0f256e03f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jun 23 11:59:48 2011 +0200

    T60: add additional EC events
    
    We missed a few bits, i.e the battery and some hotkey events.
    
    Change-Id: Ia5561532f421eb3b40225301f0af639112abc3cc
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/60
    Tested-by: build bot (Jenkins)

commit 0326165a0140235e4abeb54f54cfc543ec949384
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jun 23 11:15:55 2011 +0200

    Add ThinkPad models
    
    Change-Id: I4f1a5d99486929eb0be76a0ab3bf0158a23c7d36
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/59
    Tested-by: build bot (Jenkins)

commit d266b6a999adde8784dc79e6470a898207ba90c9
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 22 16:08:51 2011 +0200

    T60: add missing License Header
    
    Change-Id: I03636deac7b6d8e01654cf978b1aac79cba10641
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/58
    Tested-by: build bot (Jenkins)

commit 3352b293d6642ebfd8af655dfa0d0ed7fc4035d3
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 22 16:08:45 2011 +0200

    X60: add missing License Header
    
    Change-Id: I9d6e80a633990e86dd3adfa2a761d09f62978349
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/57
    Tested-by: build bot (Jenkins)

commit 3aefab54e1e3517c8618a7a3031738685070cb81
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 22 16:08:32 2011 +0200

    H8: add missing License Header
    
    Change-Id: If472e1e8bb93d64cc52a9084ad33fb9abbf0fb33
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/56
    Tested-by: build bot (Jenkins)

commit d74f97e310a46177c822251cf007c127243adfa8
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 22 16:08:20 2011 +0200

    PMH7: add missing License Header
    
    Change-Id: I3468689408fce05142a0959d5d725bdbd03faea7
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/55
    Tested-by: build bot (Jenkins)

commit 3c74a2ab2c0d3a454a1b46242cf99ce133d19dc9
Author: Scott Duplichan <scott@notabs.org>
Date:   Tue Jun 21 20:05:19 2011 -0500

    Move SB800 clock init earlier
    
    Committing Scott's e350m1 changes (svn r6585):
    Move SB800 clock init earlier,
    Fixes problem where initial serial port output is garbled.
    
    Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Reviewed-on: http://review.coreboot.org/32
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit d367b00c5b2f05644e3fae41d4d560720e58cc38
Author: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Date:   Sun Jun 19 03:03:28 2011 +0200

    Add the coreboot config to CBFS
    
    The CBFS will contain a new file, named 'config' of type 'raw' that is a
    stripped-down version of the .config file that was used to build the
    current coreboot image. For space savings, all the comments and empty
    lines were removed from the original config, except for one that lists
    the coreboot git revision that's built into the image.
    
    This is done in order to easily reproduce the work of  someone else when
    only having their ROM image. In theory the reproduce could even be
    automated by a new dedicated make target.
    
    This should work even with abuild now.
    
    Change-Id: I784989aac0227d3679d30314b06dadaec402749e
    Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
    Reviewed-on: http://review.coreboot.org/46
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 621ca384a7a5efb2cc7597504dc17b741cd2df10
Author: efdesign98 <efdesign98@gmail.com>
Date:   Mon Jun 20 18:12:43 2011 -0700

    Move existing AMD Ffamily14 code to f14 folder
    
    This change moves the AMD Family14 cpu Agesa code to
    the vendorcode/amd/agesa/f14 folder to complete the
    transition to the family oriented folder structure.
    
    Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/52
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 05a89ab922473f375820a3bd68691bb085c62448
Author: efdesign98 <efdesign98@gmail.com>
Date:   Mon Jun 20 17:38:49 2011 -0700

    Rename {CPU|NB|SB}/amd/*_wrapper folders
    
    This change renames the cpu/amd/agesa_wrapper, northbridge/
    amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
    to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
    simplify the folder names.
    There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
    append "ull" to a trio of 64-bit hexadecimal constants to
    allow abuild to run successfully.
    
    Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/51
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit ee39ea7e7edf9699f1bae1b2708ad6816f054817
Author: efdesign98 <efdesign98@gmail.com>
Date:   Thu Jun 16 16:39:30 2011 -0700

    Add AMD SB900 CIMx code
    
    This code is added to support the AMD SB900 southbridge.
    
    Change-Id: I7dc5e13a53ffd479dcea4e05e8c8631096e2ba91
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/41
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit b0969d65e675f7c7a3004fc3f6fc154f22e73d44
Author: efdesign98 <efdesign98@gmail.com>
Date:   Thu Jun 16 16:35:54 2011 -0700

    Add AMD Family 12 cpu Agesa code
    
    This is the addition of the AMD Family 12 cpu code.
    
    Change-Id: I3febc81e192b4e86bbd3e8d6e1da62a28598fa8c
    Signed-off-by: Frank Vibrans<frank.vibrans@amd.com>
    Signed-off-by: efdesign98 <efdesign98@gmail.com>
    Reviewed-on: http://review.coreboot.org/40
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit d1cb0eecd130cb4259ce9fedb32ebcd9ada0d4b7
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sat Jun 4 10:37:35 2011 -0700

    sb800: move spi prefetch and fast read mode to sb bootblock.
    
    So we don't waste time on the first cbfs scan.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    [adapt persimmon with the same change, and work around romcc bug
     in bootblock code: it doesn't like MEMACCESS[idx] |= value;]
    
    Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
    Reviewed-on: http://review.coreboot.org/9
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 46b033e8cb30000148104e45753a033ed6d919c1
Author: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Date:   Sun Jun 19 21:07:20 2011 +0000

    Introduced support for 8MB and 16MB flash sizes
    
    Change-Id: I217ff84be3575ec09781710f19ad272c88227663
    Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
    Reviewed-on: http://review.coreboot.org/49
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit b531e4e8dece39ab6ade533a4e378f957697aa32
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 18 12:04:41 2011 -0500

    ASRock E350M1: Enable USB3 support
    
    Requires Scott Duplichan's patch for NIC support.
    Enables required PCIe port for USB3 - does not interfere
    with normal operations on non-USB3 model.
    
    Change-Id: I451bb1b4f799d6485e75fa949933e25e821b65f9
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Reviewed-on: http://review.coreboot.org/45
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>

commit 8fed77ae4c46122859d0718678e54546e126d4bc
Author: Scott Duplichan <scott@notabs.org>
Date:   Sat Jun 18 10:46:45 2011 -0500

    ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic
    
    Scott Duplichan's patch from the mailing list:
    sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function
    once, after determining device 0x15 function enables.
    
    1) Update the asrock e350m1 devicetree.cb to match the hardware.
    2) Change the way the sb800 cimx wrapper code works. The original
    cimx code calls sb800 cimx function sbBeforePciInit() once. When
    ported to coreboot, the gpp component of this function was called
    once for each gpp port, as the gpp port's enable/disable state
    became known. A 05/15/2011 change makes the early gpp code run
    only once, triggered by processing the 4th gpp port. This method
    is not general enough because the 4th gpp port is not enabled on
    all boards. With the current change, the early gpp code runs when
    the first gpp port is processed. If any gpp ports are enabled, the
    first must be enabled. Tested with Win7 and linux on asrock e350m1.
    This change will also affect amd inagua, and has not been tested
    on that board.
    
    Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Reviewed-on: http://review.coreboot.org/44
    Tested-by: build bot (Jenkins)
    Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>

commit 47b3fb403d5b7f7fc756d3567bacf66ea0c1b9e9
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Jun 17 20:47:08 2011 +0200

    SMM: flush caches after disabling caching
    
    Fixes spurious SMI crashes i've seen, and ACPI/SMM interaction.
    For reference, the mail i've sent to ML with the bugreport:
    
    whenever i've docked/undocked the thinkpad from the docking station,
    i had to do that twice to get the action actually to happen.
    
    First i thought that would be some error in the ACPI code. Here's a
    short explanation how docking/undocking works:
    
    1) ACPI EC Event 0x37 Handler is executed (EC sends event 0x37 on dock)
    2) _Q37 does a Trap(SMI_DOCK_CONNECT). Trap is declared as follows:
    
       a) Store(Arg0, SMIF) // SMIF is in the GNVS Memory Range
       b) Store(0, 0x808)   // Generates I/O Trap to SMM
       c) // SMM is executed
       d) Return (SMIF)    // Return Result in SMIF
    
    I've verified that a) is really executed with ACPI debugging in the
    Linux Kernel. It writes the correct value to GNVS Memory. After that,
    i've logged the SMIF value in SMM, which contains some random (or
    former) value of SMIF.
    
    So i've added the GNVS area to /proc/mtrr which made things work.
    I've also tried a wbinvd() in SMM code, with the same result.
    
    After reading the src/cpu/x86/smm/smmhandler.S code, i've recognized
    that it starts with:
    
            movw    $(smm_gdtptr16 - smm_handler_start +
            SMM_HANDLER_OFFSET), %bx
            data32  lgdt %cs:(%bx)
    
            movl    %cr0, %eax
            andl    $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
            orl     $0x60000001, %eax /* CD, NW, PE = 1 */
            movl    %eax, %cr0
    
            /* Enable protected mode */
            data32  ljmp    $0x08, $1f
    
    ...which disables caching in SMM code, but doesn't flush the cache.
    
    So the problem is:
    
    - the linux axpi write to the SMIF GNVS Area will be written to Cache,
      because GNVS is WB
    - the SMM code runs with cache disabled, and fetches SMIF directly from
      Memory, which is some other value
    
    Possible Solutions:
    
    - enable cache in SMM (yeah, cache poisoning...)
    
    - flush caches in SMM (really expensive)
    
    - mark GNVS as UC in Memory Map (will only work if OS
      really marks that Area as UC. Checked various vendor BIOSes, none
      of them are marking NVS as UC. So this seems rather uncommon.)
    
    - flush only the cache line which contains GNVS. Would fix this
      particular problem, but users/developers could see other Bugs like
      this. And not everyone likes to debug such problems. So i won't like
      this solution.
    
    Change-Id: Ie60bf91c5fd1491bc3452d5d9b7fc8eae39fd77a
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/39
    Tested-by: build bot (Jenkins)

commit 00d46499a2b4a62af4ad5c22e229460d4da13449
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Jun 17 21:26:28 2011 +0200

    T60: set dock LED's in mainboard.c
    
    The docking takes place in romstage to have early serial I/O for debugging.
    But to keep romstage small and prevent linking the EC code to romstage, set the
    status LED's in ramstage.
    
    Change-Id: I89fadbd61b6bfd9aff8c22370e51c84325f24751
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/42
    Tested-by: build bot (Jenkins)

commit c045b4cc458a62dbb1dd99ae6a9343e52d1fe1e0
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jun 16 16:43:46 2011 +0200

    X60/T60: disable USB power during suspend
    
    Change-Id: I11afba5d7531132a0274e55e8a478985a0ef956f
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/38
    Tested-by: build bot (Jenkins)

commit 86e1aea3e6ff0610ab832d923b530b3c5a768c71
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jun 16 16:43:04 2011 +0200

    Lenovo H8 EC: add usb_power_enable()
    
    Can be used to disable/enable Power output on USB ports.
    
    Change-Id: I5eb52b33c9e3359b0e5874bda2c0c8d75c196bc2
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/37
    Tested-by: build bot (Jenkins)

commit bfe8e5186ea9916634d31182ec0437f6175e7724
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Jun 14 20:55:54 2011 +0200

    SMM: don't overwrite SMM memory on resume
    
    Overwriting the SMM Area on resume leaves us with
    all variables cleared out, i.e., the GNVS pointer
    is no longer available, which makes SMIF function
    calls impossible.
    
    Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/34
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit b629d14becd78c634ad412df726d964ed5d51214
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 12 14:30:10 2011 +0200

    i945 GMA: restore tft brightness from cmos
    
    Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/24
    Tested-by: build bot (Jenkins)

commit d4dc9a5a039123f788848d1fa54926270b6c8805
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 15 17:13:27 2011 +0200

    Remove old ACPI code
    
    it isn't used anywhere, and could be fetched from git/svn history if
    needed.
    
    Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/35
    Tested-by: build bot (Jenkins)

commit d8c68a9d08afbd9475de8bf2ff6b43eec892fe8a
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jun 15 09:26:34 2011 +0200

    i82801gx: replace cafed00d/cafebabe by defines
    
    We're using '0xcafed00d' all over the code as magic for ACPI S3
    resume. Let's add a define for that. Also replace 0xcafebabe by
    a define.
    
    Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/33
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 5eef65bbbf99d262a5fe53bee8a642c2350fb789
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jun 10 20:05:53 2011 +0200

    Update README with newer version of the text from the web page
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Change-Id: I4f181979ca5e47b27731c681a320b34cbecc0027
    Reviewed-on: http://review.coreboot.org/19
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303@gmail.com>
    Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
    Reviewed-by: Sven Schnelle <svens@stackframe.org>

commit 8b39e07d04e7231e655124d539356c2462ab6a18
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 12 16:49:13 2011 +0200

    X60: handle EC events in SMM if ACPI is disabled
    
    Change-Id: I0fee890bd2d667b54965201f5c90da3656d7af5c
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/27
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit 4297a9a101f342ed9699848c8d55f26f78b3816c
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 12 14:35:11 2011 +0200

    X60: trigger save cmos on volume/brightness change
    
    Change-Id: I020e06bc311c4e4327c9d3cf2c379dc8fe070a7a
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/25
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit d29e5bb9335a7d185480a8a780b619d3a3151f11
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Jun 6 15:58:54 2011 +0200

    CMOS: add set_option()
    
    Change-Id: I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/23
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit d40d4f77126a6d7cbe932b4e6a43f86cde5a8689
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 12 15:08:58 2011 +0200

    X60/T60: set CMOS defaults
    
    Change-Id: I5789a03898cdbade67887c0389aab5c773f867d9
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/26
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit eab1db192f9c5e2cc75f77203cc02017a6ef9168
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Fri Jun 10 21:16:41 2011 -0500

    ASRock/E350M1: Skip memory clear for boot time reduction
    
    Applying Scott's patches to e350m1, svn r6600:
    Memory clear is not required for non-ECC boards.
    
    Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Reviewed-on: http://review.coreboot.org/20
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit 0f9cd435145f1d34a6ebe67ad547c79bc4246f3d
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 12 16:55:56 2011 +0200

    X60/T60: fix return value of mainboard_io_trap_handler()
    
    The handler should return 1 if it handled the request. The current
    code returns 0, which causes 'Unknown function' logs.
    
    Change-Id: Ic296819a5f8c6f1f97b7d47148182226684882a0
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/29
    Tested-by: build bot (Jenkins)

commit 5d9a83c9f00a22896029b994cce65fa64aea827d
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 12 16:53:25 2011 +0200

    log ec data with DEBUG_SPEW
    
    Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/28
    Tested-by: build bot (Jenkins)

commit fed129b0d533ad9aa6dd2cb0b507582d92536869
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Wed Jun 8 10:18:43 2011 -0500

    Add ACPI automatic PIC/APIC interrupt routing logic for ck804
    
    Change-Id: I2d462ca1220ea31af243c7a58a1dc33c39e9c840
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Reviewed-on: http://review.coreboot.org/13
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit c55bcdecf70586ba575af403f26f92dbbbc05190
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Jun 9 20:56:29 2011 +0200

    superiotool: Cosmetics and coding style fixes.
    
    Change-Id: Iacda2a9e37635d5cffc5004caf588ef3e5e09b5e
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Reviewed-on: http://review.coreboot.org/18
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix@chromium.org>

commit 1b8068e24467d812752c71888c4880d3cac41cf8
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 5 20:47:49 2011 +0200

    H8 EC: add volume CMOS setting
    
    Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/12
    Tested-by: build bot (Jenkins)

commit cc5dd98c1b93281651781643dfbc7efc7f34a174
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Jun 9 05:04:20 2011 +0200

    util/crossgcc: Add build-without-gdb Makefile target
    
    Change-Id: I5d02f1a23e54aa67be0cc01d921898c28c22f8e4
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/16
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>

commit ceacd77356259b23aa22a5beb34b6e19a0c7912c
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Jun 9 04:54:16 2011 +0200

    util/crossgcc: Add buildgcc -G and --skip-gdb options
    
    Change-Id: Ic31130774ad56abf0b5498b04b4890348352a621
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/15
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>

commit 0b6b4d6d439091cc83b8a63c821ca7e6817da94c
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Jun 9 05:06:25 2011 +0200

    Change make crossgcc to build without gdb by default
    
    Using gdb with coreboot is not (yet) very common, so at least for
    now it makes sense to not build gdb by default. A make crosstools
    target is also added, which runs the full build in util/crossgcc
    and thus generates a toolchain with both compiler and debugger.
    
    Change-Id: I939ebcd06ae9a1bc485fd18e70cac98112d3bbbf
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/17
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>

commit 486e03228e15c4e26e199900b8909c0676c1140a
Author: Marc Jones <marcj303@gmail.com>
Date:   Wed Jun 8 14:41:52 2011 -0600

    Revert changes to set the sb800 to AHCI mode.
    
    Seabios doesn't have this support included yet,
    which causes the generic Persimmon and other CIMx
    sb800 platforms to not boot.
    
    Change-Id: If07328b7c62d7fc314647adce8fab983ed327854
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Reviewed-on: http://review.coreboot.org/14
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit fe0b4c591602355c7219a1e3240bf396907417be
Author: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Date:   Tue Jun 7 14:55:40 2011 +0200

    Add basic .gitignore
    
    Ignore directories created by abuild, jenkins, payloads and crossgcc.
    
    Change-Id: I7d4145fc1e54a10ffdc4b884d8b8f0ae53e615c6
    Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Reviewed-on: http://review.coreboot.org/10
    Tested-by: build bot (Jenkins)

commit 51e1bc3a7b15dd635e2afb9d4d2ee1807fa057d5
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 5 21:32:51 2011 +0200

    T60/PMH7: move 'touchpad' option to pmh7
    
    This option is PMH7 specific, and should be moved there,
    so all Notebook utilizing a PMH7 have this option.
    For Thinkpads without Touchpad (like the X60), simply
    don't add 'touchpad' to cmos.layout.
    
    Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/6
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

commit e261807baceef199f31528f700fdd9a8a27d348e
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 5 11:39:12 2011 +0200

    i82801gx: enable ACPI during S3 resume
    
    disabling ACPI during S3 wakeup breaks ACPI wakeup, as the
    Host OS is assuming that ACPI is enabled.
    
    Change-Id: I8ced72c4b553d41a57f26d64998118e8a77621f8
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/7
    Tested-by: build bot (Jenkins)

commit f4dc1a73e440766bbc12b738462ae9467f6030fe
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 5 11:33:41 2011 +0200

    SMM: add defines for APM_CNT register
    
    in the current code, the defines for the APM_CNT (0xb2) register
    are duplicated in almost every place where it is used. define those
    values in cpu/x86/smm.h, and only include this file.
    
    And while at it, fixup whitespace.
    
    Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/4
    Tested-by: build bot (Jenkins)

commit bb60528e73ed611553befba2ea1bdf8c690a26e5
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Jun 5 15:15:49 2011 +0200

    Add "gitconfig" make target to simplify gerrit configuration
    
    "make gitconfig" installs the gerrit commit-msg hook and validates
    that user.name and user.email are configured.
    
    No data will be overwritten.
    
    Change-Id: I49ec98538574866e7ad6238ff3d02b9c1beef1bb
    Reviewed-on: http://review.coreboot.org/2
    Tested-by: build bot (Jenkins)
    Reviewed-by: Peter Stuge <peter@stuge.se>

commit b924eb45f1dee85b1366b202f7e8435069893d0f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Jun 5 20:43:04 2011 +0200

    T60: fix touchpad option
    
    Code used 'int' as return type, but the cmos option is only one
    bit. get_option returned with the value in bit 0-7, but all remaining
    bits were left unitialized by get_option(). fix this by using char
    as type.
    
    Change-Id: I60e609164277380f936f66c99ef9508fa6a6b67c
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/5
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit 44c1d3111b4c0873ddb459ba832cdfcb20a7437a
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sat Jun 4 10:36:21 2011 -0700

    re-indent, so files conform to coding guidelines.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab
    Reviewed-on: http://review.coreboot.org/8
    Tested-by: build bot (Jenkins)
    Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>

commit c21b054acc866dc79c4783338e97337b9ca9c587
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sat Jun 4 19:35:22 2011 +0200

    SMM: add mainboard_apm_cnt() callback
    
    motherboards can use this hook to get notified if someone writes
    to the APM_CNT port (0xb2). If the hook returns 1, the chipset
    specific hook is also skipped.
    
    Change-Id: I05f1a27cebf9d25db8064f2adfd2a0f5759e48b5
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-on: http://review.coreboot.org/3
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
    Tested-by: build bot (Jenkins)

commit 140a990a612e25a6d4974f696b9fa757e834d764
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Jun 3 21:56:13 2011 +0200

    Teach abuild to emit JUnit formatted build reports
    
    Jenkins can produce reports from JUnit test cases, so we fake testcases
    for each board.
    
    Change-Id: I34d46d15c83f4f04d2228f302eb626b261ac098d
    Reviewed-on: http://review.coreboot.org/1
    Tested-by: build bot (Jenkins)
    Reviewed-by: Sven Schnelle <svens@stackframe.org>
    Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

commit fb38eb01cae8b2ff3b3dd99544abadff242d8a46
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sat Jun 4 16:30:27 2011 +0000

    WARNINGS_ARE_ERRORS is y per default, don't set it twice.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d1760c834ae89052aee737364c5e0411fcdda870
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 4 15:48:14 2011 +0000

    Port persimmon r6594 to e350m1: Cosmetic cleanup
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8e33e356fbe352e77830387ffd0e1e4af03618a
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 4 15:47:56 2011 +0000

    Port persimmon r6593 to e350m1: Remove unused Kconfig options
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2334c8d2b7771dd77299ef0e5983dc994c798a60
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 4 15:47:30 2011 +0000

    Port persimmon r6592 to e350m1: Update GPP port configuration
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 314f4a2077b78fbbab3bfe60308e82b875ddcc07
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:47:05 2011 +0000

    Port persimmon r6591 to e350m1: ROM cache early
    
    Enable rom cache early to reduce boot time.
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a7699f42a1f485d912dcf99b5b5ef1d1c39393e
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:46:50 2011 +0000

    Port persimmon r6590 to e350m1: Work around memory allocation problem
    
    Fix memory allocation problem in amdInitLate. Disabled until further debug.
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb2ca2bafd1185294334eae5c6e0c740ef6b9487
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:46:32 2011 +0000

    Port persimmon r6589 to e350m1: Strip down AGESA options
    
    Remove some non-essential agesa options to reduce boot time.
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af85315707049fa36106cf6a3b41941fdce3895b
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:46:13 2011 +0000

    Port persimmon r6588 to e350m1: VGA framebuffer
    
    Declare legacy video frame buffer so that Windows generic VGA driver will work.
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit adc89b033e35c43f92b7dba7fc383bcda5cc381a
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:45:46 2011 +0000

    Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible
    
    Declare RTC as not PIIX4 compatible to match AMD hardware.
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ac4bef49079be534ff60c0d2dea9e04902161f2b
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:45:29 2011 +0000

    Port persimmon r6586 to e350m1: FADT revision
    
    Make fadt revision match its length. Solves Windows 7 checked build assert.
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 552ad9f75ed6b72decdfa8768ed2e9753eb5b7fa
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:45:12 2011 +0000

    Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
    
    Enable SPI cacheline prefetch early to reduce boot time.
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd460e620e8ea945548121d860e032cca9d452bf
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:44:54 2011 +0000

    Port persimmon r6583 to e350m1: pstate 0 early
    
    Switch processor cores to pstate 0 early to reduce boot time.
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b3ee0d6bd6df18b61779f64c8b0abf19b1dce018
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:44:31 2011 +0000

    Port persimmon r6582 to e350m1: 33 MHz SPI read early
    
    Enable 33 MHz fast mode SPI read early to reduce boot time.
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69e1bfcf341713be9cafa3565a0329a902cfb4f1
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 4 15:44:14 2011 +0000

    Port persimmon r6578 and r6596 to e350m1: MMCONF base
    
    Remove multiple mmconf settings and just use kconfig setting.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb92b5ad64fcc7cd5f7b7ada83df646e9340c6ae
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:43:56 2011 +0000

    Port persimmon r6574 to e350m1: MMCONF size
    
    Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a403191cb1e2988f4d973a20fe15d969e637807
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:43:38 2011 +0000

    Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy
    
    1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
    2) Extend PCI MMIO limit from dfffffff to fecfffff.
    3) Add AMD recommended non-posted mapping for SB800 legacy devices.
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d5ee2d80a0fc0a30322df0c40f2d374c963a370
Author: Marshall Buschman <mbuschman@lucidmachines.com>
Date:   Sat Jun 4 15:43:15 2011 +0000

    Port persimmon r6572 to e350m1: I/O APIC ID
    
    1) Set I/O APIC ID according to BKDG recommendation
    2) Correct I/O APIC ID reported by mptable
    
    Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e1898b5fa1f007069c25be53a8369429135fa7e9
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 4 15:40:12 2011 +0000

    vt8237r: Simplify bootblock init to work around nested if() romcc problem
    
    During the hackathon in Prague we discovered that romcc has a problem
    compiling the previous nested if() statements correctly. This patch
    makes the code a little simpler, and indeed works around the romcc issue.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 471f103e530b97c1125acdab259043dd7f252fe9
Author: Marc Jones <marcj303@gmail.com>
Date:   Fri Jun 3 19:59:52 2011 +0000

    This patch sets max freq defaults for ddr2 and ddr3for fam10.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Scott Duplichan <scott@notabs.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23d3dfaa96649c71295de205885e97c6b45f9183
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Fri Jun 3 19:46:25 2011 +0000

    Correct wrong PCI ID for VIA K8M890 Chrome.
    
    With the K8T800/M800 patch from r6367 the PCI IDs for the VIA chrome were
    moved to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly.
    (3220 instead of 3230). This patch defines the correct PCI ID for this device.
    
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3bf2708664c4e7465607fc69ca17a22c537fc6ee
Author: Kerry She <kerry.she@amd.com>
Date:   Fri Jun 3 10:14:56 2011 +0000

    advansus/a785e-i mainboard enable warning as error
    
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Acked-by: Kerry She <kerry.she@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b2a4264ea54e19729f86e9d01b9933ad83ce16be
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Jun 1 19:54:16 2011 +0000

    Really fix iasl filename issues in our build system
    
    There's a remaining issue that iasl cuts of "\..*$" from
    output paths, even if that substring contains "/" (ie.
    across directories)
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9d19f2a26f81a52cc995e701cb9a29e0b72a428
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Jun 1 19:29:48 2011 +0000

    Report build result from abuild (did all requested boards build?)
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 76d53b22d393ca15d3c0eef8b2d37478000ae86c
Author: Kerry She <kerry.she@amd.com>
Date:   Wed Jun 1 02:00:30 2011 +0000

    trivial remove blanks at the end of line
    
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Acked-by: Kerry She <kerry.she@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 991f8808933a8b528108dcd48a029ebf40b05c6b
Author: Kerry She <kerry.she@amd.com>
Date:   Wed Jun 1 01:56:49 2011 +0000

    This patch fix a AMD sb800 wrapper compile warning:
     src/southbridge/amd/cimx_wrapper/sb800/late
     call clear_ioapic but not include the prototype declare header file.
    
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b2ecd8151481af7c5a74ed61967ad9698486253e
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Mon May 23 22:48:13 2011 +0000

    We don't have pausing versions of single-IO instructions.
    
    Hence remove the wrong comment.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cb175632d652a8441b10e1c996db6eb109deb71
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Mon May 23 22:43:43 2011 +0000

    AP_IN_SIPI_WAIT is already defined in the CPU Kconfig of those boards.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4053e1412fc304ca03b2c22c970d35cbd7b81ddd
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Mon May 23 17:55:20 2011 +0000

    Correct implementation of r6608.
    (.align actually takes its argument in bytes)
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c19f5d3337f5c8b057bab07b474ffcf4ce67b42
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Mon May 23 17:16:44 2011 +0000

    exclude src/vendorcode from GPLv2 license checks.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6409a2258628487cf9061a4335b30ce1f27c8afd
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Sun May 22 15:39:25 2011 +0000

    Ensure ck804 romstrap is 16-byte aligned.
    This alignment seems to be necessary for the chip to recognize it.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 40ad842ade3d3b4178b26034b00a06162fd5e5ab
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat May 21 22:18:59 2011 +0000

    Add regression test for build directory handling to make lint target
    
    A couple of scenarios that were fixed in the last few revisions are
    tested to ensure that it's easy to determine breakage.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29ddbb813fecc42ebb40aa52e5dd73696027d791
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri May 20 23:31:41 2011 +0000

    Handle absolute source file paths
    
    We used to fail there because we unconditionally prefixed the relative directory where it was referenced.
    Tested in various scenarios:
    - obj=build
    - obj=../obj
    - obj=$PWD/../obj
    - obj=/some/other/absolute/path
    - obj=/./some/other/absolute/path
    
    In-tree relative paths still work as before, the only change in behaviour is when a source file name (as specified in one of the *-y variables) starts with "/".
    
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 64ccc3b80348d5d8e6b8f698ec5ef2b596a46153
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri May 20 23:08:12 2011 +0000

    Handle both cases, obj being absolute and relative
    
    gnu make's handling of filenames is less than optimal. It simply
    compares strings, so foo/../bar is different from bar, even though
    they're logically the same.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 447cf563ca03902d744c9dd5a269bc1940f2eb72
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri May 20 22:17:58 2011 +0000

    Fix building with relative path to object directory outside the source tree
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0c5b0642a94e5725bf02dfd353ddb4a9ad3bb690
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri May 20 22:16:49 2011 +0000

    iasl still can't cope with extra "." in file paths
    
    It's really a work around, but given how this issue seems to come
    back again and again, let's work around it.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96dafaf44dd2bb9068e3fb59bd80c1bf400b83ac
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri May 20 22:14:07 2011 +0000

    Fix ccache behaviour if more than one ccache in PATH
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb93178f13c49c786ba142b119de9245eaf5b52b
Author: Scott Duplichan <scott@notabs.org>
Date:   Fri May 20 17:50:14 2011 +0000

    Correct amd persimmon romstage code for early SPI prefetch enable.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Scott Duplichan <scott@notabs.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20aad25e6e8275815cfdbf4fbb07f9317e3c4812
Author: Scott Duplichan <scott@notabs.org>
Date:   Fri May 20 00:06:09 2011 +0000

    Move the ACPI FACP table to the front of the RSDT list. This is done to work around a Windows XP or Server 2003 setup failure where an error message such as: "An unexpected error (805262864) occurred at line 1768 of d:\xpclient\base\boot\setup\arcdisp.c" occurs. This change updates AMD reference board projects, but could applied to others as well.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c44550df1684d13cc2c1bf29410c99e91bfa204
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon May 16 15:32:28 2011 +0000

    Move crossgcc rules to coreboot specific Makefile
    
    Toplevel Makefile should (as far as possible) be coreboot-agnostic,
    we have Makefile.inc for that.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b933d4644a9cc73bf6f54ee148ddc3b0638a0f7
Author: Cristian Magherusan-Stanciu <cristi.magherusan@gmail.com>
Date:   Mon May 16 01:35:03 2011 +0000

    Add crossgcc target to automatically build reference toolchain
    
    This means that a simple:
    
    $ make crossgcc
    
    creates the reference toolchain in the correct directory. Thanks to the
    dependency on the clean-for-update target, an existing .xcompile along
    with any compiled objects in build/ will be cleaned out, so the next
    build will automatically use the newly created reference toolchain.
    
    Signed-off-by: Cristian Magherusan-Stanciu <cristi.magherusan@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f0075b3d2acfb93f06f76d3b5e11e4ea6987efe
Author: Peter Stuge <peter@stuge.se>
Date:   Mon May 16 00:05:50 2011 +0000

    cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 44d3c3dade57b3564bcf6bcafc490756d9f45d44
Author: Marc Jones <marcj303@gmail.com>
Date:   Sun May 15 23:13:54 2011 +0000

    Remove multiple mmconf settings and just use kconfig setting.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 16c8e37a2d4e5164742c605b5894d31d9cbab3e1
Author: Peter Stuge <peter@stuge.se>
Date:   Sun May 15 22:40:40 2011 +0000

    agesa_wrapper: Avoid repetitive Kconfig depends, trivial
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c462637212735b1850c22f7cd51e0c947f28564
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 22:10:15 2011 +0000

    Cosmetic cleanup.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5d878ad3123b82630cc4992f4fae448d0403be24
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 22:09:09 2011 +0000

    1) Remove unused kconfig options.
    2) Correct UMA graphics PCI device ID.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a64ab46b629737658a461914d0d63ae713c0e760
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 22:07:56 2011 +0000

    Update gpp port configuration.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 769527e523bb40ecb33a1f6811dae0d689ca4e26
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 22:06:09 2011 +0000

    Enable rom cache early to reduce boot time.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c639e7df84996926535e5f66ddfdfb9076c6b74
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 22:05:00 2011 +0000

    Fix memory allocation problem in amdInitLate. Disabled until further debug.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b886ae3c305ff69635cf4cc586a356a54418304
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 22:03:45 2011 +0000

    Remove some non-essential agesa options to reduce boot time.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dbbbca3f33db8726593b2916e5df68598ea75bb8
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 22:02:27 2011 +0000

    Declare legacy video frame buffer so that Windows generic VGA driver will work.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ebefd27c8e1c9794afd19a663aaf9f88964fe2a
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 22:00:23 2011 +0000

    Declare RTC as not PIIX4 compatible to match AMD hardware.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 254a6d6ea7f7477444e09ca86a092d185d0a9f80
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:59:19 2011 +0000

    Make fadt revision match its length. Solves Windows 7 checked build assert.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7e068305c4186608ae70a6af8a3862a43a68b8d
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:56:03 2011 +0000

    Enable SPI cacheline prefetch early to reduce boot time.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2cc5f550c72ac6a13da798b8f073e3d5c55177e0
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:54:04 2011 +0000

    Enable SPI cacheline prefetch early to reduce boot time.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9a634c7560d0af50e141ad18ffc8c48519209e7
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:51:31 2011 +0000

    Switch processor cores to pstate 0 early to reduce boot time.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e73fc20886e094149f44f9306ef15971154f59ee
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:48:22 2011 +0000

    Enable 33 MHz fast mode SPI read early to reduce boot time.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ab3c6c3a95d0dd438e9b105a22a45f021a24aec
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:45:46 2011 +0000

    Build device paths for AP cores so that coreboot will report them to the OS.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be8fae1c710c71c9bf7479cf3d91a9f17a5594d1
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:41:00 2011 +0000

    Program the I/O APIC ID.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f191c720389b5f4cffc3480096a11e2ff5a050b1
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:38:08 2011 +0000

    Enable AHCI mode and hide IDE controller to reduce boot time.
    Note: enable AHCI in seabios and apply seabios patch:
    http://www.mail-archive.com/seabios@seabios.org/msg00437.html
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc312cca530940e4019bb3b0d9bbb97f9c748575
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:26:04 2011 +0000

    Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b9143afccef8ec9454914ab6d084c1630edb849
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:19:54 2011 +0000

    Fix ACPI shutdown function by removing reliance on SMI.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e78ae24eb1003f5fa22bd54365025dda78f37dda
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:18:59 2011 +0000

    Configure CIMx to use 33 MHz fast mode for SPD read.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 444c49c68c224ac5b88a6efd96d4d3b911347356
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:13:00 2011 +0000

    Match DIMM SPD addressing to implemented slots.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6719c23a47bf21acf0d1b45c436e16fdfb05eee0
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:11:41 2011 +0000

    Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b0b4063d6a5a43ffb2d9fc6cb6caadc21c31af3c
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:10:20 2011 +0000

    1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
    2) Extend PCI MMIO limit from dfffffff to fecfffff.
    3) Add AMD recommended non-posted mapping for SB800 legacy devices.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f7375c24c0284af1811f7d14118b21fff10160a
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:07:43 2011 +0000

    1) Set I/O APIC ID according to BKDG recommendation
    2) Correct I/O APIC ID reported by mptable
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d6a456c9af2fdb88260d06b532a3be0b0b55e2f
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:06:30 2011 +0000

    Correct the number of MCA error reporting banks cleared.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a72425a7e624efd01bacbea87154383b05e41b57
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun May 15 21:01:42 2011 +0000

    1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.
    2) Remove coreboot variable MTRR initialization because AMD reference code handles it.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb97e9688f4ae8060c12cd1c57c3bc80c547e5b2
Author: Josef Kellermann <seppk@arcor.de>
Date:   Fri May 13 06:25:16 2011 +0000

    siemens/sitemp_g1p1: Adapt read_option() to latest changes
    
    Signed-off-by: Josef Kellermann <seppk@arcor.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ceccd8dd676deca966a0b47377a3eb7d485d9f12
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu May 12 06:53:52 2011 +0000

    Remove uart_init() in Siemens sitemp-g1p1
    
    uart_init() was moved to common code in r6531, but I
    missed that when integrating the new mainboard code.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bfa7ee5b043c8f6e5823fc8ce48e53f354b053f7
Author: Josef Kellermann <seppk@arcor.de>
Date:   Wed May 11 07:47:43 2011 +0000

    Add Siemens SITEMP-G1 board
    
    The code is loosely based on AMD dbm690t (and copied from there)
    and adapted to match the Siemens SITEMP-G1 board.
    It boots both Linux and Windows XP (and if it doesn't then complain
    with me [Patrick] because in that case I must have messed it up when
    integrating the patch)
    
    Signed-off-by: Josef Kellermann <seppk@arcor.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d6cf3a2d7f3acb00829613b9c9734f376b23497
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed May 11 07:44:27 2011 +0000

    Work around unclean CMOS handling for now
    
    Stefan switched away from #ifdef across the tree (and is absolutely right with that), but
    unfortunately there are some special cases that trigger in even more special situations.
    
    Revert one such change selectively. It's destined to go once CMOS is reworked.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b251753b4fae1e827f5398daf679773eba643dce
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue May 10 21:53:13 2011 +0000

    Change read_option() to a macro that wraps some API uglyness
    
    Simplify
    read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
    to
    read_option(foo, somedefault)
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6649d9740d79b8c52d40218d78393547aaad7548
Author: Vikram Narayanan <vikram186@gmail.com>
Date:   Tue May 10 21:47:57 2011 +0000

    This replaces the fixed shift values in the apic timer init with macros.
    
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a8f0f5120b69e02eff5337932b92771363d159a5
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue May 10 21:42:52 2011 +0000

    Fix compilation error due to non-unix style line endings in cmos.layout file while generating option_table.h.
    
    Windows, Mac and *nix type line endings are now taken care of.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
    Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2ed23f45b84d23afd8991d4c12dc1085d94e523
Author: Ivaylo Valkov <ivaylo@e-valkov.org>
Date:   Mon May 9 20:53:38 2011 +0000

    Adds RS740 HT and internal graphics PCI ids.
    
    Signed-off-by: Ivaylo Valkov <ivaylo@e-valkov.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6401fdb02593940e3091b1d200c64d9c1d7269f3
Author: Kerry She <kerry.she@amd.com>
Date:   Sat May 7 09:15:02 2011 +0000

    ADVANSUS A785E-I Mainboard support, Family10h ASB2, RS880(RS785E) + SB820 platform.
    
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit faafd14fe0d18de1f71491f4503f36a4f9d9a188
Author: Kerry She <kerry.she@amd.com>
Date:   Sat May 7 08:51:32 2011 +0000

    RS780 DDI Lanes configure support,
    and remove RS780 get_cpu_rev().
    
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb995c209c81bcc0851335dd9bc3b1f38965271d
Author: Kerry She <kerry.she@amd.com>
Date:   Sat May 7 08:43:40 2011 +0000

    SB800 CIMX code can share the AGESA V5 lib code,
    some platform only use sb800 cimx code, not use AGESA v5 code.
    for such platform, one can compile the sb800 cimx and AGESA v5 lib code.
    
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c85c7794ebf7f98862d9c94541b02b6264c9a7f
Author: Kerry She <kerry.she@amd.com>
Date:   Sat May 7 08:37:38 2011 +0000

    1. move _mm_clflush_fs() to __SSE3__ block, because __builtin_ia32_sfence() is the sse built-in function
    2. move the Amd Lib functions using sse build-in functions to __SSE3__ block
    
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c4b499ba57b78aa69735c95bbd9361d41f1a2c1
Author: Kerry She <kerry.she@amd.com>
Date:   Sat May 7 08:33:14 2011 +0000

    put the amdlib and agesa constant to .rodata segment.
    so amdlib.c would not complain "Do not use global variables in romstage"
    
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ccad951e7d7198ea915fc8d9c8dee1062bcf57d8
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Thu May 5 16:49:11 2011 +0000

    Adds VOID to empty parameter lists to get rid of some build warnings.
    
    This change modifies a collection of files by adding the VOID parameter
    to empty parameter lists to cut down on the number of warnings produced
    when compiling the AMD Agesa code.  This should cut down the number of
    warnings by about 1100 each for rom- and ramstage.
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec40260ade7f9d03978f3a15b5c4e8343d3e6065
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Thu May 5 16:45:36 2011 +0000

    Remove AMD Agesa requirement for standard include files
    
    This change modifies Makefile.inc to add the -nostdinc flag to the default
    CFLAGS value and removes the test for non-AMD Agesa builds.  Other code is
    added to the gcc-intrin.h file in the Agesa Include folder to make the
    requirement for the standard includes obsolete from the Agesa perspective.
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f81c03d3a0d3183061ca56aecc306995dd648f2
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue May 3 07:55:43 2011 +0000

    Enable caching for ROM area in model_6ex/cache_as_ram.inc
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 49ae971333408f2a37b9fd6752f6cc9b8fb7f5b4
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue May 3 07:55:30 2011 +0000

    i82801gx: enable SPI prefetching
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8eee19d0eafd3a34742df4d26c810424097211fe
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon May 2 19:53:04 2011 +0000

    Add option 'compress ramstage'
    
    Add an option to make compression of ramstage configurable. Right now
    it is always compressed. On my Thinkpad, the complete boot to grub takes
    4s, with around 1s required for decompressing ramstage. This is probably
    caused by the fact the decompression does a lot of single byte/word/qword
    accesses, which are really slow on SPI buses. So give the user the option
    to store ramstage uncompressed, if he has enough memory.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4ee7d80e06a206a248a265348669b78150ba059d
Author: Scott Duplichan <scott@notabs.org>
Date:   Sat Apr 30 00:22:04 2011 +0000

    Sorry, my mistake.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0401f732f4382ac5c0cd60d41fe71edb43405fce
Author: Scott Duplichan <scott@notabs.org>
Date:   Sat Apr 30 00:17:23 2011 +0000

    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 95ebe66f7f5fef64d363cb48e5a441ad505353d1
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Apr 28 09:29:06 2011 +0000

    Thinkpad: Enable Battery events
    
    Enable the following events for battery objects on
    Thinkpad X60/T60:
    
    24: BAT0 critical
    25: BAT1 critical
    4A: BAT0 present
    4B: BAT0 state change
    4C: BAT1 present
    4D: BAT1 state change
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50270b822fcfe0e58deb18210001a92661e52401
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 27 19:48:05 2011 +0000

    X60: enable Ultrabay if device is plugged in
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit edabf54da9abd4b5d7d37606595b4a97553897b8
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 27 19:47:49 2011 +0000

    T60: enable Ultrabay if device is plugged in
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bf9e9309c01602d378f6238a51e86c78c25e2301
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 27 19:47:42 2011 +0000

    Lenovo PMH7: add pmh7_ultrabay_power_enable()
    
    Can be used to enable/disable Ultrabay power on Thinkpads
    who control that with the PMH7. (i.e. T60)
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cf7dffeabc82c50f807a62ba8ef6ed45ff53cbc8
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 27 19:47:28 2011 +0000

    Lenovo H8: add h8_ultrabay_device_present()
    
    returns 1 if a CDROM/HDD device is plugging in the
    ultrabay. Return 0 if there's a battery or superio
    extensions plugged in.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4885daadb33bea37ef3970696d3cf0d05e9852a3
Author: Stefan Reinauer <reinauer@google.com>
Date:   Tue Apr 26 23:47:04 2011 +0000

    Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an
    example.
    
    This newer version reflects the recent changes to further simplify the console
    code and partly gets rid of some hacks in the previous version.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3187d0267d4b456eb43bca21a817c78687d6f73b
Author: Stefan Reinauer <reinauer@google.com>
Date:   Fri Apr 22 23:12:40 2011 +0000

    Add (partly) support for Nuvoton NCT6776F
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a4ae82809348acef74b09326f33baa284b91c1a
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 22 23:10:35 2011 +0000

    cosmetic changes to superiotool's nuvoton code
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b721287580e60007368644b5433e3874fa89d3d8
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Apr 22 22:26:04 2011 +0000

    Fix of fix copy and paste errors in ne2k.c (r6512 by stepan)
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f5ce87d10c2471f5ee9b51c41c9e2ce2bdc60645
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 22 02:32:03 2011 +0000

    fix typo ttys0_index -> b_index
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f349d55beb6d93aca4d49ac4515c5ef11bb58d8d
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 22 02:17:26 2011 +0000

    Get rid of all but one (I/O mapped) UART init functions.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6aca1e8b26e712d056816ba936fb4d5834a07467
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 22 01:45:11 2011 +0000

    The UART divider should be calculated based on the base frequency
    and baudrate, not hardcoded in addition to that.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3e4fb9d1a12c6a4b69702badc7223fec3b6e8ddb
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 21 21:26:58 2011 +0000

    more ifdef -> if fixes.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4814bd41c080fb9dda87c762fcaecf4e72fc996
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 21 20:45:45 2011 +0000

    more ifdef -> if fixes
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d888a97849d68a7136da558c3697c7f2a8d898a
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 21 20:24:43 2011 +0000

    some ifdef --> if fixes
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 305f2f50abe0360b10f2fef3d65a102912dade40
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 20 22:23:56 2011 +0000

    drop dead code from sb800 bootblock
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 685ee37a12f66f57b76e4be28fc59b30faa666da
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 20 21:14:05 2011 +0000

    drop excessive newline in uart8250.c
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bbd2f21184fdede46f7b6136bf0be47582236376
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 20 21:11:22 2011 +0000

    Simplify coreboot's console/console.h
    
    - shift most (romcc) code out of console.h into arch/x86/lib/romcc_console.c
    - rename arch/x86/lib/printk_init.c to .../romstage_console.c
    - drop FUNCTIONS_FOR_PRINT since __console_tx_* are already functions, so there
      should not be any side effects to eliminating another indirection.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42fa7fe28b60b448f501e99ee285a0af12c86d34
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 20 20:54:07 2011 +0000

    run uart_init() from console_init, just like the other console initialization functions.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8129f92c0cbd6a561195c1628ba3f9f98eccd50
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 20 09:12:17 2011 +0000

    Add Lenovo ThinkPad T60
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea3b58532a0b13cc8569ef3e1fb7a242ef4a8e79
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 20 09:05:37 2011 +0000

    PC87384: remove unused init function
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 81725b2effe9269e5079c6043077ba516e72aa82
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 20 08:58:38 2011 +0000

    pci1x2x: remove latency/bridge control/cacheline size settings
    
    Those settings should be handled by the generic PCI/Cardbus code,
    and not by the driver itself.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c72a8752bb5ce1c3b1bfb77c08039c71c2113ef
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 20 08:58:30 2011 +0000

    pci1x2x: use cardbus_read_resources()/cardbus_enable_resources()
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f22f303772ec55dbeeb817592678d0ee7777b62
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 20 08:58:16 2011 +0000

    pci1x2x: use pci_ops set_subsystem instead of custom code
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20f7f3bf913652d11e8d606471f7da213a7a7ffb
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 20 08:58:08 2011 +0000

    pci1x2x: add PCI1510 device IDs
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit baec0346b028d59c4ec226961d977bec0c57ed7e
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 20 08:57:53 2011 +0000

    pci1x2x: use devicetree register configuration
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b297b4901a5e7dd0aa037b184329a0e96722149e
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 20 01:08:25 2011 +0000

    drop dead uart init code.
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 012d867f731386309c5678d0d6636e4040b411c5
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Wed Apr 20 01:03:58 2011 +0000

    fix boards that still had some uart init remainders
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 13508b94cba913b94ba9afc8dc3d97313140152d
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Apr 19 21:33:40 2011 +0000

    Drop baud rate init to an arbitrary baud rate from Super I/O code.
    
    See discussion at
    http://www.mail-archive.com/coreboot@coreboot.org/msg29394.html
    
    config->com1, devicetree.cb cleanup and init_uart8250() removal
    will follow once this patch is comitted
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    Updated to drop com1, com2.... from config structure and devicetree.cb
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4fff74b69f9c1ad7f835e6545a71631c34a4ab09
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Apr 19 19:57:26 2011 +0000

    Lenovo PMH7: add pmh7_touchpad_enable()
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1571dc96372899c802e37e7d530acc2ba4848195
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Apr 19 19:34:25 2011 +0000

    Cast arguments to ctype(3) functions through (int)(unsigned char).
    
    Signed-Off-By: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-By: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6519 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4c50cb24576d962ef266cc6d24123c5ec0c5fae1
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Tue Apr 19 19:21:27 2011 +0000

    Fix compilation of all i82371eb boards when ACPI tables aren't generated
    
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b18f9b0ff47df16d076c17b0a5ce6e1957984562
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Apr 19 06:40:56 2011 +0000

    The "temp" will be used later. So it has to be calculated correctly.
    
    Comment by Peter,
    The variable name "temp" unfortunately does not explain what the value
    is. The commit message also does not have hints. Hopefully in the
    future it's possible to also use a brief moment to improve the clarity
    of the code, while it is already being fixed for some other
    reason. Ie. fixing up variable names, writing particularly informative
    commit messages, or of course both at the same time! :)
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52ffb2b66d3c7400f5338901129c3066913b3d54
Author: Scott Duplichan <scott@notabs.org>
Date:   Tue Apr 19 01:36:24 2011 +0000

    Recently the 3 projects using the new AMD reference code have been
    failing the check for globals (or statics) in romstage. This causes
    ASRock E350M1, AMD Inagua, and AMD Persimmon builds to fail with the
    message "Do not use global variables in romstage". The message is
    working as intended. It is detecting data declared as 'static' when
    'static const' was intended. The code executes correctly because it
    never tries to modify the data.
    
    To make reference code updates easy, it is probably best to avoid
    modifying the AMD provided code if possible. The following change
    bypasses the "Do not use global variables in romstage" check for
    the AMD reference code only.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6516 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 582748fbb35f930f1d40e62dc685b526f4ab74cc
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Apr 19 01:18:54 2011 +0000

    Fix some more misuses of ifdef/if defined
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 432461ec7fad51190cda33716b90f693de2a6ec6
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Apr 19 00:36:39 2011 +0000

    cleanup wrong use of defined() after exporting all variables in Kconfig
    
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b3ae1867d1a4b495a56078f521bebec9981f7494
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Mon Apr 18 23:51:12 2011 +0000

    * Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value
      to unify calls to *_enable_usbdebug()
    * rename *_enable_usbdebug() to enable_usbdebug()
    * move enable_usbdebug() to generic romstage console init code
      and drop it from the individual romstage.c files.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 261f842c1c3ce5e4ee151889f692a16856c400f3
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Mon Apr 18 02:26:56 2011 +0000

    fix copy and paste errors in ne2k.c
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebc93def5be132006c373d883c4b1b498b262a21
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Mon Apr 18 02:07:16 2011 +0000

    Emit unwritten symbols in Kconfig so we don't have to do constructs like
    #if defined(CONFIG_FOO) && CONFIG_FOO anymore. This was partially implemented
    but didn't work for symbols that were unset because of a missing dependency.
    
    Patch taken from SeaBIOS.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ee4c6f7c8028f9854442c08b61aa3436dca5ab36
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Apr 17 14:55:21 2011 +0000

    Lenovo H8 EC: add missing systemstatus.asl include
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b9d2ee6ca80a0ac9a946d3fad4efb884998622c
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Apr 17 12:54:32 2011 +0000

    PMH7: Add dock event control
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e67731011fa36a6f211ae150a38461664e6ccc0
Author: Stefan Reinauer <reinauer@google.com>
Date:   Sat Apr 16 00:13:17 2011 +0000

    Allow libpayload to use an OXPCIe 952 card on systems without
    onboard serial port
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Acked-by:  Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6508 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7163f1eb9a5461ba7a59c946d841a2b77b4932f
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sat Apr 16 00:09:53 2011 +0000

    bootblock updates:
    
    - allow CPU to define bootblock code, too.
    - drop unneeded __PRE_RAM__ define
    - move CBFS specific code out of bootblock_common.h into cbfs.h
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6aef5542f8f4c61c571055fe675170fa0d4deaa5
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 15 09:01:42 2011 +0000

    sorry for breaking the tree.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b77a73e40b1a88668cc16ca0b398e96c544b7c2e
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 15 04:12:03 2011 +0000

    comment cosmetics in bootblock.ld
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e50952f53294b3939f851c0feacaf13e31bc5a44
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 15 03:34:05 2011 +0000

    add FILO easy payload option
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d85400d80548d8db8dd604d959fe858d33ca39be
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 15 03:30:03 2011 +0000

    Handle drivers/ equally to any other sub directory.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8345a194ba30051d640c6d0340379b15696ea1a0
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Apr 15 00:19:27 2011 +0000

    fix mainboards that were including earlymtrr.c without actually using it.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24ef134b37131064a6f45a221b6478e55f0a38ca
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 14 22:28:00 2011 +0000

    drop half an uart8250 implementation from smiutil and use the common code
    for that instead. This also allows using non-uart8250 consoles for smi
    debugging.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 40e42a824b2800ed90614f3a5d3e5edf7cb877ff
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 14 21:05:41 2011 +0000

    fix coreboot compilation without serial console enabled.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23f49a82f9b6fca33c423aca8c779f1211847593
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 14 20:39:49 2011 +0000

    earlymtrr.c: wipe some dead code, use names instead of numbers and some
    cosmetics.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1fdfed1798259ad9e123e9329b9810033df0e3c0
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 14 20:33:53 2011 +0000

    add some comments to walkcbfs.S
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31853d8976ffd817bc773d559f104d2c42ed0c43
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 14 20:30:21 2011 +0000

    - drop remaining CONFIG_ROM_IMAGE_SIZE
    - re-enable .data section check for bootblock.
    - rename ldscript_fallback_cbfs.lb to bootblock.ld
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8902502c4ad04909c5fdfa7b7a3384bfb696731b
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 14 20:21:49 2011 +0000

    drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61089587640646022359c97e79aede4560566305
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 14 20:11:34 2011 +0000

    nvidia mcp55: drop unused dbg_info
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 28cd29192b750ae03665aabbef842504996b85b5
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 14 20:10:27 2011 +0000

    cosmetic cleanup of sis966 usb2 code
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 139e6f9555d6ff31c81ff6620bbe6214fa11b1e5
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 14 20:06:30 2011 +0000

    Use symbolic names for some MTRR bits instead of numbers in CAR code
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 528b43db32647c10d2d6b16b3585547bf3ab7b03
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Apr 14 19:52:04 2011 +0000

    coding style cosmetics.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14748a58d9a738f8582c52300e366349d107836c
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Apr 13 09:23:45 2011 +0000

    Lenovo H8 EC: add missing include for thermal.asl
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3e2f6790ed0e6dc81e39755e548f85f464d8a027
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Apr 12 18:18:24 2011 +0000

    Lenovo H8 EC: Set fancontrol to Automatic management
    
    My Notebook gets far to hot without fan, so just enable automatic
    fan control by default.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae08c56d6c43b9e5f2896164615a6c96562345df
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Apr 12 18:18:12 2011 +0000

    PC87384: add GPIO defines
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 484281b90f92b0ae4e226a090edecc026b37529c
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Apr 12 01:12:46 2011 +0000

    Use TOM2 for highest sysmem setting for northbound memory routing (DMA). This fixes 4GB memory issues.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Kerry she <kerry.she@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5005bb06c17461ef75cd1fef55c24dffaa05e580
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Apr 11 20:17:22 2011 +0000

    Unify use of post_code
    
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1fa61ebb3344105ae633ed7eb1be05cc574b666c
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Apr 11 19:43:50 2011 +0000

    PMH7: Add chip config
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ffcd1439f36ec27388139b9d5a379dd4294417b8
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Apr 11 19:43:32 2011 +0000

    EC: Add Lenovo H8
    
    Move the EC support code from the X60 mainboard to a generic
    driver, as this EC is used in many thinkpads. Also move the
    ACPI code to this directory for this reason.
    
    This patch also adds a chip config, so that the initial setting
    for basic register can be specified in devicetree.cb
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 18b02360b9dba6ca61538923e27b5ba68a2b3299
Author: Ruud Schramp <schramp@holmes.nl>
Date:   Mon Apr 11 07:46:27 2011 +0000

    Add detection/dump support for ServerEngines SE-SM 4210-P01.
    
    Note that the registers and their defaults are mostly based on educated
    guessing, due to the lack of datasheet.
    
    Signed-off-by: Ruud Schramp <schramp@holmes.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 148a4f5681263a24408d5988261bb3fd6b3c647e
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Apr 10 07:41:56 2011 +0000

    i945: improve get_top_of_ram()
    
    The current version doesn't honor TSEG, and fails to
    report the correct top of RAM if IGD is disabled. This
    is because it uses the BSM (base of stolen RAM) register.
    In that case, we should use the TOLUD register.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61aee5f4b1d596a0cb007e666df13094abed6d10
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sun Apr 10 04:15:23 2011 +0000

    In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.
    http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html
    
    It's about time we follow this advice.
    
    Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and
    drop unused CPP define
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df6fd566ba6f8541ee5611e57bfbab58b632a269
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Apr 5 13:00:33 2011 +0000

    X60: use pnp_write_config() instead of custom function
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b31eb3e4a82a8e81dbe7adf91492e80a8fd5b5f5
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Apr 5 13:00:14 2011 +0000

    X60: move ec version info code to log_ec_version()
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc608339545dc0561d1170e5a57b54b5bd74f3ea
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Apr 4 15:19:59 2011 +0000

    X60: assert audio mute before entering Suspend
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bdb10594aa4fcff3c2200224fb33052cbbe753be
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Apr 4 12:33:54 2011 +0000

    X60: log firmware version
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8099cbf76402e3ea6d5f8505426e4e224ead84cb
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Apr 4 10:57:17 2011 +0000

    X60: blink suspend LED during resume
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5fc5a80ce375a14cf69e8644a3a80821ce6d848d
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Apr 4 10:57:06 2011 +0000

    X60: we have ACPI_RESUME
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4678914d65ebbd5f37428ab57ff20009db28270e
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Apr 4 10:56:52 2011 +0000

    X60: deassert audio mute on boot
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b1d5d399f0594fdbb8b4dcf3fd569fe4beaff31f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Apr 1 07:41:47 2011 +0000

    remove swp files accidently added
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fea6bd16909a29854539c431497ccc460f3cdf7a
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Apr 1 07:28:56 2011 +0000

    X60: add dock code for Ultrabase X6
    
    Move the old docking code from romstage.c to dock.c, and use that code
    both in romstage and SMM code.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1aba09678913404826d7581f329bfa75d26cbdca
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Apr 1 07:28:50 2011 +0000

    Add GPIO definitions to PC87392 superio
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a539b6678661891cc750e71ffb3789cb32d0eec
Author: Sven Schnelle <svens@stackframe.org>
Date:   Fri Apr 1 07:28:35 2011 +0000

    ICH7: Fix register naming error
    
    There's an off-by-one error in the ACPI GP_LVL declaration:
    it declares GL00 with a bit count of 6, and continues with GP07
    afterwards. This should be GP06, as the first bitfield covers
    GP00-GP05.
    
    While at it, change it to GP00-GP05, as right now GL00 isn't used,
    and single bitfield are more usable here.
    
    Also adjust the Getac P470, as this is the only user of those defintions
    right now.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0df0b5256831609559514378bfd33ff35fcdea17
Author: Yang Hamo Bai <hamo.by@gmail.com>
Date:   Fri Apr 1 00:39:07 2011 +0000

    Add build instructions for coreinfo, specially pointing out installing
    gcc-multilib on a 64bit system.
    
    Signed-off-by: Yang Hamo Bai <hamo.by@gmail.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2633d272d45238aed170b1b14aa766edd0718ae0
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Tue Mar 29 19:29:01 2011 +0000

    Update repo path in libpayload readme.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3af120fd2b8ac9ed7bb80cccbb37452892bed1a0
Author: Prakash Punnoor <prakash@punnoor.de>
Date:   Tue Mar 29 12:02:03 2011 +0000

    Revert r6460, add full W83627DHG-P/-PT support instead.
    
    Add support for detecting/dumping the registers of Nuvoton W83627DHG-P/-PT.
    This is a different chip than the Winbond W83627DHG (different IDs).
    
    Signed-off-by: Prakash Punnoor <prakash@punnoor.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d69438e05ebc94f0de6df12b70e329cf76672b00
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Mar 29 09:01:10 2011 +0000

    BUILD: add missing config.h dependency
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 910f4ca5c50ef9d1d05c46b3ff52c69d29f745dd
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Mar 28 04:38:14 2011 +0000

    Add support for Supermicro H8scm.
    It is AMD C32 + SR5650 + SP5100.
    It is created by svn copy amd/tilapia_fam10.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d3de3eed7b64ac2a8e37a7c7eec13f76965ff97c
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Mar 28 04:36:21 2011 +0000

    Add the SR5650 & SP5100 to the Kconfig and Makefile.inc
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ca2f177245fdfa34ae7bd732052c8984e2b8b7d
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Mar 28 04:29:14 2011 +0000

    Add AMD C32 support.
    It is based on other existing Fam10 code.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3422235b14d97c16bd13113c522827d1cfda9b4
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Mar 28 03:33:10 2011 +0000

    SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx.
    Since the SB700 has changed to sb7xx_51xx, change legacy name in
    other mainboard.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98fcc09cf9955e24376d15f6fe13f02545547276
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sun Mar 27 16:39:58 2011 +0000

    Add AMD SR56x0 support.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a281880a36967361e7eb39056c4ff228f97c9a3
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sun Mar 27 16:33:09 2011 +0000

    This is for board Supermicro H8scm. The code was done by existing chips and
    superiotool.
    
    WPCM450 is more like an EC. SuperIO is just a part of multi-features.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fde7025b611c58888fca4f6ba6444708930b9107
Author: Prakash Punnoor <prakash@punnoor.de>
Date:   Fri Mar 25 16:54:38 2011 +0000

    I noticed some registers of Winbond W83627DHG, which the datasheet mentions, were not dumped by superiotool. This patch adds those registers to the dump.
    
    
    Signed-off-by: Prakash Punnoor <prakash@punnoor.de>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 13c16cbd68e876392c6022362f1153878a95d96a
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Mar 22 13:40:09 2011 +0000

    libpayload: Fix documentation
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0446f9630b85e9431d7d428c34623e36cc753b24
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Mar 21 14:43:21 2011 +0000

    X60: Add notification for LID objects
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e10699905e793e33bb2f18aa98a301358b524901
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Mar 21 14:43:09 2011 +0000

    X60: remove beep call from _Q26/_Q27
    
    no need to trigger sound, the EC takes care of generating the annoying
    AC state beep if enabled in the sound mask.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e6de7069def0fabe3388d3bd078a3e575d4105bf
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sun Mar 20 19:34:05 2011 +0000

    BUILD: add -MMD to iasl cpp call
    
    Right now there are no dependency rules for compiling dsdt.asl.
    If ACPI code includes asl files, the dsdt isn't recompiled if any
    of those file is changed. Add the flags to the preprocessor call
    to have it generate the neccessary dependency rule.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4cf7879cf032fca11d14bda68ba250931acd3e62
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Mar 18 22:53:38 2011 +0000

    oops, one URL fix was missing. Add new DirectHW URL
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cff573d3a455c20d427e70db84fd2acfe59194d1
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Mar 18 22:08:39 2011 +0000

    DirectHW fixes for coreboot utilities
    
    See http://www.coreboot.org/DirectHW for more information
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a46e89c757c17f625505ab7cbc6c3c18751e22a
Author: Marc Jones <marcj303@gmail.com>
Date:   Thu Mar 17 23:14:24 2011 +0000

    Fix breaking the build after removing files in tthe previous checkin.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c2fb60bfc463906ef07933d5b60f5c5b989a29c
Author: Frank.Vibrans <frank.vibrans@amd.com>
Date:   Thu Mar 17 22:19:45 2011 +0000

    Perform cleanup and file shrinkage of the AMD AGESA code.
    
    Signed-off-by: Frank.Vibrans <frank.vibrans@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea1c0a714d3916aafd053e22b76ca90dfbdad199
Author: Josef Kellermann <seppk@arcor.de>
Date:   Thu Mar 17 12:34:15 2011 +0000

    Fix power_on_after_fail handling on AMD SB600
    
    Bit 0 of pm reg#74 have to be set turn on system after power resumes.
    See '42661_sb600_rrg_nda_3.02.pdf' (or '46155_sb600_rrg_pub_3.03.pdf')
    for details, look for 'PwrFailShadow'.
    
    [Patrick: I didn't include the get_options reorganization as get_option
    doesn't overwrite "on" if power_on_after_fail isn't found in CMOS.
    Style changes were also left out.]
    
    Signed-off-by: Josef Kellermann <seppk@arcor.de>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3eb5e4e9a363b090e957bbf4e3b1d170f3c71022
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Mar 17 12:20:04 2011 +0000

    libpayload: fix string-to-numeric functions for base > 10
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8e9ba9a7af6e5563de9f284d70812e3fb3e75b8
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Mar 17 07:47:49 2011 +0000

    More complete control over KERNELVERSION variable
    
    Allow using revision information (from svn or git) even if the version
    number is changed on the command line (eg. make KERNELVERSION='11.03$(REV)')
    or dropping it entirely if having that information in the coreboot binary is
    not desired.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 08827287d65faa50cdd7db96c41d830a48f07fce
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Mar 15 09:52:17 2011 +0000

    X60: Clear EC events when wake GPE is triggered
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9a0b927f5dceeba7bb1d1fff94569343da98835
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Mar 15 09:52:07 2011 +0000

    ACPI EC: add ec_query function
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 07ca1c47b20e968ff4dce64192f0b10adeb0c488
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Mar 14 15:23:44 2011 +0000

    X60: LPC bus is LPCB, not LPC
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 91c31dac0c4a2c1c865d2379aa74237389353c22
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Mar 14 14:26:41 2011 +0000

    X60: fix typo in dsdt.asl
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b188a9309d265e4dd2965c874831df32875e49b9
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Mar 14 13:42:08 2011 +0000

    X60: Add _PRW/_PSW methods to LID/SLPB objects
    
    This patch adds the required methods for enabling/disabling
    the LID and SLPB objects as wake source. On Thinkpads, the
    Fn key can (and is by the Vendor BIOS) programmed as Wake source,
    so let's do it the same way.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9018b6ee641407703a0c3967356a07d50f6bb4b5
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Mon Mar 14 09:08:27 2011 +0000

    msrtool: Update to use DirectHW on Mac OS X
    
    http://www.coreboot.org/DirectHW
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0238a9caa3c6bc4cbc084b350f5cc016dc24178d
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Mar 14 08:18:27 2011 +0000

    ec/acpi: make ACPI register pair configurable
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d94d7c4a7305712478071250bda88eba9ad30d8
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Mar 14 08:18:17 2011 +0000

    ACPI EC: add ec_set_bit() / ec_clr_bit()
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 155c379b747e14ee181794d6ee460495886bee14
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Thu Mar 10 07:52:02 2011 +0000

    nvramtool: Move code so it has access to the right data structures
    
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 314dd0bee5f995164c0206798486cfce366160eb
Author: Scott Duplichan <sc...@notabs.org>
Date:   Tue Mar 8 23:01:46 2011 +0000

    Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF.
    
    The patch makes these changes:
    
    1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15
       romstage.c files where it is used (AMD family 10h projects).
    2) Add a prototype to amdfam10.h.
    3) Modify the swap list and test in real hardware for mahogany_fam10 and
       kino family 10h and confirm HT3 operation for the SB link.
    
    Abuild tested.
    
    Signed-off-by: Scott Duplichan <sc...@notabs.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57205c7e43e1ec3d4d62ea86e33c7acb7dbad81d
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Mar 8 20:49:18 2011 +0000

    Add option_table.h as dependency for all C based object files if option tables are used.
    
    This is to make sure that the file exists when it is needed. While this isn't the case for every C source file, it doesn't hurt either to create the file a bit sooner than strictly necessary.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 943b8b599758016380939b76394ab1b2cf913258
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Tue Mar 8 12:58:16 2011 +0000

    nvramtool: Change precedence order for data sources
    
    nvramtool couldn't handle certain combinations of sources for CMOS
    layout and CMOS data. This change allows for nearly all combinations.
    
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fab35e3f73ba149eb109c24a8f906347b877d2ea
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Mar 8 07:50:43 2011 +0000

    Move cmos.default handling to bootblock
    
    The cmos.default code wasn't actually used so far, due to an oversight
    when forward-porting this feature from an old branch.
    
    - Extend walkcbfs' use by factoring out the stage handling into C code.
    - New sanitize_cmos() function that looks if CMOS data is invalid and
      cmos.default exists and if so overwrites CMOS with cmos.default data.
    - Use sanitize_cmos() in both bootblock implementations.
    - Drop the need to reboot after writing CMOS: CMOS wasn't used so far,
      so we can go on without a reboot.
    - Remove the restriction that cmos.default only works on CAR boards.
    - Always build in cmos.default support on boards that
      USE_OPTION_TABLE.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85e666dc37183c491227b794debb24e03a909ac1
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Mar 7 09:09:51 2011 +0000

    X60: add thermal zone 1
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b641e98839b3310f46f822c7d5947cce33f7b622
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Mar 7 09:00:50 2011 +0000

    X60: add thermal zone 0
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5fb8fc093ffe9c9d6a755a258c190985ab4e2674
Author: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Date:   Sun Mar 6 17:58:31 2011 +0000

    Add support for the NSC PC87364 Super I/O.
    
    superiotool -deV output:
    http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html
    
    Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09b36291f724c73eb709d58402fae0813a096e72
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Fri Mar 4 20:01:15 2011 +0000

    Add P-states for select Socket 754 processors.
    
    States for AMA3000BEX5AR, SDA3100AIO3BX, and SDA3400AIO3BX
    are from AMD document 30430 3.51.  States for ADA3200AIO4BX
    derived from SSDT of a MS-7135.  States for TMDML34BKX5LD derived
    from legacy PowerNow! table of a MS-7135, and therefore lack accurate
    TDP information.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9a08ddafdc647447d59f91e41b8e32493eb8c03
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Mar 4 17:09:21 2011 +0000

    Redo r6099 after copy&pasted code reintroduced DIMMx #defines
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d5782f3588f402124a2659e9027f249a8eceb7c2
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Thu Mar 3 23:09:43 2011 +0000

    Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code.
    With this change the last P-state entry of the last CPU in the table
    is successfully conveyed into the SSDT.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fadb0043593dcee6f8b4d3a820894b2aca67bd80
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Thu Mar 3 20:52:50 2011 +0000

    Improve ck804 IOAPIC and HPET resource handling.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a73ffa0a3ee65714184579e2c3408a95a6fa376d
Author: jakllsch <jakllsch@kollasch.net>
Date:   Thu Mar 3 15:36:08 2011 +0000

    Configure PCIe lanes on ms7135 as original BIOS does.
    
    Signed-off-by: <jakllsch@kollasch.net>
    Acked-by: <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 071d8359766c198c9656fb36fa65df69c667e057
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Mar 3 08:29:03 2011 +0000

    add PC87384 SuperIO
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b9bbeeed8e1b798d34d531eb4ac0321f6ef1162
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Mar 2 19:56:28 2011 +0000

    Fixes licensing of src/southbridge/via/k8t890/k8x8xx.h to GPLv2+ from GPLv3.
    
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 82419413b108d33a265aa2c82623c2a307692cb9
Author: Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
Date:   Tue Mar 1 22:02:37 2011 +0000

    Fix some subsystemid statements in r6421
    
    Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5325a48340158d1251a55d54eb437a695fdc428a
Author: Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
Date:   Tue Mar 1 21:57:11 2011 +0000

    [SCONFIG] remove unused variable in inherit_subsystem_ids()
    
    i is a leftover from debugging, no longer needed. So just remove it.
    
    Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8269e211134860785d103493a8de6d596dfa913
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Mar 1 21:51:29 2011 +0000

    Fix a simple whitespace error in src/include/device/device.h
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    Reported-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 750edfd88c26423edf6c2526d83e6839a9809ecb
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Mar 1 21:43:57 2011 +0000

    Add lex output
    
    lex.yy.c_shipped wasn't committed in r6420, which breaks the build
    if you don't have the expert option checked that rebuilds those files.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Sven Schnelle <svens@stackframe.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 91321028ec3fac017e8e2c47ec5fe7742409b3b0
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Mar 1 19:58:47 2011 +0000

    Use subsystem id from devicetree.cb instead of Kconfig and move
    all boards to the new config scheme.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 270a908646273461b41e591739d778d3d675ff6f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Mar 1 19:58:15 2011 +0000

    Add subsystemid option to sconfig
    
    Allow user to add 'subsystemid <vendor> <device> [inherit]' to devicetree.cb for
    PCI and PCI domain devices.
    
    Example:
    
    	device pci 00.0 on
    	       subsystemid dead beef
    	end
    
    If the user wants to have this ID inherited to all subdevices/functions,
    he can add 'inherit', like in the following example:
    
    	device pci 00.0 on
    	       subsystemid dead beef inherit
    	end
    
    If the user don't want to inherit a Subsystem for a single device, he can
    specify 'subsystemid 0 0' on this particular device.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e38d0a6743aab8bde432e97c48c147fea5b30363
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Mar 1 08:09:22 2011 +0000

    Fix double inclusion of toplevel Makefile.inc
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 11ac1cfaa30bff3162d9f857d0269e28d900d281
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Mar 1 07:30:14 2011 +0000

    Mark non-returning function as noreturn to help some compiler versions
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6eb6a7c8d57969cde6db50072ac4e1a241f6ade7
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Mar 1 07:26:00 2011 +0000

    libpayload: Add more libpci-compatibility (#defines)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb2d29ec75667eeccc793bcd786207a38b1cc1a7
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Mar 1 07:24:53 2011 +0000

    libpayload: Implement pci_cleanup()
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d08996e81f9b70b089c1648c038f035afc3511fc
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Mar 1 07:23:49 2011 +0000

    libpayload: Implement ffs()
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa622fcc5a27e58201d148263a7cb08e1a9da08a
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Mar 1 07:13:10 2011 +0000

    Some more standard types and defines (libpayload)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b1eab1495ce1164df189aaf6b9990afe051ee1ae
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Mar 1 07:12:08 2011 +0000

    Add lib/ to the default library path of lpgcc, so -l works
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d175f44139d07d07db3595658d02adcd3e4090c4
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Feb 28 18:09:58 2011 +0000

    add functions to set Subsystem Vendor/Device to rl5c746
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b6711723208e35451f1f65910a50e8c2a3f6eb3b
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 03:59:34 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    I don't understand what this was doing nor find docs for these regs
    Maybe it was left over from some copy & paste ?
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6bdc83bf5e76aa0b36cb5f52c11544091d71770b
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 03:56:52 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    I don't understand what this was doing nor find docs for these regs
    Maybe it was left over from some copy & paste ?
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 061c89e15d336b92b1e9fb2f9866c32f6496fb09
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 03:53:47 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    I don't understand what this was doing nor find docs for these regs
    Maybe it was left over from some copy & paste ?
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3132105bdd35ba174cd0938847ebf292e2eda26
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 03:49:28 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    In fact I changed coreDelay before deleting
    the code in fidvid that called it. But there're
    still a couple of calls from src/northbridge/amd/amdmct/wrappers/mcti_d.c
    Since the comment encouraged fixing something, I
    parametrized it with the delay time in microseconds
    and paranoically tried to avoid an overflow at pathological
    moments.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6276b6f151e050f0470fa7f1c5a2d73ff3f65282
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 03:35:43 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    bits 13 - 15 of F3xd4 (StutterScrubEn, CacheFlushImmOnAllHalt and MTC1eEn
    are reserved for revisions D0 and earlier, so whe should not set them
    to 0 in fidvid.c config_clk_power_ctrl_reg0(...), called from prep_fid_change.
    For revisions > D0 (when we support them) it is ok not ot clear them,
    because they are documented as 0 on reset. bit 12 should be left alone
    according to BKDG. Should I set 11:8 ClkRampHystSel to 0 in the mask
    too, just to indicate we're touching them ? We'll OR them to 1111 anyway...
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 82b241a2b5e38046a519673264c47c64d4c85728
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 03:32:23 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    Well, I understand it better like this, but maybe
    it's only me, part of the changes are paranoic, and
    the only effective change is for a factor depending on
    mobile or not that I can't test.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5bcedee0f88fa6390d84f2641dc5b3e109cf6ea3
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 03:25:07 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    Add an untested step in BKDG 2.4.2.8. I don't
    have the hardware with Core Performance Boost and
    I think it's only available in revision E that does
    not even have a constant yet.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce62350d8f5a619c9ce754caeb1e33224e0cce56
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 03:19:17 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    Add to init_fidvid_stage2 some step
    mentioned in BKDG 2.4.2.7 that was missing . Some lines
    are dead code now, but may handy if one day we support
    revison E CPUs.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e80ce0a134bc88581db40b02ce250bee5adba3a3
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 03:12:00 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    Add to init_fidvid_stage2 some step for my CPU (rev C3)
    mentioned in BKDG 2.4.2.6 (5) that was missing
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26f97d2cf9542694f337abf6ce35fe52b23e5108
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 03:08:06 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    Looking at BKDG the process for updating
    Pstate Nb vid after warn reset seemed
    more similar to the codethat was there fo
    pvi than the one for svi, so I called the
    pvi function passing a pvi/svi flag. I don't
    find documentation on why should UpdateSinglePlaneNbVid()
    be called in PVI, but since I can't test it,
    I leave it as it was.
    
    This patch showed some progress beyond fidvid in my
    boar,d but only sometimes, most times it just didn't
    work.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 19245c94c8d8e293fdb7e4c734ef0abccf601ca2
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 03:02:40 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    Factor out some common expressions.
    Add an error message when coreboots hangs waiting for a pstate
    that never comes (it happened to me), and throw some
    paranoia at it for good mesure.
    
    If I understood BKDG fam10 CPUs never need a software initiated vid transition,
    because the hardware knows what to do when you just request
    a Pstate change if the cpu is properly configured. In fact
    unifying a little what PVI and SVI do was better for my board (SVI).
    So I drop transitionVid, which I didn't understand either (why
    did it have a case for PVI if it is never called for PVI ?
    Why did the PVI case distinguigh cpu or nb when PVI is
    theoretically single voltage plane ? ).
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cbcf1ada4ac32b3fb638b0a002f9cb7ae003072
Author: Marc Jones <marcj303@gmail.com>
Date:   Mon Feb 28 02:36:15 2011 +0000

    Kino devicetree.cb SIO PNP  devices were not matched up with the
    actual SIO. This fixes the serial device  being disabled during PNP
    init.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Scott Duplichan <scott@notabs.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e485aa496b2230226abf2255837b9e1d422e9b42
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 02:33:59 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    Contemplate the possibility of nbCofVidUpdate not being
    defined, trying to get closer to BKDG
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6fcc961fe846aca897480bb637142d50914a4ea7
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 00:31:24 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    Configuration of F3x[84:80] was hardcoded for rev B.
    I change that for some code that checks for revision
    and configures according to BKDG. Unfinished but
    hopefully better than it was.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f93fea160fff042f7d5467c56eaf2fc0286995f
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 00:24:21 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    BKDG says nbSynPtrAdj may also be 6 sometimes.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e5d3e16b494aafa3c08a28a0484ee0845d84512
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 00:18:43 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    I didn't understand quite why it did that iwth F3xA0 (Power
    Control Misc Register) so I moved Pll Lock time to rules in defaults.h
    and reimplemented F3xA0 programming. A later patch will remove
    a part I don't know what's mean to do.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit adb23a51f5f711d10798a0bcddf4764a5dc0ae7c
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 00:10:37 2011 +0000

    Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode.
    
    Bring F3xD4 (Clock/Power Control Register 0) more in line
    with BKDG i more cases. It requires looking at the CPU package type
    so I add a function for that (in the wrong place?) and some
    new constants
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f4fffb9ccaa3d145b66ddc3e57109cfe8f9fef7
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Feb 28 00:00:51 2011 +0000

    Prepare for next patches (Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode).
    
    No change of behaviour intended.
    
    Refactor FAM10 fidvid . Factor out the decision whether
    to update northbridge frequency and voltage because there
    was the same code in 3 places and so we can later modify it
    in one place.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7ef421eadd84141334d09e1a044645bef1dbf28
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Feb 27 23:58:34 2011 +0000

    Prepare for next patches (Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode).
    
    No change of behaviour intended.
    
    Refactor FAM10 fidvid . Factor out the decision whether
    to update northbridge frequency and voltage because there
    was the same code in 3 places and so we can later modify it
    in one place.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d26e5e6bb3209f195ef9cacdda1b18525f30fa62
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Feb 27 23:56:00 2011 +0000

    Prepare for next patches (Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode).
    
    No change of behaviour intended.
    
    Refactor FAM10 fidvid. Factor out a little common code.
    Also, our earlier  config_clk_power_ctrl_reg0
    was still too long and it'd get longer with forthcoming patches.
    We now take apart F3xD4[PowerStepUp,PowerStepDown]
    to its own function.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 40f9b4b07e98f35336458cdc7a9a6257fb842470
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Feb 27 23:53:11 2011 +0000

    Prepare for next patches (Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode).
    
    No change of behaviour intended.
    
    Refactor FAM10 fidvid . prep_fid_change was already long and it'd
    get longer with forthcoming patches. We now take apart F3x[84:80],
    ACPI Power State Control Registers, to its own function.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d80e5101772220213f64a8845b21fa063710995
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Feb 27 23:50:30 2011 +0000

    Prepare for next patches (Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode).
    
    No change of behaviour intended.
    
    Refactor FAM10 fidvid . prep_fid_change was already long and it'd
    get longer with forthcoming patches. We now take apart F3xDC[NbsynPtrAdj],
    Northbridge/core synchronization FIFO pointer adjust, to its own function.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9683b1deb2b4489247418c477eb6a5ad59fa0bd1
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Feb 27 23:47:57 2011 +0000

    Prepare for next patches (Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode).
    
    No change of behaviour intended.
    
    Refactor FAM10 fidvid . prep_fid_change was already long and it'd
    get longer with forthcoming patches. We now take apart F3xA0,
    Power Control Misc Register to its own function.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a5cbd25e48b5e33726ff7f7a193b10622207fd22
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Feb 27 23:45:34 2011 +0000

    Prepare for next patches (Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode).
    
    No change of behaviour intended.
    
    Refactor FAM10 fidvid . prep_fid_change was already long and it'd
    get longer with forthcoming patches. We now take apart F3xD4,
    Clock Power/Timing Control 0 to its own function.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d7294596218addf11feefb4cb2411eb7729b5b11
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Feb 27 23:42:58 2011 +0000

    Prepare for next patches (Improving BKDG implementation of P-states,
    CPU and northbridge frequency and voltage
    handling for Fam 10 in SVI mode). No change of behaviour intended.
    
    Refactor FAM10 fidvid . prep_fid_change was already long and it'd
    get longer with forthcoming patches. We now take apart VSRamp in step b
    of 2.4.1.7 BKDG to its own function.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 70a373315513244266024c3591dc9db103f7ace1
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Feb 27 02:48:41 2011 +0000

    Add 300 MHz and 500 MHz HT frequency limits
    
    Needed to build successfully with Expert mode enabled.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4c28a6f01870e017dbedb4a0bba1e91148077040
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sat Feb 26 23:29:44 2011 +0000

    Make AMD Fam10h CPU microcode updates optional in Expert mode
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 837403dddf7b05b1a2b1a09a2cd57975484c7568
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Feb 26 19:46:08 2011 +0000

    Following patch fills in the callbacks for PCIe x16 resets. This board uses GPM8,GPM9 as reset toggles.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 656060d1d944c4deab16102fffb7f3d2806574f7
Author: Scott Duplichan <scott@notabs.org>
Date:   Sat Feb 26 18:42:04 2011 +0000

    Correct error in ASRock E350M1 commit that breaks build for ASRock 939a785gmh.
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 63896e75b42697a8898c0386c492091318cf5c82
Author: Scott Duplichan <scott@notabs.org>
Date:   Sat Feb 26 17:49:49 2011 +0000

    Add support for the ASRock E350M1, an AMD family 14h Fusion board.
    A video option rom must be added for UMA graphics support. It can
    be extracted from the supplied UEFI BIOS.
    
    ASRock E350M1 support is based on the AMD persimmon project. The
    major differences are SIO model and DIMM SDP addressing. With this
    coreboot and seabios, the board can boot DOS from a SATA drive and
    can boot WinPE from a USB flash drive. I was unable to get
    Windows setup to run.
    
    The board has a socketed SPI flash BIOS chip and a serial port
    header. The SIO is Nuvoton NCT5572D. Using coreboot's existing
    Winbond w83627hf is a good enough match to get the serial port
    and keyboard working.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 199c694f49e2ecbc3bd2cc6c5e7d7570a4c3cf62
Author: Rudolf Marek <r.marek@asssembler.cz>
Date:   Sat Feb 26 13:34:01 2011 +0000

    It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
    
    Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG.
    
    Signed-off-by: Rudolf Marek <r.marek@asssembler.cz>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed1d116e62b57b9c5c8746d17ecbf842845d4be2
Author: Josef Kellermann <seppk@arcor.de>
Date:   Thu Feb 24 14:35:42 2011 +0000

    Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS
    
    This affects the CMOS options iommu, ECC_memory, max_mem_clock,
    hw_scrubber, interleave_chip_selects.
    If they're absent in cmos.layout, a Kconfig value is used if it exists,
    or a hardcoded default otherwise.
    
    [Patrick: I changed the ramstage CMOS handling a bit, and dropped the
    reliance of hw_scrubber on ECC RAM, as it has nothing to do with it -
    it's the cache that's being scrubbed here.]
    
    Signed-off-by: Josef Kellermann <seppk@arcor.de>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 855224bb28031bd3d51fa53201fcd7efdd235ec6
Author: Josef Kellermann <seppk@arcor.de>
Date:   Thu Feb 24 13:54:10 2011 +0000

    Add new option 'sata_mode' to CMOS and 'SATA_MODE' to Kconfig for AMD SB600
    
    coreboot used to set the chipset to IDE mode unconditionally.
    Now, the user has a couple of ways to choose the configuration:
    - If a CMOS variable sata_mode exist, it is used to decide if IDE or
      AHCI is to be used as interface.
    - If not, a Kconfig option is used.
    - If unchanged, the Kconfig option is set to IDE.
    
    So unless the cmos.layout is extended or Kconfig is modified, this won't
    change behaviour.
    
    [Patrick: Compared to Josef's version, I changed the Kconfig option to
    be boolean, instead of a magic string. Also, the "IDE" default is
    handled in Kconfig, instead of an additional line of code.]
    
    Signed-off-by: Josef Kellermann <seppk@arcor.de>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20bd19619e8b394ef8d2befb0996bdebad2727f4
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Feb 24 07:43:37 2011 +0000

    Tyan/s2735 doesn't need to define its own hard_reset function anymore.
    
    The southbridge already provides hard_reset.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c977c7df7189c251ccfb7d0ed09178833f779809
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Feb 24 07:18:11 2011 +0000

    libpayload: Move stdin/stdout/stderr away from headers
    
    Otherwise they exist in several object files, confusing the linker
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a649a96efe9cf345ade3e7a0463507f9e4360ef0
Author: Scott Duplichan <scott@notabs.org>
Date:   Thu Feb 24 05:00:33 2011 +0000

    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71b8480921731c20521b80acae2db9d622acfa05
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Feb 22 14:35:05 2011 +0000

    Move coreboot specific rules and setup to toplevel Makefile.inc
    
    KERNELVERSION issue found by Stefan is fixed.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6375 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 541269bc85b7d63b7660cd299e70335a52d5fdf4
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Feb 21 09:39:17 2011 +0000

    [i945] Add SPD adress mapping
    
    The current code works only with dual channel if Channel 0 uses SPD address
    0x50/0x51, while the second channel has to use 0x52/0x53.
    
    For hardware that uses other addresses (like the ThinkPad X60) this means we
    get only one module running instead of both.
    
    This patch adds a second parameter to sdram_initialize, which is an array with
    2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single
    DIMM socket. If NULL is given as the second parameter, the code uses the old
    addressing scheme.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0c8e664713d4dc726bedb5ba0b2e356eed9ae14c
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Feb 19 14:51:31 2011 +0000

    It turns out that the code which enables specific LDN is somewhat buggy.
    Instead of enable the device the device gets disabled. However after some time the serial line gets back, most likely some "enable resources" might fix it.
    I'm attaching patch which somewhat fixes the problem and changes the function to look same in all superio code. Some boards even did not convert the dev->enabled to 0,1 values.
    
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8cdd9b4506309ced1529862d7598131a5cb4ea7
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Feb 17 20:48:45 2011 +0000

    Handle compiler options for source classes more generically
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 58262656c6caa6df0bf51a45f6b1d29a47ccaad5
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Feb 17 20:47:49 2011 +0000

    Make Makefile.inc parser loop more generic
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b159f7ab37c480e54bf3593e2e1cb880f6f8ef84
Author: David Hendricks <dhendrix@google.com>
Date:   Thu Feb 17 00:52:02 2011 +0000

    add mec1308 support to superiotool
    
    This patch also disables FDC37M81x since it has a conflicting device ID
    and is not supported very well anyway.
    
    Signed-off-by: David Hendricks <dhendrix@google.com>
    Acked-by: Stefan Reinauer <reinauer@google.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 650cf237ac4e314d168fbe23fe8fceb9c192849b
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Feb 16 17:40:04 2011 +0000

    Fix build errors introduced in r6367
    
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e8a7df84ad6db044647cd34d2b6e1e030c17774c
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Feb 16 15:04:59 2011 +0000

    Add ACPI code for Lenvo X60
    
    It currently supports:
    
    - Sleepbutton
    - AC state
    - Battery state
    - Interrupt routing
    - Display Brightness control
    - Hotkeys
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 025ead7792eebd8c088c9e913c2224bca5918435
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Wed Feb 16 13:43:00 2011 +0000

    Extended K8T890 driver to include the K8T800 and K8M800 northbridges
    
    The K8T800 is almost identical to the K8T800Pro, also added to this patch.
    The K8T800_OLD is also defined, which is an older version of the K8T800,
    but which has no driver and early HT code yet. Also extended the K8M890 VGA
    driver to work for the K8M800 (not tested). According to the datasheet, the
    K8T890 and K8T800 are similar enough to be able to use the same
    initialization code. At least for the K8T800, this is sufficient to have
    a working HT link with the CPU, and to initialise the V-Link to the
    southbridge.
    
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ddb3f0adaa0cc1a0a0dfa8b46eeee5c3d2dbca9e
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Feb 16 13:12:41 2011 +0000

    Lenovo ThinkPad X60: Enable SMI handler
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7afbb9936f0dcbb86d46fb8ff52f7e87e3d72dc3
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Feb 15 13:07:32 2011 +0000

    Remove more files and lines mistakenly copied from Roda to X60
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d5966deb2b6f55ef5d6828e8d52a9bb23a118fb
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Feb 15 11:14:17 2011 +0000

    Remove ACPI mistakenly copied from Roda to ThinkPad X60
    
    It is incorrect, and will be replaced with proper ACPI for X60.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c427a7a4a8b7681d4af60ba072d40583f08fc22
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Feb 15 00:27:24 2011 +0000

    Remove Inagua Kconfig items for external VGA and AHCI binaries. These can be addded by the developer if needed.
    
    Fixes abuild issues.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd6c1e67f6313e55191c1b4ed2746a21c340fa20
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Feb 15 00:23:05 2011 +0000

    SERIAL_POST was renamed to CONSOLE_POST a while ago
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f58b63d6dc30e9400002fd0e791948a6be4384ef
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Feb 15 00:14:32 2011 +0000

    use git.seabios.org for checking out seabios.
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e2ca71efd903a76426b754d4b385fac4a7947390
Author: Sven Schnelle <svens@stackframe.org>
Date:   Mon Feb 14 20:02:47 2011 +0000

    Lenovo ThinkPad X60 / X60s Support
    
    Adds support for Lenovo X60 series ThinkPads. So far, only X60s
    (Model 1703) has been tested.
    
    It's a basic patch without SMI and ACPI, as this makes it easier to
    review. SMI and ACPI patches will follow.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9122895731212b991e1ef7a2b6acb791db73d91
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Feb 14 19:26:22 2011 +0000

    Use fprintf(stderr, ...) in library
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd913bdf5c995fb3768aaaaeec364e7f5527e4e9
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Feb 14 19:25:27 2011 +0000

    Stub out FILE*, stdout/stdin/stderr and implement fprintf on these
    
    - Add FILE*
    - Add stdout, stdin, stderr stubs
    - Add fprintf that redirects to printf for stdout and stderr and fails otherwise
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4a022c9418096ae7f6e8074dcd917ff68294e8e
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Feb 14 19:24:37 2011 +0000

    lpgcc was too noisy in some cases
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6b5ca4efb9273f91d839383b1cb59f6747e02f3d
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Mon Feb 14 19:23:33 2011 +0000

    Some more POSIX compatibility
    
    - Add assert.h
    - Add arpa/inet.h
    - Add assert macro
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f0ccf6ed18bc128f657d72e6695aaeba3101922f
Author: Josef Kellermann <seppk@arcor.de>
Date:   Mon Feb 14 19:21:28 2011 +0000

    Errata #169 works on HT, not MC
    
    Signed-off-by: Josef Kellermann <seppk@arcor.de>
    Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cf37a5942fc4aecb8ceb71baf983eb29cc131da9
Author: Josef Kellermann <seppk@arcor.de>
Date:   Mon Feb 14 19:19:58 2011 +0000

    Removed LPC DMA Deadlock workaround...
    
    Setting bit#21 in k8_f0#68 is part of the errata#169
    which is handled in amdk8/coherent.c
    
    Signed-off-by: Josef Kellermann <seppk@arcor.de>
    Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 144fe883388c54589cf6cfe6a7a879b4e7e6dd50
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Feb 14 19:15:36 2011 +0000

    Fix Typo. (and why is that file, and some of its siblings per-board?)
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69da1b676cd3f126b27a6fd3c23c557ac1a03961
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Mon Feb 14 19:04:45 2011 +0000

    Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8.
    
    This code provides support for IBASE Technology DB-FT1 (AMD code name Persimmon) and AMD Inagua platforms. It is dependent on all other patches in this set.
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b904d84ba4e4e40149a8dcb98ca518e3bc6b911
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Mon Feb 14 19:00:13 2011 +0000

    This code provides support for the superio chip on the AMD Inagua platform (not commercially available). It is independent of the AMD>code.
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6b4674e28978b1573d994b47f985ea98ad33a14b
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Mon Feb 14 18:56:10 2011 +0000

    I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347.
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d0a8ebf053375e10822acf043e2b01048663d371
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Mon Feb 14 18:52:15 2011 +0000

     This code provides support for the superio chip on the IBASE Technology DB-FT1 (AMD code name Persimmon) platform. It is independent of the  AMD code.
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0822ad8b1916e2461ef9e3af83e97ad1fcdac2ab
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Mon Feb 14 18:47:37 2011 +0000

    This code fixes a number of build issues related to the AMD Agesa code. The particular issues are global variables existing in romstage and the use of GCC intrinsics in the build. The former issue will be addressed shortly, and the latter issue requires community assistance. This code is dependent on the AMD Family 14h mainboard code.
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 420faca0d0152a70e9855b78e028efe5bd3e3448
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Mon Feb 14 18:42:12 2011 +0000

    Add AMD cpu wrapper code. Patch 4 of 8.
    
    This code provides cpu early initialization for Family 14h cpus. It is dependent on the AMD Agesa code.
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 63e62b03a8385663bebff3bdee88327bb57b27fd
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Mon Feb 14 18:38:14 2011 +0000

     This code provides southbridge initialization for SB800 south bridges. It is dependent on the AMD CIMx/SB800 code.
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39fca80b0015600f95131717a867ab3baaa2b7ad
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Mon Feb 14 18:35:15 2011 +0000

    This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code.
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b4c831b4d16b55a7abdea20bce82cccd168232c
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Mon Feb 14 18:30:54 2011 +0000

    Add AMD Agesa and AMD CIMx SB800 code.  Patch 1 of 8.
    
    This code currently generates many warnings that are functionally benign.  These are being addressed, but the wheels of bureaucracy turn slowly.  This drop supports AMD cpu families 10h and 14h.  Only Family 14h is used as an example in this set of patches.  Other cpu families are supported by the infrastructure, but their specific support is not included herein.  This patch is functionally independent of the other patches in this set.
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74ad66cdc143e04f976ba21e538e02b20362d7e6
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Feb 12 16:24:48 2011 +0000

    Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early only Serial/SIO/RTC.
    Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
    Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
    
    Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
    Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
    
    While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit daecb1888ee813978a1d177a02ffd394445966a9
Author: Scott Duplichan <scott@notabs.org>
Date:   Thu Feb 10 20:49:56 2011 +0000

    According to AMD documentation, cache type WP should be used for
    execution from flash memory. Coreboot uses WB. While there is no
    noticeable performance difference between the two settings, use
    of WB can cause a problem for a jtag debugger. The attached
    patch changes AMD cache as ram setting for flash execution from
    WB to WP.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20ecc5af40adbd63a3a55eefe7e53bd16412c712
Author: Josef Kellermannseppk <Josef Kellermannseppk@arcor.de>
Date:   Thu Feb 10 08:49:57 2011 +0000

    RS690: Provide support for MMCONF.
    
    If enabled, set up 0xe0000000..0xf0000000 as MMCONF
    area. Must still be configured in per-board ACPI for
    the OS to pick it up, so it's disabled by default.
    
    Signed-off-by: Josef Kellermann<seppk@arcor.de>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1df854248b60b93aef9e4c37bd6da95371a6d867
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Thu Feb 10 07:51:51 2011 +0000

    Implemented workaround for erratum 169, obsoleting erratum 131.
    Workaround for 131 removed.
    Changed workaround for erratum 110 to only include pre-revision-F
    processors.
    
    For details, check AMD publications:
    #25759 (Errata for Fam F pre-revision F processors)
    #33610 (Errata for Fam F revision F and later processor)
    
    Based on work and previous patches by:
    Rudolf Marek <r.marek@assembler.cz>
    Josef Kellermann <seppk@arcor.de>
    
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31e0deac0e8771a0c98d9463fd7caa101ffb3be1
Author: Josef Kellermann <seppk@arcor.de>
Date:   Thu Feb 10 07:48:07 2011 +0000

    Fix a potential system hang by handling AMD Model F Erratum 89
    a bit later.
    
    Signed-off-by: Josef Kellermann <seppk@arcor.de>
    Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b0c94a1866debb262ff1343674de871f6b770f3f
Author: jakllsch <jakllsch@kollasch.net>
Date:   Tue Feb 8 16:07:49 2011 +0000

    Add NetBSD support to nvramtool.
    
    Signed-off-by: <jakllsch@kollasch.net>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 167b79232744eea31d966bce4007d0a7c6d982ee
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Feb 8 08:37:47 2011 +0000

    Fix cmos-files-y for relative paths
    
    Thanks to Josef Kellermann <seppk@arcor.de> for reporting the issue.
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a038ca112f04312c233b6519c76572eaa1a57be
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Tue Feb 8 02:36:39 2011 +0000

    Place the W83627EHG MIDI base address mask in the correct position.
    Corrects "index 98 has no mask" error at runtime.
    
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b1d1c4d0840c74ebfa2ced0c56d492a075e4599f
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Feb 7 20:16:40 2011 +0000

    Reliably build arbitrary Kconfig-based revisions of SeaBIOS
    
    Reliability is accomplished by checking out the desired SeaBIOS commitish
    into a branch named 'coreboot' in the local SeaBIOS git repository. Using
    a branch allows TAG-$(CONFIG_SEABIOS_..) to refer to any commitish in the
    SeaBIOS git repo, not just branches and tags.
    
    Configuration is done with make defconfig followed by enabling and
    disabling of the relevant coreboot-specific SeaBIOS options by appending
    to .config using echo. This works, because later entries in .config will
    overwrite earlier ones.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1440d0880b76c67beb341d59ee7b4fcb39307f60
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Feb 5 13:32:56 2011 +0000

    Actually add PC87382 into Kconfig, missing from r6332
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 82e3617e8cdc4b035c6154f76bef1e3a4a79ab1c
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sat Feb 5 12:26:07 2011 +0000

    Add PC87392 support
    
    This adds support for the NSC PC87392 Super I/O. It is used in Lenovo
    Docking Stations as Super I/O chip.
    
    v2 because of:
    
    - skip some empty files
    - missing newlines in Kconfig and Makefile.inc
    - add the Kconfig option in sorted order
    
    Thanks to idwer on irc for pointing that out.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 92cf08c8f39869b619bd1129230df9e5174ba3f5
Author: Sven Schnelle <svens@stackframe.org>
Date:   Sat Feb 5 12:20:23 2011 +0000

    Add PC87382 support
    
    This patch adds support for NSC PC87382 Super I/O. It is used in many
    Lenovo Notebooks as Docking LPC Switch.
    
    v2 because of:
    
    - Skip some empty files
    - Fix newlines in Kconfig and Makefile.inc
    - chip.h missed uart8250.h include
    - add the Kconfig option in sorted order
    
    Thanks to idwer on irc for pointing that out.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7c2eec00a206d57db593a4a9dd9d2c425aaedd81
Author: Christian Ruppert <idl0r@gentoo.org>
Date:   Thu Feb 3 16:00:28 2011 +0000

    Add support for the IT8720F Super I/O
    
    Signed-off-by: Christian Ruppert <idl0r@gentoo.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a96b218c9c19c97476cc846715f5d8b204f96bc0
Author: Josef Kellermann <seppk@arcor.de>
Date:   Thu Feb 3 09:29:57 2011 +0000

    Fix subvendor/subdevice programming on RS690
    
    Some RS690 devices require subvendor/subdevice IDs to
    be programmed at locations other than default 0x2c.
    
    
    Signed-off-by: Josef Kellermann <seppk@arcor.de>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87fcffac82a4e3b24e152678e73cd7e6c2f1dcad
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Feb 3 09:14:40 2011 +0000

    Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functions
    
    This is so that boards can determine them on runtime based on hardware
    properties, if so desired.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Joseph Kellermann <Joseph.Kellermann@heitec.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 539500ee3373b91985aec9749ae35fb5a94e1c51
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Feb 2 23:56:15 2011 +0000

    pmh7.[ch]: Add missing license headers.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed61c4ad7edd1fd4463a24f17fed4e39ecdafe67
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Feb 2 23:49:41 2011 +0000

    Add detection/dump support for the NSC PC87382.
    
    It is a rather small 'Super I/O' device, containing a serial port, IR,
    GPIO, and a Docking LPC switch. It is used in various Thinkpads.
    
    Add 0x164e/0x16ef to the list of probed ports for NSC chips, as
    Thinkpads are using this address pair.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f92d21b12f89a3e1db984b228fd1339d5c7458c
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Feb 1 19:19:53 2011 +0000

    Properly add Lenovo EC to build
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a6c9d159c38ed52397fa7b98b57d48e8c53c427
Author: Sven Schnelle <svens@stackframe.org>
Date:   Tue Feb 1 10:44:26 2011 +0000

    Add support for the Lenovo PMH7 embedded controller
    
    Lenovo PMH7 (Power Management Hardware Hub) is found in
    most recent (starting with X60/T60 AFAIK) Lenovo/IBM Laptops.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 478b77d3884f8c1ca54144380a417ba7a73162ea
Author: Mathias Krause <mathias.krause@secunet.com>
Date:   Tue Feb 1 10:42:52 2011 +0000

    Fix using custom build configs in abuild
    
    The undocumented config argument for the -t option implicitly assumes
    the config file is within the mainboard directory but fails to honor
    this assumption when it comes to copying the file.
    
    Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aeead274a105058a6eb84e41cf6d8a32662a3e2c
Author: Stefan Reinauer <reinauer@google.com>
Date:   Mon Jan 31 21:16:48 2011 +0000

    Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if
    a rare condition arises.
    
    Based on findings by Alexandru Gagniuc <mr.nuke.me@gmail.com>
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    
    Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 38b1f3b772456a1b8ccdba97be3e6bac314a9788
Author: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date:   Mon Jan 31 21:14:02 2011 +0000

    Add PCI ID's for VIA K8T800 and K8M800 northbridges.
    
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b82673bd23122cc092a7a6ba32349183bde0f9f5
Author: Stefan Reinauer <reinauer@google.com>
Date:   Mon Jan 31 21:03:14 2011 +0000

    Build failure because of src/pc80/mc146818rtc_early.c unused variable
    Fixes #173
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Acked-by: Stefan Reinauer <reinauer@google.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ff9d78c9641e57996ef016147cb001d8b4956fc4
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Sun Jan 30 16:37:39 2011 +0000

    Replace special rules for auxiliary files by cbfs-files-y entries
    
    VGABIOS, Intel MBI and the bootsplash image were added with special
    build rules. These are replaced by generic cbfs-files-y entries now.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c0bca2ffd7e59462a1b553d130d4077824a4cdb
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Sun Jan 30 16:31:15 2011 +0000

    Inverse two arguments of cbfs-files-y and adapts its users (one of which already used the new order)
    
    This is in reponse to feedback that the original setup was too complicated.
    
    New cbfs-files-y behaviour:
    cbfs-files-y contains the names of files as they appear in CBFS. The
    arguments describe the on-filesystem name, the type and (optionally) the
    position. Example:
    
    cbfs-files-y += foo
    foo-file := bar
    foo-type := splashscreen
    foo-position := 0xffff8000
    
    This configures a CBFS file called "foo" that is marked "splashscreen",
    located at 0xffff8000 in flash and contains the data of the file "bar"
    in the filesystem (either in the current directory, ie. where the
    corresponding Makefile.inc resides, or if that doesn't exist, relative
    to the toplevel directory).
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aaafec31842d287527477337c179ec1dd7cca7d8
Author: Kevin O'Connor <kevin@koconnor.net>
Date:   Sun Jan 30 07:40:32 2011 +0000

    Make cbfstool available in $(obj) for simple user access.
    
    - integrated Peter's suggestion ($< $@)
    - removed @ prefix, we use the .SILENT pseudo-target
    
    Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3509fdb681a65fb945dca28b5193733a1b84b22
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Sat Jan 29 05:51:54 2011 +0000

    Pass all required toolchain parts to SeaBIOS correctly
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86bd99aba2cec223df48c2a00bdea0450f6346e0
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Jan 28 20:57:48 2011 +0000

    Attached patch fixes the LPC decode ranges of SB700. We enable early only Serial/SIO/RTC. Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
    Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
    
    Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
    Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
    
    While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 16ce01b0d8414a7250fcf142a966ff22c153e85f
Author: Stefan Reinauer <reinauer@google.com>
Date:   Fri Jan 28 08:05:54 2011 +0000

    This patch gets usbdebug console working in romstage.
    - actually hook up usbdebug in printk/print_ for romstage
    - make usbdebug.c more similar to the Linux kernel version it was
      originally derived from.
    - increase retries and timing for usbdebug init (at least one chipset
      seems to need this)
    - src/pc80/usbdebug_serial.c is not needed
    - some small console cleanups
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36ade67007e0e93fb36a982f87e91bf12e2ed869
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 28 07:56:39 2011 +0000

    Separate CMOS layout from lbtable handling
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1e916e076640c133dd32d69804325db02f1707be
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 28 07:54:11 2011 +0000

    Move CMOS handling into separate files in accessors
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 49a74437aab0c253243e62aca20966cf22f864e6
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 28 07:50:33 2011 +0000

    Move the parser for cmos.layout text files to accessors
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 582d369fbdaed82a05a7f494998ab44bdb28c474
Author: Stefan Reinauer <reinauer@google.com>
Date:   Fri Jan 28 07:47:35 2011 +0000

    rename CONFIG_SERIAL_POST to CONFIG_CONSOLE_POST
    because that is what it does.
    
    Signed-off-by: Stefan Reinauer <reinauer@google.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6d2b09f7673a33e75a4f5a38368e9684c2ecc79
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 28 07:47:10 2011 +0000

    Move CLI portion of nvramtool into cli/ subdirectory as first step towards librarization.
    Also: update one regex wrapper user.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7ca3e5ca4f5e2e1c005f24905f6e0b466535525
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 28 07:41:10 2011 +0000

    Eliminate a couple of 3-line functions that barely wrap *printf calls
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bf64985e3b2d4edb59914042830da64d5354dcfb
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 28 07:40:08 2011 +0000

    No need to add varargs magic to a simple regex wrapper.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c2734f5b67f08f8b440ca29b74831e05e4206bb
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 28 01:06:39 2011 +0000

    Fix Bimini build
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c439c3b4ea230d141b926416fa11f898dbf8b5d
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Fri Jan 28 01:03:18 2011 +0000

    rk886ex lacked EC_ACPI
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f13d7f185b49a86987fed7eec76dad0bebac59da
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Jan 27 23:56:48 2011 +0000

    Only add EC code if EC is selected in Kconfig
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7592e8bd9ce46bdb470ace6509bbb32b31987942
Author: Sven Schnelle <svens@stackframe.org>
Date:   Thu Jan 27 11:43:03 2011 +0000

    Add new ec subdir for Embedded Controllers and common ACPI EC support
    
    Adds a new src/ec subdir for embedded controllers (mostly found in laptops)
    and converts Getac P470 and Roda RK886EX to use the new ACPI EC instead
    of having their own copies of those functions.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4096fc53727fa081a7fa014dbee005566537421a
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Jan 27 11:09:36 2011 +0000

    SMM code on i945 platforms needs udelay()
    
    smm-y wasn't required before, because udelay.c used to be #included from
    various files in src/mainboard.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a470019b7a19e164b5dc93b1d541dc4158edbeda
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jan 27 07:39:38 2011 +0000

    Add a new CMOS variable which triggers activation of the
    LPT port. With the CMOS variable set, LPT is found by SeaBIOS,
    with the variable reset, it's not.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a5c949eff288af3eb4caffec57a3724c497150de
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Jan 27 03:31:50 2011 +0000

    Trivial. Re-indent the code.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 066cbe0cb7275a41216ab51a67bb596257202a30
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Jan 27 02:19:55 2011 +0000

    Set the phy via weak function.
    As Rudolf called.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce952652a1099b71fcd6e7ad24bb6edad50ba6d1
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Thu Jan 27 01:11:20 2011 +0000

    oops. this is weird. CAR addresses should be specified in the socket and not in
    the board. I thought we did this ages ago.
    
    Also push CAR BASE further down so it won't conflict with a 32mbit flash part.
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 33ee3ee6b4b0432bb9958b9d959f4783856b37ff
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date:   Tue Jan 25 19:27:23 2011 +0000

    Fix abuild
    
    thanks to Kevin who came up with this
    
    Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9dcca3bc3eb5c4923dffaf4ac2e89514005a79c5
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Jan 25 06:06:58 2011 +0000

    Set the SB800 SATA PHY correctly.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a5950581975c1dd1736de5c52986d353af680fc3
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Mon Jan 24 21:27:22 2011 +0000

    If the tool has 64bit issues, we need to find and fix them. No papering over them.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 679d38b7a2af32ac82350561810d9ba20b1a9917
Author: Josef Kellermann <Joseph.Kellermann@heitec.de>
Date:   Mon Jan 24 21:07:57 2011 +0000

    This patch fixes an 'write_tables: coreboot table didn't fit (f0221)' issue.
    
    Signed-off-by: Josef Kellermann <Joseph.Kellermann@heitec.de>
    Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e296653091e0258b5cc49769db48e3b61ecae44
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Jan 24 21:05:53 2011 +0000

    Add CFLAGS when compiling resulting executable. It broke 64bit systems, because the rest uses -m32 now.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a302b58d0157dd216522ca468979b7fcc8b43d51
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Jan 24 07:50:07 2011 +0000

    Change fadt revision back to 3.
    The AcpiPmaCntBlk have to be set.
    Further research is needed to find out why.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f81e198aeb3b46d7e60fcce5f10fb3ad5127b02
Author: Kevin O'Connor <kevin@koconnor.net>
Date:   Sun Jan 23 06:47:09 2011 +0000

    Clone a tag rather than SeaBIOS stable branch HEAD
    
    Use a tag (rel-0.6.1.3) for SeaBIOS stable checkouts instead of the
    stable branch.  The tag is a little safer because it prevents an
    incorrect commit to the stable branch from being immiediately picked
    up by coreboot users.
    
    Note - rel-0.6.1.3 (and 0.6.1-stable) now have the CFLAGS build fix
    that was causing build failures for coreboot users.
    
    Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3eb534f18b2708839ef6a97cc1161c0a4af43cc
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 21 13:20:10 2011 +0000

    ... And fix the other compile time issues in cmos_layout.bin support
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f0bf4b5c2abd9a226dd681d88132e8d66f8ba92a
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 21 12:45:37 2011 +0000

    Make YABEL warnings-are-errors safe
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ccbbd982b77831d7f3dd6a5dc2382a40127179a
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 21 11:43:06 2011 +0000

    Typo. s,CMOS_COMPONENT,CBFS_COMPONENT,.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 72cc87fba51205044157132bb32e9ad15281b564
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Jan 21 08:46:27 2011 +0000

    Now bimini can boot linux to login.
    Note:
    1. bimini_fam10/Kconfig: Set GENERATE_MP_TABLE in Kconfig. This will make sure the
       smp_write_config_table will run. Then intr_data will be written
       into 0xC00/0xC01.
    2. bootblock: Use PCI_DEV(0, 0x14, 3) instead of
       pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_LPC), 0).
       The pci_locate_device will cause the system crash.
    3. fadt.c: Change fadt revision to 1. 3 will cause the linux hang. Why?
    4. early_setup.c: pmio 0x65 has change its meaning.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba185722d4cb18289fea144a5e3e371ddbf342a0
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Fri Jan 21 07:46:32 2011 +0000

    push ts5300 rom size to 1MB. In fact the flash part on that
    board is 2MB and the entry point is somewhere in the middle. quite weird setup
    http://www.embeddedarm.com/products/board-detail.php?product=TS-5300
    
    We should probably wipe the board from the tree. It will not work anyways with
    current coreboot and the architecture is kind of obscure.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 202be7b6b7e06597f672426af29649c92353db17
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 21 07:29:40 2011 +0000

    Add nvramtool -D option that allows taking cmos data from
    a plain binary file. Overrides using cmos.default in CBFS
    if both -C and -D are given.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 269e932340869696abfaeb63736ba887d88ef690
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 21 07:24:08 2011 +0000

    Add nvramtool -C option that takes a CBFS file as argument.
    When using this option, nvramtool looks for a cmos_layout.bin
    and cmos.default in the image and uses these for layout information
    and CMOS data.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cd7eba1180396cbd91776a94444696f6b4069c4
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 21 07:19:59 2011 +0000

    Add support for working on in-memory CMOS data (eg.
    as loaded from a file).
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be5a178de731dd6b255c38c1e63b3de8b3008a14
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 21 07:18:20 2011 +0000

    Abstract CMOS accesses a bit more in preparation of using
    files for CMOS data.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d4f6536b0b61ead20b4a8c2e1600dec513218e8
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 21 07:04:05 2011 +0000

    There's another place where nvramtool can look for
    the CMOS checksum specification.
    When using nvramtool on files (instead of CMOS and runtime firmware)
    it's the only place.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ae82e370b7c293ccb6286a209abae79ffc0eb26
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Jan 20 06:28:25 2011 +0000

    Remove the code for debugging.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4da254a39cf8d2d98140c12b48b3163192594dd
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Jan 20 05:59:22 2011 +0000

    S3 feanture of SB800. Compiliant with SB700.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 79c04d559a54e1480e59039468bee1956c039d61
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Jan 20 05:41:11 2011 +0000

    Move some board specific functions to sb800.h.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8210e8972c42efbfcf10b49232d882d909983f8f
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Jan 20 05:29:37 2011 +0000

    Features of Bimini board:
    RS785
    SB800
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d098575b0e8440da33eceaf715967ea8273bbaf2
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Jan 20 04:45:48 2011 +0000

    This sb800 code is derived from sb700.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd676ddc54f8d210f9c62a0f6a259dd4482c9b1b
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Jan 20 02:09:24 2011 +0000

    For Cx, each ChipSel need to be sent MR command.
    After this patch, tilapia can run in higher memory frequency.
    To test the high frequency, dont forget to change the freq limit in
    mcti_d.c:
     static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
     {
    	 pDCTstat->PresetmaxFreq = 800;
     }
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c29675f3324db3d4a14b77b1c9d4988cb9a89a0a
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Wed Jan 19 07:25:26 2011 +0000

    Add a GX2 Kconfig option to choose the framebuffer size.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb2b584ac4ccb2030ab9e111ee44de196270b27a
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Wed Jan 19 06:56:33 2011 +0000

    Add Geode GX2 memmory descriptors.
    Add a simple README file.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b0500c24ca103e8f8d802b476517afc2ac8eef5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jan 19 06:54:42 2011 +0000

    Revert r5902 to make code more readable again. At least three people like to
    have this go away again.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Kevin O'Connor <kevin@koconnor.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5bb9fd6e4dae32f86a07676228034d3828820037
Author: Kevin O'Connor <kevin@koconnor.net>
Date:   Wed Jan 19 06:32:35 2011 +0000

    Now that the VIA code is run above 1Meg (like other boards), it should
    cache that range instead of the first 1Meg.  This reduces boot time by
    about 1 second on epia-cn.
    
    This patch also adds a MTRRphysMaskValid bit definition.
    
    Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4adc9eb60047e7dc3a7921793c489fff4fe3fc57
Author: Kevin O'Connor <kevin@koconnor.net>
Date:   Wed Jan 19 06:31:24 2011 +0000

    The cn700.c code references mainboard_interrupt_handlers() which isn't
    defined if VGA_ROM_RUN is off.  Define a dummy implementation of that
    function for this case.
    
    Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3ad0851d79c0046bdcd2d56c4f9889c5fa4f0913
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jan 18 14:38:59 2011 +0000

    Fix fwrite tests.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cef3b896c1593de5a41b57bff4d4600d0c90e06e
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jan 18 14:28:45 2011 +0000

    Report if cmos_layout.bin can't be found when it should.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 244793784ce63957f3ba3a1b9dbf2d2cdf0c506a
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jan 18 13:56:36 2011 +0000

    Move option table (cmos.layout's binary representation)
    to CBFS and adapt coreboot to use it.
    
    Comments by Stefan and Mathias taken into account (except for
    the build time failure if the table is missing when it should
    exist and the "memory leak" in build_opt_tbl)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 024ec852c29685549e5167f4b5d9065e80287ee2
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jan 18 12:14:08 2011 +0000

    Remove overengineering, part 1/many
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2601697c6f70e0200f6f115d6e6e5e5d67fe6101
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Tue Jan 18 12:12:47 2011 +0000

    Eliminate strict aliasing related warnings.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 884554c4e306e2b01941361c7166ca546d1052a4
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Jan 18 09:36:44 2011 +0000

    remove the code which is not ready to release.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a19c622c060831a5414cb9b0929e622cf894b58b
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Jan 18 09:34:31 2011 +0000

    remove the code which is not ready to release.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 752ab0d785178869492b4cf90af69d8c9d14aa7b
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Jan 18 09:32:15 2011 +0000

    remove the code which is not ready to release.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 078efb5a6fed4fe059af63f3f7d9844c52841cf3
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Jan 18 09:31:29 2011 +0000

    remove the code which is not ready to release.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 10219012f29692c7860e505cf2d71004ba82c1f3
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Jan 18 09:29:19 2011 +0000

    remove the code which is not ready to release.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 441426b486f695b462731d1026c07fb15406dc68
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 17 05:08:32 2011 +0000

    cbfstool: When extracting, refer to files in CBFS as file instead of payload
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b347e0d8011883ac91683978a96eab28103af200
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 17 05:02:09 2011 +0000

    cbfstool: Trivial move of newline after commands in usage
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7296e74f1c1bd33f2c19c498443955d674cfacb
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Jan 17 02:20:33 2011 +0000

    The code is tested on my board with register DIMMs. More tests need to be
    done. Please send the testing report.
    
    Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set
    to a higher limit, otherwise the frequnce will be set as 400MHz.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Scott Duplichan <scott@notabs.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a1125235ecc8c6ff9df1fd293de273111774345a
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Jan 16 17:15:36 2011 +0000

    Ooops lets see if this extra comment removal fixes this.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa55f3768a5420715c9b9bdf01d809a2110103a4
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Jan 16 16:23:51 2011 +0000

    Trivial, cleanup of GPIO comments.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3dc8f8ebc57f35132687a1a1a201ef08063c195
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 14 08:36:34 2011 +0000

    Disable CMOS recovery code for ROMCC boards as the CBFS code used for
    that feature is not ROMCC compatible.
    Fixes build errors introduced in r6253.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef3296542a1a1883e8a0f5a05992b2db5b507f2c
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 14 07:41:42 2011 +0000

    Improved GPIO setup for roda/rk886ex, and some documentation
    on what the GPIOs are used for.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a865b17eff05fa3936494716401f6aa9a9ef6358
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Fri Jan 14 07:40:24 2011 +0000

    Allow coreboot to initialize CMOS if checksum is invalid.
    
    If a file "cmos.default", type "cmos default"(0xaa) is in CBFS,
    a wrong checksum leads to coreboot rewriting the first 128 bytes
    (except for clock data) with the data in cmos.default, then
    reboots the system so every component of coreboot works with the
    same set of values.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4c8e269841bbdfd3325b8eb98a651a8b1df85399
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jan 13 11:40:38 2011 +0000

    Default to CRT on Kontron/986lcd-m. "default display" doesn't always
    select the right output device.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9144304771be6cc89fcd010a0c8bc123bb750cfc
Author: Patrick Georgi <patrick.georgi@secunet.com>
Date:   Thu Jan 13 11:38:46 2011 +0000

    Improve compatibility of YABEL with real-world VGABIOSes
    
    Some of them do weird things to the option rom region (mapping
    registers there or so) which failed as we handled these memory
    region in emulation. As they were copied back to real memory
    after the emulation was done, we can just as well use real
    memory directly for these regions.
    
    This affects IVT, BDA, and option ROM space.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fe7d6b9a4a784f0b92b3c9dc5b6c6070b4c2e10c
Author: Aurelien Guillaume <aurelien@iwi.me>
Date:   Thu Jan 13 09:09:21 2011 +0000

    Add "cbfstool extract" function.
    
    It dumps everything you ask for, but you might not
    get what you expect if the file is compressed or
    otherwise converted (eg. payloads in SELF format).
    (Originally it would only extract "raw" files.
    This is a change by me, as filetypes are commonly used
    to differentiate raw data files --Patrick)
    
    Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
    Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
    Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb433bea6a886e8c00620bf4c799feae0d6c7072
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Wed Jan 12 21:09:25 2011 +0000

    drop unused files
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09e0e9a68b589e1a23758e70dbee32cc4e4a2e5d
Author: Kerry She <kerry.she@amd.com>
Date:   Tue Jan 11 02:15:57 2011 +0000

    change a readable way to fix SB800 CIMX "multi-character constant warning".
    by using 'Int32FromChar' macro, instead of the ASCII code.
    
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 965c43b4db8df752a2db609fef01c7235291c144
Author: Marc Bertens <mbertens@xs4all.nl>
Date:   Thu Jan 6 23:03:46 2011 +0000

    Various Nokia IP530 fixes.
    
     - Correct default ROM image size for this board (512KB is correct).
    
     - devicetree.cb: Add AUX I/O config (mainly GPIO settings).
       This allows you to control the LEDs in the front panel and JP900/JP901
       can be read.
    
     - irq_tables.c: Rework PIRQ table to make more onboard devices work.
       Also, avoid IRQ9.
    
     - mainboard.c: Drop unneeded functions, everything is done in devicetree.cb.
    
    Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69436e1a8ccf50d67004f74360f3ff5e6a146b9a
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Jan 6 02:18:12 2011 +0000

    Fix some settings fo AMD MCT. It is based on BIOS test suite.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da712f3f45bf27dc7326887c2d38cc7599f7448a
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Wed Jan 5 02:40:53 2011 +0000

    uart_init is only used in romstage.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b342263f0d8546b4eb9ba235bd3cb6524c9ffec
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Wed Jan 5 02:27:53 2011 +0000

    move single options out of main menu and remove stray "options"
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 355632bc318dca9a26627dec6831052045370089
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Wed Jan 5 02:10:50 2011 +0000

    fix compilation of mconf on some systems.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c28522ec128cae1615dc61f2b9b149a1bff8eb1
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Wed Jan 5 01:37:48 2011 +0000

    fix "make clean"
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7f0c8feaba0208fd6b4d8a23459be7ed9419635
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Jan 4 19:51:33 2011 +0000

    MCP55: Cosmetic fixes, switch to u8 et al.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e2fbd5dd3a9271edaf4c0b3fcc2301e10a83f8f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Jan 4 17:36:55 2011 +0000

    CK804: Cosmetic fixes, switch to u8 et al.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ecab12a09e9d38e8e6f6ce5079fbf740d2cde1a5
Author: Kerry She <kerry.she@amd.com>
Date:   Tue Jan 4 06:39:29 2011 +0000

    Trivial:
     add missed CIMx file to romstage. in order to link them into romstage, move all CIMx table to .rodata section.
     Run dos2unix on Makefile.inc, which is not upstream CIMx code
    
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Acked-by: Kerry She <kerry.she@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7917f430b2e2cffc806ccdac6df35d265853a687
Author: Kerry She <kerry.she@amd.com>
Date:   Tue Jan 4 06:15:46 2011 +0000

    Trivial: use the IO_APIC_ADDR constant defined in ioapic.h, and spell check
    
    Signed-off-by: Kerry She <kerry.she@amd.com>
    Acked-by: Kerry She <kerry.she@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e92596503425b0c7e9a62fcacd55a30803d5215d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Jan 1 23:36:03 2011 +0000

    src/southbridge/amd/cimx_wrapper: Run dos2unix on the files.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6a1373da2c4f49b1f96b6516bc88c72de7338b4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Jan 1 23:30:37 2011 +0000

    AMD SB800: Drop component prefix from filenames.
    
    We did the same with other chipsets in r6150.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9bd9ae9eb7809c1fd513e0a4cdcd1b630aacb25
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Jan 1 22:05:57 2011 +0000

    Add detection support for the ITE IT8721F.
    
    Tested on hardware by me.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48b8b924395b8b2119646fd9f07924586b436f6b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Jan 1 18:58:39 2011 +0000

    AMD Bimini: Use mptable_init() in mptable.c.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26c182340fa5569f034a50010bb6d47ed13e5fd6
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Jan 1 18:40:02 2011 +0000

    AMD Bimini: Small fixes, and updates to recent trunk conventions.
    
     - Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed
       to HAVE_DEBUG_CAR in r5898.
    
     - Move QRANK_DIMM_SUPPORT to Kconfig, see r6028.
    
     - Drop obsolete/unused COMPRESS, see r6145.
    
     - Drop obsolete SET_NB_CFG_54, see r6086.
    
     - Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077.
       Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it.
    
     - Rename some GENERATE_* options to HAVE_*, see r6027.
    
     - Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151.
    
     - Drop ACPI_SSDTX_NUM, the global default is 0 already.
    
     - Random whitespace and coding style fixes.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7e7519ff56a05b2f89eb647a7764afda032aeca
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Jan 1 18:10:07 2011 +0000

    AMD Bimini: Drop duplicate ASL files as we did for other boards.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ee5fcacba707d137f289f2e496c57eea398839d0
Author: Kerry She <Kerry.she@amd.com>
Date:   Sat Jan 1 18:04:42 2011 +0000

    Add support for the AMD Bimini eval mainboard.
    
    Signed-off-by: Kerry She <Kerry.she@amd.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84f59aee3c4710dd7a9ebebd2bd6f7c1d2465e90
Author: Kerry She <Kerry.she@amd.com>
Date:   Sat Jan 1 17:52:34 2011 +0000

    Add AMD SB800 southbridge support via cimx_wrapper.
    
    Signed-off-by: Kerry She <Kerry.she@amd.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 799fed98ea57fc9632b7bf95b3f1d79519cbdd15
Author: Kerry She <Kerry.she@amd.com>
Date:   Sat Jan 1 17:44:07 2011 +0000

    Add AMD SB800 southbridge CIMx code.
    
    The main CIMx code is in a src/vendorcode directory and should not be
    changed with regard to coding style etc. in order to remain easily syncable
    with the "upstream" AMD code.
    
    Signed-off-by: Kerry She <Kerry.she@amd.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 123edb0f688f2c6b7146929d6650751f6674a95c
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Fri Dec 31 19:20:23 2010 +0000

    Use $(MAKE) instead of make when cleaning for SeaBIOS.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 40992d33b8d9f0b3c762d77c7538a8a4aacf3bfb
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Dec 31 01:46:12 2010 +0000

    Add RS785(RS880) support. Just few pci_ids.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d81646314af1b720665b6bdb4e7523ae80cca73
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Dec 31 01:38:45 2010 +0000

    Add detection of Nuvoton WPCM450.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8098e429445723a60cf7772777385259e2c498bb
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Thu Dec 30 19:23:29 2010 +0000

    Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code
    and fix CIS mode comments.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8cf54c9f236afef6b74b6510983bd25e8536055a
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Thu Dec 30 19:21:08 2010 +0000

    Use die()  to assure the processor can't wake up from an interrupt.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f1939bb29b15cb68e90c68ceda86d8d9ad20e746
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Thu Dec 30 17:39:50 2010 +0000

    Per default, use SeaBIOS payload instead of no payload.
    Add choice to use stable or master version of seabios repository
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d7ce71d58f7dc2bdc9c0dd8eb7b804f0194071fa
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Thu Dec 30 16:57:58 2010 +0000

    superiotool: Don't skip probing on a port if a a chip was detected on another port.
    Only skip probing if chip was found on the same port already to avoid
    duplicates.
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84be0f59b7158d5d60e1d7d61786d0a6e449d682
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Wed Dec 29 21:12:10 2010 +0000

    -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)
           to FG (FooGlue). As the GX2 has no VIP port.
    -Change the Memmory setup MSR register names so they correspond better to the
           databook. (Part1)
           This is less confusing for beginners.
    -Add a MSR printing function to northbridge.c like in the Geode LX code.
    -Remove the AES register names.(GX2 has no AES registers)
    -Delete some unused code.
    -Clean up GX2 northbridge code  to match Geode LX code.
    -Add missing copyright header to northbridge.c.
    -Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
    
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cdcf9833e804f3549257c3d071862a0e6ac4bfac
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Wed Dec 29 21:02:50 2010 +0000

    fix i810 boards with ram init debugging disabled.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef15ff4de485b9c301d828f758cc5b40511c51ab
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Wed Dec 29 20:31:31 2010 +0000

    -Clean up some comments.
    -Remove some white spaces.
    -Remove some leading zeros.
    -Fix a typo in LX code.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc01e5e3bb5ea6d6ba78ca67fd7f5e87af3cdb2e
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Mon Dec 27 14:31:05 2010 +0000

    proper printk handling in src/northbridge/intel/i82810/raminit.c
    and drop some romcc relics in 440bx code too
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50e723368970d765e18971bd303f28558c2cb61f
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Mon Dec 27 13:30:39 2010 +0000

    __PRE_RAM__ is defined by the makefile
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c2c75098eab5f80ab8c50180061fe44fe797518
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Mon Dec 27 13:29:38 2010 +0000

    dump_spd_registers() is only defined when ram init debugging is on.
    
    Most boards unconditionally call this. Fix it in header file instead of each single romstage.c
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c0bfaf7da0f93d6887c0a99b85a43cffbcbf6e2
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Mon Dec 27 11:34:57 2010 +0000

    Fix most CONFIG_DEBUG_RAM_SETUP issues.
    
    The intel/xe7501devkit is still broken, I think the (romcc) image is too big to
    fit in the bootblock if CONFIG_DEBUG_RAM_SETUP is enabled. It would make sense
    to convert all CPU_INTEL_SOCKET_MPGA604 to CAR, but I have no hardware to test.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit acda2fc9acaa02b97efec9b82835306ef85ac90c
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Mon Dec 27 08:21:23 2010 +0000

    Intel SCH: make state machine binary selection available in Kconfig for now.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a35eb2c5e2826cc52fc91c0d52f75ed047dd3122
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Sun Dec 26 16:49:57 2010 +0000

    All the values should stay untouched or be set automatically by the resource
    allocator. If that does not work out, they should be set in the code. Setting
    them in Kconfig is the worst possible thing to do.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d1d9cebffbd48d2c3737ff8c919da76e5f12586
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Dec 26 14:12:38 2010 +0000

    Random fixes for TI pci1x2x / Nokia IP530 / others.
    
     - nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c:
       - Fix SMSC FDC37B787 name (was a typo).
       - Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either.
       - Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/.
       - All of these are confirmed by Marc Bertens on IRC.
    
     - Fix a few CHIP_NAME HP board names.
    
     - Random whitespace and coding-style fixes.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 19d69e3bab787f51f2eb9bef48bc49468a635016
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Sun Dec 26 05:24:50 2010 +0000

    Move Geode GX2 UMA video memory size to Kconfig
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 642509c965341d3eee09a5f2bd3650e95f85b851
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Sun Dec 26 05:21:18 2010 +0000

    Remove dead and unused Geode GX2 code
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3344743215acab0b7805592a7c52a9c93636b347
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Sun Dec 26 05:16:47 2010 +0000

    Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c6d4e605588c03edf4e7ab70056d7c075fc5bb1
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Sun Dec 26 05:12:49 2010 +0000

    Clean up Geode GX2 comments, whitespace and coding style. Trivial.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88929f9bf4cb22c5f6e57845f8637864fb578d6a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Dec 25 22:54:41 2010 +0000

    Nokia IP530: Add missing "select SDRAMPWR_4DIMM".
    
    This is needed for all Intel 440BX boards with 4 DIMM slots (such as this one).
    
    Thanks Marc Bertens <mbertens@xs4all.nl> for bringing up the issue and
    for the success report for this fix on IRC.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09f5a7446a016b845f421a3a6e10deedb4a101ed
Author: Keith Hui <buurin@gmail.com>
Date:   Thu Dec 23 17:12:03 2010 +0000

    Fix build with CONFIG_DEBUG_RAM_SETUP on Intel 440BX, use printk().
    
    It's a good thing to use printk() instead of print_*() anyway
    on 440BX (and other chipsets which have been converted to CAR).
    
    Build tested and boot-tested on ASUS P2B-LS.
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d43498d1be832f01ea43bb2450759dfdae3e7cbd
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Dec 20 23:40:23 2010 +0000

    Various Winbond/Nuvoton W83527HG fixes as per datasheet.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bccbbe6b69077170335d14a0413a36ce5e76f493
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Sun Dec 19 21:20:14 2010 +0000

    The same mechanisms are used for normal and fallback images.
    Hence drop the FALLBACK_ prefix
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a05ddbc46d242760cb7e29426d7ca52efa12e0bb
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Dec 19 01:08:40 2010 +0000

    ASUS M2N-E: Enable PCI-E x16 slot.
    
    Simple devicetree.cb fix, tested on hardware using a PCI-E x16 graphics card.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c3662710ae4f2ef063098c5dfb58dbe74fe121e
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Dec 18 23:30:59 2010 +0000

    SMM on AMD K8 Part 2/2
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cadc54583877db65f33d2db11088d5fae1b77b74
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Dec 18 23:29:37 2010 +0000

    SMM for AMD K8 Part 1/2
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 405721d45c8f7cd58c2466e43df8c2aee6f8e714
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Dec 18 13:22:37 2010 +0000

    Fix a few whitespace and coding style issues.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a0360af0f1645d91b139022353f7a3a9f7f85f8a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Dec 18 11:55:06 2010 +0000

    A couple of Poulsbo fixes:
    - Don't include cmc.bin to the build. It's required, but we don't ship it
    - mptable's API changes a bit. Adapt.
    - Fix ACPI for new iasl versions with improved code validation
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be61a173512ece32de01562995a91fbbf3f5b335
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Dec 18 07:48:43 2010 +0000

    Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board
    which uses it.
    
    Compiles, but not boot tested lately.
    Many things missing (eg. SMM support, proper ACPI, ...)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 312fc96874ff2b3fd1a839b72dd10edb1b8937b8
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Fri Dec 17 22:34:58 2010 +0000

    inteltool: Model 0xf2x, ICH5, i865 support.
    
    Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
    registers on ICH5. Add ICH5 and i865 to the supported chips list.
    Enable the dumping of BAR6 on i865.
    
    Sample output:
    
      Disabling memory access:
      $ sudo setpci -s 6.0 0x04.b=0x0
    
      $ sudo ./inteltool -m | head -n 9
      Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7
      Intel Northbridge: 8086:2570 (i865)
      Intel Southbridge: 8086:24d0 (ICH5)
    
      ============= MCHBAR ============
    
      Access to BAR6 is currently disabled, attempting to enable.
      Enabled successfully.
      BAR6 = 0xfecf0000 (MEM)
    
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 397ff6815f48182e9f05372aefcad55950d2dc36
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Dec 17 18:04:26 2010 +0000

    Remove some more unused/incorrect hda_verb.h files.
    
    As discussed on the mailing list at
    http://www.coreboot.org/pipermail/coreboot/2010-December/062393.html
    http://www.coreboot.org/pipermail/coreboot/2010-December/062510.html
    
    Someone who owns these boards should create correct files at some point.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5411e718c1eaa0f1d8f1dc26c74e4250d034e916
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Fri Dec 17 02:32:42 2010 +0000

    Update reference toolchain due to some inlining bugs in 4.5.1
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6195 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3817494e0829305694aee49480d3bcf13765928c
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Fri Dec 17 01:51:34 2010 +0000

    fix the tree again.
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f726602984de4a8376f7a6933166e51c6b49bd9c
Author: Marc Jones <marcj303@gmail.com>
Date:   Fri Dec 17 01:27:22 2010 +0000

    This was accidently not svn added when the compiler was updated.
    
    Update coreboot crossgcc toolchain, GDB 4.5.1, MPFR 3.0.0, GDB 7.2.
    Add libelf_cv_elf_h_works=no to produce a libelf.h for Cygwin.
    Add GDB patch to handle #pragma pack in the i386-elf gcc target.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6559f43dd96845c7fde9720a6c1b720aa1cb9361
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Fri Dec 17 00:13:54 2010 +0000

    add license headers to some trivial files and pc87427.h
    Mostly done according to initial file creator.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85b0fa1ace685bfdb1f1febbbf5127710a314888
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Fri Dec 17 00:08:21 2010 +0000

    drop one more version of doing serial uart output differently.
    
    coreboot made it kind of complicated to print a character on serial. Not quite
    as complicated as UEFI, but too much for a good design. Fix it.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit efbfd501fee8decd0942808a47a3f9e93d30ae38
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Fri Dec 17 00:03:18 2010 +0000

    guard against the case that CONFIG_WAIT_BEFORE_CPUS_INIT is not defined at all.
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43c1a2173371a0325f12733413503a78442dccd0
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Thu Dec 16 23:57:43 2010 +0000

    drop unused code in div64.h
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d3e12b51a6178c0039f224876ee283b59e8bdb6
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Thu Dec 16 23:57:00 2010 +0000

    print what make is doing (CBFS call)
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6188 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5fb62168f6e93c481f4f4a0ce3029311cc53aae7
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Thu Dec 16 23:52:04 2010 +0000

    don't hardcode CONFIG_PC80_SYSTEM
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8aedcbc436db37986d6e8a41873ac5c523a8df0a
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Thu Dec 16 23:37:17 2010 +0000

    - Fix shortcoming in Kconfig when handling multiple "choice"s
    - move some variables where they belong
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 259a39f3930a4032f0ebc8946d26549c5a79bcea
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Thu Dec 16 23:24:27 2010 +0000

    fix according to coding guidelines
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9c224e9c53c8e0df9835c0cfe5d28f98678c375
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Dec 16 19:57:54 2010 +0000

    Add TINY_BOOTBLOCK support for the SiS966 southbridge.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c36d506a05ad02f65d92d0f5a7b70a7c25666445
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Dec 16 19:51:38 2010 +0000

    Get mptable OEM/product ID from kconfig variables.
    
    We currently use "COREBOOT" unconditionally as the "OEM ID" in our
    mptable.c files, and hardcode the mainboard name in mptable.c like this:
    
      mptable_init(mc, "DK8-HTX     ", LAPIC_ADDR);
    
    However, the spec says
    
      "OEM ID: A string that identifies the manufacturer of the system hardware."
      (Table 4-2, page 42)
    
    so "COREBOOT" doesn't match the spec, we should use the hardware vendor name.
    
    Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID"
    (truncate/fill it to 8 characters as per spec).
    
    Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID",
    and truncate/fill it to 12 characters as per spec, if needed.
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c2c23dca8bea16a0198a21fe900fb1d43170489a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Dec 16 07:36:28 2010 +0000

    Add support for cbfs-files-y to the build system.
    That variable allows chipset components to add files to
    the CBFS image, for details see
    http://www.coreboot.org/pipermail/coreboot/2010-December/062483.html
    
    Compared to the patch in that mail this commit improves dependency
    tracking a bit.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d0d6718a3afac24029d45540d587a24802730a4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Dec 15 11:32:11 2010 +0000

    Build fix.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 41dc1c0656a60484464834fb5b05290035af280a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Dec 15 08:56:19 2010 +0000

    Cleanup up HD audio codec / hda_verb.h files.
    
    Most of the current hda_verb.h files are identical (same MD5 sum) and are
    intended for a specific MCP55 board with the Realtek ALC880 audio codec,
    which has the vendor/device ID of 0x10ec0880. They were splitted out from the
    MCP55 southbridge code and put into board dirs a long time ago (which is
    correct, as those settings are indeed board-specific), but they were never
    adapted to those boards.
    
    Here's the table of which codec is soldered onto which board, based on
    checking the vendor website board spec pages, and the board manuals:
    
     - GIGABYTE GA-M57SLI-S4: Realtek ALC883
     - MSI MS-7260: Realtek ALC883
     - MSI MS-9652: Realtek ALC888
     - MSI MS-9282: Server board, doesn't have audio at all
     - Tyan S2912: Server board, doesn't have audio at all
     - All Supermicro boards: Server boards, don't have audio at all
     - NVIDIA l1_2pvv: No public info to be found, but I assume this was the
       original MCP55 eval board for the port and it's probably has the Realtek
       ALC880 codec used in the original hda_verb.h.
    
    These are the codec vendor device/IDs involved:
    Realtek ALC880: 0x10ec0880
    Realtek ALC883: 0x10ec0883
    Realtek ALC888: 0x10ec0888
    
    The following files are marked as incorrect / TODO, as the ID of the codec
    doesn't match and thus will never get actually used (you'll see
    "HDA: no verb!" or similar in the coreboot logs). Even if the ID matched,
    the rest of the table would be incorrect anyway because the values are
    highly board-specific.
    
    ./src/mainboard/gigabyte/m57sli/hda_verb.h
    ./src/mainboard/msi/ms9652_fam10/hda_verb.h
    ./src/mainboard/msi/ms9282/hda_verb.h
    
    The following files can be safely dropped as these are server boards and
    don't have HD audio (or other audio) at all:
    
    ./src/mainboard/supermicro/h8dmr/hda_verb.h
    ./src/mainboard/supermicro/h8qme_fam10/hda_verb.h
    ./src/mainboard/supermicro/h8dme/hda_verb.h
    ./src/mainboard/supermicro/h8dmr_fam10/hda_verb.h
    ./src/mainboard/tyan/s2912/hda_verb.h
    ./src/mainboard/tyan/s2912_fam10/hda_verb.h
    
    The following two are correct and can stay:
    
    ./src/mainboard/nvidia/l1_2pvv/hda_verb.h
    ./src/mainboard/getac/p470/hda_verb.h
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca466b2fb35e78d2bd797d9f7db3b77061c0a057
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Dec 14 02:02:34 2010 +0000

    Add dump support for the Winbond/Nuvoton W83527HG.
    The datasheet is available on nuvoton's website.
    http://www.nuvoton.com/NuvotonMOSS/Community/ProductInfo.aspx?
    tp_GUID=cf73485c-9e0a-4218-9bee-89dfe9a7bb87
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb9bceebc15718d28ec7c914edbfb1158aadffa8
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Dec 14 01:47:18 2010 +0000

    Set the ROMSIZE as 4MB.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd6619f5e9c4626613d70714e00ddfa0a1b4b67f
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Mon Dec 13 22:16:45 2010 +0000

    no leading zeroes.
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc1e6452489a5223068809edd0d8ccf05ab1f7ee
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Dec 13 20:43:33 2010 +0000

    Attached patch implements the memory speed reductions (and 2T/1T clock logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3.
    
    The patch looks at certain DDR configurations (dual rank/single rank) and lowers the clocks to 2T or frequency as guide suggest. It sets the DualDIMMen bit which I believe should be set for non-dual channel configs.
    
    The patch does not implement support for three dimm configurations supported from revE.
    On the other hand it should improve greatly memory stability across the 939 platform.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52ff06580d5d2f7af76370c4ab7541e2f6ef0b89
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Dec 13 20:04:25 2010 +0000

    This patch just turns on the ACPI resume.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 475916ddbfb0ba9fed7f17a2613736551912e3f9
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Dec 13 20:02:23 2010 +0000

    Compile cbmem.c instead of including it in romstage,
    and do that only if resume is done.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4369536da601a02b23cb936c16e54c0485ec21e
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Dec 13 19:59:13 2010 +0000

    Following patch adds support for suspend/resume functions. I had to change the get_cbmem_toc because macro magic did not work well.
    
    The writes to NVRAM are not used in asrock board (k8 pre rev f) but they should work when used with am2 boards. In fact maybe the suspend will work on mahogany or others ;) - with some  simple patch which follows for asrock.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59f410fa43e4176f2f4ded254ee4438f446b1c2d
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Dec 13 19:53:58 2010 +0000

    Following patch adds support to bring out the memory out of self refresh when doing resume.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    
    The patch is based on my 2008 patch.
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97be27ebbae4693a0698838edd7ccea2239ef2db
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Dec 13 19:50:25 2010 +0000

    We hardcode highmemory size in  every northbridge! This is bad, and especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic.
    
    Abuild tested. Please check all changes if I did not make any wrong while converting this to bytes.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29c7dfcadc49262271dba95697dab841ea076d17
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Dec 13 13:44:33 2010 +0000

    Add support for the ASUS M2N-E board.
    
    This is an AMD K8 + NVIDIA MCP55 + ITE IT8716F mainboard.
    
    It has a working hda_verb.h file for HD audio, and a fanctl.c file is
    used to enable the CPU fan (among others) so that we don't kill the
    CPU due to excessive heat.
    
    Even though some TODOs remain of course, it works good enough to
    successfully boot Linux (e.g. via SeaBIOS).
    
    The full status report is available at:
    http://www.coreboot.org/ASUS_M2N-E
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb6c9e09422e4f9a2419997d6e49ab3a7a18690c
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sun Dec 12 14:40:29 2010 +0000

    Add detection support for the Winbond W83527HG Super I/O.
    
    Running result.
    superiotool r6131
    Found Winbond W83527HG (id=0xb0, rev=0x73) at 0x2e
    
    The documentation is not available yet.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dfeb04d46323b412e940ae5c4d52814b18670aa1
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Sun Dec 12 00:37:41 2010 +0000

    fix model 106cx
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4041925039f3504481a9f2263ca96669fc597a4a
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Dec 11 23:28:17 2010 +0000

    Fix the build failure. We have now common fadt.c.
    [PATCH] SB700 common FADT was not applied to this board because it was in the meanwhile added.
    
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e8191b4b2ab650cc31f4d8f4231b92c460cf5c60
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Dec 11 22:41:31 2010 +0000

    I was bitten by the rename, this is part of r6165.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3310934f32e683b6092b565773081434cba19ecf
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Dec 11 22:26:10 2010 +0000

    Following patch makes just one fadt.c file. For SB700.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2a27b20226a2fd593bfd5f6a0eee45418233fe04
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Sat Dec 11 22:14:44 2010 +0000

    factor out cpu power management base into a separate file. And fix a bug in
    model_1067x
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b9070a610132eaf61dca67e7713c082903fffef
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Sat Dec 11 22:12:32 2010 +0000

    catch some illegal configurations (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e7a30ee1663ebce8cfec3c2fb21eee8e1c1246a2
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Sat Dec 11 22:07:07 2010 +0000

    Don't skip already built targets anymore, because a recent change could have
    broken them again. Instead rely on coreboot's dependencies to figure out
    what to rebuild.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8677a23d5b053d550f70246de9c7dc8fd4e2fbf9
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Sat Dec 11 20:33:41 2010 +0000

    After this has been brought up many times before, rename src/arch/i386 to
    src/arch/x86.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 198cb96387c457affa01696405ffaa4531e8e361
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Dec 10 12:52:50 2010 +0000

    Two hda_verb.h files: Add more comments.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e7efb7cab53d924e17c59196d78dbbdb208e6dd
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Dec 10 09:02:50 2010 +0000

    Add TINY_BOOTBLOCK support for AMD SB700.
    
    Factor out the ROM decode enable functionality into bootblock.c and
    handle it via the usual TINY_BOOTBLOCK mechanism.
    
    Use "select TINY_BOOTBLOCK" in the southbridge, not individual boards.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42b1c43c4dad6a58f444e868b84c6bbd10009681
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Dec 9 18:09:14 2010 +0000

    Merge enable_rom.c files into bootblock.c files.
    
    All southbridges using TINY_BOOTBLOCK have a bootblock.c files which
    simply includes an enable_rom.c files. As discussed on the mailing
    list, drop the enable_rom.c file by merging it into bootblock.c.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6ecfdbc84298840ded02f5c4d009732786ed847
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Dec 9 13:10:57 2010 +0000

    Build fix, forgot to run abuild on the latest tree.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8ba64d7b75794556132ffdcaf926bc328712937
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Dec 9 12:39:48 2010 +0000

    Deduplicate various ACPI .asl files.
    
    The files debug.asl, globutil.asl, and statdef.asl are duplicated in
    many K8/Fam10h boards. However, they're neither board-specific nor
    K8/Fam10h-specific nor AMD-specific, so move them to src/arch/i386/acpi.
    
    debug.asl contains generic chunks for I/O port 0x80 handling, and debug
    output over serial port (init COM port, send byte, send string, etc).
    
    globutil.asl contains utility methods for string comparison, string length
    and similar stuff.
    
    statdef.asl contains generic ACPI bit definitions / status codes from
    the ACPI spec (not board- or chipset-specific).
    
    This patch was mostly generated by:
    
    mkdir src/arch/i386/acpi
    svn add src/arch/i386/acpi
    svn cp src/mainboard/amd/dbm690t/acpi/debug.asl src/arch/i386/acpi/
    svn cp src/mainboard/amd/dbm690t/acpi/globutil.asl src/arch/i386/acpi/
    svn cp src/mainboard/amd/dbm690t/acpi/statdef.asl src/arch/i386/acpi/
    cd src/mainboard
    find . -name debug.asl -exec svn rm {} \;
    find . -name globutil.asl -exec svn rm {} \;
    find . -name statdef.asl -exec svn rm {} \;
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a778db86edfb65fe74ba2a2596efe3347780b8c
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Dec 9 06:18:29 2010 +0000

    Add missing instruction break.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abebf5ca92c0b9a8adef4c83ab1feed3040c6644
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Wed Dec 8 21:45:57 2010 +0000

    These empty files sneaked in from another patch and shouldn't have been included in r6153, remove them.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b672d94ce0199bc0bd882c61c7be9ac2c90eded5
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Wed Dec 8 21:40:12 2010 +0000

    Tobias Diedrich wrote:
    > Definitively a iasl problem, it can't even disassemble it's own
    > output back to something equivalent to the input file.
    > It seems to be generating Bytecode for the Add where it shouldn't.
    
    Here is a solution using the SSDT.
    
    Unfortunately iasl does not resolve simple arithmetic at compile
    time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the
    Processor statement.
    This patch instead dynamically generates the processor statement.
    I can't use the speedstep generate_cpu_entries() directly since the
    cpu doesn't support speedstep.
    For now the code is in the southbridge directory, but maybe it
    should go into cpu/intel/ somewhere.
    IIRC notebook cpus of the era can already have speedstep, so it
    would probably be possible to pair the i82371eb with a
    speedstep-capable cpu...
    Also, I don't know if multiprocessor boards (abit bp6?) would need
    to be handled differently.
    
    Abuild-tested.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 89ec3760a9c2e5189681240aae866b20a9d6b592
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Dec 8 19:58:30 2010 +0000

    Allow user to define location for Kconfig config via
    DOTCONFIG make variable (defaults to .config).
    Let abuild use that.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d35192544675575276482e5ce65d1b6a6fd9e4a0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Dec 8 08:22:04 2010 +0000

    Move "select CACHE_AS_RAM" lines from boards into CPU socket.
    
    All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM"
    into the socket directories, and remove it from the individual boards.
    
    Do the same for Intel CPUs/sockets where all boards use CAR.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8301d8348a0848d56fdf4dbd76acd6bdcd3fc944
Author: stepan <stepan@coresystems.de>
Date:   Wed Dec 8 07:07:33 2010 +0000

    second round name simplification. drop the <component>_ prefix.
    
    the prefix was introduced in the early v2 tree many years ago
    because our old build system "newconfig" could not handle two files with
    the same name in different paths like /path/to/usb.c and
    /another/path/to/usb.c correctly. Only one of the files would end up
    being compiled into the final image.
    
    Since Kconfig (actually since shortly before we switched to Kconfig) we
    don't suffer from that problem anymore. So we could drop the sb700_
    prefix from all those filenames (or, the <componentname>_ prefix in general)
    
    - makes it easier to fork off a new chipset
    - makes it easier to diff against other chipsets
    - storing redundant information in filenames seems wrong
    
    Signed-off-by: <stepan@coresystems.de>
    
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 836ae29ee325b1e3d28ff59468cc50913b1e24ce
Author: stepan <stepan@coresystems.de>
Date:   Wed Dec 8 05:42:47 2010 +0000

    first round name simplification. drop the <component>_ prefix.
    
    the prefix was introduced in the early v2 tree many years ago
    because our old build system "newconfig" could not handle two files with
    the same name in different paths like /path/to/usb.c and
    /another/path/to/usb.c correctly. Only one of the files would end up
    being compiled into the final image.
    
    Since Kconfig (actually since shortly before we switched to Kconfig) we
    don't suffer from that problem anymore. So we could drop the sb700_
    prefix from all those filenames (or, the <componentname>_ prefix in general)
    
    - makes it easier to fork off a new chipset
    - makes it easier to diff against other chipsets
    - storing redundant information in filenames seems wrong
    
    Signed-off-by: <stepan@coresystems.de>
    
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1bc5ccac51d94cfb4f9666ecf2cac619d8dc80a6
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Dec 7 19:34:01 2010 +0000

    Move MMCONF resource into the domain for fam10 for the resource allocator.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Scott Duplichan <scott@notabs.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4028ce7b768c9b33e4b0b1af20eede9968359071
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Dec 7 19:16:07 2010 +0000

    Get rid of some unneeded function prototypes in romstage.c files.
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7f20d73eba22babbc5bf9efd8df8a3e9d3a117c7
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Dec 7 06:27:44 2010 +0000

    Trivial. Fix typo.
    sh> find -name "acpi_tables.c" | xargs sed -i "s/FDAT/FADT/g"
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d421c81d728da6ade3760ab6641956f57ccb79d0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Dec 6 20:27:12 2010 +0000

    Drop unused/obsolete CONFIG_COMPRESS from a few board Kconfigs.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f08c643fa3ea773a1b911978c20ddb6a37042ec
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Dec 6 18:20:48 2010 +0000

    Get rid of some useless/empty *_fixups.c files.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b9791c29d0f4e88127f59bb87d53cfed65cd912
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Dec 6 18:17:01 2010 +0000

    Winbond W83627HF: Use existing functions instead of open-coding.
    
    Use w83627hf_set_clksel_48() where needed instead or open-coding the same
    functionality, and also use w83627hf_enable_serial() instead of
    w83627hf_enable_dev() (which does exactly the same, but isn't wrapped in the
    enter/exit config mode functions).
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29cb06abca665954e910f91397957ec93c627e86
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Dec 6 08:19:38 2010 +0000

    Before lane reversal,
    De-asserts STRAP_BIF_all_valid for
    PCIE-GFX core.
    After lane reversal,
    Asserts STRAP_BIF_all_valid for
    PCIE-GFX core.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: QingPei Wang <wangqingpei@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a8c8490c114f97462a3060ce77777ea546d0bbc4
Author: Juhana Helovuo <juhe@iki.fi>
Date:   Mon Dec 6 01:11:12 2010 +0000

    Add initial support for the ASUS M4A78-EM.
    
    Signed-off-by: Juhana Helovuo <juhe@iki.fi>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a4ed157dcd93f845b92fcea272368bdc41d7a11
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Dec 5 22:36:14 2010 +0000

    W83627DHG/W83627EHG fixups for virtual LDNs.
    
    W83627DHG:
    
     - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those
       that don't have their "enable" bit in bit 0 of the 0x30 register).
    
     - Fix various I/O masks in the pnp_dev_info[] array as per
       datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN.
    
    W83627EHG:
    
     - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was
       mostly implemented already, though).
    
     - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN.
    
    Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt
    for the virtual LDNs.
    
    include/device/pnp.h: Add comment that 'function' (which refers to the
    LDN and should probably be renamed later) has to be at least 16 bits
    wide. In theory LDNs could use u8, but due to the virtual LDN info being
    encoded in the "high byte" of 'function' it must be at least u16.
    
    asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV.
    
    ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial
    port 1 in this case) to avoid confusion. The global registers
    manipulated there are accessible from any LDN.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e55eb97f4a6c4ce77d0884aaf1adcb0b29e240bf
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Sat Dec 4 20:50:39 2010 +0000

    ACPI table dumping wrapper script
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0bafd964b7725121ac066baf20d207c87753b6bc
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Dec 4 10:08:55 2010 +0000

    Following patch removes the cut-and-paste stuff from Mahagony and fixes the _CRS object to make it work (same code as on M2V-MX SE)
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3693266d0d0ca490ac1e63f1e66726227ee3376d
Author: Marc Jones <marcj303@gmail.com>
Date:   Fri Dec 3 00:45:56 2010 +0000

    Update coreboot crossgcc toolchain, GCC 4.5.1, MPFR 3.0.0, GDB 7.2.
    Add libelf_cv_elf_h_works=no to produce a libelf.h for Cygwin.
    Add GDB patch to handle #pragma pack in the i386-elf gcc target.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea62e9b47db50cf3cd1551525693eddb2617bd7a
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Dec 2 01:50:38 2010 +0000

    More explicite and straight way to set seed.
    The read-modify-write wasn't needed. This is easier to understand.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c9ae3ae8fe7ae00e6826976fb4849f8e3857db3
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Nov 30 21:21:33 2010 +0000

    The patch just make the power LED on.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f41752c1924e0cbd8bbe2f45dc5d663b7efef0a1
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Nov 30 20:18:53 2010 +0000

    Fix the SPD to channel mapping. Please note that there is something wrong with UMA.
    
    Single channel (in slot DDR1 and DDR3) produces strange artefacts on screen (and hang)
    Dual Channel (in DDR1 and DDR2 aka blue slot) - works nice
    All slots populated - same case as Single channel - must be something wrong with UMA.
    
    Tested with 2x 512MB CAS 2.5 DDR400
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6b8c721e2063b94d66d5dd7540c2b8a4f33d51cc
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Nov 30 02:05:17 2010 +0000

    Trivial. Reindent and dos2unix.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca6d8084dde1e60cb0bef3bf6cb502a95efbf965
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Mon Nov 29 20:40:33 2010 +0000

    Tobias Diedrich wrote:
    > Stefan Reinauer wrote:
    > > The specified IO port is most likely wrong. As the comment mentions, the
    > > SSDT is a good place for that. A preprocessor define used both in the
    > > CPU init code and in the asl would solve the problem without an SSDT.
    > > For some info on CPU SSDT creation on intel check out
    > > src/cpu/intel/speedstep/acpi.c
    >
    > The IO port is ok (and I wrote the comment myself ;)):
    > DEFAULT_PMBASE is 0xe400
    > PCNTRL reg offset is 0x10
    >
    > Using the preprocessor will probably work too if iasl can do simple
    > arithmetic (likely yes), I'll look into that.
    
    BTW, my first idea was to use an acpi method that looks up pmbase in
    the pci cfg space, but when I define a method like this:
    
            Method(TEST, 2)
            {
                    Return (Add(Arg0, Arg1))
            }
    
    I get:
    |build/mainboard/asus/p2b/dsdt.ramstage.asl     9:   Processor (CPU0,
    |0x01, TEST(0xe400, 0x10), 0x06) {}
    |Error    4096 -       syntax error, unexpected PARSEOP_NAMESEG,
    |expecting ')' ^
    
    While using the builtin Add() directly works.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b97030d706987a466751eac9c29d9f26e68a9683
Author: David Hendricks <dhendrix@google.com>
Date:   Mon Nov 29 11:56:39 2010 +0000

    Add Fintek F71889 detection and dump support.
    
    The patch was tested by a user on IRC who had the F71889FG. I
    wrote it using documentation from Fintek's website available here:
    http://www.fintek.com.tw/files/productfiles/F71889_V0.28P.pdf
    
    This patch also seems to work for the F71889ED, which uses 0x09 and 0x09 for
    chip ID bytes 1 & 2. However, I have not been able to find documentation to
    verify that the two chips are identical from superiotool's perspective.
    
    Signed-off-by: David Hendricks <dhendrix@google.com>
    Signed-off-by: Alec Ari <neotheuser@ymail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6fc7d2798398142af5629e50d2544b1d8f5d0fff
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Mon Nov 29 00:20:20 2010 +0000

    fix typo
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d73c50565b526c86195cc10184e0eda2a03d9a1a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 28 14:24:07 2010 +0000

    devicetree.cb: Only add as many entries as there are DIMM slots.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3645e61608a802f66b3109a090a591d9f2bb1dcd
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sat Nov 27 14:44:19 2010 +0000

    - Add support for Intel Pentium III MSRs
    - pmbase is on southbridge function 3 on I82371XX
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e87c38e0af8b5eca8b7482e52a2a6f15388cedfe
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sat Nov 27 09:40:16 2010 +0000

    After finding the missing bit poweroff works now.
    I cleaned up the patch and moved most of the dsdt.dsl and
    acpi_tables.c into the southbrige/northbridge directory.
    Updated patch should fix abuild error and incorporates suggestions
    on irc by uwe (thanks for the comments).
    Thanks to Idwer Vollering <vidwer@gmail.com> for the original patch.
    
    Tested:
      Linux (poweroff, powerbutton event)
      XP (poweroff, powerbutton event)
    
    Abuild-tested
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39124dd6c5f577861c16b947088ac1fd31169b8f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Nov 26 22:42:41 2010 +0000

    Broadcom BCM5785: Add TINY_BOOTBLOCK support.
    
    In bcm5785_enable_rom(): Use PCI IDs from pci_ids.h instead of hardcoding,
    and use 'dev' instead of 'addr' as device_t variable name.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e89d8a57accbac5066f80266d1e98e63f62ba4c5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Nov 26 22:39:40 2010 +0000

    AMD SB600: Add TINY_BOOTBLOCK support.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f7d3c5672ec90f8d71907b1a07c8a87fa461047
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Nov 26 22:35:11 2010 +0000

    AMD-8111: Add TINY_BOOTBLOCK support.
    
    Also, add missing license header to amd8111_enable_rom.c, add some more code
    comments and use PCI IDs from pci_ids.h instead of hardcoding.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df323fcefd6020f8f418a13d65a075d282eed3de
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 25 09:03:55 2010 +0000

    MCP55: Add TINY_BOOTBLOCK support.
    
    Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make
    the build work (but this is a good idea anyway, as it's used in
    multiple files).
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48ae6086da64eb260c6eed676c593cdcd0957fbf
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Wed Nov 24 20:03:09 2010 +0000

    S3 support for ASUS M2V
    
    This adds the board-specific parts for S3 support on the M2V board.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba9f0b30fb3d2081e30c8957194f3a0a202bc2ef
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Wed Nov 24 19:57:08 2010 +0000

    With low serial console loglevels a pcie graphics card is not
    initialized properly because the pcie link takes some time to come
    up.
    
    I set the timeout rather arbitrary to 100ms, this is what a BIOS_ERR
    and higher only boot looks like on my system (with pcie printks set
    to BIOS_ERR so they show up):
    
    |Device error
    |Device error
    |PCI: 00:02.0 PCIe link up after 35800 us
    |PCI: 00:03.0 PCIe link up after 12900 us
    |PCI: 00:03.1 PCIe link timeout
    |PCI: 00:03.2 PCIe link up after 32000 us
    |APIC: 00 missing read_resources
    |I2C: 01:50 missing read_resources
    |I2C: 01:51 missing read_resources
    |I2C: 01:52 missing read_resources
    |I2C: 01:53 missing read_resources
    |Start bios (version pre-0.6.2-20101025_023503-nukunuku)
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88dc53178177c3cfc28bfebab2422dc4133bd7dc
Author: Scott Duplichan <scott@notabs.org>
Date:   Wed Nov 24 00:39:44 2010 +0000

    This patch solves crashes and BSODs that occur when booting Win7 with
    AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB
    by running dxdiag and Windows media player at 1600x1200 true color.
    Additional changes needed to boot Win7 on Mahogany_fam10 will follow.
    
    -- Enable and program the debug bar as required by the ATI graphics driver.
       First, make the debug bar writable and allow resource allocation code
       to program it. Once programmed, enable its operation.
    -- Disable the family 10h processor mmconf while the RS780 mmconf is in use.
    -- Make strap programming more closely follow the reference BIOS.
    -- Disable PCIe bar 3 after using it.
    -- UMA size is no longer hardcoded.
    -- Disable write combining for all steppings to eliminate stability problem.
    -- Correct task file data.
    -- Improve the accuracy of the Atom table that passes information to the driver.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0cda9597109f2e4cd922ee4ec66367b6513360db
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Nov 23 07:30:50 2010 +0000

    USBDEBUG by default in abuild was committed by mistake and
    then left in because USBDEBUG was actively worked on.
    This isn't true anymore, so drop it
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 612fcc3955ff238a6c35b96198ee85d82692ffa0
Author: Patrick Georgi patrick <Patrick Georgi patrick@georgi-clan.de>
Date:   Tue Nov 23 07:19:54 2010 +0000

    Make smp_write_bus static (local scope), to prevent new boards from
    using it directly again.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bcaea142f344389ed0c1857f53b7c8556a804c8d
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Nov 22 22:00:52 2010 +0000

    1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c
    
    2) the patch implements get_cbmem_toc in chipset specific way if defined.
    On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached)
    
    3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself.
    
    4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right.
    
    I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again.
    Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b5295f522fa08b84d222ba08f5801d8e812dbc6
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Nov 22 16:23:54 2010 +0000

    Drop unused ACPI_WRITE_MADT_IOAPIC #define.
    
    This should probably be C code in some .c file anyway.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d5a6accc84530d44f35ba4f3a74b370a1f88f86
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Nov 22 15:57:57 2010 +0000

    Drop per-board ram_check() calls for now.
    
    Every board had a slightly different invokation, very often commented out
    anyway. We could either decide that this is only to be used by developers
    during bringup (and thus added manually to romstage.c and removed before
    the board gets committed). This method seems to be preferred from what I
    have heard on IRC / mailing list in the past.
    
    Or, we add the ram_check() somewhere globally and allow the user to enable
    it via menuconfig (possibly only if EXPERT is selected).
    
    Either way, the current method of spreading the calls all over the place is
    not really the way to go.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7411eabcdb544205316dfa90e7e708b4b0495074
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Nov 22 14:14:56 2010 +0000

    Final set of smp_write_bus -> mptable_write_buses changes.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 394965dd6493943a908a044c5cd3bc3d27e599ec
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Nov 22 13:07:10 2010 +0000

    Workaround to get die.c to work with romcc.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e9ab97106925f74b993ddf66db0b6525dc71580
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Nov 22 12:59:36 2010 +0000

    i855: Remove useless memctrl indirection.
    
    This needlessly complicates the code and increases register pressure on romcc
    chipsets. We did the same conversion on i440BX, i830, and others.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abc0c8551604933ca54e9eaa48c3f00e4915dc90
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Mon Nov 22 08:09:50 2010 +0000

    Printing coreboot debug messages on VGA console is pretty much useless, since
    initializing VGA happens pretty much as the last thing before starting the
    payload. Hence, drop VGA console support, as we did in coreboot v3.
    
    - Drop VGA and BTEXT console support.
      Console is meant to be debugging only, and by the time graphics comes up
      99% of the risky stuff has already happened. Note: This patch does not remove
      hardware init but only the actual output functionality.
    
      The ragexl driver needs some extra love, but that's for another day
    - factor out die() and post()
    - drop some leftover RAMBASE < 0x100000 checks.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: QingPei Wang<wangqingpei@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e9c447326a0ff5565886b0c18c806c77c4a03cb8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Nov 22 00:42:42 2010 +0000

    acpi.h: Small fixes and adding comments.
    
     - Mention full name of all the tables (SSDT, FADT, etc).
    
     - Drop obsolete / incorrect "LXBIOS" reference.
    
     - Add missing ACPI address space type #defines specified in newer versions:
       ACPI_ADDRESS_SPACE_EC, ACPI_ADDRESS_SPACE_SMBUS.
    
     - Add missing "enum acpi_apic_types" entries: Localx2Apic, Localx2ApicNMI.
    
     - Add ACPI_FACS_64BIT_WAKE_F #define.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fae0d6c12bc3ad112b948cffbe7d085e6afd5fc6
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Sun Nov 21 22:55:46 2010 +0000

    Move CK804_PCI_E_X and CK804B_PCI_E_X defines (which have been 4 by
    default on all boards) into Kconfig.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 21 22:47:22 2010 +0000

    Simplify a few code chunks, fix whitespace and indentation.
    
    Also, remove some less useful comments, some dead code / unused functions.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57b2ff886e0ce2c92820f5722c8031def3ac94cf
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 21 17:29:59 2010 +0000

    Drop excessive whitespace randomly sprinkled in romstage.c files.
    
    Also drop some dead or useless code snippets.
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5244e1ba63e5f3ea12066734bfb0d864a8f1f11d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Nov 21 14:41:07 2010 +0000

    Convert more boards to use mptable_write_buses.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8cda9699d4a2fea8ed2c5e4a7e66e8e1e0f831df
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Nov 21 14:40:09 2010 +0000

    Convert boards to use mptable_write_buses.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8a789f6dfa6a8215ee3f737111e19c265af8f92
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Nov 21 14:38:24 2010 +0000

    Move MCP55_PCI_E_X_* to Kconfig. Any useless values in romstage.cs were
    not brought over to Kconfig (this applies to all #defines to 4, as
    that's the default anyway)
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6dc92f0d1a4b6a79c2db800c5bd071daa75a9a23
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 21 11:36:03 2010 +0000

    Use DIMM0 et al in lots more places instead of hardocding values.
    
    The (0xa << 3) expression equals 0x50, i.e. DIMM0.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86a571797d9ede9d79edcfdce38f50a80b9a49f9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 21 10:26:04 2010 +0000

    Build fix.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26535d6e28b9c6697ff2865ba0fd6b2b63054f24
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Nov 20 20:36:40 2010 +0000

    Merge all spd_addr.h into the resp. romstage.c files.
    
    Except for one instance the spd_addr.h were now very tiny, there's not
    much point in keeping that stuff in an extra file. The only user of those
    files is the romstage.c file anyway.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d773fd370a92a6da2f7dbf91c085eb0df1f6f30d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Nov 20 20:23:08 2010 +0000

    Some more DIMM0 related cleanups and deduplication.
    
     - VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.
    
     - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
       romstage.c files and lots of spd_addr.h files. Don't even bother for
       those spd_addr.h which aren't even actually used, drop them right away.
    
     - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
       and 0xa0 with (DIMM0 << 1) where appropriate.
    
     - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
       SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.
    
     - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.
    
     - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
       Then, replace 0xa0 (which now becomes 0x50) with DIMM0.
    
     - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.
    
     - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sat Nov 20 10:31:00 2010 +0000

    Unify DIMM SPD addressing. For Geode, change the
    addressing scheme to match the rest of the tree
    (0x50 instead of 0xa0).
    
    abuild tested.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 622824cadbbbe003bc3e8c97694d2cf6bae0de9b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Nov 19 15:14:42 2010 +0000

    Cosmetic fixes and comment additions in acpi.c.
    
     - Fix whitespace, coding style, and indentation in some places.
    
     - Add comments for less obvious entries and hardcoded numbers (e.g. 'type').
    
     - Add comments for all/most 'revision' fields, mention in which version
       of the ACPI spec which revision number is to be used.
    
     - Add URLs to a few external documents which describe tables that are
       not mentioned in the ACPI spec (or where the external document may
       provide further info), e.g. SRAT, SLIT, HPET, MCFG, etc.
    
     - Use the ASLC #define instead of hardcoding "CORE" in one instance
       (ASLC is already used everywhere else).
    
     - Add some TODOs for additional stuff which is in the spec but not yet
       handled by our code / #defines.
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e882630d47e9ed4f1d9cfea18e5709335a119c12
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Nov 19 10:16:43 2010 +0000

    Add test to check for up-to-date GPL license headers to lint.
    "make lint" should not stop after first failed test.
    Improve "make lint" output.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 911e2ac4b2af88591052be62d909e19ed60e3085
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 19 00:29:32 2010 +0000

    drop temp file from coreboot tree
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 607614d0a9cb589c914d92c1b8957b8141dcaf8e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 18 20:12:13 2010 +0000

    Fix/drop some obsolete comments,
    
     - s/Options.lb/devicetree.cb/
    
     - s/Config.lb/devicetree.cb/
    
     - s/cache_as_ram_auto.c/romstage.c/
    
     - h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in
       the tree now.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24f324cb855b77db17b543feed72a03da0e06bc6
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 18 19:40:33 2010 +0000

    Drop unused and incorrect RTC_DEV for Winbond W83627EHG.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17e5266c737ce5f88607118be0cfd39c6a3fdf50
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 18 18:12:09 2010 +0000

    Make lint script executable, otherwise invocation fails.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 302993fe778dacfe378f1a386e7e32b9839286a7
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Nov 18 15:07:06 2010 +0000

    lint tests can now describe what they do (for the benefit of
    make lint users)
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6ef20fb70f7ce834fa44fa63ad46880be9d51ee
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Nov 18 15:05:06 2010 +0000

    Add "make lint" target that calls all util/lint/lint-* scripts
    and fails if any of these output text to stdout.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 558362fa3491663ea9b8c0aac95965e3afcd44c0
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Nov 18 14:33:02 2010 +0000

    Set locale to POSIX to avoid problems with invalid 8bit character
    sequences.
    Increase scanning speed.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c107bc9e4ac0378e6a6e6ee200e59b8c0c84960
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Nov 18 11:36:16 2010 +0000

    Move DIMM_MAP_LOGICAL to Kconfig.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9e180387bdaf4ad6e29cd2b7044bccfb1b1e6f67
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Nov 18 10:48:15 2010 +0000

    Move register block definitions out of board code into
    chipset code (where it belongs)
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4917692ec81cb5a24a915a38a5a13837fadc619
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Nov 18 00:46:53 2010 +0000

    For completeness sake: License header.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d28c2986d69141280fce64ac5603b107512f8771
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Thu Nov 18 00:11:32 2010 +0000

    Eliminate SET_NB_CFG_54 option. There was no board that
    deselected it, and very likely there won't ever be any
    hardware that requires it deselected.
    
    Keep the "selected" code path around, leading to no
    functional change.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Scott Duplichan <scott@notabs.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 361bd10bcea5db98cfc573987023449c2f59287d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Wed Nov 17 21:52:15 2010 +0000

    Move Intel power management related defines to some central location.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0fe6e9a9a4dfdabf0ad1336112207899b868ee9c
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Wed Nov 17 16:27:06 2010 +0000

    Dynamically generate PNP0C02 mainboard resources in SSDT
    
    Updated patch with improved comments and small bugfix (use same
    value for min and max on io resource).
    
    While adding the area between TOM1 and 4GB to \SB.PCI0._CRS seems to be the
    easiest way to get both Linux and Windows happy, it is not quite correct
    because reserved areas like APIC, MMCONF etc. ranges need to be excluded.
    
    This is a proof of concept patch for the M2V board that dynamically creates a
    ResourceTemplate() containing these in the SSDT and adds a corresponding
    PNP0C02 device to the DSDT.
    
    All resources that have IORESOURCE_RESERVE and (IORESOURCE_MEM or IORESOURCE_IO) set
    are added.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    
    Added M2V-MX SE too.
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8520e01af792bca95aaed332bc0cbc7116948706
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Wed Nov 17 11:30:50 2010 +0000

    Linux also needs the MMCONF area to be reserved either in E820 or
    as an ACPI motherboard resource or it will not enable MMCONFIG
    and the extended pcie configuration area will be unaccessible:
    
    This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF
    resource flags to do this.
    I also added a new resource for the mapped bios rom area just below 4GB.
    I'm not sure if the choice for the index parameter of new_resource()
    is correct though.
    Note that the bios rom decode is enabled in
    src/southbridge/via/vt8237r/vt8237r_early_smbus.c
    for the whole 4MB area (even though the comment says 1MB).
    
    Ruik: I extended the flash range to 16MB (This is what VT8237S can decode)
    Remove the MMCONFIG region reserve in the mainboard file (this patch makes it obsolete)
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e0c0a82954978747aa68eceb19709d93a019829d
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Wed Nov 17 11:02:05 2010 +0000

    This problem was introduced with
    http://tracker.coreboot.org/trac/coreboot/changeset/3953
    
    Note that all corresponding DSDTs only ever check TOM2 against 0.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a71dcd3212fb438ffd725f4b09fa1bb831ee904
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Wed Nov 17 10:58:13 2010 +0000

    The only southbridge having a pirq_assign_irqs function (needed for
    CONFIG_PIRQ_ROUTE) so far is the amd cs5530.
    Add one for vt8237 too.
    Setting up the pci routing is important in case you want to boot DOS,
    OSes that don't support ACPI or MP tables and ROMs for add-in storage
    controllers may depend on this too.
    TODO: Fix the 4 routing links limitation in
          src/arch/i386/boot/pirq_routing.c
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b6e93bd7ad11e7553e6cd220e1a5038930b09cb
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 16 23:15:37 2010 +0000

    Drop W83627THF, it's the same device as W83627THG.
    
    The only difference is that the "G" version is in a Pb-free package, which
    is not relevant from a programmer's view.
    
    We keep W83627THG (and drop W83627THF) because:
    
     - The W83627THF had a CIR device / LDN which doesn't actually exist.
    
     - The W83627THF had no GPIO2, GPIO3 LDNs (were commented out).
    
     - The W83627THF didn't use the PNP_MSC0/1 which is needed/used by boards.
    
    This also fixes an issue on MSI MS7135's devicetree.cb:
    
      device pnp 4e.6 off end           # XXX keep allocator happy
    
    The line above can be (and is) removed, as it was only needed due to the
    incorrect CIR LDN in the W83627THF.
    
    In the iwill/dk8x target: Drop incorrect LDNs 4 and 6, add 0xb.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3226cf8b9cff3dfeda64c189344baa239b375b6e
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Nov 16 22:15:09 2010 +0000

    Drop commented out debug defines
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5876d06b96d9c51fb83ffc236ecf2c239f609abf
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Nov 16 22:10:55 2010 +0000

    Forgot to remove one set of SET_FIDVID defines
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 76e8152c3924d52fc700b8eee656aa16f88f6e3a
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Nov 16 21:25:29 2010 +0000

    Move the SET_FIDVID* family of configuration options to Kconfig and
    make their defaults more obvious.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f02daf19bd74de76a7fe5da9b4d03e767c9fc47
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Nov 16 00:41:17 2010 +0000

    back out parts of #6073
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20c3d77d98481f62df4f54cd2b546170a81fe449
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Nov 15 21:09:57 2010 +0000

    fix random breakage
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c2bf26d2477aee7d606a5933017f9f98f4e82303
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Mon Nov 15 19:44:42 2010 +0000

    Move RCBA defines to northbridge (instead of mainboard)
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a69d978be8a068944466e776de87527fb104a878
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Nov 15 19:35:14 2010 +0000

    C and other Super I/O cosmetic fixes.
    
     - Random coding style, whitespace and cosmetic fixes.
    
     - Consistently use the same spacing and 4-hexdigit port number format
       in the pnp_dev_info[] arrays.
    
     - Drop dead/unused code and less useful comments.
    
     - Add missing "(C)" characters and copyright years.
    
     - Shorten and simplify some code snippets.
    
     - Use u8/u16/etc. everywhere.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e9323e5bef293c051d9fd982214e6db2e3305ee
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 14 21:48:14 2010 +0000

    Add a target for the ASUS A8V-E Deluxe (trivial).
    
    For now this is a plain copy of the ASUS A8V-E SE target, I reported
    that most of the code also works (sort of) for the ASUS A8V-E Deluxe
    a long while ago, see
    
      http://www.coreboot.org/pipermail/coreboot/2008-March/031866.html
      http://www.coreboot.org/ASUS_A8V-E_Deluxe
    
    There will be a bunch of changes necessary though (devicetree.cb, mptable.c,
    ACPI, etc) which do not apply to the A8V-E SE, so we need an extra target.
    
    Also: Increase ID_SECTION_OFFSET on the VIA K8T890/K8M890 southbridge, as
    otherwise there will be build errors if the MAINBOARD_PART_NUMBER string
    gets too long (as is the case for "A8V-E Deluxe"). The error is:
    
      ld: section .id loaded at [00000000ffffffd2,00000000ffffffef] overlaps
      section .romstrap loaded at [00000000ffffff80,00000000ffffffd3]
    
    (both with stock Debian gcc and with xgcc)
    
    Increase ID_SECTION_OFFSET (default 0x10) to 0x80 as other southbridges do.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0675d5c34f90d0b2a3864d0f30461dfe696374f0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 14 20:10:11 2010 +0000

    CK804/MCP55 devicetree.cb cosmetic and indentation fixes.
    
    Add a few more comments for the entries, and also change the devicetree.cb
    files to the more compact and better readable variant with indentation level
    of 2 spaces (instead of random mix of tabs and spaces).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 727edb0b320e46acc8ab272fdec87e6444203bfe
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Nov 14 14:39:29 2010 +0000

    Return 0, (as for 40pin cable if SB not found)
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5d72eb5e8eda5e7b8a653a4e9b3bba2d4adbba9e
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sun Nov 14 14:17:29 2010 +0000

    Move cable detect logic to a weak function in vt8237r_ide.c and add
    an override function in m2v/mainboard.c
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d441afda9106d000ff1d518bad01e98cfb26630e
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sun Nov 14 14:12:14 2010 +0000

    Currently the
            cablesel |= (sb->ide0_80pin_cable << 28) |
                        (sb->ide0_80pin_cable << 20) |
                        (sb->ide1_80pin_cable << 12) |
                        (sb->ide1_80pin_cable << 4);
    in vt8237r_ide.c ends up doing
    	cablesel |= 0xfffffff0;
    (with both bits set to 1) which is probably not the intended result. ;)
    
    After a short discussion on irc the consensus was to change the
    bitfields to u8 as it's probably not worth it using bitfields here.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3cce2f3c4ff4af4a386bddd49c92a55ad9cefa2
Author: Scott Duplichan <scott@notabs.org>
Date:   Sat Nov 13 19:07:59 2010 +0000

    MTRR related improvements for AMD family 10h and family 0Fh systems
    
    -- When building for UMA, reduce the limit for DRAM below 4GB
       from E0000000 to C0000000. This is needed to accomodate the
       UMA frame buffer.
    -- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En
       and Tom2ForceMemTypeWB) are not set consistently across cores.
    -- Enable TOM2 only if DRAM is present above 4GB.
    -- Use AMD Tom2ForceMemTypeWB feature to avoid the need for
       variable MTRR ranges above 4GB.
    -- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing
       this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for
       DRAM above 4GB. AMD systems use this option to conserve MTRRs.
    -- Northbridge.c change to deduct UMA memory from DRAM size reported
       by ram_resource. This corrects a problem where mtrr.c generates an
       unexpected variable MTRR range.
    -- Correct problem causing build failure when CONFIG_GFXUMA=1 and
       CONFIG_VAR_MTRR_HOLE=0.
    -- Reserve the UMA DRAM range for AMD K8 as is already done for AMD
       family 10h.
    Tested with mahogany on ECS A780G-GM with 2GB and 4GB.
    Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5960fb3dbd5c942d3c11f06dcd0c55f940444260
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Fri Nov 12 20:46:02 2010 +0000

    mainboard/asus/m2v: Set DDR2 voltage to 1.8V
    
    The power-on default is 1.95V, set the DDR2 voltage to
    standards-conforming 1.8V.
    
    I also measured with a multimeter to confirm this.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e85e0c7c54aa6a3b32918fc218d585df70b23eda
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Nov 12 09:46:30 2010 +0000

    Consensus seems that this is wanted, integrated into the tree somehow.
    This isn't hooked up anywhere, so won't affect anything, except for
    developers trying to remove configuration #defines.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab940df3315549468e79d31d0b86874830816590
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Thu Nov 11 22:25:55 2010 +0000

    Add support for Fintek F71872 superio.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5330dd91741d12ae52b9c5db179c1a6c24f3e56c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 11 13:14:55 2010 +0000

    Remove superfluous Super I/O res0/res1 lines.
    
    The pc_keyboard_init() function no longer takes any base addresses
    since r5152 (passed in via res0/res1 variables previously), so drop them.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1dcd26cddc477c1274bef30ad3deb7d04f2db843
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Thu Nov 11 05:12:01 2010 +0000

    Add VT8237A id to src/southbridge/via/vt8237r/bootblock.c
    
    I missed this one since it was working anyway, since
    "The LPC BIOS ROM is always accessed when ISA addresses
     FFF80000-FFFFFFFF and 000F0000-000FFFFF are decoded" (VT8237R datasheet)
    And the rom I use for testing is smaller than this 512KB default range.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e080bcabd0d58200211bcec38d10d516f3153aaf
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Thu Nov 11 05:08:33 2010 +0000

    Add pci id and ops for VT8237A SATA controller
    
    Needed to change class from raid to ide so seabios can boot from it.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f00e0c80072ba8cb42000a15e0eee202f4da20f
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Wed Nov 10 22:09:42 2010 +0000

    Use the new mptable_write_buses() on the ASUS M2V.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca033311f9366830fd72b4f4fe9b3bb16f6fb176
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Wed Nov 10 19:08:52 2010 +0000

    Add mptable for ASUS M2V.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d1a1d57adca92dd71f62dfb9363def532c3fc0e6
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 10 18:22:11 2010 +0000

    Restructure i3100 Super I/O driver to match the rest of the codebase.
    
     - i3100_early_serial.c:
    
        - Split out enter/exit functions as the other Super I/Os do.
    
        - Make i3100_enable_serial() take a device_t as usual, and convert
          it to use the standard pnp_* function instead of open-coding
          the same functionality by hand.
    
        - Factor out i3100_configure_uart_clk() from i3100_enable_serial(),
          we do the same in various other Super I/Os, e.g. ITE ones.
    
     - Add some #defines for register / bit values and some comments.
    
     - Only functional change: Don't set bit 1 of SIW_CONFIGURATION, it's
       marked as "READ ONLY, WRITES IGNORED" in the datasheet.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 340fa9396b4b73fd894a15fe48882c98d74292ce
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 10 14:53:36 2010 +0000

    Random Winbond Super I/O cosmetic and coding-style fixes.
    
     - Whitespace, coding style, and typo fixes.
    
     - Drop unused/obsolete "#config chip.h".
    
     - Use u8/u16/etc. everywhere.
    
     - Use pnp_read_config()/pnp_write_config() instead of open-coding them.
    
     - Use pnp_set_logical_device() instead of open-coding it.
    
     - W83627EHG: Fix incorrect enable_hwm_smbus() code comment.
    
     - Use ARRAY_SIZE.
    
     - w83627hf/superio.c: w83627hf_16_bit_addr_qual(): Bugfix, the code was using
       'dev->path.pnp.port >> 8' as config port, which is incorrect in superio.c
       (which has a "real" device_t struct, in contrast to *_early_serial.c which
       uses "unsigned" as device_t where 'dev >> 8' is required).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 02d66fd1bf3e5548dc5edaed074d2946fe5a37df
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Nov 10 02:12:05 2010 +0000

    Make amdk8 printk_raminit() accept just a single string parameter
    
    The function is called with no format specifiers in the first parameter
    throughout the code, so it needs to work also with just one parameter.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5015f79857738c47d98b01446eb0e248ba835f5a
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Nov 10 02:00:32 2010 +0000

    Ensure that config options hidden by r6054 have defaults, and fix MALLOCDBG()
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a953f371ddc0cebf2b3b9d1eebeb857e0567c709
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 10 00:14:32 2010 +0000

    Debugging facility improvements.
    
     - Hook up malloc() debug code via CONFIG_DEBUG_MALLOC. Only show it in
       menuconfig if at least DEBUG or SPEW are selected as loglevel, as this
       code does additional printk(BIOS_DEBUG, ...) calls which would otherwise
       not be visible anyway.
    
     - Similarly, make DEBUG_CAR and REALMODE_DEBUG only visible if thr DEBUG or
       SPEW loglevel is selected.
    
     - Get rid of a custom "debug" macro, use printk() as usual.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f228a6cf93f662c3d178198aa9f8ff4d129227b3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 10 00:08:42 2010 +0000

    ITE IT8661F changes to match the common code structure.
    
     - it8661f_enable_serial() is now in the usual format, using pnp_* functions.
    
     - Factor out pnp_enter_ext_func_mode()/pnp_exit_ext_func_mode().
    
     - Factor out it8661f_set_clkin() to set the CLKIN to 24/48MHz.
    
     - Factor out it8661f_enable_logical_devices(), might not be needed though.
       We leave it here until it's confirmed on hardware that it's not needed.
    
     - Move some #defines to it8661f.h.
    
     - Drop no longer used it8661f_sio_write().
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c29246739af6faa56ceba4e912968464cbc9f4de
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Tue Nov 9 22:31:11 2010 +0000

    This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up the
    Linux kernel, which was previously complaining that the MTRR setup
    is wrong, if the cpu supports more than CONFIG_CPU_ADDR_BITS bits of
    address space.
    
    Shamelessly copied from Linux arch/x86/kernel/cpu/mtrr/main.c
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Scott Duplichan <scott@notabs.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b3cac2a6c8790abda72e386ed60dea39f322a54
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Tue Nov 9 22:18:28 2010 +0000

    Add acpi tables and dsdt.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6222fe04437d60630d894259cd11e3e48b132fbe
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Tue Nov 9 22:11:00 2010 +0000

    Add pirq table for ASUS M2V.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7fa0819ecf076c283c942d4af5e9bcfaf8c4bd49
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Nov 8 20:55:24 2010 +0000

    Add #include guards to all Super I/O header files (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f648d619c994f856d6ca7d86fe18c532a974d31b
Author: Ward Vandewege <ward@gnu.org>
Date:   Mon Nov 8 17:41:43 2010 +0000

    We can't print this early.
    
    This patch fixes a hang on
    
      supermicro/h8dme
      supermicro/h8dmr
      supermicro/h8dmr_fam10
    
    and possibly on other mcp55-based boards.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c6bae213ea55e1436e010706560d86120b0b286
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Nov 8 15:16:30 2010 +0000

    Random ITE Super I/O fixes.
    
     - Drop some of the less useful / outdated / duplicated comments.
    
     - Simplify and streamline some code to look like the other Super I/Os.
    
     - Use u8/16/etc. everywhere.
    
     - ITE IT8718F: Add missing GPIO LDN.
    
     - Add missing braces around SIO_DATA #defines, potential bug even.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6018e1ba7f797db3a7f1ae34bdb10ec1fa5c8a6c
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun Nov 7 20:11:39 2010 +0000

    DSDT.asl should not report the AMD SB600/SB700 RTC as Intel PIIX4
    compatible. The extended cmos is accessed differently for AMD
    and Intel RTCs. Not sure what if any OS cares about this distinction,
    but non-Intel compatible seems like a safer way to report the AMD RTC.
    Tested with Win7 on Mahogany_fam10 and kino-780am2-fam10.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e6305f4abd12bdc0a091d16bc091774f72aa55c
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sun Nov 7 20:08:45 2010 +0000

    Should be part of 6044. I forgot to add the directory :/
    
    This adds the m2v directory and necessary files to src/mainboards/asus and
    adjusts the Kconfig.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a6dfebf39c3de9140d3b0923a0043010680535d
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sun Nov 7 19:27:45 2010 +0000

    This adds the m2v directory and necessary files to src/mainboards/asus and
    adjusts the Kconfig.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a151f27cb02d437fe3123bda700f252437226fab
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sun Nov 7 19:17:18 2010 +0000

    Depends on the "Introduce get_vt8237_lpc() function" and
    "Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid()" patches.
    
    This adds VT8237A specific VLINK/LPC init in vt8237r_early_smbus.c
    I ran some tests and apparently both the
    
    |			/* So the chip knows we are on AMD. */
    |			pci_write_config8(devctl, 0x7c, 0x7f);
    
    and
    
    |	/*
    |	 * Allow SLP# signal to assert LDTSTOP_L.
    |	 * Will work for C3 and for FID/VID change.
    |	 */
    |	outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
    
    in vt8237r_early_smbus.c are needed on VT8237A, otherwise I get a (non-fatal)
    fid/vid change error on boot.
    
    While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
    vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7714cd051569059ab6779608920fe49107e08631
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sun Nov 7 18:57:10 2010 +0000

    This adds the VT8237A LPC pci_locate_device call in vt8237r_early_smbus.c
    Depends on the "Introduce get_vt8237_lpc() function" patch.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e165d41b08bcf121cc5d9eaae20cd33f0f3180af
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sun Nov 7 18:51:13 2010 +0000

    Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid() too.
    I broke this out into a seperate part to keep the other half as
    straight-forward as possible.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef2928e708b881d6d54c2308a4c596a6d003743b
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sun Nov 7 18:46:13 2010 +0000

    Instead of duplicating the pci_locate_device calls multiple times,
    add a get_vt8237_lpc() function.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6953eeb3427c8f72d88d8eff52cb211bc2f224dc
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sun Nov 7 18:37:39 2010 +0000

    Add pointer to public PCIe bridge documentation on
    http://linux.via.com.tw/ as VX800 seems to be compatible.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 113b29f3c1b46b0aaefb740507245d5f7e9c3352
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sun Nov 7 18:28:34 2010 +0000

    This adds VT8237A specific VLINK/LPC init functions in vt8237_ctrl.c
    and vt8237r_lpc.c.
    
    While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(),
    vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init().
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9e16dffd3807ef713c891535bc13a9f92a4f649
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Nov 7 18:25:11 2010 +0000

    Remove empty files added by accident. Sorry about that.
    Rudolf
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7bbd7f2318efc8958d206fab19d454b4484b74ce
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Nov 7 18:20:51 2010 +0000

    Move K8_ALLOCATE_IO_RANGE to Kconfig.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2210135468de313c6fbf60735ef9028d6c8fb335
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Sun Nov 7 18:20:32 2010 +0000

    This adds the VT8237A LPC device id and the pci_driver struct in
    vt8237r_lpc.c
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9fb2e3ab762c5428d9bee0a20eb0a4dc413be62a
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Nov 7 17:49:05 2010 +0000

    FIRST_CPU, SECOND_CPU, TOTAL_CPUS are only used in one
    other place, and that defines these symbols itself (and
    identical, too). Drop them.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 168acf9bb69d323e302cf3d03176ff7d337bbe8d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 7 17:47:01 2010 +0000

    Fix a few incorrect GIGABYTE board names (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fbd85a13aeb49aa73bec899e284347f7640909a0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 7 16:49:31 2010 +0000

    ECS P6IWP-Fe: Fix typo, add missing license header.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68854f3cc96ab9eed30c347fdf029dac5c47d792
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Nov 7 08:15:13 2010 +0000

    Remove unused defines (UART_*)
    All other uses of these symbols have their own (identical)
    definitions.
    
    abuild-tested and trivial
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c02368e2d2e0574cf3999939f7cd26407cdf93a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Nov 6 23:36:49 2010 +0000

    Various Super I/O fixes and corrections.
    
     - VIA VT1211:
       - Add missing LDNs and respective code to handle them.
       - Add some TODOs for other stuff that needs fixing.
       - Use VT1211_SP1 instead of hardcoding the LDN number (2).
       - Fixup pnp_dev_info[] as per datasheet, but some TODOs remain.
       - Various coding style fixes and changes to u8/u16/etc.
    
     - Serverengines Pilot: Various coding style fixes and changes to u8/u16/etc.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9915944b18847b5e83b664a3e445645a2a4c8578
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Nov 6 00:57:19 2010 +0000

    Remove comments that are obsolete since r6028.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 00e1460a8367c4199358034064329abcfb7e5c28
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Nov 5 22:59:49 2010 +0000

    Move QRANK_DIMM_SUPPORT to Kconfig, removing it from romstage.c
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d51122df4e0bb23758a497268efaccc4fc1ddd75
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Nov 5 16:17:46 2010 +0000

    Various PIRQ/MPTABLE/ACPI Kconfig fixes.
    
     - Use HAVE_ACPI_TABLES, HAVE_MP_TABLE, and HAVE_PIRQ_TABLE (instead of
       GENERATE_*) in the board's Kconfig file, as all other boards do.
    
     - Add missing HAVE_ACPI_TABLES/HAVE_MP_TABLE/HAVE_PIRQ_TABLE to boards
       which have the respective files. The only exception: EPIA-M700 doesn't
       select ACPI, as it doesn't have dsdt.asl. Added a comment that the user
       is supposed to run the 'get_dsdt' script and edit Kconfig afterwards.
    
     - Fix minor warning/error in
       src/mainboard/msi/ms9652_fam10/acpi_tables.c,
       now that the file is actually used.
    
     - msi/ms9652_fam10: use #include instead of Include() as we usually do
       now.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit adc975098df1e878d181c14c88c74d4d8014d74a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Nov 5 12:44:25 2010 +0000

    Follow-up for r6025, do 0x87 twice in superio.c, too.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 27770c93d49cfd5f5cdec7094259ae600ca4bcca
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Nov 5 07:59:06 2010 +0000

    According to the description in datasheet of f71889,
    
    "To enable configuration, the entry key 0x87 must be written to
    the index port"
    
    "
     -o 4e 87
     -o 4e 87	(enable configuration)
     -o 4e aa	(disable configuration)
    "
    This piece of text appears in most of the datasheet of fintek superio.
    It doesnt say it quite clear, but it seems that the 0x87 should
    be written twice. I tried on f81865, which is not in the coreboot tree
    yet. If the 0x87 is only written once, you can only R/W the index/data
    port once. All the subsequent RW will fail. Writing twice will be ok.
    
    Plus, in the superiotool, the function enter_conf_mode_winbond_fintek_ite_8787
    also write 8787.
    
    The fintek superio chips seem to enable the UART automatically when the
    power is on. So I didnt find it failed to access.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e40e6ba4d087ec89dc6029475523ef033896822
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Nov 5 00:34:12 2010 +0000

    Add detection support for the Fintek F81865/F81865-I.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eca32808cb271f3f11c2fdb29eaf71c7f192e765
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Fri Nov 5 00:23:11 2010 +0000

    Add Kconfig CPU speed selection to Geode GX2 boards.
    
    This is Abuild and boot tested.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f29b3b68c849ea6cb8124e11d06427ab92bc4451
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Fri Nov 5 00:19:21 2010 +0000

    GX2: Define the unused DIMM1 to 0xFF to make it obvious it is a bogus value.
    
    This is Abuild and boot tested.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a1e2c5607902e392cf390efa77a74c16fdb5e027
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Fri Nov 5 00:13:14 2010 +0000

    Remove banner wrapper function and unify print(k) usage.
    
     - Drop banner(), use printk()s instead.
    
     - Uncomment a few printk()s, if a users doesn't want to see them he/she
       can lower the debug level.
    
     - Replace print_emerg() with printk(BIOS_EMERG) etc.
    
    Also change 'Assymetirc' into 'Asymmetric', thanks to Idwer for spotting.
    
    This is Abuild and boot tested.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d3418849de907b82e3a5cca9969d261553f61a0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Nov 5 00:07:13 2010 +0000

    Fintek and Intel i3100 Super I/O cleanups.
    
     - Drop commented out "config chip.h" and a duplicate link to a datasheet.
    
     - F71805F -> F71805F/FG, to mention all variants.
    
     - Use u8/u16/ etc. everywhere.
    
     - Add a missing (C) line.
    
     - Fix up a bunch of pnp_dev_info[] structs according to the datasheets.
    
     - Fintek F71889: Drop res1/PNP_IO1 from KBC, there's no 0x62/0x63 register
       pair on this Super I/O.
    
     - Fintek F71863FG: This Super I/O _does_ have a keyboard/mouse LDN, add the
       respective code in superio.c. Also: Add missing LDNs to f71863fg.h.
    
     - i3100: Add some more comments and datasheet infos.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e4870474b9026ad6b2ccabe59a8623e28722007f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 4 23:23:47 2010 +0000

    Various cosmetic and coding style fixes in src/devices.
    
    Also:
    
     - Improve a few code comments, fix typos, etc.
    
     - Change a few more variable types to u8/u16/u32 etc.
    
     - Make some very long lines fit into 80chars/line.
    
     - Drop a huge duplicated comment, use "@see" to refer to the other one.
    
     - Reduce nesting level a bit by restructuring some code chunks.
    
     - s/Config.lb/devicetree.cb/ in a few places.
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 305e8861d66b050a3e35133603acce69324349fe
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 4 18:33:42 2010 +0000

    Add a rom_enable() function to via/vt8231 and call it from via/epia/romstage.c
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ae7131f2e65ae1d16d31feeedbb303d6f2e2277
Author: Alec Ari <neotheuser@ymail.com>
Date:   Wed Nov 3 21:46:41 2010 +0000

    Add Fintek F71889 Super I/O support.
    
    Untested, but should work mostly (even though some TODOs remain).
    
    Signed-off-by: Alec Ari <neotheuser@ymail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a215b0f0be2116b77192d6a3ec06a5616207432a
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Wed Nov 3 13:24:29 2010 +0000

    Remove some unused code from gx2/raminit.c.
    
    This is Abuild and boot tested.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e98db798c9cbf30dd982fdacbaf0b860c1e42a48
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Wed Nov 3 13:21:41 2010 +0000

    Clean up some more comments and white space in model_gx2/cpureginit.c.
    
    This is Abuild and boot tested.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5beac7f996633733d45df28479c20b7574aa60de
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Wed Nov 3 13:19:50 2010 +0000

    Clean up some comments and white space in gx2/northbridgeinit.c
    and gx2/raminit.c.
    
    This is Abuild and boot tested.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b54585244bbda67908e0baf4c265b85c62868d25
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Tue Nov 2 21:24:29 2010 +0000

    Need to clear downstream read cycle retry bit, or the bus scan will
    hang.  Also need to set lane config to 0x00 for autonegotiation.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d50b43a1289a7ffb9c206a2c39b7568f5b1c3bf2
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Tue Nov 2 20:54:37 2010 +0000

    This adds pci device ids and pci_driver structs for the K8T890 CF
    variant. It also adds additional dev_find_device calls in k8t890_ctrl.c for
    subfunctions 3 and 7.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 76890dde1428741a7c91732b04cc3c95ada9c321
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Mon Nov 1 15:20:27 2010 +0000

    Change Geode GX2 to use the auto DRAM detect code from Geode LX.
    
    Also, change the GX2 boards to use it.
    
    Add a processor speed setting function in human readable MHz and remove
    the useless and broken PLLMSR settings (the processor speed was hardcoded
    to 366MHz in pll_reset.c).
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96446239346128308a9f8500c4018aae579a876d
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Mon Nov 1 14:39:49 2010 +0000

    Remove some unused code.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 809e29ec8fdf49f65f87076005bbc778b9f10caa
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Mon Nov 1 14:36:54 2010 +0000

    GX2: Clean up some white space and comments.
    
    Also, add a copyright header to pll_reset.c.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc9fcf7414c482a480ec9a87d32abd4a77ab1b26
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Mon Nov 1 14:18:11 2010 +0000

    GX2: Change MSR register numbers into more descriptive names.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e5b60bcf0495992557ccd7f23c359d7ab6e8c8fb
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 31 23:24:18 2010 +0000

    Remove definitions of ACPI_SSDTX_NUM to 0, that's the default anyway.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9892166d548d523911263a4a2a550cd03a3309d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 31 19:37:50 2010 +0000

    Remove incorrect IOAPIC lines from some mptable.c files.
    
     - via/epia-n/mptable.c
     - intel/eagleheights/mptable.c (commented out anyway)
     - asus/p2b-d/mptable.c
     - asus/p2b-ds/mptable.c
    
    Some files still incorrectly contain some smp_write_ioapic() lines from
    the original mptable utility target (Supermicro P4DPE), which has one
    IOAPIC in the southbridge (Intel ICH3-S), two IOAPICs contained in
    the first P64H2, and two more in the second P64H2, i.e. 5 IOAPICs in total.
    
    However, none of the boards where this chunk of code is present has
    multiple IOAPICs (and even if they had, the PCI devices where those are
    located would probably be different anyway), so drop the incorrect
    mptable.c contents.
    
    Also drop the lines from the mptable utility, so that future mptable.c files
    don't incorrectly inherit any of this stuff.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 27612ed4f28dd29eecbae6d20ed137d03ca5bbdf
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun Oct 31 14:17:51 2010 +0000

    Fix AMD family 10h engineering sample is reported as 'thermal test kit'.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da22d2190df46f08796088038ddbbd80603c2251
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 30 21:27:13 2010 +0000

    Mptable related fixes for ASUS P2B-DS.
    
     - Add "select IOAPIC" in the board's Kconfig file.
    
     - Set CONFIG_MAX_PHYSICAL_CPUS to 2 on the board. There are two
       CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
       didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).
    
     - Drop useless/duplicated enable_lapic() call from ASUS P2B-DS's romstage.c,
       that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
       are set.
    
     - Rework ASUS P2B-DS mptable.c to fix a number of things:
    
       - Convert it to use mptable_write_buses() as all mptable.c files should do.
    
       - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC).
    
       - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dca8b1b5995291e9ee610e178e1fc7b3f710aeb9
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Fri Oct 29 20:40:06 2010 +0000

    Use common code to set PCI subsystem in mcp55.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7f3f80cf06165fc4e645a88590d7d8c982395de
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Fri Oct 29 15:56:04 2010 +0000

    Deduplicate ck804 subsystem-setting functionality.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb42300f036c1bd1b047ba89104e97ed565f12ef
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 29 14:26:27 2010 +0000

    Drop duplicate HAVE_ACPI_TABLES (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d23f275aa1a1c71391070b40201453026591d937
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Thu Oct 28 19:57:52 2010 +0000

    The no point in having a non-NULL ops_pci pointer when the set_subsystem operation within is NULL anyway.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b34ff66a7a7462a427242c27d01ab241615fe2d3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 28 14:22:20 2010 +0000

    Fix broken build due to missing #if CONFIG_IOAPIC.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 77180546c84278f8e613aa912e432ee084425f88
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 28 08:19:22 2010 +0000

    Add IOAPIC support for Intel 82371EB and fixup SMP on ASUS P2B-D.
    
     - Add enable_intel_82093aa_ioapic() which enables IOAPIC usage in the
       Intel 82371EB southbridge (sets the proper chip-select) and sets an
       IOAPIC ID.
    
     - We only call enable_intel_82093aa_ioapic() if a board does "select IOAPIC"
       as on 82371EB-based boards the IOAPIC is an external chip (not integrated
       in the southbridge) and it's only populated on multi-CPU boards.
       That is, we cannot unconditionally enable it, only on SMP-capable boards.
    
     - Due to the reason explained above, remove "select IOAPIC" from
       src/southbridge/intel/i82371eb/Kconfig, and add it to
       src/mainboard/asus/p2b-d/Kconfig.
    
     - Also set CONFIG_MAX_PHYSICAL_CPUS to 2 on ASUS P2B-D. There are two
       CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
       didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).
    
     - Drop useless/duplicated enable_lapic() call from ASUS P2B-D's romstage.c,
       that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
       are set.
    
     - Rework ASUS P2B-D mptable.c to fix a number of things:
    
       - Convert it to use mptable_write_buses() as all mptable.c files should do.
    
       - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC).
    
       - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.
    
    This is build-tested on ASUS P2B-D, and also boot-tested successfully there.
    On Linux I now get two entries in /proc/cpuinfo (where only one appeared
    before this patch), i.e. both populated CPUs are found.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 706b350be89185def17eb18fa8ccc1310ea1e0ac
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Wed Oct 27 20:32:49 2010 +0000

    Enable CK804 AC'97 audio interface and explicitly enable NIC on A8N-E.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5433a838327d15cb938b4756d0397faccd1ef801
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Wed Oct 27 20:30:32 2010 +0000

    Correct an apparent copy-paste error that shows up at compile time on
    boards using ck804_early_setup.c that select CK804_USE_NIC.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2585d2db2448fc4f4c96645bb19287984a4d460c
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Wed Oct 27 17:41:40 2010 +0000

    Drop referenced-yet-does-nothing static function from ms7135 romstage.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8bed0a4c1b59f701f6866bda5d721a22a0139af
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Wed Oct 27 17:26:57 2010 +0000

    Convert ck804_early_smbus.c to a separately compiled unit.
    Additionally, make the second SMBus more accessible in romstage.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b69cb5a31058c0295f2d810c852cc5b52d77225c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 26 22:46:43 2010 +0000

    Convert some comments to proper Doxygen syntax.
    
    Also, make them all fit in 80chars/column, fix some whitespace issues
    and also some typos I noticed.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b907d321a5d0957f5cbb03d8f9c8d0ff0c23523b
Author: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date:   Tue Oct 26 22:40:16 2010 +0000

    We need to call smp_write_lintsrc() instead of smp_write_intsrc() for
    local ints. This is wrong in most coreboot mptables, probably all
    generated by util/mptable/mptable.c.
    
    After fixing this now XP can boot in MPS mode on my M2V.
    
    Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a8d9938b24e54321b9b68e56af5ea4437cf65d5
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 26 16:10:20 2010 +0000

    Convert all ck804-based boards to tiny bootblock.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9d4212fff2e3a66b3a319a5cf094df539cf7b599
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Oct 26 15:51:57 2010 +0000

    Move bcm5785_enable_rom.c include to where it's used.
    Right now, it breaks the build of bootblock enabled boards
    with that chipset.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3e8542cc498da4a18f66cb7894afa6a49f977c2
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Oct 26 15:11:45 2010 +0000

    reg is only used inside the #if clause, so declare it there. trivial.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45057d2753220dd4100951097d844f56dae93f46
Author: Scott Duplichan <scott@notabs.org>
Date:   Tue Oct 26 05:26:01 2010 +0000

    When gcc 4.5.0 is used, compiling mcp55_early_setup_car.c fails. This change eliminates the compiler warning that causes the build to fail.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 55dc223ccd0bb2a34ec46f36b36b658ecd677c2f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 25 15:32:07 2010 +0000

    Factor out common mptable code to mptable_init().
    
     - Drop sig[], oem[], and productid[] fields in all mptable.c files, no
       longer needed. The sig[] is always the same ("PCMP"), the oem[] is
       currently also always the same ("COREBOOT"), and productid is being
       passed into mptable_init() directly as string now.
    
     - LAPIC_ADDR is passed in as parameter, too. While at the moment it's
       always the same value that is passed in, the LAPIC base address could
       also be relocated theoretically, so keep it as parameter for now.
    
     - Fix a few productid entries, they were (partially) incorrect:
    
       - DK8S2 (was "DK8X", copypaste)
       - 939A785GMH (was "MAHOGANY", copypaste)
       - X6DHE-G (was "X6DHE", incomplete board name)
       - H8DME-2 (was "H8DMR", copypaste)
       - H8QME-2+ (was "H8QME", incomplete board name)
       - X6DHE-G2 (was "X6DHE", incomplete board name)
       - X6DHR-iG2 (was "X6DHR-iG", incomplete board name)
       - GA-M57SLI-S4 (was "M57SLI", incomplete board name)
       - KINO-780AM2 (was "KINO", incomplete board name)
       - DL145 G1 (was "DL145G1", small fix as per vendor website)
       - DL145 G3 (was "TREX", wrong board name)
       - DL165 G6 (was "HP DL165 G6", drop vendor)
       - S2912 (was "S2895", copypaste)
       - VT8454c (was "VIA VT8454C", drop vendor, lower-case "c")
       - EPIA-N (was "P4DPE", copypaste)
       - pc2500e (was "PC2500", incorrect name)
       - S1850 (was "S2850", copy-paste)
       - MS-7135 (was "MS7135")
       - MS-9282 (was "MS9282")
       - MS-9185 (was "MS9185")
       - MS-9652 (was "K9ND MS-9652")
       - Ultra 40 (was "ultra40")
       - E326 (was "E325", copypaste)
       - M4A785-M (was "TILAPIA", copypaste)
       - P2B-D (was "ASUS P2B-D", drop vendor)
       - P2B-DS (was "ASUS P2B-DS", drop vendor)
    
     - Adapt the mptable utility to use mptable_init() too.
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 11abcc0ae529e1a5c562f439df65ac091a322683
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Oct 25 02:12:04 2010 +0000

    Make ectool -i work; add missing break
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7c1fb7b79860baf1af2110b7fb90903b9cdcfa99
Author: Scott Duplichan <scott@notabs.org>
Date:   Sun Oct 24 16:22:11 2010 +0000

    Running a checked build of Windows is needed for understanding its various BIOS related BSODs. Win7 checked build complains when running coreboot+seabios:
    
     FADT revision inconsistent with length.
         Revision:        0x1
         Length:          0xf4
         Expected Length: 0x74
    
    Change the FADT revision from 1 to 3 to match its length and prevent the Windows checked build assert.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7015989464d9d12f3250983bd5b095b13e255724
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 24 14:19:09 2010 +0000

    Add small comment about LDN 5 on F71872F/FG / F71806F/FG.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 760498f8ea96096314900861d492f2125121a112
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Sun Oct 24 14:18:55 2010 +0000

    Fix superiotool build on non-NetBSD x86_64.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 51ac8382dc99be21760bb40a641325b276324a83
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Sun Oct 24 14:10:35 2010 +0000

    Provide for I/O space access on NetBSD.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f91d813efe80045e322f7c6a767b403911b8a1c
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Sun Oct 24 13:50:13 2010 +0000

    Add inteltool support for FreeBSD.
    
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Acked-by Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4d77dc74d6500e651a6d4e477f9d499915cac7f
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Sun Oct 24 13:42:32 2010 +0000

    Update superiotool support for FreeBSD, Makefile fixes.
    
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d74c7748aaad02668eb1efeb0cf4b165fd73d42f
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Sun Oct 24 12:43:41 2010 +0000

    Teach superiotool about the registers in a Fintek F71806 (and F71872).
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c009276f17730c1c224d30522bd77b635edd6f1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 20 20:21:27 2010 +0000

    Revert sblk/sblink change, use sblk like the rest of the codebase does.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa78d998d51d36a3d5e491e51fd76d6ddff3c14a
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Oct 20 19:23:22 2010 +0000

    Now that no boards set RAMBASE < 1M, get rid of some dead code.  Trivial.
    
    It's probably time to reconsider moving all fam10 boards to RAMBASE = 1M.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bda153be7365ab48b5414ce3a72267f566ced3f3
Author: Scott Duplichan <scott@notabs.org>
Date:   Tue Oct 19 21:08:11 2010 +0000

    For AMD family 10h processors, msr c0010058 is always programmed
    for 256 buses, even if fewer are configured. This patch lets msr
    c0010058 programming use the configured bus count, CONFIG_MMCONF_BUS_NUMBER.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 115e66018a28e66eb8d4388633f1299ede24bf94
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 19 15:25:06 2010 +0000

    Drop duplicate SB_HT_CHAIN_ON_BUS0 in Kconfig for MS-7135.
    Trivial.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f566b7a60a8021399d0603f4a7cfb608e3dfac2
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 19 15:17:18 2010 +0000

    Use the correct (W83627THF, not W83627HF) superio code in MS-7135 romstage.
    This is consistent with the device tree and the chip actually on the board.
    Trivial.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e6f4cfa9cb993b92170989cb76786206fa96899
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 19 14:02:10 2010 +0000

    Copy ICH4 hard_reset() for 6300ESB.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b8700b5029421bebdbf74c38944be2baff44cee
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 19 13:49:11 2010 +0000

    Remove unused variables from 6300ESB smbus_write_block().
    
    #ifdef DEADCODE out smbus_write_byte() and smbus_write_block() as
    they are static and nothing uses them or are incompletely implemented.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9fe50695841aa44713f5ee0486ca25f7d39b724e
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 19 13:39:38 2010 +0000

    Correct spelling of "spacing" (in comments).
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d208c1aa2cfa2dd7da58c1f9d290310a2e10fb4a
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 19 13:11:56 2010 +0000

    Use mptable_write_buses().
    Remove unhelpful comment.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6b0ade7550196a9e62974833a99d172618cbb56f
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 19 13:03:34 2010 +0000

    Modernize socket_754 Kconfig with CAR and address bits information.
    Also, update the board that uses this socket to match.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1ba2eee2b4f38231254525a6a4ffcf1999dea636
Author: Scott Duplichan <scott@notabs.org>
Date:   Tue Oct 19 04:58:49 2010 +0000

    Revision 5966 changed the end of line style of the 3 modified files. This change restores the original end of line style.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Scott Duplichan <scott@notabs.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 236aef238f6e5c735cc9f253746def582fbaf8ff
Author: Scott Duplichan <scott@notabs.org>
Date:   Tue Oct 19 04:36:42 2010 +0000

    To reduce boot time, remove the double startup IPI and 10 ms delay from lapic_cpu_init.c. The change is
    currently restricted to recent model AMD processors, though it could be applied to others after successful testing.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af786b618d5e1aafe1e5b8d9ed49b55903381a2e
Author: Scott Duplichan <scott@notabs.org>
Date:   Tue Oct 19 04:26:17 2010 +0000

    When debug logging is enabled, a message such as '* AP 02 timed out:02010501'
    is sometimes logged. The reason is that the AP first sets a completion value
    such as 0x13, which is what function wait_cpu_state() is waiting for. Then a
    short time later, the AP calls function init_fidvid_ap(). This function sets
    a completion value of 01. When logging is off, wait_cpu_state is fast enough
    to see the initial completion value for each of the APs. But with logging
    enabled, one or more APs may go on to complete function init_fidvid_ap, which
    sets the completion value to 01. While mostly harmless, the timeout does
    increase boot time. This patch eliminates the timeout by making function
    wait_cpu_state recognize 01 as an additional valid AP completion value.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d7acdfb44acfcebe6107b7286c5e4b79f25a33e0
Author: Scott Duplichan <scott@notabs.org>
Date:   Mon Oct 18 04:01:12 2010 +0000

    This patch enables SB700 option PrefetchEnSPIFromHost in early setup.
    It affects only systems booting from SPI flash, not those booting from
    LPC flash. By default, the SB700 reads dwords from the SPI flash chip.
    Setting PrefetchEnSPIFromHost causes the SB700 to read entire cache
    lines from the flash chip.
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c104cb0d9d7f1a6cc3549d7177d1c36ad4d7e5ac
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Mon Oct 18 00:21:39 2010 +0000

    update intel microcode files.
    
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 321ebe095308d207d6b565122b0ad01996e3df3b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 18 00:20:40 2010 +0000

    Make update-microcodes.sh executable.
    
    This also has an additional benefit:
    
    I was running "sh update-microcodes.sh" previously which broke with
    
      update-microcodes.sh: 102: Bad substitution
    
    due to the script requiring /bin/bash instead of /bin/sh (uses bash-specific
    stuff). Running "bash update-microcodes.sh" works fine.
    
    Making the script executable in svn reduces the likelyhood of people
    running the script with differing shells that may not work.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d453dd0c4d8c31e508abea8dd14e616b9c61da71
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 18 00:00:57 2010 +0000

    Cosmetics and coding style fixes in devices/*.
    
     - Whitespace and indentation fixes in various places.
    
     - Fix various typos.
    
     - Use u8, u16 etc. everywhere.
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a600a3f7000b3cc1bb14999bd834103b7c4c0b13
Author: Stefan Reinauer <stepan@coreboot.org>
Date:   Sun Oct 17 23:55:17 2010 +0000

    update intel microcode update script
    Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
    Acked-by: Stefan Reinauer <stepan@coreboot.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a14b11726960b3ab49f9a7cef1ad740794a88be3
Author: Keith Hui <buurin@gmail.com>
Date:   Sun Oct 17 22:07:08 2010 +0000

    Removes model_65x CPUIDs from model_6xx code.
    They now have their own home at cpu/intel/model_65x.
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 676d0298a1d3853034d86053dd71d3b4065c4026
Author: Liu Tao <liutao1980@gmail.com>
Date:   Sun Oct 17 21:59:43 2010 +0000

    In the RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set
    to zero, so for boards with RS780 not on CPU's HT chain 0, the function will
    mis-configure the MMIO dst-link routing, and the following enable_pcie_bar3()
    function will hang when it visits the MMIO.
    
    The following patch fixes the problem, and is tested on a K8 board with RS780
    on HT chain 1.
    
    Signed-off-by: Liu Tao <liutao1980@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dfecd2740b9ecc6950bf08b8b40573158541d56a
Author: Liu Tao <liutao1980@gmail.com>
Date:   Sun Oct 17 21:34:45 2010 +0000

    We currently read the CPU HT speed from HT chain 0's register.
    Fix that to read the register from the chain where the SB chip is on.
    
    Signed-off-by: Liu Tao <liutao1980@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6a106286bb30bd0532ffdd2443e8add52072967
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 17 19:30:58 2010 +0000

    Add more missing GPL-headers, fix inconsistencies in others.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8af6d5574ba6d9ea847b27ae582396240b3e8d41
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 17 19:13:18 2010 +0000

    Use common GPL-header format in CK804 files, add missing ones (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c1ee42913534ea2ef1747cfc6bfd1ec687a0f9a3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 17 19:01:48 2010 +0000

    Various Doxygen comment fixes, typo fixes, etc.
    
     - Fix incorrect argument names for @param entries.
    
     - Add missing @param and @return entries, partly as TODOs.
    
     - s/@returns/@return/, that's a typo.
    
     - Small whitespace fixes while I'm at it.
    
     - Drop useless @brief commands, they just clutter the comments and make them
       harder to read. Doxygen has an option to always use the first sentence
       of a Doxygen-comment as @brief automatically (should be on per default).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b14fb6abd6cc04ea9f06e4dedd5f13c183e9450e
Author: Keith Hui <buurin@gmail.com>
Date:   Sat Oct 16 08:45:31 2010 +0000

    Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory.
    
    abuild-tested. I have no Deschutes CPUs to boot test this with.
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af8b2b91b48229d804f1f391e294467cd91adef5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 15 07:47:51 2010 +0000

    Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.
    
    This CAR implementation hardcodes the Cache-as-RAM base address to:
    
      0xd0000 - CacheSize
    
    so the DCACHE_RAM_BASE is never actually used for this implementation
    and these sockets.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e49903650cbb8a924a18bcfa28b270f79ef398a1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 14 23:40:10 2010 +0000

    Cosmetics in ioapic.c (trivial, no functional changes).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 212d0a2eaefac97c55ad932e775be68a975fe164
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 13 23:00:41 2010 +0000

    Remove various .c #includes from Intel i810/i82801ax/i82801bx boards.
    
    This is pretty much the same mechanism as in r5929.
    
     - Use 'romstage-y' to turn i82801ax_early_smbus.c and i82801bx_early_smbus.c
       into distinct compilation units, and don't #include the files anymore
       in romstage.c files.
    
     - Ditto for northbridge/intel/i82810/raminit.c, and
       northbridge/intel/i82810/debug.c.
    
     - Add various header files which are now needed, drop unused includes.
    
     - Make functions that need to be visible non-static.
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6529c2a7172f166f53ec3d6204dd375cd6441579
Author: Keith Hui <buurin@gmail.com>
Date:   Wed Oct 13 17:00:42 2010 +0000

    Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x.
    
    abuild-tested. Boot tested on P2B-LS.
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab50d62ea6867712eca79e9f0770d6ac35f72ce1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 13 08:21:44 2010 +0000

    Convert all Intel i810 boards to CAR.
    
     - Drop "select ROMCC" from the boards, as well as early_mtrr stuff.
    
     - Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the
       usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables.
    
     - In socket_PGA370/Makefile.inc add:
       cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
    
     - Other smaller related fixes.
    
    Abuild-tested and boot-tested on MSI MS-6178.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 51eafdeae621f1b04db51c3b4a690fa993aa48a0
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Oct 13 06:23:02 2010 +0000

    Enable or disable the power button in Kconfig
    
    Some mainboards need to disable the power button to avoid turning off
    right after being turned on, while other boards ship with a jumper over
    the power button and should allow the user to configure the behavior.
    
    This adds infrastructure in the form of four mutually exclusive options
    which can be selected in a mainboard Kconfig (power button forced on/off,
    and user-controllable with default on/off) and one result bool which
    source code can test. (Enable the button or not.)
    
    The options have been implemented in CS5536 code and for all mainboards
    which select SOUTHBRIDGE_AMD_CS5536, but should be used also by other
    chipsets where applicable. Note that if chipset code uses the result
    bool ENABLE_POWER_BUTTON, then every board using that chipset must
    select one out of the four control options in order to build.
    
    All touched boards should have unchanged behavior, except
    pcengines/alix1c, traverse/geos and lippert/hurricane-lx where the
    power button can now be configured by the user.
    
    Build tested for alix1c, alix2d, hurricane-lx and wyse-s50. Confirmed
    to work as advertised on alix1c both with button enabled and disabled.
    
    Includes additional traverse/geos changes from Nathan and
    lippert/hurricane-lx changes from Jens to correctly use the new
    feature on those boards.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Aurelien Guillaume <aurelien@iwi.me>
    Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2573bd23727db672b22f3840ce91d08ec3aea5d
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Wed Oct 13 05:16:48 2010 +0000

    Fix a stupid bug in rs780 and rs690 code.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Scott Duplichan <scott@notabs.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 89122856e06822e08040cc9e87496c9b649a743b
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Wed Oct 13 02:46:59 2010 +0000

    Trivial. Clean up code and add some comments.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e9c1cd693101bad8a8947d9a0cad7c71cb77e0e
Author: Keith Hui <buurin@gmail.com>
Date:   Tue Oct 12 23:22:08 2010 +0000

    Add missing include of model_6bx for slot_1.
    
    I could no longer boot my P3B-F with my Tualeron and r5938. Dies with
    "unknown CPU". I believe it will happen with any Slot 1 440BX boards
    that supports model_6bx CPUs.
    
    I need to make the change below to make it work. abuild tested. Boot
    tested on P2B-LS and P3B-F.
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f1aa9841a948edf3615bcab72ce1e9d635eae412
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 12 21:37:03 2010 +0000

    Move translate_spd_to_i82810[] from .h to .c file (trivial).
    
    This is in preparation of further i810 fixes and switching it to CAR.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74d1a6e8a166cd477f667a6fcb1e96b8a0cbdac1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 12 17:34:08 2010 +0000

    We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.
    
    As both ioapic.h and acpi.h define a macro named "NMI", rename one
    of them (NMI -> NMIType in acpi.h).
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4ffde94c4ec51cdb24103ec13653e6f40513e1bb
Author: Warren Turkal <wt@penguintechs.org>
Date:   Tue Oct 12 06:13:40 2010 +0000

    Reduce duplicate definition in CAR code.
    
    Macros for the register addresses for the MTRR MSRs are already defined
    in include/cpu/x86/car.h. This patch uses those macros instead of
    creating a second instance of that same data.
    
    I also added a few macros to the amd mtrr.h to make the MSR naming more
    consistent.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c814d2e9ee203a2e4f8c27cb023be8c26380e7b
Author: Warren Turkal <wt@penguintechs.org>
Date:   Tue Oct 12 06:12:00 2010 +0000

    Build bootblock.S instead of bootblock.c.
    
    The file is actually just including a bunch of assembly. The build rule
    for bootblock.c even states that the file will be "assembler-with-cpp."
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5b2fd1ea1568eaee821fe0e5250bd636b01d6024
Author: Sylvain Hitier <sylvain.hitier@gmail.com>
Date:   Mon Oct 11 23:22:24 2010 +0000

    Fix typo after r5925.
    
    BTW, embed the always-the-same string instead of referencing it through "%s".
    
    Do the same for i82371EB while we're at it.
    
    Signed-off-by: Sylvain Hitier <sylvain.hitier@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e62fc0d355d11c4081d9ef587bb4f75d345f2900
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 11 22:49:39 2010 +0000

    Build fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ea281f70077b6f8d69d3070447205b7afd6883a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 11 21:38:49 2010 +0000

    First round of ICH2/ICH2-M cleanups after split from i82801xx.
    
     - Drop all non-ICH2 "struct pci_driver" entries from all files.
    
     - Kconfig: Add missing USE_WATCHDOG_ON_BOOT.
    
     - Drop i82801bx_sata.c and i82801bx_usb_ehci.c, ICH2 doesn't have SATA/EHCI.
    
     - Simplify lots of code, getting rid of i82801xx remainders.
    
     - Use u8 et al (instead of uint8_t) in a few more places.
    
     - Use #defines from header files where possible.
    
     - Various other fixes and updates.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b42a62966527f18f3894af953b0757080424b00
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 11 19:36:13 2010 +0000

    Factor out a few commonly duplicated functions from northbridge.c.
    
    The following functions are moved to devices/device_util.c:
    
     - ram_resource()
    
     - tolm_test()
    
     - find_pci_tolm()
    
    There are only two tolm_test() / find_pci_tolm() which differ from the
    defaults, one of them can easily be eliminated in a follow-up patch,
    maybe even both, but for now keep it simple and only eliminate the majority.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa8612ee903db447c2f59e0f084e35577fa49db4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Oct 10 22:05:02 2010 +0000

    fix typo in minilzma.cc, found by Idwer.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5936 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4f98b63a72edc6a73105b76a115b9a29b749878
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Oct 10 21:15:53 2010 +0000

    don't include unused code, we only need the header.
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0a58a7b3edc9d1a20bf3aee0c747d5777b0c8696
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Oct 10 21:15:01 2010 +0000

    fix typos found by zbao in other files.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 470e1821c3fd37b92ab5200ad4d0d17c06efe0a6
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Oct 10 20:43:00 2010 +0000

    Same applies for SB600.
    
    Following patch enables UDMA on ALL IDE devices. The current code enables it only for primary master, which causes my DVD drive to fail under windows install
    and even after hard reset in linux (DMA seems lockup).
    
    The fix should not have any influence for Linux because the IDE driver will
    correctly reprogram this bit.
    
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e522164ae15fab2e96309bc439ff431c6910f021
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Oct 10 19:55:32 2010 +0000

    Following patch fixes the boot_switch_sata_ide logic. It can swap
    primary / secondary IDE channel with SATA (in IDE mode).
    
    The bug was that setup was done in wrong device.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14cc9271780b8348f5007b6247290c15367fb45c
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Oct 10 19:54:15 2010 +0000

    Following patch enables UDMA on ALL IDE devices. The current code enables it only for primary master, which causes my DVD drive to fail under windows install
    and even after hard reset in linux (DMA seems lockup).
    
    The fix should not have any influence for Linux because the IDE driver will
    correctly reprogram this bit.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2a5101aba49315b6c46aa3dc4c6c07633e453c06
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sun Oct 10 15:18:53 2010 +0000

    Trivial. Spelling check.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 115c5b982495f8495968e0ea4fd77f63df6e5d71
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 9 17:00:18 2010 +0000

    Remove various .c #includes from Intel 440BX/82371EB boards.
    
     - Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c
       into distinct compilation units, and don't #include the files anymore
       in romstage.c files.
    
     - Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and
       northbridge/intel/i440bx/debug.c.
    
     - Add various header files which are now needed.
    
     - Make functions that need to be visible non-static.
    
     - Drop a remaining "select ROMCC" from a 4440BX board.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Idwer Vollering <vidwer@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53b52f356abe8212f8b06b14c3237ca05b71d597
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sat Oct 9 07:18:50 2010 +0000

    Trivial. Spell checking.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1dcf66896dc90edee0dd8eda4d99618f1bc1dcb8
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sat Oct 9 02:31:10 2010 +0000

    Trivial. Spell checking.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 713ae2c0906e442bbe9af6d2e3850ca46e5e10b4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 8 20:09:21 2010 +0000

    Drop unused i82801ax_early_lpc.c and i82801bx_early_lpc.c.
    
    Nothing ever calls the functions in these files, and we already have
    i82801ax_watchdog.c and i82801bx_watchdog.c which basically do the same
    _and_ are hooked up correctly in the Makefile.inc and via the
    USE_WATCHDOG_ON_BOOT mechanism.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab06fb0caea2469fdf212a7655517a836a8dede6
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 8 19:24:56 2010 +0000

    Round 2 of i82801AX fixes to get it into a usable shape.
    
     - Remove left-overs from more generic code in i82801xx times, and fix
       register names as needed.
    
     - Simplify IDE init code (and save some ROM space too).
    
     - Simplify PIRQ code.
    
     - Use u8 et al instead of uint8_t everywhere.
    
     - Random other fixes.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b8db813809f3485ceaa77bf91595e64cc588d92
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 8 16:40:23 2010 +0000

    Intel 82801ax/82801bx: Fix and hook up i82801xx_smbus.c.
    
     - Fix incorrect #includes, add missing ones.
    
     - Drop unused do_smbus_write_block() and smbus_wait_until_blk_done().
    
     - Pass smbus_io_base to all functions as the other ICH implementations do.
    
     - Random other fixes which are required to make it build.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3af12fb8a930b8885b1c6c6b35d2aeff155b3c3
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Oct 8 05:08:47 2010 +0000

    Trivial. Spell checking.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d682fe8887b2ddd6c3c7e30c13b4e2f1c59779d
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Oct 8 03:35:12 2010 +0000

    Trivial. Fix the typo.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 554c052b48ac0b36503cb41b1c054a5ead7ae4b4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 7 23:42:17 2010 +0000

    Remove some duplicate #include files (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e5b7507882d4ee042d9c4d03e2e763bb49774b43
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Thu Oct 7 23:02:06 2010 +0000

    Remove duplicate line from pci_ids.h.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3bd1b1b25bb3056a6cc092b7a17a383e119a21f
Author: Scott Duplichan <scott@notabs.org>
Date:   Thu Oct 7 18:25:04 2010 +0000

    RS780 function ProgK8TempMmioBase is setting a reserved
    bit in the AMD processor 'MMIO Limit Address Register'.
    I suspect it is because of a typo where 0x80 was entered
    as 0x8. If 0x80 is used, then the strap configuration
    register accesses become non-posted, which is how the
    Shiner reference BIOS does it.
    
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6798b478027cb3fd44d52706ad69dee29bae19ba
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 7 16:24:28 2010 +0000

    Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK.
    
    Also:
    
    Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device
    on various PCI bus:device.function locations.
    Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
    
    Thus, instead of hardcoding PCI bus:device.function numbers such as
    PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which
    works the same on all boards.
    
    As an additional benefit this patch also gets rid of one .c file include
    in romstage.c.
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f2d20ec490a276a087acad0b3866c0f3ee844c4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 6 19:32:39 2010 +0000

    Convert all Intel 440BX boards to Cache-as-RAM (CAR).
    
     - Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig.
    
     - Add the following in src/cpu/intel/slot_1/Makefile.inc:
       cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
    
     - Remove "select ROMCC" from all 440BX board Kconfig files.
    
     - Drop all early_mtrr_init() calls, that's done by CAR code now.
    
    Various small fixes were needed to make it build:
    
     - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(),
       those were never called anyways.
    
     - Remove the "static" from the main() functions in romstage.c files.
    
     - Always call dump_spd_registers() from the 440BX debug.c, but use
       "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging
       is enabled in menuconfig.
    
     - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if
       commented out) from romstage.c's, as we've done for most other boards.
    
     - Add missing #includes or prototypes. Some of the prototypes will be
       removed later when we get rid of the #include'd .c files.
    
    Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5225520172a1d1e5c19a93c9178ecd7b72a13248
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 5 19:39:35 2010 +0000

    Remove duplicate line from pci_ids.h.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7a7b7903bf410b896adfbd505c1435b6e6da4fa
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Oct 5 19:38:04 2010 +0000

    Use %p instead of %x to print void *.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a5a776131aef5a861d3c27dd4e9a37457991dc98
Author: Eric W. Biederman <ebiederm@xmission.com>
Date:   Tue Oct 5 18:22:00 2010 +0000

    mkelfImage: set kernel_alignment so 2.6.31+ work
    
    The kernel initialization code as of boot protocol 2.10 is now reading the
    kernel_alignment field.  With the field left unset the kernel attempts to
    align things to 4GB which is unlikely to work, so change the alignment to
    the kernel's normal value of 16MB so newer kernels processed by mkelfImage
    will boot.
    
    Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f89d0a7a4f80b26082def1667b30a24b0b1218c
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 5 18:21:58 2010 +0000

    Add second CK804 for tyan/s2895 and sunw/ultra40.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abc0c7791e18dbd97949a49016f9ebedb823ed84
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Oct 5 17:59:12 2010 +0000

    attached patch moves a couple more config flags out of romstage:
    CK804_USE_NIC, CK804_USE_ACI, CK804_NUM.
    MCP55_USE_NIC, MCP55_USE_ACI, MCP55_NUM.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Pter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5692c5733633bfb8b23f1111de152eff0233b713
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Oct 5 13:40:31 2010 +0000

    - move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1
    - move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges
    - drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d0835953506263b0d9218b62176693315f2ef2f3
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Oct 5 09:07:10 2010 +0000

    Remove lib/ramtest.c-include from all CAR boards.
    Remove many more .c-includes from i945 based boards.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc0dc7f839f5ccc3361e186f6bbc4c9a48155c78
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 4 20:43:55 2010 +0000

    Add missing Intel Pentium II/III era CPU IDs.
    
    Add links to the respective Intel specification updates or manuals where
    the IDs are listed. Mention the possible core steppings of each CPU ID.
    
    There are duplicate IDs in model_6xx and model_68x for now, not sure if
    those should be eliminated, but there were already duplicates before this
    patch, so that's probably an extra issue to look into.
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36455aade46a1ca44aa1387e1785e72519f7b82d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 2 20:51:29 2010 +0000

    Add comments to make it clear why these two lines are written like that:
    
      movl    $REAL_XIP_ROM_BASE, %eax
      orl     $MTRR_TYPE_WRBACK, %eax
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae3f2b3706b3655627fdaee897d28ac4b5fe2659
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 2 20:36:26 2010 +0000

    Allow selecting the physical USB Debug Port on AMD SB700.
    
    The AMD SB700 allows changing the physical USB port to be used as
    USB Debug Port, implement support for this.
    
    Also, fix incorrect PCI device of the SB700 EHCI device. Actually, the
    SB700 has _two_ EHCI devices (D18:F2 and D19:F2), but for now we only use
    D18:F2. Our generic USBDEBUG code cannot handle multiple EHCI PCI devices
    currently, AFAICS.
    
    Hook up all SB700 boards to the CONFIG_USBDEBUG_DEFAULT_PORT facility.
    
    Untested, but should work.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa7efe9f40248f9041671ecdc03634f716841e21
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 2 20:33:56 2010 +0000

    AMD SB600 uses a hardcoded USB Debug Port number.
    
    It cannot be changed via software according to the datasheet, whereas
    this is indeed possible on AMD SB700. I tested using the SB700 mechanism
    on SB600 but it didn't work, so I suspect the datasheet is indeed correct.
    
    Thus, don't show the kconfig option for selecting the physical USB port
    on the AMD SB600 southbridge.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df67c674a0649fe8e95e88d0b56a4ce3c0890737
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Sat Oct 2 14:10:08 2010 +0000

    Don't define K8_4RANK_DIMM_SUPPORT, nothing uses it.
    
    All these boards define QRANK_DIMM_SUPPORT anyway,
    which is probably what was meant.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebe6d5820a497aea624ef9f20a4db93fe29af0ca
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Sat Oct 2 12:51:38 2010 +0000

    Fix spelling/typos in comments.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42f58277ef9325a88629ef6b55b784a61d4c4fb9
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 1 21:48:52 2010 +0000

    Redirect the output of iasl to a file to make the build quieter.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd8367006cf1a400384ff7076379bb53c6abea8a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 1 21:46:04 2010 +0000

    Factor out common CAR asm snippets.
    
    This makes the CAR implementations a lot more readable, shorter and
    easier to follow, and also reduces the amount of uselessly duplicated code.
    
    For example there are more than 12 open-coded "enable cache" instances
    spread all over the place (and 12 "disable cache" ones), multiple
    "enable mtrr", "save BIST", "restore BIST", etc. etc.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ba2b553b5ec01dced1ebadfa086c926f441f754
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 1 17:37:45 2010 +0000

    Cosmetics, whitespace and coding-style fixes for Intel CAR (trivial).
    
    This is abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d3f620299c784abbca4c3bd6b7ce5fe4cfb806c4
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 1 15:23:41 2010 +0000

    Fix make warnings:
    
    Makefile:261: warning: overriding commands for target `coreboot-builds/a-trend_atc-6220/lib/lzma.ramstage.o'
    Makefile:261: warning: ignoring old commands for target `coreboot-builds/a-trend_atc-6220/lib/lzma.ramstage.o'
    
    lzma.c is already included unconditionally in the same file.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7e982bbefc70acebd79c051e64fb25df6e8b668
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 1 15:16:20 2010 +0000

    Fix some breakage from 5890.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e82618d03719e1c3f012b6ac227aa4b34ae4950b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Oct 1 14:50:12 2010 +0000

    Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,
    rename it slightly, make it visible only on relevant northbridges,
    drop it entirely from via boards (as they seem to have picked it
    up from AMD code without using it themselves), and make it
    default to false for all boards.
    
    Some romstages used to set this to "true" (ie. "print debug output"),
    but I didn't follow up on it in Kconfig - if you need it to debug CAR,
    enable it yourself.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f11b81d18d36ecf732452a861d79ecd75f380adc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Oct 1 12:24:57 2010 +0000

    fix VIA C7 code.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c05bf411456a4166be9ad7d1775f5a3aa37ef9a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Oct 1 11:34:05 2010 +0000

    ICS951462_ADDRESS defined but _never_ used. Drop it.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 76d914391cb0a25af0962d0a5e615d551e44a777
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Oct 1 10:02:33 2010 +0000

    Make i945/raminit.c:fsbclk() return u16 rather than int
    
    This is needed for Gentoo gcc-4.1.2 to build the i945 code. A warning is
    thrown because the comparison in the last hunk is between u16 and -1 and
    can never be true.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f56ad2d2ef6fbf9564123c5a9b64f05d006b2d7
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Oct 1 09:58:44 2010 +0000

    Remove a couple of defines that seem to be the result of
    copy&paste, without actually being used.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e4bc0f648067606841e5b24ed0bfe4d921838aec
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Oct 1 09:13:18 2010 +0000

    Split NORTHBRIDGE_INTEL_I945 into more precise _I945GC and _I945GM
    
    Both chipsets use the src/northbridge/intel/i945 code but that code
    needs to know which chipset is actually used. Having separate
    NORTHBRIDGE_ options allows the I945GC/I945GM choice to be removed
    since code can test the NORTHBRIDGE_ option directly.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c2d0bfb4705b4fe3eb9332df00f01903f55d3521
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 1 09:11:15 2010 +0000

    Add missing parenthesis (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 77d6683edd1c0af74e4435cf432a558df3fe71eb
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Oct 1 08:02:45 2010 +0000

    Move several i945 config #defines from romstage.c to Kconfig.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66d1687b927a94991233d1ee87dc916fb6ae033f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 1 07:27:51 2010 +0000

    CAR simplifications, typos, readability improvements (trivial).
    
     - Use some more #defines instead of hard-coding values.
    
     - Merge multiple movl/orl or movl/andl lines into one where possible.
    
     - Add some TODOs in places which seem to have either an incorrect
       code or incorrect comment.
    
     - Fix typos: s/for/from/, s/BSC/BSP/, s/size/carsize/.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52000e1688e3b3f0c4cd62c4faa102737055d5e1
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Oct 1 06:27:35 2010 +0000

    Trivial. Re-indent the code.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4292684e1aa74b06e6797014f6eaf4ee5d879fc1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 30 23:15:36 2010 +0000

    Various cosmetic and coding style fixes in CAR code (trivial).
    
    Also, whitespace fixes, consistency fixes, and drop some of the less
    useful comments.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d36d6df7dafea5a6f9dec80f4a3998470d440a2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 30 21:22:40 2010 +0000

    Use existing, readable MTRR #defines instead of hardcoding numbers.
    
    Replace $0x200 with $MTRRphysBase_MSR(0) etc. Also, move some #ifdef stuff
    a little bit around (should not affect any functionality) to make the
    Intel/AMD/VIA CAR implementations more similar and easier to compare.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8463dd9db0dc2ce02423775d0eb62e28aa01e9f9
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Sep 30 16:55:02 2010 +0000

    Rename build system variables to be more intuitive, and
    at the same time let the user specify sources instead
    of object files:
    - objs becomes ramstage-srcs
    - initobjs becomes romstage-srcs
    - driver becomes driver-srcs
    - smmobj becomes smm-srcs
    
    The user servicable parts are named accordingly:
    ramstage-y, romstage-y, driver-y, smm-y
    
    Also, the object file names are properly renamed now, using
    .ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently.
    
    Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't
    easily fit in the build system and aren't useful anyway.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coreystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4d0a456d349002642c1c7e508f2729f1497ab96
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Sep 30 07:56:12 2010 +0000

    fix Kontron KT690 and clean up socket S1G1 boards accordingly.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 011d0d86b0269ab1f5c07db9ecdf27676e1073c9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Sep 30 07:45:58 2010 +0000

    drop unneeded earlymtrr.c include
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98a8c0ca7fc5206a07d193c1bc2813b2beb86943
Author: Warren Turkal <wt@penguintechs.org>
Date:   Thu Sep 30 03:35:00 2010 +0000

    Move CAR settings to board config for socket 940 boards.
    
    For the a number of the socket 940 based machines, I collapsed their CAR
    configurations into the socket config.
    
    However, I have kept a number of overrides in place for the following
    machines:
    * broadcom/blast
    * ibm/e32{5,6}
    * newisys/khepri
    * sunw/ultra40
    * tyan/s488{0,2}
    
    These machines used different setting than the defaults for socket 940
    systems.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a59a44e17fa728cddd33b08b78db365f743df44
Author: Warren Turkal <wt@penguintechs.org>
Date:   Thu Sep 30 03:13:21 2010 +0000

    Move VIA C7 board CAR config to VIA C7 instead of boards.
    
    This change is somewhat dangerous as it enables CAR for some boards that
    it was not enabled for before.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit afbf072f35a25143540c7e5e1a084fac3a2ea8c2
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Sep 29 20:28:59 2010 +0000

    Don't run clean-abuild on distclean target. It breaks full abuild runs.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17cae3599fa91e4d2d0cf13155af80fdc73ba039
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 29 10:51:05 2010 +0000

    Forgot to 'svn add' src/cpu/x86/name (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aac8f661f5ab4f65fa25f25a7cfd3097cf924f09
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 29 09:54:16 2010 +0000

    Factor out fill_processor_name() and strcpy() functions.
    
    The fill_processor_name() function was duplicated in multiple
    model_*_init.c files, move it into a new src/cpu/x86/name
    directory.
    
    The strcpy() function was also duplicated multiple times, move it
    to <string.h> where we already have similar functions.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ff5b449ce259ab6633db88da9ed7417c25bf110
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Tue Sep 28 21:11:48 2010 +0000

    As $PWD is not exported by all shells, use make-builtin $(CURDIR)
    instead of $(PWD).
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f98ee72c35081f4cff5b145fa56ad8ff936c9e9
Author: Warren Turkal <wt@penguintechs.org>
Date:   Tue Sep 28 21:02:03 2010 +0000

    Fix small typo in root Makefile.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c9bc138ec00dedd56c5556873731beb4d104772
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Sep 28 17:48:24 2010 +0000

    Drop some unneeded "#if CONFIG_USBDEBUG" (trivial).
    
    We don't surround the <usbdebug.h> #include with those checks in other
    places either. Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24a5213a3930ce676f56b47b4e55a8e2a8c24844
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Sep 28 16:16:58 2010 +0000

    Remove redundant HW_MEM_HOLE_SIZEK and HW_MEM_HOLE_SIZE_AUTO_INC settings.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b1a3c334cbb71f44c03f9d72cb33715856c563d
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Sep 28 04:43:16 2010 +0000

    Trivial. re-Indent the code.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3bd792947b71b2398163de03151ad195ccc58e70
Author: Warren Turkal <wt@penguintechs.org>
Date:   Mon Sep 27 21:28:21 2010 +0000

    I missed these boards in a previous commit.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c0bde289c2173eec0e06b657290a8dab151e65a9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Sep 27 21:26:46 2010 +0000

    Good bye, OLPC...
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e0afe735a0fa0564a9ab082593c60f56c291493a
Author: Warren Turkal <wt@penguintechs.org>
Date:   Mon Sep 27 21:18:26 2010 +0000

    All these boards already had the CACHE_AS_RAM option in their individual
    configs. I just moved it the the CPU that they all use.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 768d8ea09830a02fe815b8b60825430a3ec6a10a
Author: Warren Turkal <wt@penguintechs.org>
Date:   Mon Sep 27 21:15:56 2010 +0000

    Move CAR config from mainboard to CPU config for AMD GX2 boards.
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e8f204277ac6af885a9e45ec569f1bcff89ebbf
Author: Warren Turkal <wt@penguintechs.org>
Date:   Mon Sep 27 21:14:19 2010 +0000

    The commandline parsing for abuild doing a couple of buggy things:
    * Long options of the form --opt=arg were not having the arg stripped
      off into a another argument in the output. As a result, all long
      options with args had to be written like "--opt arg" on the command
      line to be recognized.
    * The --remove option was shifting too many times.
    
    As a bonus, I also added some logic to make "make distclean" cleanup
    the default abuild build dir.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7571c0b566e6915b7724dd9f3a2493d4ebe5653e
Author: Warren Turkal <wt@penguintechs.org>
Date:   Mon Sep 27 21:11:54 2010 +0000

    This patch moves one of the CAR configs to the socket from the single
    mainboard that uses it.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7cdf1eca924d6eab6eb51982fc5d0769c8f1e58f
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Mon Sep 27 21:08:40 2010 +0000

    Obviously missing brackets.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 49a7ac7ee5a19a3390955a0b4bbe1465a1136985
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Sep 27 21:00:34 2010 +0000

    drop some dead code from model_fxx_init.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f7a5c4544876806913068d1b5e7c6afc75eca80
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Sep 27 20:51:33 2010 +0000

    oops. always run abuild on a clean tree with no other patches applied.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c679ab54257e5a2d4e17d0f7fff964ac374f4b13
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Sep 27 18:57:07 2010 +0000

    RAMBASE = 0x4000 is no longer needed. Drop it.
    Now we only need to clean out the FAM10 stack mess and we're good to go with a
    uniform RAMBASE.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e278cafb5799036652a84925b86f9ef83cccc3d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Sep 27 18:55:00 2010 +0000

    drop excessive blank line
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2a8ad41e7b3fd0aba353312f3580db079c8988d9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Sep 27 18:49:46 2010 +0000

    Add 2 missing license headers based on svn logs and remove an unneeded #include
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2dd1ded19736b322e410eee05375446af013feb5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Sep 27 18:48:15 2010 +0000

    minor include cleanups
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ac4c26177713cf2b1ada8c8d377929aedd109e4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Sep 27 18:03:18 2010 +0000

    Add a kconfig option to allow the user to select a specific physical
    USB port for use as Debug Port (on chipsets which support that).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5211a7023e90580505acc4eda855206540f588c7
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Sep 27 17:53:17 2010 +0000

    Add a few missing license headers based on svn logs, and also add a
    few more code comments to src/cpu/x86/*.inc files.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da28cd85428f8469d8de8c083b7fe950941bbc08
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Sep 27 11:11:09 2010 +0000

    drop double include (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86d1a50796dc3021777bfcf00cddbeff49187a01
Author: Jonathan Kollasch <jakllsch@kollasch.net>
Date:   Sun Sep 26 16:01:08 2010 +0000

    Duplicate the MCP55 EHCI Debug Port enable code for use with CK804.
    
    Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 024d248e986d16efe86e25294259ce531c10b080
Author: Warren Turkal <wt@penguintechs.org>
Date:   Sun Sep 26 15:23:28 2010 +0000

    i82801bx defines the hard reset function, so move the "select" statement to
    that component rather than the mainboard.
    
    The intel/d810e2cb is the only board using the i82801bx southbridge.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09f51827d5a3e8b45d222bdcad83feebc8a4e9c4
Author: Warren Turkal <wt@penguintechs.org>
Date:   Sun Sep 26 15:20:56 2010 +0000

    Remove hard reset config from some mainboard configs
    
    Most of the mainboards with i82801gx SBs seem to use the
    HAVE_HARD_RESET, which is already selected in the i82801gx SB config.
    Removing it from some of those boards should be a functional no-op.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef077f2394c11c924644b4697e772eb8cf0e7c73
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Sep 26 15:19:44 2010 +0000

    drop some more unneeded ../../..
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5854 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6924e820fd7e1b461081de0ac9f820129769e79
Author: Warren Turkal <wt@penguintechs.org>
Date:   Sun Sep 26 15:18:21 2010 +0000

    Normalize the config option for the Intel Atom CPU.
    
    All Intel CPU models appear to be identified with the form
    INTEL_CPU_MODEL_xxxxx. I haved changed the Atom to fit this normal form.
    
    A side effect is that the CPU doesn't need to be listed on the boards
    that support it since the socket identifies the CPUs it supports.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 64b26009a1303dab9da4d118c19c22f3992830be
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Sep 26 15:15:48 2010 +0000

    the utility is called dumpmmcr, not dump_mmcr
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48323b5873fe13326ff297fd07c6053e7d006bd5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Sep 26 15:04:46 2010 +0000

    dumpmmcr utility is available under util and shares most of the code.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e079ce31c9076a70cf4b36636fa54b838839136b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Sep 26 15:04:14 2010 +0000

    update license header for dumpmmcr utility according to svn history.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 02260bcdee8ce5b663f9420394c62516b6fec6de
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Sep 26 10:34:36 2010 +0000

    Fix the build, CONFIG_USBDEBUG must always be defined (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 65e60344adb6f4a121f6f80514e943da183ab168
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Sep 26 07:35:55 2010 +0000

    Only show the USB Debug Port kconfig option to the user if a mainboard
    is selected that uses a chipset which actually has that functionality _and_
    we have code to initialize the Debug Port in coreboot (for that chipset).
    
    Also, remove the duplicate list of PCI IDs and just link to the wiki page at:
    
      http://www.coreboot.org/EHCI_Debug_Port
    
    The list is now less useful in the kconfig help as this option will only
    appear for those boards where it's actually supported.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc3aa7abff4246bdbf5a6a397e758e4aa918a285
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 25 23:47:15 2010 +0000

    Various Debug Port southbridge implementation fixes / cosmetics.
    
     - Use PCI_COMMAND and PCI_COMMAND_MEMORY from pci_def.h instead of
       hardcoding their values.
    
     - SB600/SB700: Drop useless/unused SB600_DEVN_BASE and SB700_DEVN_BASE.
    
     - ICH7: Drop unused EHCI_CONFIG_FLAG and EHCI_PORTSC.
    
     - s/uint32_t/u32/.
    
     - Cosmetics, whitespace, coding style fixes and added code comments.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86224f634a74bd38823c620beb647276c9c8d95c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Sep 25 17:24:10 2010 +0000

    Mark read-only data as read-only, so the global vars test doesn't fail on it.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7f43dc1060adfaf82b7b58be9a26dc714d686f5a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Sep 25 17:01:13 2010 +0000

    Add an EHCI driver to libpayload's USB stack.
    Interrupt transfer support is missing (ie. no keyboard),
    bulk and control transfers work (ie. mass storage).
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5df4168db81d6a113922af66034c6e32f85adb08
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 25 16:17:20 2010 +0000

    Drop some useless "../../../" in #includes (trivial).
    
    Build-tested using abuild.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f14c9194ff6a0036f2ebec492670dd23a55493d2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 25 14:58:28 2010 +0000

    Various CONFIG_DEBUG_RAM_SETUP related fixes (trivial).
    
    Some boards still used the old DEBUG_RAM_SETUP (without _CONFIG prefix).
    
    Also, consistently use "#if CONFIG_DEBUG_RAM_SETUP" (not #ifdef) as we do
    elsewhere.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 370d979a93b1a63d1f8afc1ec2eb7cf54947ce35
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 25 14:23:31 2010 +0000

    Various USB Debug Port fixes (trivial).
    
     - Drop unused DBGP_DEFAULT #defines on boards with chipsets where no
       USB Debug Port support is implemented anyway (at the moment, at least):
    
        - hp/dl145_g3
        - hp/dl165_g6_fam10
    
     - ICH7: Move unrelated code out of set_debug_port(). All ICH southbridges
       with Debug Port hardcode the physical USB port used as Debug Port to 1.
       In other words, this port is not user-configurable (as seems to be
       the case on NVIDIA MCP55). For now we keep the 'port' parameter in order
       to not change the API, this might be fixed differently later.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bcabf2fa749f0690da982aaba52d9045f231c119
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Sep 25 14:15:41 2010 +0000

    Make globals in romstage break the build, so we don't have to
    wonder why variables in .data or .bss (both somewhere in ROM space)
    are wrong.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b124dcf93564732100154305b8e49b2b72c6b5f6
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 25 12:37:33 2010 +0000

    Drop <cpu/amd/mtrr.h> #include from Intel CPUs.
    
    Three CAR implementations on Intel CPUs include <cpu/amd/mtrr.h>, which
    is obviously wrong, so drop the #includes. None of their #defines are used
    in the Intel code.
    
    Build-tested with two of the affected boards.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7fd931b11d6727f489f8ed76530b43a382ed3c60
Author: Myles Watson <mylesgw@gmail.com>
Date:   Sat Sep 25 10:42:55 2010 +0000

    Keep the mc146818rtc.h include close to the option table include where
    possible.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 10ec0fed8e3336d52ab35f8da91a2a9423d3e969
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Sep 25 10:40:47 2010 +0000

    - Fix race condition in option_table.h generation by moving the include
      statement to those files that actually need it. This significantly
      reduces the number of dependencies, so it's no longer extremely ugly to
      specify them manually (see the src/pc80/Makefile.inc portion)
    - Add double include guards around option_table.h defines
    - Also, drop the AMD DBM690T work around for the issue
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ff492b18550d6e24cdaffbb265f2fecc294486a3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 24 23:37:25 2010 +0000

    Make SB600/SB700 more similar for easier diffs (trivial).
    
    Also fixes random whitespace issues, typos, etc.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 977b985095098fc64b223faea32141680a13c7e3
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Sep 24 22:15:54 2010 +0000

    Fix CCACHE handling, and make use of ccache's BASEDIR feature
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20979584fe28e9e62a71aa92c5c5ad8074790de4
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Sep 24 18:42:56 2010 +0000

    Automatically fetch bus information for mptable from
    the device tree, instead of using hardcoded values.
    
    If this changes behaviour, this is either
    - a bug in mptable_write_buses(), or
    - a bug in the old mptable or device config, that is
      they were inconsistent.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0a6d1aebf12b786b4c5cbb85ce14cb89f3498958
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Sep 24 18:28:50 2010 +0000

    Undo stupid mistake in r5832
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b015d02a857b27a65a3ef52839361236645754d2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 24 18:18:20 2010 +0000

    Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.
    
    Without a (currently) dummy set_debug_port() function the build fails,
    this may or may not be fixed differently in the future.
    
    Manually build-tested on all SB600/SB700 boards, and tested on hardware on
    one SB600 board I own, works fine.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a6163e02b7fcbbeb0d3e88569a5df8bc3c7b072
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Sep 24 18:12:46 2010 +0000

    Fix hp/dl165_g6_fam10 build. Failed to take r5800 and
    another recent change into account.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9139e7b7c55d34ae3c5e8b941db037a92d2ace54
Author: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Date:   Fri Sep 24 17:35:32 2010 +0000

    Add support for HP DL165-G6 with Fam10 CPU.
    
    Original patch was
    Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
    
    Updates to accomodate changes in coreboot are
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 16db6c3486fba7292bade3233df96b4ab2ecc889
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 23 18:48:27 2010 +0000

    Whitespace/typo/cosmetic fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6b4f1cd0ad43d29fe925a6cc6951f205a8ead50
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Sep 23 18:29:40 2010 +0000

    Fix some wrong capitalizations, reformat comments, fix a typo.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 06694a89528329e0a1bff2b9adf83f0f30e1a77e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 23 18:16:46 2010 +0000

    USB Debug Port related license header fixes (trivial).
    
     - Add missing license headers, or missing (C) lines to various files.
       (most are from AMD / Yinghai Lu, based on svn logs)
    
     - src/include/ehci.h was taken from the Linux kernel. Updating it to
       the latest version from git HEAD while I'm at it (build-tested with
       one board). It also sports some new EHCI 1.1 addendum #defines which
       we may or may not need.
    
       This new file also already has a proper GPL header.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c3126936d0387df5308817f63f25f170e2c5cb0
Author: Marc Jones <marcj303@gmail.com>
Date:   Thu Sep 23 15:38:55 2010 +0000

    Generate and extract debug sysmbols for coreboot. *.debug files can be
    used for source level debug.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a34a0b1876948d34c8f7d49f224998a6dfc7755a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 22 23:42:32 2010 +0000

    Fix a compiler warning in src/lib/usbdebug.c (trivial).
    
    The 'delay' variable shadows the global 'delay()' function, yielding
    this compiler warning/error:
    
    src/pc80/../lib/usbdebug.c: In function `ehci_reset_port':
    src/pc80/../lib/usbdebug.c:281: error: declaration of `delay' shadows a global declaration
    src/lib/delay.c:9: error: shadowed declaration is here
    
    This fixes the issue by renaming the 'delay' variable to 'delay_ms'.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7df50a8b0ead14610134e57b05a81340febd8db8
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Wed Sep 22 22:46:47 2010 +0000

     Here is a proposed way how to handle the SATA PHY settings on SB700. It
     consits of weak function which always exists (with defaults) and a possibility to
     override this with normal function in main.c. This is the other way of
     doing that and not using the devictree.cb.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 138cdbb17b9ae8543a65a6b61ab6daac5c6ef7f7
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Sep 21 23:53:47 2010 +0000

    First round of i82801ax clean-ups (trivial).
    
    After we splitted up the old i82801xx driver which was supposed to support
    multiple generations of ICH* chipsets, some of the generified code
    is now obsolete in i82801ax which should only cover ICH/ICH0 and none of
    the later ICH* generations.
    
    Hence:
    
     - Drop "struct pci_driver" entries for chipsets other than ICH/ICH0.
    
     - Drop drivers for hardware that is not present on ICH/ICH0: NIC, SATA, EHCI.
    
     - Drop PIRQE-PIRQH #defines and code, not available on this chipset.
    
     - Simplify some parts of the code (more will follow).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8fa90ec274ae28d98188f576a06dcaeab9f180ce
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Sep 21 21:16:27 2010 +0000

    Cut the crap.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0c51ddd98b6355e4f070ff13766cd1e75b77037c
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Sep 21 02:51:31 2010 +0000

    Complete the code which was missing.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 951a0feb2d5b2c68c1a15c192333578c6769e99e
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Sep 21 01:24:55 2010 +0000

    Fix the typo. Field DisAutoRefresh is in DramTimngHi.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df35cdc198d9be8cb5a1c6a39c1adef92f5fd336
Author: Keith Hui <buurin@gmail.com>
Date:   Mon Sep 20 23:41:37 2010 +0000

    A number of cleanups for 440BX raminit code.
    
    Resolves a number of TODOs items within, and clarified a number of other TODOs.
    
    Change register_values[] from long to u8 (byte). For what we are doing
    this is sufficient and makes it only 1/4 the size.
    
    Remove a hard-coding of SDRAMC register that is redundant and now
    incorrect, now that SDRAMC is conditioned on SDRAMPWR_4DIMM Kconfig
    and set through register_values[].
    This fixes all boards with 3 DIMM slots (e.g. ASUS P2B, A-Trend ATC-6220).
    
    RPS registers are now set in runtime code; remove it from
    register_values[] table.
    
    Bring DUMPNORTH() back. The code it refers to is still there.
    
    Move #define of NB up so the DUMPNORTH() macro can use it.
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0865b4d9c06d584cfb43793f710d7dfa58e3275e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Sep 19 21:12:05 2010 +0000

    Make ASUS P3B-F RAM init actually work by enabling SPD access.
    
    On this board all reads from SPD return 0xff by default, there's a custom
    GPIO fiddling needed to enable access to the SPD SMBus offsets at
    0x50-0x53. While coreboot actually sort of booted sometimes before r5193,
    that was just sheer luck as the RAM init was hardcoded in certain ways.
    Since the proper, more heavily SPD-based RAM init the brokenness of the
    ASUS P3B-F RAM init was becoming visible.
    
    This patch uses GPIOs to enable access to the SPD SMBus offsets,
    and resets the GPIOs again after RAM init (this is needed to allow for
    lm-sensors to work, for example).
    
    Tested successfully on hardware.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Idwer Vollering <vidwer@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 78301d02b01d01302e6f9ce95db1e59c360a0ba9
Author: Scott Duplichan <scott@notabs.org>
Date:   Fri Sep 17 21:38:40 2010 +0000

    AMD Fam10 code breaks with gcc 4.5.0.
    Root cause: After function STOP_CAR_AND_CPU disables cache as
    ram, the cache as ram stack can no longer be used. Called
    functions must be inlined to avoid stack usage. Also, the
    compiler must keep local variables register based and not
    allocated them from the stack. With gcc 4.5.0, some functions
    declared as inline are not being inlined. This patch forces
    these functions to always be inlined by adding the qualifier
    __attribute__((always_inline)) to their declaration.
    
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 01d56d4276c800f4aa53acd657aed24676a52f4d
Author: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Date:   Fri Sep 17 00:13:52 2010 +0000

    Clear bit 35 of msr c001_102a in Fam10 rev C cores.
    
    
    Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
    Acked-by: Scott Duplichan <scott@notabs.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8985ef179be85eda9cc10b23f9c143a47e56a2f7
Author: Marc Jones <marc.jones@gmail.com>
Date:   Thu Sep 16 21:36:44 2010 +0000

    Add default libpayload build, xcompile, and lpgcc setup to tint.
    
    Signed-off-by: Marc Jones <marc.jones@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c5637d9263fc58154dfde28ed09b2cdcc2523cf
Author: Marc Jones <marcj303@gmail.com>
Date:   Thu Sep 16 21:04:54 2010 +0000

    Add more Fam10 CPUID strings from the AMD revision guide. Includes
    newer Phenom II.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b0c690c09137d85d9c9280ce082094089ee9032
Author: Scott Duplichan <scott@notabs.org>
Date:   Tue Sep 14 17:28:41 2010 +0000

    This patch corrects a coding error in the original implementation
    of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code
    sets msr c001_102a bit 3 when bit 35 was intended.
    
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f1d29c408e35d379c85a6c2671401fcc4964e34
Author: Marc Jones <marcj303@gmail.com>
Date:   Mon Sep 13 19:31:21 2010 +0000

    IEI Kino added to IEI mainboard Kconfig. I missed this in r5812
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 738347e7c3f9ba059cb56740703c9b513744aac6
Author: Marc Jones <marcj303@gmail.com>
Date:   Mon Sep 13 19:24:38 2010 +0000

    IEI Kino mainboard support based on Mahogany Fam10.
    svn copy amd/mahogany iei/kino-780am2-fam10; then apply the patch.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b28614cc5021a0f3b20d3b8df6ac0d7813c1196
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Sep 13 17:46:13 2010 +0000

    CONFIG_MMCONF_SUPPORT is always defined.  Fix build.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e7a5b76a748a27b033122b55356661b79839874c
Author: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Date:   Mon Sep 13 15:11:35 2010 +0000

    Move initialization of MMCONF BAR to cache_as_ram setup phase, in order
    to make sure MMCONF is set up before use.  Otherwise, PCI config
    accesses run before init_cpus() will be lost if MMCONF is enabled
    (unless explicitly done as port-based accesses).
    
    This obsoletes removal of RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78) in
    mcp55_early_setup, so reinsert.
    
    Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d09d1f7846d546f1790cd9db107014ffec92cc27
Author: Juhana Helovuo <juhe@iki.fi>
Date:   Mon Sep 13 14:51:26 2010 +0000

    Add support for Asus M4A785-M.
    
    Signed-off-by: Juhana Helovuo <juhe@iki.fi>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c029e6963eed378f80eeaebd5cbc7827c5d5c9f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Sep 13 14:50:20 2010 +0000

    Add reserved areas for fam10.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 687b3ba327a703e9951c1297fa49aefce0ea5655
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Sep 13 14:49:02 2010 +0000

    Port k8 UMA handling to fam10.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6b56e43b6d96678cf7adeb1878702d3e52573985
Author: Juhana Helovuo <juhe@iki.fi>
Date:   Mon Sep 13 14:47:22 2010 +0000

    Generate multiboot tables from coreboot tables.
    
    Signed-off-by: Juhana Helovuo <juhe@iki.fi>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50b78b66d3e8c08ff86b0b82bbfa35537d3de053
Author: Juhana Helovuo <juhe@iki.fi>
Date:   Mon Sep 13 14:43:02 2010 +0000

    Print an error and correct pci scan limits.  Skip sb700 ISA DMA init if needed.
    
    Signed-off-by: Juhana Helovuo <juhe@iki.fi>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb817beb67986df5b315f04f7c9c620a2d5eefde
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Sep 13 13:23:20 2010 +0000

    Fix a typo reported by Sylvain Hitier.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 25d1213e3fd596281f2d7a3bb3aa975a4bf66545
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Sep 13 13:14:48 2010 +0000

    Convert i945 boards to use reserved resources instead of directly adding
    coreboot table entries in every mainboard.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43882f1714a5fd415cdf3dab1dfd6328fb2f0a33
Author: Marc Jones <marcj303@gmail.com>
Date:   Fri Sep 10 22:13:34 2010 +0000

    Add F71859 SIO.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36224b479bff4002df22d3552ffb4e6c90ca1e30
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Fri Sep 10 21:51:34 2010 +0000

    Add support for LiPPERT Hurricane-LX (EPIC board with AMD Geode-LX,
    CS5536, ITE IT8712F).  Board support is based on the SpaceRunner-LX
    (with tiny bits from the RoadRunner-LX) even though the hardware really
    was the ancestor of our three other -LX boards and in fact among the
    earliest Geode-LX boards on the market.  (Might even have been the first
    Geode-LX EPIC?)
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ea2115ceae9d426f293b029f305e61a01346640
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Sep 10 18:33:24 2010 +0000

    Move memory type information out of some AMD sockets.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17daf9a941e1c5653a84ba651b21815404f2b4b5
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Sep 9 22:12:40 2010 +0000

    Adapt comment, too. (trivial)
    
    Noticed-by: Uwe Hermann
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c934d1d468fca0fd955e869324f5846426e1b32
Author: Scott Duplichan <scott@notabs.org>
Date:   Thu Sep 9 20:37:00 2010 +0000

    This patch avoids a timeout during PS/2 keyboard
    initialization. It can reduce KBC init time by up to 400 ms on
    real hardware, and by a minute or so on AMD simnow.
    
    
    Signed-off-by: Scott Duplichan <scott@notabs.org>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f8a51cded3338327059dc9e87e4e8a3519793f2
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 9 16:00:20 2010 +0000

    Make huge macros inline functions for readability.  Remove warnings.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6689ed7813b37c92bbe6058155d67c4757fef26
Author: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Date:   Thu Sep 9 14:54:07 2010 +0000

    Please find appended.  This patch gets rid of the %gs magic altogether,
    fixes a few alignment wrinkles and sets up and registers the MMCONF area
    for AMD Fam10h CPUs (where selected by mainboard configuration).  It
    removes a bit of code that proved troublesome in MMCONF setups from
    mcp55_early_setup_car.c, as per earlier discussion.
    
    Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e0a000cc12984700c87fea6b153fa4221a125e19
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 9 14:51:17 2010 +0000

    Add support for reserved regions to resources and coreboot tables.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6b247d3ef866704108d7f30a3195db0a72db2095
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Sep 9 14:44:51 2010 +0000

    Only try to beep when speaker support is compiled in.
    Trivial change.
    
    Reported-by: Aurelien Guillaume <aurelien@iwi.me>
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f53eaa39662b614763035031bd2586176c43c85c
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 9 14:42:58 2010 +0000

    My Jmicron SATA card writes the name of the hard drive to the screen.
    This redirects that output to the console and implements a basic
    keyboard stub.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e150e9a5717235878e491157721966f446d6c66b
Author: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Date:   Thu Sep 9 10:35:52 2010 +0000

    Also improve boot time on AMD for the DDR3 code path.
    Fix a typo, too.
    
    Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6556534bab10fdd485f3c803321751b6eb9626ce
Author: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Date:   Thu Sep 9 09:56:19 2010 +0000

    Apparently, it's not crucial to clear this at the exact moment we switch
    to using ram, so something like the appended is perhaps more
    appropriate.  Confirmed to work on hw.
    
    Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c35c8409db16cd88dd93266575766f8a1695a27
Author: Kevin O'Connor <kevin@koconnor.net>
Date:   Thu Sep 9 08:34:02 2010 +0000

    Add a DRIVERS_PS2_KEYBOARD option which controls the PS2 keyboard
    initialization.  Not all payloads require it and some keyboards take a
    long time to init.
    
    Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 080ed7c5d586b7f610af5a6ecd6fbf48bc802fe6
Author: Marc Jones <marcj303@gmail.com>
Date:   Wed Sep 8 21:30:07 2010 +0000

    Trivial - remove stray characters from a comment block.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3c9b01efb50c691bacc4a9acc7abf69d5640eae
Author: Kevin O'Connor <kevin@koconnor.net>
Date:   Wed Sep 8 11:00:25 2010 +0000

    Code must not access the smbus registers before the RTC power well is
    ready (PSON gating).  Some boards boot faster than this power well
    stabilization, and thus see bad data when accessing the smbus
    registers.
    
    Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4c0a1d6e6669736e101ada54b81d529f7c84cde
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Sep 8 10:58:02 2010 +0000

    Make timer2 the default choice for TSC initialization.
    For boards where timer2 is unusable, there's still the IO based
    initialization available using the Kconfig option TSC_CALIBRATE_WITH_IO
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Kevin O'Connor <kevin@koconnor.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24f83a76ae2608f7df0a11d80537fdc907f1e88c
Author: Kevin O'Connor <kevin@koconnor.net>
Date:   Wed Sep 8 10:53:44 2010 +0000

    It should not be necessary to read in the rom during CAR setup.
    Removing the code preloading reduces the boot time.
    
    Preload code is enabled when doing CARTEST (not exposed
    to Kconfig given that it's a pure debugging measure)
    
    Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e914b501d25fe5af769a3753a56f7b01fb08ab2c
Author: Liu Tao <liutao1980@gmail.com>
Date:   Wed Sep 8 10:27:13 2010 +0000

    Changes to str*cmp functions. Fixes a couple more corner cases.
    
    Signed-off-by: Liu Tao <liutao1980@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fe09fd1dacd76badd7a2adf8c8933d927f4bce93
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Sep 7 23:27:59 2010 +0000

    My Jmicron SATA card depends on the BIOS not clearing AL when setting AH.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c9bc01b0ead45ebde3479e2c3c0c150ce99625f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Sep 7 22:30:15 2010 +0000

    Make a Kconfig option for debugging output from realmode emulation.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c13738540483511a88b02a64195453cbaf3d67bc
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Tue Sep 7 17:33:17 2010 +0000

    Add support for LiPPERT Cool LiteRunner-LX (PC/104 board with AMD
    Geode-LX, CS5536, ITE IT8712F), based on very similar SpaceRunner-LX.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 625a0cb433c08a2dfe2a70f7ab2ce3d84bdfce1c
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Sep 7 09:18:08 2010 +0000

    Remove unused ide0_enable and sata0_enable entries from SB7xx
    and SB600.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3e4daf1345a6fbe55871076c71e3c212a3cf3565
Author: Kevin O'Connor <kevin@koconnor.net>
Date:   Tue Sep 7 07:53:26 2010 +0000

    2ms is enough time to accurately obtain the clock rate.
    
    Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34697d67c18780bf765ac9f66dcb1f14c7ef74c8
Author: Aurelien Guillaume <aurelien@iwi.me>
Date:   Tue Sep 7 07:43:10 2010 +0000

    Set up an arbitrary amount of system memory on Geode LX, so
    coreboot_ram can be unpacked to 1MB. The value is quickly
    replaced with the real value later, thus causing no harm.
    
    Move RAMBASE to the default of 1MB for the affected boards
    
    Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31b2e8f566c886386187d5580b5ca1569f36e9b1
Author: Kevin O'Connor <kevin@koconnor.net>
Date:   Mon Sep 6 20:20:47 2010 +0000

    Instead of requiring users to modify qemu to allow writes to
    0xc0000-0xfffff, have coreboot qemu support enable the memory range at
    startup.
    
    Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7a999ae65cc5825ac8e2fce34638a142b444ce3
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sun Sep 5 05:52:33 2010 +0000

    Trivial. Currently the max frequency is preset as 400Mhz. We need to set a
    platform specific value. Before that, we can set it manually if the boards
    need to run in a higher frequency, which has been tested on Tilapia.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 08c92e03bf46e40559a25062fc77258c0eff2efb
Author: Kerry She <Kerry.she@amd.com>
Date:   Sat Sep 4 06:13:02 2010 +0000

    AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.
    
    Signed-off-by: Kerry She <Kerry.she@amd.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9140530261213bcd1c0a1eb8e44b4b06a3a5877
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Fri Sep 3 15:16:36 2010 +0000

    Update RoadRunner and SpaceRunner config to get in sync with current
    standard BIOSes RRLX0013 and SRLX0013.  Specifically move SPI and PME
    I/Os to 0x1228 and 0x298 and switch SIO watchdog to ext. 48 MHz CLKIN.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e1ac83bb61707210500a4bbf59c9aa6095e36b6
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Fri Sep 3 14:54:50 2010 +0000

    The AMD CS5536's USB controllers are located at device 0F, functions 4
    and 5.  They're not found if only function 0 is checked.  So if a device
    exists at all, try all its functions.  usb_controller_initialize() will
    silently skip all device classes != 0C03.
    
    (changed to continue to use 32bit accesses -pg)
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3cf287dab0d71cc7bfa864609016c47f3310a9e3
Author: Warren Turkal <wt@penguintechs.org>
Date:   Fri Sep 3 09:36:37 2010 +0000

    Add support for dumping ACPI registers for i7
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3d3cedf8021f1053788babacd629fd9eb1c988f
Author: Warren Turkal <wt@penguintechs.org>
Date:   Fri Sep 3 09:33:50 2010 +0000

    Add support for dumping RCBA registers for i7
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5329195e60ef26ce19562514671582040b5d32de
Author: Warren Turkal <wt@penguintechs.org>
Date:   Fri Sep 3 09:32:17 2010 +0000

    Remove some errant spaces
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3235eea7289ab274d74052613b2cd55732565310
Author: Warren Turkal <wt@penguintechs.org>
Date:   Fri Sep 3 09:31:13 2010 +0000

    Add DMIBAR support for Intel X58 southbridge
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a9fc3309ecdb678e217395cb2940e648240dfa80
Author: Warren Turkal <wt@penguintechs.org>
Date:   Fri Sep 3 08:57:32 2010 +0000

    Add convenience rules for cscope to Makefile.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba3b0ebdf8dfc054d962ac291a538d41770c4419
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Sep 3 08:53:06 2010 +0000

    The current workaround for binutils on mingw (or any non texinfo system) failed.
    While we're at it, improve DESTDIR handling
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8377c2d4bfabf69f42f7af86cea85bbd207473ab
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 2 22:02:53 2010 +0000

    Fix compilation for mtarvon.  CAR initialization does early_mtrr_init,
    jarell/debug.c isn't ready for gcc, and skip_romstage() doesn't compile.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dfe8d766fb5a561fb8b27007f5802c255f20167b
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 2 20:30:31 2010 +0000

    Trivial warning fix for adl855pc.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7f072fe564e1ffb8f91ad6c2acb6855d3a6c1f8f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 2 18:36:29 2010 +0000

    Fix abuild to build all boards.  Revision 5754 changed the way vendors and
    boards were specified in Kconfig, and abuild depended on that.  Since that rev
    it has only built qemu.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e448eba75942df3eefbd877b37b63f82c4faf440
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 2 18:29:31 2010 +0000

    Revert 5762.  It silently broke a lot of boards because abuild was broken.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 70679a095a9f9dde910d5944688f80d2ee4db6b4
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Sep 1 21:03:03 2010 +0000

    Simplify last_dev_p so that it matches comments.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5763 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3fad5633b8b17dc15c56733188fd27aa02589d9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Sep 1 16:27:13 2010 +0000

    Fix race condition in option_table.h generation by moving the include statement
    to those files that actually need it. This significantly reduces the number of
    dependencies, so it's no longer extremely ugly to specify them manually (see
    the src/pc80/Makefile.inc portion)
    Also, drop the AMD DBM690T work around for the issue.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7f2b0e339a2a051d5e0269eaa8fbb84530b6058
Author: Warren Turkal <wt@penguintechs.org>
Date:   Wed Sep 1 03:40:57 2010 +0000

    Add support for dumping GPIOS on Intel ICH10R. This information comes from the Intel ICH10 Family Datasheet.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9ee31d881879ab1d95b4bfb485bd6586367649d
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Tue Aug 31 19:19:16 2010 +0000

    SMC_CONFIG is needed before the device tree is ready and some people
    would rather not have mainboard settings like sio_gp1x_config in the
    device tree anyway.  So found a nice united home for both in Kconfig,
    where users can change them without having to mess around in the C code.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3063d5dfdee3ccf674b863ca6d22a229210c04a7
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Tue Aug 31 19:02:45 2010 +0000

    Make ALIX.2D3 support 2D2 as well.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9fae99fc4efa0e88f9e601848735ae20a251a862
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Aug 31 06:10:54 2010 +0000

    Get Byte65/66 for register manufacture ID code. RegMan1Present will
    be used in write levelization training.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd61a819496200c135d02ed999b229fdd11f6832
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Aug 30 21:52:38 2010 +0000

    Make yabel work for non-zero bus numbers.  The link_num is not the bus number.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 704b59662d8bf17cac387109a186cc6f702f27f9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Aug 30 17:53:13 2010 +0000

    We call this cache as ram everywhere, so let's call it the same in Kconfig
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 849498d4471003ff959e0151828abfe9a7be4621
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Aug 30 16:52:48 2010 +0000

    Fix intel mtarvon compilation by switching it over to CAR.
    
    This should be unproblematic, as there are other boards with the same "socket"
    that work with CAR already. Tests are highly appreciated though!
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a684fcb0fe28a47d23b7cb3acbd2add47c6ac50
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Mon Aug 30 16:36:51 2010 +0000

    Restructured all vendors' Kconfig files to no longer source the boards'
    Kconfigs from within the choice/endchoice block.  This makes it possible to
    define user visible board specific options.  Moved all vendor names and PCI
    ids to the vendors' Kconfigs.  Now all options in each file depend on the same
    symbol, so replaced all "depends on"s with a single "if".  Sorted boards
    (sort -d), cleaned whitespace.
    
    This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is
    always "y" and never used.  It it simply needed to have something to attach
    the boards' "select" statements to.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 459b0d2ddd966823a40da06d6cc3c30d8cb8bdd2
Author: Andreas Schultz <aschultz@tpip.net>
Date:   Mon Aug 30 16:32:23 2010 +0000

    This file was missing from r5751.
    
    Signed-off-by: Andreas Schultz <aschultz@tpip.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4c94c05b7cc9732dd3c161af3a6eb08e4f2d8b48
Author: Andreas Schultz <aschultz@tpip.net>
Date:   Mon Aug 30 16:22:22 2010 +0000

    Support for Lanner EM-8510 Board
    
    Signed-off-by: Andreas Schultz <aschultz@tpip.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    ---
     src/mainboard/Kconfig                     |    8 ++
     src/mainboard/lanner/Kconfig              |    8 ++
     src/mainboard/lanner/em8510/Kconfig       |   38 +++++++++++
     src/mainboard/lanner/em8510/Makefile.inc  |   21 ++++++
     src/mainboard/lanner/em8510/chip.h        |   23 +++++++
     src/mainboard/lanner/em8510/cmos.layout   |   74 +++++++++++++++++++++
     src/mainboard/lanner/em8510/devicetree.cb |   60 +++++++++++++++++
     src/mainboard/lanner/em8510/irq_tables.c  |   56 ++++++++++++++++
     src/mainboard/lanner/em8510/mainboard.c   |   27 ++++++++
     src/mainboard/lanner/em8510/romstage.c    |  103 +++++++++++++++++++++++++++++
     10 files changed, 418 insertions(+), 0 deletions(-)
     create mode 100644 src/mainboard/lanner/Kconfig
     create mode 100644 src/mainboard/lanner/em8510/Kconfig
     create mode 100644 src/mainboard/lanner/em8510/Makefile.inc
     create mode 100644 src/mainboard/lanner/em8510/chip.h
     create mode 100644 src/mainboard/lanner/em8510/cmos.layout
     create mode 100644 src/mainboard/lanner/em8510/devicetree.cb
     create mode 100644 src/mainboard/lanner/em8510/irq_tables.c
     create mode 100644 src/mainboard/lanner/em8510/mainboard.c
     create mode 100644 src/mainboard/lanner/em8510/romstage.c
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b6b29dbbb9126f80b592f7856cd09882c231e745
Author: Andreas Schultz <aschultz@tpip.net>
Date:   Mon Aug 30 16:19:04 2010 +0000

    Rework i855GM/i855GME support
    Signed-off-by: Andreas Schultz <aschultz@tpip.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    ---
     src/northbridge/intel/i855/Kconfig       |   30 +
     src/northbridge/intel/i855/i855.h        |   76 +++
     src/northbridge/intel/i855/northbridge.c |   21 +
     src/northbridge/intel/i855/raminit.c     | 1036 +++++++++++++++++++++++++-----
     src/northbridge/intel/i855/raminit.h     |   14 +-
     5 files changed, 1002 insertions(+), 175 deletions(-)
     create mode 100644 src/northbridge/intel/i855/i855.h
    
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1bab1fb839c59594b8dd0e48d35c15353266d6ad
Author: Andreas Schultz <aschultz@tpip.net>
Date:   Mon Aug 30 16:16:01 2010 +0000

    mPGA479M Sockets can take Intel Mobile Celeron.
    The 1.2GHz model has CPUID F29. This adds them to the list of CPUs for that socket.
    
    Signed-off-by: Andreas Schultz <aschultz@tpip.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    This patch likely breaks the following two boards since it unconditionally
    activates CAR code for this socket:
    
     * digitallogic/adl855pc
     * intel/mtarvon
    
    stepan suggests moving those two boards over to CAR, too, so we don't have to
    worry.
    
    ---
     src/cpu/intel/socket_mPGA479M/Kconfig      |    1 +
     src/cpu/intel/socket_mPGA479M/Makefile.inc |    2 ++
     2 files changed, 3 insertions(+), 0 deletions(-)
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 819ee74888c7c482cfec037b28dc37bbc2fb1ef1
Author: Kerry She <Kerry.she@amd.com>
Date:   Mon Aug 30 09:40:41 2010 +0000

    Multi-DIMMS on AMD ddr2 MCT channel B fixed.
    
    Signed-off-by: Kerry She <Kerry.she@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99cfa1e6bdc7e89f571a52ed636704be894418d1
Author: Kerry She <Kerry.she@amd.com>
Date:   Mon Aug 30 07:31:31 2010 +0000

    Multi-DIMMS on AMD ddr3 MCT channel B works.
    
    Signed-off-by: Kerry She <Kerry.she@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 108d30ba8652b27a2c78a0d5db22a445e272f396
Author: Kerry She <Kerry.she@amd.com>
Date:   Mon Aug 30 07:24:13 2010 +0000

    Trivial syntax correction of AMD mct_ddr3 dir.
    
    Signed-off-by: Kerry She <Kerry.she@amd.com>
    Acked-by: Kerry She <Kerry.she@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7b98f57669ffe8453fa00067b322f82961d7b82
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 28 23:23:47 2010 +0000

    fix compilation of hello.elf example payload.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b3f8090f4e42a73434da3f6d7854762f855ee679
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Fri Aug 27 09:36:41 2010 +0000

    drop three unneeded config variables:
    - HAVE_HIGH_TABLES
    - HAVE_LOW_TABLES
    - FALLBACK_SIZE
    
    Jens Rottmann sent an almost identical patch at the same time, so
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 78265d5609d37b528cf8f605878a792299d11a47
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Aug 26 18:24:04 2010 +0000

    Remove unused mainboard_config definitions.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d11f2db1fad2bac07588ed6238d48d74f46c76b
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Thu Aug 26 12:46:02 2010 +0000

    CONFIG_DEBUG_RAM_SETUP and CONFIG_DEBUG_SMBUS are only available if the board /
    chipset support it.  But this involves a long list of 'depends', which you have
    to remember updating manually.  Converted this into HAVE_... properties, which
    will be inherited automatically if someone copies a chipset to create a new
    one.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d058ad1b4a5746190651e9feabfadb624c59a98d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 26 12:43:58 2010 +0000

    One of my boards needs this mini delay in order to survive ram initialization.
    Odd. The others don't.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e523a20cac0ef58e6d303c32255bf4ca3806e6b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 26 12:42:43 2010 +0000

    kontron 986lcd-m: Fix compilation if there is no oprom execution at all...
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc8613ecaf858419288f4cef784c562f3d8a5093
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 25 18:35:42 2010 +0000

    Fix i945 based boards
    
    - prevent GCC from inlining do_ram_command - it will break RAM initialization.
    - fix the PCIRST# mechanism in those boards that do it, it requires 200ms, not
      200us
    - move PCIRST# as early as possible (before ich7_enable_lpc)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f22ecc2c920b41f5c48d96030333d1874f67c8d
Author: Aurelien Guillaume <aurelien@iwi.me>
Date:   Tue Aug 24 12:58:17 2010 +0000

    * Adds support for PC Engines Alix.2D(1)3 board to Coreboot.
    * DRAM initialization done message is now printed in debug-mode only, rather than everytime.
    
    Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 83628902adacc8eece332c6968ff4e910d43c5b4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Aug 23 18:43:27 2010 +0000

    mark unused variables in x86emu as unused. gcc has a mechanism for this.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53a811eeb5b00d165cb7cc7956d7c46cee3d4a73
Author: Wang Qing Pei <wangqingpei@gmail.com>
Date:   Sun Aug 22 20:02:27 2010 +0000

    Fix up some copyrights
    
    Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3bff8b523fd830925bf1c6e2398e4caec960577c
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Aug 22 20:00:42 2010 +0000

    I've checked Revision Guide for AMD Family10h processors (#41322) rev
    3.74 June 2010 for errata 351 and it agrees with the comment on
    setting ForceFullT0= 000b but I believe the code didn't honor the
    comment.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa81b69bfdaeb88899851a15acab289519e6edd1
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Aug 22 19:59:27 2010 +0000

    RB_C3  should also apply the workaround for errata 354, according to
    Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a43b7d2bb06081b0f3dd55d4be0d671ccf401dd
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Aug 22 19:56:47 2010 +0000

    RB_C3 and HY-D0 should also apply the workaround for errata 344, according to
    Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
    
    My processor wasn't getting the workaround
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4793ef1f824a2143443c5e2fe63b44deaae7dba7
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Aug 22 19:54:26 2010 +0000

    documented workaround erratum 414, see
    Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
    
    with patch.erratum414 it stops here (next patches don't make it get further,
    but they're needed according to documentation, don't break anything for me and
    I still don't have a solution for booting, so I'm keeping them there in case
    they fix something.
    
    testx = 5a5a5a5a
    Copying data from cache to RAM -- switching to use RAM as stack... Done
    testx = 5a5a5a5a
    Disabling cache as ram now
    Clearing initial memory region: Done
    Loading stage image.
    Check CBFS header at fffffd2e
    magic is 4f524243
    Found CBFS header at fffffd2e
    Check fallback/romstage
    CBFS: follow chain: fff00000 + 38 + 15b41 + align -> fff15b80
    Check fallback/coreboot_ram
    Stage: loading fallback/coreboot_ram @ 0x200000 (1114112 bytes), entry @
    0x20000
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 213ab94ea4bd23f4b5f2b00a09a535925fe2c6a6
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Aug 22 19:51:34 2010 +0000

    documented workaround erratum 372, see
    Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
    
    with this one  it stops here or earlier (as soon as before the patch,
    sometimes):
    
    *** Yes, the copy/decompress is taking a while, FIXME!
    v_esp=000cbf48
    testx = 5a5a5a5a
    Copying data from cache to RAM -- switching to use RAM as stack... Done
    testx = 5a5a5a5a
    Disabling cache as ram now
    Clearing initial memory region:
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e9f0dfe63185222e403d81dd1b6bce27d81eb9a5
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Aug 22 19:49:46 2010 +0000

    Complete code for errata 343.  Revision Guide for AMD Family10h
    processors (#41322) rev 3.74 June 2010 says to set the register
    to 1 before CAR and to 0 after. We were setting it to 0 after CAR,
    but not to 1 before.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc6244a922ecf4cc58e1c7158cb211e7ef1ee7c1
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Aug 22 19:48:29 2010 +0000

    Include RB_C3 in erratum 346
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 752f1b4ee790ef4caa9cdaea0e8cb4f80673e6e8
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Sun Aug 22 19:45:57 2010 +0000

    Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc.
    
    While reviewing impact of this change it seems code for erratum 531 was not in
    sync with current docs. I have checked uses of AMD_FAM10_ALL, but I
    haven't looked up the docs for all of them, at first sight it seems ok
    to include all FAM10 revisions in this mask.
    
    Apply errata 531 only to revisions listed in  Revision Guide for AMD Family10h
    processors (#41322) rev 3.74 June 2010. Before it was applied also to
    DR-B0, DA-C3 or HY-D0 which are not affected according to current docs.
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 28e4af58019249d21b70f518636c4aa90a9abb7f
Author: Anders Juel Jensen <andersjjensen@gmail.com>
Date:   Sun Aug 22 19:41:47 2010 +0000

    Add suport for normal register dumping on ite8510E/TE/G
    
    Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d0ff918f891d4f1917a371f826d94a833b57f95
Author: Anders Juel Jensen <andersjjensen@gmail.com>
Date:   Sun Aug 22 19:40:58 2010 +0000

    Add another port to find ite8510 on.
    
    Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4fd7df9535eb2f7eeeba87ebd260a8094fe59ff5
Author: Anders Juel Jensen <andersjjensen@gmail.com>
Date:   Sun Aug 22 19:40:11 2010 +0000

    Add support for non LDN register/device naming.
    
    Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 280275dcb5348202f5e545a7fdb4e896eb417906
Author: Anders Juel Jensen <andersjjensen@gmail.com>
Date:   Sun Aug 22 19:39:04 2010 +0000

    The LDFLAGS = -lz is needed to compile on slackware.
    Clubbering CFLAGS is never a good idea.
    
    Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3613d05e24514d7e2b6db96f85076a13b0502932
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Aug 20 20:45:04 2010 +0000

    Remove a couple of warnings.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 37106a762a2158003c6267873fd6ebc1ec5d685e
Author: Oskar Enoksson <oskeno@foi.se>
Date:   Fri Aug 20 20:37:27 2010 +0000

    Add support for the HP DL145 G1, based on the Tyan s2881.
    
    Signed-off-by: Oskar Enoksson <oskeno@foi.se>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca1a76247920ae3953db12ec290cf702053e970a
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Wed Aug 18 21:23:27 2010 +0000

    libpayload: fix garbage on screen with Geode-LX VGA
    
    Clear initial garbage in VGA memory and fix scroll_up, which scrolled 1 scanline
    instead of 1 text line by mistake.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6c43959279866f0c360e8d75d0a25b3e530e9e5
Author: Wang Qing Pei <wangqingpei@gmail.com>
Date:   Wed Aug 18 01:55:11 2010 +0000

    The attached file add pa78vm5 dev3 detection function to avoid the building error.
    
    Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7d2773e121637b5b76d1437fac5a93e397a64bb
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Aug 17 21:03:17 2010 +0000

    Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and
    I removed the gpio asserts - I think those are not used here.
    
    The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better.
    
    The classic PCI slot works fine too. However it seems SATA has some issues.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da71ba528406cadea6e83b30dd3448cc53e482f4
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Tue Aug 17 16:32:42 2010 +0000

    Correct for size_t would be %zx, but coreboot's printf doesn't support this.
    Trying to keep it simple:  Two sizes are expected equal so use same %x for both.
    Cast to unsigned int to make sure it fits.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ede4c08a9eb5e68420dde42e9a0fec004076b3e
Author: Wang Qing Pei <wangqingpei@gmail.com>
Date:   Tue Aug 17 15:19:32 2010 +0000

    Commit (non-working!) Jetway PA78VM5 mainboard
    
    Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42e7c32cc5253c2c8c6149a57a4667ec5ebf8262
Author: Wang Qing Pei <wangqingpei@gmail.com>
Date:   Tue Aug 17 15:05:05 2010 +0000

    Support for Fintek F71863FG. This might need some work on the copyright
    notices. Getting it into the tree so people can get to it.
    
    Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit acc374964421cad55d47770b5f27c5bce05228f3
Author: Marc Bertens <mbertens@xs4all.nl>
Date:   Tue Aug 17 11:32:21 2010 +0000

    image parsing for getpir
    
    when adding for example build/coreboot_ram as parameter
    it looks in the file for the PIRQ table prints it to stdout
    and shows if the checksum is correct.
    
    getpir works as before without any commandline parameters.
    
    This is very handy for developing a PIRQ table.
    
    Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 931d6f378220fd6d1db30b79313b97bbdf5ec8ca
Author: Wang Qing Pei <wangqingpei@gmail.com>
Date:   Tue Aug 17 11:22:40 2010 +0000

    Another AMD 780/700 mainboard: Gigabyte MA78GM-US2H
    
    http://www.gigabyte.cn/products/product-page.aspx?pid=3118#ov
    the simple config is
    AM2+DDR2+SB700+RS780, the superIO is IT8718F
    
    The patch has been tested with SeaBIOS + SUSE11.2
    
    Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 543f767dbf86aa4625d22d3055f729c5fd3b45ac
Author: Wang Qing Pei <wangqingpei@gmail.com>
Date:   Tue Aug 17 11:11:09 2010 +0000

    Tilapila supports both dual slot and single slot. The difference should be
    detected by the existence of dev3. Some other RS780 mainboard has
    the same function. The patch added the function to make these boards work
    smoothly.
    
    Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f90125ab53af9957e4191b97c8e6e0f3da37f17
Author: Wang Qing Pei <wangqingpei@gmail.com>
Date:   Tue Aug 17 11:08:31 2010 +0000

    Add support for Gigabyte MA785GMT mainboard.
    
    Details of the hardware configuration can be found at
    http://www.gigabyte.com/products/product-page.aspx?pid=3478
    
    Brief configuration is:
      1. CPU:Support for AM3 processors: AMD PhenomTM II processor/ AMD Athlon™ II processor
      2. North Bridge: AMD 785G
      3. South Bridge: AMD SB710
      4: Super IO : ITE8718F
    
    The mainboard has two bios flashchip. Coreboot ROM should be flashed into the
    M_BIOS (which means main bios).
    
    Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 92fafbd0d345b441204c518cc5573cc32a224c50
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 17 10:54:36 2010 +0000

    fix nokia ip530 Kconfig, missed on last check-in
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59a1b7f7f1a847e20b58dbf426ba00b6b1fc8344
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 17 10:14:50 2010 +0000

    libpayload: Add function to fix CMOS checksum.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 835674b9298b19315ae1ed70c2fc9d82a7f3535b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 17 09:52:01 2010 +0000

    Whatever happened here,... The DEC Tulip is a network card, no bridge of any
    kind. Move it to drivers and make the necessary adaptions. Also drop empty
    drivers/generic/generic and start cleaning up Makefiles in drivers/
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f366ce05ef3eb95c6c9d84a97cde1a4026f22787
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Tue Aug 17 08:33:44 2010 +0000

    Add support for the Intel NM10 (a variant of ICH7) and ICH8 southbridges.
    Both are tested and appear to be working, however I'm not 100% clear
    on if the NM10 has any other PCI IDs.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e7b7ae23e688fb883003aed42f614bcfa977894e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 17 08:24:01 2010 +0000

    Add support for Fintek F81216D/DG/AD
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e480ca6779a1fdce8808471c00c368faf37d4e4
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Aug 17 07:46:50 2010 +0000

    Clarify comment a bit
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a6f000cbb8955e974e7932dbd0c7e4c5d4b650ff
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Tue Aug 17 07:14:44 2010 +0000

    Add support for the Nuvoton NCT5571D. This chip acts nothing like the other
    supported Nuvoton chip, but identical to a Winbond, and Nuvoton is a subsidary
    of Winbond, so for simplicity's sake I've added it to the Winbond file.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae7a4258c123b53e2a348f6a5913dc4e964fe8ca
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Aug 17 06:18:47 2010 +0000

    Look for actual framebuffer size instead of hardcoding UMA
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e660f041610e2030d85663735ebad247a1d534ae
Author: Xavi Drudis Ferran <xdrudis@tinet.cat>
Date:   Tue Aug 17 06:12:59 2010 +0000

    Fix warnings (that become errors) in AMDHT for certain configurations (unused functions)
    
    Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52a3c3b7f71bde9667b75bfb2d53823614f7807f
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Aug 17 02:14:53 2010 +0000

    Feature of lane reversal of AMD RS780 is tested.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e39251973bd854c297d5934e0c1e3f990f20b923
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Aug 16 20:00:49 2010 +0000

    White space changes for s2881 device tree.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7c1f6b84896465321e3051ed7b153f18328c3b12
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Aug 16 18:21:56 2010 +0000

    sconfig parser:
     - print erroneous string in error message
     - print line numbers starting from 1 instead of 0
     - exit with return code 1 on errors
     - check return values of fopen operations
     - only create output file if input file was parsed without errors
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 154931c66fcc70424a10f3c99f63e361538cd888
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Aug 16 18:04:13 2010 +0000

    Fix strcmp and strncmp. They failed in several important scenarios
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1457aad00b38b4745ba564b6cc803ff98c128ea2
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Aug 16 17:51:47 2010 +0000

    Add #define that states the libpci interface version we implement
    (flashrom needs it)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1bd3fb750de5de8ae832d902200e151002b1705a
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Aug 16 16:25:23 2010 +0000

    Call mainboard init functions.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d7c1fc3a4a5dbf0c9f784b76f878f05386425a0
Author: Wang Qing Pei <wangqingpei@gmail.com>
Date:   Sun Aug 15 11:37:41 2010 +0000

    Gigabyte dual bios mainboard will always reboot, caused by the superio.
    After lots of testing, the SuperIO LDN 7, register 0xEF is the key to the
    problem. This patch adds a function which stops dual bios mainboards from
    rebooting, when called.
    
    Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 30584912579d050c6bb3de3d55ca887e6ae094b5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 14 20:38:17 2010 +0000

    My forgotten CAR cleanup patch...
    
    - Drop lots of dead code from the various cache_as_ram.inc files.
    - Use some descriptive macros instead of magic numbers for MTRR MSRs
    - drop unused duplicate descriptors from romstage GDT
    - slightly reformatting code and comments
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b24d07c3605742095d603f703c7adef39dc09aa6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 14 17:45:54 2010 +0000

    My old mcp55 azalia fix from May 2010. Was never checked in.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ccbe0509189fe5f801c52745e04f0e8a2470aef
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 14 17:31:49 2010 +0000

    bootblock_prologue.c (not a .c file!) and i386/init/crt0_prologue.inc were
    pretty much 1:1 the same file (despite an include and a typo) so drop one
    instance of it. We only have one prologue.inc for the romstage code now.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a6f0e1291cd06eb1c226a74d3ee80fcd95079f49
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 14 17:27:27 2010 +0000

    clean up comment in entry32.inc
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 18719f0b071bf33a22e6055ed5992208c1538bc1
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Aug 13 15:42:09 2010 +0000

    Build 8151 for s2885.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6615ef3bfc3ff20643a31f01e40473e174460b46
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Aug 13 09:18:58 2010 +0000

    Add support for OHCI controllers and prelimiary support for xHCI (USB3) controllers.
    Improve scanning for USB controllers.
    
    Limitations:
    - OHCI doesn't support interrupt transfers yet (ie. no keyboards)
    - xHCI just does initialization and device attach/detach so far
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03e54de648db0c7059ff7732b8b74a44317ef1a9
Author: Donald Huang <donald.huang@ite.com.tw>
Date:   Tue Aug 10 23:34:51 2010 +0000

    Superiotool support for the IT8500 embedded controller.
    
    Signed-off-by: Donald Huang <donald.huang@ite.com.tw>
    Signed-off-by: Yung-chieh Lo <yjlou@google.com>
    Signed-off-by: David Hendricks <dhendrix@google.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ad6d55e38c51acc4191ea5578caebe3287f6521
Author: David Hendricks <dhendrix@google.com>
Date:   Mon Aug 9 23:13:13 2010 +0000

    Some chips do not require enter/exit sequences. This causes them to be
    detected and printed multiple times in probe_idregs_* functions where a
    simple series of enter --> probe/print --> exit calls are made.
    
    This patch adds a simple check after each set of those calls to make the
    functions quit after a chip is found.
    
    Signed-off-by: David Hendricks <dhendrix@google.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9bf7810dacc34e791431f5511b6ed6febda29940
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Aug 9 13:28:18 2010 +0000

    make sconfig parser regeneration menu selectable
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 35d346fe2d98b3ec5ed0451b87cc31be06177d68
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Aug 9 12:58:16 2010 +0000

    Fix build error introduced in r5868.
    
    aliased_name was a compatibility hack to match the output of the C rewrite
    with the python version's results. It seems that we carried these
    useless symbols with us for years, just without any impact good or bad.
    
    By declaring devices static and tightening the screws (-Werror), the
    compiler now knows that these declarations are useless - and stops.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stefan.reinauer@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df61dd28f635bf57a1dc81c75b09b069041ab2f3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Aug 9 12:02:00 2010 +0000

    non-root devices are not supposed to be accessed outside of static.c except by
    walking the tree.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29ee87338cb2fb01f73105c831b132fbe87e43cc
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Aug 5 14:41:29 2010 +0000

    Change default path and configuration for Coreinfo.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Cai Bai Yin <caibaiyin.pku@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23ffe8b6904187ecc4860f71794e995bd123704a
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Aug 5 06:12:16 2010 +0000

    The number of cores is got by reading the bit 15,13,12 of [0,24,3,e8].
    The bit 15 seems to be a new feature when CPU started to have more than 4
    cores.
    
    Zheng
    
    Yes, this was add for revD.
    
    Marc Jones
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 127e976ec287df4ceb16a3b176b58497e58e0d8d
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Aug 4 19:29:11 2010 +0000

    Remove warnings from USB debug console code.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c4f31b3b5f6c3b7ba0ece39cd7df6273ff70a7e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 3 15:42:29 2010 +0000

    Drop the USE_PRINTK_IN_CAR option. It's a bogus decision to make for any user /
    board porter: printk should always be available in CAR mode.
    
    Also drop CONFIG_USE_INIT, it's only been selected on one ASROCK board
    but it's not been used there. Very odd.
    
    There is one usage of CONFIG_USE_INIT which was always off in
    src/cpu/intel/car/cache_as_ram.inc and we have to figure out what to do with
    those few lines.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0362c6d6a7da2fb1ce23da544587bb1aa406e67e
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Aug 3 15:01:39 2010 +0000

    VGA code needs to be refactored before it can be compiled conditionally.
    
    Revert until someone with the boards refactors it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d7ff69a036c9878976f983a6f4de37575e87fc4
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Aug 2 15:14:13 2010 +0000

    Build VGA code conditionally to avoid errors when using SeaBIOS.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Kevin O'Connor <kevin@koconnor.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 25bf69a6c9eb4871bcff7d5dc3116f9d076ab545
Author: Mattias Mattsson <vitplister@gmail.com>
Date:   Mon Aug 2 02:34:20 2010 +0000

    Adds id for ITE IT8707F to superiotool.
    
    Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9ce895199653555c2e5610a824c9de43494e66d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Aug 1 17:22:17 2010 +0000

    make early_mtrr_init() invisible for cache as ram targets as it breaks them.
    Fix up converted mainboards that still used early_mtrr_init()
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f97654833adc12d9ebcceff633755e2dc9939158
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sun Aug 1 17:20:20 2010 +0000

    Clarify a comment on an old hack, remove the call to early_mtrr_init
    that causes CAR to hang, provide more debugging output wrt memory size,
    and correct the numbering on the ram init sequence.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc0f7a68df9c07518eb34ef4549a2f704ededcdd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Aug 1 15:41:14 2010 +0000

    - fix SMM code relocation race
    - make SMM relocation debugging Kconfig accessible
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d33dc40965c6f7f3dae585a330c2cd06b816c85
Author: Björn Busse <bj.rn@co-assembler.net>
Date:   Sun Aug 1 15:33:30 2010 +0000

    add i945GSE to inteltool
    
    Signed-off-by: Björn Busse <bj.rn@co-assembler.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43110f5403895b8a9ab5fc15781b86109432bd29
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sun Aug 1 02:33:42 2010 +0000

    Update my old, no longer active email addresses
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23d98c768f0c0d53a71f77dd5f0ee83f01d66e16
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Thu Jul 29 19:25:31 2010 +0000

    Add support for the Intel Atom D400/500- and N400-series integrated
    northbridge. Also add support for the very similar Q963/965 northbridge.
    Tested:
      D510: confirmed working, with MCHBAR enable code
      Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work
    
    Untested:
      D410/D525/N400: should be the same northbridge
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b3cf8ef0812fd21f438640543c7aa9d138ed69c
Author: Cai Bai Yin <caibaiyin.pku@gmail.com>
Date:   Thu Jul 29 00:08:21 2010 +0000

    Resolved the bug of filo+libpayload building. The bug is if libpayload is installed before filo load "make -C ../libpayload/Makefile DEST=**", it would not
    install correctly. Also, distclean removes .xcompile now.
    
    
    Signed-off-by: Cai Bai Yin <caibaiyin.pku@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bba0d76952754da0c38cf94cf4a6860cff3ce9ba
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Wed Jul 28 00:27:09 2010 +0000

    Let Geode GX2 use geode_post_code.h just like Geode LX
    
    Also clean up gx2def.h and geode_post_code.h a little.
    abuild tested and boot tested on a Wyse S50.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a4952a54fa5db941aa95bfd8fa7427e96c1bacf
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Tue Jul 27 00:30:42 2010 +0000

    Add src/cpu/amd/model_gx2/cache_as_ram.inc missing from r5669
    
    Part of converting GX2 to use CAR.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e474070bdd3410fef471a7a142453a883a9f7793
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Mon Jul 26 23:46:25 2010 +0000

    This patch converts the Geode GX2 boards to CAR.
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3fb1c2531573ca246221167156721e40c3ef47c
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Jul 26 21:45:11 2010 +0000

    Make include paths more consistent.  Fixes compilation errors for me.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e1822d9f2461b301c6f9efc6f5131849a68f9fc7
Author: David Hendricks <dhendrix@google.com>
Date:   Thu Jul 22 22:56:44 2010 +0000

    Superiotool support for Nuvoton WPCE775x/NPCE781x.
    
    Signed-off-by: David Hendricks <dhendrix@google.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4aa93ccd3302d7db0eef00f5963bc991f3f233ff
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Jul 16 20:02:09 2010 +0000

    Add support for the console over Ethernet (through PCI NE2000).
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Cristian Magherusan-Stanciu <cristi.magherusan@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7fc9e291d7581845461efbdd74b56a8e0360f1e0
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Jul 15 15:59:07 2010 +0000

    Trivial: Improve error reporting of sconfig slightly by reporting the line number.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 857a7784497e887f7881e635dec31e3d53837d60
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jul 9 18:52:17 2010 +0000

    become more standard with libpayload headers. PATH_MAX belongs in limits.h,
    tiny curses can use standard includes now.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f969a6ab087255fdb242f3ef010f67177391b40
Author: Cristi M <cristi.magherusan@gmail.com>
Date:   Fri Jul 9 18:06:23 2010 +0000

    Trivial -Werror fix.
    
    Signed-off-by: Cristi M <cristi.magherusan@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 187e9d06205de101a4627af4251d315ce48c3413
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Jul 9 14:24:23 2010 +0000

    Trivial fix to make CONFIG_BOOTBLOCK_NORMAL switch compile again.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c358b650657764149b6533d6342eb54e19c83813
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jul 8 17:20:07 2010 +0000

    Ugly temporary fix until we figure out how to deal with the race condition.
    
    Justification:
    - dbm690t isn't actively developed (no new warnings will be introduced)
    - having this board fail clutters the mailing list
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f57b514cb6e0598b295a3d8a4345dd42209e1e6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Jul 8 16:41:05 2010 +0000

    Fix all warnings in the tree
    
    (does not fix the cmos.layout race yet)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 817d7542f708215c4128b6cdc39ca7d7e1256b26
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Jul 8 00:37:23 2010 +0000

    get rid of even more fam10 and k8 warnings.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e33e827083abe332cf404793d33fa2152a95bab
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jul 7 21:59:06 2010 +0000

    fix some more warnings
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42da0e6da6edd2dfe7fd752719ec5d2c94d5e055
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jul 7 17:51:41 2010 +0000

    fix some warnings.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e32d3991d04e896bcb9fd8315bab68d54146e017
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Jul 7 15:09:09 2010 +0000

    Kill a few more warnings.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7bcaa920e8028b79e039137736ebfbd91e1afaa6
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Jul 6 21:40:11 2010 +0000

    Eliminate a couple of warnings from setup_resourcemap.c
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a58c2609003c49d31d36381af956f86b5c3d378f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Jul 6 21:37:39 2010 +0000

    Select HAVE_OPTION_TABLE for msi/ms9652_fam10.  It fixes the build and doesn't
    change the behavior, since it is disabled by default.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb50c7d922e91f0247b3705eccb2d2eec638c277
Author: Edwin Beasant <edwin_beasant@virtensys.com>
Date:   Tue Jul 6 21:05:04 2010 +0000

    Re-integrate "USE_OPTION_TABLE" code.
    
    Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8376831eafc1be1175529fd21e0d2fe40339d4eb
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Jul 6 20:36:36 2010 +0000

    A bug fix:
    Fix the ctrl_devport_conf_clear to clear the enable bit.
    
    A simplification:
    Dynamically enable ck804s that are found instead of relying on #defines.
    Removing an Opteron changes the number of ck804s that are present.
    
    Simple changes to make it easier to compare the factory BIOS with Coreboot when
    using SerialICE for boards with the Nvidia ck804 chipset:
    If the mask is zero, don't read the value, just write the new value over it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 106f7ffadf0a5a95b7f465607e9b9cac0a24647e
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Tue Jun 29 21:26:17 2010 +0000

    Add support to IT85xx series
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e59f769ef02599a6e88df7443780727dc64e3ca
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Tue Jun 29 21:13:20 2010 +0000

    Add support to extended EC series
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a82eebe1a60ed5e49fbfc14cbe006c320846f01
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jun 29 21:02:32 2010 +0000

    fix misnamed functions.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fde6a4c4d74f1f217a39cbc54749563db442462e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jun 28 10:40:38 2010 +0000

    Run doxygen -u on doxygen configuration files
    (make sure we can build images in parallel)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab272664ee24c2e497186b4ed3f94e5910e8eac9
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Jun 25 13:43:22 2010 +0000

    Add new function to create all mptable entries for buses by
    reading that information from the device tree.
    
    Use this function on kontron/986lcd-m
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43c970f56a1dbba72543e9e1cd007726ad31c626
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Jun 24 14:43:17 2010 +0000

    __i386__ and __powerpc__ are set by the compiler already.
    Not need to set them in lpgcc.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9f705b12195b7c1ff9814f76c78c76d4b8498b1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Jun 24 14:15:49 2010 +0000

    Incomplete implementation of libpci's (of pciutils) interface.
    
    No pciutils code was harmed in its production - this code was written by
    looking at flashrom's expectations, so there's no license pollution.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9bb0438535d29329f6a01a136caa2f2ad79fdceb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Jun 24 13:37:59 2010 +0000

    fix return value checks of cbfstool's writerom
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 980a69b8c20ad975553980ccb320bf25ff7c0b16
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Jun 24 11:16:10 2010 +0000

    Attached patch moves functions out of the huge libpayload.h into headers
    according to libc/posix traditions, to simplify porting applications to
    payloads.
    
    It also adds a couple of functions:
    strcasecmp, strncasecmp, strcat, strtol, strspn, strcspn, strtok_r,
    strtok, perror, exit, getpagesize
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 815c47f7b458f7342195ffe99e994e2757df96c1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Jun 24 11:14:51 2010 +0000

    Add __LIBPAYLOAD__ and __i386__/__powerpc__ symbols to lpgcc's build context.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ad5107e5e6cb6d79e6b3e228226ffd87b72f62f1
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Jun 22 20:36:52 2010 +0000

    Finish fixing Tyan s2881.  Simplify ADT7463 initialization code.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ccbcc56c642cc0bb9c50514ed8384f67bd36f0d9
Author: Cai Bai Yin <caibaiyin.pku@gmail.com>
Date:   Tue Jun 22 19:12:58 2010 +0000

    Fix libpayload xconfig script to find coreboot utils xgcc.
    
    Signed-off-by: Cai Bai Yin <caibaiyin.pku@gmail.com>
    Acked-By: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d0bac7edab1fb1f389f20e27bfc8cdec2b61fd4b
Author: Cai Bai Yin <caibaiyin.pku@gmail.com>
Date:   Tue Jun 22 17:24:11 2010 +0000

    Change the libpayload "make install" default destination to be the source directory. Libpayload is not a runtime library and has many different configurations for different payloads, so doesn't really belong in /opt.
    
    Signed-off-by: Cai Bai Yin <caibaiyin.pku@gmail.com>
    Acked-By: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 49cdb0c052f2712c9b8dd8295195f6c79b3bea28
Author: Joseph Smith <joe@settoplinux.org>
Date:   Mon Jun 21 23:27:15 2010 +0000

    This patch adds support for the Intel D810E2CB (i810e/ICH2) desktop board. Hurray, this is the first i810 board running CAR.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b94a79fa6a7a9fa2e4dae9f38fc5c67aeaee09c9
Author: Joseph Smith <joe@settoplinux.org>
Date:   Mon Jun 21 23:25:06 2010 +0000

    This patch adds support for the Intel D810E2CB (i810e/ICH2) desktop board. Hurray, this is the first i810 board running CAR.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 40bffc22cd6b83b186c023d473e6213a65c2d51d
Author: Joseph Smith <joe@settoplinux.org>
Date:   Mon Jun 21 19:40:09 2010 +0000

    Create new socket for FCPGA370 and PGA370 CPU's for CAR. Add CAR support for Coppermine FC-PGA CPU's (model_68x).
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 992ae486c7f4eddca9046be8bed250292b0fbd28
Author: Joseph Smith <joe@settoplinux.org>
Date:   Sun Jun 20 18:59:40 2010 +0000

    This patch implements GFXUMA on all supported i810 boards. Also some fix-ups to the i810 northbridge.c code.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bfca8efab37497dba0753f38d914a759b007be0e
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sat Jun 19 06:55:17 2010 +0000

    Trivial. Cleaning up about the blank line.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7eac4450b32f6961d5abd8dae32c5eefc1a07c11
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jun 17 16:16:56 2010 +0000

    Always enable parent resources before child resources.
    
    Always initialize parents before children.
    
    Move s2881 code into a driver.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e10757ed525cdd1a5263b9d79e284310c999c0f7
Author: Joseph Smith <joe@settoplinux.org>
Date:   Wed Jun 16 22:21:19 2010 +0000

    This patch adds inteltool support for i810E and ICH2.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cfaa081f98ef44aa45b98d450367d8742135eae6
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Jun 11 14:25:40 2010 +0000

    Follow up to the USB refactoring patch: Missed setting pid values correctly.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9fb55cb75ca1186ad66e83379c53f8d16e15f759
Author: Edwin Beasant <edwin_beasant@virtensys.com>
Date:   Thu Jun 10 16:19:02 2010 +0000

    Fix a missing include file that was breaking the Traverse Geos build.
    
    Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
    Acked-by: Edwin Beasant <edwin_beasant@virtensys.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f333ba09580c00a6f27e3ee0796431f5df936ecf
Author: Edwin Beasant <edwin_beasant@virtensys.com>
Date:   Thu Jun 10 15:24:57 2010 +0000

    This commit updates the Geode LX GLCP delay control setup from the v2 way to the v3 way.
    This resolves problems with terminated DRAM modules.
    Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
    Acked-by: Roland G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1965a237124cc8e988cf760eb7e9a61efb2adabb
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jun 10 04:06:52 2010 +0000

    Check for NULL before calling device_match()
    
    It matters for multifunction devices who don't have siblings.
    
    The error in the rumba device tree created that situation.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a60c37c9346b9f9ba9aa623d10c052c6df5a5f7
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jun 10 03:14:00 2010 +0000

    The devicetree was wrong, but I'm still surprised it broke.  This fixes the
    board, but doesn't fix the device tree parsing.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 894a34715f41f7c819a593dc3ff8e3033ffaa9fe
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Jun 9 22:41:35 2010 +0000

    Same conversion as with resources from static arrays to lists, except
    there is no free list.
    
    Converting resource arrays to lists reduced the size of each device
    struct from 1092 to 228 bytes.
    
    Converting link arrays to lists reduced the size of each device struct
    from 228 to 68 bytes.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6507b390467591928f16aab68f247321ad3f2262
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Jun 9 22:39:00 2010 +0000

    Make k8 & fam10 northbridge.c code more similar.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42e5f649ede7c931b25feb854b3f78dffc1e5d15
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jun 9 19:07:19 2010 +0000

    The interrupt controller lives at I/O 0x4d0/0x4d1.
    However on these platforms we were causing a resource conflict by
    letting the resource allocator start allocations at 0x400.
    Change the constraints to start at 0x1000 so we avoid allocating over
    LPT ports (0x778-0x77f), PCI (0xcf8-0xcff) and some other fixed
    resources that might live down there (smbus base, acpi base,...)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a06f950c27651d82e2e1b95fa2690a3cab70750b
Author: Anders Jenbo <anders@jenbo.dk>
Date:   Wed Jun 9 08:08:12 2010 +0000

    This patch adds the ECS P6IWP-Fe board to coreboot.
    
    Signed-off-by: Anders Jenbo <anders@jenbo.dk>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd8d7eed2d4ded65ebd3ecc0f9300e8eba822068
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Jun 8 05:57:05 2010 +0000

    Fix auto-mangled comments (trivial)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 356f848407c10106c1d02d754ff54cdaffa1d309
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Jun 7 20:15:54 2010 +0000

    Fix some of Peter's suggestions for the Nokia IP530.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84e8e453c820aee0964a8825e08632fcbbae31a4
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Jun 7 17:12:57 2010 +0000

    Remove the rest of cardbus_scan_bus.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03adcfdb191db5ad4d3f507c776851f9598108e8
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Jun 7 16:51:11 2010 +0000

    cardbus_scan_bridge is identical to pci_scan_bridge
    (since PCI_PRIMARY_BUS == PCI_CB_PRIMARY_BUS.)  Remove it.
    Fix a typo while there.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 81af48e4913af3fdd5cbe5f9a12954a5fa4c928f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Jun 7 15:39:04 2010 +0000

    This patch extends the reserved resources for the cs5536 to avoid the excluded
    range as detailed on p104 of the cs5536 Device Data Book.
    
    Extended to 0x1000.  Same change for cs5535.
    
    Signed-off by: Edwin Beasant edwin_beasant@virtensys.com
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7923c495015ecb271da6e48b28cf5c065fcdd4bc
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Jun 7 14:09:41 2010 +0000

    Make sure VSA is linked as ELF32 for i386 (instead of whatever the compiler considers native).
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d78691d49db4efb03c1466f9a02c590df1f5efc1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Jun 7 13:58:17 2010 +0000

    Avoid using the name "pid_t", which is used on unixoid systems.
    Move controller specific data structures into private headers,
    to avoid conflicts between controller drivers.
    Factor out the USB PID ids, which are only exposed on UHCI. It's
    of not much use on the other controllers.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aed992054f3af248e12ec88de4c047456fe9b104
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jun 7 08:29:36 2010 +0000

    replace outb -> port 0x80 with post_code() in some places.
    Especially most _smbus functions misuse port 0x80 writes for delays.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4f1a77cd238b106e84d15a4b62e1ffe169e6200
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jun 5 10:03:08 2010 +0000

    Fix two warnings:
    
    108 src/arch/i386/include/arch/acpi.h:402:5: warning: "CONFIG_HAVE_ACPI_SLIC" is not defined
      1 src/mainboard/getac/p470/mainboard.c:83: warning: assignment discards qualifiers from pointer target type
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1946284594199accc9fb5733c1fad32bd6e6745e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jun 5 09:52:37 2010 +0000

    tly cosmetical. don't use movw because we use mov in most places.
    Also, drop some dead code at the very end where some segment registers
    get set up and are immediately overwritten by pops.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0c47c4d02d55eb8b7c0f467dbf2971e7a1d870e0
Author: Edwin Beasant <edwin_beasant@virtensys.com>
Date:   Fri Jun 4 20:32:12 2010 +0000

    This patch fixes the option rom code that was buggy when it switched
    segment registers before restoring register values. This was breaking
    the Geode VSA, and probably would have hurt other option roms as well.
    
    Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29a6a19715eb3d33f8eef0a963f71250430bb707
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Jun 4 20:24:11 2010 +0000

    Kconfig value is hex, not int.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed4e0057c8eaddcf3219b53aaa4a8d8a97dbd5b2
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Jun 4 20:20:37 2010 +0000

    128KB is the default, and isn't large enough with the 30K payload for abuild.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ad8ab8e7b0d193e6ed8e9b2768cc3afd9ca7bc4
Author: Marc Bertens <mbertens@xs4all.nl>
Date:   Fri Jun 4 19:53:55 2010 +0000

    Fixes for Nokia IP530 and associated drivers.
    
    Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Marc Bertens <mbertens@xs4all.nl>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3df121e4f471e037a95db4a9349c3101dbf9f1b
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Jun 4 15:55:12 2010 +0000

    Enable PCI_OPTION_ROM_REALMODE when GEODE_VSA is selected.
    
    Using YABEL isn't supported for the VSA, so don't allow a choice.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c282a1876fe445ebee8f44aba3bc79c7d6e9453f
Author: Frank Vibrans <frank.vibrans@amd.com>
Date:   Fri Jun 4 07:49:53 2010 +0000

    This patch replaces the headers of the following files:
    
    src/cpu/amd/model_fxx/model_fxx_update_microcode.c
    src/northbridge/amd/amdk8/amdk8_acpi.c
    src/southbridge/amd/amd8132/amd8132_bridge.c
    
    Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    http://www.coreboot.org/pipermail/coreboot/2010-June/058668.html
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5d6aede981a02bdef353bea09bd16f3cea4a4be9
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Jun 3 07:51:09 2010 +0000

    The code was ported. Now it is what it should be.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f067015ea97f56012cf0c1e386bc98de5f72d2c
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Jun 2 21:13:44 2010 +0000

    Fix hard-coded log levels.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e9d4bcc737f12dbcf121be5c50b4ff756dedcf4a
Author: Marc Bertens <mbertens@xs4all.nl>
Date:   Tue Jun 1 19:28:45 2010 +0000

    Fix a format string to keep the compiler happy.
    
    Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 80e914ffd59ea011b1d4ba1c1a1a1421dc2c6ecc
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Jun 1 19:25:31 2010 +0000

    CONFIG_DEBUG is too generic.  Remove it and replace it with CONFIG_DEBUG_SMBUS
    and CONFIG_DEBUG_PIRQ.
    
    Fix a couple of typos.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94de72b919d2a6bdf8f89973b682a53225bf5fcb
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Jun 1 15:19:25 2010 +0000

    Check the value of ulzma and do not continue if there was an error.
    
    Print fewer characters for pointers to make the output more concise.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74cd569821f2bc4148e1fb6281c587323d14811e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jun 1 10:04:28 2010 +0000

    inteltool: basic poulsbo sch support.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b987f7bb3f69eabfb5eb515041bbcabb36d1ccf8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun May 30 13:44:32 2010 +0000

    don't generate C source code file but use objcopy to include the SMM blob.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e554de0988fb1fd3e02aca6b6f2fc10c8fdc7ee
Author: Bernhard M. Wiedemann <corebootbmw@lsmod.de>
Date:   Sun May 30 12:56:17 2010 +0000

    This patch adds support for mainboard iBASE:MB899
    
    based on Kontron 986LCD-M
    changed superIO chip to w83627ehg, dropping MIDI
    dropped second superIO at 4e
    changed superIO-addr from 2e to 4e
    adjusted irq_tables.c and devicetree.cb
    dropped setup of 3xGBit-Ethernet
    adjusted IRQ-map (using values from mainboard/intel/d945gclf)
    disabled parts about HD-audio (missing on that board)
    
    Signed-off-by: Bernhard M. Wiedemann <corebootbmw@lsmod.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c60c88679f692dee5e547e58b4124c8639d4f07
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun May 30 12:35:39 2010 +0000

    whitespace cleanup inteltool cpu.c
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da0b456ad087daa384d30498132e4e59fa311e14
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Sun May 30 12:33:12 2010 +0000

    Added support to ICH9 chipset family
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 32e6e411eaab6b745aca1f74f2d9b5b2df641915
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri May 28 16:21:21 2010 +0000

    Add Intel Atom microcode
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b2e2b99661bc15a8722ed30e02ab872a4b1c976
Author: Joseph Smith <joe@settoplinux.org>
Date:   Thu May 27 22:47:13 2010 +0000

    Fix MBI walker.
    
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c56e5ad7254ddf7ee9f1f016150de9e28c3ff57e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu May 27 15:41:15 2010 +0000

    fix warnings.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 89ef0a9f4114f88dfd4c8053152e3448d971bd92
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 26 17:08:13 2010 +0000

    Update Intel microcode include files from their web page.
    This still requires someone to adjust the #includes in the
    model_XXX_init.c files but with a script we're getting closer
    to automate the update of 3rd party files.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f71fca0a7f2963c38ea877b45d94b2d7dc241947
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 26 16:54:33 2010 +0000

    Use the microcode files as created by the new microcode update script. (Fixes some whitespace and gets in new time stamps).
    No new microcode files included.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a998eae425e19601ae4accaee447881db70f1986
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 26 12:55:14 2010 +0000

    Drop problematically licensed Intel microcode files
    and replace them by their counterparts from Intel's
    opensource microcode file.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c8f8a6cb91e6aa5d6785f8ad09aae40048980efd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 26 12:53:43 2010 +0000

    cosmetical changes on intel's microcode.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2305f748953867ddfdc0f449401148e97e78e506
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 25 23:06:42 2010 +0000

    Move CS5535 specific setup from GX2 driver to CS5535.
    
    To apply this patch you need to
    cp src/northbridge/amd/gx2/chipsetinit.c src/southbridge/amd/cs5535/
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e00a44b773ba16b72fa1ca69825407be0c98ad5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 25 17:09:05 2010 +0000

    also rename the config option.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 75a05dc0b91fb5748bb4f8b0eee9cee168c2cda1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 25 16:35:51 2010 +0000

    fix most usbdebug warnings and fix function names.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da3237376f8f4d35731ef9abfb7a7e5b94926198
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 25 16:17:45 2010 +0000

    Long ago we agreed on kicking the _direct appendix because everything in
    coreboot is direct. This patch does it.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 56394484e3b46d234ec504dc23114b9cf8c67778
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 25 16:02:28 2010 +0000

    Fix usbdebug compilation.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b01a8a5cd84af76e0b4ad7cc0ffc22e1e2f5146
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 25 16:00:08 2010 +0000

    cosmetics.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba818172cb33cdd72a2cafd32056d7e41dceca92
Author: Michael Marineau <mike@marineau.org>
Date:   Mon May 24 15:51:15 2010 +0000

    Fix VGA after switching to realmode_interrupt()
    
    Signed-off-by: Michael Marineau <mike@marineau.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f296e8456e83e062cdb3cbdf204bd28e249adde
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun May 23 11:08:37 2010 +0000

    consistently use decimal for the register offsets, and fix comment typos.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae3f4b572599ed1e2f149aee0d74e976948a5305
Author: Peter Stuge <peter@stuge.se>
Date:   Sun May 23 04:50:41 2010 +0000

    Fix bug from r5476 re CS5536 device search during GeodeLX PCI domain enable
    
    cs5536.c:chipsetinit() is called during northbridge pci_domain_enable()
    which happens before scan_bus() so the device tree does not have PCI
    vendor/device ids yet. Let's use dev_find_slot() for now. This works
    only as long as the CS5536 has PCI device id 0xf in all mainboards,
    and a better solution is needed in case that ever changes!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Nathan Williams <nathan@traverse.com.au>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 78c733c2b737d0bfba8e9c614ab50a9dd04c8cc8
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat May 22 15:07:15 2010 +0000

    Add tinybootblock support for broadcom/bcm5785.
    In the bootblock, 4MB of ROM are mapped instead of the
    default 1MB
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36de0424f2dd7376cf801a6f02d9842d59d9fac2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri May 21 20:40:38 2010 +0000

    Add "reasonable" values in ASL at places we overwrite from
    coreboot later. Current ASL compilers check for validity
    and complain about the dummy values.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c0c6372a9ecbaec6ee9504e47824d6481a0e977
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri May 21 20:36:47 2010 +0000

    Fix amdk8_util.asl and explain behaviour a bit.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d96ed433641c44404387f555458fab46b3832ee
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri May 21 17:15:55 2010 +0000

    Get rid of this warning:
    
    src/cpu/amd/model_10xxx/fidvid.c:758:
    	warning: 'fid_max' may be used uninitialized in this function
    
    Quoting Marc:
    
    It [fid_max] should be initialized to 0. The !nb_cof_vid_update would mean that
    the fidmax shouldn't change so the value isn't important, but 0 would be the
    safest if there is another hole in the logic and CPUs are not matched.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c25cc11ae32e10a7d0c9f04c29bfb7eca4d9c210
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri May 21 14:33:48 2010 +0000

    Use lists instead of arrays for resources in devices to reduce memory usage.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c5b87c8f895502b235e1619a23bd89dda955000e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu May 20 15:28:19 2010 +0000

    Move generation of mptable entries for ISA to generic code.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a169d2a46047e72e34977b74884b8d9d250f124
Author: Nathan Williams <nathan@traverse.com.au>
Date:   Thu May 20 07:35:17 2010 +0000

    Add support for the Traverse Technologies Geos mainboard.
    This board is similar to the AMD Norwich mainboard.
    
    Signed-off-by: Nathan Williams <nathan@traverse.com.au>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d77252e743424ee7f80ad0920003b46aa29727a
Author: Joe Korty <joe.Korty@ccur.com>
Date:   Wed May 19 18:41:15 2010 +0000

    Move the 'USE CMOS' Kconfig question.
    
    Move the 'USE CMOS' question from the top level to the
    General Setup section of Kconfig.
    
    Signed-off-by: Joe Korty <joe.Korty@ccur.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c3c0faabc220ef4fc921d9d1dbddb125198abab
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 19 18:39:23 2010 +0000

    cosmetic comment changes.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ace2dc3ac117ea1a353fc1fb9922c88cb91b0d0c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 19 10:01:37 2010 +0000

    The AMD Fam10 code breaks with coreboot 4.5.0.
    Potentially caused by reordering. Going back to 4.4.4 which is known working on
    Fam10 until gcc or the Fam10 code is fixed.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5b0280fb142d524a0762066e8b83f255410fc0d4
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed May 19 07:21:31 2010 +0000

    Fix path for mingw workaround. Trivial.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb33fbeb91bad7521a8262ada40d51405b22c429
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 18 16:24:07 2010 +0000

    get rid of some duplicate inclusion warnings.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f1ad890203748e8440101edbd72ab12ff44a9b8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon May 17 11:02:25 2010 +0000

    New buildgcc version.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 119c58910c355278021123226ae0fab0bc6d5835
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon May 17 10:21:10 2010 +0000

    drop old patches from crossgcc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b1180b42af83341426ad6d69ff1a6de8f178bb49
Author: Peter Stuge <peter@stuge.se>
Date:   Mon May 17 07:40:20 2010 +0000

    msrtool: Print hex values using only as many digits as the field needs
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87964864ae43bca67542f098b99a5ead49676019
Author: Peter Stuge <peter@stuge.se>
Date:   Mon May 17 07:29:47 2010 +0000

    msrtool: Remove some unneeded casts
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 417e66baa527c9bd843992e7ba163ebabb08b197
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun May 16 22:32:58 2010 +0000

    Sorry for this for second time. Now compile tested for both cases ;)
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fdddce3b926b5ad1d27f807feaeb318471a543ab
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun May 16 22:26:25 2010 +0000

    Sorry for this. I fixed that reverting the change for ROMCC.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit beba99045c7e7af21481d359384d06c77e636d53
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun May 16 21:51:34 2010 +0000

    Following patch reworks car_disable into C. Tested, works here. I compared
    also the GCC generated code and it looks all right. Please test on some
    multicore CPU.
    
    I added the "memory" clobber to read_cr0 / write_cr0 function as it is in Linux
    Kernel. Seems that if this is missing, GCC is too smart and messes the order
    of reads/writes to CR0 (not tested if really a problem here, but be safe for
    future users of this function  ;)
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4bb368cc73446240ea4c6d6aa6de4c5c867be3bf
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun May 16 15:34:02 2010 +0000

    Part of 5560 Dunno why I need extra delete after move.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9c2549333e1d688cf0b4ec82d8945dea77e0bbf
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun May 16 15:31:53 2010 +0000

    Following patch reprograms SIL3114 into PCI IDE native mode compatible class code allowing
    legacy software to recognize it as IDE and boot from it. I think
    this should be the default for two Tyan boards (k8s aka s2882 and s2881).
    
    Rename the directory to sil prefix to match the Linux kernel naming.
    (And I think it was a SiliconSystems wish to be named sil ;)
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7cfa7f97a1affb06f493a2335c99b213a91d335d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun May 16 14:24:41 2010 +0000

    Add support for the Getac P470
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09e0c49f3649745aca4fa28770ac07f877281979
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun May 16 14:22:43 2010 +0000

    v2 -> v4
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9e7a5d435980280407f58249181bd4f8d1d63d1b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun May 16 14:08:32 2010 +0000

    Add two new superios to coreboot:
    
    - SMSC FDC37n972
    - SMSC SIO10N268
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23f703464a45c4c5df53c40ef3152083f3c921fa
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun May 16 13:07:59 2010 +0000

    Add TI PCI 7412 support.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96d8fef5d2151878d96f6b445ec1678a529b4001
Author: Anders Jenbo <anders@jenbo.dk>
Date:   Fri May 14 21:29:08 2010 +0000

    ITE IT8671F: Add it8671f_48mhz_clkin().
    
    This fixes serial console on GIGABYTE GA-6BXE.
    
    Signed-off-by: Anders Jenbo <anders@jenbo.dk>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9d1c76f54c105a15f227183460ebe8d88cb719a7
Author: Anders Jenbo <anders@jenbo.dk>
Date:   Fri May 14 19:50:11 2010 +0000

    Add initial support for the GIGABYTE GA-6BXE.
    
    Signed-off-by: Anders Jenbo <anders@jenbo.dk>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f4b7f6cb1be61f4c36a85cbf3cb12822375a4f0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri May 14 19:11:44 2010 +0000

    clean up some prototypes
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bf264e940e3c97b3924a2361b7149f8533f400b4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri May 14 19:09:20 2010 +0000

    i945:
    * fix some potential compiler issues with newer gccs
    * add some more comments
    * make 32bit accesses for feature test functions
    * make some objects drivers because they contain a pci_driver struct.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cbac4981be1e485a2bab731338694d13cb768296
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri May 14 17:15:57 2010 +0000

    more acpica fixes... The tricky part is the stuff in the AMD mainboard directories.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86d72782c7e64f2c4def98fea15243ddf61ea6a7
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri May 14 16:44:45 2010 +0000

    Fix i945 ACPI for ASL Optimizing Compiler version 20100428.
    The values are overwritten on the fly but without the patch iasl will refuse to
    compile the code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4bdd6438f83e5c07cc34ecacbb0508b40b319a31
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri May 14 16:40:55 2010 +0000

    Various superiotool fixes.
    
      - IT8671F/IT8687R:
    
        - Fix typo: Parallel port register 0x60 value is 0x03 (not 0x01).
    
        - Fix typo: APC register 0xf6 is 0x00.
    
        - Drop register 0x07 (LDN 0 / none), that's not useful and not listed in
          any of the other Super I/Os either, it always contains the LDN number
          selected "last time", which is useless.
    
        - Fix indentation and other cosmetics.
    
      - Cosmetics, and consistency fixes in LDN names of various Super I/Os.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c928a295b3c23cc0fad0e40d9ddd9ffff3b0660a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri May 14 11:02:56 2010 +0000

    Remove another set of includes from Fam10 romstages:
    
    northbridge/amd/amdht/ht_wrapper.c
    northbridge/amd/amdfam10/raminit_amdmct.c
    cpu/amd/model_10xxx/fidvid.c
    pc80/mc146818rtc_early.c
    
    They are now included by the fam10 chipset code that requires them.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 930d32ba8741f059280feba79006da710411faeb
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Fri May 14 09:59:59 2010 +0000

    fix SeaBIOS loading on GX2.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa567a795e54cb71e9862736d0af591958ac9775
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri May 14 09:56:46 2010 +0000

    Fix warning. Hardware tested and didn't change behavior.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd6ad3447b10ffd1c0c823129aadc42038cb2b7e
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Fri May 14 09:48:05 2010 +0000

    license header fixes
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1e211327fb7e50e28b8943076db08596e6f27d2d
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Fri May 14 09:45:29 2010 +0000

    This patch cleanes up the Wyse S50 port and unifies the memmory regions
    with Geode LX , adds gpl2 headers plus some white space fixes.
    
    This is build and boot tested.(of course vsa loading is stil not fixed,it now
    runs forever with :"Oops, exception 13 while executing option
    rom")
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 841af5e01e3e6b017a4f0ab7800fdf14baffd93f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 11 15:39:20 2010 +0000

    Change real mode API to allow passing intXX number or entry point and
    some register values from C.
    
    This theoretically fixes non-vga option roms, but it also allows to use
    the same assembler code for option roms and vsm.
    It will also make using the bootsplash without yabel a lot easier.
    
    Factor out and improve BDA setup, do some rom segment setup for those
    option roms that need it.
    
    Don't call the coreboot exception handler if an exception occurs in real
    mode. It's only partly usable, but mainly the Kontron 986LCD-M (and other
    i945GM boards) choke on an exception #6 (invalid opcode). This particular
    issue is not introduced by the changes in this patch but has been around
    for quite a while at least.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48beb8276989f35f5510fbdc101cd2a222a3d21e
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon May 10 19:45:45 2010 +0000

    Make show_all_routes work for fam10.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b904d7bce9e258b2a460a0025a6a3828ec192cf0
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon May 10 19:38:59 2010 +0000

    High tables don't have to be on node 0 on K8.  Make it less restrictive.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ec3ead6dc238ae91d07f4154342a4388a306e74
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun May 9 21:44:52 2010 +0000

    Remove extra NULL #define in amdht code. The
    common one is enough. Trivial
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d5bb236aa6147ce24d9618f2d482e76eefc58c6
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun May 9 21:15:13 2010 +0000

    Move includes to where they are needed. This allows to simplify
    romstage.c files in mainboards.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bf9e5384d7c25be41d008d29c38b24155676acc0
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun May 9 21:09:58 2010 +0000

    Remove pc80/serial.c includes in ROMCC boards and include
    it centrally in console/console.h instead.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b5df5a445614fe83cbdb52f30abd6b8037122b2
Author: Anton Kochkov <anton.kochkov@gmail.com>
Date:   Sun May 9 15:30:45 2010 +0000

    Begin implementation support to IT8512/IT8513
    Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29d3a92e15498da51f4bcdcd91cc5f79877673cd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun May 9 15:15:08 2010 +0000

    i82830: fix debugging output and clarify bracketing
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14db1c0c6b7e88d20141dbf772a519390bbac25e
Author: Anders Jenbo <anders@jenbo.dk>
Date:   Sat May 8 23:28:33 2010 +0000

    Add registers for the it8671f chip.
    Signed-off-by: Anders Jenbo <anders@jenbo.dk>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cee5f7d99631c2c30e7d3d9ff474f7140fb6693b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat May 8 22:02:54 2010 +0000

    autoprobe apic cluster and application processors on K8 systems
    (fixes #18)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d37ce2e28eaa7607442bf3670ed2daec3724dc24
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Sat May 8 21:50:31 2010 +0000

    Add the Wyse S50 thin client to Coreboot.
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 133887d540620d1c13cf3f3be0fdd46cd7adcff1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat May 8 18:14:50 2010 +0000

    wipe some old unused code, this has been cleaned up now.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c53d1f341513cb21d57e39c575553fef61ccab6a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat May 8 17:15:36 2010 +0000

    Patrick Georgi wrote:
    Given that this is exclusively used for checking for mingw and cygwin
    (both support this), at most this requires routing the error message to
    /dev/null.
    
    And rename the variable so it's not used for any non-windows purpose.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2196a0a47a2ee3688b13408a1ac187dbc8aa5d66
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat May 8 15:50:44 2010 +0000

    Slightly improve detecting Windows. Trivial
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 67ee3e612f5a2968c1e6d92f5f6551fcf1500173
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat May 8 11:17:24 2010 +0000

    We didn't have console.initobj.o before, but the same hard coded
    build rule is needed as for console.o
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12584e2bd2ec7ab1ed60dc524574c8ae04dc17d6
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat May 8 09:14:51 2010 +0000

    Drop console/console.c and pc80/serial.c from mainboards'
    romstage.c.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66e5bbe45fac014fb6e49c03fab453f0e866dad6
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu May 6 19:32:12 2010 +0000

    Remove duplicate Kconfig entry. Trivial.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f625f6e9361e06da7017593df841fc69d5d68df
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed May 5 13:13:47 2010 +0000

    Improve the sconfig parser:
    - The device tree must start with a chip (not a device)
    - It's more clearly visible at which places chip, device, register and resource can be used.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d313685b094f0ffa020e5707c5857b1a2063d28
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed May 5 13:12:42 2010 +0000

    Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster"
    in device trees. Adapt sconfig as necessary.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68befd5d34ce22b03ea78028dc362eec0440f83c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed May 5 12:05:25 2010 +0000

    sconfig: Make cur_bus and cur_parent local to the parser.
    Instead of accessing them globally, pass them as arguments where necessary.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 114e7b2990cd2b64956ddb271638646ef5108d54
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed May 5 11:19:50 2010 +0000

    Split C code in sconfig's parser into a separate file.
    Update generated parser files.
    Add proper include path for utils.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 80da618ab0bff7152b2f3b9ee0fb80bbfd7fa986
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue May 4 22:30:33 2010 +0000

    Fix arima/hdama.  It was changed to match newconfig, which was broken.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7339f36961917814ed12d5a4e6f1fe19418b8aca
Author: Valdimir Serbinenko <phcoder@gmail.com>
Date:   Mon May 3 16:21:52 2010 +0000

    Qemu, despite "emulating" an intel chipset, uses the CMOS to
    tell the BIOS how much RAM the virtual machine has available.
    This patch fixes the detection.
    
    Signed-off-by: Valdimir Serbinenko <phcoder@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 80d9804ff776c677932937ac3faf494acf378b45
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 30 20:44:30 2010 +0000

    fix superio warnings. interesting side node: most superio .h files have no
    guards.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c32e9902c4f4a76e404a9a3e673857d5fe7835b
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Apr 30 20:36:02 2010 +0000

    Factor out casmap calculation.  Gets rid of a warning.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5519 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 95bf86be342ea43a99fc7430480d527484d938f9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 30 20:30:47 2010 +0000

    Remove some warnings. For code that is called from the mainboard romstage.c
    files using prototypes is the way to go I think. It would make our life a lot
    easier should we ever decide to move (some mainboards) over to not #include
    all those .c files in romstage.c anymore.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2eac9d496d05f023413fbcee05d466d01d5c113f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 30 20:28:35 2010 +0000

    Remove some more warnings. The code is only used by functions protected by the
    same preprocessor check
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c8873ce2a047a9e64ecabe5b2eb60d2ad088f61b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 30 19:21:01 2010 +0000

    get rid of some more warnings..
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5516 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a8d11a20324fab65b07793ed4bb870c048a32e4d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 30 17:50:53 2010 +0000

    fix compilation of mtarvon
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a2f6a9095c964158dcd02cf4d5cbe173a33b7adc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 30 17:46:16 2010 +0000

    Doesn't need to be a warning.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ec3d38130cfeb7a42178a1e18e927542fa2d7cd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 30 17:44:39 2010 +0000

    drop extra pci access functions. these are exact copies of romcc_io.h.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ad894c54492781253cb7e01373a9d5d2f039f753
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Apr 30 17:11:03 2010 +0000

    Get rid of a few more warnings.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 636d9244259a86afd5af64268c5f6ab660d522fa
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Apr 27 15:00:18 2010 +0000

    Enable the cache before initializing the processor name, like model_10 does.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ebd65d77f85233983eebcb6ed9e2cde8af2a5f1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Apr 27 09:23:33 2010 +0000

    More "prepare"-dependencies we don't need anymore
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 25fc5ffd924b40fdcf6d34e43b10d010df2c21ea
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Apr 27 09:19:47 2010 +0000

    Force mkdir before resolving any make rules.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 771b0e42280ac688ddfae654b3df9582c3caaf6f
Author: Anders Jenbo <anders@jenbo.dk>
Date:   Tue Apr 27 08:45:30 2010 +0000

    Enable 440BX NB to use large memory modules
    
    Signed-off-by: Anders Jenbo <anders@jenbo.dk>
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5508 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14e22779625de673569c7b950ecc2753fb915b31
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 27 06:56:47 2010 +0000

    Since some people disapprove of white space cleanups mixed in regular commits
    while others dislike them being extra commits, let's clean them up once and
    for all for the existing code. If it's ugly, let it only be ugly once :-)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e1e8065e303030c39c3f2c27e5d32ee58a16c66
Author: Anders Jenbo <anders@jenbo.dk>
Date:   Tue Apr 27 06:35:31 2010 +0000

    Remove some additional white space to make it look nicer in nano
    Signed-off-by: Anders Jenbo <anders@jenbo.dk>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b333718e90dba5819769b03403326847d9d67a8e
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Apr 26 13:33:23 2010 +0000

    I meant SSE.  Reported by Dustin Harrison.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03a5d802ffae730cf9e8b92d229d3c2d7e4332f3
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Apr 26 13:27:35 2010 +0000

    Enable SSE2 for ep80579.  Reported by Dustin Harrison.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12fa159451ea4ec3a0d0147848b68bb28456b432
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Apr 26 12:27:18 2010 +0000

    For the mainboard with AMD Family 10, if we make clean and make again,
    it will fail. why?
    
    After make clean, .c files created by iasl are still left in the build
    folder, it will match the rule of
    	$(obj)/%.o: $(obj)/%.c $(obj)/config.h
    		@printf "    CC         $(subst $(obj)/,,$(@))\n"
    		$(CC) -MMD $(CFLAGS) -c -o $@ $<
    it will miss the rule which should be applied.
    	define objs_asl_template
    	       ....
    
    So we move the .c file back to .hex (or other suffix? or delete?).
    This patch will work after make distclean, otherwise nobody will rename
    the .c.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 607cdf62b665230a943a271042bf9c3bf9803cab
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Apr 26 12:08:51 2010 +0000

    fix a bug in pcibios check.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 79255fcdb30a1e04ee25a98a4b25e63e56dba6a7
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Apr 26 06:59:07 2010 +0000

    Set success flag in cx700 int15 handler
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d2759fff554d77c486d822d45e8e917f6c1bcafc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 25 21:44:33 2010 +0000

    cx700 int15 handler rework. Int15 handler needs to provide the
    correct ram clock to the vga bios or there be dragons.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e08c29e0e7f1c1e8682bdb66ce0c51d168fdd502
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 25 21:43:29 2010 +0000

    a single place for the romstage stack for copy_and_run.
    geode lx and amd opteron don't use this yet.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f5436f935412a339e127e0863d39df8a2308830
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 25 20:42:02 2010 +0000

    drop "arch/asm.h" and "arch/intel.h" and create "cpu/x86/post_code.h"
    (which could at some time hold global post code definitions, too)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53b0b50dc838f98a2f3745861414d8b54474f3ba
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Apr 25 20:24:09 2010 +0000

    Fix the the build of r5494 on Asus A8V-E SE. The K8M890 and K8T890
    were not treated separately until now. Fix it. Hope self ack is OK,
    compiled tested locally.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bcb8c97af94c9fc814fdbdafe5361666bf81d442
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 25 18:06:32 2010 +0000

    try to unify timing initialization across those boards that need it...
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14b62da01ded297e12db6ed3b41778202e9aae41
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Apr 25 18:05:42 2010 +0000

    Only do complete VGA init if a VGABIOS was found and installed.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3c10acaacb6baeac377338dae3bc0d5b0fb104a
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Apr 25 15:21:18 2010 +0000

    Following patch changes the K8M890 VGA handling. It reverts the framebuffer size
    to option based (similar what Uwe did) and also it uses GFXUMA to handle the
    high_tables_start offset from memory top.
    
    To satisfy the CMOS option users (Hi, libv!  ;)  I added also a possibility to do
    that through CMOS.
    
    Fixed printks to match the new style.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 467a065384f0d50cbf2d100b55b58168ec98f0d3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 25 14:37:18 2010 +0000

    no warnings days.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d55e26f1b1efe50aa013ad32bdf3e2b58101a64f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 25 13:54:30 2010 +0000

    zero warnings days
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d2a39631efa117d7a5e89810e905a838789518f
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sun Apr 25 11:57:21 2010 +0000

    Trivial. The comment also need to modify.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b6128b6d05fb04578253249f55f91a12b0f1db9e
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sun Apr 25 11:53:09 2010 +0000

    The device number of SATA SB700 is 0x11, while the one of SB600 is 0x12.
    We changed almost associated code when we ported but overlooked some.
    Some legacy of SB600 are also fixed.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4186d8e6eaf2aedb9451580e716a69d634ac08bf
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 24 23:16:23 2010 +0000

    these cpus are explicitly supported by model_6bx
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 714e2a1ac1c41f2150231766fcdb216633fab8c9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 24 23:15:23 2010 +0000

    drop all duplicate copies of vgabios.c in favor
    of devices/oprom/x86.c.
    
    We have some tests on hardware. Moving RAMBASE to
    1MB needs to wait a bit until C7 cache_as_ram.inc
    has been adapted to cache that area or things will
    become incredibly slow (1.5s boot time instead of 0.5)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0704058327e5a8fa00ea32bbe10be748d7824fc1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 24 21:24:06 2010 +0000

    print the known cbfs types in cbfstool "usage"
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3173d8c94a6a091be2a9ad182e707c6f933ee3e9
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sat Apr 24 07:56:32 2010 +0000

    Trivial. Fix a space to tab.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ba3c4fa094921a856cf04dbcff982ecfc68d3be
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Apr 23 20:58:13 2010 +0000

    Attached patch adds support for tinybootblock on VT8237* to decode whole flash
    independent of strapping, making larger flashes work. We cannot walk anything
    else than PCI bus 0 because HT is not setup yet.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 116ec61844982961aab8f89f1dfee1572ffac843
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 23 19:16:30 2010 +0000

    zero warnings days...
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1ad9f29886a547d597b609d496512d151b5c6531
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Apr 23 17:37:41 2010 +0000

    AMD Tilapia board support as a demonstration of an AMD Fam10 DDR3 board.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eedf7a646c36ee5c48a996e2c571223e2eae244b
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Apr 23 17:35:37 2010 +0000

    AMD Socket ASB2 and AM3 support.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb75f652d392d2f4f257194e112f3f0db7479145
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Apr 23 17:32:48 2010 +0000

    DDR3 support for AMD Fam10.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fe6c2cda6e6977894d9b668af9509b983c850f68
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 23 08:03:14 2010 +0000

    Make USE_OPTION_TABLE user visible, so it can be edited.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 676939620a0a7d3e1a763a8b363a14f35eb5dd87
Author: Bernhard M. Wiedermann <corebootbmw@lsmod.de>
Date:   Thu Apr 22 22:47:29 2010 +0000

    Fix AHCI mode on i82801gx.  Fixes SATA hotplug on iBASE:MB899.
    
    Signed-off-by: Bernhard M. Wiedermann <corebootbmw@lsmod.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f75b19ac85ccfffba5eca37700d4c705b24a355e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 22 18:15:32 2010 +0000

    via epia-m now works with default x86.c instead of its own copy of vgabios.c.
    Allows to drop quite a bunch of nasty code
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 64d3baf9829baf9285c94cae0406ee0f428c04c0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 22 13:18:09 2010 +0000

    zero warnings days...
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4292685f5adbe45bb5b23f32c3b6aaed04187f48
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 22 10:44:08 2010 +0000

    None of the cs5536 settings in devicetree.cb were ever used and nobody noticed.
    Fix it!
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba09695b58f7254d646618d1207840e33ca3d1d8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 22 09:22:15 2010 +0000

    fix compilation remaining geode boards
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e169f903071b6201bdb046020d9c73f95e64715
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 22 00:52:42 2010 +0000

    fix ARRAY_SIZE issue.
    the gx2+5536 issue is still open, and it reveils a serious problem with the
    code that was hidden under a bunch of warnings until now.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f94a97be7208781cd63f4aebfc48ee94a739eecc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 21 20:55:38 2010 +0000

    oops, sorry for the last commit. This commit changes the code to distinguish
    between having VSA functionality in the code, and adding a VSA image to the
    ROM.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c705110f65e3de4df11e0a433005876925f539f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Apr 21 20:36:09 2010 +0000

    Move the prototype for run_vsa.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9839cbd53fdcfcee52c406d9f52af924192e618d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 21 20:06:10 2010 +0000

    * clean up all but two warnings on artecgroup dbe61
    * integrate vsm init into normal x86.c code (so it can run above 1M)
    * call void main(unsigned long bist) except void cache_as_ram_main(void)
      on Geode LX (as we do on almost all other platforms now)
    * Unify Geode LX MSR setup (will bring most non-working LX targets back
      to life)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cf036d1266d7ec307aac437105b094acbc9681ec
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Apr 21 06:36:20 2010 +0000

    Optimize distclean and configuration.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca3548e79fd9005d9e9a5694b438bedd87e70560
Author: Pat Erley <pat-lkml@erley.org>
Date:   Wed Apr 21 06:23:19 2010 +0000

    This patch adds:
    
     ICH6 Southbridge,
     82915 Series Northbridge,
     P4 6xx Series CPU
    
    to inteltool
    
    Tested on my Clevo D900T, based on ICH6 and i915P, with a p4 630
    installed.
    
    Signed-off-by: Pat Erley <pat-lkml@erley.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b769126d0065e237eea2fcb0b8218781faf4d1c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 20 23:04:46 2010 +0000

    bayou compile fixes
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bda29314c25aca190071988ec9adfb42f4ba5114
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 20 18:35:33 2010 +0000

    Make VSA code selectable in Kconfig
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e5e7c309157c1f8f047149e55d12a224d262a3e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 20 18:22:20 2010 +0000

    install libpayload.ldscript on libpayload "make install"
    to make coreinfo happy.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97f546cf2d317496c18b49ce4b4b43889830b759
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 20 17:19:20 2010 +0000

    Allow easy libpayload compilation using xcompile.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 338150ed18fec783063550ca0ffacecfebb4caa7
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 20 16:20:48 2010 +0000

    fix artecgroup dbe61
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 01c2f5b0f20331bcfb16df2b7e1f3122a57795c2
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Apr 20 16:00:07 2010 +0000

    Copy mingw support for kconfig from coreboot to libpayload
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 682ea3cc2132639311d772ad9bcb00748e59a257
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Apr 20 15:52:57 2010 +0000

    Make RAM init on i945GC work
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9aea8933c754295436d58027b5b43065bd59c90
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 20 15:49:59 2010 +0000

    cosmetics.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 169dc7e5ac948ccaecadcfd243551f4247df866d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 20 13:22:02 2010 +0000

    - move src/arch/i386/smp/ioapic.c to src/arch/i386/lib/ioapic.c (has
      nothing to do with SMP)
    - move src/arch/i386/smp/mpspec.c to src/arch/i386/boot/mpspec.c (where
      acpi, pirq and coreboot table generation lives)
    - modify src/arch/i386/boot/Makefile.inc,
      src/arch/i386/lib/Makefile.inc
      and src/arch/i386/smp/Makefile.inc accordingly
    - src/arch/i386/smp is now empty. drop it.
    - drop src/arch/i386/init/car.S (unused)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29ceae2c370fcd5a7c159771050611f03de006ba
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 20 11:03:41 2010 +0000

    As Myles suggested a while back: Switch long time #warnings to be comments
    only. Keeping them as #warnings will not likely that they're fixed.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea6772d306fc38fc934792cade14f0c8fc0a4ae5
Author: Marc Bertens <mbertens@xs4all.nl>
Date:   Mon Apr 19 21:21:54 2010 +0000

    Add support for the Nokia IP530.
    
    It's currently its able to run coreboot + seabios + sgabios.
    
    The following hardware works;
            P3
            i440BX  northbridge
            82371   southbridge
            IDE     normal disks + CF
    
    The following hardware doesn't work:
            4x NIC          21143-PD
            2x PCMCIA       PCI1225PDV
    
    Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 961a7b0c08e73e8a7d0061caaef842f1584335fb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Apr 19 20:47:29 2010 +0000

    (trivial)  utils are not depending on config.h. This slipped in by accident.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1cd76e77bf1b8227ddc290a5c347d2f2ec5f4569
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Apr 19 20:39:22 2010 +0000

    - Make abuild -sb work again
    - More explicit rules for obj/%.c->obj/%.o builds
    - Hide printf even with verbose make
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97dbf69106737993d70e8ac6db7b30c1b3909f93
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 17 17:59:40 2010 +0000

    This piece of code was somehow lost in the switch to Kconfig, and re-activates
    proper libgcc handling, which we introduced by revision r4679, which was
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b111ba45906fc0f29a3e1aa3b4ddf5fb90ed4e01
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 16 23:01:34 2010 +0000

    Don't use $(ROMCC) as dependency (due to ccache and scanbuild support
    modifying the variable for their own purposes)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a2acbc70a3eb6544a9909e71939633cf160b082e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 16 22:48:57 2010 +0000

    Build utils into their source directory equivalent in
    the build tree.
    Allow separate build tree for utils
    Use separate build tree for utils in abuild
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 83cce3e8def1a87bff94ba1ab3f94a2eaf85af6a
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Apr 16 13:43:49 2010 +0000

    Fix a typo to remove a few more warnings.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4aeff4ffcfc3a8080646a197938b77c0cafbed54
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 16 11:45:16 2010 +0000

    enable more warnings for vgabios utility, and enable some debugging
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7dcdb3051e8bc85d8841436f1e0e8c0d6e64700c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 16 01:45:44 2010 +0000

    fix romcc compiled i3100 boards.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94c27b3d47dfa6d64192b0fde68d3011074a5bae
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 16 01:14:50 2010 +0000

    fix up sb600 and it8712f tree.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6532116c94c705c7e94a34ab2f046e431fb3682
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 16 00:31:44 2010 +0000

    zero warnings days: unify mp tables. fix warnings.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e46c1c85c90b6d263f951ab745a9fadd93041111
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 15 23:01:59 2010 +0000

    remove more warnings. move ROOT_COMPLEX selection to fam10
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c24d383c15f6d31cd1dd5fb8e090db0561421599
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Apr 15 14:55:01 2010 +0000

    Avoid strdup(0) in build_opt_tbl
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c797a101bf30634eead8714db8a68782fa1b304
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Apr 15 14:32:17 2010 +0000

    Avoid two conflicting invocations of build_opt_tbl
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5391fe02596a4e89947228f9ae57cb8f2a3241d5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 15 12:43:07 2010 +0000

    Myles suspected this hangs certain machines, so back it out.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7bb34db21abc748b718a692525b247e4b6e26747
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 15 12:41:11 2010 +0000

    don't leave VGA disabled by default on thomson ip1000
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23836e2345282151b0b46de6cdcd2bb2faee87f6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 15 12:39:29 2010 +0000

    zero warnings days...
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c30a6e859e20dbadbad006f2f93068e7f9c36043
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 15 08:26:30 2010 +0000

    the dump function assumed that the mbi data comes right after the header.
    Which is not (always) the case.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 075fbe820127c454a6854b87c277a2ca30dee1c2
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Apr 15 05:19:29 2010 +0000

    Remove a few more warnings from fam10.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 07ef092ef228b4cc7c85f375c0390acc901b5181
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 23:58:07 2010 +0000

    get rid of this nerving crt0.d stuff
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 737735b802079cdc09584eeef9dc0ae971fd054d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 21:47:24 2010 +0000

    fix COM2 resource bug in fintek f71805f driver.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6630ce15d7dba1665ba9db0e8fcc4f44caaecbc7
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Apr 14 20:47:45 2010 +0000

    Quote test -f argument, so it doesn't fail on spaces.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 73166c7a50e7905ff3168b4e221afb253c733763
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Apr 14 20:42:42 2010 +0000

    Update mingw source versions and allow parallel builds in buildgcc
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 523ebd927d80807fa8a8c30cddfe0f549b7f62d8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 18:59:42 2010 +0000

    zero warning days. Move RAMTOP and RAMBASE together.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97b21be8c74a2e9da5a7c01944a727e0bab05170
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 17:18:34 2010 +0000

    fix a case where the fam10 code would overwrite parts of a struct.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17b60a985b94a6a6cb71fa3b5ed85e09e42e0ea0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 17:11:47 2010 +0000

    drop setup_ics code that was blatantly copied from cx700 and
    was mainboard specific and unused there already.
    
    some more minor warning fixes.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f4cc089f1eb4b8b4a31c4aae63990034f49c5a97
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Apr 14 16:50:16 2010 +0000

    Remove few more warnings and some dead code.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8816cdf3118d9d197c1b56b0ce0ed63cc119dd71
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 16:39:30 2010 +0000

    geeesh! And this really compiles and even runs?
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4bcfb095b1de5767006527dbd2f8f3c4bc9d22a2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 15:45:02 2010 +0000

    HWHoleSz must be u32...
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d85fbed162c8c3ad017a1505faa9ee3c59e5ccc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 15:44:21 2010 +0000

    udelay_tsc does not exist in the whole tree.
    Neither does quadcore.h (anymore)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71ed353ae25e77bfafd6a2a5ec09cf39e3f36f7e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Apr 14 14:41:30 2010 +0000

    sconfig should return success when it's successful
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34ee3cd512188baa93ba5595da2982e39fcc7491
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Apr 14 14:35:40 2010 +0000

    Rename variable to not confuse gcc on mingw
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5d3dee8334c2303434d7b00bec3aad4911120ac1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 11:40:34 2010 +0000

    drop quite a lot of dead code that did nothing but produce warnings and make
    the rest of the code unreadable.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4154c668f24da79672099dfac06f5263c415fee0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 10:12:23 2010 +0000

    zero warnings days. Down to under 600 different warnings
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c264ad930a2579dc235de0c95842374e89ff5d6a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 09:04:31 2010 +0000

    fix digitallogic adl855pc compilation (and clean up the warnings while at it)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ccdd20a539f81591df3ca5d89e2b74663865e0b1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 14 07:47:07 2010 +0000

    move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list.
    this patch also slightly changes it so we have a single cache_as_ram.inc which
    requires no "help" from cache_as_ram_post.c and cache_as_ram_disable.c (or
    worse, a lot of cruft hacked right into romstage.c like on tyan s2735)
    
    Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new
    simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1abf46c74ed34eb394921d2f72817c728e3bb9ee
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 13 21:31:42 2010 +0000

    ip1000: fix seabios start, fix flash gpio detection
    simplify i82830 code.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ae1db0a9b3904c27c9d180170be844ee39ee869
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 13 21:29:43 2010 +0000

    fix a trivial warning when yabel with direct hw access is enabled.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f10de6cab6e00189621b9b60f1e4640497bd805
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 13 13:48:20 2010 +0000

    fix timer choice in Kconfig. HAVE_INIT_TIMER is selected correctly, no need to
    mention it explicitly.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 79253841a7b72351346755fea0c9d89b2426f81a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 13 13:43:35 2010 +0000

    clean up LD scripts and add some comments and proper license headers
    where applicable.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea7f5a253b5e7b954a207349d61ca24a145765a3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 13 10:04:35 2010 +0000

    use the standard udelay on sc520.
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f17ca16624140b0a2509fc37b084616b7857089e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 13 10:01:14 2010 +0000

    Speed up coreboot_ram loading by moving the decompression stack
    into the cached area. Back to 469ms until coreboot_ram is actually
    running on epia-cn
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d68df779f26b577632c2110dac233c01457b91f
Author: Marc Bertens <mbertens@xs4all.nl>
Date:   Tue Apr 13 01:22:20 2010 +0000

    Add support for the SMSC FDC37C932 Super I/O.
    
    This chip is found e.g. in the Nokia IP330 (firewall hardware).
    
    Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 170679b9ddc3ccd92840c14d2b51be2908c67875
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 13 00:11:59 2010 +0000

    update atom car code in the same way that 6ex/6fx was updated.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d1b0d84f2f35bd2a8db77a16ef54c7cf5c4b838
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 13 00:02:20 2010 +0000

    Fix eagleheights
    not a 6ex board, but using the same CAR code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1977b891c55a01e436b2aae1421f635b0c873778
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Apr 12 23:12:15 2010 +0000

    port latest model 6ex car changes to 6fx car, which is almost identical and
    currently unused. Just keep it in sync, we might need it some day.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3e1f524566dd89e5a7af424a06091e78c5a696da
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Apr 12 23:04:29 2010 +0000

    move model_6ex car to a single file. No more .c files that only consist of a
    single several pages long asm statement
    
    Could use some renumbering of post codes, but that's good for another time.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5934b507d5dcac9063ce180e0fa46be4cc01d69c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Apr 12 15:28:34 2010 +0000

    Move the CPU specific includes from
    src/arch/i386/Makefile.inc to the respective CPU directories.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09f6718dda28d09312d45f841f585f6e0a4934f7
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Apr 12 10:22:20 2010 +0000

    Enable lazy evaluation of incs/lds for tiny bootblock, too.
    Necessary for romstraps
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f1ce6f2c2518b70eae23502593393fd40fd73806
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Apr 12 09:50:53 2010 +0000

    - move the XIP_ROM_* flags to src/cpu/x86/Kconfig exclusively
    - set them to span the last 64k, instead of the last 128k
      by default
    - fixes via CAR for tiny bootblock
    - enabled tiny bootblock for via/vt8454c
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9466493ec85045659336d11868ddd626944b650
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 11 20:04:50 2010 +0000

    add int15  handler for thomson ip1000
    fix mbi length detection, this will remove what looked like an endless loop
    during vga init in some cases.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4cc5af95b510141214fb454ffbf7796d4e086813
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 11 20:02:47 2010 +0000

    do better error reporting in i82801dx early smbus functions.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit accb50a4e3db15629dd3bc24e602e3af47a974db
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 11 19:02:10 2010 +0000

    The ADL855PC was never confirmed working (in fact it's pretty sure that code
    does not work as it is, but it's the only compile test case for i855pm). It's
    the only board left using an ICH4 that does not use CAR. Change that.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 735c5acdce4403de90258362705ece059b0cdffe
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 11 18:57:10 2010 +0000

    add support for reading ip1000 gpios.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d93af23d6aa69e2b8534fabcd8b123d751b65fd8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 11 18:54:47 2010 +0000

    simplify ram_read32 on i82830
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 77d31ec4a88aeba08db6b7864959a87aeefc6b2b
Author: Joseph Smith <joe@settoplinux.org>
Date:   Sun Apr 11 16:36:13 2010 +0000

    More trivial changes to i82830 raminit.c for USE_PRINTK_IN_CAR.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bdf26a6bf523eefa577b5e3d68c1e414d990838a
Author: Joseph Smith <joe@settoplinux.org>
Date:   Sun Apr 11 05:50:08 2010 +0000

    Trivial changes to i82830 raminit.c for USE_PRINTK_IN_CAR.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 948f922342ce9f577e3ba498a1ece953c93fc96f
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 9 22:25:27 2010 +0000

    We don't define LB_CKS_* per board anymore:
    build_opt_tbl figures them out for us.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c8a9ead1c5cdba3b19440c7bcc27369f58c02a74
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 21:05:36 2010 +0000

    Drop ASM_CONSOLE_LOGLEVEL from LX car code. We do output in C in copy_and_run /
    later.
    Call copy_and_run instead of cbfs_and_run_core because we can choose the
    coreboot_ram filename in C instead of Assembler.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 314e551447f408300e56cd6206af3e52d9b22059
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 20:36:29 2010 +0000

    This patch changes C7 CAR code to be a single assembler file instead
    of the ugly mixture it was before. It also enables CAR for all C7 boards
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fbb02a5f9d8aa04ce69ed955f739022a1e0dce9f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 15:39:21 2010 +0000

    zero warning days.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c0db453b69e025049bc114c21fdc294648eefdf
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 15:29:13 2010 +0000

    fix the broken nvidia chipset boards,
    remove more warnings.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4f53738e678f99bd12068b2e2b2ecae9fc046b0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 14:46:51 2010 +0000

    zero warnings days.
    
    The tyan s2895 is down to 3 warnings, 2 of which are caused by #warning.
    
    The 1000 ways of how the AMD code waits for the cores to be started up
    are a real pain for the brain.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f358c0c55510e4272ace99e192b9494e64f89697
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 13:49:48 2010 +0000

    drop now unussed cpu_reset.inc
    make it more clear if coreboot is building without payload.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 306343266b47db9022591a342571631fb864ae18
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 13:35:03 2010 +0000

    zero warnings days.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d41a0bc532c837705d5abc2334e1bbf9dd06eb83
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 13:33:59 2010 +0000

    Drop the need for cpu_reset, it's really just a short cut to stage2.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa987b23e4a639d1c6bfd6f3043a465874d56953
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 13:31:07 2010 +0000

    drop unused files
    drop some non-car code from amd/dualcore (there is no AMD dualcore without CAR)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e34aeffd39bb672de520f403533efa2f77df1da
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 11:55:43 2010 +0000

    remove some amd mainboard warnings.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c666a64395efd7472ff6f5de5589593c7d5f8e33
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 11:37:58 2010 +0000

    drop unused files, and we only use ASM_LOG_LEVEL in one file now
    (LX CAR)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a445e812604edaa0f11c99d835eddaeefa83d3b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 11:34:59 2010 +0000

    zero warning days.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7488e049df9899dd7062b2ffe393b3e9a6f50dc5
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri Apr 9 11:10:25 2010 +0000

    1. This patch adds CAR for Intel P6 series processors.
    2. Add support for Micro-FCBGA 479 Celeron and PIII's
    3. Add support for model_6bx and microcode updates
    4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson
       IP1000
    
    Build and boot tested.
    
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    
    The change to CAR reveiled a few more warnings in the ICH4 and i830 code,
    I fixed them on the fly.
    
    Checking this in because my last two commits broke Joseph's CAR patch. This
    version fixes the issues.
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 853263b963b4cacb4f7fa3a7f2c68dcbd094f1d7
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 10:43:49 2010 +0000

    copy_and_run.c is not needed twice, and it is used on non-car too.
    So move it to src/arch/i386/lib/cbfs_and_run.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 10b29d8cfe60891851817e81b6e705da6c6d4534
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 9 10:12:18 2010 +0000

    thin out romcc epilogue and have it call copy_and_run as
    all the others do. Make sure copy_and_run is called with
    the right calling convention. Fix up 2 license headers.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c58f1d1df610e6fb819240919749974045d3c636
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Apr 9 04:01:55 2010 +0000

    Indent model_fxx_init and model_10xx_init.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae60855f918dfc7f3f560528296fdd2d4b4ca791
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Apr 9 03:41:23 2010 +0000

    Copy acpi blobs in two parts to make sure gcc does the right thing.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e64b63750f029dac66902dee8cf6a7cf82ba44a3
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Apr 8 21:04:45 2010 +0000

    Split crt0.S.lb into prologue and epilogue
    (the latter only for romcc), rename crt0_includes.h
    to crt0.S, and compile that directly.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 362db613a0556a102e2812c1c00e3491eafdb66f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Apr 8 15:12:18 2010 +0000

    Cosmetically make init_cpus more similar for fam10 and K8.
    
    Remove some fam10 warnings.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b43afde3922e7c4c58dbed85df2a9ea26e11bdf
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Apr 8 15:09:53 2010 +0000

    Clean up fidvid files using indent.
    Remove some special print statements.
    
    In general, make them easier to compare.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4839e2c495d16e7c49acd5eb933ef7f42e67713a
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Apr 8 15:06:44 2010 +0000

    Replace dual_core and quad_core CMOS (nvram) options with multi_core.  Fix some white space.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 604877eb2a29ee24d4c99659ae5155792c6e3628
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Apr 8 15:02:39 2010 +0000

    Move Kconfig for HT limits to northbridge/amd/Kconfig.
    
    Guard the code with CONFIG_EXPERT to remove warnings.
    
    Make it only show up for fam10, since it isn't implemented for K8 yet.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e705f9cee2a7bcfebd2b468365c0522434d29200
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 8 13:16:32 2010 +0000

    output cosmetics
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 05245ec05b69d2431b8ed78c05b99b1aac95a44b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Apr 8 12:59:41 2010 +0000

    Remove #line statements in processed parser source,
    to avoid clutter in revision history.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 35784b62cde8b126cdb1fbb2a7a6d170760bd28d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Apr 8 12:47:35 2010 +0000

    cpu/emulation/qemu-x86 doesn't exist anymore, as this
    is folded into mainboard/emulation/qemu-x86. Adapt code.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2bbd0c29261d985e21dc69a731c895ee2791eb4b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Apr 8 12:46:18 2010 +0000

    sconfig: Mangle - to _ for struct names, too.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5375 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 109a1de1ef8d79ebdae79e94638bcce545d8a8dd
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Apr 8 12:00:35 2010 +0000

    Remove duplicate registers in digitallogic/adl855pc's device tree
    Create directories before trying to copy files into them
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e8c9aa271f13f67e4fc4968d2bf6fb8e5b229d7
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Apr 8 11:37:43 2010 +0000

    Replace sconfig with a C implementation.
    (smaller, faster, standard parser generator, no more python)
    
    Provide precompiled parser, so bison and flex are optional dependencies.
    
    Adapt Makefile and abuild (which uses some sconfig file as a
    magic path) to match.
    
    Drop python as dependency from README, and add bison and flex
    as optional dependencies
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 56a684a2ee52b765fc69ec8c922c3da9d8ab7430
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 15:40:26 2010 +0000

    - copy_and_run() gets the same calling convention on AMD and on all the others.
    - some vx800 Kconfig fixes
    - remove warnings...
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eea66b7c3534d2959be482fc97b84d656c5bb953
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 15:32:52 2010 +0000

    no warnings day
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e9de1e2609dfeab0b638b1e8facd642a88428745
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 15:30:11 2010 +0000

    move amd K8/Fam10 "bus detection" function prototypes to a common place.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 135a966d34123cbc4ab5959f92e5364651c1ad55
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 03:41:39 2010 +0000

    it's a long term, give the compiler a chance to breathe .. ;-)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a9268451423da1648a4454aaf3b76c2989ee3b4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 03:40:37 2010 +0000

    clean up age old via epia target.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3dfd03f8878679902927748e305643b6000d0e5b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 03:11:28 2010 +0000

    drop the use of function pointers from romcc code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c02c34e886afda101b522a9be34e6a7c7c4217cd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 02:30:57 2010 +0000

    fix epia-m700 compilation, and remove more warnings.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c214693aa5439dcaf3f0d5b2802f1b2d931ad25
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 02:09:54 2010 +0000

    no duplicate names in cmos.layout.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c2d29415c3b3c40149087fe6a379e60c030c9d58
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 02:06:53 2010 +0000

    switch some ROMCC boards back to ROMCC.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c51dc44bf2b76ac47b83ee76bee3357ce4b173de
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 01:44:04 2010 +0000

    "no warnings day"
    last round for today. still warnings - help appreciated.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39162f7b47c9258980e08d05038d79d1ff925372
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 01:41:01 2010 +0000

    oops... this is a critical issue. Some boards in the tree don't compile with
    romcc even though they don't have CAR either. We need to check all boards and
    fix those that are broken like this.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8b19238481c7581cb521c4f5bde8b9e6f091ee1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 7 00:38:09 2010 +0000

    - unify use of SB_HT_CHAIN_UNITID_OFFSET_ONLY
    - cleanup reset
    - some minor warning fixes.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ff769baa58f786bdbeef23dc911e730884d803a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 6 23:55:17 2010 +0000

    fix CK804 boards.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f2c616dbc7f36bf63d61960c2e14c6ca1c5af22
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 6 21:50:21 2010 +0000

    No warnings day, next round.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 233f186e95cf76d3a5bb5a7224769f63c36c5931
Author: Stefan Reinauerstepan <Stefan Reinauerstepan@coresystems.de>
Date:   Tue Apr 6 21:49:31 2010 +0000

    fam10 acpi fix
    
    Signed-off-by: Stefan Reinauer<stepan@coresystems.de>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 133647aa8689810c3e15d31ae163e7c865aeaf92
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Apr 5 19:47:34 2010 +0000

    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    Add Asrock 939a785gmh motherboard. The ACPI needs more cleanup, could be done when cleaning
    the Mahagony board. The SidePort mode does not work because AMD hardcoded memory type in rs780_gfx.c
    The UMA is enabled instead. The board boots, network and int VGA works, IDE too.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f932c2edadcedcab247b4f891d13c48859d202dd
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Apr 5 19:21:18 2010 +0000

    Add RS785G, looks like it works although it is RV620.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9250c6740d4aa32724115ddda166f191501b2df
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 3 15:41:27 2010 +0000

    device_t wants device/device.h
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 10dd8b4a08ed89d73f420bff8d1326e2a698e4ef
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 3 14:19:22 2010 +0000

    no need to udelay()
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c8ac786c83f4ee08442bd2233a34306b8c8e286
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 3 13:33:01 2010 +0000

    remove more warnings.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c65666f70d2b9885a7134c564784be2a49394f91
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 3 12:41:41 2010 +0000

    remove more warnings
    rename amd64_main to stage1_main..
    copy src/mainboard/via/vt8454c/debug.c to src/lib/debug.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bed872dedfeb3b3ce33c0ce715904887a729e76f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 3 00:03:07 2010 +0000

    Add noreturn attribute to die() in romcc.
    This makes life a lot easier for static analyzers such as scan-build.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26afd18e1084c026c655aea7f7066a32c5d9ef90
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 2 22:31:35 2010 +0000

    remove more warnings.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b4a3fcfb4b9ae0864d23ff88e02b694c25d40752
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 2 22:13:27 2010 +0000

    oops, sorry, overlapping work
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 720297c3d46122af14c69545f4ab22337f540ae3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 2 22:11:20 2010 +0000

    remove some more warnings
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b54deb77f03269419a257d3c5b0f06d38831f125
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Apr 2 21:39:12 2010 +0000

    Fix console prototypes for non-romcc boards.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4fa5ee88c6702681c5d54da6b759479baa81a03
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Apr 2 20:14:21 2010 +0000

    Fix includes for showallroutes.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7355c7590bfd55f5bb15a5ca06acd841ece3b24a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 2 16:30:25 2010 +0000

    The error message is misleading, even for a SPEW, because
    the slot is empty, it's NOT a bad ID (and the message is
    more confusing than helpful even in SPEW)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0c781b2694b2c137d9761704954ea38be5ba8a15
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 1 09:50:32 2010 +0000

    -Â get rid of ASM_CONSOLE_LOGLEVEL except in two assembler files.
    - start naming all versions of post code output "post_code()"
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84b685af5f1e1cf49c2c2f22ae80a8a0df8472f8
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Mar 31 14:57:55 2010 +0000

    Consolidate ifdefs in src/lib/cbmem.c for readability.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 64ed2b73451de4b655b3fdda0ff42825a165c317
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 31 14:47:43 2010 +0000

    Drop \r\n and \n\r as both print_XXX and printk now do this internally.
    Only some assembler files still have \r\n ... Can we move that part to C
    completely?
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a1f5970857a5ad1fda0cf9d5945192408bf537b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 31 14:34:40 2010 +0000

    This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and
    makes include/console/console.h and console/console.c usable both in
    __PRE_RAM__ and coreboot_ram stages.
    
    While debugging this, I removed an indirection from the e7520 ram init code
    (same as we did on a couple of other chipsets, removes some register pressure
      from romcc)
    
    Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code
    		in cache_as_ram.inc)
    
    Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with
    CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8ac05d187c6cc4e777c96d39e075c5d97d93ffc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 31 00:06:12 2010 +0000

    mini part of the patch on the mailing list to fix the boards again
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2b7a43f9d0806417847a16e24a55d07af972e10
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 22:21:06 2010 +0000

    no USE_INIT
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3ac400e6e57f2efc8db06b9b3206b253d142c741
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 22:12:59 2010 +0000

    drop USE_INIT should be USE_PRINTK_IN_CAR here.
    uint32_t should be u32
    DEBUG_RAM_SETUP was failing on some northbridges
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b01fe696d495cfd15f861d270c88547aabf1f6c4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 22:08:48 2010 +0000

    that version of console_tx_byte is private.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23a3e7940544091bcc2df6421b8fea5aad8501d7
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 22:03:10 2010 +0000

    fix some amd k8 warnings
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cca626817dc88bfaec8b6ebf787f5f57006fe0cb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 21:52:05 2010 +0000

    get coreboot_ap memory training in cache mechanism in place. Didn't work since
    Kconfig (needs more patches to ap_romstage.c but this is a first step)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c269d237f93d7867c7f4cad9a4d619b56f4a3d81
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 21:48:23 2010 +0000

    fix some southbridge warnings (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 495b92b78739ddc1b5eb3cd610629cfb4d62547f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 21:47:10 2010 +0000

    - drop unneeded Makefile.inc
    - drop ap_romstage from Fam10 boards, the mechanism was never used on Fam10
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b2f18523aeef277d9790c90fa7345e7565ec09e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 21:43:15 2010 +0000

    indent mptable.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc2b8ec5ad0e3ea7ac310e4192fe5cee0a249770
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 21:41:33 2010 +0000

    drop USE_INIT from mainboard Kconfig files, it's already set in src/Kconfig
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit acdd52fa82e2157f0777d2d2aab5d74bdc5dcec4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 20:32:01 2010 +0000

    make crt0s and ldscripts evaluate late, so the chipset_* variables are there at
    the time they are finally used. This should solve the Problem Myles was seeing
    earlier today.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ed0b7cfe819ffcf0a1c305deb63b6ea8ace78bb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 15:49:14 2010 +0000

    abuild:
    it seems make oldconfig is not safe for parallel compilation. The problem never
    occured in my tests, but go back to non-parallel build again. Also pass on the
    return value of make oldconfig correctly.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abdf84884e7ffa5335c6534a6198a38812ff51a4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 14:02:19 2010 +0000

    abuild:
    - increase context to 6 lines in case of build error
    - add update mechanism to automatically produce fallback+normal in one image.
    - tighten up output
    - in-coreboot-builds makefile main target is now "all" as coreboot.rom matches
      a file
    - time measurement now includes "make config" step
    - actually allow long-implemented long version of --remove|-r option.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd0bef825d88fa75d0703569ed01e05066766826
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 09:59:23 2010 +0000

    build_opt_tbl: error instead of null pointer access if no checksum is defined.
    xe7501devkit: If cmos.layout is used, there must be a checksum.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c719f1a506060e6283352d114fd6d589e4c6ce3d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 09:57:28 2010 +0000

    add CONFIG_NO_POST as it is used in the code, and move it together with CONFIG_SERIAL_POST
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b547b19800ab85c97103c87fedbba7512add7d6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 09:56:35 2010 +0000

    reduce warnings in MCP55 and Fam10 code
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b70cb624387999787683bd5279f11f922debf7e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 08:20:37 2010 +0000

    fix ms9652_fam10
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9050b71802b801b24544013e6a515350b615ee68
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 08:01:43 2010 +0000

    unify cmos.layout wrt AMD extended configuration registers.
    This removes double preprocessor define warnings from many boards.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ac3df8ae29b787e94b22a2c3f4b21b15c22298c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 30 00:22:29 2010 +0000

    this fixes 3 of 4 mainboards failed by the error on missing IRQ_SLOT_COUNT.
    The third, MSI MS9652, creates an IRQ table on the fly, no kidding.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e726b7363365459ab07b6f68e579b15a3ea8693
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 23:01:35 2010 +0000

    Don't include option_table.h every time we include mc146818rtc.h, that was a
    stupid idea. Instead include it where it is needed. And add some explicit
    dependencies to it.
    
    Also, error for missing IRQ_SLOT_COUNT for now, so we can fix up the boards.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 798ef2893c44ce3194c539c8c5db33d11e8edbac
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 22:08:01 2010 +0000

    This drops the ASSEMBLY define from romstage.c, too
    (since it's not assembly code, this was a dirty hack anyways)
    Also run
        awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines
        mv $FILE.nonewlines $FILE
    on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c
    cut some holes into the source.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 72bdfeb6987f9578ac7fee3f21140ab5853d6179
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 22:05:26 2010 +0000

    - drop GCC 2.x workaround, GCC 2.x is not supported anymore.
    - warn if we didn't specify IRQ_SLOT_COUNT in Kconfig
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86b6dba7eaea79c1d9f485396bd6b5ea24088160
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 21:56:26 2010 +0000

    trivial warning cleanups
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8655412673f650839fa659849da6e356895524ae
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 21:50:53 2010 +0000

    - include option_table.h when it is created, and that's HAVE_OPTION_TABLE
    - add some __PRE_RAM__ guards where needed
    - use OPTION_TABLE_H
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c5dc6594998cc8764773195bea40003e77c41bf
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 21:17:25 2010 +0000

    qemu: drop "northbridge.c" from src/cpu/...
    It's not a real northbridge, so I just move it into the mainboard directory for
    now (until we maybe have a qemu-q35 image some day?)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e32823a68f74618845c21600c8fa491f9c6c1a4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 19:19:16 2010 +0000

    __PRE_RAM__ is now correctly specified in the Makefile. No need to hack it into
    romstage.c anymore
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8013d5a568d6ad3b98587ea2bb23dcbd06d7ed18
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 19:04:13 2010 +0000

    cpu_driver structs need to be const, too...
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5828d74455a91553d78ef3077936693ae36213f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 17:14:28 2010 +0000

    This patch drops the coreboot CMOS checksum ranges from Kconfig because
    the information is already specified in cmos.layout. coreboot is changed
    to use that version instead.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmai.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 002c9ff3e453b5c93e1681c4ddc7624a4bf9e5a1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 16:23:42 2010 +0000

    abuild: fail with dignity if mainboard does not exist.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a16e3e5a6f5b0dda15343132c271afc89dbd846
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 14:45:36 2010 +0000

    dualcore.h and quadcore.h are almost exactly the same.
    Only have multicore.h for both of them.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e9f3258e0b1ed57308d277d3b5a6c67f4819e171
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 29 13:04:13 2010 +0000

    This patch fixes build.h dependencies in coreboot again.
    -include was dropped, the files in question do an #include <build.h> already.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e0d607a4c5838628822904e75bdb3cd69ffa3220
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 28 21:31:30 2010 +0000

    Add a non-time consuming version of ram check so we can print a decent error
    rather than looping on non-working ram.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bcd31fff4213345c3447f0ffffec7331dfed8c3e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 28 21:30:23 2010 +0000

    drop post_code()
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 35b6bbb7217956fe29f5d7f29d3ce780f1e640f5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 28 21:26:54 2010 +0000

    drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is more
    appropriate. Also, factor out post_code() for __PRE_RAM__ code and drop it from
    some mainboards.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 83a1dd850b9f61929a2db17a9429d3d193e34bfb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 28 15:11:56 2010 +0000

    drop __ROMCC__ define checks.. __PRE_RAM__ is what the code should be looking for.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f733d4754438f7289dd84d19871c7fe0a322801e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Mar 27 17:36:39 2010 +0000

    ccache and scan-build actually work together, so remove the
    restriction that tells Kconfig not to allow that setup.
    It's not particularily useful, as scan-build totally dominates
    the gcc runtime, but well..
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 51e142fef4c47b6ba30b9aaf5f3fcf34c781b59a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Mar 27 17:18:39 2010 +0000

    make only needs to read Makefile.incs once, thanks to the
    SECONDEXPANSION feature of GNU make (and we rely on GNU make for lots of
    things already)
    
    File paths are relative to the root directory, which simplifies
    debugging (make V=1 gives shorter command lines) and helps ccache
    finding matches for checkouts in different directories (even though it
    should normalize paths itself)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9417cc05fcd485fe699f88a73356c59c1c5181e0
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Mar 26 18:31:12 2010 +0000

    Remove dead code and make white space more consistent for acpi_tables.c
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 723c2702116af499389a9a73ff8df35fee37ee64
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 26 11:47:13 2010 +0000

    Update libpayload default configuration so a make oldconfig
    on that configuration does not ask questions.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 026476e4e3eb0f925b355c079618378248c8e7a2
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Mar 26 10:33:36 2010 +0000

    Make sconfig only complain about real conflicts.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0735142bdd2aba4cf47ee5ddde6f9696b55f9791
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Mar 26 01:43:30 2010 +0000

    1. Remove warnings and multiple blank lines.
    2. Mahogany uses GPIO9 to detect 80-pin IDE cable.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b56f2d0ad4bfc81e7ef5ffd406c652f2c3bd954a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Mar 25 22:17:36 2010 +0000

    USB updates from our internal tree
    - support MMC2 devices
    - make usb stack more solid
    - drop some unused functions
    - fix lowspeed/speed naming
    - add support for "quirks"
    - improve usbhid driver
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e5d30b78b7720ba3e511819b7fc51c11d642153b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Mar 25 22:15:19 2010 +0000

    libpayload update
    
    * rework Config.in
    * add string_to_args function to actually make getopt usable.
    * add strchr
    * add strlcat
    * some malloc fixes (exposed by the USB stack)
    * add malloc debugging (thanks to Matthias Krause from Secunet!)
    * make LAR support optional, it's not really used anymore
    * (define htoX macros for ppc)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 516a2a7bfaee5d4aa4d1e7e5ff52d3038513c82f
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Mar 25 21:45:25 2010 +0000

    Add support to build with ccache in the build system
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ab9d12e290ab79786d34fdf12c99922f5255aff
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Mar 25 19:01:27 2010 +0000

    Make build verbose when requested by abuild
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b700254aa5150023a13902adbe31839ec4f926cb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Mar 25 18:56:26 2010 +0000

    Add coreboot framebuffer support to libpayload
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7208f6e031957ab163136546c191d577c7418299
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Mar 25 18:54:43 2010 +0000

    don't hardcode i386 in lpgcc
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0350c0fe197947bfe67d6cfad62dfe2132238ec3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Mar 25 18:54:08 2010 +0000

    allow libpayload to completely build out of tree.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d361308f1862a9c662a21ffe50aed08fb4c4fdb7
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Mar 25 18:53:20 2010 +0000

    prevent timer overflows in libpayload
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1beabe10cded46a7b21b6ab163f95b1e19172492
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Mar 25 18:52:24 2010 +0000

    make keyboard reset driver generic (not pc keyboard driver dependent)
    so it can be used by usb, too
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c2d0b62cc1af8ba3f2ae63ee64c18c1234c6c89e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Mar 25 15:49:40 2010 +0000

    Copy argument of -include as it's modified later.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09a0eb478b229261920c155324c3a5cb2f14bc78
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Mar 25 15:25:15 2010 +0000

    It's really obj=, not O= (see toplevel Makefile)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86dbe15017d2042e6b15d89b7f2e19e100a884eb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Mar 25 14:18:57 2010 +0000

    One feature I've been really missing since we switched to
    Kconfig is that after an abuild run you could cd to
    coreboot-builds/mainboard_name and just run "make" to rebuild
    that one target (and get a non-parallel build easily)
    
    This small add-on to abuild brings that feature back.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 715d6e0982ad05a317478738acb8d7e3d3cf85da
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 24 22:39:40 2010 +0000

    abuild should be using O=, not obj=
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 565a281f3696bf6252fe3153f4b680db85fe7906
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Mar 24 22:02:53 2010 +0000

    Get rid of type-punned pointer errors.
    
    Defining AmlCode differently in different source files is a bit ugly...
    Creating a void * to do the casting is not exactly beautiful either...
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d1149d7ef13ba63baac89dfe687bdd01e93f79ca
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 24 21:24:17 2010 +0000

    Some keyboards need a longer timeout. Also increase error level, because a
    not-connected keyboard should normally not raise an error.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a2e5f3713d2d23993fb754e49bda310ad5567ad6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 24 21:21:33 2010 +0000

    Drop unneeded code that checks for CONFIG_ variables in
    build_opt_tbl.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb44d0e7e003f7e9a43f55a6f357297092bc3471
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 24 20:59:43 2010 +0000

    fix acpi dsdt copy on roda rk886ex
    
    thanks to Myles Watson for spotting this...!
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f0aefbef54473c20a04ffe04779d13ef100ef73
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 24 16:45:46 2010 +0000

    SMM: remove hack that was needed back in oldconfig times.
    
    These days it even does the wrong thing (not using the .smmobj.o version of
    vtxprintf.c and printk.c)
    Also, SMM never needed libgcc, it's only in coreboot_ram for yabel/x86emu's
    crazy math.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7103eb707ab836a371aca89617bf842b78d6c28e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 24 16:18:06 2010 +0000

    oops, forgot to cleanup extra output in bootblock creation for dependency patch
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6bee951c302686fd3598859f9116a4bf36252673
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 24 15:51:48 2010 +0000

    dependency tracking for coreboot
    
    Obviously compile time increases slightly because more work has to be done, but
    I'm sure the benefit of having to rm -rf build less often is worth it :-)
    
    Other small changes:
    * be a bit more verbose on some of the created files
    * move -O2 from compiler rule into bootblock_romccflags
    * drop rule needed for util/*.c -> build/*.o as x86emu no longer lives in util.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9db39d3b43b56ba16e05e4434518092bf31e99f4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 24 09:53:50 2010 +0000

    CPPFLAGS and DEBUG_CFLAGS don't exist since Kconfig. Drop their remainders.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 93a69b87564105f100e9f914de59fb3c5abe2e4c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 23 17:01:23 2010 +0000

    mahogany_fam10: rename apc_auto.c to ap_romstage.c like on all  other boards
    that have one.
    
    Can we get rid of ap_romstage.c completely? It sounds like the wrong thing to
    do.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cadefaf20fb4a32fad6e0da9292a51ab9b862af9
Author: Maximilian Thuermer <maximilian.thuermer@ziti.uni-heidelberg.de>
Date:   Tue Mar 23 15:58:29 2010 +0000

    Fix reading HT link offsets.
    
    pci_read_config32 overwrites the real value, use another variable for that.
    
    Signed-off-by: Maximilian Thuermer <maximilian.thuermer@ziti.uni-heidelberg.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86051f919fc34d731619fc3a1266c5a2c4855b01
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 23 15:53:38 2010 +0000

    Use coreboot-internal version of x86emu for the vgabios utility.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7f53b2329d468a6efa50c7c1163079d296fbdc3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 23 15:49:44 2010 +0000

    Prepare for using coreboot x86emu in userspace utility "vgabios"
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f0aa09b51b1874b8d52574d18a497162eda9cdf5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 23 13:23:40 2010 +0000

    fix newly introduced printk_foo warnings..
    
    Interesting enough, console_printk was only used in a single place and
    duplicated a large part of console.h which is included in the same place.
    Thus, just drop console_printk.c and we're one down with console complexity
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b2cda82b460098768d74dc4e01df00f78c60e41
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Mar 23 06:49:16 2010 +0000

    Remove the building warnings.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b63bdbe29bd8bbc4756369792cc271ef6efa5e34
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Mar 23 06:46:01 2010 +0000

    Remove the building warnings.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c8c09bb23942762ab9bc5e645b696bbad631628f
Author: Wang Qing Pei <wangqingpei@gmail.com>
Date:   Tue Mar 23 06:25:55 2010 +0000

    Removing build warning of sb600 & rs690.
    
    Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5466b0251a187b345cac1bb1d174590c1d98cab
Author: Joseph Smith <joe@settoplinux.org>
Date:   Mon Mar 22 23:10:53 2010 +0000

    Fix i82801dx_power_options() so CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL works, and rewrite HPET code.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e799c8b140283eccd2db014a0daacc007a195619
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Mar 22 16:35:38 2010 +0000

    Revert my debugging patch that got committed by accident.  Sorry.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 08e0fb881093c977488de6e8d701dd69369123ec
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Mar 22 16:33:25 2010 +0000

    Fix all the format string warnings.
    Some other random warnings.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53b0ea4bf24c0ae51aa9f8447d4ce9d44d46af72
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 22 11:50:52 2010 +0000

    drop some unused files and fix warnings on i945 based systems.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c02b4fc9db3c3c1e263027382697b566127f66bb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 22 11:42:32 2010 +0000

    printk_foo -> printk(BIOS_FOO, ...)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 27852aba6787617ca5656995cbc7e8ef0a3ea22c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 21 23:33:36 2010 +0000

    drop dead code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1425add4c83cf55ed57c33607fb9922c77905565
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 21 22:35:58 2010 +0000

    fix "make" after "rm -rf build"
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 121f0b8cf0999af0ead783c72fab151156325a69
Author: Christian Ruppert <idl0r@gentoo.org>
Date:   Sun Mar 21 21:22:51 2010 +0000

    Don't abuse LDFLAGS and fix linking with -Wl,--as-needed.
    
    Signed-off-by: Christian Ruppert <idl0r@gentoo.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd0381a705246fb7e94675999a92fe0e3c98ee8f
Author: Ed Swierk <eswierk@aristanetworks.com>
Date:   Fri Mar 19 21:57:40 2010 +0000

    I ran into a couple of errors while building a mahogany_fam10 target;
    CONFIG_CAR_FAM10 was renamed some time ago to
    CONFIG_NORTHBRIDGE_AMD_AMDFAM10, and l3Cache() is actually defined as
    l3_cache().
    
    Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a0c6498a40040a0bb72a48a9cf3903f78d41b59
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Mar 19 08:23:50 2010 +0000

    The parameters of memset() should be
    memset(addr, value, size), right?
    It is an obvious bug created at r5201. I am wondering
    why it doesnt trouble you. I took a quick look at other
    files and didnt find other calling error.
    
    Trailing white spaces are also deleted.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 342619526c0e7bd084c6739782e4b332e01fa564
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Mar 19 02:33:40 2010 +0000

    Get rid of a few warnings:
    1. Add some more prototypes to lib.h
    2. Include console.h when not using romcc
    3. Eliminate an unused function
    4. Set a default for SSE2, since it is just for ramtest performance
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 78acf932912669eb0eb7f7280da1b3c550035ebb
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Mar 18 20:58:41 2010 +0000

    Remove remaining uses of
    HAVE_FAILOVER_BOOT
    HAVE_FALLBACK_BOOT
    USE_FAILOVER_IMAGE
    USE_FALLBACK_IMAGE
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2bd91003413d431f0a4db6c3c6691f4b688cf5c5
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Mar 18 16:46:50 2010 +0000

    Rework boolean expression (DeMorgan and all) for
    better readability.
    Also remove failover.c files in mainboards, as they're
    not used anymore (and useless, too)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 776b85ba457ff82f795c6c65b5574ef27e611097
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Mar 18 16:18:58 2010 +0000

    Remove fallback/normal handling in mainboards'
    romstage.c like r5255 did for failover/fallback/normal
    mainboards.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a41b939294c2e90197c57a2faa565bf48d4b506d
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Mar 18 05:57:32 2010 +0000

    trivial. Delelte double blank line.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce6fb1ee2b37193fa828b4c6d475e23c58171346
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Mar 17 22:44:39 2010 +0000

    Remove failover/fallback/normal handling in mainboards'
    romstage.c. That's newconfig stuff.
    
    1. In failover_process(), I removed the fallback/normal selection logic
    and kept the remaining hardware init in. The if-clauses' conditions are
    reverted to match.
    Remove #if failover||fallback guard.
    
    2. Change cache_as_ram_main() to first call failover_process, then
    real_main unconditionally.
    
    3. Move failover_process's code to the beginning of real_main, remove
    failover_process and its call in cache_as_ram_main.
    
    4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same
    arguments, so no problem with that)
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 78b40335841eae958865f67ac8ee0020fd43aead
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 22:09:26 2010 +0000

    more warnings gone...
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 527aedc17bbbc65f665c4d925a72b3e120d9d7ec
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 22:08:51 2010 +0000

    revert the faulty part of r5252
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 07190470053f1e4f937a0d0d100859c452c00fbc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 17:50:48 2010 +0000

    fix HPET on some ICH southbridges
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50776fab1c9062ddfa353ee6c138f69d901c11b7
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 04:40:15 2010 +0000

    trivial warning fixes, mostly for ACPI code
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dfd29aa41347083fbc7a26ca7d639f7f60fe1eea
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 04:38:22 2010 +0000

    drop shadow variable from hypertransport code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cfef7dff9b80b42e2c9373e8c80d8e5ba2bf8d02
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 04:37:52 2010 +0000

    Actually enable HPET
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c486f8f76b2ad526538af14cf5cf74fcf627ba9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 04:04:20 2010 +0000

    Clean up warnings in yabel vbe code. No more warnings on the IP1000
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87489e1ab226d4efc26d1b69dbfec8e16bfca82a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 04:03:22 2010 +0000

    clean up shadow variables in jpeg decoder.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2549d52c045d88518f36d48c44ca7d6777e9f17e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 03:44:45 2010 +0000

    fix minor warnings in RTC code when HAVE_OPTION_TABLE is disabled.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c32d242e475bcc40a92538efc4ac0fa9d21c7af
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 03:40:23 2010 +0000

    bug fix for IOAPIC on i82801dx.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48f3e2b5e1fa75ff9d43485ac9a620255e1048bf
Author: Joseph Smith <joe@settoplinux.org>
Date:   Wed Mar 17 03:37:18 2010 +0000

    This patch fixes up the i82801dx_lpc.c code post transition.
    
    Boot Tested (bootlog attached)
    
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d7a99669545bef76d57d17fd41ab376e061b109
Author: Joseph Smith <joe@settoplinux.org>
Date:   Wed Mar 17 03:18:29 2010 +0000

    This is kind of a pre CAR patch to properly allocate "shared" graphics memory
    area.
    
    CONFIG_GFXUMA is used in src/cpu/x86/mtrr/mtrr.c which is called by the cpu.
    
    Attached is a revised patch which works well.
    
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    See boot snips below:
    
    Root Device assign_resources, bus 0 link: 0
    8MB IGD UMA
    Available memory: 581632KB
    PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
    ----------------------------
    Adding high table area
    Adding UMA memory area
    coreboot memory table:
     0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
     1. 0000000000001000-000000000009ffff: RAM
     2. 0000000000100000-00000000237effff: RAM
     3. 00000000237f0000-00000000237fffff: CONFIGURATION TABLES
     4. 0000000023800000-0000000023ffffff: RESERVED
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd112980ffcc7d9809dff88b7208e804c54345ab
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 03:14:54 2010 +0000

    more warning fixes.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b319b1778c0546d9fc0777ccb9a0b82291b5a60e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 03:14:28 2010 +0000

    fix HPET base addressed.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4e77df5797361db39058f478ee300e9638435f9
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Wed Mar 17 03:10:39 2010 +0000

    The SB600 also has the BootFailTimer. We should disable it,
    otherwise it will keeps reboot. The comment was also added in
    detail to make less confusing when we debug SB600/SB700.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68f542cdf82efe257ee4251047a264558dd8645f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 02:48:24 2010 +0000

    remove more warnings, and fix some boards (watchdog.h)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b48ba6625b4028a12ddf22ec660922a8dc51113a
Author: Keith Hui <buurin@gmail.com>
Date:   Wed Mar 17 02:15:07 2010 +0000

    From Keith Hui:
    
    This patch implements a full SDRAM buffer strength programming algorithm in
    set_dram_buffer_strength(), checked against my P2B-LS factory BIOS. With this
    in place, I now have 133MHz (!) stability with three 256MB PC133 modules, and
    can boot Fedora 11 all the way to the init daemon (actually upstart, but that's
    another story). Not to login prompt yet. We'll find out why later.
    
    This again assumes a 4-DIMM board because that's all I have. I need someone
    with a 3-DIMM board to test it.
    
    As a bonus, there's a big comment block within that illustrates the algorithm.
    :-)
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4ab7c5efbe3e8bc398dd541465bbfc5efe37035
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 02:09:12 2010 +0000

    fix dell s1850, ROMCC didn't seem to like SSE2 memtest here.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 348a1ba589c784f8b15d7179b2d9488c2c31ccb6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 01:51:11 2010 +0000

    fix a couple of warnings
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 37e781706bb079af3c16079892576512680987e6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 01:50:15 2010 +0000

    clean some more files in make clean
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 052fab995d4957f3736137a53888b0e0e7eab770
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 01:22:01 2010 +0000

    remove warnings from cs5530 driver. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9035dd7d8dde1f3173221b4b389dfb4943b63b8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 01:18:14 2010 +0000

    make clean: delete failover.inc and romstage.inc, drop auto.inc (obsolete)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd33c74162c9bd82d72496ef1c32041732becfb8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 17 01:09:58 2010 +0000

    drop unused variable
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9659013f9fdbc2073c466712c01325bc040b38f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Mar 17 00:55:39 2010 +0000

    Source all Kconfig files for IntelÂ® CPU models..
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8483b70ebfc50f91a989ea4ca2d35b794c0802d1
Author: Eric W. Biederman <ebiederm@xmission.com>
Date:   Wed Mar 17 00:23:34 2010 +0000

    Catch non-static arrays in romcc. Not allowed.
    
    Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e96ba2978b622bb605caaeb07600c45516651c2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 16 23:33:29 2010 +0000

    pci drivers should be const.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 859e94a30420c726a0043a00a73abb946cfb94c3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 16 23:07:29 2010 +0000

    it was reason for workaround rules already, and it's somewhat ugly:
    util/x86emu is the only part of coreboot that is linked into coreboot
    itself that lives in util/.
    It's not a utility and it does not really belong where it lives.
    
    ---> svn mv util/x86emu src/devices/oprom
    
    plus necessary Makefile changes to get it building again
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 11b1eb994cedef869618bff5368859d9b3c99b1d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Mar 16 19:23:17 2010 +0000

    Left over strip_quotes definition. Top level Makefile
    already provides this.
    
    Thanks Myles for catching this.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a84e98bd5f7310f6b9995fb0b5713c3b584e05e0
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Mar 16 19:01:32 2010 +0000

    Strip quotes from COREBOOT_ROM_DEPENDENCIES
    Macro-ify stripping quotes
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 182b09e679dc74909740cf5c9a63f78dbe9656b2
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Mar 16 16:59:03 2010 +0000

    Improve dependency tracking for coreboot.rom
    Improve handling of problems while building coreboot.rom
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c5f773d7f4f04e6bde3f23613d53e198da805e56
Author: Patrick Georgi patrick.georgi <Patrick Georgi patrick.georgi@coresystems.de>
Date:   Tue Mar 16 12:01:13 2010 +0000

    Various changes to the buildsystem:
    - Single instance of the CC build rule in Makefile, instantiated as
    necessary
    
    - Remove manual static.o and option_table.o rules, they're now covered
    by those instances of the CC build rule
    
    - Normalize object file paths, so it can be $(obj)/option_table.o
    instead of $(obj)/arch/i386/../../option_table.o now
    
    - Add -pipe to compiler flags. It might be detrimental on rare scenarios
    (building with extremly high disk bandwidth, eg. RAM disk), but it
    significantly helps on win32 (which seems to cache less aggressively
    than most unix-alikes)
    
    - Silence stderr on hostname and domainname invocations (cosmetic fix
    for cygwin)
    
    - Test for -Wa,--divide functionality of the target compiler (taken from
    abuild). It might be possible to remove most patches in crossgcc with that.
    
    - Report build of failover.inc and romstage.inc
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b2831c63c1facee8f5be3962b4cc84a7ebd0f57
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Mar 16 02:02:26 2010 +0000

    Delete Config.lb in new southbridge folders.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f1fe237a2a24ba5421675d64eaddd2b7dc1e353c
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Mar 16 01:59:28 2010 +0000

    Add entries of RS780, SB700, Mahogany, Mahogany_fam10 into the
    Makefile and Kconfig.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 584ab84e92a4db3b96c253bb559d64a8f82cf367
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Mar 16 01:53:10 2010 +0000

    The code can run on the Mahogany board, which is one of sample boards
    made by AMD. Its major features are:
     CPU:
      * AMD AM2+
      * AMD Athlon 64 x2
      * AMD Athlon 64 FX
      * AMD Athlon 64
      * AMD Sempron CPUs
     System Chipset:
      * RS780E
      * SB700
     On Board Chipset:
      * BIOS - SPI
      * Azalia CODEC - Realtek ALC888
      * LPC SuperIO - ITE8718F(GX).
      * LAN - REALTEK 8111C
      * TPM - SLB9635TT1.2
     Main Memory:
      * DDR II * 4 (Max 4GB)
     Expansion Slots:
      * PCI Express X16 slot*2 (PCI-E X8 Bus)
      * PCI Express X4 Slot*1
     Intersil PWM:
      * Controller - Intersil 6323
    
    Note:
    1. The only difference to mahogany is the CPU is changed to K8 family 10.
    2. The main structure of the code is based on
       serengeti_cheetah_fam10. I am a rookie to fam10. I am still
       confused about CONFIG_HT_CHAIN_UNITID_BASE and
       CONFIG_HT_CHAIN_END_UNITID_BASE. I set them as the way dbm690t
       does.  And I have to modify the some fam10 code (see the patch
       ht_chain_unitid_base.patch). I dont know how to solve this. Please
       help.
       Updated findings: In h3finit.c, the code goes the AMD_CB_ManualBUIDSwapList().
       The swaplist is {0x00, 0x00, 0xFF, 0x00, 0xFF}. I am trying to find the meaning
       of the list. The amdht wrapper needs to modify definitely.
    3. With fam10 processor, the HT link can work in HT3.
    4. The ACPI _PSS table is set staticly. The auto configuaration
       process doesnt seem to work correctly.
    5. Currently the fam10 code in coreboot doesn't support DDR3. If you
       happen to get a board with DDR3 and you don't have the patience to wait,
       please find another board with DDR2.
    6. It will take "Uncompressing image to RAM" about 1 minute. I know it is a
       issue for a long time. I disable the compressing currently. When the problem
       is fixed, we can re-enable it.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dec279fa300243bc3c5afe039a5ff6f1fc3264de
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Mar 16 01:42:50 2010 +0000

    1. Features of mahogany.
    The code can run on the Mahogany board, which is one of sample boards
    made by AMD. Its major features are:
     CPU (only K8 system):
      * AMD AM2+
      * AMD Athlon 64 x2
      * AMD Athlon 64 FX
      * AMD Athlon 64
      * AMD Sempron CPUs
     System Chipset:
      * RS780E
      * SB700
     On Board Chipset:
      * BIOS - SPI
      * Azalia CODEC - Realtek ALC888
      * LPC SuperIO - ITE8718F(GX).
      * LAN - REALTEK 8111C
      * TPM - SLB9635TT1.2
     Main Memory:
      * DDR II * 4 (Max 4GB)
     Expansion Slots:
      * PCI Express X16 slot*2 (PCI-E X8 Bus)
      * PCI Express X4 Slot*1
     Intersil PWM:
      * Controller - Intersil 6323
    
    2. The ACPI feature is already added. I suggest that firstly we can test
    the board without the ACPI by setting the HAVE_ACPI_TABLE as 0.
    With Rev F processor, the HT link can only work in HT1, whose max
    frequency is 1GHz.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1088bbff4503df7e8507aae45da823268262ca8f
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Mar 16 01:41:14 2010 +0000

    Features supported in RS780 code:
      * PCIe initialization.
      * Internal Graphics initialization.
      * HT Link initialization. It works in HT1 or HT3 mode.
    
    Note:
    1. I tried to add the description of every step to the code. For example,
       if it is made based on rpr, section 2.4.5, I will pasted the words
       from 2.4.5 to the c code. But the document I worked with might be
       different with the most updated one. A new section has been added and
       the 2.4.5 might be changed to 2.5.5. That migh lead to confusing. I
       correct every comment if I met one. But I have to confess that I am so
       reluctant to find out everyone. I believe it will be correct in the long
       run.
    2. The interanl graphics part is done by Libo Feng <libo.feng@amd.com>.
    3. There is a conflict between RPR and our CIM code. Please see the comment in
       switching_gppsb_configurations in rs780_pcie.c.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eff2ffdee8489f97b265b0335b766be3db9a633a
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Mar 16 01:38:54 2010 +0000

    Features supported in SB700 code:
      * SATA initialization.
      * USB initialization.
      * HDA initialization.
      * LPC initialization.
      * IDE initialization.
      * SMBUS initialization.
    
    Note:
    1. I tried to add the description of every step to the code. For example,
       if it is made based on rpr, section 2.4.5, I will pasted the words
       from 2.4.5 to the c code. But the document I worked with might be
       different with the most updated one. A new section has been added and
       the 2.4.5 might be changed to 2.5.5. That migh lead to confusing. I
       correct every comment if I met one. But I have to confess that I am so
       reluctant to find out everyone. I believe it will be correct in the long
       run.
    2. I only test the SATA port 0-3. The ports 4, 5 are "PATA emulations".
       I am confused about it.
    3. This patch is not only about SB700. Actually it should be
       SB7x0. But I dont think it is nice to change everything to
       SB7x0. It is ugly, isn't it. As far as I know, they all use the
       same code with revision checking. If you guys think it is
       appropriate, please modify it to sb7x0.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8069eb17208c775632c6cf3a4d9e173e899ef047
Author: Zheng Bao zheng.bao <Zheng Bao zheng.bao@amd.com>
Date:   Tue Mar 16 01:36:21 2010 +0000

    1. This patch is about the pci header of RS780 and SB700. It is made
       seperatedly because both RS780 and SB700 will modify the pci_ids.h. It
       maybe will cause conflict if the sequence the patches are applied is
       different with the one they are created.
    2. Dev 0-10 of RS780 has AMD's Vendor ID. So we think it is better to
       define the Device ID as XXX_AMD_RS780_XXX. Does anyone think it is
       better to move this definition to the AMD zone? That will split the
       RS780 into two parts. Is it inappropriate?
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23d89ccfd2444c9784e6a27256012f71f8e609dd
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Mar 16 01:17:19 2010 +0000

    Make CLANG selectable in Kconfig
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68a564f7ac3975de5ce6e6d0f65db63bbe7d2d64
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 16 01:02:18 2010 +0000

    This patch is what I needed to compile coreboot with LLVM.
    
    - call va_* directly if coreboot is running on GCC so we don't need
      to maintain hacks to get to stdarg.h
    - only define LIBGCC_FILE_NAME if it's an absolute path. GCC and LLVM
      just print "libgcc.a" if the file is not there.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6b0e7e2d926f00ebec402f1364c31518c33a051
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 16 00:58:36 2010 +0000

    back out r5212 and r5210; Follow the thread of
    http://www.coreboot.org/pipermail/coreboot/2010-March/056501.html
    for the details.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c0fbbd0416a6c117d69c71d68a2951e1b1885ce1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 15 13:35:19 2010 +0000

    Create a new build.h on every make call; this makes sure it contains a
    valid compiler signature and time stamp. Since we maintain correct build.h
    dependencies in the source code we can also drop "prepare2"
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f4546f7cacd4dfecd2b318e6810dce1f57e45db
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Mar 15 10:32:59 2010 +0000

    Use copy_triple only on non-flattened nodes.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b8d6a866deaa7b21ee25ce78eedd99118d7663a
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Mar 15 10:04:06 2010 +0000

    Add an AM2R2 entry in to the src/arch/i386/Makefile.inc.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f761aef9326ebbb9d2018feaaf3471e2a15f471b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Mar 14 22:20:57 2010 +0000

    Fix segfault of romcc when complex assignment operators
    were applied to non-trivial LHSs, eg.  c[4] |= 1;
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc6692695588efee192a64e1f70bdb343b2b39c5
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Mar 14 21:31:05 2010 +0000

    Move deprecated Kconfig options to their own file,
    so it's clear that they should be gone.
    More can (and should) be added, but this is a start.
    
    Of course, eliminating the uses of the flags (and then
    the flags themselves) that are in Kconfig.deprecated_options
    is a noble task for the future :-)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 020f51fdc0c54c8dcb115de611d48946695b155d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Mar 14 21:25:03 2010 +0000

    Add scan-build support to the build system.
    When configured in Kconfig, just running "make"
    calls scan-build as appropriate (however, it does not
    check for the presence of scan-build)
    
    The target directory for the scan-build report is configurable
    and defaults to the scan-build default of /tmp/scan-build-$date-$num
    
    abuild is adapted to properly run scanbuild when ran
    with the -sb option.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8702ab5ab1ee3e9f4f4d6edd7cec85ed6029aac8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 14 17:01:08 2010 +0000

    ICH4 update, fix ATA init, drop SATA (chipset doesn't have SATA)
    fix some PCI IDs, enable USB bus mastering, add some license headers, ...
    
    LPC code needs another look, but I think we're getting there.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c503927f482cc167ebe245ac6d4a394179ea6e2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Mar 13 22:07:15 2010 +0000

    Fix llshell
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53c7276bd1a18160f022c468b7ce021c5386577c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Mar 13 20:36:11 2010 +0000

    Use CPU_INTEL_SLOT_1 for Slot 1 boards (trivial).
    
    This fixes a longstanding TODO item.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c1e1f0d3a562d6f1fb1a1bad5a8f58f62bf4613
Author: Keith Hui <buurin@gmail.com>
Date:   Sat Mar 13 20:16:48 2010 +0000

    Add SDRAMPWR_4DIMM Kconfig option (not user-visible in menuconfig).
    
    Each Intel 440BX board should select this option if it has 4 DIMM
    slots on the PCB, and _not_ select it (it defaults to 'n') if it
    has 3 DIMMs on the PCB.
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7f9e92b4235169974c8f314ff6a921a0b7c4f9e
Author: Knut Kujat <knuku@gap.upv.es>
Date:   Sat Mar 13 12:54:58 2010 +0000

    Fix supermicro/h8qme_fam10 by enabling SPD ROM properly.
    Also configure GPIOs so the power LED is working.
    Some whitespace cleanups (but by no means comprehensive)
    
    Signed-off-by: Knut Kujat <knuku@gap.upv.es>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f326e3a4fef3081e4baf8f85d5cc63d91e8c7676
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Mar 11 22:12:10 2010 +0000

    Replace spaces with tabs.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed15220b87d298088a074747b24e212c23333e33
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Mar 11 21:34:27 2010 +0000

    Replace clear_memory with memset.
    Replace set_init_ram_access with the call to set_var_mtrr.
    Remove unused #include statments.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc259d09d342f09987c65290422009615a8287a7
Author: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Date:   Wed Mar 10 03:43:05 2010 +0000

    The following patch implements Opteron Fam 10 rev D (aka Istanbul)
    support for coreboot.  I have not updated MAX_CPUS for all fam10
    mainboards, but it might make sense to multiply those by 1.5.
    
    Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
    
    
    I assume the line
    pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
    should be put outside the loop.
    
    Everything seems to be fine. I don't have Istanbul to test. I have
    read every changes and they all look good.
    
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a51021b9a11ab0910fb3fa827c0dd094a89960bb
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Mar 9 21:51:31 2010 +0000

    sb600 has problems with the virtual wire mode setup in setup_ioapic(). It causes problems when interrupts are enabled (specifically timer).
    Previously the sb600 setup was equivalent to clear_ioapic(), so that is what we will do for now.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2140575066d3890a74c2820932af9bf26a7b0adb
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Mar 8 23:44:30 2010 +0000

    Remove Kconfig entries that disable
    WAIT_BEFORE_CPUS_INIT. It's disabled by default
    (see src/cpu/x86/Kconfig)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9b3a0694a8e1d904b77ace63e5992bac01bd4d8
Author: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Date:   Mon Mar 8 23:38:43 2010 +0000

    Set options to make AMD CAR code compile correctly,
    and increase MAX_CPUS to aid support 6-core CPUs.
    
    Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 128ac9149cdd46794a6121280c4c2de4bcd71e4f
Author: Mathias Krause <Mathias.Krause@secunet.com>
Date:   Mon Mar 8 13:08:24 2010 +0000

    Trivial fix, use correct define.
    
    Signed-off-by: Mathias Krause <Mathias.Krause@secunet.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 47d68d8b66841b0f42269691a79f5afdbe3f12e4
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Mar 6 21:18:43 2010 +0000

    More readable recursive descent macro in Makefile
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5195 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59356ca48b620b7be431455fa4c3332bc2a25a24
Author: Keith Hui <buurin@gmail.com>
Date:   Sat Mar 6 18:16:25 2010 +0000

    440BX: Do not hardcode DIMM number + size anymore.
    
    The code currently assumes a 4-DIMM-slots board, this will be fixed soon.
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7b3c5e8524ac4629f5711fa9172259699f36799
Author: Keith Hui <buurin@gmail.com>
Date:   Sat Mar 6 16:19:11 2010 +0000

    Add support for the 0x06B1 CPU ID for Celeron (Tualatin).
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9493bfbda81391fe37c7671d81fb7261e9df0405
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Mar 5 19:12:34 2010 +0000

    Remove redundant run_bios prototype.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b0259117f214a80d1ca945bd1fe05b6b3d9858a9
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Mar 5 18:27:19 2010 +0000

    1. Move run_bios prototype to device.h
    2. Use time.h for get_time() and move tb_freq into functions.c
    3. Move read_io and write_io to io.c and make them static
    4. Make a couple of functions static in interrupt.c
    5. Refactor a cast from char[] to u64 to get rid of potential alignment problems and a warning
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f98ad3ace0852159c6e716a5563a9c3df8cf76f3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 5 18:25:19 2010 +0000

    i945 mini patch:
    - don't skip the reset on S4 violations. Specs ask us to do this so we do it
    - hlt on waiting for reset instead of hot looping.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b4f435281e20c6c71077c2985717d96ca43c8d4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 5 18:03:49 2010 +0000

    Fix creation of coreboot.bootblock when -O2 is specified instead of -Os (4GB image issue).
    
    According to some GCC folks -Os should be considered a buggy and unreliable
    code path, so at least keep -O2 working. coreboot_ram is only 4KB bigger.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec42c2e8ac5a2d390ae16641312fd4421dab8d42
Author: Keith Hui <buurin@gmail.com>
Date:   Fri Mar 5 16:31:41 2010 +0000

    Add support for the ASUS P2B-LS mainboard.
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5188 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e1ec158c0a96c2bd51afa73e1bb74d64701264b0
Author: Keith Hui <buurin@gmail.com>
Date:   Fri Mar 5 16:18:38 2010 +0000

    Add proper Slot 1 CPU support code/infrastructure.
    
    Signed-off-by: Keith Hui <buurin@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae22bcd6d99174994b5ac5e3369e0154bb9678c3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 5 10:20:28 2010 +0000

    This patch fixes two things:
    
    - -m32 is already defined by xcompile if the compiler is a 64bit compiler so
      drop it from the Makefile.
    - allow "obj-.. += foo.o" for util/, too. Otherwise the source files in
      util/x86emu/ put their objects in util/ instead of $(obj)/util
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 01ce601bdb4e664b502e8816a3e13e7b1d275e50
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Mar 5 10:03:50 2010 +0000

    This patch is from 2009-10-20
    
    Convert all DEBUG_SMBUS, DEBUG_SMI, and DEBUG_RAM_SETUP custom and
    local #defines into globally configurable kconfig options (and Options.lb
    options for as long as newconfig still exists) which can be enabled
    by the user in the "Debugging" menu.
    
    The respective menu items only appear if a board is selected where the
    chipset code actually provides such additional DEBUG output.
    
    All three variables default to 0 / off for now.
    
    Also, drop a small chunk of dead/useless code in the
    src/northbridge/via/cn700/raminit.c file, which would otherwise break
    compilation.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    Reworked to still apply to trunk, added X86EMU_DEBUG (and make the x86emu/yabel
    code only work printf instead of a redefined version of printk and
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5fa76e2864fada5a87d210a0b994a55f8a235024
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Mar 1 20:16:38 2010 +0000

    Whitespace changes to make s2912_fam10/ms9652_fam10 more similar.
    
    Also, fix another typo in the ms9652 board name.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d71e771081cb05281217d7f87378e2d0e4f08731
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Mar 1 17:21:15 2010 +0000

    Drop unused doit.sh files (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2bb4acfeccc803a89d908579bc731be5fddbe5e1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Mar 1 17:19:55 2010 +0000

    Various cometic and coding-style fixes (trivial).
    
     - Fix whitespace, alignment, and indentation in a few places.
    
     - Some more consistency fixes in license headers.
    
     - Fix incomplete license header: src/mainboard/msi/ms9652_fam10/devicetree.cb.
    
     - Fix typo for LIMIT_HT_SPEED_1800: s/1.6GHz/1.8GHz/.
    
     - Fix typo in src/mainboard/msi/ms9652_fam10/Kconfig: s/MS-9256/MS-9252/.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9d24c7f202c4ff353a8a97e955ee68ed340a98b1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Mar 1 17:16:06 2010 +0000

    - Simplify stack size determination: MAX_CPUS * STACK_SIZE
    - Check that this doesn't run into vga/oprom/bios area at link time
    - Avoid overly complicated and not well understood hack which avoids that
      area by leaving a hole in the stack area.
    - Adapt technexion/tim5690 to put ramstage at 1MB
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d3b2bbe08c59e36488ca9d04d01ddd61c04504ca
Author: Timothy Pearson <tpearson@raptorengineeringinc.com>
Date:   Mon Mar 1 10:56:51 2010 +0000

    Add msi/ms9652_fam10 board.
    
    Updated Timothy's patch to match recent changes in the tree. It's build tested.
    
    Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 55cf7bcbeb605648ccfa2fdab102506f87388c07
Author: Timothy Pearson <tpearson@raptorengineeringinc.com>
Date:   Mon Mar 1 10:30:08 2010 +0000

    Allow per-board setting of HT clock and width so
    less than optimal PCB designs can still work reliably
    with reduced clock.
    
    Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 72f75b1c8b3a5513e467cea1af745bcbd310e881
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 1 09:09:33 2010 +0000

    Fix YABEL guards; make debugging optional; fix some warnings
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 800379f7aa07ca54898faa2c51e6f41ea5b228df
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 1 08:34:19 2010 +0000

    This patch implements MBI (modular bios interface) support to the i830 chipset.
    This is needed on the IP1000T to get VGA output. The VGA option rom will ask
    through an SMI for hardware specifics (in form of a VBT, video bios table)
    which the SMI handler copies into the VGA option rom.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 75bf053fd65bd962fe7a144eb4956f47d9e43d35
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Mar 1 07:42:02 2010 +0000

    - Add rules that build either 4 or 5 ssdts (only those variants exist in the board now)
    - Change ACPI_SSDTX_NUM to either 4 or 5 for boards that have ssdtX.asl
      files, according to the number of ssdtX.asl there.
    - Remove custom ssdt rules
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 806a29eb1909cc4df0fb4bdb0f25083976c3ea6c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Feb 28 20:56:42 2010 +0000

    Use the romstraps build infrastructure created for "tinybootblock"
    (chipset_bootblock_inc and chipset_bootblock_lds) instead of using
    chipset specific rules for "bigbootblock" in the generic i386 Makefile.
    
    It also adds rules for the romstraps of
    * southbridge/nvidia/ck804
    * southbridge/sis/sis966
    * northbridge/via/vx800
    for the benefit of both image layouts.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43fed9b4ed2fe831ed8c65e28e7593d2fa4902f0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Feb 28 19:40:03 2010 +0000

    disable AP_CODE_IN_CAR. The K8 code has an alternate code path to do the job,
    and it's not working anyways.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c3e8b52d64c95d8e27c187598f6e4e41e596da9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Feb 28 19:12:37 2010 +0000

    use names instead of numbers where possible, also print a better message if no
    keyboard is connected.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c89c4d4602d76e87391ea124aea8e11f2c3eea21
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Feb 28 18:37:38 2010 +0000

    Add attribute((noreturn)) to romcc
    It doesn't do anything, but it allows the same code to be compiled with gcc and
    romcc.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ea7bff22ecaba50eefd817dd74d092120682f1a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Feb 28 18:23:00 2010 +0000

    - Add config flag for boards that have their own fadt.c
      This should eventually go, as fadt seems to be better
      put into the southbridge
    - Add config flag for boards that have get_bus_conf.c
      Might be cleaned out as well, no idea
    - Use flags where appropriate.
    - Move the following rules to src/arch/i386/Makefile.inc:
      - fadt.o
      - dsdt.o
      - acpi_tables.o
      - get_bus_conf.o
    - Rename objs_dsl_template in toplevel Makefile to the more
      appropriate objs_asl_template
    - Remove all Makefiles that are empty now, which includes
      src/mainboard/Makefile.k8_CAR.inc and
      src/mainboard/Makefile.k8_ck804.inc
      and the include statements that used these files.
    - Add workaround to intel/xe7501devkit:
      It uses ACPI in an unusual way: It adds a MADT, but no
      DSDT. As this is highly unusual, I didn't want to add
      explicit support for that scenario (and encourage such
      uses that way), and added a dummy dsdt.asl instead. It
      will be linked to dsdt.o, but not linked into the final
      binary.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 55259bd73ba89ec648d9bfc29aa9583fb089903f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Feb 28 18:13:09 2010 +0000

    assert.h: have the same information on asserts in romcc and non-romcc code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b7fd32c33eb688c1c1c1a74f5015d94edac6b16
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Feb 27 13:11:34 2010 +0000

    Put .config, build/, coreboot-builds (abuild) and
    temporary/backup files to svn:ignore
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 37bdb87fab34f772d17c694d3969fd177c4adf57
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Feb 27 08:39:04 2010 +0000

    - make HAVE_HARD_RESET match what newconfig did
    - introduce BOARD_HAS_HARD_RESET and use it if a board provides
    hard_reset in $(MAINBOARDDIR)/reset.c, instead of some chipset component
    - move a couple of rules out of the mainboards' Makefiles into
    src/arch/i386/Makefile.inc:
    	initobj-y += crt0.o
    	obj-y += mainboard.o
    	obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
    	obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
    	obj-$(CONFIG_BOARD_HAS_HARD_RESET) += reset.o
    - remove Makefile.incs that are empty (or comment-only) after these
    changes, incl. Makefile.romccboard.inc (and references to it)
    - Make include not fail if Makefile.inc doesn't exist.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 138be8315b63b0c8955159580d085e7621882b95
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Feb 27 01:50:21 2010 +0000

    This does the following:
    
    cd coreboot/src/southbridge
    svn mv i82801ca i82801cx
    svn mv i82801dbm i82801dx
    svn mv i82801er i82801ex
    svn copy i82801xx i82801bx
    svn mv i82801xx i82801ax
    
    Plus, fixing up the filenames in these directories and the romstage.c and
    Kconfig files of the mainboards using those drivers.
    Plus, switching the thomson ip1000 and rca rm4100 to the i82801dx driver.
    
    There's a lot more to be done, like
    - adding device IDs for the ICH3 and newer drivers that have been kept in
      i82801xx so far
    - drop the additional parts support from the ax and bx drivers.
    
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be07eb29bc087a97903f72c2253442c285ce5942
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Feb 26 20:32:08 2010 +0000

    Work around stack size breakage observed on fam10.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29336512858f84c23720a85e9174d8f0deaff545
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Feb 25 22:48:33 2010 +0000

    drop unused file
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31b0bea940e73583d66435383cceed58e43e477a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Feb 25 21:50:26 2010 +0000

    Move the ldscripts logic to src/arch/i386/Makefile.inc
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e694eda333df2e9a2855d27b0548ec255b9e1a3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Feb 25 18:23:23 2010 +0000

    Drop  i855pm port and rename i855gme to i855 instead.
    This patch also changes the digitallogic/adl855pc to use that port.
    It probably won't work, but at least we will get an error if something
    breaks compilation of the i855 code that is there.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb49f9d04fd19114787c85c173a083574d13fece
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Feb 25 17:03:17 2010 +0000

    Unify crt0s setup to src/arch/i386/Makefile.inc. This variable
    is not something users have to concern themselves with anymore.
    
    Also fixes some wrong romstrap configs for boards, fixing a couple
    of them.
    
    Also add "make printcrt0s" target for debugging crt0s when updating
    modified checkouts.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dbbecb5c17c5dc62f6115cf5ce076d972cc3b702
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Feb 25 16:09:53 2010 +0000

    Various minor fixes (trivial).
    
     - More license header cosmetics.
    
     - New official "Building coreboot" document is now at:
       http://www.coreboot.org/Build_HOWTO
    
     - Drop "(mostly those derived from the Linux kernel)" part of the GPL-v2-only
       parts from the README. Many other files are also GPL-v2-only, too.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 13f2bb09d4befd63f2f2c5307f0e1835eb747732
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Feb 25 13:45:08 2010 +0000

    Make Kconfig more similar to newconfig: enable "HAVE_HIGH_TABLES" per
    default.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7acc515bd10f24d400b3aa3a3c807076cac4f95
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Feb 25 13:40:49 2010 +0000

    HAVE_MOVNTI really means SSE2. Also add sfence in the MOVNTI case.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a54ac9c362d2e5900edd7e1c459ffea1e29df64
Author: Anish K. Patel <anishp@win-ent.com>
Date:   Wed Feb 24 16:36:56 2010 +0000

    Add Win Enterprises' PL6064 board
    
    Signed-off-by: Anish K. Patel <anishp@win-ent.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9fa96d04c85430c7397473b2995f8f4913beb9c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Feb 24 13:58:23 2010 +0000

    Enable user selectable bootblocks, and provide a bootblock that
    selects between "fallback" and "normal", in addition to the
    already present "fallback"-only bootblock.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d3428b071e256f0b09f40ef3d18837749401b6f8
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Feb 24 13:18:01 2010 +0000

    This patch fixes an issue with the wrong build rules being selected.
    Make is free to choose any fitting rule for a target, and so some
    obj-y files were compiled with initobj flags. This patch also fixes
    the behavior for objects being both in initobj and obj.
    
    At the moment all object rules are the same, but if we start not including
    all .c files in romstage.c anymore we need to define __PRE_RAM__ in the
    initobj rule and that's when things start breaking.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a8aa1b1b1387706d5907378a7c75e501c6758816
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Feb 24 13:09:09 2010 +0000

    Remove register pressure from e7501 driver by not indirectly referencing
    0:0.0 through a struct passed all through the code. This behavior makes a lot
    of sense for CPUs with a memory controller built-in. But this is not the case
    for the e7501.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4801e32f9700ce6431a22e12b784b8f561fd0e90
Author: Knut Kujat <knuku@gap.upv.es>
Date:   Wed Feb 24 08:48:35 2010 +0000

    Several fixes to the supermicro/h8qme_fam10 board, so it
    builds and boots correctly.
    
    Signed-off-by: Knut Kujat <knuku@gap.upv.es>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d1fc066697ea3d06cc2cb77de5d653b9b79e932d
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Feb 23 21:43:42 2010 +0000

    Clobber registers as appropriate in AMD CAR code, and
    build a better barrier for gcc to reflush all registers
    when moving the stack.  memcpy was taken from Linux.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 740b587baa749f89361e53e05e2f629e6941e378
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Feb 23 20:31:37 2010 +0000

    Remove nonsensical wrapper for function in
    PS/2 keyboard API.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c1d9a034a190277c6c9bfd5f262df8cad46b01e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Feb 23 19:38:44 2010 +0000

    - Remove src/arch/i386/init/ldscript_cbfs.lb as it's not used anymore
    - Remove _lrom and _elrom, as they're only set but never used
    - Make bootblock size dynamic in the tiny bootblock case.
      It's 0.5-3K instead of 64K now.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8dc4b933b180edd850b8a778fb9593fc17340827
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Feb 23 16:54:20 2010 +0000

    Only handle code as "driver" that actually uses our driver
    infrastructure (special linking, data structures, etc)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7bc3f369df30d0a2606d95fe59e8f757b3d791b
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Feb 23 10:33:25 2010 +0000

    Find out the svnversion we are working on is quite important.
    The whole command (which also parses git data, if it's a git-svn tree)
    is copied from original newconfig.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 326c1591285da7d629cc3eca5d30db0476e8dde1
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Feb 23 10:22:37 2010 +0000

    Disable ACPI Resume on asus/m2v-mx_se, it's broken
    since cbmem
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 040553f262bb34f6a51362e1f1fcad3fa91bfe9a
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Tue Feb 23 10:18:43 2010 +0000

    Adjust msi/ms7135 DCACHE_RAM_* config to previous 32KiB values,
    4KiB is not enough to work.
    
    Additionally, modify the device tree so that the undocumented LDN 6
    is ignored by the resource allocator, and while here, assign the
    parallel port DRQ, hardware monitor IRQ and drop NIC MAC address
    on SMBus EEPROM hint, the ms7135 doesn't have such hardware.
    
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 548dbe7bc88e60a4d1750de835532b84d7cdde96
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Feb 22 16:41:49 2010 +0000

    Random cosmetic fixes (trivial).
    
     - Fix typos.
     - Whitespace and consistency fixes.
     - Make "menuconfig" help easily readable in 80x25 terminals / xterms.
     - Use full/correct prototype for cbfs_and_run_core() everywhere.
     - More cosmetic fixes in license headers.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 92b85aa71f50ea23c909e4fcf674de1780fb1c50
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 22 14:55:16 2010 +0000

    Fix SMM handler comment. Thanks for noticing, Peter!
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f6fbfafbba2ed8b6ea87f19d485ddd53e75b6c6a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Feb 22 12:58:01 2010 +0000

    - Make walkcbfs capable of loading files other than the first
    - Look more closely for files, which should make the code robust
      against defective CBFS images, as long as the bootblock is usable.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 44ca39f0743c277a705aa7746e8646f2df979612
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Feb 22 11:27:33 2010 +0000

    drop empty x86emu Makefile
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 04844816ac177254ce4128c1411041329050ac31
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 22 11:26:06 2010 +0000

    Inteltool: Add i830/Tolapai/Ich4 support
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 881a553000d001bc62085d3055c8e19075e898e2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 22 09:32:33 2010 +0000

    mini update SMM:
    - allow northbridge and cpu handlers, too
    - support for older rev 2 cpus
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6363050c3f9c450417bcb860b878891adc0f42bd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 22 09:28:15 2010 +0000

    drop two warnings (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c834c79216c51e50ad5aeef8a925b9454e136597
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 22 09:27:26 2010 +0000

    CONFIG_ was missing.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a7d34bdc7f681e0a6f8ec2413976a926a8bfcf1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 22 09:15:13 2010 +0000

    fix builds...
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 159b01213202f33e661f9125287b2b3056019dbf
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 22 07:28:06 2010 +0000

    don't call verify_copy_pirq_routing_table() if it's not there.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit de3206a7bebce99f11e753164cc4d46357bba96a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 22 06:09:43 2010 +0000

    This is a general cleanup patch
    - drop include/part and move files to include/
    - get rid lots of warnings
    - make resource allocator happy with w83627thg
    - trivial cbmem resume fix
    - fix payload and log level settings in abuild
    - fix kontron mptable for virtual wire mode
    - drop some dead includes and dead code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d650e9934ff8da9b9cb69e42e642c0ee6d390bf6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 22 04:33:13 2010 +0000

    YABEL update
    - drop x86emu + old biosemu in favor of YABEL
    - Add YABEL_DIRECTHW to get the old biosemu behavior
    - add support for vesa console using YABEL
    - add coreboot table entry with console information
    - add bootsplash support (reads /bootsplash.jpg from CBFS)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Pattrick Hueper <phueper@hueper.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 30b90fe4f0b31aa6676f507d3913579453942ba8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Feb 21 06:45:43 2010 +0000

    Add Doxyfile to bayou
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4c5c44d276b57ca87aadb22c1f918c4912e264f
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sat Feb 20 09:38:16 2010 +0000

    trival. All the changes is about comment and spaces.
    
    1. Delete trailing white spaces.
    2. Change the // comment to /* */.
    3. Add some copyright header.
    4. reindent.
    5. delete multi blank lines.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c970eee2a0a388374e672d7fd80b12fe0382abc
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Feb 19 19:59:03 2010 +0000

    Revert deletion of src/arch/i386/init.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e9234ffff5730df6a498fae6cfaf5c0ee101c5b
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Feb 19 19:08:11 2010 +0000

    1. Change CONFIG_DEBUG to DEBUG in util/x86emu/*
    2. Make DEBUG depend on CONFIG_YABEL_DEBUG_FLAGS being nonzero
    
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99f75793c1efbce8e0cde24d811ed1789a257604
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Feb 16 00:06:42 2010 +0000

    fix APCI typos.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 30a4a936cb99dbed9206ca49ae39e897497274b9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 15 23:27:48 2010 +0000

    fix clock polling in pc97317 driver.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0dd63a26a24b3503c6082a99fba3814a3cc4a92a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Feb 15 23:24:51 2010 +0000

    Document the reason for r5124 in the code/Makefile (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c70e9fc2337519fc8ef6faca5bccb0e92e68675d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Feb 15 23:10:19 2010 +0000

    Various license header consistency fixes (trivial).
    
     - Consistently use the same wording and formatting for all license headers.
    
     - Remove useless whitespace, add missing whitespace, fix indentation.
    
     - Add missing "This file is part of the coreboot project." where needed.
    
     - Change "(C) Copyright John Doe" to "Copyright (C) John Doe" for consistency.
    
     - Add some missing "(C)" strings and copyright years where needed.
    
     - Move random comments and file descriptions out of the license header.
       - Drop incorrect file descriptions completely (e.g. lpc47m10x/Makefile.inc).
    
    There should be no changes in _content_ of the license headers, if you spot
    such changes that's a bug, please report!
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d37d2221843004c56c116dfbea4a47a955f76a85
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Feb 14 16:17:55 2010 +0000

    Add missing Copyright line, sorry.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 13df640bf7a9b7e402fd4d3082415ab65ef45057
Author: Anish K Patel <anishp@win-ent.com>
Date:   Sun Feb 14 16:13:03 2010 +0000

    Add w83627hf_set_clksel_48() function which sets CLKSEL to 48MHz.
    
    The Win Ent platforms are using the Winbond W83627HG part, but this part does
    not appear to enable 48MHz clock by default as claimed in the datasheet.
    
    Signed-off-by: Anish K Patel <anishp@win-ent.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 516255e6330873470590c843f569a31e52508c00
Author: Marc Jones <marcj303@gmail.com>
Date:   Sat Feb 13 18:06:29 2010 +0000

    I was having problems building a working romcc with the -O2
    optimization flag on ubuntu hardy. It was causing this error building
    the bootblock:
    bootblock.c:49.0:
    Internal compiler error: low: next != prev?
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 01708ca504e02450cf4c504e808534177d79d56b
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Feb 12 21:28:15 2010 +0000

    romcc: Fix a few (harmless) warnings
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ae11632ed03575d5d2b2d97cd0da5e8a4e4c3a8
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri Feb 12 17:58:53 2010 +0000

    This patch allows a Kconfig option to choose between 64MB (IP1000) and 128MB (IP1000T) of onboard memory.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2593d1068153aefaa3f78b567ef5061387665f82
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Feb 12 11:59:37 2010 +0000

    update doxygen config file to latest doxygen version
    (doxygen -u)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a35853c9b251399c5b52dd5a40d0637bab14edb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Feb 12 09:32:17 2010 +0000

    Add two YABEL options to Kconfig
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba295dce8476399ec436688f618076b9abafe6e2
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Feb 11 23:00:10 2010 +0000

    Fix AUTO_XIP_ROM_BASE issues on AMD boards with certain compilers,
    and expose the error earlier in the build.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 535e3b4baa6edc43fb4f7d9ad77854b9eef4c76b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Feb 11 21:51:04 2010 +0000

    Adapt all uses of CONFIG_XIP_ROM_BASE to use
    AUTO_XIP_ROM_BASE (as implemented for tinybootblock) if available.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97fc40b6b1356102190e8f0e700707497e156f11
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Feb 11 12:12:19 2010 +0000

    Don't remove config.h on "make clean"
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 78fbb514fc35ec8df761125ba7fd00773eb2842a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Feb 11 11:13:32 2010 +0000

    romcc: Ignore empty string tokens. So far, romcc emitted a single double-quote for them.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 184761864dcf515973bd514e8c35a5f06568f245
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Feb 11 08:44:20 2010 +0000

    $(DISTRO_CFLAGS) is newconfig heritage and was never used on Kconfig. We do
    what it was supposed to do in xcompile now..
    
    Moved ap_romstage.o rule to src/arch/i386/Makefile.inc, too.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b4d3af8888f261abb1f45ca42503f7170bdb3470
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Feb 11 03:21:29 2010 +0000

    separate build.h and config.h usage (now possible because newconfig is gone)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    This patch is slightly reworked to include a necessary romcc change that allows
    more than one -include specified on the command line, and gets rid of the
    explicit build.h dependencies of all files. (The files do keep an explicit
    config.h dependency though)
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e82f4754ee905437d434f0d58c03e9ee2929224e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Feb 10 20:31:38 2010 +0000

    Improve compiler detection and configuration in xcompile.
    Move -fno-stack-protector support from Makefile to xcompile.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 942a40da3ae2688ab9303d54d8b0fffdd98002b7
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Feb 10 19:52:35 2010 +0000

    Do not print the full path name to coreboot.rom in "cbfstool print" (trivial).
    
    This makes the output look a lot nicer, e.g.
    
      /home/uwe/foo/bar/baz/whatever/build/coreboot.rom: 256 kB, bootblocksize 65536, romsize 262144, offset 0x0
    
    now becomes:
    
      coreboot.rom: 256 kB, bootblocksize 65536, romsize 262144, offset 0x0
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a432abf17a0b4152e6190624f2adfdd7cbfc444
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Feb 10 19:40:10 2010 +0000

    Forgot a CBFS_PREFIX change in appropriate commit (r5102).
    Also, delete duplicate romstage file in qemu-x86
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a47b5e5dceaa9bc1d63b48daafdc7f25e8c0835
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Feb 10 18:53:40 2010 +0000

    Remove uses of the shell to remove double quotes, or to figure out the
    current directory (already available in $(PWD))
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7faf22fbbb31fdb85be6d6efa248fe1148baafd4
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Feb 10 18:50:36 2010 +0000

    Handle potential race condition with $(obj)/util/cbfstool
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68882a33220e802ef38d562ea1c96fd5fb779e49
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Feb 10 18:08:22 2010 +0000

    Remove two perl calls with sed, and adds an alternative
    for another two (using GNU date, and with limited impact if both
    alternatives fail)
    
    Those were the remaining perl calls in our build tree, so remove perl
    from our dependency list in README.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1bbad5c66b639a6459962b4e73ceddfae068e9ee
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Feb 10 15:36:53 2010 +0000

    fix doxyfile path
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94f5f70745490c4b8ce988d204cbc2eea1faa333
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Feb 10 15:34:15 2010 +0000

    python is no longer used in abuild.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 531704ed71c48a41fba23948fe8f9104c5e1f470
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Feb 10 11:56:21 2010 +0000

    Drop src/config alltogether
    
    - drop two "newconfig" based files
    - drop two obsolete doxygen config files and check
      in our latest Doxyfile.coreboot (that has been
      used to build coreboot online documentation since
      2005 or so)
    - move two i386 specific linker scripts to src/arch/i386
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f60a2567d2428360b855e12618d85d3b516d5c77
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Feb 9 20:02:32 2010 +0000

    Emergency fix: r5102 carried some local change that doesn't
    belong in this patch, which makes tinybootblock builds fail.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 967952a102f13825085fdab6e37738d437eca655
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Feb 9 19:41:11 2010 +0000

    Add image updating support. When selecting it, it
    expects a coreboot.rom to be available, and adds the files to it.
    
    It has no idea how to replace files, it merely adds them. It only works
    with Tinybootblock and the bootblock is immutable.
    
    The "clean" rules allow "make clean-for-update", which
    removes everything but coreboot.rom
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b8a24193512c8889c532e56df7e706c79dec447
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Feb 9 19:35:16 2010 +0000

    Allow building images with different prefixes (ie. normal/romstage,
    helloWorld/romstage, ...).
    It defaults to fallback/, so there's no user visible change now.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f64b42ed7a0ec95e275b78e6a6c453aa523d9ee0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Feb 9 15:15:29 2010 +0000

    I took Rob Landley's nice "menuconfig2html.py" script from
    http://landley.net/hg/kdocs and modified it to produce MediaWiki output
    for coreboot's Option List at http://coreboot.org/Coreboot_Options. The
    attached patch exchanges our old ("newconfig") optionlist script with
    the new one.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5543c66cca1907895576096b28effb2866ed3e2c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Feb 9 12:32:55 2010 +0000

    Actually set HAVE_OPTION_TABLES for the boards that need it.
    (See last commit)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2063197a4f610898c6e258e9fbd58b0bc92c7e85
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Feb 9 12:21:10 2010 +0000

    Move all the copies of the romstage.inc rule to
    src/arch/i386/Makefile.inc
    
    For that to work, I had to:
    - Add a CONFIG_ROMCC variable
    - Set that variable on all ROMCC boards
    - conditionally choose romcc or gcc rule based on that variable
    - remove those two rules from all the boards' Makefiles
    - switch a couple of boards to HAVE_OPTION_TABLE, as they actually have.
    
    Also remove the duplication of rules with the sole difference of if
    they depend on option_table.h or not.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e4119ccff8d213c0592fe7a1884e5b2604928f7b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Feb 9 12:00:06 2010 +0000

    The COM2 enable code is global now. Use global API and
    retire duplicate function.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e30db0e37034f6698eced00727b6ad0ba3fc5c7b
Author: Edwin Beasant <edwin_beasant@virtensys.com>
Date:   Tue Feb 9 10:22:33 2010 +0000

    Port of CS5536 early UART setup from v3.
    Permit early setup of COM2
    
    Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 37d8c215a27f3c7938e921ccb849a9b8fa01be77
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 8 18:30:41 2010 +0000

    update coreboot trunk version
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9f5f877098f6cd7bcd3e1302c1ba9aebc679d69
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 8 17:04:04 2010 +0000

    get rid of old news.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af97d33ec426b9414133fd82d958cf9ab52a390f
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Feb 8 15:46:37 2010 +0000

    Clean up ACPI:
    - unify all iasl related rules into the toplevel Makefile
    - build a filesystem standard for ACPI files and use it
    - pass ACPI sources through cpp, so constants can be shared
      between C and ACPI more easily
    - use cpp's #include instead of ACPI's Include() so cpp gets
      the whole picture
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e92974904703272b55d66dc4959d95adba6f30c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 8 12:32:30 2010 +0000

    straighten naming scheme for application processor rom stage files.
    Apparently they are not used. If you have any of the boards touched in this
    commit, please test and report (so we can figure out what to do with the
    ap_romstage.c files in general)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 38f147ed3d9fdd6bfb23d7226f6fdd3fc5db53d0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Feb 8 12:20:50 2010 +0000

    janitor task: unify and cleanup naming.
    cache_as_ram_auto.c and auto.c are both called "romstage.c" now.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d51eddbb6611965165ad72eb3fb04377a51ab64a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Feb 7 22:56:06 2010 +0000

    fix further build.h dependencies that were undetected before we enabled it on
    our parallel build server ;-)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bfff67db7d7781a685827e25e3779b1deac0af60
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Feb 7 22:27:49 2010 +0000

    romcc _also_ has to wait for build.h to be generated.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abf2ad716daff751d75907d47bcae4a7044fd7b4
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Feb 7 21:43:48 2010 +0000

    newconfig is no more.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 389240f288b2708617a35ebe8d7f89b3bff316c5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Feb 5 16:10:01 2010 +0000

    this should get the VIA VT8454c in shape with Kconfig
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b6b192af9fd13e8774757830bea0eb1b2b3f9b45
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Feb 5 14:32:00 2010 +0000

    Add -pipe .. notably speeds up windows builds.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2598214f57c66fbabeba8e6939da597b173e439c
Author: Harald Gutmann <harald.gutmann@gmx.net>
Date:   Thu Feb 4 11:08:59 2010 +0000

    This patch fixes the build for the dsdt.asl/dsdt.c.
    
    Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f14e69bc622e43d11aab8dd78d68e05aef0df3c3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Feb 4 11:05:59 2010 +0000

    typo
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8ab6bd0db3e87948b874ae69bf2163bd1982680
Author: Harald Gutmann <harald.gutmann@gmx.net>
Date:   Thu Feb 4 10:28:16 2010 +0000

    Remove lots of cruft from gigabyte/m57sli's Config.lb
    and fix the build.
    Change the default ROM size to 1MB
    
    Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit de7c6fa5fce39014800a50ef2a2173af44b7c3c1
Author: Ward Vandewege <ward@gnu.org>
Date:   Thu Feb 4 03:03:39 2010 +0000

    Revision 5051 broke Kconfig booting for the Tyan s2881 board. Up to 5050, there
    were two SB_HT_CHAIN_ON_BUS0 sections in the mainboard Kconfig file - one
    setting the parameter to 0, the other setting it to 2.
    
    Revision 5051 removed one of the two SB_HT_CHAIN_ON_BUS0 sections - the wrong
    one. This patch fixes that.
    
    Revision 5051 removed the wrong setting because newconfig for this board was
    *also* wrong. This patch fixes that too.
    
    Tested on real hardware, both with Kconfig and newconfig.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 04d74b1fdd52acfa5d31fa3c5317dd562feac5fa
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Feb 4 01:32:43 2010 +0000

    Move CAR settings for all GX1, GX2, LX and Intel Slot2 boards to the CPU.
    This automatically adds the settings for those boards that didn't have settings
    at all yet. Also, small fixup to compareboard.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    --> Please help porting all boards from newconfig to Kconfig <--
    
    This is a lot of janitor work and we can use your helping hands.
    The sooner we can get rid of Kbuild, the better. The KBuild report
    on the mailing list shows the config differences between newconfig
    and Kconfig. In theory, all Kconfig configs should be equal to their
    newconfig pendant. In practice it's better to come close but stay
    clean.
    
    --> Please help porting all boards from newconfig to Kconfig <--
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52da560bf653748a468a9062a8d76bbc1e8672b2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Feb 4 00:55:06 2010 +0000

    Add dump support for the Winbond W83877AF (trivial).
    
    This Super I/O doesn't seem to know the concept of LDNs, it's just a
    bunch of registers not splitted into banks/LDNs.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d0d7c0158d71b0fc8a358d768bc6a531a6931d71
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Feb 3 22:07:57 2010 +0000

    Supermicro H8QME-2+ (Fam10) whitespace fixes (trivial).
    
    This makes the code more similar to the h8dmr_fam10 target in order to make
    the diff between both smaller and more readable.
    
    Build-tested with newconfig and kconfig.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3fb8c6637e4dc6bfa006c326cec3013d7f469c89
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Feb 3 20:52:14 2010 +0000

    Add missing CONFIG_ prefix to make manual QEMU build work (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f657bfce3bd9b854262647b03795c39e28a7842c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Feb 3 17:57:55 2010 +0000

    Trivial: In QEmu, the fallback image should USE_FALLBACK_IMAGE.
    (fixed buildtarget)
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a6c337dec0837135949cc3927a77b07290e1d2cb
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Feb 3 17:56:37 2010 +0000

    Guards against errors that are hard to track down:
    - if crt0s is empty (eg. because crt0-y is still used),
      break the build, and say where that behaviour changed
    - if a stage is unusable for cbfstool because it's placed
      outside the ROM space (linked to 0 is somewhat notorious),
      warn about it, give some hints and exit instead of crashing.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stefan.reinauer@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f1b6f1f2bb723d7b7e8e59e95da9ea8ccd146053
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Feb 3 17:25:34 2010 +0000

    Fix incorrect board names in Kconfig strings (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 081c8978acd5f4ad9dfb79cc8e7eafb01695cf88
Author: Knut Kujat <knuku@gap.upv.es>
Date:   Wed Feb 3 16:04:40 2010 +0000

    This patch adds the Supermicro H8QME-2+ (fam10) Motherboard with the
    following remaining issues:
    - ACPI not working
    - SMBus gets irq 0 instead of 5
    - Loading VGA rom fails (using seabios to do it)
    
    (copied a newer Makefile.inc from h8dmr_fam10 vs. the patch on the list)
    
    Signed-off-by: Knut Kujat <knuku@gap.upv.es>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a559d4386b4f659bfeddffa8f38670e24a35ac0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Feb 3 13:49:24 2010 +0000

    The UART2 on the AMD cs5536 is incorrectly configured in two places.
    GPIO lines 4 and 3 are swapped and also incorrectly put in IR mode receive (compound fault).
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Edwin Beasant <edwin_beasant@virtensys.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa742da56be11090fc713c21bc3faf786d99b135
Author: Joseph Smith <joe@settoplinux.org>
Date:   Mon Feb 1 22:51:18 2010 +0000

    Alot of it is trivial clean ups and 830 is now able to initialize one row/side of memory at a time.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14be4d0d521826c0917ff7a42c6c847be5cec85a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 31 21:46:12 2010 +0000

    - Improve help texts for option ROM initialization methods
    - disallow REAL_MODE method if ARCH_X86 is not set.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 15b03541076acf1fd01dffc81cc50602c80eb351
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 31 20:51:00 2010 +0000

    compareboard:
    - drop all occurences of LOGLEVEL settings.
    - drop CONFIG_CPU_[VIA|INTEL|AMD] because they're Kconfig only.
    - re-enable CONFIG_IOAPIC for now, it might need some fixing.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 588d1660915d6a4883431f47ff5f6bb105402d48
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jan 31 18:48:34 2010 +0000

    Add detection support for the Winbond W83877AF (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f0074e6b63b056a40589f23f8347e4a3bf6e88b
Author: Joseph Smith <joe@settoplinux.org>
Date:   Sat Jan 30 14:56:15 2010 +0000

    Trivial fixup on IP1000 and RM4100 copyright entries.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8a89da2130a934e61019973c1e2476adf70ce8b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 30 10:58:30 2010 +0000

    These lines slipped in. Sorry for the inconvenience.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c2ef1463b69482dab43f53bf5e9307e5f04dd11f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 30 10:50:57 2010 +0000

    ifeq wants a space before the (
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68003b8d14526e76709068569a1f207eeb69941a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 30 10:44:28 2010 +0000

    add Kbuild support to abuild and enable it per default;
    use -o/--oldconfig to get the old behavior (and use that
    option in kbuildall to get the old config)
    
    I changed the qa.coreboot.org autobuild system to use -o
    for now so we get build reports from the old and new config,
    still.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e37785791ae2be959cfe07962944745c81ca88f5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 30 09:47:18 2010 +0000

    * fix crt0s/ldscripts paths to fix out of tree build.
    * fix iasl output directory for i945 boards (patch
      for moving it to the mainboard directory will follow)
    * coreboot_table.c: lb_mainboard can be static
    * coreboot_table.c: dump memory table in debug and spew mode
    * fix a warning in bootblock.c
    * don't include arch/i386/init in arch/i386/Makefile.inc
    * announce generation of crt0_includes.h
    * allow overriding $(obj)
    * drop unused src_types from Makefile
    * correctly use hostname -s instead of hostname for COMPILE_HOST
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 89e45773a977da2c996221b74aef06596d345211
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri Jan 29 19:15:10 2010 +0000

    RCA RM4100 and Thomson IP1000 auto.c rework.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6bba29f84a725c67f548290bb3a9832c793797cc
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Jan 29 17:40:52 2010 +0000

    Add the BSD-licensed getopt tool to crossgcc, to use
    if there's no native getopt around.
    
    Use $PATCH instead of the hardcoded "patch" for patching
    files (after we already looked it up)
    
    Ignore various temporary files via svn:ignore
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cccbb898e2568178ea251b9c19242809a79efc62
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Jan 29 17:38:57 2010 +0000

    Make $(obj)/build.h an explicit dependency for all
    object files, as it's dragged into the build by
    -include $(obj)/build.h for pretty much everything.
    
    Also, generate build.h atomically.
    
    This fixes parallel build with kconfig on my box.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24ddfd4b7dd521d5acf52fb35f197ecacc86991d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Jan 28 22:25:49 2010 +0000

    Fix manual build of the ASUS A8N-E (trivial).
    
    Without this patch the manual newconfig (not kconfig) build would fail with:
    
      #error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
    
    I tested an image on hardware, it starts booting now, but doesn't fully
    succeed as there are other issues (I'm investigating).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9d5e345c0caa6c41be884e457da901293e13a15
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Jan 27 19:55:01 2010 +0000

    reformat Kconfig file, too.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4355beb893d4f7c8e9cac0c1e972e05229d63418
Author: Edwin Beasant <edwin_beasant@virtensys.com>
Date:   Wed Jan 27 19:20:29 2010 +0000

    Add the MSR writes that are needed to provide VGA legacy routing for the Geode LX
    Add appropriate Kconfig defines to provide 8mb of VGA ram allocation
    Add the Kconfig defines to cover TSC calibration from TIMER2 and UDELAY setup
    Two small warning removals about excessive prototyping.
    
    Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87d0c542b64c417971e375dc762e80298b8c6dc6
Author: Edwin Beasant <edwin_beasant@virtensys.com>
Date:   Wed Jan 27 18:19:33 2010 +0000

    Change memory map of geode lx: 768kb-systop is a
    single range.
    This change allows both seabios and filo to boot
    linux successfully (which was confused before)
    
    Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 47afa44a9f66cb1e8d80b1bc3b7c5aa0f4cd91f0
Author: Edwin Beasant <edwin_beasant@virtensys.com>
Date:   Tue Jan 26 15:34:15 2010 +0000

    Mark c0000-fffff as usable on geode-lx. SeaBIOS needs it.
    a0000-bffff might be usable as well, but it won't hurt to
    keep that range excluded.
    
    Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6d3ff6cdd6f34a4a1d41a2db4ef450067cdc5ea
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 26 14:09:30 2010 +0000

    use stdint types for structures, and don't use pointers
    for fields defined 32bit in the multi processor specification.
    
    Also, fix lots of trivial warnings in the code.
    
    If you ever wondered, why you get odd or wrong mp tables on your x64
    system: It's not because bios vendors neglected mp tables; it's because
    we neglected 64bit systems. ;-)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a9796ed362f0d2b80f6c4e59c94db5d564324ebb
Author: Edwin Beasant <edwin_beasant@virtensys.com>
Date:   Tue Jan 26 11:22:43 2010 +0000

    - Clean up and comment writing of MSRs for cache control (Backport from v3)
    - Invalidate Cache Tags (by means of in-place rewrite of cache data) which allows CAR data to be flushed to RAM
    - Re-enable cache after flush of CAR to RAM
    
    
    Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e8d943f2668ab25d98ed61cd10d68353c4915f4b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Jan 25 15:17:11 2010 +0000

    Fix ACPI build on a couple of boards (now that it's active)
    Fix timer handling on amd/sc520 systems
    Match UDELAY_* configuration of newconfig in Kconfig
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3e4a0b87c84f82d4187ead100666e4d966c1fa45
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jan 25 13:15:17 2010 +0000

    This code was copied from amdk8 and never really made usable.
    It's supposed to be a userspace regression test for ram init, but
    in fact, it doesn't even execute ram init. This was suggested by
    Carl-Daniel on 2009-08-27
    Thus, dropping it.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b962a3c39b9e5d223c8a084084936abbd0c66bf
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Jan 25 10:50:21 2010 +0000

    More Kconfig changes to improve match with newconfig:
    
    DIMM_SUPPORT
    APIC_ID_OFFSET
    ACPI_SSDTX_NUM
    IRQ_SLOT_COUNT
    MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
    	(except msi/ms9185)
    MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
    MEM_TRAIN_SEQ
    HAVE_ACPI_RESUME
    
    Also remove MMX (kconfig specific) and HAVE_MOVNTI and IOAPIC
    (which we deliberately differ in kconfig) from compareboard
    report.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29647d97c5e66484ab5c8b56ede57329ab5410c4
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Jan 25 07:56:01 2010 +0000

    Align several kconfig options to match newconfig:
    
    HT_CHAIN_UNITID_BASE
    HT_CHAIN_END_UNITID_BASE
    SB_HT_CHAIN_ON_BUS0
    SB_HT_CHAIN_UNITID_OFFSET_ONLY
    MAX_CPUS
    MAX_PHYSICAL_CPUS
    ROM_SIZE
    TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
    
    Also hook up asus/p2b-ds
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 480b37f8e9b16efd3b9a91def3d3007241126833
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jan 24 17:29:38 2010 +0000

    Document CONFIG_PCI usage in the README (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ca94910d806ad9caed0e2b9ae976e3eeb96c77d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jan 24 17:15:25 2010 +0000

    Update list of superiotool contributors to r5048 (trivial).
    
    The list is mostly generated by grepping for Signed-off-by in 'svn log'.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 622fb793e543eeb1f66bb60b56d43b6ba1cb3f4c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jan 24 01:47:58 2010 +0000

    Add missing files from the last commit (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb38f3213b6889db9fcdab79086bb860f3a32547
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sun Jan 24 01:40:46 2010 +0000

    Add VIA VT82C686A/VT82C686B detection support to superiotool.
    
    This adds an additional requirement to superiotool: libpci.
    The PCI code is conditional on PCI_SUPPORT. You can set the
    CONFIG_PCI variable in the Makefile to 'no' to disable it.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5142dcd530e27c5a94612a532b2deaf229670223
Author: David Bartley <dtbartle@csclub.uwaterloo.ca>
Date:   Sat Jan 23 21:51:10 2010 +0000

    Add detection support for the Winbond W83667HG Super I/O.
    
    $ sudo ./superiotool
    superiotool r4931
    Found Winbond W83667HG (id=0xa5, rev=0x13) at 0x2e
    
    Details: http://lists.lm-sensors.org/pipermail/lm-sensors/2008-July/023683.html
    
    Signed-off-by: David Bartley <dtbartle@csclub.uwaterloo.ca>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b850eb8e478c6f2ee8526019488e96a6f41c0adb
Author: Anders Juel Jensen <andersjjensen@gmail.com>
Date:   Sat Jan 23 15:50:12 2010 +0000

    Add detection support for ITE IT8510E/TE/G and IT8511E/TE/G.
    
    Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 16f515adfc2a94f37283528c5668d3b1c42ef8dd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jan 20 18:44:30 2010 +0000

    These two files accidently got a wrong license header.
    Clarified with the authors
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 762a230dc0cda0242befd74e282f5d4c0f4f94e4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 19 21:15:37 2010 +0000

    Kontron 986LCD-M MP table:
    When any of the onboard network cards are disabled, the bus numbers change
    and thus PCI devices in the riser wouldn't get their interrupts right if a
    kernel without ACPI support is booted. This patch dynamically creates the
    correct bus numbers for the firewire and riser card entries
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6f2bd0d69d52b3ace287e6c3418109e2ac49957
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 19 21:15:01 2010 +0000

    Add Yabel support (int 15 5fXX callbacks for vga bios) on the kontron 986lcd-m
    so it's possible to use the LCD panel connector. Values are hard coded instead
    of read from CMOS but it's a start.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 775a766462a84385d9be10a3c1fe4799db5811f4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 19 21:14:24 2010 +0000

    dev->rom_address was dropped a while ago which broke yabel. This patch fixes it
    again.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ed1b6d2dc16b25334dff13033843b8c7f125f83
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 19 21:13:44 2010 +0000

    drop COREBOOT_V2 and COREBOOT_V4 define. We're not sharing code with v3
    anymore so this ugly hack is no longer needed.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d5663bac2c6b2cea2f8c5fa4bd972517325af13b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Jan 18 17:30:36 2010 +0000

    Move all IOAPIC selection to southbridges, and remove them
    from mainboards.
    Some adaptations were necessary after the IOAPIC cleanup,
    so this should fix the build.
    
    Fix intel/d945gclf build, which was missing some ACPI component.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e97383b5487cd3ce88830d0a52800b20ef8ba97
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jan 18 15:08:14 2010 +0000

    run preprocessor on DSDT of D945GCLF, otherwise
    smart iasl will segfault.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6acc0a1795e30819b2b153e3680bf8543a1caf2a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jan 18 12:01:10 2010 +0000

    ncurses is only a requirement for make menuconfig, not for Kconfig in general.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 81d5b0ca3061084e12c287ee6992611f2a97a2eb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jan 18 11:10:03 2010 +0000

    add ncurses to list of requirements
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29c0ec10a617da9398a67b00722523c642b7d073
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jan 18 11:09:24 2010 +0000

    get rid of Kconfig warning.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85bb83aeaf2a1ffb02dd4af299f6a65132b2e9a4
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Sun Jan 17 21:59:27 2010 +0000

    msrtool: Fix typo
    
    Trivial!
    
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cba6169515f56e0902650e332ad0eb3c894e8b0b
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jan 17 18:34:00 2010 +0000

    msrtool: Read both MSR values from file in diff mode
    
    Previously, msrtool would assume that MSR values should be compared
    between stored value in file and current value in hardware which msrtool
    was running on. This does not always fit the use case and with this
    change msrtool can now compare two sets of MSR values stored in a file.
    If only one MSR value is stored in the file, msrtool will behave as
    before, and read the second MSR value from hardware.
    
    This change means that msrtool does not always need access to the system
    MSR functions so it can now be run as a regular user when using diff
    mode with both MSR values stored in the file.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34f2907a1b969270e92281849cfdfc43c343799c
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jan 17 18:33:53 2010 +0000

    msrtool: Add endptr to str2msr() showing how many characters were parsed
    
    This also introduces a small change in the user interface for immediate
    mode (-i). Previously, whitespace could separate high and low words in
    an MSR as such:
    
    msrtool -i 4c00000f='f2f100ff 56960004'
    
    That is no longer allowed, a space character now ends the MSR value. Any
    other character can still be used as separator however, so the following
    syntax still works as expected:
    
    msrtool -i 4c00000f=f2f100ff:56960004
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 838c5a5d8019eff857dac21c24a2bca624fa3152
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 17 14:08:17 2010 +0000

    Add support for the Roda RK886EX a.k.a Rocky III+ ruggedised notebook
    
    http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f6eb88adfb8535cdd6c71d5adeed6ca8ed78952d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 17 13:54:08 2010 +0000

    Initial PCIe tuning: Enable Active State Power Management (ASPM)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e73e1975149aea1ac78dced3d9e8b0b7f684113
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 17 13:52:50 2010 +0000

    Add support for the Texas Instruments Cardbus+Firewire bridge TI PCI7420
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f00052afbfffe87a3f0e07bbb5b8453f48ad19f5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 17 13:51:48 2010 +0000

    Add support for Renesas M3885x Embedded Controller
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 55426dfd577a6f7eddb5e4918ad0401537807ae9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 17 13:50:17 2010 +0000

    Add support for the SMSC LPC47n227 SuperI/O chip
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a3d09521370d493c377955db9f1fa8c5dbb55bb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 17 13:49:07 2010 +0000

    ICH7 update
    * change the code to use macros names instead of constants in many places
    * SMI/ACPI: rework power-off code to work with old Linux kernels (2.6.12.x)
    * SMI: Add support for mainboard GPI handler
    * SMI: immediate power-off on power button press, if OSPM is not active
    * Add fix for some USB errata
    * Some register tweaks for mobile systems
    * Enable configure SCI on interrupt 9 correctly.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24b4df5f9904216e1651b087e4e7a57f8d5220f9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 17 13:47:35 2010 +0000

    Support a few more i945 variants. With this framework in place it should
    be possible to support i955 and i975 relatively easy, too.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e6cf7c0d4f1ce7dc5933956e744fa9bf44c7c3bc
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jan 16 18:39:35 2010 +0000

    msrtool: More trivial rearrangement
    
    Rename some variables
    Remove the 'found' variable which turns out not to be needed anyway
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0401bd89b6e7105ca597a221fdbe2a8b75c35296
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 18:31:34 2010 +0000

    coreboot has 13 instances of IOAPIC setup distributed across a lot
    of components. This patch is a rewrite of the generic IOAPIC setup code.
    Additionally it drops the other 12 instances of IOAPIC setup code and
    makes the components use the generic code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9fe4d797a37671a65053add3f7cca27397db0b9b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 17:53:38 2010 +0000

    coreboot used to have two different "APIs" for memory accesses:
    
    read32(unsigned long addr) vs readl(void *addr)
    and
    write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)
    
    read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
    Some unclean implementations then made readl available to __PRE_RAM__ too which
    results in really messy includes and code.
    
    This patch fixes all code to use the read32/write32 variant, so that we can
    remove readl/writel in another patch.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 984e0f3a0c3a82339ef8afcf7f315f377e0c81fc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 17:50:55 2010 +0000

    ectool: Support for dumping EC "index ram"
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 350ca4a94faa4f35b0b63045f9c7132c2801e1b8
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jan 16 17:21:17 2010 +0000

    msrtool: Remove indent by using continue inside for() to avoid an if block
    
    The only actual code change is from
    if (.. >= 1) {
    }
    to
    if (.. < 1)
    	continue
    so this is pretty trivial.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ade16144221b528bad0b971dfe38f3e0a13ef16
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 16:44:20 2010 +0000

    Update reference toolchain to
    
    gcc 4.4.2
    binutils 2.20
    gdb 7.0
    
    and add mingw support.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2da0d5654b1646646161a640791bdab0d27ebb1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 16:39:50 2010 +0000

    Intel D945GCLF: Enable SMI and ACPI in Kconfig, too (it's enabled in newconfig)
    and guard SMI specific parts of the ACPI code.
    (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 38c9965977bd29504a06689ec6b1b39e5aaeca4d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 16:37:27 2010 +0000

    (trivial) cosmetics for i82801gx cmos failover.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 67cd80299057d83790da235c4dc7286298dc6b16
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 16:35:38 2010 +0000

    * drop reset files from 945 mainboards (and use southbridge specific reset)
    * drop debug.c files from 945 mainboards (and share it in the northbridge code)
    * adapt the mainboard and auto.c files for above changes.
    
    Rather trivial
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42944c3989f27b14a66fa7c75a47c820c8d92119
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 14:57:32 2010 +0000

    nvramtool: Consider a string with non-printable characters a "bad value".
    Otherwise nvramtool -a with random cmos contents can mess up your terminal.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12ee934cb398f28a29ceef455c98ff3fa2ad956f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 13:49:03 2010 +0000

    Make internal functions static in speedstep ACPI generation code.
    (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f0ec23028096e9c9c912b947d7382e607502dcf7
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 13:48:20 2010 +0000

    Fix stack base for Atom CPUs, the resume mechanism (cbmem etc) expects this.
    This unifies the base with Core and Core 2 CPUs.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba8b21c37638837a2afbb95c056b9ce6c25366bd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 13:47:07 2010 +0000

    Micro-optimization: movl $0 --> xorl.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68b3c4637a32004c956dd89d01d2288aff2f24d2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 13:42:43 2010 +0000

    new microcode for Intel Core 2(tm) CPUs
    (taken from Intel's Linux microcode release)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2fbbea0f3098405cd695ae09bb1048317be83a74
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jan 16 13:27:39 2010 +0000

    RTC: Don't drop the alpha specific code but get it in shape for our Kconfig scheme.
    (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb333c423ef7532574a30da979d38e17391b8a42
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Fri Jan 15 10:07:05 2010 +0000

    (missing svn add)
    Support for the AMD Geode GX2
    Processors to Msrtool.
    It seems to work as it was tested on a Wyse Winterm S50.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 58a901f6f93c1988066f39cf6ef21c8458e4547c
Author: Nils Jacobs <njacobs8@hetnet.nl>
Date:   Fri Jan 15 10:06:39 2010 +0000

    Support for the AMD Geode GX2
    Processors to Msrtool.
    It seems to work as it was tested on a Wyse Winterm S50.
    
    Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90b96b68e0fedbc1d76e8547cad39c57021d5119
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jan 13 21:00:23 2010 +0000

    indent all of nvramtool to make it fit into coreboot's
    coding style
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 766db7ea09addca79d91436cb7ac06a9bff491a5
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Jan 11 09:05:52 2010 +0000

    Make qemu use the udelay function in src/pc80/udelay_io.c
    instead of the equivalent copy in src/cpu/emulation/qemu-x86/northbridge.c.
    Also, delete the copy.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 07684e6ce7461d329ef442290234b47561961798
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Jan 8 11:26:02 2010 +0000

    - Makefile.romccboard.inc supports tinybootblock romcc boards, too.
    - via/epia-cn is a romcc board, not a CAR board. (Thanks Kevin, for the report)
    - Make emulation/qemu-x86, dell/s1850, via/epia-cn use Makefile.romccboard.inc
    - New flag: BIG_BOOTBLOCK, which is always the inverse of tinybootblock
      Suitable for Makefile.inc rules (foo-$(CONFIG_BIG_BOOTBLOCK) += ...)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f44eb7876b79787f5439767921419af23b8860f1
Author: Maciej Pijanka <maciej.pijanka@gmail.com>
Date:   Thu Jan 7 21:37:18 2010 +0000

    Print (empty) instead of nothing at all for empty
    filename entries (particularily "null" files)
    
    Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7250d9d00e9bfb4a85a43423f37e2e95077a8b1f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Jan 6 17:05:37 2010 +0000

    Move fam10 temp files from build/ to build/northbridge/amd/amdfam10/  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1af297c6eb44a349bad5d0019a7b841081fbea80
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Jan 6 16:59:18 2010 +0000

    Check for installed compilers (remove .xcompile) at make clean, not distclean.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d1135948a0445a80e04c4fb560178b262c874bd
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Jan 6 10:07:31 2010 +0000

    Fix amdht on newer compilers.
    We were lucky with friendly compilers. Now they're assuming too much.
    
    Identified-by: Myles Watson <mylesgw@gmail.com>
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 753169dc251e3f5e71a9f678c93b68c040aebbf0
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Jan 6 09:14:08 2010 +0000

    Kconfig builds all boards now.
    
    This patch also aligns the configuration of a couple of
    boards more closely to what newconfig does.
    
    Also, the romstrap inc/lds files are declared in the
    Makefiles of the southbridges they belong to, instead of
    some global file.
    
    AMD CPUs have their own timer functions, so disable UDELAY_IO
    for them and set HAVE_INIT_TIMER as appropriate, same for
    emulation/qemu-x86.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 95c50c6091cdc700c79da832f61b2a94b3e5c87c
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Jan 5 17:35:44 2010 +0000

    - Let AMD CAR code pick the right XIP area
      for tinybootblock
    - move asus/m2v-mx_se to tinybootblock
    - Add romstrap for via southbridge to tinybootblock-bootblock
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a0c68f864e9095a94c684183deb41f706e0bd1c3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 5 13:03:02 2010 +0000

    * Explicitly add __PRE_RAM__ where it should be added.
    * Don't implicitly add __PRE_RAM__ in romcc.
    
    Fixes intel/xe7501devkit
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f807fd42f4c4d175c2af1357979fdf235f0be9a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Jan 4 20:09:27 2010 +0000

    - Fix UDELAY options and HAVE_INIT_TIMER [kconfig]
      (defaults to UDELAY_IO again, like newconfig)
    - Use UDELAY_TSC on Via C7 [kconfig]
    - Support Tinybootblock on Intel CPUs
    - set XIP location correctly for Tinybootblock on Intel
    - provide correct XIP location in Tinybootblock configuration
    - Make kontron/986lcd-m use Tinybootblock
    - Some kconfig fixes to kontron/986lcd-m [kconfig]
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce56835a5cc2cb762ecba0d672a9d33fbfc2f7fd
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Jan 4 14:36:55 2010 +0000

    - use LAPIC timer if selected (instead of TSC all the time) [kconfig]
    - uncomment commented out intel socket [kconfig]
    - HAVE_MOVNTI is a property of the cpu [kconfig]
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a29fb61ff43403941161a6e3c4b4288aa237512e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 3 15:35:52 2010 +0000

    improve debug output.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1bb68289001f95b49499ac8eb483a7a10e64cc52
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Dec 31 12:56:53 2009 +0000

    romcc:
    - Set __PRE_RAM__ define per default
    - Properly handle ignored (#ifdef'd out) #include lines
    
    amd/serengeti_cheetah_fam10:
    - write ACPI files to $(obj) instead of the top dir (alias $(CURDIR))
    
    tinybootblock:
    - provide a way to define code that should be added to the bootblock,
      to map the entire ROM for use by CBFS
    
    amd/model_fxx, amd/model_10xxx:
    - add CONFIG_SSE
    
    walkcbfs.S:
    - eliminate the use of two registers, to make space for romcc to wiggle
    
    amd/serengeti_cheetah_fam10:
    - use the enable_rom framework. not entirely functional yet
    
    Boot-tested on emulation/qemu-x86
    Build-tested on amd/serengeti_cheetah_fam10
    amd/serengeti_cheetah_fam10 fails in amdht/ somewhere, but builds
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9db833bec394b886ca990965970cdb100b65d9ac
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Dec 28 09:59:44 2009 +0000

    trival. All the changes is about comment and spaces.
    In superio folder.
    
    1. Delete trailing white spaces.
    2. Change the // comment to /* */.
    3. Add some copyright header.
    4. reindent.
    5. delete multi blank lines.
    
    I tried my best to find them. If anything left, please fix it
    or tell me.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f0aa15e7eac54dae8d1710c3a4751c80b61709a
Author: Marc Jones <marcj303@gmail.com>
Date:   Wed Dec 23 22:16:18 2009 +0000

    Fix technexion tim5690 build failure - REALMODE option required for x86.c mainboard function to be built.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a64f888b2741b0c019daec63959a8b020b525254
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Dec 23 19:46:36 2009 +0000

    newconfig compilation failed with
    (.text+0x4989): undefined reference to `vgabios_init'
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c143693c260391918bf1233c59172514bb9bfa21
Author: Libra Li <libra.li@technexion.com>
Date:   Wed Dec 23 19:16:47 2009 +0000

    Add mainboard x86emu interrupt function support. Add tim5690 VGA BIOS functions: int15 getting LCD panel ID.
    
    Signed-off-by: Libra Li <libra.li@technexion.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9341acda13aa2e8d8df4f04f80c14ace52f9aa27
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Dec 23 12:52:56 2009 +0000

    Tiny Bootblock, step 1/n.
    
    Introduce the tiny bootblock infrastructure and use it on QEmu.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 336daa76faa6255cf487100a9741c740802bb32f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Dec 21 15:09:01 2009 +0000

    make strcmp happy by including string.h (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 467b12acab5be2b394093d25d8972f0bf971b110
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Dec 21 13:50:37 2009 +0000

    Allow user to specify the size of a newly created cbfs image
    to be stated in kilobytes or megabytes. Usage is
    cbfstool coreboot.rom create 1048576 coreboot.bootblock
    cbfstool coreboot.rom create 1024k coreboot.bootblock
    cbfstool coreboot.rom create 1m coreboot.bootblock
    to get an 1048576 bytes = 1024kb = 1mb image.
    
    Kconfig also uses this instead of calculating bytes from kilobytes itself.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a27fc558d8ae47abe74d5a958b7a8b81797a3e7
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Dec 21 12:32:29 2009 +0000

    Make coreboot load VSA from CBFS on amd/gx2.
    
    You have to convert the VSA bios image to ELF using the following
    commands (assuming i386/32bit binutils, if in doubt, use crossgcc's
    i386-elf-* tools):
    
    objcopy --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 vsa.binary vsa.o
    ld -e 0x60020 --section-start .data=0x60000 vsa.o -o vsa.elf
    
    Then, after build, use
    cbfstool coreboot.rom add-stage vsa.elf vsa l
    to add it to the image.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eecaba8b6cfdab1b082e84e3bdfc56a96268cb4e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Dec 18 16:43:30 2009 +0000

    Clean up amd/dbm690t and kontron/986lcd-m some more (not
    fully). Also fix the kconfig build for HAVE_ACPI_RESUME.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3662fcd2c741ce40e53da6b5fcb900cf5f080a8
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Dec 18 15:29:23 2009 +0000

    CONFIG_K8_MEM_BANK_B_ONLY and CONFIG_PCIE_CONFIGSPACE_HOLE aren't used _anywhere_, so drop
    them from view (they could be dropped from newconfig, too - but why bother?)
    
    trivial
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99cf3499b0cef4077bc9c0e0db4b6771656efbdf
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Dec 18 13:36:43 2009 +0000

    Filter out some more K8/Fam10 specific options on unrelated boards.
    Trivial.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50b5b2b4ee7e75c5a01bbb9cd03fd51b765f2d22
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Dec 18 10:20:15 2009 +0000

    - speed up board comparison by only building abuild configs, not the whole
      target.
    - use a template for mktemp (fixes OSX error)
    - convert all numbers to hex to make comparison easier.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a4d90078a60b717cd64250c3c8f5f189c0034c6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Dec 17 18:47:50 2009 +0000

    Make "KBuild report" a bit happier
    - drop some unused options from "newconfig"
    - filter some Kconfig only options from the report
    - drop targets directory of a non existent mainboard.
    
    (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48ca7b2d083a22f92482055cf2a8d698e2caf435
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Dec 17 09:42:30 2009 +0000

    minor bug in the cbfs documentation (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ee55f804105c496793e735061ee26cda80e52204
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed Dec 16 19:48:45 2009 +0000

    Make sure that the h8dmr_fam10 has the proper version string.
    
    This is a trivial patch.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8fddb24abb3db6c312c16917e05c2d8730d54da6
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Dec 14 21:52:56 2009 +0000

    The drivers for the k8t890 weren't being built. Increased heapsize.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85e6870098eb4b64556e8451d61d7a627c0b6271
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Dec 13 13:39:01 2009 +0000

    crossgcc: Fix MPFR download location
    
    We want to download a specific version so fetch it from the right directory.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b66fb79d56feeb7cdcf5123cca7609fa2b3a8103
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Dec 10 17:38:30 2009 +0000

    Push VSA into CBFS for amd/lx systems. It's not hooked up to
    the build system yet, so some additional steps are necessary.
    It's not that bad, given that the code didn't work before.
    
    You have to convert the VSA bios image to ELF using the following
    commands (assuming i386/32bit binutils, if in doubt, use crossgcc's
    i386-elf-* tools):
    
    objcopy --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 vsa.binary vsa.o
    ld -e 0x60020 --section-start .data=0x60000 vsa.o -o vsa.elf
    
    Then, after build, use
    cbfstool coreboot.rom add-stage vsa.elf vsa l
    to add it to the image.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f4aca1da486d06fbb8e2da080558b982e05dfbd8
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Dec 6 12:14:39 2009 +0000

    cbfstool: Fill memory allocated in create_cbfs_file() with 0xff
    
    This should improve programming speed a bit.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a76ebe2a20f2a30dfebd77ffea8d3daf6807505
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Dec 2 21:11:12 2009 +0000

    Trivial fixes for kconfig.  They fix all non-fam10 build failures.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59968f5c81a83ba3a45c9ce26e28ecaa7621b87b
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Dec 2 05:43:50 2009 +0000

    Trivial fix for kconfig socket 441 (typo was 411) so that d945gclf builds.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb097aad6aa31abe1a340aae2b80d4819aab39a6
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Dec 1 18:19:42 2009 +0000

    Eliminate some noise in the output of compareboard on non-K8/Fam10h boards
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f6ee7b719dd5b8858a22b509009b7a47dff8c0c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Dec 1 09:35:19 2009 +0000

    Not all boards cope with automatically sized bootblocks, leading to 4GB
    images due to the "helpful" 4GB rollover behaviour of ld(1).
    
    Back out r4961, something like this should go in eventually, but more
    completely tested and working.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 702a5a57417cd75f29a6ba8c2203170272d987ff
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Dec 1 08:15:38 2009 +0000

    Atom only supports 32bit MTRRs (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 01dd9e1182fc76dc39feffad69bd2a388d13e776
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Dec 1 03:22:16 2009 +0000

    Trivial. SCH4304 and SCH4307 have the same device id.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6085527461408d782558c7e1918232e0f2fa7f07
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Nov 30 23:53:06 2009 +0000

    Add support for the SMSC SCH4304 Super I/O.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d41a3bfc3c20d0218e3b89dd97b5051f4e81263
Author: Maciej Pijanka <maciej.pijanka@gmail.com>
Date:   Sat Nov 28 09:31:30 2009 +0000

    Maciej Pijanka tried to get the Biostar M6TLD running, and created a patch for
    440lx using the 440bx code as a template.
    
    Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f30a222074c3a017fd0fb866c8387aaf0dd6579f
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Nov 28 05:30:57 2009 +0000

    msrtool: Fix simple breakage in r4964
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d80e57c9c8d02181ec53bf2858ca790ee7ce93f8
Author: Andriy Gapon <avg@icyb.net.ua>
Date:   Sat Nov 28 05:21:42 2009 +0000

    msrtool: Add FreeBSD support using /dev/cpuctl ioctl interface
    
    Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7df17af13bc07888ffe47677db3ce9b93c8e4955
Author: Andriy Gapon <avg@icyb.net.ua>
Date:   Sat Nov 28 04:54:33 2009 +0000

    msrtool: Make configure more POSIX sh friendly
    
    Change a few bash-specific constructs to more portable syntax specified by
    POSIX.  After the change the script keeps working with bash interpreter and
    can also be interpreted by FreeBSD /bin/sh.
    
    Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be89c41ae396577e1dd4b685dd6ee255a19df92a
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Nov 28 04:45:34 2009 +0000

    msrtool: Actually do PREFIX substitution in Makefile
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 436f99b72a75e38c4a1558a23642ea838e621745
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Nov 27 16:55:13 2009 +0000

    Eliminate special case id.inc/id.lds in favor of a configuration variable ID_SECTION_OFFSET
    which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative)
    where necessary (if romstraps get in the way).
    For Kconfig, the special case is set per southbridge (as these define the necessity for this
    workaround), for newconfig it's added to each single board.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c58290c2ff3a77ebca00d9d2edbe005d6e950e0f
Author: Maciej Pijanka <maciej.pijanka@gmail.com>
Date:   Fri Nov 27 14:32:17 2009 +0000

    Let ld(1) calculate the required size for code in the bootblock
    automatically.
    
    Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b0f82d9cd3dffb15acf0b80a7d4756c50d6eb295
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Nov 27 11:04:08 2009 +0000

    Really hook up s2850 and s2875. Trivial.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4638c924f0e0ceb150956acead08b97949074e8e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Nov 27 11:03:20 2009 +0000

    Make newconfig and kconfig agree on MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID
    Usually, this means adding values to Kconfig, but in a few cases, adding values
    to newconfig, too (which doesn't hurt).
    
    Also really hook up tyan/s2850 and tyan/s2875 to kconfig, and have them still
    build.
    
    Trivial and stupid kconfig changes, just lots of them.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 13250d13f726b3ecc54ae39deabb7b1e7372918a
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Nov 26 14:03:25 2009 +0000

    Remove commented out example MSR definitions
    
    Now there are definitions for actual MSRs that can be referenced instead.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 226280cdb9f162c05b633136b8d4f93f848ae737
Author: Nathan Williams <nathan@traverse.com.au>
Date:   Thu Nov 26 13:54:40 2009 +0000

    Add the following GeodeLX memory controller MSRs
    
    0x20000018 MC_CF07_DATA
    0x20000019 MC_CF8F_DATA
    0x2000001a MC_CF1017_DATA
    0x2000001b MC_CFPERF_CNT1
    0x2000001c MC_PERFCNT2
    0x2000001d MC_CFCLK_DBUG
    
    Signed-off-by: Nathan Williams <nathan@traverse.com.au>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Nathan Williams <nathan@traverse.com.au>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9276e5eab508b13355e94469e45ef6d7cfa8cfb
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Nov 25 08:35:59 2009 +0000

    Trivial style changes, replace a few C++ type comments, and some code reuse
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e54b4037f6460c9232d1cfcbe4c01a84ae8ea13
Author: Libra Li <libra.li@technexion.com>
Date:   Wed Nov 25 08:14:04 2009 +0000

    This patch is buzzer of TechNexion TIM-5690.
    
    I forgot to svn add the speaker.c and speaker.h.
    
    Signed-off-by: Libra Li <libra.li@technexion.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4cede7176770d8ab810cc6753b3e3a18cd423f34
Author: Libra Li <libra.li@technexion.com>
Date:   Wed Nov 25 07:48:24 2009 +0000

    This patch is buzzer of TechNexion TIM-5690.
    
    Change EARLY_STAGE into __PRE_RAM__.
    
    Signed-off-by: Libra Li <libra.li@technexion.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 46c920e13ac83513897bed1bc27529ff2cdbb436
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Nov 25 02:25:37 2009 +0000

    msrtool: Fix Geode LX probe function, Family/Model were swapped
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26774f2b729d791c9dbf5ba0f7fcf4a59e3795a5
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Nov 21 19:54:02 2009 +0000

    Make the kconfig-style build work in mingw:
    * use relative paths in ldscript.ld and crt0_includes.h
    * avoid use of dd(1) in xcompile
    * build libregex for kconfig, if necessary
    * work around missing utsname on win32
    * unlink targets before rename on win32
    * implement (crude) mkstemp for win32
    * avoid open/read/close, use fopen/fread/fclose instead
    * don't free certain data structures in romcc on win32 to
      avoid crashes (likely use-after-free())
    * handle "\CRLF" and win32 style absolute paths (X:/ or X:\)
      in romcc
    * make lzma (part of cbfstool) build on XP
    * implement ntohl/htonl on win32
    * handle CRLF in awk script
    * set larger stack for romcc on win32
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b198a478ed190552f5228e43bc34391ca7b0f2dd
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Nov 21 06:02:48 2009 +0000

    Add GLCP_SYS_RSTPLL MSR defines for GeodeLX
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Nathan Williams <nathan@traverse.com.au>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 354bde6e0dd09e0ec9d9ba0eaec5e90c0aa8e9dc
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Nov 19 14:25:31 2009 +0000

    Trivial fix for tyan/s2912 to build.  Remove overspecified options in Config.lb.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3aa5f6178a4e19a6731196a450b7d8226459ddab
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Nov 18 17:10:36 2009 +0000

    Update amdk8/util.c since __PRE_RAM__.  Make node & link more unique.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a1e81a56f266179a2e8dee80bdf46ea74608807
Author: Libra Li <libra.li@technexion.com>
Date:   Wed Nov 18 03:47:34 2009 +0000

    This is a patch to control the DIP switch and digital I/O.
    
    Signed-off-by: Libra Li <libra.li@technexion.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae3e9989ed8137ddebad759385d1405817c7b2c7
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Nov 17 15:20:22 2009 +0000

    Silence two warnings.  Only use the Qemu hard-coded address for VGA devices.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61c6aec071e47312aa39f6e0e1edf284f96e7c69
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Nov 17 11:52:18 2009 +0000

    Initialize memory before using it. put_bits wants it that way.
    Trivial.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34b876cfe1a53b251a5d8c3f1e1ba239964a7b2a
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Nov 16 17:29:22 2009 +0000

    msrtool: Add comment with DirectIO URL to the code where it is used.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cafac66d16324eeaf21de93376ad19430e44e613
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Nov 14 19:34:55 2009 +0000

    Fix manual (non-kconfig) build of the following boards, due to
    missing renames of CONFIG_HAVE_PIRQ_TABLE to CONFIG_GENERATE_PIRQ_TABLE:
    
     - iwill/dk8s2
     - iwill/dk8x
     - emulation/qemu-x86
     - iei/juki-511p
     - tyan/s1846
     - msi/ms7135
     - arima/hdama
    
    Build-tested for the QEMU target and IEI JUKI-511P.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5b69883877cea05d95028649616dc63d94eb14d1
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Nov 13 06:43:33 2009 +0000

    Complete the Kconfig of socket_AM2r2.
    This patch is from socket_F_1207, even though the fam10
    can not be "make menuconfig"ed currently.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a3ca4e0e96c8715adefad0584923af8e433ba13
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 12 20:06:32 2009 +0000

    Cosmetics (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d082d512eb8346552ec5187eb1acd1c99fe36c7
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Nov 12 17:46:59 2009 +0000

    Print size of file on cbfs_add_file failure.  The size of the file after
    compression is nice to know.  Trivial
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bdf4157d818f67077863ea510b86b567f8afc41a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Nov 12 17:25:16 2009 +0000

    Adapt ROM_IMAGE_SIZE, too. ROMBASE should probably be defined
    by ROM_IMAGE_SIZE (so ROM_IMAGE_SIZE + ROMBASE - 4GB == 0),
    but that's for another patch.
    
    Should fix the issues created by the bootblock cleanup patch.
    
    Build tested on kontron/986lcd-m, trivial change.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e6727362410294ad39116a3d84d99746565ce05
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Nov 12 16:38:03 2009 +0000

    Add CONFIG_WARNINGS_ARE_ERRORS and set it for qemu.
    
    Remove all remaining warnings from qemu.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9a72600a9fc4b6ed9aeebb7641c9209861c6548
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Nov 12 16:20:04 2009 +0000

    Trivial debug print format string fix for romcc.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d892f1b37f1077b8dffbf844203961ab29c6d06
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Nov 12 13:48:39 2009 +0000

    Get rid of the ugly warning the right way.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 339722e89e7e6462b8fc152c8c49fbdfbcae6606
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Nov 11 23:59:19 2009 +0000

    Revert my too-hasty commit.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4936 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f848137755934d1ec91fb188500881796694d28
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Nov 11 23:32:36 2009 +0000

    Silence an ugly-looking warning.  Two casts were not enough, so just don't cast
    it.  Trust the option_table generator to get the length correct.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6056b97fce79d3534363dcf508ab7b4a18a459d6
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Nov 11 21:32:23 2009 +0000

    Rework bootblock size handling:
    - don't pretend to create a bootblock as large
      as the ROM in Kconfig (it's 64k at most)
    - don't pretend to accept a bootblocksize value
      in cbfstool create (it ignored it)
    - patch up the build systems to keep it working
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c243639797dc480eea9d2b3253e1085096bb355a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Nov 11 19:31:53 2009 +0000

    Help track down enable_rom issues in CBFS. If the magic
    looks like unmapped memory, point to the wiki page with
    more information.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c0ac7e9046b52ae4bd13269a98c12b0172562d5c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Nov 10 22:17:15 2009 +0000

    * Simplify acpi_add_table
    * fix some comments
    * Simplify ACPI wakeup code and make it work without a memory hole
    * Add resume entries to global GDT so we don't need our own for resume.
    * add ECDT description to acpi.h for anyone who might need it  ;-)
    * remove rather stupid math to get the right number of MAX_ACPI_TABLES
      and just define a reasonable maximum for now.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a0141f050bd8ebbecf65b5eba2af0e321e69e4c8
Author: Sean Young <sean@mess.org>
Date:   Mon Nov 9 22:34:17 2009 +0000

    Add detection and dump support for the Winbond WPCD376I.
    
    Signed-off-by: Sean Young <sean@mess.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7f91d9236ccd3428093ff163a2904424935fccec
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Nov 9 17:56:47 2009 +0000

    Enable Multiboot table support (for GRUB2) by default.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Robert Millan <rmh.grub@aybabtu.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0da38dde4b173e43e29435751549809b4b13053d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Nov 9 17:18:02 2009 +0000

    Add a "locate" function cbfstool, which helps you find
    out a suitable address to put a XIP stage to.
    
    Specifically, you pass it the file (to get its filesize), its filename
    (as the header has a variable length that depends on it), and the
    granularity requirement it has to fit in (for XIP).
    The granularity is MTRR-style: when you request 0x10000, cbfstool looks
    for a suitable place in a 64kb-aligned 64kb block.
    
    cbfstool simply prints out a hex value which is the start address of a
    suitably located free memory block. That value can then be used with
    cbfs add-stage to store the file in the ROM image.
    
    It's a two-step operation (instead of being merged into cbfs add-stage)
    because the image must be linked twice: First, with some bogus, but safe
    base address (eg. 0) to figure out the target address (based on file
    size). Then a second time at the target address.
    
    The work flow is:
     - link file
     - cbfstool locate
     - link file again
     - cbfstool add-stage.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 031029d4d4f80c1754ba57d21cda69e4f381850a
Author: Libra Li <libra.li@technexion.com>
Date:   Mon Nov 9 11:53:41 2009 +0000

    These are post codes for TIM-5690 LED debug message.
    
    Signed-off-by: Libra Li <libra.li@technexion.com>
    Added object reference to Config.lb, too and
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d27c08c2898d1d74765a7799628d1c18369fd671
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Nov 6 23:42:26 2009 +0000

    Remove drivers/pci/onboard.  The only purpose was for option ROMs, which are
    now handled more generically using CBFS.
    
    Simplify the option ROM code in device/pci_rom.c, since there are only two ways
    to get a ROM address now (CBFS and the device) and add an exception for qemu.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 547d48ab01049a634dccb16d1847524d5ba93e33
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Nov 6 17:32:32 2009 +0000

    Remove some white space and comment differences from devicetree.cb and Config.lb
    files.
    
    These boards have non-trivial differences:
    gigabyte/m57sli
    kontron/986lcd-m
    dell/s1850
    via/epia-m700
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d63085b20ef40caae1c60a7532b5243e1e30b109
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Nov 6 17:11:05 2009 +0000

    Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.
    
    Since we have CBFS setting rom_address in board files is no longer
    necessary.
    
    Also, drop vga_rom_address from RS690 completely, it was never used
    in the code.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eeec0ef00a6be64d6846599fe7cf81ead22e2f02
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Nov 6 17:09:11 2009 +0000

    Revert the deletion of drivers/pci/onboard that snuck in ahead of its time.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d6d45e3c98e16cbb86915483f771a7bf0e9a633
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Nov 6 17:02:51 2009 +0000

    Split the two usages of __ROMCC__:
    __ROMCC__ now means "Don't use prototypes, since romcc doesn't support them."
    __PRE_RAM__ means "Use simpler versions of functions, and no device tree."
    
    There are probably some places where both are tested, but only one is needed.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 637309d65e6448d34cc92d44f92a93324c154e79
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Nov 6 15:31:49 2009 +0000

    Remove hard coded bus numbers from arima/hdama mptable code and fix warnings.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be10190b7b8f1c85d89af17c5139124cf4c95882
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Nov 5 21:02:35 2009 +0000

    Add debugging utility file for dumping routing registers on K8.
    
    Ported from Ron's code in v3.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb81a5b5fc088ec8503318f12e1e320ef89cf939
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Nov 5 20:06:19 2009 +0000

    Don't try to set fixed resources.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4374f428fff5c11cc26f08e1a0696e6646127998
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Nov 5 18:08:16 2009 +0000

    fix length field in dmi tables. Newer DMI versions through errors
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d18faac7ebb77955fa600a8a432da360ae78130d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Nov 5 18:06:43 2009 +0000

    if x86emu was running for VGA init a corrupted low table RSDP
    is generated in the F segment. Clear the memory before generating an
    RSDP to fix the problem.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4172efc17f4185d1762f6d3d2aa3e1f4b2594499
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Nov 5 17:24:03 2009 +0000

    biosemu (non-yabel) cleanup
    * Drop pcbios folder that only exists for a single function
    * include int1a handler in biosemu.c
    * Wipe a lot of dead code, and set up F segment correctly
    * include return value check from yabel.
    
    On the long run we should teach yabel to be able to run with a reduced feature
    set, ie. no emulation of (almost) all system hardware. Then we could drop the
    non-yabel x86emu.
    But for now this patch cleans up the non-yabel biosemu.c to a state where it's
    not all that ugly anymore..
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 46634e7100f7ab8b2d1a38e671d00fc26b4f3d78
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Nov 5 12:44:50 2009 +0000

    fix Qemu
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 67fed69653a684355edd9c7a13fba24e4f0fdd1a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Nov 5 12:38:34 2009 +0000

    http://www.coreboot.org/pipermail/coreboot/2007-October/025740.html
    
    This function is not called right now,... Please step in and fix up your code,
    folks.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e6ad7fa4a6a8456ed229b4797addb97ceb35d7cc
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Nov 5 10:02:59 2009 +0000

    If the coreboot and filo overlap, it will "slice off" a piece at the
    "beginning" or "end". In the beginning case, a new segment is inserted
    before the current one.  But the ptr will move forward and doesn't
    seem to have any other chance to process the "new" segment.
    
                    ptr ---------+     move --->
                                 |
                                 V
            +--------+       +--------+
            |        |       |        |
            |  new   | <---> |current | <---> .....
            |        |       |        |
            +--------+       +--------+
    
    Now we change the ptr to the previous one and restart the loop. The
    new and current segment will both be processed. Even if the current
    segment is done twice, no new segment will come up and ptr will move
    forward as we expect.
    
          +----------------ptr      move --->
          |
          V
     +--------+        +--------+       +--------+
     |        |        |        |       |        |
     |  prev  | <--->  |  new   | <---> |current | <---> .....
     |        |        |        |       |        |
     +--------+        +--------+       +--------+
    
    It is tested and fixes the crashing on my AMD Family 10 board.
    
    Some trailing whitespaces were deleted.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 448509bb4e93b3ffe870f048c6b4a82b1f2cb9a7
Author: Mark Marshall <mark.marshall@csr.com>
Date:   Thu Nov 5 09:09:20 2009 +0000

    Get the passed in Bus/Device/Function from the correct location on the
    stack.
    
    Signed-off-by: Mark Marshall <mark.marshall@csr.com>
    
    Clarified the comment and
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d08e69dd5e8fdddcef10b31dea223a9b2fd70d94
Author: Mark Marshall <mark.marshall@csr.com>
Date:   Thu Nov 5 09:03:04 2009 +0000

    Use more care when implementing the PCI BIOS functions.
    
    
    The READ_CONF and WRITE_CONF functions would both do the wrong thing
    if the passed in BDF was not found.  We should return and error to the
    caller, but not stop running the option ROM.
    
    Signed-off-by: Mark Marshall <mark.marshall@csr.com>
    
    I slightly reworked the patch:
    
    The 'CHECK' function seemed to be both wrong code and the wrong
    number.
    
    In fact the CHECK function was given the function number of
    the "Microsoft Real-Time Compression Interface". Since this is definitely wrong
    I removed the code.
    
    Dropped some unneeded scopes, too, to make the code easier to read.
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2fa7c2e210dc685d091c8bbb4012c91b80fc0a81
Author: Mark Marshall <mark.marshall@csr.com>
Date:   Thu Nov 5 08:10:12 2009 +0000

    When loading an option ROM use the class stored in the device to
    decide whether the option ROM is a special VGA type.
    
    An S3 card that I've got has the wrong class in the VGA BIOS.
    (A Stealth 64 DRAM T PCI, from 1994 - BIOS V2.02)
    
    Signed-off-by: Mark Marshall <mark.marshall@csr.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5fc7f98c51b898a6b584b360be6072cc5f49b44d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Nov 4 12:18:44 2009 +0000

    Fix up typo in Socket 441 CPUs, and add a few (trivial) Kconfig files for them.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6680487b950e79164db8ad340648e87adc27d91
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Nov 3 15:02:15 2009 +0000

    Some fixes.
    Atom does not like 36bit MTRRs in CAR setup.
    Enable XIP setup again (works with 32bit MTRRs)
    Keep code more similar to 6ex code..
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7110d40fbf27b1fafe70e3cd560f53ca7be094a5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Nov 3 14:59:43 2009 +0000

    x86emu: Add support for the following opcodes:
    
    * SMSW
    * INVD/WBINVD
    * RDMSR/WRMSR
    * CPUID
    
    The implementation is kept very simple (mostly dummies) but it should get
    us successfully through the Poulsbo VGA OPROM code in order to determine
    further requirements.
    
    Also, fix up a lot of warnings (mostly about missing prototypes for
    functions that should be static anyways)
    
    This version adds a break in smsw that was missing in the patch that was sent
    to the list.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8429de75a6cd6c6fbc13e0b85cbe9fba49dad211
Author: Loïc Grenié <loic.grenie@gmail.com>
Date:   Mon Nov 2 15:01:49 2009 +0000

    Add 82Q35/P35/Q33/G33/G31/P31 support to inteltool.
    The registers are (as far as I can tell) unchanged with respect to those
    of the PM965.
    
    Signed-off-by: Loïc Grenié <loic.grenie@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba49fb76a51ddb3c27e7c4c9873e75bf8687a73c
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Sun Nov 1 09:18:23 2009 +0000

    typo. trivial. Then -> Than.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68ce4e7692da16ca1b2f777ad869ed3ba1b05e87
Author: Myles Watson <mylesgw@gmail.com>
Date:   Sat Oct 31 22:13:04 2009 +0000

    Set SB_HT_CHAIN_ON_BUS0 correctly for arima/hdama.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc3214851bffaaf7b23e422f9f7552b5666708b2
Author: Myles Watson <mylesgw@gmail.com>
Date:   Sat Oct 31 20:47:14 2009 +0000

    Only remove .xcompile with distclean.  Look for crossgcc in util.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f3a5f60d3e2d2470ce3099874f753ae7107b3f2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Oct 30 20:38:15 2009 +0000

    ADLO has long been replaced by SeaBIOS, and it's also in v1 if someone needs
    it...
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20d626572bf95cd20bfeec98e81a74a2b40366b8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Oct 30 18:16:09 2009 +0000

    drop svn:externals in the tree and add it locally.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ac9e94b452b5ac58b6f7c44f1356b8e212ffcec
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Oct 30 16:54:52 2009 +0000

    new utility.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 850b22b90a1d8ef5aff57352761b6b26fb8d2bca
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Oct 30 16:53:37 2009 +0000

    coreboot repository cleanup
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 552890b6cd0dc5d0b05e5db7d864c715cee4888a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Oct 30 16:51:46 2009 +0000

    clean up coreboot repo structure.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7b82ef5c0927e7587e6b062e1a893ab32940621
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 30 13:10:03 2009 +0000

    Fix, um... a typo.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 81b3c0a10fe20493ecb8d4848cc27968ce822f95
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 30 12:56:59 2009 +0000

    Allow per-northbridge and per-board VGA BIOS file name and PCI ID defaults.
    
    Of course, the user can still override those defaults, if needed.
    
    Add defaults for VIA pc2500e, Kontron 986LCD-M/mITX, MSI MS-6178.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7943fe61df9e72721a8ceddb0120e4826552d5f9
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 30 02:08:07 2009 +0000

    Remove some warnings from the tyan s2895.
    
    Declare superio functions to be static and remove duplicates.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f6354b6d3d00a7041f3c770569e797da74acd04
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Oct 29 21:27:43 2009 +0000

    Split a print statement that called dev_path twice, and add a warning comment.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc4ca9a5dea9024bf17057dd78f58520183b2257
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Oct 29 16:49:50 2009 +0000

    Add prototypes to silence these warnings.
    src/lib/gcc.c:30: warning: no previous prototype for '__wrap___divdi3'
    
    The prototypes were not added to lib.h because the functions should never be
    called directly.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59b52190b3366cf27911b83de6d88b987687a4b7
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Oct 28 19:56:34 2009 +0000

    Comment out option ROM line in Config-abuild.lb to fix build.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d83cff04baaa5ba98e7ab373524dbf57f5312da
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed Oct 28 19:41:52 2009 +0000

    Add an initial version of some tools to compare (extended) K8 memory settings.
    
    This generates (dirty) html with interpreted differences between PCI dumps,
    based on the K8 socket F bkdg.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stepan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88214a48cc97b0d8f037d920d4f19c3470307428
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 28 19:40:46 2009 +0000

    Drop remainders of PPC port
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e696942cfc6d970d9a774815cc81bf1d771c857b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 28 19:38:58 2009 +0000

    Drop remainder of PPC port
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d09e231fed1395b82227ce374dca4be32e77845
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Oct 28 18:57:06 2009 +0000

    Fix some builds with Kconfig.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4ec4fbe0e94c173cf42fb9044a07b51d8e7fdd40
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Oct 28 18:51:47 2009 +0000

    Make d945gclf build.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d2f0c121f1fcb5da99174569996d8fccc1e9d1f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 28 17:36:11 2009 +0000

    Add some missing license headers, consistency fixes for others (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c73b4416ccda3d02bfaf9526ec356960260253b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 28 17:10:51 2009 +0000

    Remove all build/ prefixes in the build output.
    
    Also, remove one missing hardcoded "build" dir in the distclean target,
    and clean up files generated by sconfig in 'make clean'.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a08f582b54ec9fff0f356a824647ee40b3a5008
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 28 16:52:48 2009 +0000

    preliminary Intel D945GCLF Atom+i945 support.
    
    ram init fails, as the i945 driver currently only supports the mobile version
    of the chipset..
    
    Not sure how much sense it makes to check this in, but since it's a nice and
    cheap board, maybe someone wants to work on this.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 581707811c1c24bb0676e7582c671548b8851436
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Oct 28 16:13:28 2009 +0000

    Create lib.h for homeless prototypes.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4e5c0a2282a2af05d620fb0f8806d42a998c6da
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Oct 28 15:30:11 2009 +0000

    Replace hard coded build with $(obj) paths.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2a87ac64030da0f445dd285a09bbfe44893c4a7a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 28 14:57:14 2009 +0000

    The check for zero sized resources is already done earlier. So don't redo it
    here. I think we don't ever want to drop the extra check, since it indicates
    that the components involved need fixing.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7782319c21b0011aac316a7da945dd0e6efa5933
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 27 23:14:54 2009 +0000

    Prefix all build output file names of files which end up in the build
    directory with "build/" for consistency (trivial, sort of).
    
    Also, drop printing of "config.g" input file, we usually only print
    generated/output files in the build output.
    
    Finally, rename non-existing COMPRESSFLAG variable to
    CBFS_PAYLOAD_COMPRESS_FLAG in a printf line. The build output now says
    
        PAYLOAD    payload.elf l
    
    for payloads (the "l" specifies LZMA compression).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 312673ca729f2b3557a572a03ff6915460329286
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 27 21:49:33 2009 +0000

    Improve coreboot build output and eliminate some warnings:
    
     - Add static and const where possible.
    
     - Turn some #warning entries into TODO comments.
    
     - Add missing prototypes.
    
     - Remove unused variables.
    
     - Fix printf arguments or cast them as needed.
    
     - Make sconfig output look better. Drop useless "PARSED THE TREE" output.
    
     - Print "(this may take a while)" while building romcc. Add missing "\n".
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watosn <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a8888bd1d236af51dae1b39a5d7bc9dd8b9b4f2e
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 27 16:24:22 2009 +0000

    Remove redundant declarations.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a068164fc2e94dde83102ed72a7c0cb776d60815
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 27 15:53:27 2009 +0000

    Add $(obj) paths for a couple of smm files so they don't end up in the top directory.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea92185755a578d9a1b5df5cbf7b05ee2cea2390
Author: Maciej Pijanka <maciej.pijanka@gmail.com>
Date:   Tue Oct 27 14:29:29 2009 +0000

    Add few missing prototypes, and remove few unused (thus lonelly) variables.
    TODO
     - x86emu need (imo) some common header with prototypes at least
     - clog2, ulzma, hardwaremain prototypes added by this patch probably should
       be moved to some header too.
     - in src/devices/device_util.c prototype is before function because seems,
       it is used only within same file, if not it should be moved to debug
       section of prototypes in include/device/device.h
    
    Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 18d7c2e31e868c9f9f78b907f607b8a1b98b46aa
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 27 14:05:21 2009 +0000

    Update arima/hdama to detect how many nodes there are.  Compare to tyan/s2892.
    
    Fixes booting for Hugh.
    
    Various white space fixes as well.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a081a3b65fdb118476f000d6367d48607b7a7f2d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 26 23:52:34 2009 +0000

    Various smaller console option fixes as suggested by Peter Stuge:
    
     - Change "COM port" to "Serial port".
    
     - Also show the I/O port of the serial ports. Keep "COM1/ttyS0" though for
       easy recognition by the average user.
    
     - Change BAUD to Baud.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e21f75a8c3e6d7587fbf427ebc3144182166c6cd
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Oct 26 22:49:00 2009 +0000

    cp src/mainboard/tyan/Makefile.k8_CAR.inc to src/mainboard/Makefile.k8_ck804.inc
    
    Make more boards use both of them.
    
    Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dbbfedf8b0efc810a366ea518e298efd1a02f987
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Oct 26 22:03:30 2009 +0000

    Move src/mainboard/tyan/Makefile.s289x.inc to src/mainboard/Makefile.k8_CAR.inc.
    
    Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 63a8f2a7c29bb41191be085ca328c3938e774902
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 26 21:42:13 2009 +0000

    Add kconfig menus for most chipset VIDEO_MB values.
    
    VIDEO_MB is a variable that defines how many MB of RAM will be used
    for onboard graphics frame buffer. It's northbridge-dependent which
    values for CONFIG_MB are valid (but not board-dependent).
    
    This patch adds choices for menuconfig to select the VIDEO_MB value for:
    
     - Intel 82810
     - Intel 82830
     - VIA CN400
     - VIA CN700
    
    Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
    correct. If somebody has CN400 and CN700 datasheets, please verify.
    
    We drop all per-board VIDEO_MB variables in per-board Kconfig files as
    there's a northbridge-specific option/default now (plus the user can override
    the value if needed in menuconfig).
    
    As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
    it in util/compareboard/compareboard, we don't need to match those values.
    
    Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
    "Devices" sections into the "Chipset" menu, where NB-specific
    options will appear if you select a board using a certain NB,
    SB-specific options would appear in the "Southbridge" section etc.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 123a684ce6341e870fc1a73101e23b000c45b479
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Oct 26 21:41:06 2009 +0000

    Fix iei/pcisa-lx-800-r10. Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit afccdc0c56f372869fe476eacc8443263e9897a7
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Oct 26 21:04:03 2009 +0000

    Remove double include of smm directory.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 472837ad614e1ba7b8500c4bd7078ea7a3c6a841
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Oct 26 17:17:37 2009 +0000

    reasonable output in cbfs loading (part 2)
    run hlt in endless loop, be friendly to the cpu
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b4f3da5b143f5bc63f9bfd5332e557998d4d39af
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Oct 26 17:15:53 2009 +0000

    reasonable output for cbfs loading..
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aca6ec66bf7048e77ec960bb751a04e6b0528c70
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Oct 26 17:12:21 2009 +0000

    Kontron 986LCD-M update
    - run ACPI code through preprocessor so we get the same values
      as the C code
    - fix PCIe x16 slot
    - fix ICH7 Azalia/HDA driver
    - SMI/GNVS update security fix (only allow struct pointer update once)
    - ACPI updates
    - IDE driver fixes
    - add cmos options for disabling onboard ethernet and controlling system fan
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b314023802c7429012e5f09652047e0b32fb97a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Oct 26 17:04:28 2009 +0000

    CBMEM high table memory manager.
    
    This code adds a very simple toc based memory manager for the high tables area.
    The purpose of this code is to make it simpler and more reliable to find
    certain data structures in memory. This will also make it possible to have ACPI
    S3 Resume working without an ugly hole at 31MB.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a769344d437d608a2e714a01cdb847a2a69d0826
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Oct 26 16:49:16 2009 +0000

    intel core and core 2:
    - small preprocessor fix
    - leave some space in the CAR area for the usbdebug structure
      if usbdebug is used
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fbb8a015436d745916bfde6b521b3c36ae534e5e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Oct 26 16:48:27 2009 +0000

    Use Intel Core code for eagleheights CAR init, not Intel Core 2, as
    any of the CPUs might be used.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39e722958c80930a0d58a7cb267a0387811be099
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Oct 26 16:47:05 2009 +0000

    Now that the resource allocator is working nicely we can turn down the debug
    level output and make some output SPEW only.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d73c1b5bf1246855a4d4e847702214a3eeb6ab82
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Oct 26 15:14:07 2009 +0000

    Define some variables that were not defined.  There are a couple left.
      Do kbuildall then grep not.defined kbuildall.results/*
    The interesting ones were GENERATE_*  I had to put them in twice to make it work
    correctly: once outside the menu setting the defaults, and once inside the menu.
    Now they show up when they should, and are always defined
    
    Define HAVE_INIT_TIMER to only exclude the three boards that define it to be 0
    in newconfig.
    Define MEM_TRAIN_SEQ to be an integer and set it correctly.
    Remove CAR_FAM10 and just depend on NORTHBRIDGE_AMD_AMDFAM10
    MOVNTI is a performance enhancement, and should default to 0 so it doesn't break
    boards that forget to define it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 074356ec819be284fb1e8d18a68678b72c5282da
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Oct 25 19:50:47 2009 +0000

    Option ROM init x86/x86emu update
    
    - use default display in int 15 5f35
    - move REALMODE_BASE to 0x600, 0x500 can be BDA
    - add regparm for assembler functions
    - use memset instead of own implementation
    - YABEL: copy back the IVT, BDA and VBIOS. Some Xorg drivers require this.
    - YABEL: use hardware timer instead of emulated timer, because the emulated
      timer's base is never initialized (leading to division by zero if the
      timer is really used)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 46a895e633a6b4bd3f4a8391529cc069a8a8d04b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 24 22:52:33 2009 +0000

    Fix intel/xe7501devkit build, missing "uses" clause.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d8b0979c3cb1d63003b5f2aa1854d1d66698c66
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 24 22:42:53 2009 +0000

    Fix kconfig build error due to "source"ing a non-existant file (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d1327ce9639645f84024ddd66d2b11f57619d8e6
Author: - supermicro/x6dhe_g/auto.c <- supermicro/x6dhe_g/auto.c>
Date:   Sat Oct 24 19:17:24 2009 +0000

    Major cleanups of the hard_reset() code and config in coreboot.
    
     - Drop unused "#object reset.o" entries.
    
     - Use CONFIG_HAVE_HARD_RESET for all "object reset.o" entries.
    
     - Drop dead/commented code, i.e. useless hard_reset() from:
       - supermicro/x6dhe_g/auto.c
       - supermicro/x6dhe_g2/auto.c
       - supermicro/x6dhe_g2/auto.updated.c
       - supermicro/x6dhr_ig/auto.c
       - supermicro/x6dhr_ig2/auto.c
       - digitallogic/msm586seg/auto.c
       - dell/s1850/auto.c
    
     - Add "obj-$(CONFIG_HAVE_HARD_RESET) += reset.o" to kconfig files of boards
       that actually have a reset.c file.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d2ddff011700744d2374a95f8c807dbdfb85603
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 24 19:07:05 2009 +0000

    Change QEMU CPU Makefile.inc files to match other CPUs.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7223780b0742d18880e71e02883ef39298d75131
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 18:54:46 2009 +0000

    removal of that unnecessary include slipped through r4841
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b09cbba9efbe98224b04e5c62a2b95e096e1ae3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 18:47:43 2009 +0000

    hook up missing x86 SMM into Makefile
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7833048e1f5cc7e33de9a276dde0a30349b6c7b3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 18:46:08 2009 +0000

    drop support for various (old) PPC CPUs as per discussion from 9/10/9
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 95fca9e8f4ab2d6ec65d70880c849a3124a6a8bc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 18:38:53 2009 +0000

    add CPP to xcompile in case we need it (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 105bace68d7dbbe2f475e5a3c4e9c3cf751a2f7f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 18:36:51 2009 +0000

    Some ACPI implementations don't like to see full paths within a scope for
    CPU power management, so don't add the scope name
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd3e82ab46987628f2a86f2af1e94adedb35647a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 18:15:07 2009 +0000

    Rework the keyboard driver
    * use readable macro names rather than numbers.
    * Factor out some commonly used code
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c81a12a74895bb972444c75f4f985e7c6a9a63f3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 18:02:04 2009 +0000

    drop src/include/stream/ as the source files from src/stream were dropped a
    while ago...
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c35a4511f715b926852117d30ac106c4709fba26
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 17:59:36 2009 +0000

    * refactor x86 smi handler (put all debug stuff in an extra file smiutil.c)
    * lock other CPUs in SMI handler while one CPU is handling an SMI. Without
      this various racing scenarios could happen.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 311c56420b07daeae426d03bdfbe20933eabc844
Author: Myles Watson <mylesgw@gmail.com>
Date:   Sat Oct 24 13:40:55 2009 +0000

    Trivial regrouping of a calculation to simplify it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea67d4757b776ed7ff147e1b4cbdaf300bc4bb6c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 13:13:37 2009 +0000

    A (hypothetical southbridge) component might provide functionality that is not
    available on all boards. Thus, only print a debug level warning instead of an
    error.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52fc6b12cb458a93ba1eeac4082f4e7f574cdafc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 13:06:04 2009 +0000

    re-order console output functions, add proper prototypes,
    drop claim that our files were blatantly copied, because they have been
    rewritten a very long time ago.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b53bed15677e8bd97f58f7f5d847f1029ddaa41b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 13:02:14 2009 +0000

    Fix USB Debug Device for Intel ICH chipsets
    
    The USB EHCI controller reset is not really needed on ICH, and in fact
    the code bailed out there which is the most stupid thing to do. So just
    keep trying.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f3b8583e2fc8c6d7b869c3aab73d2364bb8e37d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 12:40:52 2009 +0000

    Fix K8 boards high tables on UMA systems (KT690 for example)
    
    Thanks to Carl-Daniel for pointing this out with some example code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 561b6c68c1a68ab42944f655431a3ea1b66ea8da
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 03:55:24 2009 +0000

    s/object-y/obj-y/ in two southbridges, since otherwise kbuild will not pick up the files
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 60fc92a42ed2ab72e6e7d11ce2b0f698064b0166
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 03:33:44 2009 +0000

    First attempt to integrate SMM in Kconfig. Unused code so far
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42dc721cdf45fee9940514aa35e8e821ece25019
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 24 00:47:07 2009 +0000

    move all register fram definitions to arch/register.h
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c1e7efa98d4dbdb8e7f397c68cd27d26cb0f78de
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 23 23:30:31 2009 +0000

    Remove left-overs from Winbond southbridge removal (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 036c15fe71c4ec69e4403e0957f6c84357177d49
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 23 22:53:26 2009 +0000

    Drop dead K8_SCAN_PCI_BUS code.  It's a bad idea to scan the PCI busses before
    RAM is initialized, and no one does it.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c21b5ee58470c16b4f31578fe19d10e66cb914ad
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Oct 23 21:57:42 2009 +0000

    New revision guide September 2009 3.46
    Lets add some more CPUs.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e1a8d10ba8a64e5bcf230323a314bf273794f62
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Oct 23 19:33:52 2009 +0000

    drop a lot of dead code, including an old winbond southbridge from our removed
    ppc port, some ambiguous use of CONFIG_IDE and an unused ide driver (we dropped
    the filesystems already to be used with it) (somewhat trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 707fad0508ffabc6a5137e35d0248ccaa188dea9
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 23 18:22:27 2009 +0000

    White space and comment fixes for cache_as_ram.inc files so it's easier to spot
    differences.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 35ed0e7ea3d9bd6641c719cf4489bfa408e48972
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 23 18:19:22 2009 +0000

    Remove PRINTK_IN_CAR tests from AMD files.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87f9514ab79340272ba4d06427ea2402cd6712d8
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Oct 23 12:14:15 2009 +0000

    VGA BIOS can be added independently of having a payload
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c8863a234f627d5d1117e13ae828b21e18605aea
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Oct 22 17:02:44 2009 +0000

    minimal whitespace fix (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26eb33faca6b22028c52c74d7cc55ef536028061
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Oct 22 16:59:33 2009 +0000

    trivial: add note that VSA blob belongs into CBFS.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99bc4514c23f0001f2da7da47f03d3ba94232cc7
Author: Libra Li <libra.li@technexion.com>
Date:   Thu Oct 22 02:54:25 2009 +0000

    The LAN chip-set on the Technexion TIM-5690 is enabled by hardware and
    does not need any handling in software.
    
    Signed-off-by: Libra Li <libra.li@technexion.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8f73ed14dc87fdbf9103f722d7e6e3c606af3ee
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 21 00:35:42 2009 +0000

    Add CONFIG_VGA_ROM_RUN to HP e-Vectra P2706T to make VGA init work.
    
    Also add pci_rom entries (commented) to targets/hp/e_vectra_p2706t/Config.lb
    for the same reason. They have to be uncommented to be used.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b8d4fae8e5c305dc111aacc211fe950b4a895e2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 20 22:36:34 2009 +0000

    Add initial support for the HP e-Vectra P2706T.
    
    Boot-tested by Paweł Stawicki <stawel@gmail.com>.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Paweł Stawicki <stawel@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce491013ac13810c9f6b6a30ebd5846af5809706
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 20 18:11:06 2009 +0000

    Minimize differences between newconfig and Kconfig for arima/hdama.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bea4cc60ba4ca51c62a2888309a145b02d4580cc
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 20 17:13:28 2009 +0000

    When I converted an #ifdef to an #if it broke the code because the variable was
    always defined, but not 1.  This commit reverts to the old behavior.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6aadbe3ebca9865d47443d11933ef11bfe31085
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 20 16:24:23 2009 +0000

    Fix #if CONFIG_VGA==1 -> #if CONFIG_VGA.
    (forgotten in last check in.)
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f74c5878dde6b610b416a5950de3219532c0f83
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 20 16:10:04 2009 +0000

    Remove CONFIG_CPU_AMD_FAM10 & CONFIG_CPU_AMDK8 from mainboards.  They should be
    selected in sockets, and they aren't used yet.
    
    Add a couple of variables to src/Kconfig for lack of a better place so that
    their selects work.
    Add select statements according to newconfig for some variables that were
    defined but never selected in mainboard configs.
    
    Fix #if CONFIG_VGA==1 -> #if CONFIG_VGA.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e015eb67432b4d46003023cd4bc8c04282896e4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 20 13:55:35 2009 +0000

    Fix all board names in Kconfig as per wiki / vendor website.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1529576019b41baf008b871339b9dd225959f5a9
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 20 13:40:30 2009 +0000

    Correct typo.  Thanks to Mark Marshall for spotting it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ec971020fbb740fbcdd76b789f068bb3141577f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Oct 19 19:08:18 2009 +0000

    Move ITE-specific option to src/superio/ite/Kconfig.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ba7bfe7c4c99b268e49548d7bc8a0964a398f08
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 19 18:55:08 2009 +0000

    Add missing SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL kconfig variable.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42fd936de229126aba0217997b945cf3cf675e9f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Oct 19 16:58:51 2009 +0000

    Fix builds of amd/db800 and digitallogic/msm800sev with smaller bootblocks.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66f03e4b145c2ee645b60c8471a4bdf74e811254
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Oct 19 16:48:32 2009 +0000

    Unselect AP_CODE_IN_CAR in tyan/s289x.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec0ee64da7aa7e569da7d55ef86804d9b7fbea1b
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Oct 19 16:21:30 2009 +0000

    Clean up some #ifdef CONFIG_*
    Change HAVE_FAN_CTL to be specific to the SuperIO that supports it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a29ad5cb09c1fd983bbace35185148630c62de5d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 18 18:35:50 2009 +0000

    Add EXPERT kconfig option so we can hide more advanced options
    from beginners who should rather not touch them unless they know what
    they do.
    
    Also, add a random Kconfig help comment.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7f3005093960155749a03ea22137e6e28a492521
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 18 18:27:42 2009 +0000

    Drop a duplicated implementation of failover.c.
    
    Abuild-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e405327b46523ea93f84d29798b394c43a0f0f52
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 18 13:47:30 2009 +0000

    Simplify Kconfig files by using "select" where possible (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c57df6c1a672218254c2625dd2bc949dacf469f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 18 13:42:50 2009 +0000

    Drop dead/unused code (trivial).
    
    DEBUG_SETNORTHB is never defined, and even if it was, setnorthb()
    is never called anyway.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c1bf62d0c8c21bdda316ea0e20be6904bbcb6f5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Oct 18 03:15:59 2009 +0000

    Remove this, we no longer need it.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d08be7eecdfd3ee5adff11341a4b7510e7d004dd
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Oct 17 15:01:00 2009 +0000

    Move files from src/cpu/x86/{fpu,mmx,sse}/ to x86/
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0bc615482e34af308712be970479aeb613f5fa41
Author: Myles Watson <mylesgw@gmail.com>
Date:   Sat Oct 17 13:25:07 2009 +0000

    Remove CONFIG_ from #defines that aren't config variables.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d7b37b0a670abc24e538700c0e2762f1cde7faf7
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Oct 17 03:00:04 2009 +0000

    Silence src/Kconfig:349:warning: config symbol defined without type
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f078be2cb132da65540aa1a3d98649203d7ea139
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Oct 17 02:51:26 2009 +0000

    Remove some more instances of including previous empty x86/fpu/Makefile.inc
    
    Thanks to Jakob and Uwe for spotting the mistake!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b1924301cac75adc9f63d75e03d6d165d418ddc8
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Oct 17 01:12:42 2009 +0000

    Drop src/cpu/x86/fpu/{Config.lb,Makefile.inc} since they are also empty
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d12b7030c600f4b70055a073ab100e83105ccd12
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 16 22:39:55 2009 +0000

    Make COM port selection and BAUD rate a "choice" for better usability.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e052bb7a601d63eb2ab5251ad87ca5ea28572e9c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 16 22:07:20 2009 +0000

    Drop duplicate version of the documentation/cbfs.txt file as discussed.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e19eee460adb3e9a701eabfff0d127093e23c9c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Oct 16 22:07:15 2009 +0000

    This is a snapshot as the availability of the systems for this
    project is now uncertain, and I can't invest the remaining time
    needed to get it done.
    
    Status is that memory is still not quite configured correctly. It is close
    but here are DRAM Row Boundary registers.
    Here is coreboot
    60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00
    This is close. But:
    60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00
    is the real hardware. So we are somehow missing those last slots. I think it's
    because the SPD connections and the chip connections differ, some dumping
    of RAM registers differ. But it's very close.
    
    This is under serialice. Once we get to this point we get stuck here:
    Copying coreboot to RAM.
    Copying coreboot to RAM.
    Copying coreboot to RAM.
    
    Forever.
    
    Here is the total config for 0:0.0 from coreboot:
    PCI: 00:00.00
    00: 86 80 90 35 06 00 90 00 0c 00 00 06 00 00 80 00
    10: 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00
    20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
    40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00
    50: 0c 60 2a 00 00 00 00 00 00 30 33 33 33 33 33 33
    60: 10 10 20 20 20 20 20 20 00 00 00 00 00 00 00 00
    70: 0a 0a 00 00 00 00 00 00 67 11 5e 55 1e 02 20 2c
    80: 41 28 21 00 00 00 00 00 80 01 00 f0 00 00 00 00
    90: 00 00 00 00 00 a1 04 39 aa aa 0c 30 5f 08 02 07
    a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00
    b0: 32 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    c0: 44 c0 50 11 00 c0 ff 03 00 00 df 03 20 00 00 e0
    d0: 02 28 00 0e 07 00 00 00 00 00 93 b5 00 00 00 00
    e0: 00 00 00 00 00 00 00 00 36 3c 00 00 00 00 00 00
    f0: 00 00 00 00 3a 01 42 00 80 0f 0c 00 00 00 00 00
    
    And from factory:
    00:00.0 Host bridge: Intel Corporation E7520 Memory Controller Hub (rev 09)
    00: 86 80 90 35 46 01 90 00 09 00 00 06 00 00 80 00
    10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    20: 00 00 00 00 00 00 00 00 00 00 00 00 28 10 6c 01
    30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
    40: 09 00 05 41 10 00 00 00 00 00 00 00 00 00 00 00
    50: 0c 20 6a 00 00 00 00 00 00 10 11 11 01 00 00 10
    60: 10 10 10 10 20 20 30 30 00 00 00 00 00 00 00 00
    70: 0a 00 0a 0a 00 00 00 00 44 11 5e 55 1e 02 20 2c
    80: 41 28 41 00 00 00 00 00 80 01 00 f0 88 00 00 00
    90: 00 00 00 00 00 aa 04 39 aa aa 0c 30 75 08 12 07
    a0: 01 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00
    b0: cc 00 99 55 00 00 00 00 00 00 00 00 00 00 00 00
    c0: 44 c0 50 33 00 e0 60 00 67 00 28 00 30 00 00 e0
    d0: 02 28 00 0e 03 00 00 00 00 00 93 b5 00 00 00 00
    e0: 00 00 00 00 00 00 00 00 3a 3c 00 00 00 00 00 00
    f0: 00 00 00 00 10 01 02 00 80 0f 0c 00 00 00 00 00
    
    I want to commit this because even if I get no further, someone else might.
    Note that for serialice you need the following temporary patch as well:
    Index: src/superio/nsc/pc8374/pc8374_early_init.c
    ===================================================================
    --- src/superio/nsc/pc8374/pc8374_early_init.c	(revision 4791)
    +++ src/superio/nsc/pc8374/pc8374_early_init.c	(working copy)
    @@ -29,7 +29,8 @@
     static void pc8374_enable_dev(device_t dev, unsigned iobase)
     {
     	pnp_set_logical_device(dev);
    -	pnp_set_enable(dev, 0);
    +/* don't disable for now, it kills serialice */
    +	pnp_set_enable(dev, 1);
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3ff6358f8e6aea0cc236544d9369875868711343
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 16 20:15:06 2009 +0000

    Revert deletion that snuck in to 4794.  Sorry.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0364618fe86a7e3ad9b9f79105c66cbefdc64ab6
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 16 19:29:45 2009 +0000

    Change console code to emit SPEW with DEFAULT_CONSOLE_LOGLEVEL==8.
    
    Make MAXIMUM_CONSOLE_LOGLEVEL >= DEFAULT_CONSOLE_LOGLEVEL.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 04000f46425da330a14044f2c60c5598b4dfa539
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 16 19:12:49 2009 +0000

    Fix AP_CODE_IN_CAR (only selected for two boards), STACK_SIZE, and HEAP_SIZE.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c54f90280dda5ba61ba7dad5b2dc3948df6b0b4
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Oct 16 18:27:13 2009 +0000

    Drop empty cpu/x86/{mmx,sse}/{Config.lb,Makefile.inc} and remove references
    
    Files in those directories are still used, but always with explicit path.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 777e069c5a709b6504736a3cbed8f5363f1e9049
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Oct 16 17:43:46 2009 +0000

    Drop enable_mmx.inc. It reads (only) "Enabling mmx registers is a noop"
    
    abuild tested
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d65509de14d95ccc7c9928c789d903098083fb23
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 16 17:37:20 2009 +0000

    Set default ROM sizes per-board to match the ROM chip that came
    with the respective board.
    
    Of course, the user can still override the size in menuconfig.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 04b9b92952d0e9f4b520fa9f1512daf5608f080b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 16 16:39:40 2009 +0000

    Drop unused and useless CONFIG_MAX_PCI_BUSES.
    
    It was added by rsmith in r2273 on 20060424, when pci_locate_device() in
    src/arch/i386/include/arch/romcc_io.h in fact scanned all busses:
    
     - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
     + for(; dev <= PCI_DEV(CONFIG_MAX_PCI_BUSES, 31, 7); dev += PCI_DEV(0,0,1)) {
    
    Today this looks like:
    
       for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
    
    and CONFIG_MAX_PCI_BUSES is never used anywhere.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f61a4fc98f135c0ed22c67ee3241bf5670a61e2
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 16 16:32:57 2009 +0000

    Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP to match CONFIG_RAMBASE.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9969bdc4fb3d36a39ed9efb67ef0bf638a4e8e09
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 16 14:34:50 2009 +0000

    Fix IRQ9 and allow ACPI without an MP table for Tyan s289x.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 025b8a387720d7766774256aad9ae1dabfa28ec1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 16 13:34:32 2009 +0000

    Fix kconfig setup for the VIA pc2500e.
    
    Add/drop Kconfig variables as needed.
    In Makefile.inc just include Makefile.romccboard.inc with -mcpu=c3.
    
    Build- and runtime-tested on hardware.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 776260675a7afda22d81b58350b404850b5f4d31
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 16 10:06:18 2009 +0000

    Similar to r4626, change obj-y to driver-y for VIA C3 and C7.
    
    Otherwise the following happens at runtime (tested on VIA pc2500e, C7):
    
      Initializing CPU #0
      CPU: vendor Centaur device 6a9
      CPU: family 06, model 0a, stepping 09
      Unknown cpu
    
    We also change C3 as it is pretty clear that the same problem occurs there.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 709a71a3b636d782675dab92cf090018fc4f89de
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 16 10:03:50 2009 +0000

    Drop duplicate CPU subdirs-y entries for "../../x86/mtrr".
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 289a2f5aad4eb8b231083ce4250bc382dad6cdbc
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Oct 16 07:44:04 2009 +0000

    Add CONFIG_VGA_ROM_RUN to dbm690t and pistachio, otherwise the
    VGA ROM can not run. After make, run
    > ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom   pci1002,791f.rom  optionrom
    to make the final image with vga bios.
    
    The macro vga_rom_address is out-of-date when CBFS starts play its role. it also should
    be eliminated from rs690/chip.h as below. But it will cause building error on other board, which I
    cant make test on.
    
    ##    Index: src/southbridge/amd/rs690/chip.h
    ##    ===================================================================
    ##    --- src/southbridge/amd/rs690/chip.h	(revision 4782)
    ##    +++ src/southbridge/amd/rs690/chip.h	(working copy)
    ##    @@ -23,7 +23,6 @@
    ##     /* Member variables are defined in Config.lb. */
    ##     struct southbridge_amd_rs690_config
    ##     {
    ##    -	u32 vga_rom_address;		/* The location that the VGA rom has been appened. */
    ##     	u8 gpp_configuration;	/* The configuration of General Purpose Port, A/B/C/D/E. */
    ##     	u8 port_enable;		/* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
    ##     	u8 gfx_dev2_dev3;	/* for GFX Core initialization REFCLK_SEL */
    ##
    
    Don't apply above patch about rs690/chip.h before every board has been fixed.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9d37532bc1075360c3f1eca8f000afd7c178de5a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Oct 16 01:08:07 2009 +0000

    this is probably in vain because this tool should use the same x86emu as
    coreboot in order to produce comparable results. But, this patch drops the
    CONFIG_ from CONFIG_DEBUG because that was added by accident when we
    automatically renamed coreboot variables to be consistent. "vgabios" is an
    independent userspace utility, and it does not use newconfig nor Kconfig, so
    it should not be converted. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61c7fbfd5e1305ab7e05b3f1e7eea50085515640
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Oct 15 22:40:41 2009 +0000

    undo another accidential rename of X -> CONFIG_X (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ba13bbf7cc031713ea6d14934714aa3dda78d8a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 15 17:49:07 2009 +0000

    Start documenting a few kconfig variables and user-visible options.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3e08cb72ff2a05409e97425833e0b3e7459b0162
Author: Libra Li <libra.li@technexion.com>
Date:   Thu Oct 15 14:23:33 2009 +0000

    Fix Kconfig for technexion/tim5690.
    
    Signed-off-by: Libra Li <libra.li@technexion.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8e2027be817159d4606f991475b59fc36b0242d
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Oct 15 13:35:47 2009 +0000

    Add CONFIG_GENERATE_* for tables so that the user can select which tables not
    to build, but by default all the tables that are available are built.
    
    Make PIRQ table build for qemu.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45b811b13552a94af4713b77613d377561e4ef26
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Oct 15 13:16:40 2009 +0000

    Add Kconfig support for kontron/kt960.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74cb9eb7e75bceadb0ebd2eee5b26f27934e5750
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Oct 14 23:51:05 2009 +0000

    cbfs_and_run_core() did not check the return code of cbfs_load_stage()
    and jumped to (void*)-1 on error.
    Die properly instead.
    I didn't use die() because that caused a linker error.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 75472d27e4b76d13812cf466d9defc51a4ecc851
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Oct 14 20:49:49 2009 +0000

    Fix high tables address calculation on cn700 with VIDEO_MB > 0.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a04f17af064927db63655dc26e5d583457232bb
Author: Libra Li <libra.li@technexion.com>
Date:   Wed Oct 14 03:19:33 2009 +0000

    Add forgotten target files for technexion/tim5690.
    
    Signed-off-by: Libra Li <libra.li@technexion.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59b2dc2cf2c24a9f9ea5e635a31b49ef4c1ef05a
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Oct 14 03:09:26 2009 +0000

    White space and typo fixes.  This makes it easier to compare the s2895 & s2892.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb69cb3e69425079d2046c7883865485f2c00dc4
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Wed Oct 14 02:56:00 2009 +0000

    delete white trailing spaces. It is done by the perl command.
    sh> perl -pi -e 's/[[:blank:]]+$//' $files
    Trivial.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by:  Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b0575d8e1fe1a3368ec4690dde4ffd4fe7f033d3
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Oct 14 02:38:24 2009 +0000

    Use CAR ck804 code with the s2892.
    Reset the s2891 so the HT speed gets updated.
    Remove some PANTA comments.
    Add SATA init from non-CAR version.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 21ee98bf79c00b3b5693f2ce43d98fa8335589d4
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 13 22:53:24 2009 +0000

    White space change in preparation for a patch to unify handling of ck804.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fbc11edd7ac806516ebd301ee721035706eb4541
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 13 20:20:55 2009 +0000

    Revert some garbage that snuck into my trivial change, correct a spelling error.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54913b98e53f5bb596732b172791326268afbae0
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 13 20:00:09 2009 +0000

    Remove a couple more warnings.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 95aa53a5c3b84b6593714db59fa8a2b2180d47b0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 13 19:21:44 2009 +0000

    Add support for the MSI MS-6156 board.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6bbe74c639b5b088f0631387c29b12452f8152c1
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 13 17:56:11 2009 +0000

    Fix kontron/kt690 build.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d3649a605cf5d535039f1932224cdeafc49f73b
Author: Libra Li <libra.li@technexion.com>
Date:   Tue Oct 13 16:56:58 2009 +0000

    This patch support for the Technexion Tim-5690 mainboard.
    It's an embedded AMD RS690/SB600 mainboard.
    
    http://www.technexion.com/index.php/tim-5690
    
    Myles added Kconfig support.
    
    Signed-off-by: Libra Li <libra.li@technexion.com>
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c270e896f0bf9c780f2c49fa258b1c225e61ec9d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Oct 13 16:47:57 2009 +0000

    This patch adds (initial) support for the Kontron KT690 mainboard.
    It's an embedded AMD 690/SB600 mainboard with a Mobile Sempron CPU.
    
    Issues with this port:
    - hangs early during "Starting Windows" with Windows 7, after loading all the
      drivers
    - sound is untested and probably not working
    - powernow seems to be not working
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45cbc35abb9e8d8cea3d1ba69891b6a0b1621709
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 13 11:45:04 2009 +0000

    Fix obvious typos (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4763 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3db199c00a4c0b7986da98f2bc5504526c3a1cf2
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Oct 12 22:39:08 2009 +0000

    Make fam10 build (but not boot due to bootblock size problems.)
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b106f9bdbd02a7aafd7db0c198fc6a1112f1e412
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Oct 12 18:43:26 2009 +0000

    Add the compareboard utility which is useful for porting
    to kconfig.
    Hook it up to kbuildall, too
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d7ec68856aa2c8aed6d84905e71d6f28900d52d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 11 18:21:45 2009 +0000

    Remove useless udelay() duplication.
    
    Abuild-tested for the boards that are touched.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c0528d61df39dc64e244c9c39eb62b7a32618a5c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 11 17:40:44 2009 +0000

    HAVE_ACPI_TABLES cleanups for kconfig:
    
     - Add "select HAVE_ACPI_TABLES" for boards which need it.
    
     - Drop sections which set HAVE_ACPI_TABLES to 'n', that's the default.
    
     - Convert sections which set HAVE_ACPI_TABLES to 'y' to the
       shorter "select HAVE_ACPI_TABLES".
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7fe4191fff69a1a32888035fd5d3168350167ced
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 11 13:35:24 2009 +0000

    Make console maximum/default log level a choice option.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fcb28b66cea2368a8e7505c999fe356d68fd38df
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 10 16:19:12 2009 +0000

    Drop "select CONSOLE_SERIAL8250" from QEMU, it's default-y anyway.
    
    Tested on QEMU.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3fe6b7002bf8da7ecd91c2ab4e8bfdec4e80e02f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 9 20:13:43 2009 +0000

    Add const to get rid of some warnings when passing quoted strings.
    Remove an unused extern declaration.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42584096c30440ecef1c50322f2f39ccbc9e5230
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Oct 9 20:07:48 2009 +0000

    This change allows us to see the spd on the s850, finally.
    There is an i2c mux out there. We found it using a user level program
    that, as usual, began by inverting all gpios until we found out
    what we needed to know. In the end, we just set up the GPIOs as
    the factory bios does.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 517bb208dcb2739108d07357c79e78ecd474523f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 9 17:40:34 2009 +0000

    Remove extra CONFIG variables.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e7bbb50ba0bf53b2a6bd7bbbe5f7052855e0da23
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 9 17:39:35 2009 +0000

    Remove default n statements to simplify .config and ldoptions files.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86bf6795c3b1b537b5de07e3a5fca9faf4bd6073
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Oct 9 15:22:35 2009 +0000

    Move the ulzma prototype out of the function to make the code easier to read.
    
    Check the return value.  Minor formatting and LAR -> CBFS.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 00f0267f7805f6d27d78c1ed586ac0f13c90637b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Oct 9 14:10:28 2009 +0000

    Remaining boards are Kconfig'd now. Whether they work
    or not still depends on how close the configuration
    options are to what they should be.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 91ff0df62777a9ec4a399ef899803c05e7caad60
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Oct 9 12:32:52 2009 +0000

    More Kconfig-supported boards, and also kconfig support
    for amd/socket_AM2R2, amd/socket_939, drivers/ati/ragexl
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 748475b800c552236aff16c1beffd55b70791ae6
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 9 11:47:21 2009 +0000

    More kconfig cleanups:
    
     - Use "default n" for all components that shall be "select"ed.
    
     - Use "0x0" instead of "0" for hex variables for clarity and to reduce
       the risk of people passing integer instead of hex values to such variables.
    
     - Add TODO comments for boards that have irq_tables.c but don' set
       CONFIG_HAVE_PIRQ_TABLE = 1. Someone with the hardware should test enabling.
    
     - ASUS M2V-MX SE doesn't have irq_tables.c so don't define
       IRQ_SLOT_COUNT in its Kconfig file.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebb43d69439d847e87e18ac332e71b9b0476936a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Oct 8 20:17:14 2009 +0000

    Fix CS5535 build for kconfig, more kconfig boards (lippert, artec)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3fcd45a7fa450cc5befdcc8bcfa7d8541f4e81e
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Oct 8 18:50:16 2009 +0000

    Simplify targets/amd/serengeti_cheetah/Config.lb.  There were too many
    variables being set incorrectly.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea1522b016d3740f5b57e682de9d936cacac2406
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 8 17:10:20 2009 +0000

    This dialogue on email was useful and hence included.
    
    
    failover.inc MUST come after enable_sse or your CPU will hang.
    
    > Can you say why?
    
    yes. if you compile failover.c with romcc options that include sse,
    then you'll see code like this in failover.inc:
    mov eax, %xmm0
    
    This will hang if you have not first enabled sse.
    Verified yesterday on the dell s1850.
    
    >
    > Does it hang in the SSE code or in the failover code?
    
    It will hang in failover code, if that code was compiled with sse enabled
    AND if the sse registers are used.
    
    >
    > Does this mean that failover requires SSE in order to work?
    
    It may or it may not.
    But if you compile it with romcc options that include sse,
    and it uses sse without sse being enabled, it will hang.
    This is a particularly nasty bug in that the failover code is not
    guaranteed to compile in a way that sse is used, even if sse is
    enabled; hence, this could be very hard to catch.
    I'm lucky this bug appeared as soon as it did.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc2b9f2abeaac660bb474fe4cc4e75eb70a8371b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 8 16:06:09 2009 +0000

    Set MMX and SSE where needed. Note that many boards don't even bother
    with this as many boards (AMD in particular) use CAR.
    
    This list determined by a series of greps etc. on mainboards, no humans
    were harmed in the making of this list.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0523875e0968e1cabf677092d8330eb6470ce969
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Oct 8 15:12:31 2009 +0000

    Disable x86emu for via based boards which bring
    their own vgabios.c
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98402455c5a21cc8de9d5d51f7e6dd0c1b7df76e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Oct 8 14:31:56 2009 +0000

    More kconfig:
    AMD LX
    AMD SC520
    boards by iei, pcengines, technexion, technologic, thomson
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 824fce488bb9c638881d8e5f5baa09f2bf02d2c1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Oct 8 10:19:20 2009 +0000

    Oops, wrong type for Kconfig value. Trivial fix
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5726f92027c4299a7cad46c9153dbe55543efb5e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Oct 8 07:43:09 2009 +0000

    Kconfig: AMD Fam10, all Tyan boards.
    Fam10 doesn't build due to size constraints at this time.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b97ee05dc72c52fbb694326863b4977736d0f225
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 7 22:53:30 2009 +0000

    Emergency fix. Failover.inc can end up with code that uses sse. It has
    to be run AFTER SSE is set up. I just had this problem cause a failure
    today.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 95313d824dabcbdecaa74346a2d9e0ab2af9df9d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 7 21:51:33 2009 +0000

    Major CONFIG_IRQ_TABLE_COUNT fixing and cleanups. Some of these boards
    and PIRQ tables were actually wrong, I cannot imagine they ever
    worked properly.
    
     - Use CONFIG_IRQ_TABLE_COUNT in all irq_tables.c files instead of
       hard-coded numbers.
    
     - Make all CONFIG_IRQ_TABLE_COUNT values in irq_tables.c match Options.lb.
    
     - Make all CONFIG_IRQ_TABLE_COUNT values match the actual number of entries
       in the irq_tables.c file.
    
     - Set all CONFIG_IRQ_SLOT_COUNT values in src/.../Options.lb for those
       boards where they were set to 0 (in order to be overridden in
       the respective targets/.../Config.lb).
    
       This is mainly done to aid Patrick's scripts for kconfig conversion.
    
     - Fix a number of comments in irq_tables.c files.
    
     - Drop CONFIG_IRQ_SLOT_COUNT usage from boards that don't have irq_tables.c:
        - tyan/s1846
        - asus/a8v-e_se
        - asus/m2v-mx_se
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17aeecab8988cb0fdb84a3269a65ff51c00a019a
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Oct 7 18:41:08 2009 +0000

    Kconfig allows you to run all PCI ROMs, VGA only, or non-VGA only.
    Update the code to support that too.
    
    Remove an unused variable.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 877119a995556241d4ac72639ed8ee9378ec6c00
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Oct 7 18:07:49 2009 +0000

    Fix trivial typo in Kconfig spotted by Peter, introduced by me.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b6a0a84bea27bdb332b082e6d602f0596a2a8c8
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 7 18:03:41 2009 +0000

    Get rid of early_serial, it is now a generic function in early_init.
    Add some more enables to the s1850.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 869bbc46166bdfe0b785b5a64ebcea2f167e1b0c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 7 16:29:12 2009 +0000

    Convert all "default y" options to "select FOO" (shorter).
    
    Also, drop per-board CONSOLE_VGA/PCI_ROM_RUN while I'm at it, they're
    global options in kconfig.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 168b11bc416eb0931581cc674a60bc53861081c3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 7 16:15:40 2009 +0000

    Various Kconfig fixes and improvements:
    
     - Add helps texts to multiple user-visible Kconfig options.
    
     - Improve some menu and option names.
    
     - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down
       (instead of up) when changing "no payload" to "ELF payload" (more
       intuitive, IMHO).
    
     - s/cbfs/cbfstool/.
    
     - Add some TODO items where needed.
    
     - Put GDB_STUB in a "Debugging" menu, no options should be top-level.
       There'll be more debug options later, I'm pretty sure.
    
     - Start converting help texts which are not user-visible to #-comments.
    
     - Re-order some options for more intuitive menus.
    
     - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them.
    
     - "Maximum reboot count" should proabably not be user-selectable, or at
       most if CONFIG_EXPERT (yet to be added) is enabled. It does definately
       not need its own "Misc options" menu.
    
     - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to
       run option ROMs.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd565145020a462725a9557b5370aca8e34e914d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Oct 7 16:00:40 2009 +0000

    Fix intel board build on kconfig. MAX_CPUS was missing
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66b74047d60133fbae6a2ab35452fbd6c666e9b1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Oct 7 15:30:58 2009 +0000

    Kconfig:
    - Add AMD Socket 754,
    - Fix MCP55 boards (romstrap)
    - Implement remaining MSI boards
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31f81a6de1515df2eebcf6e1b1afd545fc7a2714
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 7 14:36:16 2009 +0000

    Enable full ROM access on AMD CS5530(A) (needed for CBFS).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fdfaada706037287c74e2541a6151f16d93b9be1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Oct 7 14:13:36 2009 +0000

    More boards in kconfig, and moved -O2 flag for romcc into
    ROMCCFLAGS, so boards can override it where necessary.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99950c2192c93cdb19a5c49be09f8cba63ccf383
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 6 22:25:21 2009 +0000

    Use
      select UDELAY_TSC
      select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
    for all 440BX and i810 boards as per Options.lb.
    
    The UDELAY_IO / TSC / LAPIC / HPET setup will probably be checked
    and improved later when the kconfig transition is done. For now
    we keep the same values as in Options.lb.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e9a92545d0be44487f9bc5ad6ab26af5badf125
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Oct 6 20:48:07 2009 +0000

    Various fixes to Kconfig: All kconfig-boards should have a
    complete set of variables now, though they might still have
    the wrong values.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3d6ea8a737193e217be5d7003d827da215a7bab
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Oct 6 20:36:34 2009 +0000

    Remove duplicate device trees for Tyan s289x.  Remove pre-CBFS statements.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c04be9322cd69b3340d78db84b7663848170fe94
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 5 13:55:28 2009 +0000

    Backport facility to specify a local coreboot version suffix from v3.
    
    Tested on QEMU.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba6a93ddcb17b1e05480b57c1a47f8dc7084c355
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Oct 5 12:58:48 2009 +0000

    Remove svn:externals that pull in all kinds of useful tools that
    are not needed for building coreboot.
    
    The website tells you where to get them individually.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 652cd810f0b5b71fa46d780e70106d8aad5bcc67
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Oct 5 12:08:37 2009 +0000

    Without these fixes the w83627dhg driver (which is currently not used by any
    mainboard in the tree) does neither compile nor work.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84d69f78df3e56a1e696e189736de8e4c36f0e45
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Oct 5 10:23:36 2009 +0000

    fix building on Linux again, working around crude runtime OS detection.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b24e276503016618b30814d76f18e7ff13034158
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 5 00:07:12 2009 +0000

    PCI_ROM_RUN and CONSOLE_VGA are global options in Kconfig and
    should not be set in per-mainboard Kconfigs.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90950925c79b4d0b48c3d9dfc1e3de6a67212a97
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 4 23:50:06 2009 +0000

    The new CBFS based build system requires the whole ROM to be accessible
    in very early stages, otherwise the boot may hang like this because
    the CBFS headers cannot be found/accessed:
    
      Uncompressing coreboot to RAM.
      Jumping to image.
      Check CBFS header at fffedfe0
      magic is ffffffff
      ERROR: No valid CBFS header found!
      CBFS:  Could not find file fallback/coreboot_ram
      Jumping to image.
    
    This patch enables full ROM access on all 440BX boards right after the
    serial init (and before CBFS headers are parsed).
    
    Build-tested and runtime-tested on ASUS P2B-F.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24796fd364176ce8bb4f4eb727e0ba2ece188c08
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Oct 4 18:55:40 2009 +0000

    This does away with CONFIG_ROM_PAYLOAD_START and CONFIG_PAYLOAD_SIZE.
    Both were only really used in pre-cbfs, as the payload's size isn't
    relevant for the build process anymore.
    
    Various calculations in {no,}failovercalculation.lb are adapted
    accordingly.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 70b0cf23ce18371be96062476e4fdc88d4930683
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 4 17:15:39 2009 +0000

    Add initial kconfig support for all AMD GX1 boards.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5bb10282e978dd811246c921a16e535babfbac9a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Oct 4 12:30:44 2009 +0000

    This removes the uses of the buildrom utility and the coreboot.strip
    intermediate file.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0dd713330bb5fe6cca38b9165645535d5772192d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Oct 4 12:27:48 2009 +0000

    Remove a bit of pre-cbfs build system infrastructure.
    Payloads are compressed by cbfstool itself, no need for external tools.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c2d87495806b13ef7dc1bc29f0ea13cb2e1031b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Oct 3 21:13:36 2009 +0000

    Remove another FAILOVER variable. (trivial)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9ef2081bab5247a30dec92d09148224256ad92d
Author: Harald Gutmann <harald.gutmann@gmx.net>
Date:   Sat Oct 3 21:06:53 2009 +0000

    Add gigabyte/m57sli support to Kconfig.
    Whitespace fixes to devicetree.cb
    
    Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 37ea3410794758b8253ff5ad0e2918f760e39294
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Oct 3 21:04:13 2009 +0000

    Move HAVE_FAILOVER_BOOT and USE_FAILOVER_IMAGE from
    boards to global. It's not a per-board value, but
    compatibility stuff.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 689a7204855406c88b6e4e4439628b52fd8c0638
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Oct 3 16:27:48 2009 +0000

    Tell vgabios code in a couple of boards/chipsets about CBFS
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6768f39a4b5a5d6d1c2318f632f801fe1c8084cd
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Oct 3 16:24:58 2009 +0000

    Remove:
    - CONFIG_CBFS
    - anything that's conditional on CONFIG_CBFS == 0
    - files that were only included for CONFIG_CBFS == 0
    In particular:
    - elfboot
    - stream boot code
    - mini-filo and filesystems (depends on stream boot code)
    
    After this commit, there is no way to build an image that is not using
    CBFS anymore.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f3ec7b1a3771a317c2415e2366fa719582f29d1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 3 15:34:08 2009 +0000

    Remove duplicate and not too useful Kconfig board comments as
    per discussion on the mailing list.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c53d771c12cb01ec9e2a0e73bf183a28aca9414
Author: Ronald G. Minnich <rminich@gmail.com>
Date:   Fri Oct 2 15:46:10 2009 +0000

    Remove the Embedded Planet board.
    
    Signed-off-by: Ronald G. Minnich <rminich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6cc9c0ad28e0de786015691a10bc3f6588a27366
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 2 12:45:18 2009 +0000

    Remove left-over targets/motorola/*, fix Dell PowerEdge 1850 name.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4703bf16190f1a54faa6697b514ae9cce56c19ea
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Oct 2 03:36:30 2009 +0000

    Remove motorola PPC boards. These have lain untouched and unused by anyone
    for years.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5bf864e353036535551f97dbeaf2c069ba60d79d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 2 00:08:00 2009 +0000

    Drop remainders of the removed Totalimpact board. Fix typos.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 149d6754aa2022eb65aa4d9ed28dea153455d36b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 1 23:22:50 2009 +0000

    Support variables for MMX and SSE. These would be used in
    e.g. Makefile.romcc.inc to enable certain features.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4c5786b1f905aa90d788a12a3b8656d0f551a618
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Oct 1 22:34:18 2009 +0000

    Add some trivial numbers for 945, and Core2 Duo E8200 Intel parts
    
    Sorry, but I've forgotten where I found them. :\
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9536c06d18d96682da21023e9c3a83d4b78d3b58
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Oct 1 18:23:28 2009 +0000

    Add romstrap to asus/m2v-mx_se in Kconfig.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1df483d3a159100effb2cdebb680e8d95a5631c8
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 1 16:51:36 2009 +0000

    Get rid of the total impact. Vendor died 5 years ago and nobody cares.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20d5c2e14e808683ec633a5951f4ebd8a86cc433
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Oct 1 16:24:58 2009 +0000

    Fix Kconfig build for K8 boards.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3de8b7cb507bd463d9180ff6b4adb19d01b5761
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 1 15:59:49 2009 +0000

    OK, this builds and even looks right. dell needs its own Makefile.inc because
    it is a P4 and it needs SSE for romcc not to go into infinite loop.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a7ffd8dec6ee4f59e7b3edbee8b29328fb1d74d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 1 15:47:14 2009 +0000

    typo
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e14f58343bc4f6b63673e3e2af8f6ce66d0bb74c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 1 15:41:39 2009 +0000

    We need this to be Kconfig. The old way is not trusted by me.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61d66db14d9f8790982a299314101e8c5125c36d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 1 00:02:28 2009 +0000

    This is now set up more like the real hardware likes it.
    Some of this trickery was determined with serialice.
    There are several lovely undocumented features to the chipset.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26dd71c2d766f0630216aa5b8055b1f3b1e339ed
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Sep 30 21:36:38 2009 +0000

    Fix payload loading in various corner cases when working
    with the bounce buffer.
    In particular, the not-so-rare configuration of AMD boards with RAMBASE at
    2MB shouldn't crash anymore for payloads that take > 1MB in total
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aeab4fcca0ddea315ed3222eecd8ad74269c3924
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Sep 30 19:54:15 2009 +0000

    Compress stage if CONFIG_COMPRESS is activated, instead of
    relying on payload compression configuration (disabled when
    using abuild without payload, for example)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e23e37202cbad9dce81986efcd68e3a199db6605
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 30 17:14:24 2009 +0000

    Hm, quickfix to prevent the following crash, no idea yet what happens:
    
    *** glibc detected *** ././inteltool: double free or corruption (top): 0x08db0260 ***
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90d17407d8eeda82a6f4ba2170e97f609e8cc71b
Author: Maciej Pijanka <maciej.pijanka@gmail.com>
Date:   Wed Sep 30 17:05:46 2009 +0000

    Add initial inteltool support for Intel 440BX/440LX and 82371AB/EB/MB.
    
    Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2583dd209598249ca8380c3b58f90d15c9d55c2a
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed Sep 30 14:46:43 2009 +0000

    Add supermicro h8dmr fam10 target. This is largely a mashup of the tyan s2912
    fam10 and h8dmr k8 targets.
    
    Many, many thanks to Marc, Myles, Patrick and Stepan for all their help with
    this, and to Arne for doing the s2912 fam10 port.
    
    Build and boot tested. Abuild tested.
    
    There are a number of outstanding issues and caveats - see src/mainboard/supermicro/h8dmr_fam10/README.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 56f5fb734bb92efd147912794071ff57c35cab04
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Sep 30 11:21:18 2009 +0000

    Fix endless loop when trying to add a too large file to CBFS,
    and report the correct error code, and a hopefully helpful
    error message.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53ad9f585ddc3f40671adcd92a6341eadd229a06
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Sep 29 21:35:48 2009 +0000

    Make CONFIG_HAVE_HIGH_TABLES consistent in where and how it is set.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit babb03a5becfb21dff5528c906bd317e3238f0f9
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Sep 29 20:24:09 2009 +0000

    Remove pre-CBFS _vgabios_start and _vgabios_end.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e59f2e1f338e8e424437e6a2bfac83cc493c164e
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Sep 29 19:12:23 2009 +0000

    A keyboard controller fix to stop the code from waiting for a code that never
    comes.  Boot tested on SimNOW (fixes the hang there), and Tyan s2895.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 120bff83ff0c135c6248242416bbff2e61051d41
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Sep 29 18:15:06 2009 +0000

    Fix a number of board names in Kconfig (trivial).
    
    Also, simplify the M2V-MX SE Kconfig file a bit while I'm at it.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6842c0293c743ae9191d0d78fe38e1eba8391265
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Sep 29 17:28:13 2009 +0000

    Remove MAINBOARD_OPTIONS, which is a relic from early
    kconfig development.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e2357676fb9ccf202ac3dbc66c83a040f061a4e
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Sep 29 14:56:15 2009 +0000

    Remove some warnings.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e54871375a3416c576d1d1fbdfddda2dbcc7411
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Sep 29 14:38:10 2009 +0000

    More consistent use of "default n" and "select XYZ" in
    Kconfig files
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f2e435cc6bd77e9456577f4cd712b46bec82b61
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 29 13:34:56 2009 +0000

    Make the error messages somewhat less incomprehensible. I forget
    what they mean every time I see them.
    
    Add a proto. More work remains to be done.
    
    Build tested on dell s1850.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd75b1d4fbb636cd0a7ccb88a15c25ac304a5ef6
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Sep 28 22:36:40 2009 +0000

    Trivial config fix for Serengeti Cheetah.  Change a type and a default.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d05cc40390b23598d759b24418d2d0eda0f853ca
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Sep 28 21:51:39 2009 +0000

    Trivial config fix for Serengeti Cheetah.  Remove duplication, add a default.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 074d9136d7f431ab544132b976ea9f2d7d84a30a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Sep 26 16:43:17 2009 +0000

    This adds a simple script to build a default toolchain for coreboot
    compilation, to be independent of broken or missing OS/distribution
    tool chains.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bde683ce9fcc346096a07222047fa5a16aa74243
Author: Mohamed Mansoor <mansoor@iwavesystems.com>
Date:   Sat Sep 26 16:18:22 2009 +0000

    This patch changes following in getpir application.
    
    1 - Moved the check sum validation to probe_table function.
    2 - Proper handling of resources allocated.
    3 - Signature check is done in 16 byte boundaries.
    4 - irq_tables.c file is created only if a valid PIRQ table is found.
    5 – Makefile and README file are modified accordingly.
    
    Signed-off-by: Mohamed Mansoor <mansoor@iwavesystems.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5db685fedfe7f291719c90088bbf7618b31f3da6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Sep 26 15:52:05 2009 +0000

    * drop libgcc from coreboot_apc.o, not needed.
    * wrap libgcc calls into regparm(0) variants so that coreboot can be compiled
      with other regparm values
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 19a99c6965511db908a56018c0bb586ce11ee157
Author: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Date:   Fri Sep 25 22:21:47 2009 +0000

    check for ELF payloads in cbfstool
    
    Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
    Acked-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6bd571e060d65257c9a7ba0f87c991dbdac0b582
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 25 21:59:57 2009 +0000

    drop some dead code, clarify small comments and small cleanups to malloc.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0a181fd642d0c0780b4b88654d732cf625d1c862
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 25 21:57:25 2009 +0000

    improve lzma error messages. When coreboot panics because lzma decompression
    goes wrong, it might not be clear that it's lzma that failed, if the log level
    is low enough..
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45847beb4947442f6e7e78e04de50bfbc5798a7e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 25 19:53:59 2009 +0000

    Trivial fixups to get this board further along.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03bdc3e07003308da3a85e773811556a1e540200
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Sep 25 19:09:23 2009 +0000

    Fix build of romcc boards.
    
    Invalid option specified: -mcpu=-mcpu=p2
    romcc 0.71 released 03 April 2009
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88f55b2c12f94fd0451902ee2edc663f12e401f4
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Sep 25 18:43:02 2009 +0000

    some progress on kconfig:
    - northbridges are done
    - southbridges are done
    - Intel CPUs are done, with a design that the board only has to specify
      the socket it has, and the CPUs are pulled in automatically. There is
      some more cleanup possible in that area, but I'll do that later
    - a couple more mainboards compile:
      - intel/eagleheights
      - intel/jarrell
      - intel/mtarvon
      - intel/truxton
      - intel/xe7501devkit
      - sunw/ultra40
      - supermicro/h8dme
      - tyan/s2850
      - tyan/s2875
      - via/epia
      - via/epia-cn
      - via/epia-m
      - via/epia-m700
      - via/epia-n
      - via/pc2500e
    (PPC not considered, probably overlooked something)
    
    All of them only _build_, but some options are probably completely
    wrong. To be fixed later
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6bb3bdf869ab06a972520c5a58c6fc9b7cfe99f4
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Sep 25 17:24:08 2009 +0000

    Rename CONFIG_SERIAL_CONSOLE to match newconfig.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a21cc3d33e7d129ade7cebac5f1638044361654e
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 24 16:56:08 2009 +0000

    Make build_opt_tbl depend on config.h since it uses it.  This fixes:
    
        GEN        build/build.h
        OPTION     option_table.h
    Error - Range end (122) does not match define (125) in line
    checksum 392 983 984
    
    This happens when you switch from one board to another with incompatible CMOS
    defines.  'make clean' didn't help.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74fb8f224f11806b21038ecf117ba6380efce43d
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 24 15:09:11 2009 +0000

    Remove HyperTransport support from boards that don't need it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f0cfb22970db1cc91e7a73f139939ef13786fbb5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 24 14:05:19 2009 +0000

    Re-enable option table for the ASUS MEW-VM and fix build.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a57a0ac53edf40a69c5aac2bb83ccf9d6f35c4c9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 24 12:17:07 2009 +0000

    Add detection support for the SMSC FDC37M602.
    
    The ID was found on a Biostar M6TLD board (not mentioned in the
    FDC37M60x datasheet, though).
    
    Thanks Maciej Pijanka <maciej.pijanka@gmail.com> for the report.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cdceab8facb3938a387042e4f0ed7986493ef5a1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Sep 24 09:28:41 2009 +0000

    Trivial fix for kbuildall: initialize "i", not CURRENTARGET [sic]
    that isn't used anywhere.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 892b091e967cd2a54e23d22c8b37bfe12ebaaab5
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Sep 24 09:03:06 2009 +0000

    Make all Kconfig enabled boards build (tested with kbuildall).
    Also enable building individual boards with kbuildall for
    debugging.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ac7a2d2f848928fba5054d37343754fc4b2d557d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Sep 23 21:53:25 2009 +0000

    fix some wrong occurences of the FSF's address (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c641ee035fbef06ca0cbb42c921fb7028cf5216
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Sep 23 21:52:45 2009 +0000

    fix some wrong versions of the FSF's address (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 920279842dec7a2233e36eeba158ec399703b34a
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Sep 23 20:32:21 2009 +0000

    Fix the bounce_size global so that the bounce buffer works with CBFS.
    
    Make self_boot() static.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f250f191f833b1f8ceb5e8e4324e0abdac66cfe4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Sep 23 18:54:18 2009 +0000

    Looks like this should have become cpu init code after growing up. The
    remaining questions are:
    
    - Why was it never used?
    - Why is it in /src and not in /src/cpu/ppc?
    
    Given this is dead code and part of an unmaintained powerpc port, I consider
    removing it trivial. (The code really does not do much)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c13093b1484565382bd5e00722149442e46635ee
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Sep 23 18:51:03 2009 +0000

    simplify source tree hierarchy: move files from sdram/ and ram/ to lib/
    It's only three files. Also fix up all the paths (Gotta love included C files)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a946214ea09d4ca89a575525d0ae0469526e7dcc
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Sep 23 17:59:56 2009 +0000

    Add Kconfig support for Tyan s2881.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 422d0cb71262d27f0eff33ab324703b4a94374e5
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Sep 23 17:48:28 2009 +0000

    Separate payload compression from stage compression.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6ac964c89d27428e6ab36d6cdd489626bbd2900
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Sep 22 22:08:47 2009 +0000

    Fix compilation for serengeti when HAVE_ACPI_TABLES is set.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed03556fbf62c6150a2a9c6eb22e49e638262fbb
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Sep 22 21:29:32 2009 +0000

    src/Kconfig: Remove HT-specific options.
    src/cpu/amd/socket_F/Kconfig: Remove second occurrence of CPU_SOCKET_TYPE.
    src/mainboard/amd/serengeti_cheetah/Kconfig: Add HT_CHAIN_UNITID_BASE here, since it is board specific.
    src/mainboard/tyan/s289X/Kconfig: Fix typo and change APIC_ID_OFFSET to match old config.
    src/devices/Kconfig: Change default value of *_PLUGIN_SUPPORT to match old config.
    src/southbridge/amd/amd8131/Makefile.inc: Remove check since it was a typo, and the correct variable is checked in the parent directory.
    src/Makefile:Use devicetree.cb instead of Config.lb to generate static.c.
    
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a74ae635caeb0598fc1422356f13722c03262e8e
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Sep 22 18:53:50 2009 +0000

    failoverR.diff: Revert my failover change since Kconfig only supports fallback.
    kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45bb25f36f05df7bf9ccbf9e038169d6619aba48
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Sep 22 18:49:08 2009 +0000

    tables.diff: Add Kconfig dialogues for ACPI, MP_TABLE, ...
    Kconfig_bools.diff: Change some more ints to bools, change some default values.
    xip_size.diff: Make XIP_SIZE + XIP_BASE add up to 4GB.
    smp.diff: set CONFIG_SMP based on MAX_CPUS.
    
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3fec29cc963c95d44ff45151a1bc64d8988073ab
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Sep 22 15:58:19 2009 +0000

    This separates the code for each command in cbfstool. For the good and for the
    bad: It brings a certain amount of code duplication (some of which can be
    cleaned up again, or get rid of by proper refactoring).
    On the other hand now there's a very simple code flow for each command, rather
    than for each operation. ie.
    
    adding a file to a cbfs means:
     - open the cbfs
     - add the file
     - close the cbfs
    
    rather than
    
    open the cbfs:
     - do this for add, remove, but not for create
    
    create a new lar
     - if we don't have an open one yet
    
    add a file:
     - if we didn't bail out before
    
    close the file:
     - if we didn't bail out before
    
    
    The short term benefit is that this fixes a problem where cbfstool was trying
    to add a file if you gave a non-existing command because it bailed out on
    known, not on unknown commands.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 853270af390f9e200f4a165ec55d3b2fa5246c0b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Sep 22 15:55:01 2009 +0000

    * guard all mallocs in cbfstool
    * fix an issue that could lead to cbfstool writing outside of its allocated
      memory
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e0655e6ef815524107481856e40266ba23248f1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Sep 22 15:53:54 2009 +0000

    .. make abuild Kconfig proof for the time being.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dbdd91bc5bacbc1b583df00880224ced5464c6bd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Sep 22 15:53:02 2009 +0000

    back out some overzealous renames
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7cf8c58618c407f88828f448b871f8d168ee8950
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Sep 22 12:31:57 2009 +0000

    Kill dead comment.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 93c027279fb45205378e36766bd1ad29beea7695
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Sep 22 12:22:35 2009 +0000

    Help text for maximum and default console loglevel in Kconfig.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4d4770a3e6e0ba9d3c20f7c24cd77bbbe2a7e7b
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Sep 22 10:03:15 2009 +0000

    r4534 introduced devicetree.cb in every mainboard directory, but didn't
    copy any comment lines before the start of the device tree.
    Fix up amd/pistachio and technexion/tim8960.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 513e03bd96b9c2d2c3a9ad10961de4f76586ace3
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Sep 22 09:43:25 2009 +0000

    r4646 enabled early usage of pci_{read,write}_config{8,16,32}
    
    This allows us to change
    dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
            sm_dev->path.pci.devfn, 0x64);
    
    to the much more readable
    dword = pci_read_config32(sm_dev, 0x64);
    
    Clean up all PCI operations in mainboards based on AMD 690:
    amd/pistachio
    amd/dbm690t
    technexion/tim8690
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 00003ae7129802d7f943756c94b35372c1b1b053
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Sep 22 00:09:41 2009 +0000

    If no pci access method has been set for the device tree so far (e.g.
    during early coreboot_ram), pci_{read,write}_config{8,16,32} will die().
    This patch changes pci_{read,write}_config{8,16,32} to use the existing
    PCI access method autodetection infrastructure instead of die()ing.
    
    Until r4340, any usage of pci_{read,write}_config{8,16,32} in
    coreboot_ram before the device tree was set up resulted in either a
    silent hang or a NULL pointer dereference. I changed the code in r4340
    to die() properly with a loud error message. That still was not perfect,
    but at least it allowed people to see why their new ports died.
    Still, die() is not something developers like to see, and thus a patch
    to automatically pick a sensible default instead of dying was created.
    Of course, handling PCI access method selection automatically for
    fallback purposes has certain limitations before the device tree is set
    up. We only check if conf1 works and use conf2 as fallback. No further
    tests are done.
    
    This patch enables cleanups and readability improvements in early
    coreboot_ram code:
    Without this patch:
    dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
            sm_dev->path.pci.devfn, 0x64);
    With this patch:
    dword = pci_read_config32(sm_dev, 0x64);
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6afb698433ba005cdfa00296fdfe07a6e11a70db
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 17 18:30:23 2009 +0000

    I forgot to add CONFIG_VGA_BRIDGE_SETUP to the old build system.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 079300b987dd93324c354fd725fc12897757aad9
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 17 16:59:07 2009 +0000

    Remove warnings from Kconfig.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 28412f58b62c73cee47ad3f09a4a056e64d422a6
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 17 16:54:46 2009 +0000

    Separate CONFIG_VGA_CONSOLE from CONFIG_VGA_BRIDGE_SETUP.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a758ca2ba9adc5b6ad01e5fe2515e0d636fffad2
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Sep 17 16:21:31 2009 +0000

    Move VGA BIOS settings from the payload menu into it's own menu
    
    Remove dependency on PAYLOAD_ELF so that config items are shown.
    Build tested. With this, coreboot.rom has a VGA BIOS optionrom added.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a1af7b877192143fdb12f98062caa458a1e02e0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 17 15:35:08 2009 +0000

    There was a missing addition of the size of the .notes.pinfo
    section header which could lead to corrupted malloc arena.
    
    Also, make cbfstool always build with debugging on. Performance
    is not an issue here. Don't strip it either.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b796a06cc6daa6cc7ee379fb64faa854f06556ff
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 17 00:28:29 2009 +0000

    This is a patch for killing IPMI on the s1850 -- or at least geting the BMC
    out of the way of the serial port. Tested extensively in user mode.
    Works and gets the BMC out of my way, which is good, because there
    are few more useless things than IPMI and the BMC.
    The BMC, all by itself, is the cause of most of our problems in booting
    and talking to these nodes.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f76a567953764d56eb50065577955c8b2db11f1
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 17 00:24:52 2009 +0000

    copyright name error.
    I don't know what else to do for files generated by programs ...
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e9910e5c9e9100ddeb8d90fb3ddb5a57a68771f
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Sep 16 20:18:03 2009 +0000

    kbuildall is a utility that generates default configs for all
    boards, builds them, and keeps the config and build logs around and
    creates a roster of all boards and their build status.
    
    abuild does this for the newconfig based buildsystem, kbuildall does
    this for kconfig/kbuild.
    
    It's supposed to be put in the tree as util/kbuildall/kbuildall, and
    called like that (ie. from the top level directory).
    
    The results can be found in kbuildall.results/ in the toplevel
    directory, the roster is called _overview.txt ("_" to make sure it's
    sorted before or after all the board files)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab13458c34961cd709604c68059a9b209607e0b9
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Sep 16 08:19:07 2009 +0000

    Build cbfstool with debug flags and don't strip the executable
    from any symbol information.
    
    Variant of Ron's patch.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 057712a3b7450606fb88b10ce82c92885e3a913e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 15 23:38:27 2009 +0000

    This is an otherwise dead platform. I'm just committing the basics that
    let it build.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b261205f5e447022f5828f6ccc5c1a6407a30ed3
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Sep 15 20:40:31 2009 +0000

    Don't mix int and boolean for kconfig variables. It might work, it might not.
    trivial change.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45d8a83b29e9eb2e20f4ca39914a42561a2c1f79
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Sep 15 08:21:46 2009 +0000

    More error checking when trying to open files in
    cbfstool. (trivial)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd9c9b8ff8326c07bd63b39ab85bd68f6fb6a011
Author: Marc Jones <marcj303@gmail.com>
Date:   Mon Sep 14 17:00:04 2009 +0000

    Use the coreboot pci config read/write functions instead of direct cf8/cfc
    access. The fam10 pci functions will use mmio and do not have SMP pci access
    issues.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fea8a4f8d32112d7dfa002583fa1da2de2c10f3f
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Sep 14 14:15:43 2009 +0000

    In the mainboard selection, the selected mainboard is printed twice in
    certain cases, this patch eliminates the second mention.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 77ee932a22ee321515191e358089028a85fd0fc9
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Sep 14 14:13:13 2009 +0000

    Build cbfstool with native data size. Trivial change.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7b56dd8fbe123958e196f396dab5ff3000b68dd
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Sep 14 13:29:27 2009 +0000

    New cbfstool. Works without mmap or fork/exec and
    supports fixed location files. Some parts are salvaged
    from the pre-commit version (esp. stage and payload creation),
    others are completely rewritten (eg. the main loop that handles
    file addition)
    
    Also adapt newconfig (we don't need cbfs/tools anymore) and fix
    some minor issues in the cbfstool-README.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c8d4a05f8f5df06bd98f8ee7d5ef46e61986e6b0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Sep 10 11:21:48 2009 +0000

    fix compilation issues for pirq checker tool (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8008f88df8ff6d7cbdfced5717775a446f2254c6
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 4 19:34:43 2009 +0000

    Fix clean rules for the tex files.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 105c155a0ca21c6fe7d5394cfa2d084bdbd035b3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 4 19:25:51 2009 +0000

    Fix various build issues and errors in LinuxBIOS-AMD64.tex.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6dd5223b0782a653f4eec862b47b394f8d32d837
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 4 16:30:31 2009 +0000

    Use driver-y instead of obj-y for model_6xx_init.o.
    
    Otherwise booting (but not building) fails:
    
      Initializing CPU #0
      CPU: vendor Intel device 665
      CPU: family 06, model 06, stepping 05
      Unknown cpu
    
    This patch was tested to fix the issue on MSI MS-6178.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eed10364ceffbc8f3f89742eba3efc0860e84cba
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Sep 1 15:29:12 2009 +0000

    As more users of Asus M2V-MX SE emerged. Here is long pending patch I wanted to
    write. It boots the SB/NB V-link performance to full duplex 533MB/s. (in fact x2
    for FDX)
    
    The default was 266MB/s but half duplex only. If you encourage any stability
    issues we need to look into fine tuning the bus. The values are VIA recommended.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 37f3935029cef0616fa36b9c822496e3e51f03ba
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Sep 1 10:03:01 2009 +0000

    port msrtool to darwin.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    with minor changes to allow 32bit and 64bit compilation and (I hope), Peter's
    concerns addressed.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e95eb616cc987072a1a17f8b98854645fb82bfce
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Sep 1 09:57:55 2009 +0000

    * Add OSX/Darwin support
    * Add DESTDIR support
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4db6cbd26c2913549cd3d58c6943e766ccdc6c5e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Sep 1 09:54:21 2009 +0000

    nvramtool:
    
    * Add OSX/Darwin support
    * Add $DESTDIR support
    * Clean up make install/spec
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7f2f258d8b44218c2efb83cfb276890fd4fb95c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Sep 1 09:52:14 2009 +0000

    Clean up Mac OS X support of inteltool
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    Some minor modifications to allow 64bit/32bit compilation on Darwin
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b2aedb1a3f2409b549c4094654281893b82c7435
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 29 15:45:43 2009 +0000

    add i810 and ich0
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 669c4a954ec6b57f0156844bea4f656f3aa9ccca
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Aug 29 03:00:51 2009 +0000

    File I missed committing.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ed39d9786508b273ede0fedc2a0078213418f6d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Aug 29 02:59:35 2009 +0000

    This is the final set of changes to allow rumba to build. Rumba is not
    tested. I also addressed questions raised by Uwe:
    TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
    UDELAY_TSC
    
    Are now defined as booleans in src/cpu/x86/Kconfig and can be selected in
    the mainboard Kconfig. The remaining question of Uwe's is a deeper
    problem:
    
    ---
    We'll have to check if this works. From a quick glance
    the Rumba does not have the mmx related lines (which _are_ in
    Makefile.romccboard.inc, though):
    
    crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
    crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
    crt0-y += auto.inc
    crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
    ---
    
    We're going to need a whole variant of this standard mainboard OR
    we're going to have to make (some) of the unconditional includes above
    conditional.
    
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e7f5709e148c165b38cc832b71e13804c03a90bc
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Aug 29 02:47:57 2009 +0000

    Set the mainboard/amd directory up to support more than one.
    
    remove Config variables now defined elsewhere.
    add rumba Kconfig and Makefile.inc
    
    rumba won't build until my earlier patches are acked.
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea47143f15a5f14aaf76cd4eeab2cfca7218a4ae
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Aug 29 02:44:08 2009 +0000

    Fixes per Uwe's comments.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5b1d51ba2e9ac22c7878cd5e8d9c51d8269bb76b
Author: Arnaud Maye <arnaud.maye@4dsp.com>
Date:   Fri Aug 28 20:42:21 2009 +0000

    This patch adds VGA and PS/2 Keyboard/mouse support to the already existing intel truxton (ep80579) dev board.
    This patch tries to improve the pcie portA configuration.
    The Matrox G550e PCIe gfx card shipped along with the dev board is supported.
    
    Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b1c382cc083f391405c29b2c83892e74904e801
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Aug 28 19:00:59 2009 +0000

    r4534 introduced devicetree.cb in every mainboard directory, but didn't
    copy any comment lines before the start of the device tree.
    Copy over the comments for amd/dbm690t.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84a0f54b3b317b455d4e17a75d89847a2711ae98
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Aug 28 16:38:42 2009 +0000

    Add kconfig support for all Intel 82810 (i810) boards.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 177aa3ad79678207ba1c0e9a97a56c4a7f8959e5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Aug 28 15:22:31 2009 +0000

    kconfig: Board name variable fixes and updates (trivial).
    
     - Use alphabetical order.
     - Drop non-exisiting vendors.
     - Add missing vendors (Mitac, Soyo, Technologic, TeleVideo).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 07b8c2d26bbbe5b6bb9b96175a7174bf66c75f02
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Aug 28 14:46:59 2009 +0000

    This is the beginning of support for Geode and Kconfig in v2.
    
    It also brings in the vsm from v3, which was a much cleaner cut.
    
    Over time, I hope to bring all the code back from v3. I have
    some rumbas at home and want to use them.
    
    I have a patch which comes in next that makes the rumba build.
    
    Note that I am holding the src/*/amd/Kconfig patch until these get merged.
    These have no impact on the current system.
    
    Note that this is not complete but I want to fill in the blanks bit
    by bit.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d5ced0e23d7c35207ce0b1f0b213bc29cef6534
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Aug 28 14:40:04 2009 +0000

    Move DCACHE support into the cpu family for AMD model_fxx.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e6804955c48f735074a6c56788bc9f65a412bbe2
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Aug 28 14:36:12 2009 +0000

    Add Kconfig support for PCI option ROMS.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 876d7e9658c4e27684393f04220b32aa11edf18c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Aug 28 14:23:38 2009 +0000

    Move some config variables that are in one or two mainboards to
    more rational places. The goal is to reduce the number of Config
    variables defined in mainboard Kconfig files to the absolute minimum.
    
    This has the side effect of making SERIAL_POST a menu item, which is nice.
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 05c1e9c81c78a01c7b00fd63b7d2513f52a5d2fb
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Aug 28 13:42:24 2009 +0000

    Silence unneeded #warnings, change to code comments (trіvial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 18c585b78a82c217ea32a8d529fde56b117630cc
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Aug 28 12:48:02 2009 +0000

    The resource allocator complained about 0-sized fixed
    resources before actually validating if the resource is
    a fixed one.
    
    No harm done, except some confusion of the user (in this case: me).
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d5f9f0024d4de97401871069eb462f53896d5269
Author: Arnaud Maye <arnaud.maye@4dsp.com>
Date:   Fri Aug 28 10:17:03 2009 +0000

    Fix broken compilation. As CBFS is now enabled by default,
    CONFIG_FALLBACK_SIZE should be equal to CONFIG_ROM_IMAGE_SIZE and not
    CONFIG_ROM_SIZE
    
    Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com>
    Acked-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa1eddac43349a71ec049344835274f8b615ffa8
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Aug 27 22:41:56 2009 +0000

    Correct typos /SMCSC/SMSC/ in Kconfig.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc23c95d2fa52453a3333c9cb91a82ab7372985c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 27 22:36:13 2009 +0000

    For Carl-Daniel: make x86emu silent again.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ec3f67294968a0c5346b9aad2621724e6340ef4
Author: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Date:   Thu Aug 27 22:19:23 2009 +0000

    Added support for the AMD S1G1 socket in kconfig
    
    Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea906b0e4eec2b7e657a145009f401c793aac167
Author: Cristi Măgherușan <cristi.magherusan@net.utcluj.ro>
Date:   Thu Aug 27 21:39:20 2009 +0000

    Added support for the AMD RS690 and SB600 southbridges in Kconfig
    
    Signed-off-by: Cristi Măgherușan <cristi.magherusan@net.utcluj.ro>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d30722d445709c7a6f3f204465823cc15ccbeeab
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Aug 27 14:22:56 2009 +0000

    Change some more image names to "fallback" (not "image").
    
    Also, if there's only one image, it should be named "fallback", not "normal".
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2447a9071b6f731620f6b57761bcd67faf246228
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Aug 27 13:14:09 2009 +0000

    Revert test for pre-commit hook functionality. Commits are now checked for proper
    sign off again. This is trivial, of course.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 192135007d511dbed97b20c723d3711531d1b8b7
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Aug 27 13:07:40 2009 +0000

    test
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66b9abc5dbea72287c250c8379c204113923409a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Aug 27 13:02:28 2009 +0000

    Another trivial patch to fix up the x86emu cleanup.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39ec29c47ef056f83500a5f1efdbf6b37f9a1f77
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Aug 27 12:10:50 2009 +0000

    Clean up some DCACHE related options.
    In amd/serengeti_cheetah there were duplicates, and USE_DCACHE_RAM is a
    boolean value, so make it so.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20c03fb923730f81e04b1e3ab997041eeb55d45f
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Aug 27 12:10:05 2009 +0000

    Clean up the kontron Kconfig
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c36305cdf866aa6c5136f303c98d389b1c1504e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 27 11:34:09 2009 +0000

    coreboot was still using an old set (obsolete since yabel) of x86emu includes
    instead of the versions in util/x86emu. Clean up this mess.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b883d4c433e39bfeb12060bc7c2662d099d0534d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 27 11:23:06 2009 +0000

    Make all those locally used functions static instead of exporting them. (triv)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98457a5f3cb99518a458dce24979aff23fe9dcd9
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Aug 27 07:42:45 2009 +0000

    Rename "image" image to "fallback", so CBFS can find it.
    Thanks to Carl-Daniel for finding this.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a5b8f5ba9a829c0053227e3111913d37b09ed6d
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Aug 27 04:30:47 2009 +0000

    The new resource allocator helped me find a bug in SB600 diagnostics.
    The SB600 SATA code printed that two BARs had the same address because
    it didn't mask the correct number of bits in the BAR.
    Functionality was not affected, but the debug output was incorrect.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d0ede5f132b2efe57430f224dd7068550c95916
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Aug 27 02:47:35 2009 +0000

    amd/pistachio: fallback image must be called fallback.
    
    Thanks to Stefan for providing the original fix for amd/dbm690t
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 932b8fad725c24cc84a236753fec247a5fb142a3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 27 01:47:41 2009 +0000

    fallback image must be called fallback.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 62b3513d63088ce7c0b324e2a6a88e31fec5a328
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Aug 26 18:14:30 2009 +0000

    Remove a couple of CONFIG_ prefixes that shouldn't have happened.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bca3b92df2b4af91d08a7bde76e4a98a9671d946
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Aug 26 17:10:00 2009 +0000

    Add kconfig support for all missing Intel 440BX based boards.
    
    This includes:
    
    soyo/sy-6ba-plus-iii
    a-trend/atc-6240
    a-trend/atc-6220
    gigabyte/ga-6bxc
    biostar/m6tba
    azza/pt-6ibd
    tyan/s1846
    abit/be6-ii_v2_0
    compaq/deskpro_en_sff_p600msi/ms6119
    msi/ms6147
    asus/p2b
    asus/p2b-d
    asus/p2b-ds
    asus/p3b-f
    
    The Makefile.inc for all of them are _exactly_ the same, so I made a common
    src/mainboard/Makefile.romccboard.inc (maybe needs a nicer name). I also suspect
    that many other romcc-based boards will be able to re-use this Makefile.inc.
    
    Apart from the board name, most boards only differ in the Super I/O that's
    being used and the IRQ_SLOT_COUNT value. The Tyan S1846 is a bit different
    as it doesn't have an irq_tables.c.
    
    I also dropped the broken MS-6178 kconfig stuff for now, I'll submit a
    proper config in another patch.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d7e49b40b14bc96a4b463fabd2f8021be63a3137
Author: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Date:   Wed Aug 26 16:55:06 2009 +0000

    Asus M2V-MX-SE support in Kbuild
    
    Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f608205c351fdc8e832b4753a3f79b73ea63482b
Author: Libra Li <libra.li@technexion.com>
Date:   Wed Aug 26 16:04:47 2009 +0000

    Enable Direct TMDS for the RS690, which allows to display on HDMI and DVI
    monitors.
    
    Signed-off-by: Libra Li <libra.li@technexion.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc4bb0d43f3673d425ac8509762563b9053b3fb0
Author: Harald Gutmann <harald.gutmann@gmx.net>
Date:   Wed Aug 26 15:35:36 2009 +0000

    Set the LIBGCC_FILE_NAME to fix problems with libgcc.a.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 602d2b8dc2404ff3de073e84721ba0358faea161
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Aug 26 14:11:48 2009 +0000

    Fix vendor name config variables to match company name (trivial).
    
    Any whitespace or dashes are replaced with underscores.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 879c17784f88994c03e90aca85710d7aac6582de
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Aug 25 19:46:50 2009 +0000

    Correct typos /subdir/subdirs/ in documentation and util/x86emu/Makefile.inc.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b7418ecc6f0c42b5ab6ebccb1a33d1422040404
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Aug 25 19:38:46 2009 +0000

    Use the gnu make .SILENT: mechanism instead of requiring
    $(Q) in front of every silent line.
    
    make V=1 or make Q="" still make make noisy again.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 698c0e0e5aa0492ce9ecedce787d452e87adc6eb
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Aug 25 17:38:24 2009 +0000

    Make PCI_ROM_RUN a boolean (like it is elsewhere) which
    is the correct choice. Avoids type problems in kconfig
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2389cfe8a76600c3c75ffbba964fcd7c67f148c8
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Aug 25 16:18:11 2009 +0000

    Add microcode to socket_940 and socket_F.  Part of the last reverting commit.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5cc74faeabee9d3841dd736300414ee9f8d91998
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Aug 25 16:04:45 2009 +0000

    Revert socket abstraction.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fe2664a5f244f27fd37b39135b5af734235c0c95
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Aug 25 15:03:20 2009 +0000

    Improve build output.
    
    The Makefile prints need to be @printf -- not $(Q)printf -- as they should
    
     (1) be printed always (with 'make' _and_ with 'make V=1'),
    
     (2) but the printf command itself should not be printed, hence the '@'.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20a1ae88404c6ca0e97191516ae9cda440568df5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Aug 25 14:51:25 2009 +0000

    Replace PIRQ_TABLE with HAVE_PIRQ_TABLE, the former doesn't exist.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 673c831f217abd244e4c64a7223c0d2b6d2a44c6
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Aug 25 14:41:38 2009 +0000

    Add vendor strings in mainboard/Kconfig.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9f8ecf5eb9364683fbaea881772d2550ae6339e5
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Aug 25 14:22:58 2009 +0000

    Add support for AMD Socket 940.  Move common files to model_fxx.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca5d9fb74ab3fc74c5ea74cfb320eb1f33ae8d8d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Aug 25 13:53:14 2009 +0000

    Properly check for the LZMA compression variable, and fix a print
    message for the VGA ROM that would print a useless NULL string.
    
    Signed-off by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7fec825febefd3c7dd2e82539da45f1ec9415e7
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Aug 25 12:25:36 2009 +0000

    Add kconfig support for ASUS P2B-F.
    
    Only build-tested so far, not tested on hardware.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9d4c2bad899802ecbac922ae180825bf8112a71
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Aug 25 12:19:28 2009 +0000

    Fix copy-paste error in src/cpu/x86/Kconfig.
    
    That file defines XIP_ROM_BASE twice, but the latter definition should
    be XIP_ROM_SIZE (not *_BASE).
    
    These exact two definitions are listed in src/Kconfig already, though,
    so maybe one of the two locations should remove them?
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8f5b620a2fc7938d636531036047335b7b8aefb
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Aug 25 12:18:05 2009 +0000

    Only build option_table.o if CONFIG_HAVE_OPTION_TABLE is 'y'.
    Not all boards have an option table (cmos.layout).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1476a9ecc410ab1c8443332fc8e71fc5d16442e1
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Aug 25 04:12:55 2009 +0000

    Without this patch, if we only got a DIMM in Channel B, memory can not be
    set up correctly. Now it can. Please test it.
    
    Moving "mct_AfterGetCLT(pMCTstat, pDCTstat, dct);" out of the "if" is the
    key point.
    Changing the Get_DIMMAddress_D(pDCTstat, i) to Get_DIMMAddress_D(pDCTstat, dct + i)
    doesnt seem to take any effect. But I believe this is what it should be.
    
    And a duplicated semicolon is removed.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d7ae4d96ee0b3d902034bc6878a84fbfa0d45fb
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Aug 25 01:06:39 2009 +0000

    Remove pretty useless kconfig help strings, fix some vendor names (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ec2c2b998086415047c05aca4ca7082de329e5a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Aug 25 00:53:22 2009 +0000

    Various Kconfig and Makefile.inc fixes and cosmetics.
    
     - Whitespace fixes, remove trailing whitespace, use TABs for identation
       (except in Kconfig "help" lines, which start with one TAB and two spaces
       as per Linux kernel style)
    
     - Kconfig: Standardize on 'bool' (not 'boolean').
    
     - s/lar/cbfs/ in one Kconfig help string.
    
     - Reword various Kconfig menu entries for a more usable and consistent menu.
    
     - Fix incorrect comment of NO_RUN in devices/Kconfig.
    
     - superio/serverengines/Kconfig: Incorrect config name.
    
     - superio/Makefile.inc: s/serverengine/serverengines/.
    
     - superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/.
    
     - mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string.
    
     - mainboard/via/epia-n/Kconfig: Fix "bool" menu text.
    
     - console/Kconfig: Don't mention defaults in the menu string, kconfig
       already displays them anyway.
    
     - Kill "Drivers" menu for now, it only confuses users as long as it's emtpy.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50d0b8ce17dada0f5097ebaaf8de9fcbb9986389
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Aug 24 18:36:02 2009 +0000

    Add support for Nvidia Southbridges to Kconfig.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa9f12ef7579aa09f64997c419c21108d5dfe385
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Aug 24 16:51:27 2009 +0000

    Add support for AM2 CPUs (I fixed the 0x11 issue).
    
    Signed-off by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0696bca90a07e9814ba61443f6dd5dc3265fa9df
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Aug 24 16:21:12 2009 +0000

    The variable is already checked when including the socketF subdirectory.
    
    Signed-off by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 44163f7f7198b53735820aaa84e232547fec73d8
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Aug 24 15:25:11 2009 +0000

    Update Coreinfo to use TAG_FORWARD in tables.
    Update the ramdump function cursor functions and make the address hex
    instead of decimal
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bab2bef484f2a6279bb3e7445f72d0c35c7c40fa
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon Aug 24 06:30:37 2009 +0000

    This patch is about the DA-C2 and RB-C2. Chip with install processor
    Revision ID of 0x100F62 is DA-C2, instead of RB-C2 which was incorrectly
    defined in raminit_amdmct.c. RB-C2's ID is 0x100F42. The Erratas applied to
    them are almost the same.
    
    Issues:
    1. I really dont know what their nicknames are (Shanghai C2 or something).
    2. About the mc_patch_01000086.h, I dont know if it is allowed to be released.
       If you really need it, please contact AMD Inc to see if it is public.
    3. My RB-C2 is Socket type AM3, which needs DDR3 support. Probably your RB-C2
       doesnt need DDR3. If it does and you really need it, please contack AMD Inc
       to see if it is allowed to release DDR3 code.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebed2dc72056228761e02c5e767f84a1b4187964
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Aug 21 18:08:49 2009 +0000

    Change the intel cpu makefile.inc so that it fits the model better.
    - intel/Makefile.inc only mentions sockets
    - those sockets are conditionally included
    - makefile.inc in socket directories are almost all unconditionally included
    - Get rid of if where possible, use -$(CONFIG_VARIABLE) instead as per Kconfig
      standards in linux kernel
    
    See the Kconfig.tex documentation for questions.
    
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b028a450f4f966541c3de243f8063cbcd3e7bd2
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Aug 21 14:59:14 2009 +0000

    Trivial spelling corrections.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d82e12858f34770a38dc93136f686ebab0e971ed
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Aug 20 18:05:31 2009 +0000

    This goes a surprisingly long way to building the epia-n. It also has
    important corrections to the Kconfig and Makefile.inc that were there. I
    would like to go ahead and get this in, because I don't want anyone to
    continue using what is in the upstream tree as it now exists.
    I also tested old-style build with this and it did not break anything.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b203c2f95e8174bff1170a47d06186a315de4997
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Aug 20 14:48:03 2009 +0000

    20090819-2-trim-down-cbfs:
    CBFS uses sprintf, which requires vtxprintf, which requires (in the
    current design) a nested function. That works on x86, but on PPC this
    requires a trampoline. In the ROM stage, this is not available, so
    remove the single use of sprintf and replace it with a direct string
    handler - it's only used to fill in fixed-length hex values.
    
    20090819-3-more-noreturns-in-romcc:
    Mark two more functions in romcc as noreturn. Helps clang's scan-build a
    bit
    
    20090819-4-cbfsify-ppc:
    Make PPC use CBFS. Support big endian ELF in cbfs-mkstage. Untested and
    not complete yet.
    
    20090819-5-fix-ppc-build:
    The CBFS build system requires ROM_IMAGE_SIZE to have a somewhat
    plausible value.
    
    With fixes to tohex* functions as discussed on the list, and correct
    function names.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce9d8640b1cf14419783d839afc0c53184c70bbf
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Aug 19 19:12:39 2009 +0000

    Add an error message if there is a zero-sized fixed resource.  Fix the existing
    example of one.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6bd93f4753a32c097f0cb0d6245969b7fd643e49
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Aug 19 17:29:41 2009 +0000

    Don't let zero sized fixed resource mess up the allocator's memory map.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d26053a10f36d27262324d4176fd14cfce4dffed
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Aug 19 14:08:42 2009 +0000

    Config-abuild.lb doesn't need to override ROM_IMAGE_SIZE.
    Trivial change
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7467664c09bf74abda63c2fb940196cb2dae1130
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Aug 19 13:40:20 2009 +0000

    Reduce size of the romstage on various boards that fail to build on QA.
    This eliminates 56kb of padding in the bootblock.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69a031c4e1a85beba3f24ed27781f5fb3e2a642f
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Wed Aug 19 07:08:10 2009 +0000

    The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instead of
    F2x[1, 0]9C_x0C. It is a obvious bug. Some typos are also fixed.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c5f3f19d0f80f96c00f9d9650b924c2978429f49
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 18 17:15:39 2009 +0000

    Correct usage of Makefile.inc and add support for cn400
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc9cabd6c3239e7cfd9fc9efd31f19c0c4167152
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 18 17:14:58 2009 +0000

    Add via south support. Correct usage of conditional variables.
    Note the makefile.inc may be out of date given the new commits of code
    today, but this is what was signed off ...
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c2e738653df435afec8a8f212d0c2c69aa9645c
Author: Jon Harrison <bothlyn@blueyonder.co.uk>
Date:   Tue Aug 18 15:12:13 2009 +0000

    Add the rest of the files.
    
    Thanks Jon.
    
    Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1825be291f49f892fa8c048974239aa0daa4de56
Author: Jon Harrison <bothlyn@blueyonder.co.uk>
Date:   Mon Aug 17 17:09:46 2009 +0000

    Get the Via EPIA-N(L)/CN400 to a reasonable level of maturity::
    
    Tested on Via EPIA-NL8000EG with FILO payload booting FC9 (2.6.25
    kernel) from SATA HDD.
    
    ACPI is working for PCI interrupt routing, some memory stuff and
    Soft-Off.
    USB/SATA Working
    VGA Console Working
    X Working via Onboard AGP
    
    Removed dsdt.c, fixed some whitespace.
    
    Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5f4e77bff5247dc155873f668a0ccf35400cd11
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Aug 17 15:42:18 2009 +0000

    Add more docs, this time for southbridge.
    No real difference from northbridge.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e70471b6454a3c4842e2ddd932ed2a6b0a7d86cd
Author: Thomas Jourdan <thomas.jourdan@gmail.com>
Date:   Mon Aug 17 15:19:52 2009 +0000

    Move CBFS header to a safer place.
    
    Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5034d4703df3d9232be2c02dc805a18196b06d2
Author: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Date:   Mon Aug 17 14:47:32 2009 +0000

    Remove unused normal image option in Kconfig
    
    Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 488c36c8e755106ff85fc4e6873af75c2b6a79dd
Author: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Date:   Mon Aug 17 14:46:13 2009 +0000

    Allow setting up a VGABIOS image in Kconfig
    
    Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e92ff343eed84f068070224bd94839de4e931c3
Author: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
Date:   Mon Aug 17 14:33:03 2009 +0000

    Add 4MB ROM image size to Kconfig
    
    Signed-off-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 10c41fa0088f20aa6b7f89bab7fbba1c708574e9
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Aug 13 16:02:24 2009 +0000

    Most of the changes here are trivial, but the white space changes would be harder to undo than to do over.
    
    I changed all groups of 8 spaces to tabs, then all tabs to two spaces so more of the device tree fits on the page.  It could have been three or possibly four, but the largest indents I found were 6 tabs, so 4 is a lot of the space on the page.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fabde37cb8af695c605fc04fa005930de057b9a3
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Aug 13 15:29:01 2009 +0000

    - AMD selected a couple of options that are incompatible with QEmu (and
    probably others). Only select them for AMD
    
    - Make the bootblock smaller (only one copy of it), and don't pad the
    bootblock using dd(1), but top-align inside cbfstool, to reduce
    dependencies on unix tools.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a5c8bb39b5ec7d971971a56ecf386a71a2bc5a32
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Aug 13 07:33:55 2009 +0000

    Fix some conflicting types of variables
    Remove the normal/* files from the image. they're just
    copies of fallback/* anyway.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b6e03200a49d2f682633d102a193afc98e38594b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 12 20:25:24 2009 +0000

    \\ are not escaped in a sane way between fedora and ubuntu! Just create
    these files to make sure that we don't get idiotic problems.
    
    Fix things so they build.
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 245a7da495527250ee5303b45c1829a463b797b5
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Aug 12 17:16:05 2009 +0000

    Remove duplicate file, adjust Makefile to use the original copy.
    Keeping identical files around will only bite us eventually, when they
    get out of sync. See coreboot-v2 history for examples.
    
    Trivial and build tested.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 109ab317e7544c3290700b83240849629d769494
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 12 16:08:05 2009 +0000

    drop extra whitespace at end of line for i945 + ICH7 (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd4519b5ef086fbec60041570c6c9d73d6a80a79
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 12 15:56:17 2009 +0000

    This now builds.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f6572ec8bc6eb2acd3a7882445913b0b9fe0d91
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 12 15:39:38 2009 +0000

    Fix multiple missing files and errors from the recent commit. This happened
    when Patrick's tree and mine got out of sync.
    
    Link stage still fails.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a94843820fbad070d80f6e59ec7d6558e6afdab
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 12 15:26:31 2009 +0000

    Missing files from last patch.
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0588d19abef62dad63a7794a37bdd6a71c526d9e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Aug 12 15:00:51 2009 +0000

    Kconfig!
    Works on Kontron, qemu, and serengeti.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    tested on abuild only.
    
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 38cd29ebd7282333650cf11ed50c7f2fd4031e80
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 11 21:28:25 2009 +0000

    Don't pull in x86emu from a foreign directory anymore. This
    produced numerous problems in the past, including the fact that
    x86emu doesn't work in v3 anymore even though it lives in the v3
    repository.
    
    Since this is a cross-repository move, keeping the history in the v2 tree
    would make life hard for everone. So check the v3 repository for x86emu history
    since the merger. The his commit is based on an svn export of r1175 of the
    coreboot-v3 repository.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b339e10f04869a3d8da31e7d52831c32c57302a2
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Aug 11 17:35:02 2009 +0000

    Enable CBFS everywhere. All boards compiled for me (abuild tested),
    and we will fix issues as they appear.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 401c8d1da2a5292649498ec3a2c8414bd8ecd62c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Aug 11 17:32:26 2009 +0000

    cpu/amd/model_lx used its own routine for copying coreboot_ram. This
    change makes it use the generic infrastructure.
    
    NOTE: If you're bisecting issues on geode-lx circa jumping to coreboot_ram,
    this change has a high probability to break that place - so look into it.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit edee9eb350406e8c1598bb455815469c13c089b9
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Tue Aug 11 03:18:11 2009 +0000

    The code between #if and #endif is only about UMA mode. The CONFIG_GFXUMA should be 1.
    We have another mode called side port mode. It is When the CONFIG_GFXUMA is 0.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dabae0d8fc0fce8f56bd43239cf965814c433d38
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 6 11:36:33 2009 +0000

    fix for the case that CONFIG_TTYS0_DIV is defined in mainboard's Config.lb
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 052d591e64e6f9bc1b1b50df1794aaf51efea0bc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 5 13:10:38 2009 +0000

    fix buggy comment in libpayload's strncat function
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dec1b47bd721bbee2f1982b20e374f3615519f5b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Aug 5 12:24:23 2009 +0000

    Add some more CONFIG_* prefixes that were missing.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 313973d61a930bbc9859a4d09ae3313f955572a1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Aug 5 12:16:01 2009 +0000

    Prepare for kconfig: Rename COREBOOT_V2 to CONFIG_COREBOOT_V2
    and adapt its user (x86emu) to match.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f537407e5ae1885a3f434412dd35f5f28f78343f
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Aug 5 10:48:43 2009 +0000

    Fix the generic code for copying and running coreboot_ram in case
    certain configuration options are disabled. The strings were just
    at the wrong place.
    
    Two boards fix up some variables for romstream. This isn't necessary (or
    possible) when CBFS is active, as there is no romstream. It would be
    nicer to have them depend on CONFIG_ROM_PAYLOAD, but there isn't any
    invariant that forces that to be inactive if CBFS is active, and this
    patch is supposed to be small, esp. as the stream loaders are on the way
    out.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f95edaabd3841c8e5db26d6b372611f70c7b3a6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jul 31 14:45:41 2009 +0000

    oops, these two were missed in the last cleanup.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5fe6e23c61bf1fde7a1a0568b38d32c4e625f0ef
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jul 31 11:39:55 2009 +0000

    Catch various cases in libpayload where malloc() or memalign() return NULL
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 131c0070a3b224e8ec2c817444f1ae4cf2419193
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jul 31 11:38:59 2009 +0000

    * drop duplicate prototype for lib_get_sysinfo()
    * fix delay handling in tiny curses keyboard driver
    * fix off by one error in video driver
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3f39b50cf4d6a5b7565bdb3eb173678de641b3d
Author: Ward Vandewege <ward@gnu.org>
Date:   Tue Jul 28 01:23:32 2009 +0000

    Fix erroneous comment in src/mainboard/h8dmr/Options.lb
    
    This is a trivial patch.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4551b4961abb4ef6902a4dd7212300a2547cca26
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jul 26 15:11:53 2009 +0000

    drop dead nested assignment (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc4226c5639031bd9d27b6a1026b05a1785b11fd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jul 26 15:05:40 2009 +0000

    trivial typo in a comment
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f64893a94ffb2b7d79364736fc10aebe9bd9176e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Jul 23 22:03:14 2009 +0000

    CBFS stuff:
    - update, add, and improve comments
    - whitespace here and there
    - remove unused or write-only variables
    - improve debug output
    - only build payload.{nrv2b,lzma} for non-cbfs
    - improved error checking in cbfstool
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aeb6c9870f0b1af8c0b55b2034f881da6757c4a4
Author: Luc Verhaegen <libv@skynet.be>
Date:   Thu Jul 23 16:04:58 2009 +0000

    sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
    
    Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code
    and through the general vga infrastructure i committed a month or two ago.
    Add videoram_size option for k8m890 and the Asus M2V-MX SE.
    
    Now the Asus M2V-MX SE will magically come up with a working standard VGA
    80x25 textmode.
    
    Many thanks to the people who worked hard on the Asus M2V-MX SE, and all
    of its components; this vga bringup was a breeze thanks to your hard work
    for this excellently supported board. And separate thanks to Rudolf Marek
    for spurring me on and for providing a register dump.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b2bd9963a5ceb4fc6751f2303dab5bfea43d4293
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Thu Jul 23 08:10:51 2009 +0000

    We did together some patch which makes finally a MMCONFIG workable in
    linux out of the box. There were two problems. First was that the
    mmconfig ACPI structure was empty because of cut and paste (PCI ID of
    K8M890 is different).
    
    Second problem is now nicely solvable by add_region. Linux expects that
    the mmconfig region is found as reserved memory. Otherwise it does not
    trust it.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Luc Verhaegen <libv@skynet.be>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8dee52d7a86d905b1aae4590a1f53dd4c6d2f6f4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jul 22 12:26:18 2009 +0000

    Don't put .o files in the source tree. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f5c38c0da6c678862438d16c36e792bdca17b73f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jul 22 01:42:13 2009 +0000

    Fix a redundant declaration warning (trivial)
    
    src/include/device/pci.h:75: warning: redundant redeclaration of 'pci_dev_init'
    src/include/device/pci_rom.h:39: warning: previous declaration of 'pci_dev_init' was here
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4704dc520b1d5eb8ae730b336ee5f6b7401f7dfc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jul 22 01:11:37 2009 +0000

    Fix up the tree again...
    
    * acpi_add_table requires a pointer to the RSDP, not the RSDT anymore, in order
      to properly support XSDT generation.
    * fix compilation the DSDT on gigabyte/m57sli
    * drop a remaining, forgotten HPET_NAME for "HPET"
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cdfe376c06bf95399b03196de0a436e719811eea
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 22:15:43 2009 +0000

    clean up acpi table strings, as discussed on the list
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aecf2511c67a263325c0e0cac05fc1ba20643048
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 22:01:21 2009 +0000

    Another include file slipped. This gets via/epia-m building again.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a5fdadfa18fce0dfa60f6ae45b877173d9fa312b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:58:20 2009 +0000

    Kontron updates, get board up to date with i945 and ich7 updates.
    Move interrupt routing to mainboard specific code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e1a66573b15840f2d434f0736280264a99e2250e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:57:11 2009 +0000

    this bug sneaked in during conversion
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 573f7d40be086b35b25d242818ae0e9c26d05022
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:50:34 2009 +0000

    Intel ICH7 updates
    - code restructuring (move ich7 out of i945)
    - ACPI fixes
    - major SMI handler updates
    - make sure SMBus lives where we expect it
    - try to get usb debug working
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71a3d96bc487f66c84ac869a1215b8a4a4499bf2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:44:24 2009 +0000

    * drop ich7 include
    * detect more i945 variants
    * raminit fixes
    * ACPI + PCIe updates
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4da810bd53f3e47fe0c5de64b5cec0910237a022
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:41:42 2009 +0000

    add intel speedstep support and some PM fixes.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b657a3c9b726334aac89f1af16495eab3ebefc6b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:38:33 2009 +0000

    This fixes a couple of issues with older Linux kernels (that expect an XSDT as
    		soon as there's an ACPI 2.0 or later table)
    
    * add XSDT support
    * add more table types
    
    This patch will break at least the kontron (and possibly some new boards I
    missed)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d933dd2d686879e0c27839d3f9046e348580da8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:36:41 2009 +0000

    Rewrite interrupt handling in coreboot to be more comprehensible and
    more flexible. Also some minore device allocator cleanups that sneaked
    in.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c366cd065001269afe92aa8eb8d6adf51fbd0bc7
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:31:36 2009 +0000

    Add more warnings to CFLAGS, and also add some to HOSTCFLAGS
    include ldoptions from ldscript.ld instead appending it.
    
    Not everyone was happy about the -Wmissing-prototypes in CFLAGS.
    I put it in there now anyways, so everyone can get an overview which parts of
    their code could use some cleanup. If it gets too ugly, we can still remove
    that flag again.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0001a7f1291d303b287050e440cf97be620ff5c3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:25:45 2009 +0000

    Example how simple it is to use printk instead of printk_something in
    coreboot ram stage.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 094198cf43fccdbd0da6adcda3d93b0509dd0640
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:24:22 2009 +0000

    Rewrite keyboard driver to actually wait time in ms as specified in the specs,
    rather than doing inexact and slow idle loops.
    Also improve error reporting in case of problems.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 163ff1d5ad6e16d7f02692263ab3026e43a2a46e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:22:40 2009 +0000

    - Remove superfluous / from path
    - use make -C instead of workaround
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb01f600c86ab05ee8e871a8adca2e6a78cf1894
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:20:45 2009 +0000

    Some USB debug updates, mostly comments fixing, license header updates
    and refactoring
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4fbefdd1a9c67e3ce2a215192e47278148580c2f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 21:19:06 2009 +0000

    * rework tsc based timer code to use inb instead of outb for calibration
    * Add generic Local APIC based timer code. This timer does not need expensive
      calibration and thus reduces the boot time by up to more than a second.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 925b6c0c43b92b4790533b15f78ca824f9130d8b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 21 20:27:00 2009 +0000

    * cleanup ricoh rl5c476 code:
      - drop duplicate udelay function
      - simplify code flow
      - some cosmetics on comments
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 733263c44cb363ed3ccb8333c2b07a3eed3fa8fe
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Jul 21 18:06:12 2009 +0000

    Remove a comment that no longer applies.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 28f17dbf6be3e19e84936218f1628973203f55c9
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Jul 20 19:42:15 2009 +0000

    Add legacy I/O region for vt8237r southbridge.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85a94f66b2c72a0ea4530de2b412a7cba98ad736
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Jul 20 19:34:47 2009 +0000

    Rename some preprocessor symbols. I have no idea why
    those symbols were left alone before, after this, they're
    somewhat more in line with the rest of the tree.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 951f5882e2a713db33c99f93f5730223269e8199
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jul 19 00:18:15 2009 +0000

    The file string.h is also included in romcc code, which has no malloc().
    The patch adds proper preprocessor guards and drops the malloc() prototype
    because that's in stdlib.h
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0c88655b0321da7a4ac5b1337605aaa3d7366a1e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jul 18 18:00:37 2009 +0000

    coding style fixes for powernow (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6afcea8552aecf8831b6890ad8b5e3761c10c778
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jul 18 17:58:44 2009 +0000

    drop unused variable (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f23804bda457a80f46bcdad9320230cc5154eb9c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jul 18 15:18:22 2009 +0000

    This patch fixes payloads on certain Fedora versions
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 219cece2f5a90874dc233a31bd4f53c98831fac2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jul 18 15:17:40 2009 +0000

    Fix off-by-one bug in libpayload UHCI driver
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f107538e33c880cb52ee131a527149cce9f936ee
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Jul 18 14:20:39 2009 +0000

    strdup the input of dirname, as dirname is free
    (according to the spec) to change the string in-situ,
    even if glibc doesn't do it.
    
    This avoids errors on Mac OS and Solaris.
    
    Kill nrv2b support in CBFS (we have lzma),
    slightly improve debug output in CBFS,
    properly declare all functions of CBFS in the header.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 19bc45d1e826bb60e9922eed449643f4f0d63bc9
Author: Ward Vandewege <ward@gnu.org>
Date:   Fri Jul 17 15:15:17 2009 +0000

    Bring S1g1 cpu names up to date with the official
    
      Revision Guide for AMD NPT Family 0Fh Processors
    
    Rev. 3.42 March 2009, found at
    
      http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf
    
    This patch takes its data from Table 9.
    
    Build tested.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36e8ff4c161a4d9177f6057d4299610d5d0170b0
Author: Ward Vandewege <ward@gnu.org>
Date:   Fri Jul 17 15:13:54 2009 +0000

    Bring Socket F cpu names up to date with the official
    
      Revision Guide for AMD NPT Family 0Fh Processors
    
    Rev. 3.42 March 2009, found at
    
      http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf
    
    This patch takes its data from Table 7.
    
    Build tested.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fcee8fee3fc42260ae6f4e629f3f18ab53309b0f
Author: Ward Vandewege <ward@gnu.org>
Date:   Fri Jul 17 15:12:45 2009 +0000

    Bring AM2 cpu names up to date with the official
    
      Revision Guide for AMD NPT Family 0Fh Processors
    
    Rev. 3.42 March 2009, found at
    
      http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf
    
    This patch takes its data from Table 8.
    
    Build tested, and boot tested on a AMD Athlon(tm) Dual Core Processor 5050e.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b17f9528cd1b04fe312475b3a05eae331beb9734
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Jul 17 05:41:34 2009 +0000

    This is an obvious bug which I overlooked when I worked on the AM2r2
    modules.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 782de9aa5eb33f0e5e2b57b3e2e5fa45ce7d58a4
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jul 16 15:53:11 2009 +0000

    Separate cache_as_ram_auto.c and failover.c for Tyan s2895.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e2ffb8812bd91e6f564a05b3e733a55b60a68b5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Jul 15 00:03:28 2009 +0000

    Fix VIA EPIA-M700 target enough for a first serial boot log.
    
    Add the respective Super I/O config in Config.lb (Winbond W83697HG),
    enable COM1 on the board, fix irq_table.c, as well as the PCI
    devices listed in Config.lb (based on lspci output).
    
    This has been tested by Jakob Bornecrantz <wallbraker@gmail.com>
    on hardware, i.e. there is serial output. It does not yet boot
    to a Linux console successfully, more fixing will be needed.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3839a8ebd8b4a8d249755ce9031a70913a24dbf5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jul 14 19:10:10 2009 +0000

    trivial fixes to function declarations (and build system test)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a0f01f21154b3b6065f1aa9612cd07eb0ed6ccf
Author: Luc Verhaegen <libv@skynet.be>
Date:   Sun Jul 12 14:24:06 2009 +0000

    Superiotool: Add IT8703F support.
    
    Kudos to ITE for providing the necessary information that quickly.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Tested-by: Glenn Mueller <mechwarrior5@hotmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc6de6907825336f61b93185976d52aef23d46f4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Jul 11 22:00:37 2009 +0000

    Fix MS-6178 boot by setting unused device (CIR) to 'off' (trivial).
    
    Tested on hardware, works fine.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e42e142d9fc0048574664c3c92bdc1bbca35c9be
Author: Ed Swierk <eswierk@aristanetworks.com>
Date:   Fri Jul 10 15:05:35 2009 +0000

    Apparently I'm not the only one who forgets which way the outb and
    outl arguments go.
    
    Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d4fd2c1081a7674c0631cbe96aa23ca51879586
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Jul 10 03:42:13 2009 +0000

    This seems to be a more official, common, simple way to check if the CPU is dual core or
    single core.
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9f26b8f7108f96dba4872fd344d7f102a19734d3
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Jul 10 03:10:26 2009 +0000

    msrtool: CS5536: The most important interrupt MSRs and some DIVIL MSRs.
    
    Thanks to Tom for reviewing as well!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2698fe5e1b4296c6dcf32cdd4e28f22e63fea009
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Jul 7 19:00:10 2009 +0000

    Add CONFIG_ARCH_X86=0 to sandpointx3_altimus_mpc7410.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42f75c325fec4a3ba026b3819f3aa89149aff658
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Jul 7 17:54:26 2009 +0000

    Add pci_rawops.h from the mailing list and fix the via/epia-m700 build.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bf12ddae235f66f9cff430dc997c681eaffb705a
Author: Harald Gutmann <harald.gutmann@gmx.net>
Date:   Tue Jul 7 16:15:43 2009 +0000

    ChangeLog:
    Change the parallel port from polling to interrupt-driven.
    
    This was tested by Andreas Mundt with a parallel port printer.
    
    Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
    Acked-by: Andreas B. Mundt <andi.mundt@web.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 941c1fd52a96fd3e238d1798127a137e4c4eb659
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Jul 7 15:10:13 2009 +0000

    Add initial support for a CBFS module for coreinfo.
    
    Currently it prints a list of components in CBFS and their size/type.
    There's a bunch of additional output that could be printed, but that's
    for another patch.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 280df106c0711235bfc891abfbab0020d2d0266a
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Jul 7 13:26:35 2009 +0000

    Add the IORESOURCE_BRIDGE flag to the fam10 resources for the benefit of the resource allocator.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca807f138c9dd41f8038e9b40d1c6c9c8613d94c
Author: Michael Gold <mgold@ncf.ca>
Date:   Mon Jul 6 16:05:54 2009 +0000

    Enable onboard-VGA on the Mitac 6513WU board.
    
    Signed-off-by: Michael Gold <mgold@ncf.ca>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b70a45afd0eed934c3cd6a1f2abe162061173bfd
Author: Michael Gold <mgold@ncf.ca>
Date:   Sun Jul 5 19:29:39 2009 +0000

    Add support for the Mitac 6513WU mainboard, a Compaq OEM board using the
    i810 chipset. Not all hardware has been tested, but my test PC boots Linux
    (via FILO) without any problems.
    
    Also: Add support for the SMSC LPC47U33X to the generic 'smscsuperio' driver.
    
    Signed-off-by: Michael Gold <mgold@ncf.ca>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f1458ddd42911fa63d9f55c10cd57ed3953016b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jul 5 16:23:43 2009 +0000

    Fix build for i810 boards that don't enable onboard VGA, yet.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 328bccc6103b4a61b527b8257768685973d5b333
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jul 5 16:01:57 2009 +0000

    Enable onboard VGA on the MS-6178 (i810 chipset) board (trivial).
    
    Tested on hardware with the patch from r4398 and works fine as soon
    as Linux boots (no VGA in FILO for some reason, will investigate).
    
    In order to make the 'i810.vga' VGA blob from the vendor BIOS work
    you have to make the check for PCI device ID mismatches non-fatal
    (for now) in the src/devices/pci_rom.c file like this:
    
    Index: src/devices/pci_rom.c
    ===================================================================
    --- src/devices/pci_rom.c       (Revision 4393)
    +++ src/devices/pci_rom.c       (Arbeitskopie)
    @@ -87,7 +87,7 @@
            if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
                    printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
                               rom_data->vendor, rom_data->device);
    -               return NULL;
    +               // return NULL;
            }
    
            printk_spew("PCI ROM Image,  Class Code %04x%02x, Code Type %02x\n",
    
    The reason is that the VGA blob thinks the proper VGA device ID is 0x7123
    whereas it really is 0x7121 on hardware. There are multiple ways to work
    around this (there have been many discussions in the past), we'll see which
    method will be used in future...
    
    Note: This has been tested against r4393 only for now to make sure there
    are no problems because of the recent resource allocator changes, see
    http://www.coreboot.org/pipermail/coreboot/2009-July/050486.html.
    Tests with trunk will follow.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 76a88d0805a42f3759f1444ab62760f5160fc999
Author: Elia Yehuda <z4ziggy@gmail.com>
Date:   Sun Jul 5 15:50:30 2009 +0000

    Various Intel 82810/82810E changes which allow onboard VGA to work.
    At the same time also make the 82810 code handle 82810E.
    
     - Set SMRAM register according to CONFIG_VIDEO_MB value:
        - 512 means 512 KB
        - 1 means 1 MB
        - Every other value for CONFIG_VIDEO_MB (e.g. 0) disables VGA.
       This is not very clean, changing CONFIG_VIDEO_MB to CONFIG_VIDEO_KB
       in a future patch may be nicer.
    
     - Set MISSC2 register bits as required per datasheet to make VGA work.
       The code handles both 82810 and 82810E.
    
     - northbridge.c: Add __pci_driver entry for the Intel 82810E.
    
    Also:
    
     - Rename PAM register #define to PAMR as per datasheet.
    
     - Drop unused/commented code for now.
    
     - Don't explicitly set GMCHCFG for now, the default works ok. We'll
       have to figure out the proper/ideal settings later.
    
    The code is based on a patch from Elia Yehuda <z4ziggy@gmail.com> but
    has been modified quite a bit for correctness and minimalism.
    
    Tested on hardware with a slightly modified MS-6178 target,
    patches to enable onboard-VGA for MS-6178 will follow.
    
    Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd4f2f808c258bc58814f3a230d0788a0b0fbd26
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jul 2 21:19:33 2009 +0000

    Fix many things for via/epia-m700 to build.
    
    Unfortunately it still doesn't.  I think it's close, though.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29be535a40514d7327f560d5c6f19acf5d688d0e
Author: Harald Gutmann <harald.gutmann@gmx.net>
Date:   Thu Jul 2 19:06:01 2009 +0000

    ChangeLog:
    
    Turn on Parallel Port and Floppy in Config.lb
    
    Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
    Acked-by: Andreas B. Mundt <andi.mundt@web.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7233e089923870cb4dc483034f7e9c9334c9128
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jul 2 19:02:33 2009 +0000

    Update the k8 code for the v3 resource allocator.
    The major change is that the K8 registers don't get touched until the end of
    resource allocation.
    
    Fam10 code could be updated the same way.
    
    Move VGA code before resource allocation but after device enumeration.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29cc9eda2021a87396ef31a6fc81daff6fd1be7a
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jul 2 18:56:24 2009 +0000

    Move the v3 resource allocator to v2.
    
    Major changes:
    1. Separate resource allocation into:
    	A. Read Resources
    	B. Avoid fixed resources (constrain limits)
    	C. Allocate resources
    	D. Set resources
    
    Usage notes:
    Resources which have IORESOURCE_FIXED set in the flags constrain the placement
    of other resources.  All fixed resources will end up outside (above or below)
    the allocated resources.
    
    Domains usually start with base = 0 and limit = 2^address_bits - 1.
    
    I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
    still there for resources.  Some platforms may want to change that, but I didn't
    want to break anyone's board.
    
    Resources are allocated in a single block for memory and another for I/O.
    Currently the resource allocator doesn't support holes.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2468331952bae0abdc4d76dbe6cf26f05b7825e5
Author: Ward Vandewege <ward@gnu.org>
Date:   Thu Jul 2 18:27:02 2009 +0000

    Convert Supermicro H8DMR to CBFS. Also clean up some whitespace in
    targets/supermicro/h8dmr/Config.lb and Config-abuild.lb.
    
    Importantly, this also sets
    
      default CONFIG_AP_CODE_IN_CAR=0
    
    in
    
      src/mainboard/supermicro/h8dmr/Options.lb
    
    which is required to make this box boot since the changes that went in in
    r4315.
    
    At Myles' suggestion, this patch also sets
    
      default CONFIG_USE_FAILOVER_IMAGE=0
      default CONFIG_USE_FALLBACK_IMAGE=0
      default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
    
    in src/mainboard/supermicro/h8dmr/Options.lb to simplify
    targets/supermicro/h8dmr/Config.lb a bit further.
    
    Build tested with abuild, boot tested on physical hardware.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a692d817650068e2125036d25bbaf2f3e9ec876
Author: Thomas Jourdan <thomas.jourdan@gmail.com>
Date:   Wed Jul 1 17:01:17 2009 +0000

    Add support for the Intel Eagle Heights development board.
    
    Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c96517a132ce26f906c8e38e19ebaab8b736e9a
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Jul 1 16:34:03 2009 +0000

    Fix typo and only output post code if the work was done.
    
    Thanks to Thomas Jourdan <thomas.jourdan@gmail.com> for reporting it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 08405e74119bde819bb892b55e14e407d7ad5617
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Jul 1 15:08:19 2009 +0000

    Fix abuild for via/epia-n.  Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a7368d4b73b4803f2b152efa08ce97234e72371
Author: Jon Harrison <bothlyn@blueyonder.co.uk>
Date:   Wed Jul 1 13:19:25 2009 +0000

    I missed three files.
    Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d4a08e7da73c1a24a7bb092ba6ef2c09af37239
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jul 1 12:26:11 2009 +0000

    let abuild autodetect the coreboot path a bit better. So in the top level of
    coreboot you can now do:
      $ util/abuild/abuild -t foo/bar
    instead of
      $ util/abuild/abuild -t foo/bar $PWD
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c6bd6c7736d00cdd45aca84ccac01c7e8278f42
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jul 1 12:22:26 2009 +0000

    the file was not really different, so use the default file (trivial, since it
    didn't build before, and it still doesn't)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cfb9cd2f8ab545296f94cbc0580d0a9ae73efc06
Author: Jon Harrison <bothlyn@blueyonder.co.uk>
Date:   Wed Jul 1 10:57:25 2009 +0000

    Ron,
    
    Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2.
    
    Patch should work against r4381 (or later ?)
    
    This version now boots all of the way through to attempting to launch a
    payload (I'm trying FILO right now), where it falls over with exception
    6 (invalid opcode)
    
    The coreboot_table issue seems to have been automagically resolved by
    the latest core files.
    
    It may still be that the reason for the payload not starting is down to
    some issue with the tables initialising, I'll look closer at that.
    
    Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
    
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit db8b4114ff73cc002bb4e15fd9e8f2fc012cf39e
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Wed Jul 1 07:01:32 2009 +0000

    Add AMD family 10 AM2r2 support.
    
    Coreboot used to take SYSTEM_TYPE as a lable to tell what the socket is.
    
    This patch replaces (some of, not all) CONFIG_SYSTEM_TYPE with CONFIG_SOCKET_TYPE.
    It also fix some compiling error in src/northbridge/amd/amdmct/mct/mctardk4.c
    
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9dd27bc03a53f69b55c1c9718a5e44365019c082
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jun 30 17:13:58 2009 +0000

    the tool chain settings should not be in renamed (as they will never live in
    Kconfig)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36f230eefb5a072240447fdbe1aa81ad1bb80072
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jun 30 15:54:53 2009 +0000

    whoops. missed those two..
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 775c04e53743150dbd47ef85986b681ab5522618
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jun 30 15:23:20 2009 +0000

    commit svn:externals for last commit (what a pain) (1/2)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0867062412dd4bfe5a556e5f3fd85ba5b682d79b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jun 30 15:17:49 2009 +0000

    This patch unifies the use of config options in v2 to all start with CONFIG_
    
    It's basically done with the following script and some manual fixup:
    
    VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
    for VAR in $VARS; do
    	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
    done
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9702b6bf7ec5a4fb16934f1cf2724480e2460c89
Author: Warren Turkal <wt@penguintechs.org>
Date:   Tue Jun 30 14:11:42 2009 +0000

    add new supported chipset
    Add identification for X58 and ICH10R.
    
    Signed-off-by: Warren Turkal <wt@penguintechs.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b1ff95c14d62ffad2bb417aa3372fe767342de7f
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Jun 28 22:47:06 2009 +0000

    This copy of flashrom is old and unmaintained. Delete it to avoid
    confusion, after we had a grace period to get people to move over to the
    new repository.
    
    History stays available for the archaeologists and for ancient
    checkouts (potentially with local changes). Use "svn diff" to get local
    changes, and apply it to a newer tree (if you manage to apply it, that
    is).
    
    The new repository is available at:
    svn://coreboot.org/flashrom/trunk
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1220c50919757a0a9b0ba31eba348b9e80dd7e2d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jun 28 22:40:48 2009 +0000

    flashrom is a separate project now. Thus we don't enforce it on our users.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f575486255d99cbbc85d4a68402f030485a5e20
Author: Yinghai Lu <yinghai@kernel.org>
Date:   Sun Jun 28 15:04:06 2009 +0000

    Impact: fix vmlinux from 2.6.30
    
    from 2.6.30 (?)
    the new vmlinux with per_cpu and brk support will have more sections.
    
    Elf file type is EXEC (Executable file)
    Entry point 0x200000
    There are 7 program headers, starting at offset 64
    
    Program Headers:
      Type           Offset             VirtAddr           PhysAddr
                     FileSiz            MemSiz              Flags  Align
      LOAD           0x0000000000200000 0xffffffff80200000 0x0000000000200000
                     0x0000000000e46000 0x0000000000e46000  R E    200000
      LOAD           0x0000000001046000 0xffffffff81046000 0x0000000001046000
                     0x00000000001406e0 0x00000000001406e0  RWE    200000
      LOAD           0x0000000001200000 0xffffffffff600000 0x0000000001187000
                     0x0000000000000888 0x0000000000000888  RWE    200000
      LOAD           0x0000000001388000 0xffffffff81188000 0x0000000001188000
                     0x000000000008a086 0x000000000008a086  RWE    200000
      LOAD           0x0000000001600000 0x0000000000000000 0x0000000001213000
                     0x0000000000015e20 0x0000000000015e20  RWE    200000
      LOAD           0x0000000001629000 0xffffffff81229000 0x0000000001229000
                     0x0000000000000000 0x0000000000208000  RWE    200000
      NOTE           0x0000000000b3c7e8 0xffffffff80b3c7e8 0x0000000000b3c7e8
                     0x0000000000000024 0x0000000000000024         4
    
     Section to Segment mapping:
      Segment Sections...
       00     .text .notes __ex_table .rodata __bug_table .pci_fixup .builtin_fw __ksymtab __ksymtab_gpl __ksymtab_strings __init_rodata __param
       01     .data .init.rodata .data.cacheline_aligned .data.read_mostly
       02     .vsyscall_0 .vsyscall_fn .vsyscall_gtod_data .vsyscall_1 .vsyscall_2 .vgetcpu_mode .jiffies
       03     .data.init_task .smp_locks .init.text .init.data .init.setup .initcall.init .con_initcall.init .x86_cpu_dev.init .altinstructions .altinstr_replacement .exit.text .init.ramfs
       04     .data.percpu
       05     .bss .brk
       06     .notes
    
    So need to increase NR_SECTIONS.
    
    also fix one typo about phys address mask.
    
    Peter says: A similar fix was also implemented by Maciej Pijanka, so let's
    commit this now, eh.
    
    Signed-off-by: Yinghai Lu <yinghai@kernel.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3ddbfb8901a25243a57950a3a37860225b8662b0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Jun 27 16:06:51 2009 +0000

    Add a target/ directory for the VIA EPIA-M700 board, so we can build it.
    
    Note that this board is nowhere near usable, further patches will follow
    and hopefully get this into buildable and usable shape.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 22b44ba9c3672115bfe90ff9b218553959743b6e
Author: François-Regis Vuillemin <coreboot@miradou.com>
Date:   Sat Jun 27 02:23:26 2009 +0000

    Add dump support for SMSC LPC47N252.
    
    Signed-off-by: François-Regis Vuillemin <coreboot@miradou.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4375 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit db52fb802471e5bde26a338ec1afbf8164da87f9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Jun 26 15:53:07 2009 +0000

    Don't dump 0x07 registers, they're useless as they change every time
    some software wants to do an LDN access (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 556e6fb2e34ac1e6757d0bf0a7ccf7401686ec37
Author: Michael Gold <mgold@ncf.ca>
Date:   Fri Jun 26 15:25:04 2009 +0000

    This adds register definitions for all logical devices on the SMSC
    LPC47U33x, allowing 'superiotool -d' to work.
    
    Also, some consistency string fixes.
    
    Signed-off-by: Michael Gold <mgold@ncf.ca>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 78fdd6046e6bcbab02a273b6a07235f242d5e7d1
Author: Arjan Koers <0h3q2rmn2bdb@list.nospam.xutrox.com>
Date:   Fri Jun 26 15:16:21 2009 +0000

    Add dump information for F71862FG and F71863FG.
    
    Signed-off-by: Arjan Koers <0h3q2rmn2bdb@list.nospam.xutrox.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb21b2e45bf82aa55d03b904df5f67509317f094
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jun 25 21:44:38 2009 +0000

    Remove the object files for cbfs from target directories and add a
    cbfstool-clean target to the Makefile.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 455e22336550365a19f331036e8e45281008b534
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jun 25 15:54:57 2009 +0000

    The problem is that the check to see if we're at the end is never reached.  I
    didn't look into it enough to know why fssize is 32 bytes larger than the
    offset.  There may be another bug here.  Maybe something with the CBFS header
    not being included or excluded from the calculation?
    
    Anyway, this patch fixes it for all cases size > 32.
    
    I also changed the error message so that it doesn't look like the ROM is full
    just because it can't find room for a file.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c19f949fedeb607996a6c02eb8400b594676cbc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Jun 24 00:35:07 2009 +0000

    Add support for the Soyo SY-6BA+ III board.
    
    Tested on hardware by Andrew Morgan <ziltro@ziltro.com>, boots
    Linux fine. Detailed status at:
    
      http://www.coreboot.org/Soyo_SY-6BA_Plus_III
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Andrew Morgan <ziltro@ziltro.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3310d75e6cddf3832d514b2ec26aa81ea8cfa0c6
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Jun 21 20:26:13 2009 +0000

    This patch adds a proper namestring generation to our ACPIgen generator.
    Its used for Name and Scope and Processor now. As bonus, it allows to
    create a multi name paths too. Like Scope(\ALL.YOUR.BASE).
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f17f647a62427e7241c6cbee0a81be5a46072cd9
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Jun 19 21:18:14 2009 +0000

    Undo my ugly commit that added uses clauses in lots of places instead of one.
    Fix configuration of all boards. (Abuild tested)
    Hopefully fix compilation of PPC boards (they've never compiled for me.)
    
    Apologize profusely.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24fbb7d66f6938b942e4481d2821023fbb7cd467
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jun 19 19:50:58 2009 +0000

    work around initobject breakage in pc80/Config.lb
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6114311c8eaabd14f524e2884316249de9d9578b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Jun 19 15:41:49 2009 +0000

    Convert the MSI MS-6178 board to CBFS.
    Also, enable HIGH_TABLES support for this board.
    
    The HIGH_TABLES failed with:
    
      No matching ram area found for range:
        [0x00000000000f0000, 0x0000000000100000)
      Ram areas
        [0x0000000000000000, 0x0000000000001000) Reserved
        [0x0000000000001000, 0x00000000000a0000) RAM
        [0x0000000000100000, 0x000000000fff0000) RAM
        [0x000000000fff0000, 0x0000000010000000) Reserved
      SELFBOOT RETURNED!
      Boot failed.
    
    The fix was to change northbridge.c as follows:
    
      - ram_resource(dev, idx++, 1024, tolmk - 1024);
      + ram_resource(dev, idx++, 768, tolmk - 768);
    
    This is build-tested and tested on hardware by me. It boots fine,
    for instace with SeaBIOS and the standard GRUB1 from my disk.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 62cfe169fafa5bd6a37a71cde221fc09e0b47f0e
Author: Harald Gutmann <harald.gutmann@gmx.net>
Date:   Fri Jun 19 12:03:40 2009 +0000

    ChangeLog:
    Add initial ACPI support for M57SLI.
    	Activates/Enables:
    		* native Coreboot ACPI for M57SLI
    		* Soft-Power-Off
    		* PowerNow!
    		* High Precision Event Timer
    		* Windows booting with ACPI support
    
    Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ecf4ef0b26c6bd07380c322d449aacc55f0acbb3
Author: Ward Vandewege <ward@gnu.org>
Date:   Thu Jun 18 16:38:35 2009 +0000

    Make sure the address variable is initialized to zero - it is only set when a
    [base address] parameter is supplied on the command line... This patch fixes
    random segfaults when using 'cbfstool add'.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da8336176e1b7bfa7c944533136a3a78a3907a7b
Author: Harald Gutmann <harald.gutmann@gmx.net>
Date:   Thu Jun 18 10:05:41 2009 +0000

    Change Log:
    Fix interrupt handling in mptable.c on M57SLI.
    
    Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
    Acked-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b735f85379c14b74b0eea8d57bcb19ebe133d67a
Author: Harald Gutmann <harald.gutmann@gmx.net>
Date:   Thu Jun 18 09:46:11 2009 +0000

    Change Log:
    Activate HIGH_TABES on M57SLI
    
    Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 82bc9bc31ec593c7e49c781a2d3daebf46158acd
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Jun 17 16:38:43 2009 +0000

    Fix configuration of boards that didn't have uses CONFIG_USE_INIT. Trivial.
    
    Abuild tested with -C.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aac8dc81c5ffc639a0222041b7786da0def708f7
Author: Marc Jones <marcj303@gmail.com>
Date:   Wed Jun 17 15:33:57 2009 +0000

    Patch AMD Fam10 C2 for errata 327, 344, 346, 354, 351.
    Removed c2 HT Phy 520a/530a reserved bit.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cbefc238c53ad5fbfa03b734e9dcd3dd50c00f40
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Jun 16 23:02:39 2009 +0000

    Maximilian Thuermer found a bug where the HT link capability code was always
    updating the passed value to the next link offset even when it was on the
    requested link (cap_count).
    
    Maximilian also found a bug where the linktype was still getting attributes
    even when it wasn't initialized.
    
    This should fix the HT problems for Fam10 C2. There are still issues with the
    microcode which need to be resolved.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d41de2ea7a65242f5c95e578d99cf46cd23920dd
Author: Ronald G. minnich <rminnich@gmail.com>
Date:   Tue Jun 16 15:02:52 2009 +0000

    These changes implement car in qemu.  The implementation is in several
    ways superior to v3, while lacking its completeness. But, one nice
    thing: no more included .S or .c files. It's all separate compilation.
    That should allow our Makefiles to work much better.
    
    Note that the current non-CAR implementation is the default and
    continues to work (tested FILO boot to Linux on both CAR and non-CAR).
    
    Index: src/mainboard/emulation/qemu-x86/Config.lb
    Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that
    depend on this variable are grouped in one if, and the other parts
    (romcc etc.) are in the else. This change is a model of how we should be
    able to do other motherboards.
    
    Index: src/mainboard/emulation/qemu-x86/Options.lb
    add needed options.
    
    Index: src/mainboard/emulation/qemu-x86/failover.c
    remove code inclusion from this not-yet-used file.
    
    Index: src/mainboard/emulation/qemu-x86/rom.c
    This is the entry point for the rom-based code. Called stage1.c in v3.
    
    Index: src/lib/Config.lb
    change initobject to a .o from a .c; this fixed a build problem.
    
    Index: src/pc80/serial.c
    make uart_init non-static.
    
    Index: src/pc80/Config.lb
    add initobject
    
    Index: src/arch/i386/init/entry.S
    Entry point. Unify a bunch of files that were fiddly lttle includes. From v3.
    
    Index: src/arch/i386/init/ldscript.ld
    new file. The goal is to hang all init changes for CAR here, to minimize other changes to any
    other ldscript. Besides, putting this in init makes sense; entry and car are manage init.
    
    Index: src/arch/i386/init/car.S
    generic i386 car code from v3.
    
    Index: src/arch/i386/init/ldscript_fallback_cbfs.lb
    Fix what looks like a bug: this was not including the init.text section.
    
    Index: targets/emulation/qemu-x86/Config.lb
    push up the console loglevel. qemu is for debugging so we might as well
    get all the debugging we can.
    
    Index: targets/emulation/qemu-x86/Config-car.lb
    For CAR bullds.
    
    Signed-off-by: Ronald G. minnich <rminnich@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3ba18a67eb4e4bea8801633517ee2b56e471c648
Author: Ioannis Barkas <tripl3fault@yahoo.com>
Date:   Fri Jun 12 14:20:27 2009 +0000

    Fix typo in Winbond W83977TF register listing.
    
    Signed-off-by: Ioannis Barkas <tripl3fault@yahoo.com>
    Signed-off-by: Nikos Barkas <levelwol@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 124d8767dac8827be3104db1e1d710c32813d8d3
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jun 11 18:27:41 2009 +0000

    Fix s2895 failover booting.
    
    Abuild tested and boot tested on s2895 and serengeti_cheetah.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ca6ed548ed52c4ae2e3c8f1e360e5e569bc1739
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jun 9 15:22:47 2009 +0000

    this port is horribly broken and should not have been checked in. This patch
    gets us through config, but it fails during build because the original patch
    duplicated some files for VIA systems.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a88db7bb870c8a6884da30e827e886cd26355e96
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 9 14:44:37 2009 +0000

    Fix a little white space issue. Also, don't copy the rom image
     if it is already in its correct location.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e8c6f86b80efbb90a7f708aded55f5a6032df8a5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Jun 8 13:05:47 2009 +0000

    Add (commented) line for VGA blob adding (CBFS version) to simplify things for users a bit.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ce41c06ccdf1c80600ef4cf8e140f928b09d754
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jun 8 03:33:57 2009 +0000

    This is transition code for cbfs to implement
    cbfs files at fixed addresses.
    
    I call this transitional as the approach I am taking is to add
    capability to cbfstool but not change code in a way that will break
    existing usages. Later, once we're sure nothing has broken, we can start to
    smooth the edges.
    
    Right now, fixed address file are only supported via the add command.
    
    There is one additional command syntax, so, example:
    cbfstool add rom romstrap optionrom 0xffffd000
    
    Will add the file to that fix location for a romstrap.
    
    The assumption is that the ROM is based at the end of a 32-bit address
    space. As you can see from the code, that assumption can easily be
    over-ridden, if we ever need to, with a command option.
    
    Here is one example output result.
    
    rminnich@xcpu2:~/src/bios/coreboot-v2/util/cbfstool$ ./cbfstool x.cbf print
    x.cbf: 1024 kB, bootblocksize 32768, romsize 1048576, offset 0x0
    Alignment: 16 bytes
    
    Name                           Offset     Type         Size
    h                              0x0        optionrom   251
                                 0x130      free         917120
    h3                             0xdffe0    optionrom    251
                                 0xe0110    free         97960
    
    The way this is implemented is pretty simple. I introduce a new
    operator, split, that splits an unallocated area into two unallocated
    areas. Then, allocation merely becomes a matter of 0, 1, or 2 splits:
    0 split -- the free area is the exact fit
    1 splits -- need to split some off the front or back
    2 splits -- need to split off BOTH the front and back
    
    I think you'll be able to see what I've done. I call this transitional
    because, in the end state, we only need one allocate function; for now
    I've left two in, to make sure I don't break compatibilty.
    
    Why I like this better than ldscript approach: I like having the
    ROMSTRAP located by cbfs, not linker scripts. For one thing, it makes
    romstrap visible as a first class object. I think I would have latched
    onto a problem I was having much more quickly had I remembered the
    ROMSTRAP. It gets lost in the linker scripts.
    
    At this point, we should be able to start removing special ROMSTRAP location
    code from linker scripts.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d64f403f8eeb2da55472d9f6f65b657c063414ed
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jun 7 14:38:32 2009 +0000

    A bunch of additional EPIA-M700 cleanups and also some non-cosmetic changes:
    
     - Make get_dsdt script executable.
    
     - Rename DrivingClkPhaseData.c to driving_clk_phase_data.c.
    
     - Set proper IRQ_SLOT_COUNT value in the hope that the '14' from irq_table.c
       is correct.
    
     - Fix broken or incorrect #include names to increase likelyhood of a
       successful compile.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ffff3434e610cf38c8eb06a3f1b1dece92652fa
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jun 7 13:46:50 2009 +0000

    First bunch of coding style and consistency cleanups for the
    EPIA-M700 target.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cff071ab0ed60c887ceeaafa2e722b07691fff10
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sat Jun 6 16:50:38 2009 +0000

    When I started refactoring mainboard Config.lb, I added two different
    files for targets without failover:
    src/config/nofailovercalculation.lb (64 kB XIP)
    src/config/nofailovercalculation128.lb (128 kB XIP)
    Targets with other XIP sizes were ignored.
    
    This patch moves XIP size back into mainboard code.
    
    Benefits from this patch:
    - src/config/nofailovercalculation128.lb is no longer needed
    - Targets with XIP sizes besides 64k and 128k benefit from refactoring
    - Conceptually, this makes the include files pure calculation files
    without settings.
    
    Abuild tested.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7d8ae3b1d91f3f77496b065a7d5158893c4dd28
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Jun 6 12:19:59 2009 +0000

    Make failover larger and decrease fallback's size so the total stays the
    same. The errata need some extra room in failover.
    
    Trivial and abuild tested
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a774192e22433938d527764531d81a37f985a8f2
Author: Marco Schmidt <mashpb@gmail.com>
Date:   Sat Jun 6 11:33:58 2009 +0000

    Fix for Erratum 350 for AMD Fam10h CPUs.
    
    Compared to posted patch, there are whitespace fixes
    (request by Uwe), and a guard to run the erratum only
    on AMD_RB_C2 (request by Marc).
    
    Signed-off-by: Marco Schmidt <mashpb@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c263b4471dd42895b409652b3f3567fcb5cdaae1
Author: Marco Schmidt <mashpb@gmail.com>
Date:   Sat Jun 6 11:21:52 2009 +0000

    Fix for Erratum 343 for AMD Fam10h CPUs.
    
    Signed-off-by: Marco Schmidt <mashpb@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 240ef7c7691a29e96f7710b2f6d6d95b5bb53d13
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Jun 6 07:19:53 2009 +0000

    Change the CBFS build process to use coreboot.rom
    instead of coreboot.strip. That fixes the normal
    image because the calculations for its offset in
    the ROM match reality again.
    
    This requires changes in CBFS configurations to
    minimize the bootblock size. These are also done
    for CBFS boards.
    
    Other than this a couple of minor fixes are in this
    patch:
    - make asus/m2v-mx_se build with abuild with a
      crosscompiler
    - move CONFIG_CBFS for hp/dl145_g3 to Options.lb
      as it's done everywhere else
    - change the default config of abuild to not
      provide ROM_IMAGE_SIZE values for the images
      in a CBFS configuration
    - change abuild's crosscompile autodetection to
      not try to use "i386-elf-i386-elf-gcc" (which
      is bogus)
    
    Except for the latter two abuild changes (both
    in util/abuild/abuild), they're available as
    patch set on the mailing list in a mail from
    2009-06-05 titled
    [PATCH]es to get normal image to work again with CBFS
    
    The changes in util/abuild/abuild are trivial and
    abuild tested.
    
    As discussed on the list,
    targets/hp/dl145_g3/Config-abuild.lb is
    deleted, now that Config.lb works again.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa58f5427ff5188bc867b1016ca2a41e0a516519
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Jun 5 23:43:11 2009 +0000

    Fix non-revF K8 ram init compilation which was broken in r4341.
    Change all printk_raminit to printk_spew.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20a98c9201a0a3699e64c2c2dc4c6259ae948ade
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Jun 5 23:02:43 2009 +0000

    Initial untested board code for the VIA EPIA-M700 Mini-ITX board.
    
    The patch has been submitted by bari <bari@onelabs.com> and written
    by OLPC.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c45a96138974ffd7bf5a8f54baec8a22def11de
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Jun 5 20:37:35 2009 +0000

    K8 RAM init debug messages are pretty short and sometimes cryptic. Make
    them a bit more verbose and hopefully more understandable.
    
    Old messages for my machine with 5 GB:
    RAM: 0x00400000 kB
    Ram3
    [...]
    Initializing memory:  done
    RAM: 0x00500000 kB
    
    New messages:
    RAM end at 0x00400000 kB
    Adjusting lower RAM end
    Lower RAM end at 0x003f0000 kB
    Ram3
    [...]
    Initializing memory:  done
    Handling memory hole at 0x00300000 (default)
    RAM end at 0x00500000 kB
    Handling memory mapped above 4 GB
    Upper RAM end at 0x00500000 kB
    Correcting memory amount mapped below 4 GB
    Adjusting lower RAM end
    Lower RAM end at 0x00300000 kB
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87e7050bff564820e3337c0653211a8180ef1fc0
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Jun 5 11:41:51 2009 +0000

    die() does never return. Annotate it as such.
    Any endless loop after die() can be eliminated.
    Dereferencing a NULL pointer is bad. die() instead.
    Replace endless loops with die().
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 28d71b9445ef2774baa5e1f5ad17160d90b0e8bb
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Fri Jun 5 10:00:07 2009 +0000

    After I modify the pci_ext_read_config32 and pci_ext_read_config32, the step 6a
    starts to play its role. Then the system hangs at HDA init. I dont know what the
    VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)"
    in 5.10.2. Before I know what it is, I think it is better to skip it.
    
    Tested on dbm690t.
    
    Add comment from Rudolf,
    "
    VC is virtual channel. Its used for isochronous transfer of data to sound card.
    The virtual channel guarantee "on time" delivery. In other words it sets up a
    channel for data to sound card, which means that that arrivs in time and there will
    be no interuptions in audio stream.
    
    http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx
    "
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a24e1dd6dacc4036466f5fc8acd5a1c4306790d2
Author: Elia Yehuda <z4ziggy@gmail.com>
Date:   Fri Jun 5 00:22:25 2009 +0000

    Add a hopefully more correct and flexible set_dram_buffer_strength()
    function based on test results with many different DIMMs.
    
    Tested by Uwe Hermann <uwe@hermann-uwe.de> on hardware.
    
    Might need a small increase of ROM_IMAGE_SIZE for some boards, we'll see.
    
    Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1725703a1d37e44464bd988da0bca060afa82207
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Jun 4 20:18:42 2009 +0000

    The point of the patch is to make it easier to understand the raminit
    code, specifically the difference between pre_f and f code.
    
    The only functional changes are in printk statements.  The rest is white space.
    
    1. Remove some #if 0 and #if 1 blocks
    2. Remove #if USE_DCACHE_RAM blocks.  All K8 boards use CAR.
    2. Correct typos (canidate -> candidate)
    3. Try to minimize the differences between amdk8_f.h and amdk8_pre_f.h
    4. Try to minimize the differences between raminit.c and raminit_f.c
    5. Make boards that have rev_f processors include the correct raminit code
    
    There is much more that could be done, but it's a start.
    
    Abuild tested and boot tested on s2892 and serengeti_cheetah.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d11bd003c6aa075fb1a9874a4eb23902edd96f06
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Thu Jun 4 01:57:03 2009 +0000

    This patch is about some noticable bugs which was made by no reason.
    1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right?
    2. In rs690_pcie.c,
      (1) Obviously, the mask should be 0xF, and bit 19 should be set to 1 (in comment).
          In rpr 5.10.2, step 2, step 2.1 & step 2.6
      (2) The dynamic buffer allocation is enabled by setting bit 11 of PCIEIND: 0x20,
          instead of PCIEIND_P: 0x20.
          In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a9c5ea08d07d343d32d4c083a232107bd84d8064
Author: Luc Verhaegen <libv@skynet.be>
Date:   Wed Jun 3 14:19:33 2009 +0000

    Revert "CMOS: Add set_option and rework get_option."
    
    This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.
    
    Stepan pointed out that "s" means string, which makes the following statement
    in this commit message invalid: "Since we either have reserved space (which
    we shouldn't do anything with in these two functions), an enum or a
    hexadecimal value, unsigned int seemed like the way to go."
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Luc Verhaegen <libv@skynet.be>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9efecc5408cb72d5e547736cba90c1814539a10c
Author: Luc Verhaegen <libv@skynet.be>
Date:   Wed Jun 3 14:19:20 2009 +0000

    Revert "kontron 986lcd_m: cmos.layout: mark boot_devices as reserved."
    
    This reverts commit c03527377db5951f0d3228e2a93b4c57dd81b8ec.
    
    Stepan pointed out that 's' means string, and that therefor strings do exist.
    Marking this as reserved breaks some payloads.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Luc Verhaegen <libv@skynet.be>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b005f0e2e0963c8073bf559160f1a5fbea19bb27
Author: Luc Verhaegen <libv@skynet.be>
Date:   Wed Jun 3 11:53:54 2009 +0000

    kontron 986lcd_m: cmos.layout: mark boot_devices as reserved.
    
    The kontron 986lcd_m cmos.layout had a 512bit area claimed for "boot_devices".
    The changes to the cmos code no longer allow usage of values larger than
    32bits. Since this option was completely unused, mark it as reserved.
    
    Fixes build after the get_option change (r4332)..
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Luc Verhaegen <libv@skynet.be>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ceae905f10a555835db0af072c3adfff98b3a7b
Author: Luc Verhaegen <libv@skynet.be>
Date:   Wed Jun 3 10:47:19 2009 +0000

    CMOS: Add set_option and rework get_option.
    
    To ease some of my debugging pain on the unichrome, i decided i needed to
    move FB size selection into cmos, so i could test a size and then reset it
    to the default after loading this value so that the next reboot uses the
    (working) default again. This meant implementing set_option in parallel to
    get_option.
    
    get_option was then found to have inversed argument ordering (like outb) and
    passing char * and then depending on the cmos layout length, which made me
    feel quite uncomfortable. Since we either have reserved space (which we
    shouldn't do anything with in these two functions), an enum or a
    hexadecimal value, unsigned int seemed like the way to go. So all users of
    get_option now have their arguments inversed and switched from using ints
    to unsigned ints now.
    
    The way get_cmos_value was implemented forced us to not overlap byte and to
    have multibyte values be byte aligned. This logic is now adapted to do a
    full uint32_t read (when needed) at any offset and any length up to 32, and
    the shifting all happens inside an uint32_t as well. set_cmos_value was
    implemented similarly. Both routines have been extensively tested in a
    quick separate little program as it is not easy to get this stuff right.
    
    build_opt_tbl.c was altered to function correctly within these new
    parameters. The enum value retrieval has been changed strol(..., NULL, 10)
    to stroul(..., NULL, 0), so that we not only are able to use unsigned ints
    now but so that we also interprete hex values correctly. The 32bit limit
    gets imposed on all entries not marked reserved, an unused "user_data" field
    that appeared in a lot of cmos.layouts has been changed to reserved as well.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a922b3195b77a3cc82bafad20dd3dfcfd2a61bc0
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Wed Jun 3 03:15:05 2009 +0000

    Modify it based on the RPR 5.7.7. Switching GGSP Configuration By Register Programming.
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8318fe8f9af3d92eaf24aea3457a011e5fde134
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Jun 2 23:49:00 2009 +0000

    More compact format for wiki output at
    http://www.coreboot.org/Coreboot_Options (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7a6447c8fc38f33b6f109081662199c9ce6c935
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Jun 1 20:02:21 2009 +0000

    cbfstool reacts to a too large bootblock file by stopping
    with an error code now.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fff87d31ca480a99f262bedab349f93f0b11d3a1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Jun 1 01:38:29 2009 +0000

    Cosmetics and consistency fixes in src/superio/serverengines/pilot/ (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a519fe77b60123f1fba46f1f93580d5628a88555
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun May 31 17:00:25 2009 +0000

    Following patch moves all vt8237 fadt.c from mainboard/* file to chipset
    directory just with one common file.
    
    Changes to FADT: move to rev4, fix the generic register descriptors, detect additional VT8237S features.
    Change the compiler to CORE , its revision to 42.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 608762793a4e6f1a4152858dfeb372dc4c3f10a0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat May 30 15:12:33 2009 +0000

    Many Kudos go to Segher Boessenkool and Patrick Georgi for figuring this one
    out. Fix the libgcc dependency on abort() due to nested functions.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 41216225a1b19e91af3e205666a61117d9496de3
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri May 29 18:41:09 2009 +0000

    rename the option CONFIG_PCI_OPTION_ROM_RUN_VM86 to CONFIG_PCI_OPTION_ROM_RUN_REALMODE.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 60f0f1b18f87332a569ced6c8744a1572517ba39
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri May 29 13:45:22 2009 +0000

    enable/disable IDE 0/1 (Primary/Secondary) interfaces on the i82801xx southbridge.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8a5c6ec02f1e21d62756bda07f755b3a2f4865f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri May 29 13:08:27 2009 +0000

    drop most of the crappy vm86 code and replace it with a rewritten
    version that has all assembler in a .S file and all C code in a .c
    file. Also, remove requirement to move around between GDTs.
    
    This version includes the suggestions from Peter to clean up CR0 manipulation
    and to guard critical code paths by cli/sti. Tested and working on my hardware.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43bc5a9c74c701b2a13dbe603c6983a13db622da
Author: Luc Verhaegen <libv@skynet.be>
Date:   Fri May 29 03:44:47 2009 +0000

    Fix build with CONFIG_*_ROM_RUN.
    
    Last commit broke it due to leftover "void" from prototype.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Luc Verhaegen <libv@skynet.be>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c5beb765dce9e5ded2ea1332d86d288ba347dce
Author: Luc Verhaegen <libv@skynet.be>
Date:   Fri May 29 03:04:16 2009 +0000

    Implement native VGA Support.
    
    This code brings a rather complete set of VGA IO routines for whoever wants it.
    These consist of the by now familiar read/write/mask sets. Due to the crazy
    nature of VGA, an ancient standard with bits all over the place, it makes no
    sense to define individual registers. You need a vga register spec at hand if
    you want to do anything anyway. These IO routines are always exposed.
    
    It also provides code to natively set up a 640x400 VGA textmode with an 8x16
    font. The native VGA mode code is behind the OPTION_VGA option, as the font
    really adds to the size of the compiled/compressed rom. The font is the one
    also present in the linux kernel, but this file is unlicensed. Another copy of
    this is also present in coreboot in the deprecated console/btext code.
    
    The vga console code has been cleaned up, but it still has some TODO's left
    open, but that's for when i finally have found the remaining issue with the
    epia-m. Right now, it is important to get parts of my work out already and to
    make the remainder managable again.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 195f5cd66674433cf06dbfe57e0b9bd98bb3549c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu May 28 22:18:25 2009 +0000

    Add lzma.o for CBFS, regardless if CONFIG_COMPRESSED_PAYLOAD_LZMA is
    enabled or not.
    CONFIG_COMPRESSED_PAYLOAD_LZMA is set only if the lzma utility is found
    on the system - at least when using abuild. CBFS doesn't use this tool
    for compression.
    
    The result was a failed build if lzma (the tool) wasn't found, or
    failed runtime (if src/lib/cbfs.c disables lzma decompression based on
    CONFIG_COMPRESSED_PAYLOAD_LZMA)
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9f4eaf7ab8c39691fc8b2019d511bdd17b27a37
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu May 28 21:57:11 2009 +0000

    Make memmove copy (dev->resources -i) resource structs instead of
    (dev->resources-i) bytes in compact_resources.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7365004424f58db813a092c24c404ec99507765f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed May 27 18:55:19 2009 +0000

    First batch of indent-aided code cleanups, more will follow.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c044c732fc28b09eb58956a85b141af194f2b94
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed May 27 17:06:54 2009 +0000

    Make directory hierarchy flat to match the same layout we use
    for other chipsets, as suggested on IRC.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2a4e63f926a59759309d93e1af60e3c3f7d5c13
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed May 27 14:57:53 2009 +0000

    Trivial, but brown paper bag worthy:
    #ifdef CONFIG_foo
    is a bad idea with our build system
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a034dca42cc1638e4917e38b98e7dc6b434f2357
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed May 27 14:19:31 2009 +0000

    Move coreboot_ram and coreboot_apc to CBFS. This allows to
    reduce the size of the bootblock (done for kontron/986lcd-m)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8341f44f98ad6fe8760d348e7c3cca8f49eb2557
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed May 27 13:46:37 2009 +0000

    Change all vx800 file names from CamelCase to camel_case to match
    our coding guidelines (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 612163e3833e807caeed8889dae41d24026241e7
Author: Bari Ari <bari@onelabs.com>
Date:   Wed May 27 13:12:42 2009 +0000

    Here's the VIA vx800 patch from OLPC.
    
    It's untested, but a good starting point for everyone.
    
    Signed-off-by: Bari Ari <bari@onelabs.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e6e899dde951823ebc9abf997a6af06debac82a3
Author: Luc Verhaegen <libv@skynet.be>
Date:   Wed May 27 11:39:16 2009 +0000

    util/vgabios: build/warning fixes.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bab4f92c8bdde168ad186c054967e36dc5477d10
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue May 26 19:39:14 2009 +0000

    Clean up acpi table writing code, and don't rely
    on a given alignment for the RSDP and RSDT - look
    it up instead.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5429e26b9c5ccf36ee520a03a7d34454be03acc0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 26 18:01:53 2009 +0000

    Tell lpgcc about the target architecture directory. This slipped through since
    FILO does not use lpgcc (yet)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 21dbe8ad3cdd02e6665ff201e91695bba405d7a6
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue May 26 14:49:59 2009 +0000

    Make printk_* behaviour more consistent. Without it, side
    effects in the arguments (eg. a pci config read, or variable increment)
    "vanish" with the message, and the behaviour changes.
    
    Some of these effects might be unwanted, but at least they are consistent now.
    To reduce the memory footprint slightly, the formatted strings are discarded.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af7da7253383a54a7345aeaa1bb76f756945f746
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 26 14:37:17 2009 +0000

    encapsule mbi initialization in write_multiboot_table, where it belongs. (very
    simple and trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 736221f1b2c37cdcd5073d269484b4f1cf7a4e36
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue May 26 14:31:37 2009 +0000

    Make vsprintf reentrant. More importantly, eliminate global variable.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2152ecf4f5c09eb262c99557c2adc4c413ad897
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 26 14:07:44 2009 +0000

    Major cleanup of i386 tables.c:
    
    * fix copyright messages
    * remove all HAVE_HIGH_TABLES and HAVE_LOW_TABLES preprocessor hackery
      and instead use high_tables_base to find out if high tables should be used.
      The code path with high tables disabled and high tables not available for
      another reason should be the same.
    * put MP-table into Fseg instead of 0x10. This allows us to drop an huge and ugly
      portion of code. And it will make some ugly Linux warnings go away.
    * use ALIGN macro instead of hand crafted aligning.
    * renumber post codes in this piece of code (don't jump ahead and
      back anymore)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a84a99b9948fa431bbcadf39f5216b04b3eb1d52
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue May 26 14:03:51 2009 +0000

    Various fixes to the tree to get coreboot-v2 to build on Solaris
    
    - Replace $(PWD) with $(CURDIR) in Makefiles. I don't know why
      the Solaris version behaves differently, but CURDIR is a safe
      choice on gnu make (and we require gnu make already)
    - Use tail -1 instead of tail -n1 in a file that already relies on
      tail -1 support in another place
    - Use tail -1 as alternative to tail -n1 in another place
    - Use #define for ulong_t in romcc, as that name is used on Solaris
    - Avoid fprinting a null pointer. The standard doesn't mandate that
      this is a special case, and Solaris doesn't implement it that way.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d1185bfd358fa3d72d94255961926162eff9f609
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue May 26 14:00:49 2009 +0000

    Attached patch moves the CBFS payload loader to selfboot.c as it's
    the only selfboot user in CBFS.
    
    This way, CBFS can be used without importing selfboot.c, as long as
    no payloads are loaded.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 58bb497f89aecd57f3e6b66e4b1e35f4af22225b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 26 13:03:30 2009 +0000

    the i82801xx driver does not know ide{0,1}_enable in its chip.h, so comment it
    out in the mainboard config file. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 069385fcb32bed6fcbc1457b63733c802920bb84
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 26 12:58:00 2009 +0000

    ops can not be const because of the pci conf1/conf2 hackery we do. trivial
    patch, just removes the warnings like
    coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ac97.c:73: warning: initialization discards qualifiers from pointer target type
    
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69390dbba1b213f9af1a743b1dbae292cc96e9de
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 26 12:33:52 2009 +0000

    acpi.c: add a cast to remove warning (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b556a16d3e84b07766b76c2aee4586d08ef7c00
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 26 12:33:06 2009 +0000

    remove some dead code from cpu.c (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a5c27763f4483f42851c127547e6db0fc5b69bc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 26 12:22:10 2009 +0000

    Cosmetic cbfstool update (trivial)
    * remove some dead code
    * fix indentation
    * comment in some destructors and fix some other warnings
    * use HOSTCC instead of CC (not all the way cosmetic, but very simple)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bbe29ee06e7030bbba6e2c8c5790e785bf7f0c5b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat May 23 22:02:31 2009 +0000

    keyboard driver: function definitions should not omit void if they don't take
    parameters.  (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e2825504fde2023ee3fa322b408b80b4ccbaf97f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat May 23 22:00:58 2009 +0000

    fix comment in keyboard driver (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e445c5feee84a7a34657f98538771bbcd447b54
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri May 22 18:17:06 2009 +0000

    Make the getpir output look less crappy and add a license
    header template, as people keep forgetting them.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cf7f148ac8284aaf90ebf985d9a7fcdb5e19f697
Author: Ward Vandewege <ward@gnu.org>
Date:   Fri May 22 16:03:04 2009 +0000

    Fix MAINBOARD_PART_NUMBER to be h8dme, I forgot to change it from the h8dmr
    tree it was copied from.
    
    This is a trivial patch.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54336fde0eac3f7cdee034afb492342e3edd0f30
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu May 21 15:12:39 2009 +0000

    Defaulting to the board's default size is the correct thing to do.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d385ed29b94af71dedeb5f44d72ad8dab43c4664
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu May 21 10:02:52 2009 +0000

    This change adds PPC support to libpayload, and hooks it up in the build
    process.
    The PPC support is still stubbed, with commented out x86 code as guide
    line for an implementor.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1e6f6929c1ee96b291ef17e8d801f376a5dbb0d2
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue May 19 18:15:49 2009 +0000

    Trivial update of Config-lab.lb so that it works again.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9a6f0f442846b0ed631ddceb062e632c1154da4
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun May 17 20:36:45 2009 +0000

    Add type field to memranges, and fill it from the source data.
    type field contains e820 type ids, which are used by coreboot
    and multiboot (the two source formats), so they can be used
    as-is.
    
    The MEMMAP_RAM_ONLY define is a way to allow a payload to opt
    for only having CB_MEM_RAM type fields, which might be helpful
    to support older payloads easily (just add the define, and it
    won't encounter "weird" fields)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 56ae8fcb6fe545557c6b5a3ffb72f54bd3b53ddc
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat May 16 23:05:20 2009 +0000

    This patch implements a "flash friendly" value for initialized areas of flash.
    It makes the write part of flashrom dramatically faster with small
    payloads like filo; and it also eliminates unnecessary wear on flash
    by not writing zeros (it's unlikely this really matters; let me know
    next time you flash a BIOS flash 100,000 times!).
    
    More importantly, it allows for future partial flash upgrades with cbfs.
    
    Note that uninitialized_flash_value is a global that can, if we ever need it,
    be set by an argument in main. Assuming we ever see a flash where the
    "erased" value is 0, not 0xff.
    
    At the same time, "erased" value has been "1" on every EEPROM or
    FLASH I've used for some time now.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d12acea520840b64804ec7f2d1b9fba423ed194e
Author: Vincent Lim <vincent.lim@amd.com>
Date:   Fri May 15 18:02:25 2009 +0000

    There were a few updates lately that generates ROM size > 512K. I am changing the default ROM size to 1M to accommodate this and future changes. I tested on SimNow family10h_1p.bsd and it POSTs OK.
    
    Signed-off-by: Vincent Lim <vincent.lim@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99fd2a3b3ac587498b551c2c6e5d6d20f646e65b
Author: Marc Jones <marcj303@gmail.com>
Date:   Thu May 14 23:42:41 2009 +0000

    Update equivalent processor revision ID to load latest microcode patches and
    register setting for all FAM10 processors.
    This does not include new errata for FAM10 C2.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Vincent Lim (vincent.lim@amd.com)
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ea1e0c18a44abb17497a30557a61dda25ec2922
Author: Vincent Lim <vincent.lim@amd.com>
Date:   Thu May 14 22:11:08 2009 +0000

    Trivia: remove comment
    
    Signed-off-by: Vincent Lim <vincent.lim@amd.com>
    Acked-by: Vincent Lim <vincent.lim@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fed6475f6e245b3b14f92380ee187808a81e1d11
Author: Vincent Lim <vincent.lim@amd.com>
Date:   Thu May 14 22:00:28 2009 +0000

    From AMD family 10h Processor BKDG (rev. D): a platform is capable of having up to 8 nodes, and each nodes supports 1,2,3,4,5, or 6 cores.
    
    Signed-off-by: Vincent Lim <vincent.lim@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 671cedc92f24e1b1578bb00bd3bf8c019c4cdaed
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu May 14 21:26:28 2009 +0000

    #136: failed to boot under KVM\QEMU
    > -------------------------------------+--------------------------------------
    >   Reporter:  silicium@…             |          Owner:  somebody
    >       Type:  defect                 |         Status:  new
    >   Priority:  major                  |      Milestone:
    >  Component:  coreboot               |        Version:  v2
    >   Keywords:                         |   Dependencies:
    > Patchstatus:  patch needs review     |
    > -------------------------------------+--------------------------------------
    
    Fix use of uninitialized pointers. To help in future, move
    the declaration to the same scope as the use.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 67befdc22be1b12cf3a29fcef706dd2978bac539
Author: Ward Vandewege <ward@gnu.org>
Date:   Thu May 14 03:00:15 2009 +0000

    The cbfstool print command should pretty-print the type of components that are
    type 'deleted'.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df042a18ecb2c7a4605f706a12e78878a1ec1050
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed May 13 20:11:04 2009 +0000

    This patch fixes a segfault when a file too large to fit is added to a rom
    image.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a064b5239dd8cda663af5d99603ff21492ca52d7
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed May 13 20:08:28 2009 +0000

    Add support for human-friendly component string types for the cbfstool add
    command.
    
    Make use of it in config.g (Myles)
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5eceb32a79d4298a9f57bbe9fd5e06a83db0ce95
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed May 13 16:27:25 2009 +0000

    Allow dynamic size for the {s,}elfboot bounce buffer.
    Use that to fix selfboot with compressed payloads.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f047de352d26c353c1c6bc9649a4616fa66bbd6
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed May 13 14:39:59 2009 +0000

    Make ACPI with low and high tables work again. The RSDP contained a
    bogus RSDT pointer due to a wrong order of commands.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b35354d399d4ee201cd8f652335d8e1b1a79f7b
Author: Myles Watsonmylesgw <Myles Watsonmylesgw@gmail.com>
Date:   Wed May 13 02:48:58 2009 +0000

    Remove a shadowed variable and an unnecessary local variable in cbfstool/fs.c.
    
    It is nearly trivial.
    
    Signed-off-by: Myles Watson<mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f0482dd8b06ab4220ff2c1474008afc94481854
Author: Joseph Smith <joe@settoplinux.org>
Date:   Wed May 13 02:47:14 2009 +0000

    Oops forgot small part. Set up PIRQs in mainboard Config.lb for IP1000 and RM4100 instead of using the ones in i82801xx_lpc.c.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 459259e98dc9071279f385ea18c58993e2e66b9b
Author: Samuel Verstraete <samuel.verstraete@gmail.com>
Date:   Tue May 12 15:15:07 2009 +0000

    This is the final patch that got everything working for me with the HP dl145g3.
    I would like to remind you that this firmware enables the hardware
    virtualization on the AMD cpu's on the machine. That feature was
    explicitly disabled by the factory BIOS.
    Due to an error in the VGAROM no other rom loader (YABEL or X*^BIOS)
    than SeaBIOS manages to load the VGA rom. The VGA ROM tries to read
    config space of a device that is actually not present.
    Because SeaBIOS does not support AHCI SATA it can not start the
    bootable drive of the machine so i had to add filo to seabios to
    manage booting:
    ./cbfstool coreboot.rom add-payload filo.elf img/FILO
    
    Signed-off-by: Samuel Verstraete <samuel.verstraete@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c7cf64f1ea8407f1bc541c9f16fec872d52b450
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue May 12 15:06:54 2009 +0000

    This fixes a rather silly bug in cbfs with filenames > 16 characters.
    
    Tested to booting linux with qemu.
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson<mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 67ee8f86fb317e7faeb4772b28f28116efdf2e43
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue May 12 14:24:25 2009 +0000

    There's no 'svg2pdf' in Debian AFAICT, probably the same problem on
    other systems too.
    
    So, check for svg2pdf, convert, and inkscape and use the first one that is
    found to convert the SVG files to PDF.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 019b5f4230c8cbccbe0d513fe19eae43ea4c2d16
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue May 12 14:14:54 2009 +0000

    I guess a couple of function calls pushed these boards over the 0x1700 edge on
    the build server.
    
    Add Config-abuild.lb to fix s2892 & s2891.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d272486821c43af37f476838e6eaf657015cd34
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue May 12 14:03:12 2009 +0000

    Trivially copy Config.lb to Config-abuild.lb to fix asus/m2v-mx_se.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 503959c3567b69f022154cca70f9dc381407f7a8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue May 12 14:01:14 2009 +0000

    Fix pdflatex build issues (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd5d7566d3378b268ad96c8dc986ebfc477573a0
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue May 12 13:43:34 2009 +0000

    Use the debugging functions to print out the tree and resources.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb3d8128ed41f14162daa2241eba824723bc84fc
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon May 11 22:45:35 2009 +0000

    Bring v3-style debug output to v2.  Fix a minor typo.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0520d55f5b20ed0b5f192a695aff033320875233
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon May 11 22:44:14 2009 +0000

    This patch adds high table support to qemu.  It was already added to
    src/northbridge/intel/i440bx/ but not to
    src/cpu/emulation/qemu-x86/northbridge.c
    
    It also adds a driver for the ISA device that is found when using
    0.9.1  If you look in a log without this patch you won't find the RTC
    init lines.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 032a9653a6d5e1c61221358979a45852739ff379
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon May 11 22:24:53 2009 +0000

    Trivial white space fixes so that the next patches are easier to read.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7c29dada3e11f53fcc8c093db960eaf95b56bde7
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Mon May 11 13:45:11 2009 +0000

    We should separate the it8718f_24mhz_clkin like the way IT8712 does.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by; Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dcda7fd527abafea3a089f63d1b941b043c3c8b5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon May 11 01:44:54 2009 +0000

    Fix manual build on the Kontron board (trivial).
    
    A manual build was yielding section overlaps, so increase
    ROM_IMAGE_SIZE to the same size the Config-abuild.lb is using.
    
    Build-tested by me using a manual build.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c720795868d08bfcc07c16504e7132274899e907
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun May 10 20:35:18 2009 +0000

    Following patch fixes the XIP computation issue. I removed the normal image
    because it was not working anyway (it was hardcoded) and because it allows me to
    fix the XIP base to something sane (and use generic computation and approach)
    
    This board is bit tricky because until now it required the VGA BIOS on the flash
    start. XIP will work with 64KB aligned base, therefore the VGA ROM image must be
    aligned too to 64KB.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 442fc92b1f528902524412403f8c60ef4d0e1539
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat May 9 17:14:58 2009 +0000

    I would have liked to get an ack, but the error this corrects is pretty
    critical, since unless it is fixed this tool creates empty tables that cause
    coreboot to (in some cases, e.g. on qemu) triple fault and die.
    
    For the record, an empty option_table is not allowed. The table must,
    at least, have 3 32-bit entries in this order:
    type -- should be 200, 0r 0xc8, i.e. 0xc8, 0, 0, 0
    size of table in LE order, 4 bytes
    size of header in LE order, which is always 12,0,0,0
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b534e4256570ab100456837898c81aa581deeb09
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri May 8 20:07:00 2009 +0000

    Trivial clean up of print usage and parameter checking.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 475aeda9d6d62d0249276bff657adc67d206ff31
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri May 8 19:39:15 2009 +0000

    Add -Werror to help us keep the code clean.
    Change sizes from unsigned int to int.
    Clean up some usage and parameter checking.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 83b8f0c48550bb1b2cb1a6610b1f0010bf8533a4
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri May 8 19:23:00 2009 +0000

    I have made a very simple mod to cbfstool that is compatible with the
    src/lib/ code in coreboot. I.e. the tool changes but the coreboot code
    does not.
    
    Currently, as cbfstool manages the ROM, there are files and empty
    space. To allocate files, the code does, first, a walk of the headers
    and, if that fails, does a brute-force search of the rest of the
    space.
    
    We all agree that the brute-force search has lots of problems from a
    performance and correctness standpoint.
    
    I've made a slight change. Instead of an "empty space" area with no
    valid headers, I've made a header for the empty space.
    
    So cbfs creation looks like this:
    - set up the boot block
    - create a file, of type CBFS_COMPONENT_NULL, that contains the empty
    space. CBFS_COMPONENT_NULL was already defined in cbfs.h
    
    Here's an example:
    
    [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs create 1048576 2048
    (cbfstool) E: Unable to open (null): Bad address
    [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print
    testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0
    Alignment: 16 bytes
    
    Name                           Offset     Type         Size
                                  0x0        0xffffffff   1046456
    
    So how do we create a new file?
    
    It's easy: walk the files and find a file of type CBFS_COMPONENT_NULL,
    which is as large
    or larger than the file you are trying to create. Then you use that file.
    - if the file is the same size as the NULL file, then it's easy: take it
    - if the file is smaller than the NULL file, you split the NULL file
    into two parts.
    
    note that this works in the base case: the base case is that the whole
    storage is CBFS_COMPONENT_NULL.
    
    Here's an example of adding a file.
    [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs add-stage testfixed t
    [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print
    testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0
    Alignment: 16 bytes
    
    Name                           Offset     Type         Size
    t                              0x0        stage        23176
                                  0x5ab0     0xffffffff   1023240
    
    Note that the NULL split and got smaller. But the entire ROM is still
    contained by the two files. To walk this entire rom will require two
    FLASH accesses.
    
    Add another file:
    [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs add-stage testfixed tt
    [rminnich@xcpu2 cbfstool]$ ./cbfstool testcbfs print
    testcbfs: 1024 kB, bootblocksize 2048, romsize 1048576, offset 0x0
    Alignment: 16 bytes
    
    Name                           Offset     Type         Size
    t                              0x0        stage        23176
    tt                             0x5ab0     stage        23176
                                  0xb560     0xffffffff   1000024
    [rminnich@xcpu2 cbfstool]$
    
    So, taking current ROMs as an example, I can reduce FLASH accesses for
    cbfs from (potentially) thousands to (typically) less than 10.
    
    Index: fs.c
    Changes for readability and cleanliness. Move common blobs of code to functions.
    New function: rom_alloc,which allocates files by finding NULL files and using/splitting.
    Other changes as needed to support this usage.
    Index: util.c
    Creating a cbfs archive now requires creation of a NULL file covering the file system space.
    Index: cbfs.h
    Add a DELETED file type with value 0. Any file can be marked deleted by zero its type; this is a
    FLASH-friendly definition for all known FLASH types.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    I think it is a step in the right direction.  Could you add the
    function prototype to cbfstool.h?
    
    Acked-by: Myles Watson <mylesgw@gmail.com>
    (I added the prototype)
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa1df9cba598ff1ddbf81d182a9f978f89daf2e8
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri May 8 00:45:47 2009 +0000

    Trivial fixup IRQS on IP1000 and RM4100.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b04724a0a8db6089f4a175dc34550bc3c50a400
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri May 8 00:24:24 2009 +0000

    Set up PIRQs in mainboard Config.lb for IP1000 and RM4100 instead of using the ones in i82801xx_lpc.c.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 06025df741a9c812040a0a80167a8b8f5da9962f
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri May 8 00:19:13 2009 +0000

    Disable the AC97 modem via the ICH4 LPC disable function register early in the boot process.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 919b56e6ea23c0852ad39c09c06c5213d1210f34
Author: Joseph Smith <joe@settoplinux.org>
Date:   Thu May 7 05:47:05 2009 +0000

    Trivial checksum fixup for irq tables on IP1000 and RM4100.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ac37ca11334fd0e2b63e5165c667413500de3ff
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu May 7 00:21:02 2009 +0000

    Fix my last commit. I looked at the wrong dead laptop.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0dae44c71f695708a633512199dd10e4f765e44f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu May 7 00:03:18 2009 +0000

    Support for detecting the SMSC FDC37N869 (trivial).
    
    No datasheet available, chip identified by probing and looking at the PCB.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1bb3675c1920d18d2ebee76cc46aa57d217b11a1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue May 5 14:06:20 2009 +0000

    Fix a bug introduced in the copy_and_run refactoring.
    The new code always decompressed to dst (as it should)
    and then jumped to _iseg, when it should jump to dst.
    
    With dst != _iseg this breaks (coreboot_apc)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f95b49eeb8f2fd817869c363295d1467d86be9be
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon May 4 20:27:09 2009 +0000

    This patch removes these warnings:
    Makefile:435: warning: overriding commands for target `src/lib/memset.o'
    
    And replaces these debug messages:
    partobj dir 0 parent <__main__.partobj instance at 0x7f1e846a7ab8>
    part pci_domain
    with:
    partobj dir 0 parent northbridge_amd_amdk8_root_complex_dev2 part pci_domain
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef04d82ec637edf37df5e0f8d183348d78d358f7
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon May 4 19:26:43 2009 +0000

    The rev 4099 broke ECC boards, they need to have tidy the ECC tags. Myles reverted this change.
    I think we can return the 4099 back under HAVE_ACPI_RESUME define to make everyone happy (and booting ;).
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f0154c937fbf819e34ffbb3a71dc246fb6079c1
Author: Joseph Smith <joe@settoplinux.org>
Date:   Sat May 2 21:30:57 2009 +0000

    Assign PIRQs in mainboard Config.lb or use the default ones listed in i82801xx_lpc.c.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88e71e88597d939972267cdb00aca3cc61f5e171
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat May 2 12:42:30 2009 +0000

    Run dos2unix on all files:
    
    find . -type f| grep -v svn | xargs dos2unix
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a0dbddff17986266da3342cbfb3b8194588664d0
Author: Joseph Smith <joe@settoplinux.org>
Date:   Sat May 2 00:59:03 2009 +0000

    Trivial, update email address.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fff297327d09881e3a2720f67c28532c50e16499
Author: Joseph Smith <joe@settoplinux.org>
Date:   Sat May 2 00:50:58 2009 +0000

    Trivial fix up to the GPIO's connected to the IP1000 and RM4100, only set ones that are actually connected to something.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3544c6b3b0380b893d6e037e199d32c248949669
Author: Peter Stuge <peter@stuge.se>
Date:   Fri May 1 14:33:19 2009 +0000

    Trivial removal of svn:executable property from vga.c.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03c65ef4e73a5f78947e88ad6255b9ab8eaa028f
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri May 1 04:53:58 2009 +0000

    This is a patch to use another IRQ besides IRQ12 to fix conflicts with i8042 - PS/2 Mouse.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5252b1184a20ddd40ad7ee7be87cc95130fc5d77
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri May 1 04:44:36 2009 +0000

    This patch changes the default rom emulator to VM86.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97e6dfed12604774434c2ba1abeba9ac34062d70
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri May 1 04:37:13 2009 +0000

    This patch allows a custom vga driver that will give the flexibility to run code after vga is initialized for tv-out.
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96a46920f2d0e18ca4ab0e50d9c04c207dde3615
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri May 1 04:36:38 2009 +0000

    Trivial patch to make #defines generated from cmos.layout have unique names.  Kills a few more compiler warnings.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 183cadda26e28b4612697f66760b6463f11e6e9f
Author: Joseph Smith <joe@settoplinux.org Acked-by: Joseph Smith joe@settoplinux.org>
Date:   Fri May 1 03:04:20 2009 +0000

    Trivial cosmetic fixes to IP1000 and RM4100 irq_tables.c Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 041734d859706b31122dfd0907486063371a4693
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri May 1 02:24:40 2009 +0000

    The semantics of the changed code are pretty simple and looking at
    other parts of the same file shows that it is a common construct.
    
    Remove the shadowed variable.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa12b67771f73f0e7acf2308a13cf33b8c619884
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Apr 30 22:45:41 2009 +0000

    Remove warnings from compilation of the s2892 with and without CBFS.
    
    I didn't try to remove "defined but not used" warnings because there are too
    many ifdefs to be sure I wouldn't break something.
    
    For shadowed variable declarations I renamed the inner-most variable.
    
    The one in src/pc80/keyboard.c might need help.  I didn't change the
    functionality but it looks like a bug.
    
    I boot tested it on s2892 and abuild tested it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d233f363c129dae2ba5fd7ac536cf92fb4c2dd6e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 30 16:46:12 2009 +0000

    Some driver fixes for libpayload:
    - fix minor bug in serial driver.
    - latest USB stack fixes
    - fix dead store in options.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5fb0c5c4eda2329d848aedcf4f7e8b6dc8012b2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 30 13:58:42 2009 +0000

    Add high tables support to all northbridges.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6841ce653741b3dafe8e3482b4a93adbaee53552
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Apr 30 12:53:00 2009 +0000

    Trivial fix for tyan/s2735: a newly used option wasn't defined as "used"
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94875b3f626fd06b957ff469cf7ebedb9a16e96c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 30 10:16:39 2009 +0000

    Add "printk" support to all CAR targets
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7757f20ac3bf8771c3cabfef1c0970dbb12bd2a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 30 10:14:22 2009 +0000

    * Use latest version of intel microcodes from their Linux drivers page for
      models 6ex and 6fx (core and core2 solo and duo). Also, use the names suggested
      by Intel for the microcode files instead our short version of it. This allows to
      create new microcode patches with a simple set of scripts.
    * some minor cpu setup fixes for c and p states
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cf95bfc64eecb289f5559da19307b737aa96488
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Apr 30 07:23:15 2009 +0000

    And add the new file I forgot to "svn add" in the last commit.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12aba82e55c02470ed80b7682efa8b4e8f702bc1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Apr 30 07:07:22 2009 +0000

    Refactor copy_and_run so that it uses a single code base instead of
    3 (with one of them way too much assembler code).
    
    On the way, I had to make some changes to the way the code is built,
    which is an effort I want to expand over time.
    Right now, large portions of the in-ROM part of coreboot is compiled as
    a single file, with lots of .c files including other .c files.
    That has its justification for pre-raminit code, but it also affects
    lots of post-raminit code (memcpy doesn't really make sense before
    raminit, or at least CAR)
    
    The coreboot_apc code (AMD boards) gained some .c includes because I
    don't know that part of the code enough to really rework it and only
    have limited possibilities to test it. The includes should give an
    identical situation for this part of the code.
    
    This change was posted as set of 6 patches to the list, but they
    were mostly split for review purposes, hence commit them all at once.
    They can still be backed up using the patch files, if necessary.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a43ee75d9a7dc859292b186f22ac0550f149a0a3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 29 20:34:41 2009 +0000

    increase image size
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1ff26a777835c740610f549f00bcd450ae571c0e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 29 19:11:18 2009 +0000

    working memalign version for libpayload. This fixes problems with the USB stack
    in FILO.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c9617dc945c8e1aa2a38e287908630fcb217869
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 29 19:10:10 2009 +0000

    Mostly cosmetical changes.
    - #if 0 some incomplete, non-working code instead of failing half way through
      the function
    - Don't read a NULL pointer in wclrtoeol
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ae0bcefe1aecb34b6903f0d3aa08e317dea4215
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 29 19:09:19 2009 +0000

    don't initialize "in" as it is initialized again one line below.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 76b5d20d7815841e009d1d54f7929ec3034ec688
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 29 19:08:29 2009 +0000

    getopt for libpayload. in case someone wants to pass parameters to payloads and
    parse them.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8a939eab5f712838a41ffdb69e470377f1381cc
Author: Vincent Lim vincent.lim <Vincent Lim vincent.lim@amd.com>
Date:   Tue Apr 28 16:36:16 2009 +0000

    dd the family10h Rev C0-C2 support to coreboot.
    
    Signed-off-by: Vincent Lim vincent.lim@amd.com
    
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 870f0133f4dd6ee35d1cc54924f5339a23048f5e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 28 14:49:50 2009 +0000

    fix warning: no return statement in function returning non-void
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b04403e7f7145a60300d869c0a883b55dbd347c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Apr 28 14:49:21 2009 +0000

    Only add ACPI tables if ACPI is enabled for the board.
    Trivial fix to make abuild happy.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a19f64479946a2972331855389635db16fa2623e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Apr 28 14:18:16 2009 +0000

    Enable HAVE_HIGH_TABLES by default for northbridges with
    support for it.
    The related mainboards don't need to activate it
    themselves anymore.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bccaafc677c3b51c730baebf83073f8db166550d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Apr 28 12:57:25 2009 +0000

    add_mainboard_resources is necessary for some boards (eg. kontron), but
    this generic code could be added to the caller of
    add_mainboard_resources (wrapped in HAVE_HIGH_TABLES, of course).
    That way, boards that really need it (for other things) can use this
    function, while others don't have to do anything to use
    HAVE_HIGH_TABLES.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d107593691631ff1ae34fbb98d03d5085ed5b07a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Apr 27 20:19:48 2009 +0000

    Add high table support to via vt8454c.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 55faef348a8dd20ac777f75fe00e8772a7655d7a
Author: Ward Vandewege <ward@gnu.org>
Date:   Mon Apr 27 20:19:06 2009 +0000

    Add high tables support for Supermicro H8DME.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d0b93bb54ba3bf8c693fc7c80f1ec1e7bff65da
Author: Ward Vandewege <ward@gnu.org>
Date:   Mon Apr 27 20:00:29 2009 +0000

    Special handling for MP table in low memory is only necessary if there are
    tables in low memory.
    
    This removes a hang when HAVE_LOW_TABLES=0 and HAVE_HIGH_TABLES=1. With this
    patch I can boot all the way to a payload. Tested on a Supermicro H8DME.
    
    Many thanks to Patrick Georgi for figuring this out.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1670857cc9f0958e4b78b08bfcc0b91c53c7f2c8
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Apr 27 18:31:09 2009 +0000

    Migrate via/vt8454c to CBFS.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 932257869f0bf037a3ad5f728bbc9650cc34dd1d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Mon Apr 27 18:26:43 2009 +0000

    Create a valid stack pointer after leaving CAR, so function calls don't
    reset the machine in the small window between CAR and coreboot_ram.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc9de2f1e2b9582f0bd692ef3b8f3cc98d32bfb5
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Apr 27 16:08:26 2009 +0000

    Revert 4099 patch that causes an ECC error.  Memory has to be written while ECC
    error checking is disabled.  The purpose of the patch was to preserve memory
    used by ACPI resume code.  One possible solution is to read that memory and
    write it back while ECC error-checking is disabled.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d6ce50a1e76a59cdadf47a1d3770fb061353906
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Apr 26 19:50:53 2009 +0000

    Change Flashrom's URL to svn://coreboot.org/flashrom/trunk.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6388d491434d2df6a0ea03e5a8131e46b1128e38
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Apr 26 18:17:40 2009 +0000

    Flashrom is now moved over to its own repository.
    Add a note to the coreboot-v2 version of the tree that
    contains the new location.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb2c61d844cedbe7709a784b7a713bb7a6f44956
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Apr 26 07:20:45 2009 +0000

    Use pci_rom, as we have it. Thanks Myles!
    trivial patch.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 79cba771fccb254d5f174db1d182cf4a3b1fec8f
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Apr 26 07:15:19 2009 +0000

    Trivial: allow "," in filenames
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b61bc7c68a54ec3c8701c1aebdf70ceac50c176b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Apr 25 22:15:29 2009 +0000

    Enable CBFS for qemu and kontron. Both are builds-and-runs
    tested, incl. optionrom-in-cbfs for kontron, and compressed payloads
    for both.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit baa4374cad5fe7e870a8ad7b95f7852f1ae2ee81
Author: Stephan Guilloux <stephan.guilloux@free.fr>
Date:   Sat Apr 25 22:07:28 2009 +0000

    The flashrom makefile wants to redirect both stdout and stderr to
    /dev/null for one compile test.
    The old variant of using &>/dev/null works on bash and zsh, but not on
    dash and tcsh. dash and tcsh interpret it as "background command and
    truncate /dev/null" which is not what we want. >& works on tcsh and
    bash, but it is not POSIX compliant.
    Since make uses /bin/sh and /bin/sh has to be POSIX compliant, we can
    use the POSIX variant of stderr and stdout redirection.
    
    >/dev/null 2>&1
    is POSIX compliant. This is specified in SuSv3, Shell Command Language,
    sections 2.7.2 and 2.7.6.
    
    Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dcce5210c7c9b1f81cb1a968a9f9d91e2f719bb5
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Apr 25 14:39:12 2009 +0000

    Make the CBFS file lookup skip file data instead of brute-forcing
    its way through it, looking for magic numbers.
    For one, it should speed up file access, esp. with many entries,
    but it also helps against false positives (eg. seabios, which
    contains the magic number for its own CBFS support, which _might_
    just be aligned properly)
    
    Also avoid infinite loops and give up searching for new files for
    invalid magic numbers.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 72631a01fa42cd419f8b40351cc7306fe149e334
Author: Myles Watson <mylesgw@gmail.com>
Date:   Sat Apr 25 12:39:04 2009 +0000

    The master cbfs record was located at the end of the flash and overwrote
    anything that was there.  For ck804 or mcp55-based machines that was the
    romstrap.
    
    The fix is simple:
    1. Put the master cbfs record above the bootblock instead of on it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fe6201651233fbeff7aaef84211286e7716bf8a9
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Apr 25 07:33:25 2009 +0000

    Enable cbfs payload compression (the "l" flag) if payloads are
    supposed to be compressed (with lzma only, as cbfstool lacks
    nrv2b compression support for now)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 369bc7882a6fa26bbcbd4d050a26fbc496cfdc47
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Apr 25 07:32:24 2009 +0000

    Move decompression further down the code flow, so that - where
    possible - code is decompressed directly to the right place
    (instead of copying around, as before).
    
    The downside of this approach is that it's not possible (without API
    changes to the decompressors) to put partial segments into bounce
    buffers. So if a segment collides with coreboot _and_ is compressed,
    it's bounced entirely.
    But, as this only brings back the copy we already had before, the new
    worst case is better than the average before.
    
    It also fixes handling of compressed segments.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7994164a0ee8c58c47ed2dbe06807cb91ac62778
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 24 16:44:34 2009 +0000

    Remove the inclusion of lzma.c (which really contains code)
    from another (rom_stream.c and others), instead linking it like any
    source file should be linked.
    
    The same should (and will) be done with nrv2b.c, but that has some
    deeper implications as various CAR implementations include that
    directly, and thus requires more care.
    
    It fixes an issue with the cbfs code.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a5de85cb861e1aa4ea429aa5d0fa1dd21e30a611
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 24 16:17:41 2009 +0000

    MAX may already be defined. Also, fix smaller cosmetics (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2895c45486e4f6c99013bf319ff7277e51aad32d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 24 10:23:56 2009 +0000

    Another v3-style #ifdef in v2 to kill
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d0ff4c12623300886516edae6e124c950be3c86
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Apr 24 06:32:29 2009 +0000

    These are some really horrible bugs that got through.
    
    (and, for the record: no more #ifdef in coreboot. We're not going to
    have this happen again. If we do have it in v2, let's remove it.)
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cec6dc4c15f7c2bb7c245c76e61f2ee41c3fa649
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 24 06:28:48 2009 +0000

    Change the behaviour of the ACPI generating code so it only
    writes at most one full ACPI table.
    In the cases where both HAVE_LOW_TABLES and HAVE_HIGH_TABLES
    are enabled, the table is written to high memory, and an RSDP
    is written to the low memory that points to the high mem one.
    All other cases work exactly the same way as before.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e9149038ee852df06ca1269d9179f84e91353bfa
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 24 06:27:31 2009 +0000

    Remove duplicate code.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a30a5f891885daafd548e3cb3ab16ea94b781d3
Author: Stephan Guilloux <stephan.guilloux@free.fr>
Date:   Thu Apr 23 22:51:56 2009 +0000

    flashrom: Support MX25L3235D
    
    Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 424638e7bbd7b47118ed515f6fb32162dbd0c201
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Apr 23 22:22:47 2009 +0000

    Add 'install' target for ectool (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 06db2c44825d5a69bf1139c1348ca95296ccf453
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Apr 23 18:46:32 2009 +0000

    Fix an uninitialized variable.  If it didn't end up being zero it sometimes
    caused a seg fault, sometimes executed somewhere else.  Also add an error if
    the algorithm is unknown.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 436b9de0a31095e4da0dbcba8e4004a480ed215b
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Apr 23 17:01:37 2009 +0000

    This patch cleans up Makefile generation.  It removes the
    coreboot.romfs file since CBFS will eventually be the standard.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a44228c435d129740ced86fe66e9641af165b11f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Apr 23 14:57:55 2009 +0000

    Don't duplicate option description in README, the manpage already has
    that info. Also, additional small cosmetic fix.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 72deb69ce16f07b4a79e59d1f386744a9adcc4d2
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Apr 23 13:41:12 2009 +0000

    Add VERSION to hp/dl145_g3. Trivial.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4195 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4940ab7a2116110a26c78b515c290352dee084aa
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Apr 23 13:05:45 2009 +0000

    This patch hooks up git mirrored svn revisions and adds some
    error checking to the svnrevision call.
    
    If a .svn directory exists in the top level directory and the svnversion
    utility is available, we use svnversion.
    Otherwise, if a .git directory exists in the top level directory and the
    git utility is available, we use git log.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c245ff70e85b86fe776640e43b92e3500b95d4a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Apr 23 03:59:33 2009 +0000

    This continues the doco attempt.
    
    This also mentions some ideas on the new booting setup for v2.
    
    The latest changes will remove all need for people to do math.
    
    With Peter's corrections as well.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 476053356bc429e126a643bf1692106228e1efa6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 23:39:19 2009 +0000

    Instead of just
    
      coreboot-v2 $ util/abuild/abuild -t kontron/986lcd-m $PWD
    
    you can now also say
    
      coreboot-v2 $ util/abuild/abuild -t kontron/986lcd-m/Config-myconf.lb $PWD
    
    and instead of using Config-abuild.lb or creating a temporary Config-abuild.lb,
    abuild will use the existing Config-myconf.lb to build your image.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9f0f1055f2834efeb955c3cd36406962e0980cf0
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Wed Apr 22 23:27:25 2009 +0000

    Sometimes when we debug the code, we need to know which version we are
    working on.
    Add the svn revision to the coreboot version string.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f182456013a4416e176b000076b9f101c144d586
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 23:17:44 2009 +0000

    mini fix to reliably compile inteltool on darwin, and on Linux both on x86/x86_64.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 554fce6ced7a13e3f5961fbc7b2be1e5a2d4f6ad
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 22:55:15 2009 +0000

    makes the smi handler a little bit less verbose
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6196a494c82d29b85da8b4e2a9a7a35abce78e8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 22:43:02 2009 +0000

    fix compilation of hp dl145
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4188 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6315274cc89642bad0ff5518b0907a569814ac4c
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Apr 22 22:25:45 2009 +0000

    This patch fixes the parser.  '|' has special meaning so [|] is used.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85b851add801eee5de517d32a92048bb223d4054
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Apr 22 22:08:00 2009 +0000

    Convert 12 more boards to use include statements in Config.lb.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 723bf0c568697bf0442ff1424e696ea38690934b
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Apr 22 20:41:42 2009 +0000

    Trivial patch.  I forgot to update K8_SET_FIDVID.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5b34bdd3e5c9b7b5d72ea24ec1fc152e996ef2f7
Author: Mondrian nuessle <nuessle@uni-hd.de>
Date:   Wed Apr 22 20:34:05 2009 +0000

    This patch adds the target hp/dl145_g3 together with
    the appropriate mainboard sources.
    
    Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
    Acked-by: Samuel Verstraete <samuel.verstraete@gmail.com>
    
    I updated some whitespace and the Config files. - Myles
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 21da019a1e2840ef8c17d0733c574fa4abd4eedd
Author: Mondrian nuessle <nuessle@uni-hd.de>
Date:   Wed Apr 22 20:30:42 2009 +0000

    This patch add rudimentary support for the superio functionality of
    the Serverengines Pilot BMC chip. Necessary to get serial out on the
    HP DL145 G3.
    
    Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
    Acked-by: Samuel Verstraete <samuel.verstraete@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9b1c4f42f8e2fc4c3e44fa23f815c68e5127385
Author: Mondrian nuessle <nuessle@uni-hd.de>
Date:   Wed Apr 22 20:27:53 2009 +0000

    This patch adds support for the BCM21000 (aka HT-2100)
    PCIe bridge.
    
    Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
    Acked-by: Samuel Verstraete <samuel.verstraete@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f52d11e9ee15e72c6d7ec23e1cc9f4d25dd264c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 18:16:20 2009 +0000

    drop duplicate compiler options that are already mentioned in CFLAGS.
    (scan-build chokes on this)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d59eaa93b49d42300f3e23a27e6b568e5760348
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 16:32:18 2009 +0000

    - printed CBFS rom address was always 0
    - drop dead code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f96c2d96a87a7da6c843242d210720383d73fcbe
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 16:23:47 2009 +0000

    fix warnings, shadowed declarations and style guide violations (all trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7faa7d6bde8693cdf089c869d6929f9b261548bd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 15:49:28 2009 +0000

    increase rom sizes for abuild
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e5b44ab4dc3515151379b41cdacffe6a20e4b63c
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Apr 22 13:33:43 2009 +0000

    All "unknown xy SPI chip" entries claim to have status UNTESTED for
    probe/read/erase/write. That is incorrect.
    
    A bit of confusion comes from how the #defines are named. We call them
    TEST_BAD_*, but the message printed by flashrom says:
    "This flash part has status NOT WORKING for operations:"
    
    Something that is unimplemented is definitely not working.
    
    Neither of the chip entries mentioned above has erase or write functions
    implemented, so erase and write are not working.
    Since their size is unknown, we can't read them in. That means read is
    not working as well.
    Probing is a different matter. If a chip-specific probe function had
    matched, we wouldn't have to handle the chip with the "unknown xy SPI
    chip" fallback. I'm tempted to call that "not working" as well, but I'm
    open to discussion on this point.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8afdb1c433bff17fc466de33aeb06f0f6f87e470
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 12:38:23 2009 +0000

    drop unused variable.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit afa598543317fb97082b263f550ac1162ac43281
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 12:35:57 2009 +0000

    no duplicate names in cmos.layout allowed. (fixes a bunch of boards)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 257ae3f520fae9b82c669115a8d548596ae26f48
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Apr 22 12:28:14 2009 +0000

    Quick 'indent' run on ectool with some additional manual cosmetic fixes.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0408bdd240e05ff41e24a1b9aa3f0e83f983f785
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 12:14:39 2009 +0000

    don't ignore return values (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 570933cad80fbfed7939b460139dfe43fe24ca2d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 12:00:17 2009 +0000

    remove some style guide breaks and warnings from raminit_f_dqs.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 38c49fdddec1bfe31d5f4f133a84e97aa48cac67
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 09:06:38 2009 +0000

    argh... never redo parts of the original patch on the fly. This fixes the tree
    again.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 73d5daaf97465776a4ef6ae5c99a5badaeba292b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 09:03:08 2009 +0000

    * Allow coreboot to use the full 256 bytes of CMOS memory
    * Make functions out of the accessor macros in mc146818rtc.c
    * don't hide reserved cmos entries from coreboot, only from the user.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 953253f093302ccee1cc634772a4561ffbe32355
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 08:56:50 2009 +0000

    This patch unifies the socket_mPGA604_800Mhz and socket_mPGA604_533Mhz to a
    combined socket_mPGA604. No other sockets come with clock rates, and there is
    no difference in code, except for the number of microcode patches included in a
    build.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da65fbf2082ae46b609c21d23ba39af45574be13
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 08:18:37 2009 +0000

    Factor out acpi_create_madt_lapics. It can be used on all ACPI boards.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e9771cc1a02f4154cd655386219ea69578e01f0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 08:17:38 2009 +0000

    * move i386 / ACPI dependent code out of hardwaremain.c and into the i386
      acpi code.
    * add some defines for FADT flags
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 18d7320d17622e3fb87caae3eea645d8b06f942f
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Apr 22 08:10:48 2009 +0000

    Remove the requirement for payload.sh files to be executable. This
    helps if the file is generated from patches, esp. if that happens
    often (eg. with quilt)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6af0cb6efc64bcf694056fee1e31b0f4631661aa
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Apr 22 08:07:31 2009 +0000

    Trivial removal of a freudian slip.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5ab323a4036d86654c562b957d12f4dd4789bde
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 22 07:23:00 2009 +0000

    A small utility to dump the RAM of a laptop's Embedded/Environmental
    Controller. Nothing fancy, does not know any laptops, EC types, or what
    the values mean. It just dumps them. For the dump method, have a look at
    the ACPI 3.0b spec.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e16bf3a5511b83a28769f3ff3622b3ca5aadcab
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 21 23:05:13 2009 +0000

    - function prototypes do not need "extern"
    - fix up debug messages of usb debug console
    (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6236edd47e2e470b9dfd756c24ced2f4c735e34
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Apr 21 23:03:20 2009 +0000

    flashrom: Add support for Gigabyte GA-MA790FX-DQ6. This board uses
    IT8718F LPC->SPI translation for the flash chip.
    
    Tested by Mateusz Murawski.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Mateusz Murawski <matowy@tlen.pl>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6fa03176371fc3ea2896e427050701a03bfc6c1e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 21 23:02:40 2009 +0000

    remove a few warnings, and comments Ã¡ la #include <foo.h> // include file foo.h
    (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4855f56df92477d2082c780055cadc2e96ba0f28
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 21 23:01:10 2009 +0000

    add define for Role-Based Error Reporting to PCIe defines (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5bba7529d235368530a6e5248710ac053e142f0a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 21 23:00:14 2009 +0000

    fix a warning for a misnamed define, and make a debug message printk_debug
    (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 507d843eb03c4fe3153df7e99954c2eb0517cea9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 21 22:59:00 2009 +0000

    CONFIG_CHIP_NAME is dead (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 236d1023de5f0c8cd6962f8829542ad77fc8079e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 21 22:05:50 2009 +0000

    small updates as suggested by Carl-Daniel Hailfinger.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebf2589e3b9fd15acd41c5b9d430ccad9823162e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 21 21:45:11 2009 +0000

    Update to this very old document
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df444bf68abe840ad05d689996110e9354a2fa6e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Apr 21 20:34:36 2009 +0000

    Add a helper function to acpigen to create _PSD tables.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d3e712d5698b75270acfafaf7cf1c15aeb0be8a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Apr 21 20:31:18 2009 +0000

    Add an "-l <num>" argument to abuild that sets the LOGLEVEL variables
    to the specified value.
    
    Only change Config-abuild.lb, as the others are for manual buildtarget
    use - adding __LOGLEVEL__ there would kill the build as it isn't
    replaced by the actual content.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 16cdbb244cded6f3d8df719b7a0217fdf6bf327d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Apr 21 20:14:31 2009 +0000

    Eliminate various issues brought up by scan-build.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5cda45d5ec2dc2b112cb7ec1a95b861f1fa9fd2b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Apr 21 12:41:55 2009 +0000

    scan-build prefers -include over --includes=, gcc knows both.
    With this change, romcc knows -include and the build system uses it.
    
    Also use a full path to settings.h because scan-build has trouble
    finding it otherwise.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7bd658873c5b4066b4f247255cb7a98ba1750cd1
Author: Stephan Guilloux <stephan.guilloux@free.fr>
Date:   Tue Apr 21 01:47:16 2009 +0000

    flashrom: Support Macronix MX2512805D flash chip
    
    Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9ceb65434731223ce01c1c741a7736c1d29cfc1
Author: Stephan Guilloux <stephan.guilloux@free.fr>
Date:   Tue Apr 21 01:46:07 2009 +0000

    flashrom: Trivial indent fix
    
    Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b266f6fc16d128636c20f2c37772e32b1b9aa922
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Apr 21 00:25:23 2009 +0000

    Somehow svn add didn't work for the include files. Commit the remainder
    of r4147.
    
    Thanks to Myles' patch adding support for include statements,
    refactoring Config.lb became possible.
    
    Factor out ROM size calculation from Config.lb.
    
    This patch converts 87 boards (with and without USE_FAILOVER_IMAGE),
    but it has to work around a parser bug.
    
    89 files changed, 209 insertions(+), 2415 deletions(-)
    A total of 2206 removed lines.
    
    Abuild works for all changed boards on khepri.
    
    Myles writes:
    I've tested serengeti for the failover portion and s2892 for the
    nofailover portion.  ldoptions are exactly the same and they both boot
    the same.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5e10bcf1fdaa684189581b65861ab6f7775c4f1
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Apr 21 00:16:06 2009 +0000

    Thanks to Myles' patch adding support for include statements,
    refactoring Config.lb became possible.
    
    Factor out ROM size calculation from Config.lb.
    
    This patch converts 87 boards (with and without USE_FAILOVER_IMAGE),
    but it has to work around a parser bug.
    
    89 files changed, 209 insertions(+), 2415 deletions(-)
    A total of 2206 removed lines.
    
    Abuild works for all changed boards on khepri.
    
    Myles writes:
    I've tested serengeti for the failover portion and s2892 for the
    nofailover portion.  ldoptions are exactly the same and they both boot
    the same.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 108950972504f37cc354f79a0aa0895eae751523
Author: Stephan Guilloux <stephan.guilloux@free.fr>
Date:   Mon Apr 20 22:54:13 2009 +0000

    After verification in datasheets, all MX25 accept the same opcodes
    0x60 and 0xC7 for Chip Erase.
    
    Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b88a1fcd804ecd9f5aeaaf542e741478a11d36ab
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Apr 20 22:10:34 2009 +0000

    A little more info. Failover docs are next, then proposed new mechanism
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit feaaedc1cf99c12b8d1ab4bb233a311044d7f8b0
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Apr 20 21:38:11 2009 +0000

    This patch adds
    
    cbfstool extract [FILE] [NAME]
    
    It also factors out the csize calculation in rom_add, and fixes rom_delete so
    that it can handle deleting the last entry.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2cecce5740a23327a1095c6cba6e295e4b4d2963
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Apr 20 15:36:57 2009 +0000

    Continuing the slow doc-o update
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit caf884ca8c1b171b0afb62689c3222c86b4b6e9e
Author: Luc Verhaegen <libv@skynet.be>
Date:   Mon Apr 20 12:38:17 2009 +0000

    flashrom: board_enables: reconstruct table.
    
    This patch restores the pciid based board matching table. It makes this
    table readable and hackable again, and the only disadvantage is that the
    right margin is way beyond the rather dogmatic 80. All 0x0000 pci ids have
    been string replaced by 0 to more easily spot missing ids, and extra
    comments have been added to explain how the various entries are used.
    
    Signed-Off-By: Luc Verhaegen <libv@skynet.be>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4399d3c8322d5aaac044c402cddf0f68acae92c4
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Apr 20 12:34:30 2009 +0000

    flashrom: Trivial README change Flashrom->flashrom
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dbda3a9919a21ccdf5b9bbf6562598f5edbc11e4
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Apr 20 12:02:25 2009 +0000

    Fix implicit declarations of done_cache_as_ram_main by adding a
    prototype for these assembler functions.
    Affected boards:
    digitallogic/msm800sev
    pcengines/alix1c
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f5f0c69628a23171079445aeb21ee39b7d1a4d92
Author: Stephan Guilloux <stephan.guilloux@free.fr>
Date:   Sun Apr 19 23:24:26 2009 +0000

    flashrom: MX25L1605 and 1635 accept Chip Erase opcodes 60 and C7
    
    Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 15bbfb84180484432c51b7c879bf525bd0e43211
Author: Stephan Guilloux <stephan.guilloux@free.fr>
Date:   Sun Apr 19 23:04:00 2009 +0000

    Add MX25L1635D support, as discussed on #coreboot.
    
    Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5843ffcb0b784d5e3d34e6007d102fe8afe6a44
Author: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Date:   Sat Apr 18 23:04:28 2009 +0000

    There is a typo in amdk8/raminit_f.c regarding the preprocessor symbol QRANK_DIMM_SUPPORT in line 2208, which caused the protected code fragment never to be included for compilation.
    
    Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4365659fdaaee89ac761df8a3be9dddec74d9982
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 18 18:10:38 2009 +0000

    drop the ChangeLog.cvsimport document from the transition from CVS
    to GNU arch. Does anyone remember that? What a fun!
    All history is in the SVN repository, including the CVS and TLA parts,
    so nothing is lost.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c90bb4a1d93546ff1985855f3cec277b09bfe937
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Apr 18 17:22:11 2009 +0000

    Drop long-obsolete HOWTO, it's still available in wikified form at
    http://www.coreboot.org/VIA_EPIA-M.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d2a5a5abef29e61b261a4e37fb68239074c10bcf
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Apr 18 14:18:20 2009 +0000

    s/LinuxBIOS/coreboot/.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1458228b2ee33a93d2c850dd1d0633c2b18283e5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Apr 18 14:02:00 2009 +0000

    Add support for the ASUS P2B-D mainboard.
    
    This is a pretty standard "yet another 440BX" target, so the code
    is pretty straight-forward. It's a dual-CPU machine, which might need
    some fixing, I'm booting with 'maxcpus=0' for now. It does boot
    successfully up to a Linux login prompt, though.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b1ec2ac62d6b13ff8c09ad3fcc829cd7fff9b6ed
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Apr 17 23:01:45 2009 +0000

    flashrom: Add VIA PC3500G board. It has SPI flash behind ITE8716 on LPC.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: illdred <illdred@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d1be3ba633c141ab79bc3316b4b910227cb01eba
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Apr 17 17:58:34 2009 +0000

    Add include to config.g
    
    Usage:
    
    include path
    
    path can be relative to the current directory or absolute starting at /src.
    
    I tested it with:
    
    include /config/absolute.lb
    include relative.lb
    
    in /src/northbridge/amd/amdk8/Config.lb
    which included
       /src/northbridge/amd/amdk8/relatvie.lb
       /src/config/absolute.lb
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0346c22de6be5f65ca8a33f02a30b19558c57108
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 17 17:11:39 2009 +0000

    Improvements for the coreboot v2 README:
    
     - Point to the 'Payloads' wiki page for more info.
    
     - Document (most of) the build requirements of v2.
    
     - Point to the wiki for build instructions (wiki needs more docs, though).
    
     - Mention QEMU for testing coreboot, also point to wiki page.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef5f8a73b42c61e376fbe9e9bab2116cf6153a4a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Apr 17 16:18:02 2009 +0000

    Updating documentation as I get ready to put v3-style startup in (which
    I have working in an early version in my tree).
    
    Corrections welcome.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1eb1a61e070f5cb5ab64eda84e602f982a09bf28
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Apr 17 16:11:24 2009 +0000

    There are two identical cfgfile rules in config.g.  Remove one of them.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a80a61049b4851fa559ed1562f64e6ef93f6aa55
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Apr 17 13:43:46 2009 +0000

    This patch allows you to add lines of the form
    
    pci_rom PATH vendor_id = # device_id = #
    
    to Config.lb files.  No more changing the ROM_SIZE to add an option ROM, and no more manual prepending.
    
    Examples:
    
    pci_rom ../ragexl.rom vendor_id = 0x1002 device_id = 0x4752
    pci_rom ../nic.rom vendor_id = 0x1100 device_id = 0x4152
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aeba92ab5b0afd1464d6b1a275b5f5b00b351b32
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 17 08:37:18 2009 +0000

    Add VIA CX700 support, plus VIA vt8454c reference board support.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 56c51bd120a935e64cfd96d8ad71c9d1f7aab323
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Apr 17 02:40:20 2009 +0000

    This needed to be removed.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e4be46b4c39305e4224595f2655c2c9a439bc57c
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Thu Apr 16 21:09:56 2009 +0000

    Following patch flushes the instruction queue when we set PE=0. This is normally
    done by FAR JMP, but here it is more tricky because we run at EIP>1MB. Many
    thanks to Marc and Kevin to tell me how to fix it
    
    The trick is to use 0x66 prefix (done with ljmpl) it will allow to jump in real
    mode to any EIP addresses  ;)
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9fab37ecb9b900550a904d95c9962f0ba65358f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Apr 16 16:42:05 2009 +0000

    I deleted mptable.c in my patch, but forgot to svn rm it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 13e19216ef9c489888ab05906c7dabca5ceafc12
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Apr 15 21:40:08 2009 +0000

    v2/src romfs->cbfs rename
    
    romfs.c has been replaced by cbfs.c.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 472f3ffcf8eeda12d1a07c6bb8135ec16be30cf8
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Apr 15 21:25:21 2009 +0000

    This patch cleans up mpspec.h and allows it to be included when
    HAVE_MP_TABLE=0
    
    It also removes the artifacts from the Asus m2v-mx_se that were
    necessary before the change.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e006407ec347a79b60949b03a2badccf923bb06
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Apr 15 16:07:27 2009 +0000

    Add -r|--remove option to force abuild to remove the output directory
    after every board build, in order to save disk space if you don't need
    the actual output files.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d086e5d966da9e2a3d0dfb7d4e388e271ff2d51d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Apr 15 10:52:49 2009 +0000

    Some coding style and consistency fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 82144571adb315197ded9d6f3ada29a86637117c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 15 06:00:01 2009 +0000

    r4097 broke the tree and it remains unfixed :-(
    Repeat: Cosmetic patches shall not break the tree for 20 revisions.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57f6c08837380e60153bceab75e042d535746daa
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Apr 14 20:51:41 2009 +0000

    EPIA-CN does not have any ACPI tables. Fixes manual and auto build here.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45ae92ff1ac863b798e20f5fdffbd53eda02d316
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Apr 14 19:48:32 2009 +0000

    util/cbfstool/tools/rom-mk*->cbfs-mk* rename
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 483b7bbd7703ebe100ea7b10393e18712bbafc95
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Apr 14 07:40:01 2009 +0000

    v2/src romfs->cbfs rename
    
    This also has the config tool changes in v2/util.
    
    Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3935b19d9fb46ef8b57a1f2817d20113aa867920
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 14 06:38:15 2009 +0000

    fix up the tree.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef4d7d4a67406af81754d38d3773392ba04627a0
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Apr 14 00:26:24 2009 +0000

    util: romfs->cbfs rename
    
    I noticed this before sed, but forgot to change it back after sed.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d862ded11d4a2ca42d3d0aff4ea947dd28bcb68
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Apr 14 00:08:34 2009 +0000

    v2/util: romfs -> cbfs rename
    
    It's all sed here. romfs->cbfs, ROMFS->CBFS, romtool->cbfstool
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 450b23fb2ea2f08bd2e1343e0ce34ea72f19c4a9
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Apr 14 00:01:34 2009 +0000

    v2/documentation: romfs -> cbfs rename
    
    This is svn mv romfs.txt cbfs.txt and sed romfs->cbfs, ROMFS->CBFS along with
    one manual change: CBFS_file->cbfs_file
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 299a00feb8792fa67d7f1a794ae24b060b7bd76e
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Apr 13 21:42:49 2009 +0000

    Fix the build. This error was introduced by change in acpi.c, the acpi_slp_type exists only conditionally.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c4f8392e0022f30eed571224e342670c925338a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Apr 13 21:35:49 2009 +0000

    Fix typo. Add missing copyright year.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c824b5844f2d36b799887e68b4b5461b87f36fb0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Apr 13 21:19:58 2009 +0000

    Emergency fix. Most targets now build.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 743b635ca3c89b78876095c7f61869104f9ab1b0
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Apr 13 20:07:26 2009 +0000

    I need to do uses HAVE_ACPI_RESUME for each board. Here we go.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    It should fix the build break introduced in r4101
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0fb21c4af989ca8fd813163a8cb7b3218166d1a9
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Apr 13 18:44:06 2009 +0000

    The wake_vec must be HAVE_ACPI_RESUME guarded because PPC uses -Werror on this file.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Self ack, trivial fix:
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6bb6e03912c74ad9991c524de7fe7a5ff22aec32
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Apr 13 18:37:17 2009 +0000

    Following patch adds support for the ACPI resume on Asus M2V-MX SE. The ACPI
    code just blinks the leds. The motherboard resources are use to reserve coreboot
    used memory.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 15bf50d8203af20b3079e6691bf0d9eee66ea1bd
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Apr 13 18:34:35 2009 +0000

    Following patch adds resume (exit from self refresh) support for AMD K8 revF
    CPUs. It handles both type of erratas on those CPUs.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 33cafe5bfb440d150e36872d091037fa0785863d
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Apr 13 18:07:02 2009 +0000

    Following patch implements ACPI resume support for coreboot. The hardware main
    hook will come in separate patch perhaps.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 497c8effceb9510ca89561a8fcc87cbc0acb8b08
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Apr 13 18:00:09 2009 +0000

    Following patch adds support for resume on VT8237 based motherboards. The NB
    part of this patch adds support for resume well NVRAM. In which DQS values are
    stored.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a572f83e7198eff99728335e697e9a0ef1e53a0c
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Apr 13 17:57:44 2009 +0000

    Following patch adds necessary hooks and as well the compile time checks for
    ACPI suspend/resume.
    
    The memory cleared now is just the coreboot memory not the low memory.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f04dade0548e68c549af7a551f6c254b4e0088f
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Apr 13 16:21:16 2009 +0000

    Fix the following errors:
    
    In file included from
    src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:93:
    src/northbridge/amd/amdk8/raminit.c: In function ‘sdram_set_spd_registers’:
    src/northbridge/amd/amdk8/raminit.c:2123: error: implicit declaration of
    function ‘activate_spd_rom’
    
    In file included from
    src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:101:
    src/cpu/amd/model_fxx/init_cpus.c: In function ‘init_cpus’:
    src/cpu/amd/model_fxx/init_cpus.c:319: error: implicit declaration of
    function ‘soft_reset’
    
    In file included from
    src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c:98:
    src/northbridge/amd/amdk8/raminit_f.c: In function ‘sdram_set_spd_registers’:
    src/northbridge/amd/amdk8/raminit_f.c:2848: error: implicit declaration of
    function ‘activate_spd_rom’
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6dcbe7f5401bca80c738bd2f888ff13f4d59064f
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sun Apr 12 21:47:09 2009 +0000

    This patch cleans up the calls to $CC in mainboard Config.lb files. They
    now all have the same parameter order.
    
    action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS)
    -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S
    $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -o $@"
    
    The idea behind this parameter order is:
    - *FLAGS at the beginning.
    - Use a common set of *FLAGS.
    - Include files and directories listed afterwards.
    - nostdinc, nostdlib, no-builtin tell the compiler this is standalone
      code.
    - Warnings. They do not influence source or compilation.
    - Compilation strategy (small) and output mode (asm or binary).
    - File to be compiled.
    - Output name.
    - $(DEBUG_CFLAGS) and -S are only used for asm output.
    
    
    Other changes in this patch:
    
    - src/supermicro/h8dme/Config.lb now uses $DEBUG_CFLAGS instead of
    hardcoding the respective flags.
    
    - $DEBUG_CFLAGS was added to asm outputting $CC calls:
    supermicro/h8dme/Config.lb
    lippert/roadrunner-lx/Config.lb
    
    - $DISTRO_CFLAGS was added to some $CC calls in:
    iwill/dk8_htx/Config.lb (CAR AP code)
    supermicro/h8dmr/Config.lb (CAR AP code)
    supermicro/h8dme/Config.lb (CAR AP code)
    gigabyte/m57sli/Config.lb (CAR AP code)
    gigabyte/ga_2761gxdk/Config.lb (CAR AP code)
    amd/serengeti_cheetah_fam10/Config.lb (everywhere)
    msi/ms7135/Config.lb (everywhere)
    nvidia/l1_2pvv/Config.lb (CAR AP code)
    -$CFLAGS was added to all $CC calls in:
    amd/db800/Config.lb
    amd/dbm690t/Config.lb
    amd/norwich/Config.lb
    amd/pistachio/Config.lb
    amd/serengeti_cheetah/Config.lb
    amd/serengeti_cheetah_fam10/Config.lb
    arima/hdama/Config.lb
    artecgroup/dbe61/Config.lb
    asus/a8n_e/Config.lb
    asus/a8v-e_se/Config.lb
    asus/m2v-mx_se/Config.lb
    broadcom/blast/Config.lb
    digitallogic/msm800sev/Config.lb
    gigabyte/ga_2761gxdk/Config.lb
    gigabyte/m57sli/Config.lb
    ibm/e325/Config.lb
    ibm/e326/Config.lb
    iei/pcisa-lx-800-r10/Config.lb
    iwill/dk8_htx/Config.lb
    iwill/dk8s2/Config.lb
    iwill/dk8x/Config.lb
    kontron/986lcd-m/Config.lb
    lippert/roadrunner-lx/Config.lb
    lippert/spacerunner-lx/Config.lb
    msi/ms7135/Config.lb
    msi/ms7260/Config.lb
    msi/ms9185/Config.lb
    msi/ms9282/Config.lb
    newisys/khepri/Config.lb
    nvidia/l1_2pvv/Config.lb
    pcengines/alix1c/Config.lb
    sunw/ultra40/Config.lb
    supermicro/h8dme/Config.lb
    supermicro/h8dmr/Config.lb
    technexion/tim8690/Config.lb
    tyan/s2735/Config.lb
    tyan/s2850/Config.lb
    tyan/s2875/Config.lb
    tyan/s2880/Config.lb
    tyan/s2881/Config.lb
    tyan/s2882/Config.lb
    tyan/s2885/Config.lb
    tyan/s2891/Config.lb
    tyan/s2892/Config.lb
    tyan/s2895/Config.lb
    tyan/s2912/Config.lb
    tyan/s2912_fam10/Config.lb
    tyan/s4880/Config.lb
    tyan/s4882/Config.lb
    
    - Use $@ wherever appropriate.
    
    - Kill that evil CACHE_AS_RAM_AUTO_C variable.
    
    - Trailing whitespace fixups on lines which were touched anyway.
    
    We now only have 6 remaining different calls to $CC whereas before there
    were 20.
    If I am allowed to rename src/mainboard/kontron/986lcd-m/auto.c to
    src/mainboard/kontron/986lcd-m/cache_as_ram_auto.c, we're down to 4
    different calls.
    If we can decide on the use of $CPU_OPT, we are down to 3 different
    calls.
    
    One additional point I'd like to clear up:
    if ASSEMBLER_DEBUG
    makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm
    end
    
    "-dA -fverbose-asm" is only useful for asm output. For these flags,
    DEBUG_CFLAGS is a total misnomer. What about calling them
    DEBUG_ASMCFLAGS or somesuch?
    "-g" should be controllable by a separate switch. It is useful even for
    object code.
    
    
    The following targets are broken by this patch because they contain
    implicit declarations, but the error did not trigger due to missing
    CFLAGS:
    amd/serengeti_cheetah
    asus/a8v-e_se
    asus/m2v-mx_se
    digitallogic/msm800sev
    pcengines/alix1c
    supermicro/h8dme
    supermicro/h8dmr
    
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e86c65b62e4dff095512058fe300814c424ceb6f
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Apr 12 18:01:55 2009 +0000

    The IT8712F needs to have the configuration bits changed to handle the power for
    memory correctly during suspend.s
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7845fb59a2890b7cc9d724aa0f29c463154edbde
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sat Apr 11 18:58:17 2009 +0000

    Bring S2912 and S2912_Fam10 Config.lb in line with each other.
    
    - Use $(CACHE_AS_RAM_AUTO_C) instead of cache_as_ram_auto.c
    - Compile apc_auto.c with $(DISTRO_CFLAGS)
    - Clean up whitespace
    
    If anyone can explain the remaining differences in Config.lb which are
    NOT caused by the K8/Fam10 switch, I'd be glad to hear them.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3ec56c17a3a8853132d621ee533db2834544a3e
Author: Ward Vandewege <ward@gnu.org>
Date:   Sat Apr 11 18:09:03 2009 +0000

    This patch fixes an edge case for K8 raminit. Specifically, it brings the code
    in line with the K10 code.
    
    I was trying to use DDR2 800 (CL6) memory on an m57sli, but booting failed.
    Marc Jones found this bug (thanks!), which fixes booting with this specific
    memory. For the record, it was Crucial CT2KIT25664AA800.
    
    I put the machine through a few days of use. It also succesfully passed a run
    of http://people.redhat.com/dledford/memtest.shtml:
    
      $ ./memtest
      TEST_DIR:               /tmp
      SOURCE_FILE:            linux-2.6.29.1.tar.bz2
      NR_PASSES:              20
      MEGS_PER_COPY:          270
      NR_COPIES:              45
      PARALLEL:               no
      COMPRESS_RATIO:         5
      COMPRESS_FLAG:          j
      COMPRESS_PROG:          /bin/bzip2
      EXTRACT:                yes
    
      Creating comparison source...done.
      Starting test pass #1: unpacking, comparing, removing, done.
      Starting test pass #2: unpacking, comparing, removing, done.
      Starting test pass #3: unpacking, comparing, removing, done.
      Starting test pass #4: unpacking, comparing, removing, done.
      Starting test pass #5: unpacking, comparing, removing, done.
      Starting test pass #6: unpacking, comparing, removing, done.
      Starting test pass #7: unpacking, comparing, removing, done.
      Starting test pass #8: unpacking, comparing, removing, done.
      Starting test pass #9: unpacking, comparing, removing, done.
      Starting test pass #10: unpacking, comparing, removing, done.
      Starting test pass #11: unpacking, comparing, removing, done.
      Starting test pass #12: unpacking, comparing, removing, done.
      Starting test pass #13: unpacking, comparing, removing, done.
      Starting test pass #14: unpacking, comparing, removing, done.
      Starting test pass #15: unpacking, comparing, removing, done.
      Starting test pass #16: unpacking, comparing, removing, done.
      Starting test pass #17: unpacking, comparing, removing, done.
      Starting test pass #18: unpacking, comparing, removing, done.
      Starting test pass #19: unpacking, comparing, removing, done.
      Starting test pass #20: unpacking, comparing, removing, done.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebdc7c7cfebc14d503ab383e1493aa9fd10bd7e8
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sat Apr 11 14:51:49 2009 +0000

    Kill remaining unneeded CAR/ROMCC if-blocks.
    
    Lots of Config.lb files still have "if USE_DCACHE_RAM" sections although
    USE_DCACHE_RAM is always set for them. Such checks are not only
    pointless, they actively make the files hard to read.
    
    A full abuild run confirmed that compilation did not change with this
    patch applied.
    
    The patch does not change whitespace of the remaining code to ease
    review and svn blame.
    
    With this change, it should be possible to have two or three Config.lb
    variants in total (except the actual hardware config). Right now, some
    Config.lb have comments, some don't, some have empty lines for better
    readability, some don't, some have leading whitespace, some don't. This
    is an utter mess and unifying these files would certainly reduce the
    headaches I have when looking at them.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4eb37059cea9ad4fae2f959dc023f6537f722717
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Apr 11 13:59:00 2009 +0000

    Mention a few more flash chip packages in README/manpage.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1da9a79a069a85c05314ca33b53f6c1b0d98d733
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 10 23:02:48 2009 +0000

    move architecture override before cross compiler detection, or the Sandpoint
    skeleton will have get a cross compiler before it gets the architecture set
    to SKIP. Pretty much build system internal, so self-acked.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 708ccac6ee466a4884348771ee54a4f38c8c1535
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 10 21:05:56 2009 +0000

    Add a note that 'modprobe msr' might be required.
    Remove trailing whitespace. Fix typos.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd2cbf7200f7183b9af300b00a222b2bb06b4b3d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 10 14:49:14 2009 +0000

    Fix typo.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a0eeef324fed3f4de11a5896983a4e7ae78e79fe
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 10 14:41:29 2009 +0000

    Various manpage / README fixes:
    
     - Improve description a bit, especially wrt chip packages and
       protocols.
    
     - Add some missing parameters to manpage option descriptions.
    
     - Remove long obsolete DoC support note.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d9f932f2a51ee0daea136d0814f163849f5bee1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 10 12:27:42 2009 +0000

    unify spd_ddr2.h (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 712f325237ce29ea9d0a2cf7c0955bf6199d0803
Author: Mondrian nuessle <nuessle@uni-hd.de>
Date:   Thu Apr 9 14:28:36 2009 +0000

    Fixed the typo should indeed be a 0x2e.
    Tested on an iWILL DK8-HTX board.
    
    Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 013c7cfab5fe5b6a54e0cd8614fc60d9f328b85b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 8 07:47:01 2009 +0000

    * commit previously forgotten romfs.txt
    * fix a copy & paste error in src/lib/romfs.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d36703799772f0ffd00df76b4f549c932c1eeb53
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 8 07:21:52 2009 +0000

    fix sandpointx3_altimus_mpc7410 target. We're back at all boards compiling.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d40f7db2d92c9f5421fbd80b8a479524284e781e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 8 06:41:06 2009 +0000

    Only build romfs on those target that have CONFIG_ROMFS enabled.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0de8b9111aec7ee5f625ab9c5e3f813d7929bc71
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 7 15:38:17 2009 +0000

    This tested ok, but qemu can't really handle c0000 as RAM.
    (trivial)
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 80775c1425b613047f16dd84481e96d588f85524
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 7 14:27:38 2009 +0000

    add Config-abuild for the new board (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a8523a788fb1c80a2f65a5d65fa36db85398397
Author: Ronald G. Minnich rminnich <Ronald G. Minnich rminnich@gmail.com>
Date:   Tue Apr 7 02:18:13 2009 +0000

    This is a bit of an emergency fix for qemu. Ethernet routing has not been
    working. Given all the limitations of PIRQ routing we keep it simple
    and just set the IRQ directly. Most BIOSes are doing setup this way anyways,
    since there are so many errors in PIRQ tables.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b3b7db777df142e98827c61b528c0daf3877488b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Apr 6 23:28:22 2009 +0000

    This fixes a bug in romfs code; see comment. If we add the pci rom
    to romfs for qemu,we get this:
    Check pci1013,00b8.rom
    found it, @ fff99698, first word is e946aa55
    In cbfs, rom address for PCI: 00:02.0 = 0
    On mainboard, rom address for PCI: 00:02.0 = fff99698
    copying VGA ROM Image from fff99698 to 0xc0000, 0x8c00 bytes
    
    This is sort of OK, excpet that when it gets to payload time, the
    system explodes. I suspect that copy is kind of a problem.
    
    But this is a pretty important bug fix so in it goes.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 308312ce6c1508eb1d79cd1287fedc26bd34f2b5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Apr 6 20:38:34 2009 +0000

    Some changes for option roms:
    - don't make users pick the name. Names for option roms are in the v3-defined
    format of pci%04x,%04x.rom with the vendor and device id filling in the
    %04x.
    - users pass in vendor and device id.
    - users pass in a dest. If the dest is 0, the address of the ROM image in
    FLASH is returned. If the address is non-zero, then the decmpressor is called,
    and it will make sure the ROM image is copied to the destination (even
    in the uncompressed case).
    
    move qemu over to always using ROMFS
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 662d52d24426b8fb8d11d455f8b30ae67a669ade
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Apr 6 16:03:53 2009 +0000

    Add support for romfs to option rom loading.
    
    Pretty simple: Find the rom in the romfs, if found, set dev properties so
    that the rest of the code works.
    
    At some point, we can remove some of the other code, i.e. the first else,
    and stop requiring people to do math.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df77f345e734e3a16548126ed0542615b6144ab6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Apr 6 14:00:53 2009 +0000

    (trivial) fix some warnings
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da6d92ba11ced79f0e4c6c409d37d6e36d73fd91
Author: Daniel Toussaint <daniel@dmhome.net>
Date:   Mon Apr 6 13:38:54 2009 +0000

    Daniel Toussaint wrote:
    
    As I mentioned a few weeks ago, I am in the process of porting this board:
    
    http://www.technexion.com/products/embedded_boards/tim-8690-mt.html
    
    This board has a dual BIOS , choosable with a jumper - much like the BIOS
    savier from before - so it is a pleasure to work with as a linuxbios developer.
    
    It is still a work in progress, however , I already submit the patch.
    All on board devices and slots work as expected, only need some more stress
    testing with the RAM, acpi, etc..
    
    Signed-off-by: Daniel Toussaint <daniel@dmhome.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 38891ab7e62c539a98f435c553481a85c7a8ae1e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 5 08:43:44 2009 +0000

    cross compilation fix for motorola sandpoint based boards
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85107f28dada03088d301015ba3254dd4fd78163
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Apr 5 08:39:13 2009 +0000

    two more totalimpact briq fixes. Gets us back to the romfs breakage on PPC
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a73fc4b6c57c9aaed1673732d8fa44ee9b911cbf
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 4 22:55:49 2009 +0000

    Makefile includes were mixed up.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9f243a11326724221732900b2fb37ebd2ce7b1dd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 4 22:27:10 2009 +0000

    fix this warning:
    coreboot-v2-4067//src/stream/ide_stream.c: In function 'stream_ide_read':
    coreboot-v2-4067//src/stream/ide_stream.c:47: warning: declaration of 'offset' shadows a global declaration
    coreboot-v2-4067//src/stream/ide_stream.c:13: warning: shadowed declaration is here
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd0b6ff4dd7886405a3af5f8481cd65a016226eb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 4 22:24:23 2009 +0000

    fix this warning for the embedded planet ep405pc
    
    /tmp/ccilLWBf.s: Assembler messages:
    /tmp/ccilLWBf.s:144: Warning: setting incorrect section attributes for .rodata.pci_driver
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14ad50edf6aeeff019cb3f446a8677c6eb98756c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 4 22:18:26 2009 +0000

    This fixes a race condition (revealed by my other check-in r4067) in the
    romtool by changing the Makefiles to be no longer recursive (once again,
    recursive make is to be considered harmful).  Tried to (quickly) unify most of
    the Makefile code, but medium-term this is going to be worked on for Kconfig
    support anyways.
    
    Also fix a sign cast error in rom-mkpayload in case people want to compile this
    with -W -Werror
    
    Patch relative to coreboot-v2/util/romtool
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    and
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    in order to get the tree working decently asap
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 16e34b98a1f7acb3a37579388df585fbc0fa10e5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 4 18:40:46 2009 +0000

    small workaround for romtool incompatibility with ppc ports
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e6cc67b07a8cf25a3b439febcdfdce37e64297ab
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 4 18:24:21 2009 +0000

    build romtool in mainboard target directory.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e304e66165bc98c9e226e38623741212dbd4aa8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 4 18:16:11 2009 +0000

    fix cross compilation in abuild for certain scenarios
    (coreboot.org build system internal)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e244da7a5dbfca8ff7002a052dec931b380c86b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 4 13:28:40 2009 +0000

    fix variable shadowing in lzmadecode.c (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be84b01e186697a0f03e8e6229baf9aba8563efe
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 4 13:20:33 2009 +0000

    fix some warnings by casting safely. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 962242ad2d33fd81a87067dadb58652d88edaf52
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 4 13:05:18 2009 +0000

    use $(MAKE) instead of hardcoded "make".. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ddacb60d442a725983166eadc94d10e65fb2022
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 4 12:52:28 2009 +0000

    fix configuration step of totalimpact briq and embeddedplanet ep405pc.
    (trivial).
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d2589e682a7c3a12d330f0b849bd2ace392c828
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sat Apr 4 10:01:21 2009 +0000

    Fix the concurrency issue of building romtool.
    romtool is still built in util/romtool, as happens without this patch.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d7a709a60fa8b7fa948a2f1996383bf3bde105ad
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Apr 3 22:23:34 2009 +0000

    These are some cleanups and changes. These are build and boot tested on qemu.
    Some changes for option roms:
    - don't make users pick the name. Names for option roms are in the v3-defined
    format of pci%04x,%04x.rom with the vendor and device id filling in the
    %04x.
    - users pass in vendor and device id.
    - users pass in a dest. If the dest is 0, the address of the ROM image in
    FLASH is returned. If the address is non-zero, then the decmpressor is called,
    and it will make sure the ROM image is copied to the destination (even
    in the uncompressed case).
    
    And some type and print cleanup.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ace2dc59627a733d43ba00342745e30ac95768d3
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 3 20:14:59 2009 +0000

    Add u64 typedef to ppc (trivial)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b6ea25f2194bccb7680ed0bf05923ee504e1688
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Apr 3 16:40:44 2009 +0000

    Fix up the incomplete commit in r4055.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit edf480719a69912c39f4a1d31f50898eb3982c5b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 3 16:33:50 2009 +0000

    drop unused variables in generic smm handler. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2fd2c7901ebca153afdbba5797606cb03ca6748b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 3 16:31:01 2009 +0000

    drop another shadow variable (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7116c3bd08e27fba8f1fb1ea25cfb8c4b592c67
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Apr 3 16:29:35 2009 +0000

    There are more than a dozen targets in the v2 tree which refer to ROMCC
    in their Config.lb but never use it. There's no point in keeping
    dead code around.
    
    This patch removes ROMCC remainders from Config.lb and kills orphaned
    auto.c and failover.c in the affected mainboard directories.
    
    arima/hdama
    ibm/e325
    ibm/e326
    iwill/dk8s2
    iwill/dk8x
    msi/ms9282
    newisys/khepri
    sunw/ultra40
    tyan/s2891
    tyan/s2892
    tyan/s2895
    tyan/s4880
    tyan/s4882
    
    Abuild log is completely identical with and without the patch.
    
    With this patch, the last ROMCC remainders for K8 boards are gone.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f16fb73087e0810e8fa03a8feb665ad6f7066da4
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 3 16:17:05 2009 +0000

    I thought that romfs infrastructure is done now, but there were some
    issues (see buildbot).
    The romfs image was always built, and sometimes broke (because of
    the different image layouts) for buildrom images. After the patch, these
    issues are avoided by not adding payloads to the romfs image (they
    wouldn't be read anyway). Both workarounds (in buildrom code for
    romfs and vice-versa) aren't very pretty, but that's what our buildsystem
    requires.
    As I had to create a "communication channel" (via the romfs-support
    files), I took the chance to also use it for compression
    information, so if you configure lzma support, you'll get lzma
    compressed payloads in romfs.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d107831182ebbf485590c32946ee375b3233b24a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 3 15:57:58 2009 +0000

    The attached patch tries new style compression first and runs old
    style compression if the command returned an error code (happens if
    you run an old lzma with the new arguments)
    
    Tested on new-style lzma only (as I lack a build environment with
    old lzma), but I tested that the old lzma returns with an error code.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48e8c3c36dc128969da26610d67d30c93155da5a
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 3 15:02:08 2009 +0000

    Print a pointer as pointer, it's really trivial.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b9a5c636e1bd42556fe6124229d75f3f16990f6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 3 14:04:06 2009 +0000

    This patch implements --include=file.h for romcc.
    
    The compile_file calls seem to be in the wrong order, but
    romcc actually requires it that (probably some stack-like
    file processing)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 11f054a5785af6a1c29eebbe1b91f3570dca6228
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Apr 3 12:55:55 2009 +0000

    Next step. Kill auto.c and failover.c and clean up Config.lb for
    tyan/s2735
    tyan/s2850
    tyan/s2875
    tyan/s2880
    tyan/s2881
    tyan/s2882
    tyan/s2885
    tyan/s2891
    tyan/s2892
    tyan/s2895
    
    Abuild log is completely identical with and without the patch.
    
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aed1f925a65a231ed008902f1946b3680227f098
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Fri Apr 3 12:52:43 2009 +0000

    the attached patch is the last infrastructure change necessary for
    romfs.
    Everything else to make a target romfs aware happens in the targets.
    
    What the patch does:
    1. missing romfs.h include
    2. special handling while creating coreboot.rom
    While the romfs code path in the makefile doesn't actually use the file,
    it's possible that the build of coreboot.rom fails in a romfs setup,
    because the individual buildrom image is too small to host both coreboot
    and payloads (as the payloads aren't supposed to be there). Thus, a
    special case to replace the payload with /dev/null in case of a romfs
    build.
    There would be cleaner ways, but they're not easily encoded in the
    Config.lb format.
    3. config.g is changed to create rules for a romfs build
    
    Targets should still build (they do for me)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 73ad3264525c7d076ef2aafab63841685bf53679
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Apr 3 02:18:23 2009 +0000

    There are more than a dozen targets in the v2 tree which refer to ROMCC
    in their Config.lb but never use it. There's no point in keeping dead
    code around. Kill it.
    
    This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
    tyan/s2850.
    
    Abuild build log with and without the patch is completely identical.
    
    More patches of the same type can be done, hopefully making
    ROMCC dependencies a bit more clear for v2.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e729846b64eed59e72080766d09036ebbe9760a7
Author: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Date:   Thu Apr 2 23:08:16 2009 +0000

    Ronald Hoogenboom writes:
    I've attached a patch that removes the 3-mile-long compiler
    commandlines, which vim's quickfix doesn't like so much. Instead of
    putting all those -DXYZ='bla' on the compiler commandline, they are put
    in a file called settings.h (as #define XYZ bla) and only a
    --include=settings.h is put on the commandline.
    This file is created unconditionally at the same time as when the
    CPUFLAGS simply expanded make variable used to be created (not via a
    target rule and dependency), so it shouldn't change anything.
    
    Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5cbdc1ee6f37a45c3cda62a797e81572001dc7b7
Author: Marc Jones <marcj303@gmail.com>
Date:   Wed Apr 1 22:07:53 2009 +0000

    Fix typo.
    trivial.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4ca5902b143bb087371641717362a21fd20c38cb
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Wed Apr 1 16:22:38 2009 +0000

    Updated microcode for for AMD Fam10 DR-B2 and B3.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90e0271b13fb613affcabdd37eda0a088f47f9ee
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Apr 1 16:06:33 2009 +0000

    forgot this.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61dc06c0601a32e5aebd5637e67af8b3697cfc3f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 1 13:54:16 2009 +0000

    (trivial) add filo call back for those few mainboards that still (need to)
    use the built-in filo.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3081bdfa44b89c2fa34eee902c13e0d1d618bff3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 1 13:43:21 2009 +0000

    Drop CONFIG_CHIP_NAME. Those config statements in Config.lb should
    be used unconditionally, and the names don't hurt.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 77cf00850f457e799f7b05ee9c98fb6b990b2514
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Apr 1 11:37:39 2009 +0000

    Forgot CONFIG_ROMFS for supermicro/h8dme.
    Trivial fix, just add the defaults as with all other boards.
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7798895d30fb3f2f915865dd5755e6df922bc2d
Author: ebiederm <ebiederm@xmission.com (Eric W. Biederman)>
Date:   Wed Apr 1 11:03:32 2009 +0000

    Add copyright notices to two files, src/boot/elfboot.c
    and its derivative src/boot/selfboot.c.
    
    The mail in which Eric asserts authorship on elfboot.c is
    quoted below, selfboot.c was substantially edited by Ron.
    With that information in mind the change is trivial.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    From: ebiederm@xmission.com (Eric W. Biederman)
    Date: Wed, 01 Apr 2009 03:31:15 -0700
    To: Patrick Georgi <patrick@georgi-clan.de>
    
    Patrick Georgi <patrick@georgi-clan.de> writes:
    
    > Hi,
    >
    > We found some file in the coreboot tree that we suspect is yours.
    > Unfortunately,
    > both copyright notice and license are missing.
    > Could you please take a look at it, and state whether it's yours,
    > and if so,
    > what license is to be attached?
    
    Yes. GPLv2
    
    > The file in question is
    > http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/boot/elfboot.c
    > and its history goes back to
    > http://tracker.coreboot.org/trac/coreboot/log/trunk/LinuxBIOSv2/src/boot/elfboot.c?rev=2890
    
    
    Eric
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae63126346744e20264934f01d7b4653bc366a30
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Apr 1 10:48:39 2009 +0000

    This code adds support for coreboot images that use ROMFS.
    
    It also removes the call to FILO from hardwaremain -- that
    has needed removal for a long time.
    
    abuild tested.
    Note that this code has been tested and works on
    both qemu and kontron. The changes to use it are coming
    next.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f834e20ba35bae7431bb68c5bf064f493fb74bad
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 31 17:17:30 2009 +0000

    fix typo
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ac369065cb9f94483f94c7be29daab87f24f2243
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 31 17:15:42 2009 +0000

    fix typo
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45dffef232d98ee98f1aeeeb1010e269fadff727
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 31 16:42:57 2009 +0000

    fix shadow variable in compute_ip_checksum.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d469cdab93ae1d60421116def8a9800da8374274
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Mar 31 16:32:01 2009 +0000

    Add the CONFIG_ROMS config variable.
    
    Tested under abuild, causes no trouble.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 420593e74dc1a287b342e9fb8746718b0e4ad007
Author: Robert Millan <rmh@aybabtu.com>
Date:   Tue Mar 31 14:11:19 2009 +0000

    This fixes a shadowed declaration in multiboot.c.
    
    Signed-off-by: Robert Millan <rmh@aybabtu.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit decdb3c647e15e3caf94d1f56ebeec3de7c47eb2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 31 14:10:42 2009 +0000

    cosmetic fix for function definition.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5d01ec0f80cc8379df17ed9a922de37b487770b4
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Mar 31 11:57:36 2009 +0000

    This patch adds Jordan's romtool support for v2.
    There are a few changes. The 20K bootblock size restriction is gone.
    
    ROMFS has been tested and works on v2 with qemu and kontron. Once this
    patch is in, those patches will follow.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f0f9bb9a2e1c1257fdfee0b50061e82ea92161b
Author: Mondrian Nuessle <nuessle@uni-hd.de>
Date:   Mon Mar 30 13:20:01 2009 +0000

    flashrom: Board enable support for HP DL145 G3.
    
    This is a BCM5785 based machine, WP# and TLB# need to be deasserted using
    GPIO 2 and 5 from the PM registers of the southbridge.
    This is very similar to the x3455 implementation.
    
    Signed-off-by: Mondrian Nuessle <nuessle@uni-hd.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a8565a77bbf8f41c2c5560fb2c195c71949fc8c
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Thu Mar 26 21:45:26 2009 +0000

    During the suspend/resume programming I came to an issue that first 4KB of
    memory must be clear with 0s because otherwise the resources of K8 will be
    totally messed up.
    
    res = probe_resource(dev, 0x100 + (reg | link));
    
    This is called with dev = NULL and this is no good for probe_resource at all.
    The attached patch fixes the potential problems and of course the problem
    itself. On one particular place was missing test if the device really exists.
    This was copied to fam10 and perhaps the same issue is in v3 (DID NOT check).
    The rest of the patch is just very paranoid and do all checkings.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    --This line, and those below, will be igno
    red--
    
    M    src/devices/pci_ops.c
    M    src/northbridge/amd/amdk8/northbridge.c
    M    src/northbridge/amd/amdfam10/northbridge.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 83da8dcf608d4b6549399581463fe484b71bca6f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Mar 25 17:38:40 2009 +0000

    - List SMSC LPC47N227 runtime register block as supported.
    
    - Add missing contributor in README.
    
    - Cosmetic fixes.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 951c63f2a5b57bfadbc48d2fca01db8686be8c02
Author: Zeng Bao <zheng.bao@amd.com>
Date:   Wed Mar 25 15:47:58 2009 +0000

    The latest ucode patches for Family 10h:
    
    9fh for RB/BL/DA Rev C;
    96h for DR Rev B.
    
    Signed-off-by: Zeng Bao <zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8e2517055d5f8164c6a4070d1e71c789071fc10
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 24 12:28:44 2009 +0000

    Every object file with a struct pci_driver ... __pci_driver needs to be marked
    as "driver" instead of "object" in order to get the init code actually
    executed.
    
    This patch fixes up all northbridges that did not do this before.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f28c09ce54c5dabd0aa4250203d2b38295a1fad
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Mar 23 17:43:12 2009 +0000

    msrtool: If an MSR name lookup fails in msraddrbyname(), return the strtoul() conversion result.
    
    Thanks to Mart for finding and reporting the problem!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b10ab3782ea30f9832efb297eb0f51eab36d20e
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Mar 21 11:52:29 2009 +0000

    To make use of HAVE_HIGH_TABLES following patch is needed. Also, it moves
    coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a
    bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9e9fa825fdd836f5e13db78ce4dc6bfb182dc35e
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Mar 21 11:50:20 2009 +0000

    To make use of HAVE_HIGH_TABLES following patch is needed. Also, it moves
    coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a
    bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2a63ea580a754f65ef8f2cf2f4682a51e6b7a9da
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Mar 20 18:29:49 2009 +0000

    Kevin O'Connor said:
      The bug is in src/arch/i386/boot/boot.c.  The inline assembly in
      jmp_to_elf_entry uses the "g" flag to pass in parameters.  However,
      "g" allows gcc to use stack relative addressing of parameters.
    
      Easiest fix would be to change "g" to "ri" - put the parameter either
      in a register or as an immediate value.
    
    That's what this patch does.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5dd4a20b96f2bb563ae724c4eaf2524529bc46d0
Author: Marc Jones <marcj303@gmail.com>
Date:   Fri Mar 20 16:36:05 2009 +0000

    Add Supermicro h8dm3 mainboard. This is mostly a copy from the h8dmr.
    The one issues is the SPD address switch for the second CPU. That means that
    the memory must be an exact match on each CPU.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f4979f347ea7014786934cccab10772f6a6402a
Author: Marc Jones <marcj303@gmail.com>
Date:   Fri Mar 20 16:03:37 2009 +0000

    Fix CPUID typo. This caused fid to memory speed calculations to be off.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5182f6759006d969cfd7cb31743c614966d1a53f
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Mar 19 12:18:13 2009 +0000

    Move the Atmel AT45 comments about block and page sizes from the end of
    the struct to the individual struct members to improve readability.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d0db8f904de367941e8b04f7b8a70ae3a1467a28
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Mar 19 01:30:16 2009 +0000

    fix the following warning on all boards that don't have PIRQ_ROUTE enabled
    
    In file included from coreboot-v2-4017//src/arch/i386/boot/pirq_routing.c:2:
    coreboot-v2-4017/src/arch/i386/include/arch/pirq_routing.h:45:5: warning: "PIRQ_ROUTE" is not defined
    coreboot-v2-4017//src/arch/i386/boot/pirq_routing.c:103:6: warning: "PIRQ_ROUTE" is not defined
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c675955f05411a78e7eec46faa5ce7ffd9bf481d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Mar 19 01:13:01 2009 +0000

    fix totalimpact briq compilation. the target had a cpu specific and a mainboard
    specific clock.c. Since no other target uses the same cpu, I commented out the
    CPU's clock.c.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1233054fbed27e65aabf370a2a4d42a050f980ec
Author: Pattrick Hueper <phueper@hueper.net>
Date:   Wed Mar 18 16:25:34 2009 +0000

    add YABEL flag to options to decide wether access to devices other than the one yabel is running for is possible
    
    Signed-off-by: Pattrick Hueper <phueper@hueper.net>
    Tested and Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f7d506ae72034af4245c4eabbe6553b5ff68bb0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 17 16:41:01 2009 +0000

    Add high coreboot table support to libpayload
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 927377febe49f9dbf2dc85283583d85beca2f367
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 17 15:33:41 2009 +0000

    Add support for high coreboot table to mkelfimage
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b743885b43cf735a54da6ac1eddcf81c84f28522
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 17 15:15:15 2009 +0000

    Don't know if this is the correct fix, but it fixes compilation of the PPC
    targets.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 764fe40f098d010d8d41a549a2560be3b0814d42
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 17 14:39:36 2009 +0000

    This patch adds "high coreboot table support" to coreboot version 2.
    
    Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
    the coreboot table integrity, rendering the table useless.
    
    By moving the table to the high tables area (if it's activated), this problem
    is fixed.
    
    In order to move the table, a 40 bytes mini coreboot table with a single sub
    table is placed at 0x500/0x530 that points to the real coreboot table. This is
    comparable to the ACPI RSDT or the MP floating table.
    
    This patch also adds "table forward" support to flashrom and nvramtool.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f72e32b06ec17768344032cf580acb60642afab
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 17 14:39:25 2009 +0000

    This patch adds "high coreboot table support" to coreboot version 2.
    
    Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
    the coreboot table integrity, rendering the table useless.
    
    By moving the table to the high tables area (if it's activated), this problem
    is fixed.
    
    In order to move the table, a 40 bytes mini coreboot table with a single sub
    table is placed at 0x500/0x530 that points to the real coreboot table. This is
    comparable to the ACPI RSDT or the MP floating table.
    
    This patch also adds "table forward" support to flashrom and nvramtool.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit efab4ba3bb3e26de55a7f2e62bbc224c0a7d6e7f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 17 14:38:48 2009 +0000

    This patch adds "high coreboot table support" to coreboot version 2.
    
    Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
    the coreboot table integrity, rendering the table useless.
    
    By moving the table to the high tables area (if it's activated), this problem
    is fixed.
    
    In order to move the table, a 40 bytes mini coreboot table with a single sub
    table is placed at 0x500/0x530 that points to the real coreboot table. This is
    comparable to the ACPI RSDT or the MP floating table.
    
    This patch also adds "table forward" support to flashrom and nvramtool.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5d6645ae4435337fd55e60f62daab2e3b372351e
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Mar 17 01:47:25 2009 +0000

    - TOM2 is filled in by the dynamic ACPI code. Don't hardcode it in the
      DSDT and use the dynamic TOM2 variable instead.
    - The DSDT needs to be revision 2 or above to handle 64 bit variables.
      This will require a recent (not older than 2007) iasl (ACPI compiler).
    - Fix an incorrect comment.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d01bd580944540bde6c833f444f55c92c2abe54
Author: stepan <stepan@coresystems.de>
Date:   Mon Mar 16 17:28:07 2009 +0000

    drop empty directory. (trivial)
    
    Signed-off-by: <stepan@coresystems.de>
    Acked-by: <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec75a57e364e237a5c2a57e2df289c65b0c305bb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 16 15:27:00 2009 +0000

    fix typo in pci_device.c (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d07c932bb5258b10ce76c48ff2a7475da19fd85
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 15 10:04:41 2009 +0000

    Fix all build problems on PPC except the _SDA_BASE issues caused by the
    code expecting too old binutils(?).
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f556be7668889d3a7fc2418ffcadbe7af99fb77
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 15 09:55:17 2009 +0000

    abuild: Don't forget CROSS_COMPILE anymore.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f110a80068fc35207e8d3b4cd9544f1c456a173
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Mar 14 16:33:22 2009 +0000

    trivial patch for abuild: allow powerpc-elf-gcc, too.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2075dbea45b0921e575c375eed597efd65bef9eb
Author: Pattrick Hueper <phueper@hueper.net>
Date:   Sat Mar 14 15:43:42 2009 +0000

    add YABEL Debug Flags to Options
    
    Signed-off-by: Pattrick Hueper <phueper@hueper.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84a1f4e26139090b31e427904263a9b8347c3a2a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 13 17:22:53 2009 +0000

    this commit should fix Ticket #122 (proper log files for all builds)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb2de6869c2f4929db37db7fc4fce0e345b1e799
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Mar 13 17:20:59 2009 +0000

    This patch reverts SuperIO changes that I was too hasty with.  Even though the
    address of the RTC is 0x70, you need to write 0x400 to it.  Now the dump from
    superiotool matches the factory except 0xf0 of the keyboard.  When you boot with
    the factory BIOS that is 0x04, but with coreboot it is not set.
    
    It's trivial because it is reverts.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 65e9bc13f0588fa12ed3229bddd3ad87990c3470
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 13 17:00:46 2009 +0000

    This one is an example on how to drop vgabios.c from the mainboard or chipset
    directories and use the global (v3) one in util/x86emu instead. It also fixes
    the breakage introduced by 4000
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be7f79867e4d989fc9cb7fb9e8b0b8ec55956875
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 13 15:42:27 2009 +0000

    This, ladies and gentlement, is commit #4000.
    
    Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few
    include files and missing prototypes. Also, fix up the Config-abuild.lb files
    to properly work for cross compiling.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc46e73a0221d08a30c78adfc568f162cdda407d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 13 00:44:09 2009 +0000

    ACPI implementation for i945, ICH7, Kontron 986LCD-M
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 47e42e5ebb8f912553cad57b4eebfccccfed511d
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Mar 12 17:42:20 2009 +0000

    Fix HIGH_TABLES introduced error when compiling without MP table
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 30140a59f7c34b583b670401a205338e0c8e3311
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 11 16:20:39 2009 +0000

    i945 northbridge update
    
    - lots of PCIe updates
    - various bug fixes to early init
    - some fixes for typos and warnings
    - initial support for PCIe x16
    - some minor fixes to memory init code
    - some subsystem vendor id patches, to be consistent with ICH7
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d229677b6191868661676658d84d7325d8f69f23
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Mar 11 15:43:02 2009 +0000

    20090310-3-scanbuild:
    Add support for clang's scan-build utility to abuild. scan-build wraps
    the compiler and runs its own compiler on the same sources to do some
    static analysis on them. It adds an option "-sb" or "--scan-build" that
    creates a coreboot-builds/$target-scanbuild directory for every $target,
    containing the output of scan-build, which is a HTML documentation on
    its results.
    Be aware, that scanbuild significantly increases build time: A board
    that takes 6-7 seconds normally requires 60 seconds with that option
    enabled on my test system.
    The patch also moves the stack-protector option down a bit, so it
    applies to crosscompiled targets, too (which overwrote the compiler
    settings before)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 118c1005ed11cab83fcb5c3b0958b72535b7866b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Mar 11 15:36:39 2009 +0000

    20090310-2-gcc-for-real:
    Create a variable "GCC", which defaults to the content of CC, but allows
    the user to provide a gcc to use in this instance, even when normally a
    different tool is chosen. That helps with scan-build (see next patch),
    and might help with distcc, ccache etc, too.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 25399346b3371bec44ba432d4c32f8f9c939f658
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Mar 11 15:35:22 2009 +0000

    20090310-1-paths:
    The rules changed in this patch originally wanted to write c_start.o
    into the source tree. That triggered a bug in my other work, and is
    generally not what we want.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e1025d0f7fabc20e271c578c7c3283b30d152fe8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 11 15:20:36 2009 +0000

    Kontron 986LCD-M updates:
    * ACPI updates: MCFG, HPET, FADT
    * some mptable fixes for certain riser cards
    * Use Channel XOR randomization
    * Fix SuperIO HWM setup
    * Enable all three network adapters
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc44b06d9d5dd11dbe8e5e17f2603db006447861
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 11 15:00:50 2009 +0000

    abuild:
    
    - add configure only mode to easily and quickly check Config.lb and Option.lb
      files
    - fix up cross compiler handling
    - don't use in-place sed, not all sed versions can do it
    - use perl instead of date to avoid non-gnu date trouble
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a8e1168064b34b46494b58480411a11bc98340f6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 11 14:54:18 2009 +0000

    This patch contains some significant updates to the i82801gx component and will
    be required for a series of later patches. Roughly it contains:
    
    * fixed SMBus driver (was not compiled in before)
    * fixed S-ATA/P-ATA combination
    * Added warnings to drivers being called with a NULL dev->chip_info
    * Set subsystem ids for those boards that have none specified in Options.lb
    * Fix license headers. The code was originally released under GPL v2 but
      some files sneaked in with a v2 or later header.
    * some attempts to fix azalia/Intel HDA.. not working yet
    * clean up and fix pci bridge handling code
    * Add Config based GPI handling to LPC driver
    * Add HPET enable function
    * Enable clock gating where appropriate
    * first attempt at USB debug console support (not working yet)
    * Add required options to kontron board
    * many other minor changes
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6df0c62b688d1c4157bc151f98a2feeeca79fee8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 11 14:48:20 2009 +0000

    Add support for the LPC47M182 to superiotool
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34b1d4ef376358661265fbdb64553332aa952e29
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Mar 10 20:56:54 2009 +0000

    This patch adds ACPI support for Tyan s2891, s2892, and s2895.  There is still
    a problem with IRQ 9, but besides that Linux is happy.  BSOD in Windows still.
    
    changes by file:
    
    src/mainboard/tyan/s289X/Options.lb:
    	Add options and defaults for ACPI tables and resources.
    
    src/mainboard/tyan/s289X/mainboard.c:
    	Add high_tables resource ala Stefan's code for the Kontron.
    
    src/mainboard/tyan/s289X/acpi_tables.c:
    	Fill out the ACPI tables, using existing code where possible.
    	Only the madt is different between the boards, to be combined later.
    
    src/mainboard/tyan/s289X/Config.lb:
    	Compile in acpi_tables.c and dsdt.dsl.
    	Turn on the parallel port and the real-time-clock.
    
    src/mainboard/tyan/s289x/dsdt.dsl:
    	The board layout (thanks Rudolf) and interrupts from mptable.c
    
    src/mainboard/tyan/s289x/mptable.c:
    	Minor formatting changes to make them diff better.
    
    src/superio/smsc/lpc47b397/superio.c:
    	Correct the size of the real-time-clock so it can be where it belongs.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 283a49452184365112c1520b0864d930dd8ab63b
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Mar 10 20:39:27 2009 +0000

    This patch adds common elements for ck804-based boards.
    
    changes by file:
    src/northbridge/amd/amdk8/northbridge.c:
    	Add high tables code ala Stefan's code for the i945.
    
    src/southbridge/nvidia/ck804/ck804_lpc.c:
    	Enable High Precision Event Timers.
    	Add pm_base for ACPI.
    
    src/southbridge/nvidia/ck804/ck804_fadt.c:
    	Since fadt is only dependent on the Southbridge, add it here.
    
    src/southbridge/nvidia/ck804/Config.lb:
    	Compile in ck804_fadt.c
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 210b83e764bf30552a996acefe50b1f400d97bff
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Mar 10 18:44:34 2009 +0000

    This patch adds empty acpi_fill_slit functions so they build again.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b4c9f08c72413f8d54640a08524f216e2a60eec
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Mar 10 18:06:47 2009 +0000

    This patch makes the boards use a single amdk8_util.asl.  There are only
    whitespace differences between this file and the amdk8_util.asl from
    asus/m2v_mxe.
    
    It also enables SLIT filling if you have one, zeroes the unused fields in the
    srat_lapic structure, and adds some declarations in acpi.h.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f210766d5cf673955ba62652570af78a0586f80
Author: Marc Jones <marcj303@gmail.com>
Date:   Sun Mar 8 04:37:39 2009 +0000

    Add some basic K8 MSRs.
    Fix bash script type.
    Removed const return type on msraddrbyname() to fix gcc warning/error.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b1a955ccef1c980ccea5af06349c0ea74a28d5a
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Mar 6 22:26:00 2009 +0000

    FreeBSD definitions of (read|write)[bwl] collide with our own. Before we
    attempt trickery, we can simply rename the accessor functions.
    
    Patch created with the help of Coccinelle.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Idwer Vollering <idwer_v@hotmail.com>
    Acked-by: Patrick Georgi <patrick@georgi-clan.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45cc550c3ab24e6c68fd0f9dd5ea2f96cf9afc38
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 6 19:54:15 2009 +0000

    Some updates for core/core duo/core2/core2 duo cpus.
    
    The microcode is from Intel's Linux microcode file, so it's unproblematic.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b387458b57f369056b0a45bf4f17e5e074c13ce
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 6 19:52:36 2009 +0000

    * fix a minor power state issue in the ich7 smm handler
    * move mainboard dependent code into a mainboard SMI handler.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43b29cf891c78a2cd01d22a2731c7da828d79e0a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 6 19:11:52 2009 +0000

    Fix mmconf (PCIe memory mapped config space access) support in v2. It was
    horribly broken and thus never used by any platform. This needs to get
    straightened out so current chipsets drivers can use the full feature set.
    
    Create wrapper functions similar to the io pci config space ones.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae762b5d3b84b2b6f8cf80195d10e9544605aa4a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 6 18:39:54 2009 +0000

    use include file for i8259 where appropriate (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1894463787300242a05f83e7cf0d24348933b571
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 6 18:38:28 2009 +0000

    clean up qemu target config (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d348f919cc19841e76762be1c42c4c2737bd268
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 6 17:43:20 2009 +0000

    fix strstr. Seems the function never worked before, except the searched
    substring is at the end.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8dcd50b15558dd2e3ee509779dd39b7f385238f4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 6 17:24:29 2009 +0000

    fix a bunch of cast and type warnings and don't call the apic "nvram", that
    doesn't make no sense. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 054c7235c3d1094214b9cbe9f2cc876dfb249d62
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 6 17:22:35 2009 +0000

    use pointers instead of size_t when dealing with pointers. Also fix a few
    warnings (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8c77e82c5bd097d65fdd26022ef1ad559f3c87b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 6 17:21:23 2009 +0000

    use inb instead of outb for delays in usb debug code (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cbbc7902a76dadbfa6aea55a7b65616ea680536
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Mar 6 17:20:17 2009 +0000

    really clean out all compile time generated files (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59c36f97db28aa558b6f1b4d4d63bbfb44d98978
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Mar 6 00:40:25 2009 +0000

    During the conversion of flash chip accesses to helper functions, I
    spotted assignments to volatile variables which were neither placed
    inside the mmapped ROM area nor were they counters.
    Due to the use of accessor functions, volatile usage can be reduced
    significantly because the accessor functions take care of actually
    performing the reads/writes correctly.
    
    The following semantic patch spotted them (linebreak in python string
    for readability reasons, please remove before usage):
    @r exists@
    expression b;
    typedef uint8_t;
    volatile uint8_t a;
    position p1;
    @@
     a@p1 = readb(b);
    
    @script:python@
    p1 << r.p1;
    a << r.a;
    b << r.b;
    @@
    print "* file: %s line %s has assignment to unnecessarily volatile
    variable: %s = readb(%s);" % (p1[0].file, p1[0].line, a, b)
    
    Result was:
    HANDLING: sst28sf040.c
    * file: sst28sf040.c line 44 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 43 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 42 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 41 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 40 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 39 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 38 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 58 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 57 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 56 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 55 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 54 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 53 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    * file: sst28sf040.c line 52 has assignment to unnecessarily volatile
    variable: tmp = readb(TODO: Binary);
    
    The following semantic patch uses the spatch builtin match printing
    functionality by prepending a "*" to the line with the pattern:
    @@
    expression b;
    typedef uint8_t;
    volatile uint8_t a;
    @@
    * a = readb(b);
    
    Result is:
    HANDLING: sst28sf040.c
    diff =
    --- sst28sf040.c        2009-03-06 01:04:49.000000000 +0100
    @@ -35,13 +35,6 @@ static __inline__ void protect_28sf040(v
            /* ask compiler not to optimize this */
            volatile uint8_t tmp;
    
    -       tmp = readb(bios + 0x1823);
    -       tmp = readb(bios + 0x1820);
    -       tmp = readb(bios + 0x1822);
    -       tmp = readb(bios + 0x0418);
    -       tmp = readb(bios + 0x041B);
    -       tmp = readb(bios + 0x0419);
    -       tmp = readb(bios + 0x040A);
     }
    
     static __inline__ void unprotect_28sf040(volatile uint8_t *bios)
    @@ -49,13 +42,6 @@ static __inline__ void unprotect_28sf040
            /* ask compiler not to optimize this */
            volatile uint8_t tmp;
    
    -       tmp = readb(bios + 0x1823);
    -       tmp = readb(bios + 0x1820);
    -       tmp = readb(bios + 0x1822);
    -       tmp = readb(bios + 0x0418);
    -       tmp = readb(bios + 0x041B);
    -       tmp = readb(bios + 0x0419);
    -       tmp = readb(bios + 0x041A);
     }
    
     static __inline__ int erase_sector_28sf040(volatile uint8_t *bios,
    
    It's arguably a bit easier to read if you get used to the leading "-"
    for matching lines.
    
    This patch was enabled by Coccinelle:
    http://www.emn.fr/x-info/coccinelle/
    
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    --
    http://www.hailfinger.org/
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bba113ec073f744cfaf53a59f2712319dae181ec
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Mar 5 19:33:12 2009 +0000

    If get_pbus() is called for a device which has no parent/ancestor bus
    with nonzero PCI bus operations, get_pbus() will get stuck in a silent
    endless loop.
    Detect the endless loop and break out with an error message.
    
    Such a situation can happen if the device tree is not yet
    initialized/walked completely.
    
    This fixes the unexplainable hang if pci_{read,write}_config{8,16,32}was
    used in early mainboard code for the AMD DBM690T. Instead, the code will
    now die() with a meaningful error message.
    
    Thanks to Ward Vandewege for testing my patches to track down that bug.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ac12ecd27a8e32a02193ea22dc36c89a060cc22e
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Mar 5 19:24:22 2009 +0000

    flashrom: Use helper functions to access flash chips.
    
    Right now we perform direct pointer manipulation without any abstraction
    to read from and write to memory mapped flash chips. That makes it
    impossible to drive any flasher which does not mmap the whole chip.
    
    Using helper functions readb() and writeb() allows a driver for external
    flash programmers like Paraflasher to replace readb and writeb with
    calls to its own chip access routines.
    
    This patch has the additional advantage of removing lots of unnecessary
    casts to volatile uint8_t * and now-superfluous parentheses which caused
    poor readability.
    
    I used the semantic patcher Coccinelle to create this patch. The
    semantic patch follows:
    @@
    expression a;
    typedef uint8_t;
    volatile uint8_t *b;
    @@
    - *(b) = (a);
    + writeb(a, b);
    @@
    volatile uint8_t *b;
    @@
    - *(b)
    + readb(b)
    @@
    type T;
    T b;
    @@
    (
     readb
    |
     writeb
    )
     (...,
    - (T)
    - (b)
    + b
     )
    
    In contrast to a sed script, the semantic patch performs type checking
    before converting anything.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>
    Tested-by: Joe Julian
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 51001fbd81543d738a07cd36063fe5705eeff3ad
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Mar 4 01:06:41 2009 +0000

    I just went on a bugfix frenzy and fixed all printk format warnings
    triggered by the AMD 690/SB600 targets.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b95ced365dd80eb1891f0eb7a2c79a94a7d0bfc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Mar 4 00:25:44 2009 +0000

    fix make clean as suggested by Myles Watson.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6b2e760f03a6605abe357e1cda51999de2a519e2
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Mar 2 22:45:31 2009 +0000

    Small bug somehow slipped there. The method body length is incorrectly computed.
    The attached patch fixes this. I did not spotted that because the return arg is
    moved just outside of method and I have overseen the closing }
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc1924850107c1b1cc1e817c82cade90c2445078
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Mar 1 18:05:25 2009 +0000

    (Trivial) Add missing header file.
    
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36c83404a356b5dc379dbd46e25514e487f01ec8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 1 10:16:01 2009 +0000

    Some changes required to get yabel working on v2 (and they generally make
    sense, too). Have one u64 instead of three.
    
    In order to use the old bios emulator, you have to do nothing. (Default, if
    CONFIG_PCI_ROM_RUN is enabled)
    
    In order to use yabel in your target, you need to add the following lines to
    your config:
      uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
      default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1
    
    In order to use vm86 in your target, you need to add the following lines to
    your config:
      uses CONFIG_PCI_OPTION_ROM_RUN_VM86
      default CONFIG_PCI_OPTION_ROM_RUN_VM86=1
    Note: vm86 only works on platforms with _RAMBASE in the lower megabyte.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b34db8d1de2d63ffa829fe03db0ce2aaba40233
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Feb 28 20:10:20 2009 +0000

    coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3
    a long time ago. This will make it easier to port v2 boards forward to v3 at
    some point (and other things)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c924d2f48ba1bb6a9d5a20453f230bb6be726e0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Feb 28 17:19:55 2009 +0000

    fix those two boards that broke due to the config tool fixes.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9987ad806f23a20cf2f8aced190ff3d2e50dcd0c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Feb 28 17:09:29 2009 +0000

    This is a small fix for the last checkin (does not fix those two boards) that
    caused same filenames to still cause objects being dropped from the build list
    - which was the whole purpose of the patch.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 21c8b5ab5cf0bf9c48a68305213cc81b5af0cde5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Feb 28 12:50:32 2009 +0000

    With this patch the v2 build system will create a directory hierarchy
    similar to what v3 does. This is required to have two source files with
    the same name but in different directories. (As in, two different SuperIOs on
    board, with a superio.c each)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c7f46b42215502ecaee54c85f6d08dce9e21279
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Feb 27 23:09:55 2009 +0000

    Generic approach of putting BIOS tables at the end of memory
    (in addition to their low locations)
    
    This adds the kontron 986LCD-M and the i945 as a sample.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 678d6140a5f75bde7b5a6b7ef296ebb7a3dda166
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Feb 27 17:51:16 2009 +0000

    This patch makes several CMOS/NVRAM reads dependent on whether there's a table to read.  Otherwise you never know what you'll get from the factory BIOS.  There are probably more, but these are the ones compiled into the s2895.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a85c0059f3fa5bdce6002f09e99fd70037552119
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Wed Feb 25 08:07:33 2009 +0000

    flashrom: Add SST25VF040.REMS with TEST_OK_ PROBE READ
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c5a2ec6f96a10b9dcc110fc63d78b1a46dde4ea3
Author: Mart Raudsepp <leio@gentoo.org>
Date:   Sun Feb 22 23:13:33 2009 +0000

    libpayload: Fix build when both USB and PS/2 keyboard support is disabled
    
    libpayload uses -Werror for some reason right now, and the
    variable 'c' in curses_getchar is only used if CONFIG_USB_HID
    or CONFIG_PC_KEYBOARD is defined, giving an unused variable
    warning that gets promoted to an error.
    So wrap the variable declaration around appropriate #ifdef's
    
    Signed-off-by: Mart Raudsepp <leio@gentoo.org>
    Acked-by: Ulf Jordan <jordan@chalmers.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc8744e1bfe25d8ddf291ca6082eb45fa208e270
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Feb 22 21:07:28 2009 +0000

    flashrom: SST29EE020A TEST_OK_ PROBE READ ERASE WRITE
    
    Report by Holger Mickler. Thanks!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fe849b2ff7afe7437baa1798ecf74d80a4f09388
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Thu Feb 19 08:39:16 2009 +0000

    This patch is for AMD boards which can do the P state generation. This just
    removes the ugly binary DSDT patching and all other related stuff. Stick to
    infrastructure in previous patch.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ad11e8d33bf0f377ea882848e7e9e6cdd0243bb
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Feb 18 20:41:57 2009 +0000

    Carl-Daniel's part:
    
    This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and
    mainboard_$VENDOR_$BOARD_config to mainboard_config.
    
    Ron's part:
    The config change that makes the naming change not break every build.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d58671c4bfc0376e288cb0f2936bd43d8cfbb48e
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Feb 17 21:38:51 2009 +0000

    Add QWord support to acpigen.
    
    Add TOM2 to the K8 DSDT.
    
    Thanks to Rudolf Marek for testing and fixing this patch.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 142cad1503c9b218dd71fc1e0293aa1bd51d11c6
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Tue Feb 17 16:23:26 2009 +0000

    Bayou: Clean up Bayou's window after returning from a payload.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 08afc6d9e0fe428190bcfb1bceb61418bee1538e
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Feb 17 12:56:58 2009 +0000

    Unify CAR so the same compiled code does the right thing on both
    K8 and Fam10+ CPUs.
    
    What this patch does:
    1. Enable SSE (to get some more registers to play with)
    2. Determine CPUID, and stash it in an XMM register, and reference
       value for comparison in another XMM register (mangled somewhat to
       simplify inequality comparisons)
    3. Add a macro jmp_if_k8, which jumps if the CPU is K8
       (using an SSE compare)
    4. Replace #if CAR_FAM10 sections with runtime checks using jmp_if_k8.
       This is pretty mechanical work. The macro uses local labels
       (1: and 2:) to prevent namespace issues
    5. At one time, CPU_ADDR_BITS is used to fill a register. This is
       replaced with hardcoded values for both cases, and switched
       appropriately.
    6. Disable SSE
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b575d67b9ab9b7255a615507f07cd4bbab7a60f0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Feb 15 23:32:57 2009 +0000

    This is a safety measure, since the shipping buildrom fails badly at present.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5389c7f72b251a7e02df892271adac791e7d0266
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Feb 15 02:53:18 2009 +0000

    - Fix up amd pistachio and dbm690t.
    - make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs
      on some platforms.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a175533dc34cd8b2c98b47124cae2bbd7fcb10d4
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Feb 14 16:23:16 2009 +0000

    Change Log:
    Bellongs to r3947
    
    Following patch adds dynamically generated P-States infrastructure as well as
    M2V-MX SE as example how to do that. It is based on AMD code and mine code for
    ACPI generation.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 537bd5f637456a810f9144529a3d01fc5006e38f
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Feb 14 15:42:42 2009 +0000

    Bellongs to r3946
    
    Following patch adds dynamically generated P-States infrastructure as well as
    M2V-MX SE as example how to do that. It is based on AMD code and mine code for
    ACPI generation.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f997b5554acd2c3ddcc9080b78a834853e59c783
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Feb 14 15:40:23 2009 +0000

    Following patch adds dynamically generated P-States infrastructure as well as
    M2V-MX SE as example how to do that. It is based on AMD code and mine code for
    ACPI generation.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66948f7e8c3e2e89c5fd8a7b0b4c7bc112553aa0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Feb 13 20:20:21 2009 +0000

    This target is dead.
    
    The company is dead.
    
    It causes builds to fail, and that is not a problem we need to have.
    
    Removing it to remove the problems it causes.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31197a61d9d1a82d4a3a48b4fdb0da9ea51bd29e
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Feb 13 18:46:22 2009 +0000

    Increase ROM_IMAGE_SIZE for the agami aruma to resolve overlapping
    sections.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 552b327ca39f12b21a9e1a8dfdb71f3f26abf256
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Feb 12 21:30:06 2009 +0000

    This patch converts __FUNCTION__ to __func__, since __func__ is standard.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7f86ed122068f34de4e8723b83e0d9b053cea9a2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Feb 12 16:02:16 2009 +0000

    Fix mtrr setup for UMA architectures.
    
    If high SMM memory is used (and needs to be uncached for whatever reason; it
    shouldn't in my opinion), we should do it the same way.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e755bc159688d65109cf100eb7a2da88cb6c3606
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Feb 12 14:50:43 2009 +0000

    Fix typo in PCI ID (1914 should have been 7914).
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d64b2441e46c85f0717a5f9073a818f0ee368d9d
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Feb 12 13:58:31 2009 +0000

    Remove dead lines. Trivial.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d76d5791fd740af594578169217a1b47254f9f00
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Feb 12 13:54:03 2009 +0000

    Rename TOM to TOM1 and refer to the SSDT value with an External(TOM1)
    clause.
    
    An ITE87427 Super I/O does not exist. Use the real name (IT8712F) of
    the chip on the DBM690T board.
    
    Use decimal values for KELV, THOT and TCRT on the Pistachio board for
    better readability.
    
    Tested by Maggie Li on DBM690T and Pistachio.
    Tested by Carl-Daniel Hailfinger on Asus M2A-VM.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a208781b4c199a5673ab8429cccf32bee39112f
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Feb 12 13:39:36 2009 +0000

    Improve mainboard.c comments for DBM690T and Pistachio.
    Fix reference to documentation.
    Use __FUNCTION__ instead of hardcoding function names in printk
    messages.
    
    No functional changes.
    
    I'm slowly getting to the point where adding another RS690 board is
    really easy and needs almost no changes to the existing target.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7dde1da9a7cbedcdd6d75a935c04f09f9b7cdc4c
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Feb 11 16:57:32 2009 +0000

    Print a loud warning message if we run out of MTRRs.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9dff094efdeb0d48d4ca25fe98789a6dd1e4fc0f
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Feb 11 12:08:55 2009 +0000

    Fix one leftover reference to AmlCode_ssdt which was forgotten in r3929.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3936 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6818a3236753f47aa7cb5a345ee097075010e3a5
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Tue Feb 10 21:12:35 2009 +0000

    Fix bayou payload execution.
    
    Bayou must link with its own ldscript to end up at a load address that
    doesn't interfere with payloads. Make Bayou's ldscript MB compatible, so
    the link with libpayload/lib/i386/head.o succeeds.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3ba0ce5f58265e95d5b667ab7ec8a3a180bff4d0
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Tue Feb 10 21:09:03 2009 +0000

    Fix bayou payload execution.
    
    Bayou must link with its own ldscript to end up at a load address that
    doesn't interfere with payloads. Make Bayou's ldscript MB compatible, so
    the link with libpayload/lib/i386/head.o succeeds.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94e340b22aa97821333b26dfcd29ac692ffc961e
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue Feb 10 03:02:05 2009 +0000

    Change 0x%p to %p.  Thanks Stefan for catching the one I introduced in 3931.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd7e9b55dd9887047555e99ec926a1cf762f52de
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Feb 9 20:26:14 2009 +0000

    flashrom: Fix broken flash chip base address logic
    
    Elan SC520 requries us to deal with flash chip base addresses at locations
    other than top of 4GB. The logic for that was incorrectly triggered also when
    a board had more than one flash chip. This patch will honor flashbase only when
    probing for the first flash chip on the board, and look at top of 4GB for later
    chips.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4ddbff70621449606fa3f0a1ad8277fac0f5aeb
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Feb 9 17:52:54 2009 +0000

    Remove some warnings, mainly from format strings which didn't match the
    arguments.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4505948faec7cc30edb9daebf53ca006d4a1645a
Author: Dan Lykowski <lykowdk@gmail.com>
Date:   Thu Feb 5 02:18:42 2009 +0000

    Use the correct device for switching on HDA.
    
    Reorder HDA (HD Audio) init:
    The reordering was based on what order things happen in the BIOS
    Developers guide, RPR, and SATA driver. I fixed the order of the devices
    that didn't matter to clean up the change log.
    1. Enable the Chip
    2. Setup the SMBus registers
    3. Setup the Device Registers
    4. Look for Codec
    5. Init Codec
    
    The codec init was changed to match the description in the RRG pg 235.
    Mem Reg: Base + 08h Bit 0. There were unneeded things happening.
    
    Added 1ms delay to match the BKDG while waiting for BAR+0xe to set its
    bits.
    
    Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
    
    Tested on AMD DBM690T and AMD Pistachio by Maggie Li. Works.
    
    Tested on Asus M2A-VM by Carl-Daniel Hailfinger. Improves the situation,
    but some warnings remain.
    
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8db0cfefd16c9aa6dbc0ffdfd9d2ba81a1561650
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Feb 3 22:37:22 2009 +0000

    Following patch converts the run-time SSDT patching via update_ssdt funtion to
    new AML code generator. Compile-tested on all changed targets. I think it should
    work because it works for Asus M2V-MX SE.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 742655bb4d18fcb0c5081f6d9c8ba5b870fa0b47
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Feb 3 22:25:51 2009 +0000

    Following patch adds missing CPU names. Please check
    http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
    if I did not made any mistake.
    
    Works for mine CPU  ;)
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 15884260e763abe575cb9e952b5884c3bae20c85
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Feb 2 22:55:26 2009 +0000

    flashrom: MSI MS-7046 board enable
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: David Tiemann <davidtiemann@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e66c258f1baf668fee417b08494480ddedc00749
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Feb 1 18:40:50 2009 +0000

     Following patch fixes VIA SPI (VT8237S). It needs to have opcodes
     initialized same way as ICH7.
    
     Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
     Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 293b5f52253ec0e5edb38e9f7113afc7e8f8ba6e
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Feb 1 18:35:15 2009 +0000

    Following patch adds dynamic ACPI AML code generator which can be used to
    generate run-time ACPI ASL code.
    
    Moreover it demonstrates its use on Asus M2V-MX SE where the SSDT table is
    generated by new function k8acpi_write_vars (technically similar to
    update_ssdt). But lot of nicer.
    x
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c49bc9744c2e9044ddd1c8d20a1728f57eda85c
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Jan 30 02:05:20 2009 +0000

    Bring AMD K8 ACPI mangling more in line with Fam10 ACPI mangling. No
    functional changes, only a little bit of (mostly formatting) cleanup to
    make merging easier.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b6dc72303cceab0b06b613f800b5db413b2aa7b4
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Jan 28 00:27:54 2009 +0000

    Factor out read and erase functions from flashrom main().
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fe53c7628bab78d25b3878710bae2e51d7687b0a
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Jan 28 00:19:49 2009 +0000

    Correct FDAT->FADT typo.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3108a12e9b701e6c3daeb0ae629ecb603dd6509c
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 17:18:31 2009 +0000

    msrtool: Allow MSR symbols (names) to also be used as addresses.
    
    Thanks for the idea Mart!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c1d6ed9a21bc96b0d4eb778b78c65b304e5e46f9
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 17:03:05 2009 +0000

    msrtool: Linux /dev/cpu/*/msr returns the low 32 bits before the high 32 bits.
    
    Thanks to Mart for spotting this!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a8866243d89f5a6da3fe1558b6ac469130275d97
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 15:29:27 2009 +0000

    flashrom: Add VT8237A PCI ID
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 726c16d9839cef505ed062640e2769cd7924f201
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 15:19:43 2009 +0000

    flashrom: Fix one dead increment and one dead assignment as found by clang.
    
    Thanks Patrick!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c39cb144e997a35f294b2b38377d14aab7825f18
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 06:42:02 2009 +0000

    flashrom: Driver for ST M29F002T/NT/B. T/NT TEST_OK_ PROBE READ ERASE WRITE
    
    Test report from Julia. Thanks!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Julia Longtin <juri@solarnetone.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3bc765493861f68011aa3f9ece19bb397e2453e
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 04:48:01 2009 +0000

    flashrom: Fix copypaste error in r3913.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fbda0d31439bd985a8f53e2f77924ea77cd8fe44
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 04:12:58 2009 +0000

    msrtool: AMD CS5536 probe implementation.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 279cdbb37d7106650abbbe4aca19ec770e44cdfc
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 04:10:12 2009 +0000

    msrtool: Make configure work with zsh, the default shell in Darwin.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c800eeb39bda2dbc33187af81d75651b1a9adf14
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 03:37:40 2009 +0000

    flashrom: SST25VF040B using 0x90 identification and AAI write.
    
    SST AAI is Auto Address Increment writing, a streamed write to the flash chip
    where the first write command sets a starting address and following commands
    simply append data. Unfortunately not supported by Winbond SPI masters.
    
    From July 2008.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ee44151cc9b0db006ba23999652e592e88d4708
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 03:23:50 2009 +0000

    flashrom: Decode SST25VF040B status register, also from July 2008.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 37c4a968745d22ccf8a0502415c8a3f16c635479
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 03:12:44 2009 +0000

    flashrom: Intel Desktop Board D201GLY
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36b3932f994bce7cb38d1b3bec9e25f6a346294b
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 03:08:45 2009 +0000

    flashrom: Winbond SuperIO SPI driver.
    
    Developed and tested to work on Intel D201GLY in July 2008.
    Tested by a helpful person on IRC whose name I've since forgotten. Sorry!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8991302f5450fd1a02eb107a6a0fc491cc437c8c
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 02:34:51 2009 +0000

    flashrom: Export Winbond SuperIO register access functions in board_enable.c.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 732a229a106d5e571ec2d30dcee87afe612452dc
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 02:20:56 2009 +0000

    flashrom: Document exit() codes introduced in r3907.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 800621e0c5774761531c31a5f58a0e84a8878ef8
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 02:04:19 2009 +0000

    flashrom: exit(2) on /dev/mem open() failure and exit(3) on mmap() failure.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0860215ab23c68cceb4f26f7b6c0e2a3f647ebcc
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 01:33:02 2009 +0000

    flashrom: Add license header to physmap.c so everyone is happy. :)
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 713ee92c96c0c92cdd1fe64a58cc1f9abd94d11c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jan 26 01:23:31 2009 +0000

    flashrom: Darwin / Mac OS X
    
    Through DirectIO from coresystems GmbH we now support Darwin/Mac OS X.
    DirectIO is available at http://www.coresystems.de/en/directio
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d48091a35c18745527d1e164f82bc774e4bd6b58
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 01:16:09 2009 +0000

    flashrom: Small cleanup in Makefile.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53ac3947db69be8c526958b07f59a24dbc3678be
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jan 26 01:10:48 2009 +0000

    flashrom: Abstract mmap() in physmap.c and only open /dev/mem on the first physmap() call.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ac29d61a454f0562c5c63ea1f5e14f9068904bf0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jan 26 00:57:54 2009 +0000

    fix a potential null pointer reference in strdup (as found by Patrick Georgi)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c4421ddbdd6f4fec3de2fa431d42f0421a758d1
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 00:39:57 2009 +0000

    flashrom: Change flashrom.c:map_flash_registers() from int to void.
    
    The function exit()s on failure, and no callers check the return value.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8dec57fe0c3721d7ced7b7aa41e90980867e1299
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 00:19:36 2009 +0000

    flashrom: Forgot some things in r3899.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e03d84af694259c309c1b06ef659302a45674a6b
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 26 00:15:56 2009 +0000

    flashrom: Little readability improvement in cbtable.c:coreboot_init()
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09c0b7c61d50e6f1daf75a2d71fdc8cd61431d61
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jan 26 00:07:25 2009 +0000

    flashrom: Change FreeBSD #ifdef into #if defined()
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb79ba4aae7c5b9bf270577e4e75113466804a0b
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jan 25 23:59:30 2009 +0000

    flashrom: Make Makefile a bit more portable. Shell echo doesn't always know -n.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68c0cec9dab171b716894f8f7be5069daca902e8
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jan 25 23:55:12 2009 +0000

    flashrom: Add dry Am29F080B Am29LV081B SST39VF080 definitions per data sheets.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2450419294dc9bdad5f1822cc5ecc333c5520369
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jan 25 23:52:45 2009 +0000

    flashrom: Beautify flash chip ID verbose printout a little, always use %02x.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e6ff8bfc0e5c9a5238f046892dc19bcbec55780
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jan 25 20:41:51 2009 +0000

    flashrom: Fix stupid off-by-one error in erase verification.
    
    As reported by Jody McIntyre. Thanks!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 269e1bdd13803a1946c61075d27b9aa47de755d3
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jan 24 23:01:08 2009 +0000

    flashrom: ST M50FW080 TEST_OK_ PROBE READ ERASE WRITE
    
    Report by Jody McIntyre. Thanks!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f77eeb036253115d86df0b41bfb81ae3ec0ba78
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jan 24 01:32:40 2009 +0000

    flashrom: SST25VF080B TEST_OK_PROBE
    
    Report by Scaldov M.V. Thanks!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cab81c03eb8a8ad04516571110aa5c0931499242
Author: Maggie Li <maggie.li@amd.com>
Date:   Fri Jan 23 22:16:13 2009 +0000

    Fix rs690 bug about GPPSB configuration.
    Signed-off-by:  Maggie Li <maggie.li@amd.com>
    Reviewed-by:    Zheng Bao <Zheng.bao@amd.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e5481356f7e0f925dfe935e6d7a7f1cdd3681ec
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Jan 23 05:23:06 2009 +0000

    flashrom: Check all mmap() calls and print helpful Linux error message.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a681b1d840e701e41892f8375a15baf56107ab5
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Jan 22 22:53:59 2009 +0000

    flashrom: Provide some hints for the user in case /dev/mem mmap fails.
    
    resolves #121
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df2eb8e97b67452f52723e2e93c0ebcd8e3e61d5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jan 21 01:56:53 2009 +0000

    Now that x86emu debugging is actually working, it should be switched off per
    default because it adds quite noticably to the image size.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 679c9f9299a5e11a2f7f333c69efd652526b4858
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 22:54:59 2009 +0000

    forgot to svn add
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54309d637ac2cf474793b884b5392f0a6e5390a9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 22:53:10 2009 +0000

    Update Kontron board
    
     - use new features of the ich7 update
     - move rambase above 1M to avoid memory trashing through SMM relocation
     - enable superio HWM
    
    Update ICH7 driver
    
     - minor smi cosmetics (in progress)
     - add real ac97 driver
     - add real azalia driver
     - fix some interrupt issues
     - fix some sata issues
     - include Patrick's fix for _lpc.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 977ed2d99565fc35c52f50cbe310b7b211611e94
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 22:46:52 2009 +0000

    fix small TOLUD issue in i945 raminit (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebb763fecf31e4bde782edb8ee96f15e1e45a3f0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 22:39:31 2009 +0000

    put in a little comment (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23b655f3b0fe4121e7d91fb309364fac14beea0b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 22:07:20 2009 +0000

    some brown paperbag please. fix build.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ab216023c18aad0df7f4b604bec19f4d31c412e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 21:40:16 2009 +0000

    fix compiler warnings (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a829bfe882df00810912189384145fbdda10529d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 21:38:17 2009 +0000

    add a header file for i8259.h (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5833f7c0e69df069aec918ba9f34b4a0fe0019f5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 21:36:39 2009 +0000

    Backport all x86emu fixes from Pattrick Hueper to coreboot v2 (acked in v2,
    hence I consider it trivial in this case). This does not include the Yabel
    work.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20b261dacf56a0bf09a74931cd511537b79b6983
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 21:32:37 2009 +0000

    Fix register typo for core 2 cpus (trivial)
    
    This bug was reported a long time ago by Thomas Jourdan. Thanks a lot Thomas.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c5983305ef67f2f7df81945ae5508fdf2da6c5ea
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 21:27:23 2009 +0000

    fix compiler warnings (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c4af2b9e278d0c48cc6820ae2d1a300915425cb
Author: Jon Dufresne <jon.dufresne@gmail.com>
Date:   Tue Jan 20 20:25:48 2009 +0000

    This fine work by Jon Dufresne was awkwardly rotting on the mailing list for
    almost three years. Let's put it somewher so people find it if they're looking
    for it. Someone dare sending a late announcement to the coreboot-announce list?
    :-)
    
    Add (preliminary) support for Intel 855GME (Mobile version of the 855) chipset
    to coreboot.
    
    There are some holes in the code to be filled out, but unlike the code for the
    855pm this has booted a mainboard before.
    
    Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef6cb094b83b2717fba379a2c6670c19b12c676d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 20:13:01 2009 +0000

    This patch makes the recently added assembler debug optional, as it may
    cause problems with certain toolchains. This patch will also safe some hard
    disk space for those of us working on laptops or netbooks with always too small
    disks.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94f17773efc8f1878167dd156d414abb5afa10bb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 19:21:47 2009 +0000

    fix inconsistent user interface naming. don't show compile paths to users
    during bootup (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26d431a616076950da47fe423d3c8d8d40cea567
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 19:17:51 2009 +0000

    fix coding style (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc2e8edc238b54e25aa0b69b19bfbf2fde2c7f9a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jan 20 19:17:11 2009 +0000

    Trivial stuff:
    
    * fix a warning that should not be one.
    * fix capitalization typo
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90308bb752d2ae64a763d9eed2a324202a634895
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Jan 20 18:37:26 2009 +0000

    Check the printk format string against the matching arguments. We have
    this type of checking in the v3 code since ages, but v2 will happily
    compile any code with bogus printk format strings and/or parameters.
    This can cause real bugs and at least needs to emit a warning, if not
    an
    error. Go with a warning for now since most of the flagged format
    strings are wrong but harmless in a 32-bit x86 environment.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d0363c3927ff08bf48c3a892f6e8ffa37f0e1fde
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jan 19 21:34:41 2009 +0000

    ouch. never do last minute changes. :-(
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 269563a423f9291e84b5a93859a3e17767cf27a0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jan 19 21:20:22 2009 +0000

    First shot at factoring SMM code into generic parts and southbridge specific
    parts.
    
    This should help to reduce the code duplication for Rudolf's K8/VIA SMM
    implementation...
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0fd183ce72c44f42859924de5739c73c249e7df0
Author: FENG yu ning <fengyuning1984@gmail.com>
Date:   Sun Jan 18 06:39:32 2009 +0000

    flashrom: Fix ICH9 locking register address and add important debug output.
    
    Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: FENG yu ning <fengyuning1984@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8aaeaa143b5da8ddaac709bcf34a2cd26508bdd
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Jan 16 12:44:41 2009 +0000

    The DBM90T code sets bit 10 in _PSS as part of the control value, but
    bit 10 is part of NewVID. That means the resulting VID is wrong and
    causes the processor to crash.
    The Pistachio code has the same bug.
    
    This patch fixes the wrong setting and changes control from a magic and
    incorrect unexplained value (0xE8202C00) to a combination of explained
    values and shifts which has the right value (0xE8202800).
    
    It is tested on my machine and it survived 200 changes from minimum to
    maximum frequency every 100 ms under heavy load and under no load.
    
    In the long term we want to consolidate all AMD FIDVID code into one
    generic library file.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    Maggie Li has tested it on her DBM690T board. It is ok.
    Acked-by: Maggie li <Maggie.li@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 734d09e05b54d75a190685345fa81a2de0560d78
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Jan 16 03:44:41 2009 +0000

    First part of heterogenous dualchannel support.
    
    Do not allow non-identical DIMMs yet, but prepare the code.
    
    Calculate tCL related settings per DIMM in a dual channel setup. The
    check for compatibility will come in a later patch, but since DIMMs
    still have to be identical, this does not hurt.
    
    Factor out tRC calculation to prepare for per-DIMM calculation.
    
    Add diagnostic messages to tRC code.
    
    Test booted to FILO, behaviour is identical if you ignore the added
    debug messages (which are switched off by default).
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d72e10bb4475f30423f7937fcdfc7940ba3fb5c
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Jan 16 03:03:40 2009 +0000

    Refactor K8 rev F DDR2 CL timing retrieval.
    This will allow usage of compatible DIMMS in a dual channel setup
    instead of requiring the DIMMS to be identical.
    
    Code impact is minimal because a large chunk of code has been moved into
    a separate function with almost no changes.
    
    Tested, yields identical results and identical logs.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abcddcd392bbe5e36e53ef8611df892812e2a367
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Jan 16 00:19:17 2009 +0000

    Since all K8 targets now have CONFIG_USE_PRINTK_IN_CAR enabled, using
    print_* in K8 RAM init does not make sense anymore. Convert almost all
    print_* to printk_*. This improves readability a lot and makes the code
    shorter.
    
    Reorder the SPD equality checks in the dual channel DIMM compatibility
    checking code. This is to make sure that we know if any other mismatches
    are present in the DIMM. The new order eases debugging with the old
    code.
    Add a comment about false negatives in that code. This needs to be
    implemented correctly, but that is hard to do in an efficient way.
    Check if the DIMMS in a dual channel setup have any compatible CAS
    latencies.
    
    Add better comments to explain why wrong-at-first-glance SPD CL walking
    code is actually correct.
    
    Fix a few typos.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6912846dda39e5c81993a64832301e78492ec254
Author: Dan Lykowski <lykowdk@gmail.com>
Date:   Thu Jan 15 02:35:30 2009 +0000

    Adds a retry/faildown to SB600 SATA detection logic.
    
    SATA port status kept returning 0x1: BAR5+po+28h
    1h = Device presence detected but Phy communication not established
    
    This patch adds logic to force 1.5g if the drive fails to communicate at 3.0g.
    
    Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f502c7537707c82e4cea124df53eb76a3ddd807
Author: Dan Lykowski <lykowdk@gmail.com>
Date:   Thu Jan 15 02:21:27 2009 +0000

    amdk8: This patch fixes ram init problems when using the 9W Sempron part.
    
    Trying to read the FIDVID register when the processor does not support FIDVID
    control causes a GP Fault. This patch reads the startup FID from a different
    MSR. I have verified this patch to work on the dbm690t platform.
    
    Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 884e1cbeebeefa2d38f95339545781a8c503a46d
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Jan 15 02:13:18 2009 +0000

    flashrom: Add ICH opcode debugging.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d860763e731e56aa57d6689a85ac020f9ac59de6
Author: Stephan Guilloux <stephan.guilloux@free.fr>
Date:   Thu Jan 15 00:48:24 2009 +0000

    Similarly to flashchips array, this patch intends to make the table
    board_pciid_enables more readable.
    
    Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
    
    > What real problem does this solve?
    
    1. Next time someone adds a new struct member, we avoid mistakes of
    ordering of initializers
    2. we avoid mistakes in the first place.
    
    The .x = y stuff was added for a (good) reason, I think this is an
    improvement.
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3462462b2a140c5a9f9dfcf93f2590cc6a37274d
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Jan 13 14:32:27 2009 +0000

    flashrom: Always print address when verification fails, not only with -V.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e31a8d5c959abd8f6f1c0fdef9249ec99fed7602
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 12 21:31:14 2009 +0000

    flashrom: Board enable for GIGABYTE GA-MA78G-DS3H
    
    This board has 2x MX25L8005 flash chips behind an IT8718F LPC->SPI bridge.
    The board uses GIGABYTE's patented BIOS failover technology, and at this point
    we do not know how to control which of the two chips flashrom actually hits.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Yul Rottmann <yulrottmann@bitel.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88ded318c3bd9415eb87790cee5c5dd889d0d683
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 12 21:28:03 2009 +0000

    flashrom: IT8718F works just like IT8716F.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Yul Rottmann <yulrottmann@bitel.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 475ac26a9b4f14e35839f6b0df17ea9e81531b74
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jan 12 21:00:35 2009 +0000

    flashrom: Check return value of fscanf()/fwrite()/fread()
    
    Fix build error on distros with warn_unused_result attributes in glibc.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Yul Rottmann <yulrottmann@bitel.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ef8e0f3e3a9044aa326a62e47b71670d9a218b7
Author: Dan Lykowski <lykowdk@gmail.com>
Date:   Mon Jan 12 16:16:08 2009 +0000

    Check to see if K8 processor is capable of changing FIDVID otherwise it will throw a GP# when reading FIDVID_STATUS
    
    Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6fa7e6dae97853c948d1b5e5cffb35fa0f042dc5
Author: Idwer Vollering <vidwer@gmail.com>
Date:   Sun Jan 11 03:31:02 2009 +0000

    flashrom: Update usage in README
    
    Mimicked from flashrom.c
    
    Signed-off-by: Idwer Vollering <vidwer@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4dad15084951748f1737523b260d51c528ecce56
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Sun Jan 11 00:35:30 2009 +0000

    Ignore some more sections, created by newer toolchains
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3854 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0afdea4e42a8672fa4611b8610bc11e31c17d9de
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Jan 8 16:53:13 2009 +0000

    Add erase and write functions to the following chip definitions:
    
    AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321 AT25DF321A AT25DF641
    AT25F512B AT25FS010 AT25FS040 AT26DF081A AT26DF161 AT26DF161A AT26DF321
    AT26F004
    
    Straight from the data sheets, untested because I lack the hardware.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 44b3bf7ed7bc23aaa3d189d902959c5da34d6530
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Jan 8 04:56:59 2009 +0000

    The flashrom man page has incomplete author/copyright sections and an
    incorrect license section.
    - Remove the copyright listings and refer the reader to the source
      files.
    - Update the author list to those which have copyright messages in the
    source files.
    - Correct the license from GPL v2+ to (GPL v2, with some files under
      later versions as well)
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 901f25acd3ba55966ed5b2a126e5e3579efcb7ec
Author: Stephan Guilloux <mailto:stephan.guilloux@free.fr>
Date:   Thu Jan 8 03:40:17 2009 +0000

    This patch improves machine parseability and human readability of
    flashchips.c over what's currently in flashrom HEAD.
    The explicit initialization makes sure any future struct flashchip
    reordering is not needed. (Except for the case where we need arrays
    of some of the struct members.)
    
    Signed-off-by: Stephan Guilloux <mailto:stephan.guilloux@free.fr>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d32b9e605f7d0c4f0e6b74f80dee8d383cd4ab1f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jan 7 12:35:09 2009 +0000

    Add SST49LF020 support.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f58691ffb69cec3dd92f63c600db1c3c168b1bcd
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jan 7 12:15:46 2009 +0000

    Add AMD-768 chipset support.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c84ce73ab80728fef196efd7a7e44e1a271f363f
Author: Sven Schnelle <svens@stackframe.org>
Date:   Wed Jan 7 12:11:13 2009 +0000

    Add i631x LPC support.
    
    Signed-off-by: Sven Schnelle <svens@stackframe.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 505aaf56e21b94e52cfdeb16b765163f7604e1aa
Author: Marc Jones <marcj303@gmail.com>
Date:   Tue Jan 6 16:45:42 2009 +0000

    The ACPI PSS CPU Pstate table was calculating the frequency incorrectly for
    revF CPUs. The 100MHz/200MHz stepping is already handled in the FID setting
    and doesn't need to be checked to set the fid_multiplier. The multiplier is
    always 100.
    
    Signed-off-by: Marc Jones <marcj303@gmail.com>
    Acked-by: zheng bao <zheng.bao@amd.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fdbb8d860af012718c311aaf14e2f73dfbc0dfeb
Author: Dan Lykowski <lykowdk@gmail.com>
Date:   Tue Jan 6 00:33:30 2009 +0000

    Add support for the Winbond W83627UHG Super I/O.
    
    Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d7db86b6baae440a01e8def0b6e7e97b4adea2a
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Dec 29 09:35:00 2008 +0000

    The SB600 RPR documentation does not mention what to do if SATA_BAR0+6
    is no longer 0xA0 or 0xB0. It simply assumes that will never happen.
    My 500 GB Seagate Barracuda ST3500820AS triggers that corner case on the
    first init after poweron.
    The current code hangs forever with my drive. Fix this by rerunning the
    init sequence after SATA_BAR0+6 is no longer 0xA0 or 0xB0.
    
    Add support for SATA port 2-4 (Primary Slave, Secondary Master,
    Secondary Slave).
    
    If only the 2nd SATA port is connected and the hardware acts strangely
    (contrary to documentation), it will print the error message below and
    continue anyway. The official AMD asm code behaves the same way.
    SATA port 0 status = 0
    No Primary Master SATA drive on Slot0
    SATA port 1 status = 23
    0x6=7f, 0x7=7f
    drive no longer selected after 0 ms, retrying init
    [8 repetitions]
    0x6=7f, 0x7=7f
    drive no longer selected after 0 ms, retrying init
    Primary Slave device is not ready after 10 tries
    
    Activate and improve debug messages for SPEW log level.
    
    Fix some comments.
    
    New log messages look like this:
    PCI: 00:12.0 init
    sata_bar0=3020
    sata_bar1=3060
    sata_bar2=3030
    sata_bar3=3070
    sata_bar4=3000
    sata_bar5=fc309000
    SATA port 0 status = 23
    0x6=a0, 0x7=80
    drive detection not yet completed, waiting...
    0x6=a0, 0x7=80
    drive detection not yet completed, waiting...
    [... 281 repetitions ...]
    0x6=0, 0x7=50
    drive no longer selected after 2820 ms, retrying init
    drive detection done after 0 ms
    Primary Master device is ready after 2 tries
    SATA port 1 status = 23
    drive detection done after 0 ms
    Primary Slave device is ready after 1 tries
    SATA port 2 status = 0
    No Secondary Master SATA drive on Slot2
    SATA port 3 status = 0
    No Secondary Slave SATA drive on Slot3
    
    With this patch, my Asus M2A-VM boots into Linux without problems.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Zheng Bao <zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 098d590d423a38fecaf8a4f1034b4f1710632ca0
Author: Zheng Bao <Zheng.bao@amd.com>
Date:   Wed Dec 24 18:23:00 2008 +0000

    Fix AMD Pistachio implicit declarations in the same way as with AMD
    DBM690T.
    Remove trailing whitespace.
    
    Signed-off-by: Zheng Bao <Zheng.bao@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a2f722abd40f6f946c1e45f2844b6cb4b29c68c7
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Dec 24 17:58:44 2008 +0000

    Fix implicit declarations in the AMD DBM690T target by using the right
    header files.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Zheng Bao <Zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1cced2fe70a3f978a669ba71261406045597f55d
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Dec 23 18:29:50 2008 +0000

    This belongs to changeset: 3840
    
    The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy.
    
    The FADT bootarch flags
    Blacklists MSI for this chipset (maybe not needed)
    Adds modified amdk8_util.asl
    Adds the SSDT table to chain of tables
    Aligns the FACS correctly (this should be done for other boards)
    Adds the _CRS method to Asus M2V-MX SE acpi DSDT.
    Fixes the FACS table length.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da3d5dffbcc9ecc7451e0b82d708e25b48dcfe80
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Dec 23 18:05:24 2008 +0000

    Following patch fixes error code 12 in Windows XP and Vista. The function field of _PRT entry must be always 0xffff (any function).
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-By: Patrick Georgi <patrick@georgi-clan.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 79e532560c63d5ea095aaeb218443964bbceccae
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Dec 23 17:34:15 2008 +0000

    The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy.
    
    The FADT bootarch flags
    Blacklists MSI for this chipset (maybe not needed)
    Adds modified amdk8_util.asl
    Adds the SSDT table to chain of tables
    Aligns the FACS correctly (this should be done for other boards)
    Adds the _CRS method to Asus M2V-MX SE acpi DSDT.
    Fixes the FACS table length.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 33f9633184ddc84151ab3685725d13448cdec232
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Dec 23 17:20:46 2008 +0000

    Handle RS690 quirks for 1 GHz noncoherent HyperTransport.
    The RS690 chipset has a problem where it will not work with 1 GHz HT
    speed unless NB_CFG_Q_F1000_800 bit 0 is set.
    
    Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    Bao, Zheng says:
    As a matter of fact, both 600Mhz and 1Ghz have their own specific
    setting.
    This patch has been tested on dbm690t which HT link works on 800Mhz.
    
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a3c8462dcd0335a0e7f950b9c91af636a727a7a
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Dec 23 17:16:11 2008 +0000

    Remove a unneccessary typedef from acpi_tables.c in the AMD Pistachio
    and DBM690T targets.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Zheng Bao <Zheng.bao@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b96af1ea60cf4f0c7c40901e739959aa1df8acae
Author: Maggie Li <Maggie.li@amd.com>
Date:   Tue Dec 23 02:22:07 2008 +0000

    Fix implicit declarations of pci_read_config32 and pci_write_config32 in
    the SB600 code.
    
    Signed-off-by: Maggie Li <Maggie.li@amd.com>
    Reviewed-by: Zheng bao <Zheng.bao@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c589e5acf953fdfcfa941d8514b2d4c400f74b08
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Dec 23 02:05:55 2008 +0000

    Add verbose debugging output at SPEW level to noncoherent HyperTransport
    initialization.
    
    This patch has helped immensely to track down a bug in 690G ncHT init.
    It depends on my earlier patch which enables CONFIG_USE_PRINTK_IN_CAR
    for all boards using HT. Of course that means ROMCC is not an option
    anymore for those boards, but I don't think that's a big problem.
    Another way to solve this would be #defining printk_spew to nothing.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    Marc says:
    ROMCC doesn't make sense for k8 boards.
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a5436c66bf163a9d9ae6953b78db9d917dd5bd29
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Dec 22 17:41:01 2008 +0000

    Fix implicit declarations of get_bus_conf.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29fbb761ec559b22b7aa9a4b6cb88409545b40c4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Dec 22 16:42:59 2008 +0000

    If you pass a bogus layout file to the -l option flashrom will segfault.
    Fix that by throwing an error instead.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fdc5470bcf21eb6e2f8c720bfc3f436357fe3209
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Dec 22 16:40:45 2008 +0000

    Add another board-enable line for the Kontron 986LCD-M/mITX.
    
    There seem to be at least two versions of the board out there, and the
    subsystem IDs changed between the versions.
    
    Patch successfully tested on hardware.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bfa009f3eb09281d3c74040e6b4a6f420646e0c8
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Dec 22 16:20:55 2008 +0000

    Fix implicit declarations of pci_read_config8 and pci_write_config8 in
    the following files:
    src/mainboard/intel/jarrell/reset.c
    src/mainboard/supermicro/x6dai_g/reset.c
    src/mainboard/supermicro/x6dhe_g2/reset.c
    src/mainboard/supermicro/x6dhe_g/reset.c
    src/mainboard/supermicro/x6dhr_ig2/reset.c
    src/mainboard/supermicro/x6dhr_ig/reset.c
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb30bf8ba2e2db31da454ebd8992611ef32da01c
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Dec 22 16:19:02 2008 +0000

    Fix implicit udelay src/southbridge/nvidia/mcp55/mcp55_aza.c
    Fix imlicit mdelay in src/southbridge/nvidia/mcp55/mcp55_nic.c
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3071acf37091e7217f153f993a27de936061088a
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Dec 22 14:12:08 2008 +0000

    flashrom: Initialize ICH SPI opcodes also for ICH9 and later.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 93159bf752577365e10913257a9edc8d57990a8b
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Dec 22 09:53:24 2008 +0000

    In the process of trying to debug some HT sync problems I added lots of
    debug code to src/northbridge/amd/amdk8/incoherent_ht.c.
    However, printk is not available for all boards at that stage.
    
    I have changed the following boards:
    agami/aruma
    arima/hdama
    asus/a8n_e
    broadcom/blast
    ibm/e325
    ibm/e326
    iwill/dk8s2
    iwill/dk8x
    msi/ms7135
    newisys/khepri
    sunw/ultra40
    tyan/s2850
    tyan/s2875
    tyan/s2880
    tyan/s2881
    tyan/s2882
    tyan/s2885
    tyan/s2891
    tyan/s2892
    tyan/s2895
    tyan/s4880
    tyan/s4882
    
    abuild works fine for all of them.
    agami/aruma needs a Config-abuild.lb which doesn't have fallback and
    normal due to size problems.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da416f89861a681e151d48726bbf0e6699b7ebff
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sat Dec 20 21:07:20 2008 +0000

    Fix dell/s1850 broken in r3822, and prepare it for implicit declaration
    error patch.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb390abb4e5a9476cf0b8b0c8f9a4a0119a265eb
Author: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Date:   Sat Dec 20 19:35:54 2008 +0000

    This adds register map based on NSC PC87392 datasheet. LDN#2 can be
    used for a SIR/FIR device.
    
    Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
    Acked-by: Ulf Jordan <jordan@chalmers.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48994e1633f2b673cc43de9fe2431a31ef613d0c
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Sat Dec 20 04:08:40 2008 +0000

    This adds a mptable for the VIA pc2500e.  I've tested with the devices
    in the VT8237R, and a card interrupting at Pin-A on either PCI slot.
    
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b1fc0ba3fc10a7ad261fcf16f0880fc66711b7a3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Dec 19 14:21:42 2008 +0000

    Add some comments to make it easier to enable onboard VGA for
    different ROM chip sizes (trivial, tested with 256 KB chip).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 734acd59823026055dfb46085d256bb74af57a82
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Fri Dec 19 05:53:30 2008 +0000

    Fix breakage caused by r3822. I should have known not to touch the k8 stuff...
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 40e51fd95a671cde27f98766fedc6c3212ab1d7c
Author: Myles Watson <mylesgw@gmail.com>
Date:   Fri Dec 19 03:55:51 2008 +0000

    This patch fixes the build for asus/m2v-mx_se.  Its hard_reset function is not
    implemented (It just prints "hard_reset not implemented.  FIX ME!" This patch
    defines HAVE_HARD_RESET 1 and adds a #warning hard_reset not implemented.
    
    The net effect is that hard_reset prints something instead of just entering an
    infinite loop.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e562f7258e573e52ab6e81f85f400999c3d9caaa
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Fri Dec 19 03:36:48 2008 +0000

    Fix a LOT of implicit function declarations before they become errors.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 716e5670fe5a2edcb66e587ec5a31377b2099ba8
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Fri Dec 19 03:33:37 2008 +0000

    I honestly have no idea if the previous use of the vt8235's serial functions
    worked or not, but my board doesn't have COM1, and those function don't
    support using COM2, so I've changed auto.c to use the fintek f71805f
    functions, the fintek is the onboard super io. I also cleaned up a
    whitespace issue and unused variable.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fbfdba70fa99d04693d6f3d8d64a89f79ff76d8e
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Thu Dec 18 19:53:11 2008 +0000

    Fix the only implicit declaration before it becomes an error.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 809242a71593e2a1b9661b956f2b952a911b2d4e
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Thu Dec 18 19:37:11 2008 +0000

    Fix implicit declaration in cn700/vt8237 code
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43bb9cddddf90b996e6862d261024c9149fdd59c
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Dec 18 18:24:11 2008 +0000

    This patch gets rid of all the implicit definition warnings for serengeti except get_nodes.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 845a2eba1647b7a88546bda1ad2a587e5312fd77
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Thu Dec 18 02:18:45 2008 +0000

    Add another CPUID to the Via C7's table, the one on my Jetway J7F2.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb069e1f691b6c7eeedfa330df15dc8d51d3e2f9
Author: Zheng Bao <zheng.bao@amd.com>
Date:   Wed Dec 17 02:14:24 2008 +0000

    Add 690G and 690(MT) internal graphics support.
    The device ID of 690G is 0x791E, while the ID of 690M and 690T is 0x791F
    
    This fixes booting on 690G.
    
    Signed-off-by: Zheng Bao <zheng.bao@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc4473051de21eb65b591424efba04eb8ac2fc8a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Dec 15 12:15:49 2008 +0000

    Add initial support for the ASUS P2B-DS (dual-CPU) mainboard.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a8faa2a47935992e4b18ca49cccf921cdbf88e9a
Author: FENG yu ning <fengyuning1984@gmail.com>
Date:   Mon Dec 15 02:32:11 2008 +0000

    * add a generic preop-opcode-pair table.
    
    * rename ich_check_opcodes to ich_init_opcodes.
    
    * let ich_init_opcodes do not need to access flashchip structure:
      . move the definition of struct preop_opcode_pair to a better place
      . remove preop_opcode_pairs from 'struct flashchip'
      . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure
    
    * call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.
    
    * fix a coding style mistake.
    
    Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e65dcfa07a6eb435de302b60adde5ab9ad7ca9cc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Dec 14 00:01:04 2008 +0000

    oops. there went a new mainboard into the tree and i missed it. Add mainboard
    specific changes based on the DBM690T code.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 045c348cf3d700670b5780dd713c2e75436e5b4a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Dec 13 20:51:34 2008 +0000

    Move mainboard specific changes to the coreboot memory table into the
    mainboard specific code. (And add a hook to allow other mainboards do
    a similar thing if required)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42f03e564726fbc85842f30022e4d7c074e8cccc
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Dec 12 03:40:21 2008 +0000

    Improve comments in early SB600 setup, handle non-LPC strapping and
    document verification against the data sheets.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Maggie Li <maggie.li@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8eaafbf25a3c970c38526d35b460dc798ad7c97b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Dec 10 15:42:37 2008 +0000

    Use -O2 and -mcpu=p2 as romcc options for all Intel 440BX boards.
    
    This should hopefully make the "too few registers" error pop up less often.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b3b280448243ad2250232e21d1d41e2cd67d878c
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Dec 10 10:32:05 2008 +0000

    Add 28 flash chips of the MX29 series to the flashrom ID table and
    support the MX29LV040C.
    
    MX29LV040C probe and read support tested by khetzal on IRC.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 19ead962c4c0331de6bd9624843f8a80608bff60
Author: Maggie Li <maggie.li@amd.com>
Date:   Tue Dec 9 21:52:42 2008 +0000

    AMD PISTACHIO mainboard support.
    
    The following ACPI features are supported:
     1. S1, S4, S5 sleep and wake up (by power button).
     2. Thermal configuration based on ADT7475.
     3. HPET timer.
     4. Interrupt routing based on ACPI table.
    
    Signed-off-by: Maggie Li <maggie.li@amd.com>
    Reviewed-by: Michael Xie <michael.xie@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b643cea5a3cd75f9e7ce456ba0ab4271fba2c1a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Dec 9 16:36:12 2008 +0000

    Add (parts of the) support for multiple DIMMs on the Intel 440BX chipset.
    
    This is tested on hardware with four 128MB DIMMs and works ok, _iff_
    you also fix additional registers (e.g. DRB, RPS, ...) for your setup.
    This requirement will be eliminated in another upcoming patch (i.e. all
    of the required settings will be auto-detected).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17da8d706f83d00dc962ffd37ca31be6e88b4b65
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Dec 8 23:51:45 2008 +0000

    Kill obsolete and misplaced comment.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a07f703ec89d5be98d7e47c49264a3b8184d956
Author: FENG yu ning <fengyuning1984@gmail.com>
Date:   Mon Dec 8 18:16:58 2008 +0000

    Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI
    configuration is locked down.
    
    Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 60e7eebf96e6d53913b44b95cf83fa03c33e48c7
Author: FENG yu ning <fengyuning1984@gmail.com>
Date:   Mon Dec 8 18:15:10 2008 +0000

    Breaks chip info into multiple lines.
    
    Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit baada5efaf7d53dc738b5fa2cefed1293ac45173
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Dec 6 01:37:09 2008 +0000

    flashrom: Display test status in -L chip listing
    
    Looks like this:
    
    Supported flash chips:          Tested OK operations:   Known BAD operations:
    
    AMD Am29F002(N)BB
    AMD Am29F002(N)BT               PROBE READ ERASE WRITE
    AMD Am29F016D
    AMD Am29F040B                   PROBE READ ERASE WRITE
    AMD Am29LV040B
    Atmel AT45CS1282                                        READ
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce00f1d12c5d992c979e97e926e4e1e521122494
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Dec 5 22:38:18 2008 +0000

    Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de>
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f82a07730d033f0c168dd13a7fa5d4d086016376
Author: Maggie Li <maggie.li@amd.com>
Date:   Fri Dec 5 18:38:57 2008 +0000

    The TALERT of ADT7461 should be pull back high if the temperature is within the limit. It is done by reading the register whose device address is 0xC. It is not trivial as it looks.
    
    
    
    Signed-off-by:  Maggie Li <maggie.li@amd.com>
    Reviewed-by:    Joe Bao <zheng.bao@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c73fca35e273f827ddbffa0719d2edde5c62e7e6
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Dec 5 14:15:17 2008 +0000

    Add initial support for the NEC PowerMate 2000 board.
    
    See details at:
    http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/
    
    Thanks to Quentin RAMEAU <quentin.rameau@gmail.com> for providing the
    required information and for testing the patch.
    
    This boots into a Linux console just fine.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24788351dc9c81edef9f721710302b1681766126
Author: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Date:   Fri Dec 5 11:58:43 2008 +0000

    flashrom: Add AMD SB700 flash enable
    
    This patch adds SB700 support to flashrom. The code for enabling the flash
    rom is the same as for SB600. It was tested (read, write, verify) with an
    ASUS M3A-H/HDMI which contains a Macronix MX25L8005.
    
    Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a0be5193e6875d2003603d79bd29b272425946c
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Dec 5 11:56:57 2008 +0000

    flashrom: Fix compilation of r3797 with gcc-4.3.2
    
    Thanks to Niels Ole Salscheider for the problem report.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b4b56e669b910d8595eae6af21b3e86dc3d26c9d
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Dec 5 02:22:30 2008 +0000

    flashrom: Check if erase succeeds and exit with error on failure.
    
    flashrom used to exit 0 even if erase failed. Not anymore.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e94e2e3d406af2b9c45fba2ecc16643307213c72
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Thu Dec 4 23:42:36 2008 +0000

    This belongs to changeset 3795.
    
    The patch changes the LDTSTOP length as well mostly default content of 0xec,
    0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.
    
    Furthermore this fix for powernow may not work on CPUs hit by errata #181.
    Workaround should be implemented. The powernow may not work on pre-A2 revisions
    of VT8237S silicon, revision reg is unknown.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31e52e61aa4cbe3065ea86732a689ab4cf58984f
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Thu Dec 4 23:37:12 2008 +0000

    The patch changes the LDTSTOP length as well mostly default content of 0xec,
    0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.
    
    Furthermore this fix for powernow may not work on CPUs hit by errata #181.
    Workaround should be implemented. The powernow may not work on pre-A2 revisions
    of VT8237S silicon, revision reg is unknown.
    
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1162f25a49e8f39822123d664cda10fef466b351
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Dec 4 15:18:20 2008 +0000

    Patch to util/inteltool:
    * PMBASE dumping now knows the registers.
    * Add support for i965, i975, ICH8M
    * Add support for Darwin OS using DirectIO
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fcf9be3b9305cfddaf74594fcaec4d6f23541154
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Dec 4 00:58:10 2008 +0000

    Add RDID/REMS IDs for the following flash chips:
    
    SST_25VF512A_REMS
    SST_25VF010_REMS
    SST_25VF020_REMS
    SST_25VF040_REMS
    SST_25VF040B_REMS
    SST_25VF080_REMS
    SST_25VF080B_REMS
    SST_25VF032B_REMS
    SST_26VF016
    SST_26VF032
    W_25X16
    W_25X32
    W_25X64
    
    Straight from the data sheets.
    
    The REMS IDs help in case the RDID opcode is unavailable (due to opcode
    lockdown) or unsupported by the chip.
    
    Some day, we need to pair probe functions together with IDs. Multiple
    pairs can exist per chip and duplicating chip definitions does not
    really make sense.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd5a2df876bb28e7643c4db98a4defc8e394eb07
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Dec 3 23:36:48 2008 +0000

    flashrom: gcc thinks base could be used uninitialized, so shut it up.
    
    Bug from r3791.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9602d1e8286ec17d42452b0a5ca5dc2d20c24d6e
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Dec 3 21:39:56 2008 +0000

    flashrom: Fix bug in r3790
    
    If flashbase was set before probe_flash() it would only ever be used once, for
    the very first flash chip probe.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d53f3e75468239435ec7595bb93abca3083e7299
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Dec 3 21:24:40 2008 +0000

    Replace #ifdefs for sc520 systems by run time probing.
    
    fixes #109
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9b500f456bff123e0efc24f561183b937b66042
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Dec 2 12:26:17 2008 +0000

    build_opt_tbl:
    make sure the temporary files are created in the same directory as the
    target files so they can be rename()d. This fixes a compilation issue on
    machines with the build directory living on another partition than /tmp.
    Pretty trivial.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 806def8cac0a2871f937e8a8c83ae07bc2996e2b
Author: Joe Bao <zheng.bao@amd.com>
Date:   Tue Dec 2 02:56:38 2008 +0000

    I missed the svn add on r3787. These are the additional files.
    
    Add AMD dbm690t ACPI support.
    The following ACPI features are supported.
    1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse).
    2. AMD powernow-k8 driver.
    3. Thermal configuration based on ADT7461.
    4. IDE timing settings.
    5. HPET timer.
    6. Interrupt routing based on ACPI table.
    
    
    Signed-off-by:  Joe Bao <zheng.bao@amd.com>
    Reviewed-by:    Maggie Li <maggie.li@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7c3d3b20279d07302a55df26e6e1be6cc040f988
Author: Joe Bao <zheng.bao@amd.com>
Date:   Mon Dec 1 19:52:54 2008 +0000

    Add AMD dbm690t ACPI support.
    The following ACPI features are supported.
    1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse).
    2. AMD powernow-k8 driver.
    3. Thermal configuration based on ADT7461.
    4. IDE timing settings.
    5. HPET timer.
    6. Interrupt routing based on ACPI table.
    
    
    Signed-off-by:  Joe Bao <zheng.bao@amd.com>
    Reviewed-by:    Maggie Li <maggie.li@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 40d46ba383de03ebb413ab0f3ac3af8301f5f813
Author: Joe Bao <zheng.bao@amd.com>
Date:   Mon Dec 1 19:49:57 2008 +0000

    Add AMD rs690 VID DID reporting and some minor cleanups.
    
    Signed-off-by:  Joe Bao <zheng.bao@amd.com>
    Reviewed-by:    Maggie Li <maggie.li@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 164463c551367d0ae3a9f8e5a1719200af99b060
Author: Joe Bao <zheng.bao@amd.com>
Date:   Mon Dec 1 19:37:21 2008 +0000

    Add AMD sb600 HPET setup and some minor cleanups.
    
    Signed-off-by:  Joe Bao <zheng.bao@amd.com>
    Reviewed-by:    Maggie Li <maggie.li@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Marc Jones <marcj303@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a51e50582b65bb6ac54e8923470807b5975c6e1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Dec 1 14:18:57 2008 +0000

    The Winbond Super I/O chips have another indirection of registers. The
    hwmon has generic registers and banked registers, mostly temperature
    handling, and SMI/GPIO stuff.
    
    Not all LDNs are switched via register offset 0x07, make it a parameter.
    
    Add support for dumping the hardware monitor of Winbond W83627THF/THG
    parts with the -e option.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b4eb4fb6b06878c25a43458ff11cd3939d97c60e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Nov 30 14:52:46 2008 +0000

    ok, another attempt to the build_opt_tbl problem:
    - create temp files and move them afterwards
    - remove dummy option -b
    - fix usage
    - drop implicit creation of .c file if no --option is specified.
    
    Now let's see if this fixes the issue. :-) We don't want to take 24s
    instead of 6s to build an image reliably (Yes, yes, I know Tiano takes
    over 20 minutes)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 70a1f735a97cc0f697e8f9984a944a8da9e630c2
Author: Jason WangQingpei.wang <Jason WangQingpei.wang@amd.com>
Date:   Sat Nov 29 15:07:15 2008 +0000

    Copyright update by Jason Wang for freshly written sb600 code.
    
    Signed-off-by:  Jason Wang<Qingpei.wang@amd.com>
    Reviewed-by:    Joe, Bao <Zheng.Bao@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b30d5d298b53f7015e63096652f69cf4edcff07
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Nov 28 23:47:55 2008 +0000

    Declare special commands to support the Atmel AT25F512A.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f86f1fe961f661a0c892bdd6de94007cc1466c01
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Nov 28 23:45:27 2008 +0000

    If a chip has any TEST_BAD_* flag set, we don't even list the
    unsupported functions, giving the user the impression that the
    unsupported functions are tested.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f22ce41840ae966a6f465e90c8f05aed9ae5ef6b
Author: Jason Wang <Qingpei.Wang@amd.com>
Date:   Fri Nov 28 21:36:51 2008 +0000

    Add support for the AMD/ATI SB600 southbridge SPI functionality.
    
    This has been tested by Uwe Hermann on an RS690/SB600 board.
    
    Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
    Reviewed-by: Joe Bao <zheng.bao@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4ed326be5d7dec9ee16190847ea0b9f42117fe1a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 28 12:09:17 2008 +0000

    This patch from Ralf Grosse Boerger makes debugging more comfortable.
    With this patch it's possible to
    
    - determine the according source code line for each asm statement
      (objdump -dS)
    - determine the source code file for each asm statement
      (objdump -ddl)
    
    This isn't exactly trivial because cache_as_ram_auto.c gets compiled to
    assembly and converted by a perl script afterwards.
    
    This patch solves the problem
    - by extending cache_as_ram_auto.inc with debug information and line
      numbers
    - by correcting the perl calls (".text" --> "\.text")
    - by creating a disassembly with source code and line numbers.
      (ctr0.disasm and
      coreboot.disasm)
    
    There's one minor downside to the patch: A complete abuild run takes up
    around 1.6G instead of about 700MB now. But I'm sure this is quite
    reasonable for the benefits.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    
    Please commit while this is being worked out.
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 38bee3c8b6ca49031b30e3a8f974fe0690560de3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 28 11:56:27 2008 +0000

    This patch fixes the ugly race condition created through build_opt_tbl
    running twice at the same time, overwriting its output files. This caused
    a depending rule to produce an object file with no symbols in it.
    
    This should silence up the regularly happening build failure messages on
    the mailing list since we moved to the newer, much faster server.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d95e43cc8f66203a8287f8a7c54ecc3ab74436e6
Author: Jason Wang <Qingpei.Wang@amd.com>
Date:   Fri Nov 28 05:40:27 2008 +0000

    Add SST25VF080B flash chip support.
    This is the first chip which uses the infrastructure for alternative
    erase commands, namely spi_chip_erase_60_c7().
    
    Signed-off-by:  Jason Wang <Qingpei.Wang@amd.com>
    Reviewed-by:   Joe Bao <zheng.bao@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f24cbc0833fd923238f516dd8964660807ef789
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Nov 28 01:25:00 2008 +0000

    Flashrom already has the following probe functions:
    - probe_spi_rdid with opcode 0x9f, usually 3 bytes ID
    - probe_spi_res with opcode 0xab, usually 1 byte ID
    We are missing the following probe function:
    - probe_spi_rems with opcode 0x90, usually 2 bytes ID
    
    RDID provides best specifity (manufacturer, device class and device) and
    RES is supported by quite a few old chips. However, RES only returns one
    byte and there are multiple flash chips with different sizes on the
    market and all of them have the same RES ID.
    REMS is from the same age as RES, but it provides a manufacturer and a
    device ID. It is therefore on par with the probing for parallel flash
    chips and specific enough.
    
    The order in which chips should be detected is as follows:
    1. RDID
    2. REMS
    3. RES
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c88733c0213728b483d5832585823632636f0ebb
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Nov 27 22:48:48 2008 +0000

    The existing check in probe_spi_res() was right for SPI controllers
    which support all commands, but may not exist.
    For controllers which support only a subset of commands, it will fail in
    unexpected ways. Even if a command is supported by the controller, it
    may be unavailable if the controller is locked down.
    
    The new logic checks if RDID could be issued and its return values made
    sense (not 0xff 0xff 0xff). In that case, RES probing is not performed.
    Otherwise, we try RES.
    There is one drawback: If RDID returned unexpected values, we don't
    issue a RES probe. However, in that case we should try to match RDID
    anyway.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: FENG yu ning <fengyuning1984@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1683cef9961efb3a8b843fce532da5ae640aac0b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 27 00:47:07 2008 +0000

    Remove the unnecessary memctrl[] indirection, 440BX only has one
    memory controller.
    
    Also, drop some unused '#if 0' code.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 544dca4195a6fb77286299bf42d4db5813dc28ac
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed Nov 26 19:46:27 2008 +0000

    Increase the qemu rom size (non-LAB) to 512KB so that grub2 fits.
    
    This is a trivial patch.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 58edecdc1e0c7e811c02eb2f3f9c30fa23d4890d
Author: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Date:   Tue Nov 25 16:41:21 2008 +0000

    libpayload: Fix immediate rebuild after a clean
    
    After running make clean, most of build/ directory gets deleted.
    It is (re)created in the "prepare" make target, but that was libpayload.a
    dependency after the $OBJS, while OBJS building already needs to dump its
    created object files there.
    Simply rearrange the make target dependencies to get at least "make clean;make" working.
    
    Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0924dee124acfd1f8ae96685720c7a4af068e843
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Nov 25 02:03:16 2008 +0000

    msrtool: Use libpci to let system and target probes find PCI devices.
    
    And some more notes in TODO.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef8ea01c8c6638e4cf3a9ed32857e14c3f6e7cbc
Author: Tero O Peippola <xeropp@gmail.com>
Date:   Mon Nov 24 20:23:23 2008 +0000

    Add support for 32Mbit SPI flash SST25VF032B. Tested on gigabyte m57sli.
    
    File util/flashrom/flash.h already had correct ID for that part.
    
    Signed-off-by: Tero O Peippola <xeropp@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit db8c0abefce8900c52b304d25878abf835cb5aac
Author: Jordan Crouse <jordan@cosmicpenguin.net>
Date:   Mon Nov 24 17:54:46 2008 +0000

    [PATCH] libpayload: rename config.h to libpayload-config.h
    
    Rename the generated config file to libpayload-config.h to differenciate
    it from other config.h files.  Move the default location of the file to
    $(src)/include so that LIBPAYLOAD_PREFIX= users can access the file
    without staging it.
    
    Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc9db9dfa00bc31f7c85cdd7bebb458f641f4b06
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Nov 22 18:29:44 2008 +0000

    msrtool: Very small fixes I made after sending out the rc1 tarball.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dad1e3091f2d9a3fc03b9ca83c2990e23b4ea32c
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Nov 22 17:13:36 2008 +0000

    msrtool: Release Candidate 1
    
    msrtool can decode MSRs and print the value of every field in human
    readable form. It can also be used to save a set of MSRs to a file,
    and at a later time compare the saved values with current values in
    hardware.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d24fe7e80ede60847afaa2ae30692b072ea06eda
Author: Elia Yehuda <z4ziggy@gmail.com>
Date:   Fri Nov 21 17:14:40 2008 +0000

    i810: Add support for multiple DIMMs, both single-sided and double-sided,
    as well as most (all?) combinations thereof.
    
    Drop some unused code, the unused row_offset variable, and obsolete comments.
    Also, fix a typo (thanks to Stefan Reinauer for noticing).
    
    This is tested on the MSI MS-6178 with a number of different DIMM
    combinations and so far all of them worked fine.
    
    Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4cf5ecf39d58751cbddbbeb3133886acaecc9550
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 20 23:18:10 2008 +0000

    Get rid of the unnecessary indirection by 'struct mem_controller' for the
    Intel 810 chipset (and all boards using it). This isn't required for this
    chipset as there's only one memory controller.
    
    This also helps a lot with romcc register usage, you should see the dreaded
    "too few registers" less often.
    
    Build-tested with all three boards using the Intel 810 chipset.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 76c6c95c1ee3d231ee861afba8dbc341f4c02e07
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Nov 20 20:07:38 2008 +0000

    fix Config-abuild.lb for all targets that need a failover image and
    don't have one (by fixing it for amd/serengeti_cheetah and copying the
    same file to all other broken targets)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3763 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c558d35cbdc746db979ab9510a93a33d955a9d5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Nov 20 19:26:16 2008 +0000

    OK, people, watch this.
    
    This is a school book example of why trivial indent patches just suck
    big time.
    
    This error was introduced by a trivial self-acked indent patch and was
    never detected (because of a missing Config-abuild.lb)
    
    So, indenting the code for no reason can make it a lot worse (read:
    break it) instead of improving it.
    
    I ask everyone to keep this in mind when going on indent-frenzy again.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86c9b8839217675cb1cc4830aa7d758864ee43f9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 19 13:42:14 2008 +0000

    Coding-style and whitespace fixes (also to make the code more similar
    the Lippert Cool SpaceRunner LX which is already in svn).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f31ca16793ca2898e5983a12bdd706bfdd0d0efe
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Wed Nov 19 12:19:09 2008 +0000

    Add support for the LiPPERT Cool RoadRunner-LX embedded PC board:
    - PC/104+ form factor
    - AMD Geode-LX CPU/northbridge
    - AMD CS5536 southbridge
    - ITE IT8712F superio
    http://www.lippert-at.com/index.php?id=408
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ab91d875b3572a1c9b50e2035edf996aa8727da
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 18 12:02:03 2008 +0000

    i810: Add some more comments, and especially add a list of tested BUFF_SC
    values for different DIMM configurations. This should be converted to a
    table or code later on and actually be used for BUFF_SC.
    
    Many thanks to Elia Yehuda <z4ziggy@gmail.com> for testing and collecting
    the table entries.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c0702b89b2e71f29f828c54c67f2f6bff89d5c1
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Nov 18 00:43:14 2008 +0000

    Currently flashrom assumes every vendor BIOS shares our view about which
    SPI opcodes should be placed in which location. Move to a less
    optimistic implementation and actually use the generic SPI read
    functions. They're useful for abstracting exactly this stuff and that
    makes them the preferred choice.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7cb70d9abd5423182b95c815d50ad1979519a5f4
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Nov 18 00:41:02 2008 +0000

    Check for failed SPI command execution in flashrom. Although SPI itself
    does not have a mechanism to signal command failure, the SPI host may be
    unable to send a given command over the wire due to security or hardware
    limitations. The current code ignores these mechanisms completely and
    simply assumes almost every command succeeds. Complain if SPI command
    execution fails.
    
    Since locked down Intel chipsets (like the one we had problems with
    earlier) only allow a small subset of commands, find the common subset
    of commands between the chipset and the ROM in the chip erase case. That
    is accomplished by the new spi_chip_erase_60_c7() which can be used for
    chips supporting both 0x60 and 0xc7 chip erase commands.
    
    Both parts of the patch address problems seen in the real world. The
    increased verbosity for the error case will help us diagnose and address
    problems better.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9648351d75af014e257d743a1ea0360b7119c3e7
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Nov 18 00:36:26 2008 +0000

    Implement read support for the following Atmel chips:
    AT25DF021
    AT25DF041A
    AT25DF081
    AT25DF161
    AT25DF321A
    AT25DF641
    AT25F512B
    AT25FS010
    AT25FS040
    AT26DF041
    AT26DF081A
    AT26DF161
    AT26DF161A
    AT26DF321
    AT26F004
    
    I double-checked the data sheets and am confident this will work.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b74fbc61225ace389e97e871cd6db536bd5394eb
Author: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Date:   Mon Nov 17 15:31:56 2008 +0000

    flashrom: SST39VF020 TEST_OK_ PROBE READ ERASE WRITE
    
    Tested fully on a ThinCan DBE61A
    
    Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef3f7e38eae30f733039b06df7da090bc4a0ed67
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sat Nov 15 13:55:43 2008 +0000

    The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
    The AT45 series SPI chips are DataFlash EEPROMs which means they have
    odd (non-power-of-two) sector sizes, but some of the DataFlash chips can
    be configured or ordered with power-of-two sector sizes.
    
    Add probe support for the following Atmel SPI chips:
    AT25DF021
    AT25DF041A
    AT25DF081
    AT25DF161
    AT25DF321A
    AT25DF641
    AT25F512B
    AT25FS010
    AT25FS040
    AT26DF041
    AT26DF081A
    AT26DF161
    AT26DF161A
    AT26DF321
    AT26F004
    AT45CS1282
    AT45DB011D
    AT45DB021D
    AT45DB041D
    AT45DB081D
    AT45DB161D
    AT45DB321C
    AT45DB321D
    AT45DB642D
    
    Add an explanation why the following chips can't be probed:
    AT45BR3214B
    AT45D011
    AT45D021A
    AT45D041A
    AT45D081A
    AT45D161
    AT45DB011
    AT45DB011B
    AT45DB021A
    AT45DB021B
    AT45DB041A
    AT45DB081A
    AT45DB161
    AT45DB161B
    AT45DB321
    AT45DB321B
    AT45DB642
    
    Add the ID, but no probing function for this chip:
    AT25F512A
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
    Tested-by: Andriy Gapon <avg@icyb.net.ua>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 385e90ad1c305473ff34c22199f8cdf141669027
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Nov 14 19:25:37 2008 +0000

    Rename LinuxBIOS strings and filenames to coreboot.
    
    Also, use the more generic and buildrom-friendly '../payload.elf' as
    the default payload location.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e35d5e3fa229b438fff533f0066b6b384a116a1f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 14 13:43:26 2008 +0000

    drop dead code in sb600 hda
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a04b107c6a0f536bf6e601f3ce075a4968d25c32
Author: Marc Jones <marcj303@yahoo.com>
Date:   Wed Nov 12 20:38:51 2008 +0000

    Add another AM2 cpuid to the name string. Also, colapse the cases for duplicate strings to save some space.
    
    Signed-off-by: Marc Jones <marcj303@yahoo.com>
    Acked-by: Chris Lingard <chris@stockwith.co.uk>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebb73f2dcf960c9945421eecf97673f726b5349f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 12 19:08:58 2008 +0000

    Add detection support for ITE IT8228E, IT8711F, IT8722F, IT8761E,
    IT8780F, and Fintek F71863FG.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c1f404fc0ee18ad3e42de46acdd3b6422ab69ba9
Author: Robert Millan <rmh@aybabtu.com>
Date:   Tue Nov 11 23:41:08 2008 +0000

    Signed-off-by: Robert Millan <rmh@aybabtu.com>
    Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39ebf2f06855343793fa5635d2c7b26ee2f1a7b8
Author: Robert Millan <rmh@aybabtu.com>
Date:   Tue Nov 11 23:36:12 2008 +0000

    Signed-off-by: Robert Millan <rmh@aybabtu.com>
    Acked-by: Jordan Crouse <jordan@cosmicpenguin.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3bb2628c7b36d0b6cb21bc36ea1103ce812666f9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Nov 11 21:57:20 2008 +0000

    Thanks to Uwe Hermann for spotting this typo.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1ec5094390f6d78929cc12ed31860a7c8e2c459c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 11 21:10:07 2008 +0000

    Add support for the Winbond W83627DHG Super I/O.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 81af3d4a0077f354029e92aea71eb737d20f6a3e
Author: Robert Millan <rmh@aybabtu.com>
Date:   Tue Nov 11 20:20:54 2008 +0000

    [PATCH] coreboot-v2: Add multiboot support
    
    Signed-off-by: Robert Millan <rmh@aybabtu.com>
    Acked-by: Jordan Crouse <jordan@cosmicpneguin.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5cb4d9d663d2ed5b8225dbbb00507637016d3fc4
Author: Jordan Crouse <jordan@cosmicpenguin.net>
Date:   Tue Nov 11 19:53:42 2008 +0000

    [PATCH] coreinfo:  Add multiboot parsing support
    
    Rename the "coreboot" menu "firmware", and add a module to parse
    the multiboot table.  For now, just parse memory, but it can be
    expanded as needed.
    
    Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c6e4333c4ef8a86e70e14fcff57a5747339b165
Author: Jordan Crouse <jordan@cosmicpenguin.net>
Date:   Tue Nov 11 19:51:14 2008 +0000

    [PATCH] Add sysinfo_have_multiboot function
    
    Add a new infrastructure for returning system information to payloads.
    First up - a pointer to the multiboot table.
    
    Signed-off-by: Jordan Crouse <jordan@cosmicpenguin.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b6c527322259d6ae7878411ca26ee6dd9374b3c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 11 14:26:03 2008 +0000

    Always enable serial before SMBus (or as early as possible), as the SMBus
    enable may do printk()s which result in a 2 minute delay on some boards.
    
    Fix this on all boards which currently do smbus_enable() before enabling
    the serial console.
    
    Thanks to Elia Yehuda <z4ziggy@gmail.com> for tracking this bug down.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 779b3e312901d4ef533d5cc13f551bab2823de08
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Nov 10 15:43:37 2008 +0000

    Merge some parts of the i945 review (trivial):
    
    * fix \r\n occurence in i945 code
    * drop early TOLUD write
    * fix 16bit BCTRL1 access
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb9f35d36b69551bfe0d9038c6fe9594a575fa67
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Nov 10 13:52:14 2008 +0000

    cosmetic update for getpir.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a163729862c588c8203da41208dfa57b0b0da088
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 9 10:57:26 2008 +0000

    i945.h: Add some more comments, align data for better readability (trivial).
    
    Also, add missing C1DRA2 #define (as per public datasheet).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 160361a1dfcee61c546f0039bbd235f3d45b2619
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sat Nov 8 01:51:32 2008 +0000

    The POST_CODE macro had the outb() argument order backwards.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f27a3eba4dbe35a825a6fcbe95a955cfdca5dac6
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Nov 8 01:39:12 2008 +0000

    flashrom: SST39SF040 TEST_OK_ PROBE READ ERASE WRITE
    
    Per report from Mario Rogen. Thanks!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c95338f35b4446d0945b58c2b06c51dfdcd8ef7
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Sat Nov 8 00:58:16 2008 +0000

    Update bayou to use ACS_ macros for line drawing characters.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c1c207f6277bb29d92b001abb93a9cd63a46e500
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 6 22:38:31 2008 +0000

    Re-add "based on" lines.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 65ebc791c1eb91fc49ee7979f194f2021bb4fd14
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 6 22:24:05 2008 +0000

    Drop #defines for registers that are not existant on the ICH7.
    Also, fix BIOS_CNTL, which is 0xdc on ICH7.
    
    Build-tested with kontron/986lcd-m.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 556801eb61b63e1476af162342b2aad0c9402cad
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 6 22:23:05 2008 +0000

    The enable_hpet() code in intel/i82801gx will not work with the
    ICH7 southbridge (but it might work with ICH4/ICH5 or so).
    
    The ICH7 needs a different init code. Drop the non-working code for now.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 176e88e961e5e5ca950c42e1af33ed0109ea3946
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Nov 5 22:54:36 2008 +0000

    The ST M25P16 chip has been confirmed to work fine for probe, read,
    erase and write by Stéphan Guilloux.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aad6502d8a30cb9acf2153efad2c5bf4e5001a7b
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Nov 4 12:11:12 2008 +0000

    Add support for 8 new chips to flashrom and fix up 2 existing chips
    as well.
    Replace age-old TODO comments with real explanations.
    
    Fixed chips:
    Fujitsu MBM29F400TC (ID definition)
    Macronix MX29F002T (chip name)
    
    New chips:
    Fujitsu MBM29F004BC
    Fujitsu MBM29F004TC
    Fujitsu MBM29F400BC
    Macronix MX25L512
    Macronix MX25L1005
    Macronix MX25L2005
    Macronix MX25L6405
    Macronix MX29F002B
    
    Straight from the data sheets, compile tested only.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98afd9b75b92c96c67bb02a0ec104c42c28aaade
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Mon Nov 3 23:16:00 2008 +0000

    Fix compile errors if CONFIG_FS_PAYLOAD=1:
    
    Compile error in filo.c if AUTOBOOT_DELAY=0. Replace
    #ifndef AUTOBOOT_DELAY
    with
    #if !AUTOBOOT_DELAY
    which should work for both the #undef and the =0 case.
    
    In ext2fs.c, fat.c
    #if ARCH == 'i386'
    results in a compile warning: "multi-character character constant" and
    the condition ARCH == 'i386' is mis-evaluated as FALSE, eventually
    choking the assembler on a PPC instruction. Change it to
    #ifdef __i386
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 632f86515a132b51b035794e0ba21b8a21eacd15
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Mon Nov 3 22:58:56 2008 +0000

    Add the missing I/O resources for IT8712F GPIOs. (E.g. some LiPPERT
    boards need them to switch the com ports from RS232 to RS485.) The PnP
    resources should prevent other devices from being mapped at the same
    spot, even if no OS driver actively uses them.
    
    The IT8712F manual makes it look like PNP_IO1 had a size/granularity of
    1 byte, but that must be a mistake. The Simple-I/O resource has a size
    of 5 bytes (1 for each GPIO set 1-5) and trying different addresses
    reveals a granularity of 8.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cc49b21f85c831d299966b890de42cc348d0fff
Author: Marc Jones <marc.jones@amd.com>
Date:   Mon Nov 3 22:46:27 2008 +0000

    Set asus/a8v-3_se to use printk in CAR. (trivial)
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c87ddd91c7b4f50d5d2dd4e8b0370b50d62a7367
Author: Marc Jones <marc.jones@amd.com>
Date:   Mon Nov 3 21:39:03 2008 +0000

    Update K8 FID/VID setup. Add support for 100MHz FIDs (revG).
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fbeba2313f104b0dd329fc30bfc5e6182b85cda0
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Nov 3 16:55:22 2008 +0000

    Move the default payload to be more buildrom friendly.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4ef0541dbd198defc2fcd95c2e412d828dafe26
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Nov 3 04:08:35 2008 +0000

    modify pirq tables for epia-cn.
    
    Not tested, builds, derived from getpir. Definitely better than what was there.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Bari Ari <bari@onelabs.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f31f110319418cb7c63132090f7970e3425862a
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Nov 3 00:20:22 2008 +0000

    Dump ICH8/ICH9/ICH10 SPI registers in flashrom.
    This helps a lot if we have to track down configuration weirdnesses.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6287e2e7aa2c0459a9fcb0af8a5fb1f4d5bca4f8
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Nov 3 00:02:11 2008 +0000

    Add additional SPI sector erase and chip erase command functions to
    flashrom. Not all chips support all commands, so allow the implementer
    to select the matching function.
    Fix a layering violation in ICH SPI code to be less bad. Still not
    perfect, but the new code is shorter, more generic and
    architecturally
    more sound.
    
    TODO (in a separate patch):
    - move the generic sector erase code to spi.c
    - decide which erase command to use based on info about the chip
    - create a generic spi_erase_all_sectors function which calls the
    generic sector erase function
    
    Thanks to Stefan for reviewing and commenting.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d22ef49783c60297f775f3c0136ad0d3e36ab495
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Nov 2 19:51:50 2008 +0000

    Drop nr/opcode_index parameter from run_opcode and search the opmenu for the opcode instead.
    This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54c5276c3aa9496b385097f314a6ee9abd8072d0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 2 17:48:20 2008 +0000

    Get the lzma/ directory from v3 via svn:externals, for use with Bayou.
    
    Also, fix a few Makefiles regarding lzma stuff and 'make clean' behaviour.
    
    Add bayou.xml.example which users can use as a starting point.
    
    Bayou does compile fine now (if you build ../libpayload) before.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7eb845e815924984b301aaf674b090cde28c1c6a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 2 17:01:06 2008 +0000

    Import a slightly modified Bayou version into svn. This is based
    on the last snapshot posted by Jordan Crouse. This commit is long
    overdue.
    
    Changes by me include:
    
     - Rename 'utils' to 'util' for consistency with our other projects.
    
     - Move the main code out of src/* into the top-level directory.
    
     - Add missing license headers to the following files:
       Makefile, pbuilder/liblar/Makefile, util/pbuilder/Makefile.
    
     - Dropped the util/pbuilder/lzma completely. I'm working on reusing
       the lzma/ dir from v3 via svn:externals. Alas, this also means
       that Bayou won't yet compile out of the box.
    
     - Coding-style and white-space fixes (indent) for all files.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 91df5619dbb7d2064f9947f2fbc56477f7b707c3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 2 14:33:51 2008 +0000

    Trim down the list of southbridges supported by the i82801xx driver
    to only a set of reasonably similar ones, namely (for now) ICH0* - ICH6*,
    and C-ICH.
    
    All later ICH* southbridges (ICH7-ICH10) are _very_ different and were surely
    not working with this driver anyway (and there's no chance to support
    them reasonably with this driver without ending up in #ifdef hell).
    
    ICH7 now has an extra driver in svn, whether ICH8-ICH10 are similar
    enough to be supported by that ICH7 driver remains to be seen.
    
    This patch was informally acked by Stefan Reinauer
    <stepan@coresystems.de> on IRC.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a9e23c5868dff0771ce741d3f93b8c8022daf90
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sun Nov 2 14:25:11 2008 +0000

    Add support for the ST M50FW002 chip to flashrom. Identification only,
    erase/write are not implemented.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    tested and
    Acked-by: Elia Yehuda <z4ziggy@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d9a12f65df48bee260c522c1c2d32343cc7fd73
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Nov 2 11:11:40 2008 +0000

    inteltool 82945G/GZ/P/PL Support (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5d7a1c844e56bc9dd101c8a900bf3284b633d04b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 31 18:41:09 2008 +0000

    Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines.
    
    Build-tested on kontron_986lcd_m.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50f37b0f9bc29e7522acabb4bb7c881423f3c24e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 31 05:40:04 2008 +0000

    Move the nvramtool manpage to section 8 (as it's only really usable as root),
    as we've done with the superiotool and flashrom manpages, too (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 70c793ce2844e45779f9307332aa90ab17cfdf63
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu Oct 30 22:13:51 2008 +0000

    Leave room for ROM growth and for the payload. (trivial)
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 51c7838cb06b18738c50f8cab8b7e7eacbaa4cba
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu Oct 30 21:31:54 2008 +0000

    Increased the size of the failover and normal ROM_IMAGE_SIZE so abuild will
    pass with toolsets that compile larger images. (trivial)
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 429d6b66928119df0ba0c69d7f1232e8c2b904da
Author: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Date:   Thu Oct 30 20:17:11 2008 +0000

    Here's a patch towards r3690 upping the ROM size for the S2912 Fam10 target to 1M.
    Both regular and abuild images have been boot tested successfully.
    
    Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit edc7ef2b76f8d49d1eeae9a111bdcae3f288d6f9
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Thu Oct 30 19:34:44 2008 +0000

    Add support for the LiPPERT Cool SpaceRunner-LX embedded PC board:
    
     - PC/104+ form factor
     - AMD Geode-LX CPU/northbridge
     - AMD CS5536 southbridge
     - ITE IT8712F Super I/O
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a4bf9886ac9990206ac64fd09890bca433d9bd8
Author: Andriy Gapon <avg@icyb.net.ua>
Date:   Thu Oct 30 15:41:39 2008 +0000

    Allow nvramtool to build and work on FreeBSD. Tested on FreeBSD 7.
    
    Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b076ced581669632d03b2f768b30aec2ffcd2e23
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 30 03:10:17 2008 +0000

    Mark two more chips as fully tested (trivial).
    
     - SST SST39SF010A
     - Winbond W29C011
    
    Tested by me on actual hardware, all operations.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a69d1db50408053c3766d65c54fd266afd77a158
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 29 22:13:20 2008 +0000

    Flashrom support for some Numonyx parts (M25PE)
    
    using block erase d8 as discussed with Peter Stuge
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6bb6be6d27f95851cf6b7cbb67ddbd1ee5c8c5d
Author: Ed Swierk <eswierk@aristanetworks.com>
Date:   Wed Oct 29 14:54:36 2008 +0000

    Enable SPI boot flash support on EP80579, which has the ICH7 register set
    (trivial).
    
    Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
    Acked-by: Ed Swierk <eswierk@aristanetworks.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bddc693e8d9cb3c66c2ef98da0b4de3c51aef94b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 29 13:51:31 2008 +0000

    i945/ICH7: Use #defines from pci_ids.h (trivial).
    
    Build-tested with the kontron/986lcd-m target.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36a2268d17f119e032b3f9b49ff5ef6989812504
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 29 04:52:57 2008 +0000

    Support for the Kontron 986LCD-M mainboard series.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 278534d00734a1f4c3f252f11ca234a6517a590b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 29 04:51:07 2008 +0000

    Support for the Intel 945 northbridge.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 00a889c8aabd7b731622d5ff0e765f69e158de2b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 29 04:48:44 2008 +0000

    Support for Intel Core Duo and Core 2 Duo (tm) CPUs.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit debb11fc1fe5f5560015ab9905f1ccc2e08c73e0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 29 04:46:52 2008 +0000

    Support for the Intel ICH7 southbridge.
    
    This includes an early SMI handler.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b70d1993a432af2a026c4cad0fa3dd3c5eca1ef7
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 29 04:45:28 2008 +0000

    Implement support for the Winbond W83627THG.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 532fd2dc3d3dcf9bf1f2e2c8df539d07d0f214a0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 29 03:15:42 2008 +0000

    Changes required to the device allocator:
    - leave a hole for mmapped PCIe config space if CONFIG_PCIE_CONFIGSPACE_HOLE
      is set.
    - Mask moving bits to 32bit when resources are not supposed above 4G. Linux
      does not like this, even though the resource is disabled.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b64aa60f1fd5e6c84ec8ff6ad0baa7afee0d810a
Author: Andriy Gapon <avg@icyb.net.ua>
Date:   Tue Oct 28 22:13:38 2008 +0000

    Allow superiotool to compile and work on FreeBSD. Tested on FreeBSD 7.
    
    Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c372aa4f77a81e24c1ced47b1da010814b3da3bf
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 28 12:00:59 2008 +0000

    Mark Winbond W39V040FA" (512 KB) as fully supported, tested by
    Martin Stecklum <stecky@gmx.net> (both write and erase).
    
    The tests were done on an MSI MS-7065 board, so that's supported now
    too (wiki page will be updated).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 49387739daa10d769928f55b6cf75a39996f6bf6
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 28 11:50:05 2008 +0000

    Add support for the Intel 82371MX (MPIIX) southbridge (trivial).
    
    Untested, but should work just as well as the other *PIIX* southbridges
    according to the datasheets.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 13be848dfcd9d9c3384eec2ec93fd25c223144ab
Author: Mats Erik Andersson <mats.andersson@gisladisker.org>
Date:   Mon Oct 27 13:44:07 2008 +0000

    Add initial support for the MSI MS-6147 mainboard.
    
    Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 045d32d78cadc287c5dbd44b8fceba5241772729
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 26 18:40:42 2008 +0000

    Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridges.
    
    Tested on PIIX3 hardware.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4446aa0a292142194b44b673547d35bea94e1037
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 25 18:03:50 2008 +0000

    Add support for the VIA VT82C586A/B chipset, improve documentation.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 38204a2c181b71d5c74a5bd9cfac14f450076ec2
Author: Urja Rannikko <urjaman@gmail.com>
Date:   Thu Oct 23 23:33:18 2008 +0000

    Add support for the ITE IT8661F/IT8770F, IT8673F, and IT8671F/IT8687R.
    
    They all use a different init sequence than the more modern ITE Super I/Os.
    
    For now we only use 0x370 as config port, but 0x3f0 or 0x3bd would also be
    valid. Contrary to other Super I/Os, the config port for these is _not_
    hardcoded via hardware, instead it can be programmed by software, i.e.
    you get to choose whether you want to use 0x370, 0x3f0, or 0x3bd.
    
    Tested on IT8671F by Uwe Hermann and on IT8770F by Urja Rannikko.
    
    Signed-off-by: Urja Rannikko <urjaman@gmail.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Urja Rannikko <urjaman@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4f294f33f24b92d03e2663b954fd8426925c18b
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Oct 23 12:22:24 2008 +0000

    make escape code handling for serial terminal more robust
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c811a1c6aef38f53fadc4d51b17c56116d2baaac
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Wed Oct 22 22:30:17 2008 +0000

    Made await_ide(), which polls for an ide status change, check the status
    reg much more often. In my case this reduced the time spent in coreboot
    by 1.5 sec!
    The timeout values of course aren't changed, only the granularity. Also,
    I didn't see any udelay() implementation that looked like it couldn't
    cope with 10 us delays. (Most are written as for (...) inb(0x80) loops.)
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f6fa12d89e8b260bae9652406b8a4ce519c783e0
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Wed Oct 22 22:26:09 2008 +0000

    Changed RAM speed calculation to fix RAM modules getting rejected only
    due to integer rounding errors. Previously, the formula was:
    	speed = 2 * (10000/spd_value)
    For spd_value=60 this means speed = 2 * 166 = 332, which is less than
    333 and coreboot died saying RAM was incompatible. The new formula is:
    	speed = 20000 / spd_value
    For spd_value=60, speed=333, which is fine.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e5bef5fbdc9ed15884f659ee6d822824a1080f1
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Wed Oct 22 22:24:47 2008 +0000

    Speed up copying coreboot to ram by using "movsl" instead of "movsb".
    Also use different console messages for copying and uncompressing, like
    it's already done in similar code in other places.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a9e61b7ec3f40fdf3716b95a0cfa2c695626dd0
Author: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Date:   Wed Oct 22 22:20:48 2008 +0000

    Fixes a off-by-one error when routing the IRQs. This led to IRQ15 not
    getting assigned.
    
    Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea8724578e096e5d39fc49b17d63d2af0f76e537
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 22 15:49:20 2008 +0000

    Fix ordering problem in the libpayload Makefile. The include of
    'include util/kconfig/Makefile' must come before certain pattern rules
    for compilation of kconfig files, otherwise the build would break
    in most situations.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ac431505c6c7914cbea4923c9c80eb83d72e34fb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 22 11:23:32 2008 +0000

    add multiboot support to defconfig (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b57f1c985fb69ac9e682b0789d23f180b78286e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 22 11:06:20 2008 +0000

    ouch. something went wrong with applying that old patch
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 734427ea921b4cd4cbeffc7f5e85bf585750bda4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 22 10:49:34 2008 +0000

    This has been sitting here since a looong time.
    
    * allow versions of "install" that don't know -D
    * install libpayload .config and config.h to the target.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1877b5e51d427da1a9a3dc43a838c17cd8d25fb3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 21 22:09:02 2008 +0000

    Reduce serial output, otherwise flashing will fail very often (trivial).
    
    This has been tested on hardware by me.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ec8285aa151a246a05805ee7165c3c1ddb43958
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue Oct 21 21:49:48 2008 +0000

    [PATCH] fix video console init
    
    Move console_add_output-driver() inside the for() loop
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 039255c59c11863e00a64c47c487fe59c5c12097
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 21 16:27:38 2008 +0000

    I/O ports are 16bit, so change 'unsigned long port_base' to 'u16 port_base'.
    Also, use more readable #defines instead of hardcoded config ports for
    PM/PM2 related functions, and simplify them a bit.
    
    Build-tested with the AMD dbm690t target.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 657a6dc390871721711c2becc8501d05095891e5
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Oct 21 15:08:18 2008 +0000

    This patch removes most of the #ifdefs in libc/console.c, and
    replaces it with two queues (input, output) where drivers (serial,
    keyboard, video, usb) can attach.
    
    The only things left with #ifdefs are initialization (at some point
    the drivers must get a chance to register)
    
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97f56a4b7e36a49f8d7d24dcf741df1c181f13cb
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 21 15:07:53 2008 +0000

    Add missing license header.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2433a9d9e643d828e4f9bafe04657984778c27b
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Oct 20 17:08:08 2008 +0000

    [PATCH] libpayload:  Fix overflow in _delay function
    
    On faster machines, delta might be more then 32 bits
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c53cdd782a8551ac2e0dcda9cbd5b0d319102b85
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Oct 20 17:07:47 2008 +0000

    [PATCH] libpayload:  Add a strtoul() function
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec6363dc48540db67a5966dc9987b192c26fcae1
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Oct 20 17:07:26 2008 +0000

    [PATCH] libpayload:  Bail if the keyboard controller isn't there
    
    If the system in question does not have a superIO, then a read of
    0x64 will return 0xFF and we will loop forever.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6744231197b38bfc27c43b9cc95d25b6f8595d95
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Oct 20 16:52:06 2008 +0000

    [PATCH] libpayload:  Fix the PCI search function
    
    Remove a possiblity for evil recusion and fix the function and slot
    definition in the PCI search loop
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20c9cf12a4a8bc2a7939e7bbf490324984f5b055
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Oct 20 16:51:43 2008 +0000

    [PATCH] libpayload:  Add multiboot support
    
    Make libpayload applications multiboot compatible.  Add the
    multiboot OS table and grok the loader table, especially the
    memory map and the command line.  This makes libpayload
    applications loadable by GRUB.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 369a5f6c7a18516cb4da054d0e328f7464da9da7
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Oct 20 16:51:20 2008 +0000

    [PATCH] libpayload:  Add pci_set_bus_master() function
    
    Allow the payload to enable a PCI device as a bus master.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17f6a8778817ad592a2458083a1ba46032df22f6
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Oct 20 16:50:47 2008 +0000

    [PATCH] libpayload:  Use gcc to compile assembly files
    
    Using gcc to compile assembly files lets us use preprocessor
    directives.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c880a369de89134007477c47968cec2a852195f9
Author: Andriy Gapon <avg@icyb.net.ua>
Date:   Sun Oct 19 21:03:41 2008 +0000

    Add register definitions for W83627HF based on publicly available
    specification and local testing.
    
    Also tweak a little bit algorithm for (internal) device ID calculation:
    Chips from the W83627HF/F/HG/G family have an ID of 0x52 and a multitude of
    revisions (0x1x, 0x3a, 0x41, maybe more), chips from the W83627HF/GF family
    have the same device ID but revisions 0xfx.
    
    Please note that the last line of the patch simply fixes the comment
    about internal device ID composition (upper half of reg 0x21 is used).
    I chose the most conservative way of detecting W83627HF - only if reg
    0x21 value matches 0xFx we skip the previous logic and keep using it for
    all other revisions.
    
    Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1aa329dcb0543dabe9b2eb538bb1ec1f183a10f9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 18 21:14:13 2008 +0000

    Coding-style fixes for flashrom, partly indent-aided (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 582364d8089cb630e673eaee3710733b11d5125b
Author: Urja Rannikko <urjaman@gmail.com>
Date:   Sat Oct 18 13:54:30 2008 +0000

    flashrom: Allow the SiS 620 chipset to detect and read at least 256kb chips.
    
    Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info
    about SiS620.
    
    Signed-off-by: Urja Rannikko <urjaman@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71a2fbf9d531a3e97660e60d384c1ed15191f54f
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Fri Oct 17 14:17:05 2008 +0000

    One more little fix for the Jetway J7F[24], option tables can only be
    built in the normal image, not fallback.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 400224e71ae6b2ab2b7fb1e7a0716ad4e9915871
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Fri Oct 17 02:47:20 2008 +0000

    Config-abuild.lb's for jetway/j7f24 and bcom/winnetp680, to (finally) get abuild to stop complaining about these boards. They build fine with the default configs on a regular build.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 01a9c1bf77486bf197e6cd65d3d6c12973d14899
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Fri Oct 17 02:34:06 2008 +0000

    Final fix for C7 boards, which are still using ROMCC, to be able to
    build. As far as I know, no C7 boards currently in the tree use SPI
    flash.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8829c7d904125af8040a7c15b11cbd8e7040222d
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Oct 17 00:06:50 2008 +0000

    ROMCC chokes on vt8237_early_network_init(). Since that function is only
    called from one target and that target is compiled with GCC, make the
    function dependent on GCC.
    
    ROMCC also chokes on the ULL suffix for integer constants. Change the
    affected ones to UL for ROMCC compiled code.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a3ad59653c2ecb9de0ffc91714855748f8a22b9
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Oct 16 23:44:21 2008 +0000

    Revision 3564 improved compilation time, but it also introduced a
    dependency bug which hit people running parallel make instances.
    
    With our current makefile architecture, the "right" fix is impossible.
    However, we can still kill the race conditions leading to arbitrary
    compilation failures. That trick depends on the atomicity of the mv
    command.
    
    Extensive comments explain what the workaround does.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4727c0744615d7b49c843197433937721ce9acd1
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Oct 16 19:20:51 2008 +0000

    - reduced memory requirements a lot (from >100kb/controller to
      560bytes/controller)
    - no need for the client of libpayload to implement
      usbdisk_{create,remove}, just because USB was compiled in.
    - usb hub support compiles, and works for some trivial cases (no device
      detach, trivial power management)
    - usb keyboard support works in qemu, though there are reports that it
      doesn't work on real hardware yet.
    - usb keyboard is integrated in both libc-getchar() and curses, if
      CONFIG_USB_HID is enabled
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b1b071fe17dd472192de201e463ce3d5811a2957
Author: Alex Mauer <hawke@hawkesnest.net>
Date:   Thu Oct 16 17:45:25 2008 +0000

    * Add a new board, the BCom WinNET P680
    * Add a function to change the 24/48Mhz clock input selector on the Winbond
      W83697 superio to 48Mhz, used by the WinNET P680
    
    Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca11e7c2590eba229ee62ccee86620a5d0ef7851
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Oct 16 15:05:18 2008 +0000

    Revision 3567 introduced __attribute__((packed)) for a structured which
    is also visible to ROMCC and ROMCC doesn't understand that.
    
    The fix is to use __attribute__((packed)) only for gcc compiled code.
    
    This has been unfixed for too long. There are more problems remaining,
    but at least this one is solvable easily.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7528aa6de3cf67a5310d2cfb7e555c34de7dd20e
Author: Marc Jones <marcj.jones@amd.com>
Date:   Wed Oct 15 17:50:29 2008 +0000

    SB600 has four write once LPC ROM protect areas. It is not possible to write
    enable that area once the register is set so print a warning.
    
    Signed-off-by: Marc Jones <marcj.jones@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b0ae976eaf55c677f2500e7e80810383f219f6fc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 14 16:34:38 2008 +0000

    Drop global register 0x07 for all Super I/Os (trivial).
    
    This is useless, as it changes with each access; it doesn't convey any
    useful information at all.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9c6b0e8f7eb3af186066508b3ce3093043fc11a
Author: Josh Profitt <zorn169@gmail.com>
Date:   Tue Oct 14 16:28:50 2008 +0000

    Add dump support to ITE IT8726F, and add comments and a missing GPIO
    register to ITE IT8718F.
    
    Signed-off-by: Josh Profitt <zorn169@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8e53eb50cb3745b3bf7964f0f49980dc10c08ec
Author: Ed Swierk <eswierk@arastra.com>
Date:   Mon Oct 13 23:18:56 2008 +0000

    Add support for the Intel EP80579 (Tolapai) Development Kit mainboard
    (Truxton).
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7d781dad58471d42c68eff3cf9317430a42af72
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 13 21:41:24 2008 +0000

    Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.
    
    Build-tested with the AMD dbm690t board.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 28401bd9ea0df09040e6212432d5c53e88835470
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 13 13:08:38 2008 +0000

    Drop unused (or commented / #if 0) reset.c files.
    
    This is abuild-tested by me.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 598ba437427709f808e5035832f5f650b393ddbc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 12 22:34:08 2008 +0000

    Drop tons of duplicated debug.c files, move common file to
    lib/debug.c and use that one.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ce164dda386b920a95519df196613b0cf894acb
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sun Oct 12 20:35:58 2008 +0000

    Remove an extra bracket left by the vt8237r cleanup patch (trivial)
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0a20c416226d34ef25881e4d143cf1b8bf531656
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 12 14:40:23 2008 +0000

    VIA VT8237R cleanups (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e5a9d952f3f3d23cf57a08abeffe3dee3444950
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 12 11:58:26 2008 +0000

    Add support for the VIA pc2500e mainboard (CN700 + VT8237R).
    
    Works good enough to boot to a Linux console.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3be4bc88fabf1a19cec38e5dbea515f1ddeb4be9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 11 16:10:54 2008 +0000

    Drop a number of duplicated failover.c files (they have the same content
    as the global src/arch/i386/lib/failover.c file).
    
    Also, drop a number of dummy failover.c files which are not even used at all.
    
    This is abuild-tested by me.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f4b54b413502ddd548a39439cba80dcf9b821bd6
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Oct 10 20:54:41 2008 +0000

    Add ICH10 support to flashrom.
    
    The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash
    interfaces, so this just adds the required PCI IDs.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e40e46d49fef1a9ec15a40c10deb88f11c2cada
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Oct 10 20:43:17 2008 +0000

    flashrom: Check that a filename was specified also when using force read
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 32965d8dbb7623262ed4878e2705c991a8aeecba
Author: Ward Vandewege <ward@gnu.org>
Date:   Fri Oct 10 18:06:56 2008 +0000

    Enable vga bios by default on Tyan s2881. The board has an onboard ati rage XL.
    
    This is a trivial patch.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0323a2b8f502767d42486f1c58ab1b9a02e51301
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 9 23:56:11 2008 +0000

    Add Fintek F71882FG support (trivial).
    
    Tested on actual hardware, the MSI K9AG Neo2-Digital (MS-7368).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea7b518ec087ff7847ba2ff8b717305db4c14ab9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 9 17:08:32 2008 +0000

    Indent-based + manual cleanups for CN700 (trivial). As this will be ported
    to v3 sooner or later we cleanup _now_, so we don't have to do it twice.
    
     - Whitespace, coding style improvements.
    
     - Fix a few typos.
    
     - Add a missing #endif in raminit.h.
    
     - Drop an unused variable.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c1d06b782ff140acae61253a3e663c0ac517ab04
Author: Marc Jones <marcj.jones@amd.com>
Date:   Thu Oct 9 16:05:16 2008 +0000

    Added comment about sb600 wideio setting for clarity and a minor witespace  cleanup. (trivial)
    
    Signed-off-by: Marc Jones <marcj.jones@amd.com>
    Acked-by: Marc Jones <marcj.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b1971cc6274899cf487e255048395342138f601
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Oct 8 14:47:41 2008 +0000

    libpayload: Rename Geode video driver to Geode LX video driver.
    
    This is simply wrong, the "Geode" video driver is only good for LX and one of
    our users got bit by this just now.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ff9350b79869b9247cff8414227fc424883cf4c0
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Oct 8 11:17:25 2008 +0000

    move variable declaration to where it is used, to prevent gcc failure.
    Reported by Roman Yeryomin (and also seen reported earlier). (trivial)
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 964f0665594bfdc260b49b6a2eac57b2dabeabaa
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue Oct 7 16:25:10 2008 +0000

    [PATCH] coreboot:  Don't loop forever waiting for HDA codecs
    
    We shouldn't assume the presence of a working HDA codec, so put in
    a reasonable timeout of 50usecs (timeout value borrowed from the kernel).
    This makes SimNow work, since apparently though the codec is
    present in Simnow, it is non functional.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0994c397a5ef65c4ee8ae4551cc90000c4b0c857
Author: Mats Erik Andersson <mats.andersson@gisladisker.se>
Date:   Tue Oct 7 12:21:12 2008 +0000

    Support for AM29F002(N)B[BT]. Fully tested on AM29F002NBT.
    
    Probing, reading, and erasing use the Jedec-routines,
    whereas writing resort to the recent write_en29f002a(),
    since also these chips use a byte wise algorithm.
    
    Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a643ea3beba32ed170f995b2d40169017edb1095
Author: Myles Watson <mylesgw@gmail.com>
Date:   Mon Oct 6 21:00:46 2008 +0000

    Whitespace fixes.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69e9cc4fbded07f576e8c7ca0637feb8a4f08f6c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 4 23:13:18 2008 +0000

    Fix obviously (syntactically) broken cmos.layout (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cf762a4be52ebb9082bc7e971ec31496d7aafa22
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri Oct 3 23:23:20 2008 +0000

    Ron has been doing really good work over in v3. The problem is that the work got checked into v2. This should get us back to where we were. (trivial)
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c0b6d72bcce9cbe83599682de753013b3eced17
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 3 18:16:23 2008 +0000

    Fix/amend the incorrect pnp_dev_info[] items for the ITE IT8712F Super I/O.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 92f3eda8091f400ff71b7fbaf0be7b646521ddc4
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Oct 3 15:17:47 2008 +0000

    Thanks to Jason Zhao we got a skeleton CAR code for VIA C7. I have tried
    to clean it up a bit and find justifications for every difference from
    x86 and AMD CAR code. I believe this is mostly merge-ready. Although I'd
    have preferred to do this for v3 first, we can fix v2 boards with this
    change and then move them to v3.
    Thanks to Bari Ari for getting the code to me for rewrite/review.
    
    CONFIG_CARTEST shall not be enabled (breaks the build).
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Signed-off-by: Jason Zhao <jasonzhao@viatech.com.cn>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cee94384364999a696e3b78a3fe4e2b24f87ea19
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Oct 2 19:21:30 2008 +0000

    Whitespace cleanup (trivial).
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d61ada6555ed2e8b5693b987faae1624ec4cbde6
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Oct 2 19:20:22 2008 +0000

    Whitespace cleanup (trivial).
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7f3d48c9afd8f3397f7ce85148d802082ccc9de9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 2 18:19:17 2008 +0000

    CK804 coding-style fixed based on an 'indent' run (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5107174459f581ff9a2f548768df6e1eef3c2d79
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 2 15:42:14 2008 +0000

    This is so that people can see it. This is the sb600 for v3. It almost
    certainly won't build -- that comes later. I am hoping to get some
    eyeballs on it for simple errors.
    
    rs690 is next.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 248a7df94a2f35c75eaf4fe3b949398577368816
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Oct 2 01:35:03 2008 +0000

    Fix a typo.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bdb96f8abece96f4bd11bed45d30f143d084b7c6
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Oct 2 00:52:53 2008 +0000

    Use easily readable macros to setup interrupt routing.
    Change a few PCI bus/dev/fn to use hexadecimal numbers.
    Kill unused variables.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5263b0165724165c1c492866fe3546c3d748d69f
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Oct 1 22:15:20 2008 +0000

    Missed a CONFIG_USE_PRINTK_IN_CAR define for the Asus m2v-mx_se.
    This fixes that build error. (trivial)
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cfb6ac72d1020a0a23eecfb3c8ec3b167ce1f7a3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 1 20:16:58 2008 +0000

    Add some more Super I/O IDs/names (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b816d332a316f90fa0c90df4c7fed97a2de4af40
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 1 13:10:39 2008 +0000

    Enable all available devices on the ASUS A8N-E (trivial).
    
    This is in preparation for actually making the devices work (which needs
    some extra code). Also, fix the incorrect mainboard subsystem IDs.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ee6779a64922af755a35ce70f85f2d67b488557
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Oct 1 12:52:52 2008 +0000

    The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of
    code to use it. That makes the code more readable and also less
    error-prone.
    
    Abuild tested.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc65196f8f18c28085d40ccbeb45bba3bfe28294
Author: Marc Jones <marc.jones@amd.com>
Date:   Tue Sep 30 17:09:44 2008 +0000

    Add an abuild command line option for -fno-stack-protect for toolchains that might require it.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 336935c378a865feffe09033c34b6a7790d8a99b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Sep 30 15:02:40 2008 +0000

    Coding-style fixes and simplifications for the ASUS A8N-E (trivial).
    The only non-cosmetic change is s/A8NE/A8N-E/ for the board name.
    This is build-tested by me.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94c1bd8904ec23566d5a63ad396eb07424df97ee
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Tue Sep 30 06:13:54 2008 +0000

    Do not try to display non-printable characters on the bootlog and
    ramdump screens. This fixes unaligned display on serial console.
    
    The current isprint() implementation assumes a C locale, so also
    characters with the eigth bit set are supressed (they produced
    inconsistant results on VGA and serial anyway).
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45db366d5c8222148100713b165762aab61c478f
Author: Mats Erik Andersson <mats.andersson@gisladisker.se>
Date:   Tue Sep 30 04:52:29 2008 +0000

    A duplicate register address is incremented in table register_values.
    A trivial fix to correct the address of the high byte in SDRAMC.
    Thus the leadoff timing IPDLT will be correctly referenced.
    
    Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 166ad2d7a56b6b472bb573eb331370733482610c
Author: Tim ter Laak <timl@scintilla.utwente.nl>
Date:   Tue Sep 30 04:13:32 2008 +0000

    This patch fixes support for the AT49F002N(T) chip in the flashrom tool.
    
    It replaces the write function to one based on write_byte_program_jedec()
    instead of write_page_write_jedec(), as this part does not support page
    programming.
    I have verified the NT variant to fully work now, and adjusted the test
    status accordingly. The N variant *should* also work with this patch, but
    remains untested.
    
    Signed-off-by: Tim ter Laak <timl@scintilla.utwente.nl>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5de576c1902ce4b33a56baf27fb0dd552b6cb105
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Sep 30 04:00:23 2008 +0000

    flashrom: ST M29F040B status TEST_OK_ PROBE READ ERASE WRITE
    
    Per report from Daniel Lindenaar. Thanks!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2080bd9a41dfda32e740869be8dbbdbc2978211e
Author: Marc Jones <marc.jones@amd.com>
Date:   Mon Sep 29 22:59:23 2008 +0000

    AMD K8 platforms must use CAR so it makes sense to use the PRINK_IN_CAR
    option.
    This patch converts the following patches to use PRTINK_IN_CAR
    amd/serngeti_cheetah
    msi/ms9185
    msi/ms9828
    supermicro/h8dmr
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b246158f7798674a1df1f610e6bc4115721e67dc
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Sep 29 21:21:36 2008 +0000

    flashrom: Fix typo in r3615 (TEST_PREW -> TEST_OK_PREW)
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f41bf97cb36e4ee458cbe1521c42dfd7fd280ef
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Sep 29 18:48:23 2008 +0000

    Mark the SyncMOS S29C51002T as working (trivial).
    
    All operations tested by me on hardware.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5623d18ccc642e14f7df73f5d439bac47e337ae
Author: Marc Jones <marc.jones@amd.com>
Date:   Mon Sep 29 18:09:51 2008 +0000

    This patch for the AMD K8 allows a single DIMM to be populated in the
    ChannelB slot. Previously a DIMM could only be populated in ChannelB
    if there was a DIMM already in ChannelA. This patch doesn't allow unmatched
    DIMMs to be populate in ChannelA and ChannelB. In an A & B configuration
    the DIMM must still be matched.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a67aab70834fe28c34d4a1c9203f6f1b8462cc38
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Sep 27 10:08:28 2008 +0000

    Add string support to nvramtool.
    
    To add a string to your cmos.layout, you need to specify type 's':
    
    #start     len       type    unused   name
    416        512       s       0        boot_devices
    
    With this patch you can do
    
    $ nvramtool -w boot_devices="(hd0,0);(hd2,1);(hd3)"
    
    And FILO will attempt to load a menu.lst from any of these devices in that
    order.
    
    The patch is not exactly pretty, but a cleaner solution might have resulted in
    a complete rewrite of the tool, which I did not want.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 830b17d3e38806b7977bda7df59775a301ca4584
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Sep 27 08:51:11 2008 +0000

    fix ppc mainboards (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c753926a01d94815e10480ddd3abb5c80ccbc923
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 26 19:37:16 2008 +0000

    accidently backed out r3598. Sorry Ulf, will pay more attention next time.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ecd176f304958eff33ecb5ee3f3a2c8de535fdd5
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri Sep 26 19:15:38 2008 +0000

    This patch fixes the dbm690t keyboard not working issue. It should also
    fix the a8n_e and any other it8712f SIO keyboard issues. The it8712f
    requires an archaic PS/2 mode setting to the keyboard controller before
    accessing the keyboard. Beyond that, I made the keyboard controller and
    keyboard init more robust and added more informative debug output.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 678d61cf5d7b3b985640fcc1e544e23cf5bdd360
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 26 18:56:11 2008 +0000

    add svn:ignore for temporary files and directories. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 41514397e7168fdd4b2066435cc3c668e68514d6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 26 18:42:40 2008 +0000

    * Add strsep (since strtok is considered obsolete)
    * add a bunch of string function doxygen comments.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc9cb27a8e352a42dbfe2a404e8640e8aff47ad3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 26 18:40:06 2008 +0000

    Use a block cursor on VGA console :-)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71c006fe9b1bcc74e1000c7869ec41cf3dc80894
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 26 18:39:06 2008 +0000

    fix option handling in libpayload
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d84ef1e6dc6e9b559ada98a7c2d57ead3ae19c26
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 26 18:37:26 2008 +0000

    * add keyboard layout support to libpayload
    * add a reset handler mechanism (CTRL-ALT-DEL)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e75c3d85a35f0c42fef1621ca76eb085b6ae5a94
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 26 18:36:26 2008 +0000

    * factor out serial hardware init
    * add reverse color support for serial
    * add cursor enable/disable support for serial
    * fix tinycurses compilation if serial is disabled
    * add functions to query whether serial or vga console is enabled in tinycurses
    * initialize uninitialized COLOR_PAIRS variable
    * implement has_colors(), wredrawln() functions in curses
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96bcc53071bacc284df46093cfc3981b437cf035
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri Sep 26 17:41:34 2008 +0000

    Add IRQ12 to the dbm690t mptable for mouse interrupt support.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ad9bdb4345d73c7e9ae53b4bef4796d4216c34a2
Author: Mats Erik Andersson <mats.andersson@gisladisker.se>
Date:   Fri Sep 26 13:19:02 2008 +0000

    Activate proper support for EN29F002(A)(N)[BT].
    
    Fully tested for Probe/Read/Erase/Write on EN29F002NT.
    Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()'
    are still in use, but a tailored 'write_en29f002a()' is
    needed due to a byte wise writing mechanism for this chip.
    
    Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c55b05cb2f910d5bb2823f5457de8cae3b43271
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 26 11:21:21 2008 +0000

    Add default config file to libpayload so that one can do make defconfig
    without errors.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f69d5ee13ca2e3d9437b2b9ff6370a8800efc9f9
Author: Ed Swierk <eswierk@arastra.com>
Date:   Wed Sep 24 15:06:34 2008 +0000

    Support for the memory controller and PCIe interface of the Intel
    EP80579 Integrated Processor (codename "Tolapai"). The memory
    controller code supports only 64-bit-wide DIMMs with x8 devices and
    ECC. It has been tested on a development board using a single Micron
    MT9HTF6472PY-667D2 DIMM. Your mileage will definitely vary with other
    DIMMs.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 22d5ddcd097010eead86750146a41908a436f801
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Wed Sep 24 14:21:02 2008 +0000

    Fix overflow in modwin erase. Do not refresh modwin yet, since it is
    immediately overwritten by stdscr.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 902ed76ec4372d163a89d490ac0ab20732d65062
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Wed Sep 24 14:17:02 2008 +0000

    Adjust width of stdscr to exactly SCREEN_X. This fixes alignment issues due
    to an extra space sent at end of each line, as well as a data corruption
    issue, which could result in undefined color pairs being referenced.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f5379ce4e051ef5c4cf2baba329dbc6fcb26cdb
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Sep 24 10:09:03 2008 +0000

    Fix up remaining AMD DBM690T autobuild issue.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9856fb3821a896e63c1055026939940d68d600ad
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Sep 24 03:21:55 2008 +0000

    Add abuild support for the dbm690t. (trivial)
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4590ce2b3c22be17b57fe1ed28fb8f43cfc60287
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Sep 23 22:26:27 2008 +0000

    This patch adds support for watchdog kill and adds it to Asus M2V-MX SE.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3aca4b5734e13dc5a40d238421be8c0f072ee552
Author: Marc Jones <marc.jones@amd.com>
Date:   Tue Sep 23 22:19:27 2008 +0000

    The AMD dbm690t mainboard uses the it8712f SIO with the
    default 48MHz clock input. The Asus a8n_e uses the it8712f
    with a 24MHz clock input. The it8712f early init code was
    setting a 24MHz input clock(to support the a8n_e).
    Since 48Mhz is the default I added a function to set 24MHz
    input clock to the a8n_e.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Rudolf Marek <r.marek@assembler.cz>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f4282b538213c17913821bc8e84877074838edf
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Sep 23 21:57:33 2008 +0000

    Attached patch removes HPET info from ACPI tables. HPET does not work fine on
    VT8237R (random keyboard/mouse lockups).
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3e3c83e40aedc98fd6cbf1a33bbaa3400726c0a0
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Sep 23 21:29:53 2008 +0000

    1.
    Preset CC to gcc in Makefile. There are some $(shell $(CC) ...)
    invocations with GCC specific options, so that shouldn't hurt.
    
    2.
    Replace stdbool.h include in util/kconfig/expr.h by a custom
    implementation of booleans. This is okay as these booleans are purely
    internal. It's necessary because there's some disagreement between the
    Solaris headers and GCC on Solaris, about when stdbool.h is appropriate.
    
    3.
    Remove stdbool.h include from util/kconfig/zconf.tab.c_shipped. This
    file includes expr.h already, so it picks up the right set of
    primitives, without duplicating the special case for Solaris.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 05839975bf2549d5fb3bed460745e24ffd7b832a
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Sep 23 20:36:03 2008 +0000

    Following patch adds support for Asus M2V-E SE. Works pretty well, the only
    problem left is with CPU scaling setup. No VGA - may work with the Xorg drivers
    recently released, maybe with OpenChrome too.
    
    It wont work with the little patch which will hop in soon
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 80d7c85fb9e9f0b301b01e68f475b2ede34ec877
Author: Michael Xie <Michael.Xie@amd.com>
Date:   Mon Sep 22 13:16:18 2008 +0000

    Patch for AMD DBM690T board.
    
    Signed-off-by:  Michael Xie <Michael.Xie@amd.com>
    Reviewed-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7586cef37aace94f1558a391b25245f08523ab95
Author: Michael Xie <Michael.Xie@amd.com>
Date:   Mon Sep 22 13:11:39 2008 +0000

    Patch for AMD SB600 chipset.
    
    Most of the functions in SB600 are enabled except power management.
    
    Signed-off-by:  Michael Xie <Michael.Xie@amd.com>
    Reviewed-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 06755e404eb4b97dab5bc5ff90443f7d7d74d3cf
Author: Michael Xie <Michael.Xie@amd.com>
Date:   Mon Sep 22 13:07:20 2008 +0000

    Patch for AMD RS690 chipset.
    
    All the PCIe slots are enabled in this patch except power management.
    
    Signed-off-by: Michael Xie <Michael.Xie@amd.com>
    Reviewed-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b0771d180d5b18a3d698ccac54449112a9fca91
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Sep 19 22:58:59 2008 +0000

    Attached patch fixes at least one issue  ;)  During the PCI BAR sizing must be the
     D1F0 bridge without activated I/O and MEM resources, otherwise it will hang
     whole PCI bus.
    
     U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why
     does we not.
    
     Second small change just changes a bit which controls the PSTATECTL logic.
    
     Third change deals with the integrated VGA, which needs to be enabled early,
     so the VGA_EN is set along the bridges, and PCI K8 resource maps are set
     correctly. Finally the CPU accessible framebuffer is now disabled as it is not
     needed.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4128cfbec0d496873b9a2a684cf32a23b17137d
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri Sep 19 21:19:46 2008 +0000

    Whitespace and style cleanup. (trivial)
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d183c5846d026ddb3c9ec6003bea4ece9c2985a
Author: Michael Xie Michael.Xie <Michael Xie Michael.Xie@amd.com>
Date:   Fri Sep 19 20:16:25 2008 +0000

    Add AMD K8 S1G1 socket support.
    
    Signed-off-by:  Michael Xie Michael.Xie@amd.com
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 64caf3607ea2e0e2a74c8d4c6429dcb40ec80f86
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 18 16:27:00 2008 +0000

    ck804 whitespace fixes
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a67c354cbf4a8e44982a9fe02d7df19969033861
Author: Myles Watson <mylesgw@gmail.com>
Date:   Thu Sep 18 15:30:42 2008 +0000

    Fix whitespace in tyan s289{1,2,5} files.  Also removes some #if 0 and #if 1
    that don't seem to clarify anything.  Abuild tested.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 297b91c6cde7e1570be67cc664d5adef2823a53f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Sep 18 14:49:33 2008 +0000

    fix two minor bugs in nvramtool. (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4614aedd4b6fb31c30f4eff347f91e4972edecf7
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Sep 18 07:48:59 2008 +0000

    fix regression in libpayload introduced by merge of the keyboard drivers.
    (add back function keys; trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e6408a36c9dfb98b2c15b66052f12f195e763dbf
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Wed Sep 17 18:12:46 2008 +0000

    - unify keycodes for non-ASCII keys by using curses' codes and labels
    - fix ctrl-[a-z]
    - get rid of curses' ps/2 driver. uses generic one instead
    - #ifdef's around ps/2 keyboard handling and serial handling
    - add alt-key handling (necessary for german keymap)
    - flush keyboard controller buffer on init
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57700ff81f1048d6083299f3a0262d62b4612130
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Sep 17 16:32:17 2008 +0000

    This patch adds damage detection to libpayload's tinycurses. This
    significantly speeds up serial output with large windows.
    
    It also adds the function curs_set to enable/disable the cursor (video console
    only for now)
    
    Also, use werase in one place to reduce code duplication.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f218d97a17e0ee067c5454753ade670b52c7d13c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 12 21:50:57 2008 +0000

    * Implement scrolling in tinycurses
    * Fix an off by one bug
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 229c20f3e21e556bd83287e7342f96d2375ae2f4
Author: Alex Mauer <hawke@hawkesnest.net>
Date:   Fri Sep 12 20:39:04 2008 +0000

    For the jetway jf2/4 series of mainboards:
    * change the comment for device f.0 from "IDE" to "SATA"
    * turn on firewire device a.0
    * turn on pata device f.1
    * don't turn on the unusable device 10.5 (built-in vt8237 ethernet?)
    
    Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53bbb0f6b1bd96a7ad8c5cd0d45e0b2705704f6d
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Thu Sep 11 17:44:45 2008 +0000

    makes cursorx and cursory signed, as there
    are several "if (cursorx < 0)" tests.
    
    I also added another one, to make backspace
    wrap backwards into the previous line, if necessary.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29061a59b2b09c0896a53c9208199feecb432225
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Sep 11 17:29:00 2008 +0000

    Fix the USB code to find the headers after they were moved.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6fbbd8080fdbabd5ea53c41ac566b470c3e2fb58
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Sep 11 17:26:53 2008 +0000

    Move the USB header files to a common location for install
    purposes.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 232dc970bc0f0b48b7d16b4746a5fd2fd7f62426
Author: Alex Mauer <hawke@hawkesnest.net>
Date:   Thu Sep 11 17:19:19 2008 +0000

    Add the target for the previously-added jetway mainboard.
    
    This target is a copy of the epia-cn target, with only
    COREBOOT_EXTRA_VERSION modified.
    
    Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f657d7537538ed83e0768ccce499329ac22a0b5b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Sep 11 06:52:22 2008 +0000

    From Vincent Legoll:
    Use dev_path() to have nice debug output
    patch is run-time tested
    
    Trivial, thus:
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9196dd553dcfdaefec8b4d5c94895175f796ff7b
Author: Alex Mauer <hawke@hawkesnest.net>
Date:   Wed Sep 10 20:40:46 2008 +0000

    Add the "jetway j7f[24]*" mainboard.  As compared to the Via Epia CN, this
    changes the superio to a Fintek F71805F as described at
    http://www.coreboot.org/Jetway_J7F2_Build_Tutorial
    
    It also creates the mainboard tree for this series of motherboards
    (Jetway J7F2 and J7F4).  I've tested it with one motherboard
    (J7F2WE1G3), and I believe it works with the others, as the differences
    among them are mostly trivial (processor speed, chipset and quantity of
    LAN cards, audio chipset, etc.).  A list of the relevant motherboards
    with specs can be found at
    http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16
    
    The irq_tables.c is copied directly from the epia-cn, because the one
    generated by getpir with the factory BIOS did not work properly while
    the EPIA-CN one did.
    
    Minor changes on checkin to cope with moved romcc in latest revision.
    
    NOTE: This board is broken until the issue introduced in r3567 is resolved.
    
    Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb2b8a282c5d08ed1a285c72931aae9e42cf565e
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Sep 10 09:55:10 2008 +0000

    flashrom: Winbond W49V002A TEST_OK_ PROBE READ ERASE WRITE
    
    Per report from Kevin O'Connor. Thanks Kevin!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 05e0feece96460cba17b286a17919d8bcef0428a
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Sep 7 03:14:27 2008 +0000

    flashrom: Debug print actual time base calculated by myusec_calibrate_delay()
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f044f282eafe7258c57d3e5b76e3704eb637422a
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Fri Sep 5 21:23:02 2008 +0000

    Add editing keypad keys and the missing F11 key to the curses serial
    input cooking table.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9f29c8e5e3f37335a9b737361acc286df5248f0
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Sep 5 18:20:57 2008 +0000

    This patch adds support for the VIA VT8237S south bridge. The VT8237R programming remains unchanged (tested
    on mine desktop) except of reverting the small change introduced by Bari
    (gpio/inta setup reg 0x5b). This should go for some board specific file. The
    change would broke at least mine board. But seems to be needed for jakllsch.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Bari Ari <bari@onelabs.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 10d0a81ec1c6ccedac291824eed8980d011b0ab9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Sep 5 15:18:15 2008 +0000

    define array size in a single place (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e0ecf27bb3f25408256123c2373cd553739fd25
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Thu Sep 4 21:05:59 2008 +0000

    Make the serial output driver 8 bit clean. Remove translate_special_chars(),
    since it has been superseeded by the ACS code in tinycurses.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 00809ebf02f7c3eb5713f522512207a3544635d5
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Sep 4 13:44:00 2008 +0000

    This changes the python generated makefiles
    
            targets/*/*/Makefile
            targets/*/*/normal/Makefile
            targets/*/*/fallback/Makefile
    
    to use a common copy of romcc, and to leave this compiler untouched by
    'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
    'make clean' in targets/*/*/ will clean romcc.
    
    Thanks to Mats for the initial idea and implementation of a tool to do
    this. This patch has almost the same behaviour as the original tool
    without having to run the tool each time.
    Tested for abuild-friendliness.
    
    The patch saves ~10-12 seconds for every target using romcc. For a full
    abuild run, this is ~20% time saved.
    For the first 38 abuild targets, total build time is down to 13m24s
    instead of 16m22s on my machine.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1149a3692fda831c91acd0a59d426127a4d069bf
Author: Ed Swierk <eswierk@arastra.com>
Date:   Wed Sep 3 23:32:30 2008 +0000

    Tidy up identifiers, per Uwe's suggestion.  Trivial.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Ed Swierk <eswierk@arastra.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12aa5d9acfdf989717e904a8832e4cc4dd7faca2
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Sep 3 23:10:05 2008 +0000

    flashrom: Only find "unknown .. SPI chip" if no other chip was found
    
    This removes the false positive matches we've been seeing, and also removes
    the true positive match in case there is more than one flash chip and the 2nd
    or 3rd are unknown - but I think that case is uncommon enough to warrant the
    improvement in the common case. Use flashrom -frc forced read if you have the
    uncommon case, and/or please add the flash chip to the flashchips array.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d57a68063234f56bcf7c315e9a5c16bd069e626f
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Wed Sep 3 19:59:44 2008 +0000

    Add support for curses color output over serial.
    
    Note that the sequence \e[m for turning off bold resets all attributes,
    including color.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d21f68bbd588f46c23066eb8d227b51e4823de41
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Sep 2 16:06:22 2008 +0000

    This patch adds USB capabilities to libpayload. It requires some
    memalign implementation (eg. the one I sent yesterday).
    Features:
     - UHCI controller driver
     - UHCI root hub driver
     - USB MSC (Mass Storage Class) driver
     - skeleton of a USB HID driver
       (requires better interrupt transfer handling, which is TODO)
     - skeleton of a USB hub driver
       (needs several blank spots filled in, eg. power management.
        Again: TODO)
    
    OHCI and EHCI are not supported, though OHCI support should be rather
    easy as the stack provides reasonable abstractions (or so I hope). EHCI
    will probably be more complicated.
    
    Isochronous transfers (eg. webcams, audio stuff, ...) are not supported.
    They can be, but I doubt we'll have a reason for that in the boot
    environment.
    
    The MSC driver was tested against a couple of USB flash drives, and
    should be reasonably tolerant by now. But I probably underestimate
    the amount of bugs present in USB flash drives, so feedback is welcome.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ccfa1ac7994888f57c60b80fff80e350ab3f16c
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Sep 2 15:49:32 2008 +0000

    Add memalign(align, size).
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 56471f14db710f9368a53fa709fe79465220f245
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Sep 2 09:35:43 2008 +0000

    The keyboard driver mixed up the key press/release events for the
    special keys.
    
    Patrick Georgi explained:
    The |0x80 codes are "break codes", that means, codes that are emitted
    when the key transitions from pressed to non-pressed, so the modifier
    was always in the wrong state, as soon as you pressed shift for the
    first time.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 093f6d5379ed64efcf35a2f25398047f14784714
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Sep 2 00:26:11 2008 +0000

    flashrom: SST49LF016C TEST_OK_ PROBE READ ERASE WRITE
    
    Per test report from Bari Ari. Thanks!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4759d0f22892cc740d5aae559eaf5b9b5ab735a
Author: Bari Ari <bari@onelabs.com>
Date:   Mon Sep 1 01:48:07 2008 +0000

    This patch gets the Epia-CN working without ACPI or APIC.
    
    All devices work, no irq storms. Enjoy.
    
    Signed-off-by: Bari Ari <bari@onelabs.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3153863567f51c9173227b9cb4375d53e6f3e6ed
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Aug 31 22:10:35 2008 +0000

    Various Doxygen-related fixes in libpayload (trivial).
    
     - Drop all '@brief's, they're not needed as we use JAVADOC_AUTOBRIEF.
       The first sentence of every description will be treated as the '@brief'
       automatically.
    
     - Also, put all documentation/descriptions on top of the Doxygen-comments,
       and put the '@foo' keywords at the bottom of the comments for consistency.
    
     - Change comments for SEEK_SET/SEEK_CUR/SEEK_END from '/**@def' to '/**<'
       in order to make them appear in the output.
    
     - Drop all explicit '@struct' lines (which are optional; Doxygen will figure
       out that it's a struct if the comment is right before the struct).
    
     - Fix various typos, whitespace issues, etc.
    
     - Fix incorrect @param variable names, e.g. change '@param n foobar' to
       '@param s foobar' if the variable is named 's'.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e6ad6bd09594924f6f7224bc14b27f9c4e8429c
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date:   Fri Aug 29 09:06:16 2008 +0000

    fix typo
    Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc58b7ee667fb81df9a747df3da83ca5b0b8c304
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Aug 28 23:12:34 2008 +0000

    [PATCH]: libpayload:  Document time functions
    
    No code changes.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b746178e659df1added87d7f5011f79114fd60b1
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Aug 28 23:12:22 2008 +0000

    [PATCH]: libpayload:  Document the architecture specific routines
    
    No code changes.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 483926648ebc7b0ac937a6692dc2329113d65dd9
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Aug 28 23:12:02 2008 +0000

    [PATCH]: libpayload:  change the type of the cpu_khz variable
    
    This makes it match the extern declaration in libc/time.c -
    and doxygen can find make the connection. Trivial.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 617120c8284c2abd054600207bd858a04d19b34d
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Aug 28 23:11:29 2008 +0000

    [PATCH]: libpayload:  Document readline
    
    No code changes.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e2ad80628581273558b59ea70d8e155ba567f76b
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Aug 28 23:10:55 2008 +0000

    [PATCH]: libpayload:  Document include/libpayload.h
    
    No code changes.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f0507418857fdc6aa4f473906b51834cddffb94
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Aug 28 23:10:25 2008 +0000

    [PATCH]: Libpayload:  Remove static variables from the doxygen output
    
    No code changes.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d39aad932385d46f67008f5fa3ad8c83c995bb99
Author: Ed Swierk <eswierk@arastra.com>
Date:   Thu Aug 28 18:23:58 2008 +0000

    Add definitions for DDR2 SPD registers.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7eda890d9af652558b0e710b9d17c8915ab3421a
Author: Ed Swierk <eswierk@arastra.com>
Date:   Thu Aug 28 18:22:40 2008 +0000

    Eric Biederman believes that he and Tom Zimmerman of the defunct
    LinuxNetworx own the copyright for the Intel e7520, e7525 and 3100
    raminit code.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a48bdcd361c2ee1c822e07b0db97a61eddc8572
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Aug 28 16:53:24 2008 +0000

    libpayload:  Expand doxygen definitions
    
    Expand libpayload.h to include a main page and add individual
    groups for the API functions - this adds the Modules tab to
    the doxygen output.
    
    Specify the INPUT list rather then the EXCLUDE list of directories
    to omit random .c files that we don't want.  Add clean targets to
    the makefile to clean doxygen files only.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9368e4c9919c0e6f834f1ac8e9e4d48bcf30dac3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 28 15:20:42 2008 +0000

    fix libpayload build dependencies (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b1b1d70d78791a0358258cc8e1aab39537a17a2a
Author: Mats Erik Andersson <mats.andersson@gisladisker.se>
Date:   Wed Aug 27 22:25:55 2008 +0000

    Capture output from  'ld --help', in order that the test
    becomes meaningful. The linker puts help texts on stderr.
    
    Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec2bd53c3776e928a9c7e0b9e8a26886b5fc9182
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed Aug 27 21:53:11 2008 +0000

    If you have
    
      option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
      option CONFIG_PRECOMPRESSED_PAYLOAD=1
    
    set in Config.lb but accidentally use an uncompressed payload, coreboot (v2)
    bombs out like this:
    
      elfboot: Attempting to load payload.
      rom_stream: 0xfffc0000 - 0xfffdefff
      Uncompressing to RAM 0x01000000 Decoder scratchpad too small!
      Decoding error = 1
      Unexpected Exception: 6 @ 10:04000408 - Halting
      Code: 0 eflags: 00010057
      eax: 00000101 ebx: 04000400 ecx: 000003d4 edx: fffc0000
      edi: 04000400 esi: 04000401 ebp: 04000400 esp: 0013dfb4
    
    The attached patch modifies v2's lzma code so that it assumes an uncompressed
    payload if it fails to find a properly compressed payload.
    
    Compare with the fatal error above:
    
      elfboot: Attempting to load payload.
      rom_stream: 0xfffc0000 - 0xfffdefff
      Uncompressing to RAM 0x01000000 Decoder scratchpad too small!
       olen = 0x00000000 done.
      Decompression failed. Assuming payload is uncompressed...
      Found ELF candidate at offset 0
      header_offset is 0
      Try to load at offset 0x0
    
    If you don't have CONFIG_COMPRESSED_PAYLOAD_LZMA and
    CONFIG_PRECOMPRESSED_PAYLOAD set and use an uncompressed payload, things are as
    before:
    
      elfboot: Attempting to load payload.
      rom_stream: 0xfffc0000 - 0xfffdefff
      Found ELF candidate at offset 0
      header_offset is 0
      Try to load at offset 0x0
    
    One can argue that this is a case of 'builder beware', but my counter argument
    is that anything that causes unexpected runtime breakage is really, really,
    really bad, and should be avoided where possible.
    
    This patch also fixes one erroneous comment.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98829def77291303e65e6b64374aab80d1e0b6a1
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Aug 27 21:28:41 2008 +0000

    flashrom: SST25VF016B TEST_OK_ PROBE READ ERASE WRITE
    
    Per test report from Ward.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b6412985b397a51f6640eb57b2152fdc4174251
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Aug 27 12:53:47 2008 +0000

    Add a Doxygen config file and a Makefile target 'doxy' or 'doxygen' which
    generate API documentation (HTML) for libpayload in a 'doxygen' subdirectory.
    
    A 'make clean' will remove this directory again.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b9d1b83ab792b0e0b574069924287364e91a723
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 26 21:51:04 2008 +0000

    fix string function prototypes in libpayload according to sysv/4.3bsd.
    Discussed on IRC, trivial
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54ec0afc1c5fa711d94e5e22b05f3bd7abfaab72
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Aug 26 19:37:37 2008 +0000

    Fix some Doxygen warnings and/or typos (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d129fe2db0b8f7dab253768b8635f4c3c8c0f64
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 26 11:18:38 2008 +0000

    How could -ffreestanding slip through here. Required because libpayload is not
    going to run under an OS. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6adfaa690ce918a35098b2b91028f20298b974aa
Author: Ed Swierk <eswierk@arastra.com>
Date:   Mon Aug 25 17:02:09 2008 +0000

    This patch adds PCI device IDs for the Intel EP80579 Integrated Processor,
    and renames some existing macros for clarity.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c66c957879e6569770cf420b8b916ed8414747e
Author: Ed Swierk <eswierk@arastra.com>
Date:   Mon Aug 25 14:45:00 2008 +0000

    This patch modifies the Intel 3100 southbridge code to recognize the
    integrated LPC, SMBus, USB and SATA devices of the Intel EP80579
    Integrated Processor.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 19963137568738850f786abd030d81f2f0ec5bba
Author: Ed Swierk <eswierk@arastra.com>
Date:   Mon Aug 25 14:41:11 2008 +0000

    This patch implements support for the CPU core of the Intel EP80579
    Integrated Processor.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b0d3e712738293293f07764efbda8b1551333f72
Author: Jakob Bornecrantz <wallbraker@gmail.com>
Date:   Sat Aug 23 12:17:46 2008 +0000

    A missing semicolon prevents libpayload to compile, this patch fixes that.
    
    Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b461b6b78c47f6fc32a94f2141dd1847eeed8da
Author: Ed Swierk <eswierk@arastra.com>
Date:   Wed Aug 20 20:31:41 2008 +0000

    flashrom: Recognize the Intel EP80579 LPC flash interface.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2319027d7e3a9b44110794a553b10a554fed1102
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 20 13:41:24 2008 +0000

    split the one file, as the several printing functions will continue to grow
    immensly when they know more systems / cpus / chipsets
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb02f45e6ff2a6870353816712ff6271250dc7ee
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 20 12:42:39 2008 +0000

    use seperate array for core 2 cpus (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 49f8df75072d956575b2960f411f89b5ea5bb31f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 20 09:17:30 2008 +0000

    this port seems somehow broken.. Now, is it using FAILOVER, or is it not?!
    
    ./s2912_fam10/Options.lb:default FALLBACK_SIZE=ROM_SIZE-0x01000
    
    Please, someone with the board test this and fix it accordingly.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f83325ddf9178ff11cf63dedbc2f5644e279038b
Author: Sean Nelson <snelson@nmt.edu>
Date:   Tue Aug 19 21:51:39 2008 +0000

    Add support for MSI KT4V to flashrom. The KT4V is autodetected and supports
    the KT3 Ultra 2 with "-m msi:kt4v" (but is not autodetected, yet).
    
    Signed-off-by: Sean Nelson <snelson@nmt.edu>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 989c17810b9a8b3ac9fe848aa71d105875f025b9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 19 19:18:58 2008 +0000

    trivial fix for memcpy return code in case someone uses it.
    
    Thanks to Ulf Jordan for figuring this out!
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 33e6d5dec6ef92947ba0c9d6a5197b1869cf89f8
Author: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Date:   Tue Aug 19 17:59:34 2008 +0000

    Add Tyan S2912 platform with AMD Family 10 support.
    Thanks Arne. Good job.
    
    Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34b9f867cdfe466e17da0e418b1746a517ed7256
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 19 17:51:30 2008 +0000

    misc fixes:
     * give struct memrange a name
     * add explicit cast.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99c085690365fa7af18863be292d7ada32fcf53a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 19 17:49:53 2008 +0000

    make all drivers relocatable. Per default, an 1:1 mapping is assumed.
    Patch to add relocation to libpayload will follow.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit addf443e1206f04e46828ac4f19a04788a8046fc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 19 17:48:02 2008 +0000

    * add readline()
    * add fatal()
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e51ceeb2b5eb585fcb244d50b90eb16e97b0fba
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 19 17:47:18 2008 +0000

    * add readline()
    * add fatal()
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e4671e30575ac0f12c482d128a146d85dd27987
Author: Patrick Georgi <patrick.georgi@coresystems.de>
Date:   Tue Aug 19 17:46:02 2008 +0000

    replace static functions by macros, because otherwise every unused function
    would warn. Bad thing for all -Werror folks out there.
    
    Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59fb9a2bfa704422aa3ed64bd21d32bc18c64aa9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 19 17:44:49 2008 +0000

    add functions to query cursor position to video layer
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96f57aee0ac571378ee29d1a27a24114ea10a1c3
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue Aug 19 16:55:05 2008 +0000

    libpayload:  Fix the memcpy functions
    
    There was a bit of confusion in the memcpy functions - we could simplify
    things slightly without having to revert to 8 bit copies on a 32 bit
    system.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3519 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0740cdaac9e7bf37492988af31f85bb7898bc327
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 19 16:53:47 2008 +0000

    fix typo in ctype.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2aea11f57f3163ef12e71074eaaaaf4cb566836a
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Mon Aug 18 19:29:41 2008 +0000

    Add a kconfig option to choose between outputing ACS characters or
    their plain ASCII fallbacks over serial console.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 364317b1991cf5daa08ad3ce4e52e735c9789987
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Mon Aug 18 19:28:42 2008 +0000

    Fix tinycurses color output on the VGA console.
    
    The CGA compatible 16 color VGA text mode expects Intensity RGB color
    specifications, in the order IRGB from most to least significant bit.
    Curses COLOR_ macros follows ANSI X3.64/ISO 6429/ECMA-48, specifying
    RGB color in the order BGR from most to least significant bit.
    Consequently, it is necessary to swap the red and blue bits.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3516 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43a800c55ff672e859fffcc17841ebed1c28693e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Aug 18 18:55:33 2008 +0000

    Add more information to the libpayload README (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26ba091d5127315a651d7d165d76eb6f197f3198
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Aug 18 10:58:09 2008 +0000

    inteltool: match cpuid before attempting to print MSRs (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f394c7593f21edcce71f287e12ba61072203ea3d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 16 15:17:36 2008 +0000

    add block io functions
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 11e45cd3ff43401e4eb8a58b71638b6922d4595c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 16 15:16:36 2008 +0000

    trivial fix: ipchksum takes an unspecified input blob, not explicitly a number of shorts.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 67b35cb163debfbc0bfec6e7d252b23eebca51a8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 15 09:46:55 2008 +0000

    fix typo in superiotool (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ee673194b45efda3e21507d57ef11ba190e9a502
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 14 14:40:10 2008 +0000

    * fix memory allocator bug that lead to freelist corruption on the first malloc
      (and spent 8 bytes too much per malloc)
    * if the memory allocator detects freelist corruption, print a message
      instead of silently dying.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e65adb67d9d85e920554af7b083b3d76b885688
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 13 12:16:15 2008 +0000

    Fix outb to 0x80 delay functions to use inb instead (fixes excessive post codes
    in a couple of occurences)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc5379aefd56b270ffde15572ba0b30c16c24b38
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 13 09:38:12 2008 +0000

    off by 1. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3508 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 28dff395efb03e7db0863dd3e378cea8eee1ce94
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 13 08:23:06 2008 +0000

    commit real fix to pci module of coreinfo (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87f0b13256b788cfa46b48587e77027cfc4dceb9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Aug 13 08:21:27 2008 +0000

    add PCI_BUS macro (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74eedaee8d69df8b4c03879cfacb4634149797f9
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Tue Aug 12 20:23:00 2008 +0000

    Fix incorrect mapping of ACS_PI for VGA console. A pi should look like pi and
    not like Gamma.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b86507002304756a5d4aaba18d40fe23cf82d5b6
Author: Marc Jones <marc.jones@amd.com>
Date:   Tue Aug 12 19:45:12 2008 +0000

    License updated to GPL v2.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96b734ceca4edcf100400044075fb69f16740ec9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Aug 12 14:19:40 2008 +0000

    libpayload: fix type in keyboard driver. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 716c7204685b65707f83956bbae8bd3e338f9286
Author: Segher Boessenkool <segher@kernel.crashing.org>
Date:   Tue Aug 12 11:58:00 2008 +0000

    flashrom: Fix error -EINVAL on mmap()
    
    Don't calculate "flash_baseaddr" until the final value of "size"
    is known, otherwise we end up trying to map a page right after
    the end of memory.
    
    Fixes #112.
    
    Signed-off-by: Segher Boessenkool <segher@kernel.crashing.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d133d9a23077e30f57014ab84633b7a0c4dc2518
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Mon Aug 11 20:35:32 2008 +0000

    This patch updates coreinfo to use the ACS_ macros for line graphics.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc8a9934dff6d5b2c219f4cf3ba37988a56087b7
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Aug 11 20:34:50 2008 +0000

    Document all of the external code we use in libpayload (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b4d4bac1c49d7e19dac6f29ea278df8be6e6dcd2
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Mon Aug 11 20:34:28 2008 +0000

    Add support for line drawing characters and the alternate character set.
    This enables using the ACS_ curses macros with libpayload.
    
    The translation from ACS_ macros (or characters with attribute A_ALTCHARSET)
    is done using one acs map for the video console, one for serial console
    (xterm/vt100/vt220), and one fallback, from which an ASCII substitute is
    taken if the device specific map doesn't contain an entry (ie NUL).
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42a0c80b9babaaf93ca806dd9bae4a4cc5a8936f
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Mon Aug 11 17:19:10 2008 +0000

    Make cursor positioning work by using both halves of the VGA cursor
    position register.
    
    Have vga_scroll_up() and vga_clear_line() present row/column arguments to
    the VIDEO() macro in the right order.
    
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12e27266c3cb9bd1499731a5c52da7ce565d7912
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Aug 11 17:10:58 2008 +0000

    No really, _these_ should be the last occurences of CONFIG_ without
    config.h in libpayload - also removed CONFIG_ instance in libpayload
    which would have been dangerous.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e354b7a43df8626216a5dc3b94d65a590a25349
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Aug 11 16:58:23 2008 +0000

    these should be the last occurences of CONFIG_ without config.h in libpayload.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 663ea08ef155db78e4080036649ed8095ecd7e5e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Aug 11 16:55:35 2008 +0000

    these use CONFIG_ variables, too.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb7a7c6b8c870dce9a63ba2769395ce06681e0ba
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Aug 11 16:52:14 2008 +0000

    video.c uses CONFIG_ variables, so it needs config.h (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b96a2ffaa78ff5d693daf98829b4bb9dac0a6731
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Sat Aug 9 20:17:22 2008 +0000

    Bugfixes to serial output functions: vt100 has bold with \e[1m,
    upper left corner is (0,0) in curses, but (1,1) on the vt100.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c5c1442fab2f524e32c41ef528e159af79d04af0
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Sat Aug 9 20:15:00 2008 +0000

    Fix garbage characters on screen. mvwaddch inserts one character,
    not a character array.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68285699da68490681b330f0d345079b231c11cf
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Sat Aug 9 19:34:56 2008 +0000

    Fix signedness problem in memcmp.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f1e127472bee89453a2962e7cf383bcb112449b9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 8 18:36:14 2008 +0000

    i messed this up.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7e92b3cfece10ac8a5ff32ac3113d3f3b357372
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 8 14:17:46 2008 +0000

    compile fix (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6986358341072299b5debb7fb29d183b1993b259
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 8 13:45:03 2008 +0000

    new menu structure for libpayload
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fef915c7c4540ffb890c20d4db0e71ac69175652
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 8 13:36:53 2008 +0000

    fix some more warnings.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d00bdd08133f52b3301590e924b7dd9ec60be4dc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 8 13:07:38 2008 +0000

    fix warnings when starting make menuconfig
    (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e6e98a518c91f086ee873ca85e7962a6f35538c
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Aug 8 10:55:57 2008 +0000

    flashrom: ST M50FW040 TEST_OK PROBE READ ERASE WRITE
    
    Per test report from Marcel Konrad. Thanks!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e4df11d81f8429b740342ae6e846a47ac3d3a83
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Aug 8 08:43:06 2008 +0000

    Drop useless .gitignore files.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31a4f7bc5d477ad7ba1509d3ac57ba4c5cb52437
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Aug 8 08:42:05 2008 +0000

    Drop useless .gitignore files.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e55b32ab627bac2108efb4a3d5b924e00ff60af9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Aug 8 07:56:07 2008 +0000

    Update the kconfig copy in libpayload to a much more recent one. Among
    other things this supposedly also fixes a number of build issues on Mac OS X.
    
    This is more or less the same version (i.e. equally recent) as we have in
    coreinfo and buildrom now.
    
    This patch also includes the libintl.h fix from r3475 (coreinfo).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc93affe72b4e3162fde653da5c0ea0c84bd5e39
Author: Ward Vandewege <ward@gnu.org>
Date:   Fri Aug 8 00:08:01 2008 +0000

    Enable both IDE ports for our qemu target.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a2c951edf7de94d64acd31e20b3fea7d3e869069
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu Aug 7 22:00:51 2008 +0000

    Clean up whitespace and comments style. (trivial)
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88ad6b0f919bcb3b86e0a91c903be26934097125
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 7 19:09:17 2008 +0000

    Add a full set of pci access functions.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85c7aec73ea37136a158fd7fd98249ddedaffba5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 7 15:28:31 2008 +0000

    fix stack protection detection with Jordan's suggestion
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c359124ef465e714f1cd7c6ad31429071847b074
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 7 15:22:01 2008 +0000

    fix cross compilationor libpayload / coreinfo by honoring
    the setting of CC in the payload (coreinfo) when calling
    
    make CC=i386-elf-gcc AS=i386-elf-as AR=i386-elf-ar STRIP=i386-elf-strip
    
    This still does not cope with the hardcoded -fno-stack-protector in
    libpayload's Makefile.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 695cff30e1e550f9492a365fe1109934a1a729e7
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Aug 7 14:35:39 2008 +0000

    Cosmetic fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b17bd31363dc5ccf0a680af289fa3ab77c84fd6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 7 10:32:54 2008 +0000

    fix make menuconfig if no libintl.h is found. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 95a6e1cab25abbae51dd2c02cd9158f53a0212a7
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Aug 7 10:21:05 2008 +0000

    add get_option to libpayload, so coreboot cmos options can be queried.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebc92186cc9144aaacd37ca1ae94fcff60ec577a
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed Aug 6 20:37:38 2008 +0000

    Add the contents of buildrom's
    
      packages/mkelfimage/mkelfimage-autoconf.patch
      packages/mkelfimage/mkelfImage-2.7-x86_64.patch
    
    to our svn copy of mkelfimage.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    These are the original commit messages from the buildrom svn tree:
    
    -----------------------------------------------------------------------
    r61 | jcrouse | 2007-11-28 13:06:23 -0500 (Wed, 28 Nov 2007) | 9 lines
    
    [BUILDROM]  Fixup mkelfimage
    
    My patch makes it so all targets use vmlinux and 2.7.  Including
    the mkelfimage patch from Yhinghai Lu.
    
    Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    ------------------------------------------------------------------------
    r80 | jcrouse | 2007-12-10 13:56:40 -0500 (Mon, 10 Dec 2007) | 8 lines
    
    [BUILDROM] Fix breakage in the new mkelfimage autoconf scripts
    
    Whack the autoconf scripts in mkelfimage to allow us to pass our
    stack protection flags in.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    ------------------------------------------------------------------------
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a70872cfde84863637dba1fb00498dc8a61dba48
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Aug 5 14:36:20 2008 +0000

    Move out some hardcoded strings in coreinfo to become Kconfig variables.
    This is useful for use with (e.g.) Bayou in order let the user customize the
    payload name, description, version, etc.
    
    For instance, instead of using stock coreinfo and calling the payload
    "coreinfo" and the Bayou menu item "Show system information" a user might
    only be interested in an NVRAM dump payload. Thus, he/she can enable
    only the NVRAM coreinfo module via Kconfig, and tell Kconfig to call
    the payload "NVRAMdumper" and the Bayou menu item "Show NVRAM contents".
    
    This is build-tested, and tested against Bayou in QEMU.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 754edf712cc5ee4a8014dc115ee18bb9126cbb64
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Aug 4 21:02:07 2008 +0000

    Remove duplicated code which is already in libpayload (trivial).
    Build-tested against the latest libpayload.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 83233d0a15fd7a03026e50441383d3de86a49294
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Aug 4 21:00:49 2008 +0000

    Add missing #include.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f1037cb694e4260c237fa022f9ec4b965a29b93
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Aug 4 15:40:45 2008 +0000

    Initial support for the ASI MB-5BLGP (Neoware Eon 4000s).
    
    This works fine in Linux if you use the 'irqpoll' kernel command
    line option.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ecf8fb1cf39ac093bfd38125f6048dc0e9554d8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Aug 3 10:38:26 2008 +0000

    Remove welcome message from elfboot. None of the other subsystems have their
    own welcome message.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 912857ec6c0995281460260de8da9f19277eb2f3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Aug 3 10:35:06 2008 +0000

    fix lots of warnings for cache as ram builds (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87c938f139b14a2e0b7fbfa6476c3caaa953e968
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 2 19:17:42 2008 +0000

    adapt Uncompressing.. patch for AMD code. Also replace "linxbios" by "coreboot"
    in a number of places.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 685240610b22f8e5f82204e526c6b8a8d6657173
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 2 15:15:23 2008 +0000

    Go back to SIPI WAIT state for those CPUS defining the newly introduced
    CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with
    multiple cores.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab8bb8b06128057e9816661ad7a3d386d3f8b92f
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 2 15:13:58 2008 +0000

    update copyright year (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a56edacbe3d142882c1be88d998a73f6f0eaf1ec
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 2 15:09:12 2008 +0000

    This patch
    * fixes a warning
    * puts some debug messages to spew because they're only useful to debug CAR
    * print an explicit message "Uncompressing..." instad of "Copying..." when
      coreboot_ram.rom is compressed.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42fb71f6263bc0fc47b44153e9d03481645f1909
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Aug 2 14:58:49 2008 +0000

    tested another intel chip (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit db1b608fca22627bcf485bd772654dbfc43fe5d3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 19:22:34 2008 +0000

    oops, forgot these in the cleanup..  (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 11a2014f49d4161de975145109bb18b5bc890472
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 13:08:33 2008 +0000

    a heuristics is something different
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 75f519ca86f384fc683d12baddcae95d18ec32a0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 12:53:04 2008 +0000

    Typo, thanks to Idwer for spotting this. (trivial patch)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 51754a38f2a121c78ffaaa3de9b20a252fcbddbe
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 12:28:38 2008 +0000

    clarify in the printks what function is actually called. This little smart magic
    drove me crazy during debugging. Fix Typos. Add a warning because the
    on-chipset devices are hardcoded. For newer machines, a lot more memory space
    will have special meanings, and we can't hardcode them all in an ifdef desert.
    
    (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1409136281288cfecf47091b9126d05dfbcd1e02
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 12:20:26 2008 +0000

    clean out obsoleted config.lb rules and output, fix indenting (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48b85fc6a941f662ca62c954fbb8c32e9e8c117b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 12:12:37 2008 +0000

    use printk, when possible. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a522d4a42a8fe9da6fef8bab5b47df42a8f722d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 12:11:00 2008 +0000

    match against all steppings of a CPU model, because these are _model_ drivers.
    (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ac555b1c69a094929cdf057b718446b85cc01518
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 12:06:08 2008 +0000

    serial.inc is not used anywhere. drop it (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57d2af895ee342c30fe7567bcd47dd0dceb09e91
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:54:55 2008 +0000

    same spelling in all mtrr output.. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df6c8582182e7989a36c871e40b5b97b708c17b1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:53:39 2008 +0000

    drop unused code (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96a60363f896ed4c21ef8af629b2c8eb92486d93
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:50:52 2008 +0000

    coding style fixes (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20ffc03efaea79a74bdb82adb5be67a58afe2e64
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:48:00 2008 +0000

    fix compile warnings of rom_stream.c (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 951c62f07455724913171451b5689e40cb565199
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:40:16 2008 +0000

    add some SPD values from specs. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a91e0fe4410c0cac54ce14f6ebd5371829ed0500
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:39:35 2008 +0000

    function prototypes don't need extern. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 749c05e0fd0aff1ba9d85138ec472f8b14457375
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:38:23 2008 +0000

    fix warning in vga console code (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fec2c4f47fde15d4731d448faa9dfa3a3230a307
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:37:33 2008 +0000

    fix typo in coreboot_ram.ld comment (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bba53ed1a7dd9199f54e8cd188bbe34f83630163
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:36:40 2008 +0000

    fix typo in commend of generic_sdram.c (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c580b539e5928de7ffed6152a2e28950d28bcb3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:35:46 2008 +0000

    clean up comment in onboard.c (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 807dec0ebcbbcaf2d531717455dc0de69e3e8d62
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:32:12 2008 +0000

    clean up Config.lb in lib/ (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a4f688f4fa63d25d3124b5af4c21b5b499fe5c2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:31:08 2008 +0000

    fix warnings, make mptable struct members explicitly packed, as they're
    supposed to be. rename LXBIOS to CORE in ACPI table identifiers. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d98cf5bed93e48f4cb3bdc5219a03207cd01c3ce
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:25:41 2008 +0000

    fix typos and warnings in the device tree code (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8533606db71ef9c4f77983eaea1b2f27c9bb7baf
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:21:47 2008 +0000

    CONFIG_LOGICAL_CPUS=2 does not make sense because it is a BOOL. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 62ab563ae1c771a4c0a95758d75425a900f832b4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:20:33 2008 +0000

    fix build warnings for buildrom (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e4954cd3f15a74b93e1414f8d9467b2abc0369c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Aug 1 11:20:09 2008 +0000

    fix typos in config.g, and don't arbitrarily hide some build information
    (doesn't make sense in v2). For silent build, use make -s
    (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96e3022cd411db8070716fbc324f8c60137dcfc3
Author: Roman Kononov <kononov@dls.net>
Date:   Wed Jul 23 23:22:59 2008 +0000

    This patch fixes the kernel EBDA mislocation problem. Thank you, Yinghai.
    
    The change in tables.c protects the legacy x86 BIOS data segment
    (0x400-0x4ff) from being used for storing coreboot tables. Some
    bytes from the segment are used by the kernel and should not be
    garbled.
    
    The change in coreboot_table.c is not strictly necessary. It removes
    some redundancy and confusion.
    
    Signed-off-by: Roman Kononov <kononov@dls.net>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2aa804fdccd978afc7ce4d7e5aa86cccc7e4d94e
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Jul 23 22:27:19 2008 +0000

    Fix r3434 check-in. Added missing end to Options.lb. Not entirely sure how it
    went missing....
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 35b53616366326bf39ece92109e0c66f03b2ef11
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Jul 23 21:44:23 2008 +0000

    Add AMD Fam10 B3 default settings to match AMD example code.
    Includes setting for most recent errata.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 51737cf7da3eee6df5959c8181a49c115368e909
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Jul 23 21:11:20 2008 +0000

    Update to the latest AMD Fam10 microcode patches.
    Add platform option for patch file name.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3ec1ac331e9b9338e3804f5cdd02ed177827da4
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Jul 23 21:04:03 2008 +0000

    Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a8556354d185ddbc320f3687d745b52bf0aa195
Author: Marc Jones <marc.jones@amd.com>
Date:   Mon Jul 21 22:23:57 2008 +0000

    Missed a const in my previous checkin, r3426 (trivial).
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec9e6e33a4d08c4b5afcc51cc5a964e1208731fc
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jul 21 17:48:40 2008 +0000

    flashrom: Winbond W39V040C and MSI K8T Neo2-F
    
    W39V040C does standard JEDEC commands except chip erase so add a small driver.
    probe_w39v040c() prints the block lock pin status when a chip is found.
    
    The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs.
    
    Many thanks to Daniel McLellan for testing all of this on hardware!
    Build tested by Uwe.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d135e603343431aaef3ed770ddf16fcef4847ad
Author: Sean Nelson <snelson@nmt.edu>
Date:   Mon Jul 21 14:49:04 2008 +0000

    Add support for the Winbond W83697HF Super I/O.
    
    Signed-off-by: Sean Nelson <snelson@nmt.edu>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3f057935c8a4929a76f54e8d30900eb2a6e9a0a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jul 19 14:42:21 2008 +0000

    superiotool: add support for SMSC SIO10N268 (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a12eb6a7e5154047cee12f9a7e70bf7947cfadaa
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jul 19 14:07:35 2008 +0000

    add support for 2 new SMSC superio chips. Information is a bit ambiguous
    and scattered within the datasheets. (trivial patch)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 941aaee885b27e5e897c056ea804e3d1e221a788
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Jul 18 14:08:18 2008 +0000

    Random coding style fixes and simplifications (trivial).
    This will even reduce the final payload size a bit.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eafceddf6c224d678d0d48a84db4e3bc493b5d2d
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu Jul 17 19:54:06 2008 +0000

    Add manual HT BUID fixup to detect previously set BUIDs in early init. This fixes the non-coherent(sb) link running at default speed.
    
    Fix HT event notify to output useful information.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 212486e9f634f6a6aaf1efdacfb39397c19a7bc7
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu Jul 17 19:50:37 2008 +0000

    Clean up AMD FAM10 HT variable initialization. The structure init is cleaner, avoid compiler warnings, and matches the AMD example code more closely.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2df291574dd16038714091ac44f0d602c764c17d
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu Jul 17 19:44:08 2008 +0000

    Add Fam10 Gart table walk enable for MCA reporting to match AMD example code.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aee0796506b179ae35f962b67d429abe8b5dcf9d
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Jul 16 21:09:31 2008 +0000

    Clean up comments, whitespace, and copyright date in the AMD HT code.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 049814cc8f18872a33530e17a66cd14f346c52ee
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Jul 15 13:22:21 2008 +0000

    Add missing Intel CPU (trivial).
    
    Tested by me on actual hardware.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c39c4c5a9cf767eaf92d5961c3fd2e7b60811b4
Author: Marc Jones <marc.jones@amd.com>
Date:   Sat Jul 12 00:03:26 2008 +0000

    There was a programming error which made most USB port4 setup wrong. This patch uses byte pointer and the MMIO read and write functions.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f45e770d7a16a37d6667dc3bd4a8c1a51cfbbe5
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Jul 11 00:06:38 2008 +0000

    Fix and clean up coreboot image detection heuristic.
    Additional compile fix for NetBSD.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2fbbb29e54ee6a28461ea130e02eeee2984edb22
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Jul 8 16:18:38 2008 +0000

    Add a coreinfo module which can hexdump arbitrary RAM regions and
    allows you to scroll through the RAM contents.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4793182e892c71660e24dbe12198a653f7ec1e6
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jul 7 06:38:51 2008 +0000

    flashrom: Trivial SPI cleanups
    
    While writing a new SPI driver I fixed some things in the SPI code:
    All calls to spi_command() had unneccessary #define duplications, and in some
    cases the read count define could theoretically become harmful because NULL was
    passed for the read buffer. Avoid a crash, should someone change the #defines.
    
    I also noticed that the only caller of spi_page_program() was the it87 driver,
    and spi_page_program() could only call back into the it87 driver. Removed the
    function for easier-to-follow code and made it8716f_spi_page_program() static.
    The ichspi driver's static page functions are already static.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5dc95de5e64638d5b95d7fd1fb7ef87887bfdbdc
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Jul 7 05:14:06 2008 +0000

    flashrom: Trivial indent fix in ichspi.c
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5bc95858d5262d68e16c61cfef3bb309f1826c69
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sun Jul 6 23:04:01 2008 +0000

    r3415 removed symbolic constants for device IDs by accident.
    flash.h is a database of known IDs, whereas flashchips.c is a database
    of chips for which support has been implemented. Keep it that way.
    
    Trivial.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce17f6bdb07e9348b6f6dda156e4a0edce8f12eb
Author: Andreas Thienemann <andreas@bawue.net>
Date:   Sun Jul 6 17:35:30 2008 +0000

    flashrom: Add AMIC A29002
    
    This patch adds support to the AMIC A29002 chip in its top and bottom
    configuration to flashrom. Additionally, the alphabetic order of the
    AMIC chips was fixed.
    
    The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>.
    
    A29002T PREW functionality was tested and works.
    
    This flash chip has asymmetric sector layout so it is important to use the
    mx29f002 driver, which does chip erase before writing, rather than am29f040b,
    which uses sector erase.
    
    Signed-off-by: Andreas Thienemann <andreas@bawue.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c75baea46f0037f1526a19cb5d75413e7d8a2f2
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jul 5 09:48:30 2008 +0000

    Adding support for flashing system with Nvidia MCP67
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e9dcb8931e7dd8374a1efce2a3bb5552f14417d8
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jul 5 04:12:37 2008 +0000

    flashrom: Add PCI IDs for EPIA-CN
    
    Uses the 0.0 Host bridge CN700/VN800/P4M800CE/Pro and 11.0 ISA bridge devices
    with their 1106:aa08 subsystem id:s for autodetection.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a20cdec2c360b401ffce5b90e74e31b0dcd80cc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Jul 3 19:26:44 2008 +0000

    Minor cosmetics, e.g. make stuff fit in 80 chars/line etc. (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3244b984e26652eb79b682493707a8c4840586bd
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Jul 3 19:08:52 2008 +0000

    Mark SST49LF040B as tested.
    Thanks to Paul Seidler and Ward Vandewege for testing.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4321f8be6e745f37db16ff06a6e73c3218c2bf2a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Jul 3 18:58:58 2008 +0000

    Mark the SST SST49LF040 as OK (tested by me), all operations (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8fe1a42e7dc42ab54ed342386c4504f52b8a04c4
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Jul 3 16:54:05 2008 +0000

    flashrom: Winbond W25x80 TEST_OK PROBE READ ERASE WRITE
    
    Per test report from Björn Gerhart. Thanks!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 039b8480664d8b709b7d5806b627e6f876afdb67
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Jul 3 14:40:06 2008 +0000

    Improve coreboot image detection heuristic in flashrom. It's not
    absolutely perfect, but the likelihood of this check to fail is
    0.000000000000000000000000013 (1.3*10^-26) which is good enough for me.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f74c208256003d5c52f2f40480bec1f755c8ee9f
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Jul 2 17:15:47 2008 +0000

    flashrom: probe_flash() cleanup for better code readability
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cac7286c0b4e4b188ae511a66d60e5e3d9af97fd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jul 2 13:33:09 2008 +0000

    set w39v080fa to fully supported. I'm am flashing this chip several times a
    day.
    Also enable unlocking which is only needed when running coreboot, that slipped
    in the original commit and through the original review ;-) So it must be
    trivial enough.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3c4472bd1dc2603b9e1a795e9809452a765e950
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Jul 2 03:07:46 2008 +0000

    flashrom: Update to TEST_OK for Winbond W39V040FA PROBE READ
    
    Thanks to Jake for the test report!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1ae669771c916363023f01aae806f69dff35d81a
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Jul 2 03:03:58 2008 +0000

    flashrom: Don't rm *~ in make clean, who knows what files that could be
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39a582569a16b42588c69dc2b670d4b27cf71ee2
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Jul 2 00:59:29 2008 +0000

    flashrom: Unknown vendor:board message can be triggered by -m too
    
    Thanks to Stefan for pointing this one out.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12224acb6f1e50f5ad848c433c1269244d3d03ad
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Jul 2 00:47:30 2008 +0000

    flashrom: Case insensitive matching of vendor:board strings in coreboot table
    
    Needed at least for GIGABYTE:m57sli in coreboot to match gigabyte:m57sli in
    flashrom.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9b7ae8becf903e1cb9d66a194f098fd9644b49a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Jun 30 23:45:22 2008 +0000

    First attempt to clean up SPI probing and create a common
    construct: the flash bus.
    
    At some point the flash bus will be part of struct flashchip.
    
    Pardon me for pushing this in, but I think it is important to beware of further
    decay and it will improve things for other developers in the short run.
    
    Carl-Daniel, I will consider your suggestions in another patch. I want to keep
    things from getting too much for now. The patch includes Rudolf's VIA SPI
    changes though.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e16d43c041f0de4b9be0d78e632e968ad865b75b
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Jun 30 21:48:54 2008 +0000

    Mine AMIC flash chip needs 4 bytes RDID. This enables to use the new probing code.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8a7e7d043db8395c03aeeb23849a73ab066af8a
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Jun 30 21:45:17 2008 +0000

    Mine AMIC flash chip needs 4 bytes RDID. Following patch adds support for that.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a17e02003f40495b37393b017e7c9ea4bb85638
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Jun 30 21:38:30 2008 +0000

    This patch adds support for VIA SPI controller on VT8237S. It is similar with
    few documented exceptions to ICH7 SPI controller.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b425c1c1115f258107bad368a1b1f7345a7254b
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sun Jun 29 10:57:13 2008 +0000

    Add a debug marker after ICH SPI opcode programming.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c2e8fd42b0f2d411d00893aa6e697685e345e9e6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Jun 29 06:41:12 2008 +0000

    Adds a field to the serial port descriptor about the configured line speed.
    
    Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 891f1a2650c5b32c65103fa9a5659953fab34157
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jun 29 01:30:41 2008 +0000

    flashrom: Fix ICH7 non-SPI that broke in r3393
    
    r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back
    to 0 when BOOT BIOS Straps indicate something else than SPI.
    
    Also fixes a build error in ichspi.c with gcc 4.2.2.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50e4a095ddff2efd3b780d585960fa928a6d93bb
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sat Jun 28 23:02:22 2008 +0000

    Use symbolic constants for PCI subsystem probing in flashrom.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a1dd9142c67a6651a1ea7884aa11ba41b597a1bf
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jun 27 16:28:34 2008 +0000

    * ICH7 SPI support
    * fix some variable names in ichspi.c (Offset -> offset)
    * Dump ICH7 SPI bar with -V
    * Improve error message in case IOPL goes wrong. (It might not even be an IOPL)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20e0599e69785d8aefc97a09cc06468298f241d6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jun 27 15:18:20 2008 +0000

    indent according to development guidelines (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98f32bf8ef697ecb35ffc14a907046e68c752f34
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Jun 26 19:42:25 2008 +0000

    Initial support for the A-Trend ATC-6240 board.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8613d628d538efccb0f19d6f51401ad22a97c8df
Author: Jens Kühnel <coreboot@jens.kuehnel.org>
Date:   Thu Jun 26 11:57:27 2008 +0000

    Winbond W39V080FA: Probe and Read are OK.
    
    Signed-off-by: Jens Kühnel <coreboot@jens.kuehnel.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d1cd7bc054237254e3efe068e827336f11a53a71
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Jun 24 08:18:13 2008 +0000

    flashrom: Test status OK for ST M50FW040 PROBE READ
    
    Per test report from Alex Perez. Thanks Alex!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc64a270be7b2276b5523904f856516faa2f33f0
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Jun 24 04:17:14 2008 +0000

    flashrom: Test status OK for Macronix MX25L8005 PROBE READ ERASE WRITE
    
    Per test report from Andrew Paprocki. Thanks Andrew!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0667afd2948a867754f2c3d6b3e53eeca0092671
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Jun 24 02:09:09 2008 +0000

    flashrom: Increase delay in probe_jedec() after Product ID Entry to 10ms
    
    We should follow data sheet timing, even if chips have been tested to answer
    faster in the field.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 606a207d9be0129296eda235896c9354b4e04e1f
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Jun 24 01:22:03 2008 +0000

    flashrom: Slight restructure of SPI probe_ functions
    
    Preparation for a probe optimization patch. This patch does not change any
    functionality. spi_probe_rdid was tested to still work on my M57SLI rev 2.
    
    The idea is to have error checks return error immediately when something
    fails, rather than having code inside an if block where the condition
    tests for success.
    
    This means: Less indentation, more clear what the code is checking.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12afdd82ac6299d6ec1bb571a8043a61560a2f3a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jun 22 18:50:25 2008 +0000

    Some flashrom documentation fixes, and removal of duplicated info (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f78cd6ebadd14fa7c779fffa2f621c187330ec1
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jun 22 17:54:03 2008 +0000

    flashrom: A few changes were committed before the DoC remove, update README.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b835974cd381b398ae0d5fbd6b7c789ebfd4e39
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jun 22 17:15:03 2008 +0000

    as per Peter's suggestion. clean binary in make clean
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b05b6a2555e04e3af2f62014d373aef64e0e469f
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jun 22 17:06:41 2008 +0000

    flashrom: Remove dead M-Systems Disk on Chip code
    
    DOC support has been disabled by default for many years. The write function
    does nothing but print text. It has a call to write_page_md2802() commented
    out, but that function does not exist. This is dead code with ugly #ifdefs.
    
    Updates README to reflect that there was a time when there was code, but it
    didn't work. Removes M-Systems #defines and also includes svn rm msys_doc.*
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb73fa1bcb3ac3579ad786911c09f05950c8b3a8
Author: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Date:   Sun Jun 22 14:33:17 2008 +0000

    Enable hardware fan control for m57sli.
    
    Tested on v1 and v2 of the board.
    
    Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14669ae023e9bb502866e9a49fb0577870dbda80
Author: Joseph Smith <joe@settoplinux.org>
Date:   Sun Jun 22 04:22:46 2008 +0000

    This patch allows support for multiple so-dimms, single or double sided.
    
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 67939dc75fa9147708251bdd40f1ddb3bf684414
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jun 22 02:04:49 2008 +0000

    flashrom: Update test status to TEST_OK_PREW for ST M50FLW080A and SST49LF008A
    
    Many thanks to Julio Cesar Costa for the test report!
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a6b6711cf78de3dbbad8502d1b6532681bf1cdfb
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jun 22 02:00:39 2008 +0000

    flashrom: Some Makefile cleaning
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8239a1b2fde46b0fb22853de6def52211b0127cd
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 21 04:39:17 2008 +0000

    flashrom: Fix OBJS in Makefile to compile stm50flw0x0x.c like the others
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f10902f390ad1f10aeaa2060e5c42cd8f2fa335
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 21 04:23:10 2008 +0000

    flashrom: Uppercase AMIC since that's what they write in datasheets.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e7d54a5b715757dbcbeba199f02e810dd224ea4
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 21 01:02:20 2008 +0000

    flashrom: Update comment to match delay change in probe_jedec() r3373
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3375 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ad2ef07ff7163571587edbe82471796cfd2400e9
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 21 00:21:22 2008 +0000

    flashrom: Update test status for Atmel AT29C020 and SST29EE010
    
    Thanks to Urja Rannikko for reporting test results with these flash chips.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4ff88b4d49226859ce762acd4cf49c5e98aed12e
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Jun 21 00:19:52 2008 +0000

    flashrom: Increase delay in probe_jedec() to 2ms to reliably detect AT29C020
    
    Run time is increased a few 100ms but this is needed for reliability.
    I consider this trivial.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f2e30c9ed04c617d5af6b5fed22fa82115c8512
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Jun 20 02:58:42 2008 +0000

    flashrom: Show expected and read byte on verify failure. Trivial.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7600c48bf434235c666f60b00fc9375f12ba98f1
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Fri Jun 20 00:02:52 2008 +0000

    coreinfo:  Enable serial support
    
    Remove the lines preventing serial + curses thanks to r3370. Trivial.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b4706591ce3d31628fad8953beba10a97529642
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Fri Jun 20 00:01:42 2008 +0000

    libpayload:  Support curses for serial
    
    Support the curses interface over serial by supporting a minimal vt100
    terminal.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e48408059cb07cf1fbf8f74e61cc9dc7b7cd0bf
Author: Bari Ari <bari@onelabs.com>
Date:   Fri Jun 20 00:01:14 2008 +0000

    Extend the VIA vt8237r southbridge decode range for the ROM to 1MB.
    
    Signed-off-by: Bari Ari <bari@onelabs.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42b127fe2244a037a30c5e0f5c686d4ebb70d62f
Author: Jens Kuehnel <coreboot@jens.kuehnel.org>
Date:   Wed Jun 18 13:36:34 2008 +0000

    flashrom: Add support for AMIC Technology A49LF040A and do not probe W29EE011 anymore
    
    Jens sent the first patch that added A49LF040A to flash.h and flashchips.c
    using _jedec and _49lf040 functions.
    
    An issue was found with probe_w29ee011() for the Winbond W29EE011, which
    caused the A49LF040A to no longer respond to any commands.
    
    Ward made a patch to disable probing by default for the W29EE011 following
    some discussion. Using -c W29EE011 will make flashrom probe for the chip.
    
    Peter did some more datasheet diving and found that the Pm49FL00x functions
    suited this chip quite well because of the block locking registers in
    A49LF040A, and finally tested PROBE READ ERASE WRITE to work on ALIX.3c3.
    
    Ward confirmed that this works on alix.2c3 too.
    
    Signed-off-by: Jens Kuehnel <coreboot@jens.kuehnel.org>
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 646eb245e6fd4f974a0dd3d1e57a1871cc7fb3c5
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Jun 18 02:08:40 2008 +0000

    flashrom: Force read unknown flash chips
    
    When flash chip detection fails, it is still useful and possible to read the
    flash chip contents. If no flash chip is found in normal probes and the
    -f -r -c CHIPNAME options are given, a successful probe for the specified
    chip is forced, and then flashrom reads the flash chip using either the read
    function for the specified chip, or if there is none, a simple memcpy().
    
    The patch also moves the global variable int force in flashrom.c into main()
    and passes it as a parameter to layout.c:show_id(), which was the only other
    function that used the variable. This is needed to avoid confusion with the
    new parameter int force which is added to flashrom.c:probe_flash() and used
    to force probe success for the chip named in char *chip_to_probe.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 01441bd5cfee375c3170da0a34433e176b1796b3
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Jun 13 01:39:45 2008 +0000

    flashrom: Board enable and autodetection for GIGABYTE GA-7VT600
    
    Uses the VT8237 ISA bridge with mainboard subsystem ID and Realtek 8139 with
    mainboard subsystem ID for board detection.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc18fbbc609a1c3408e08ddc9e83da36dd25b81b
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Jun 11 02:24:15 2008 +0000

    flashrom: Add support for Amic Technology A29040B flash chip.
    
    PROBE READ tested by Lyos Gemini Norezel on BioStar P4M80-M4.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d1f698ac277380114d627ad210d13cbbc3b787a9
Author: Peter Stuge <peter@stuge.se>
Date:   Wed Jun 11 02:22:42 2008 +0000

    flashrom: Board enable and autodetection for BioStar P4M80-M4.
    
    Thanks to Reinder for clean room reverse engineering and data sheet diving!
    
    This board is autodetected because there are some good BioStar subsystem IDs.
    Matching uses onboard VT6420 SATA RAID with subsystem BioStar 3206 and
    onboard UniChrome Pro IGP graphics with subsystem BioStar 1202.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d63e0d041e54da63060f1c067f3a9e6902a079de
Author: Pierre Pronchery <khorben@defora.org>
Date:   Sun Jun 8 23:05:24 2008 +0000

    Changes Makefile generation so that recursive "make" calls read
    "$(MAKE)" instead, as GNU make (or "gmake") is currently necessary to build.
    
    Signed-off-by: Pierre Pronchery <khorben@defora.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 38ee631aeff349c77943a6a41ef3df13e75f0f2b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Jun 7 12:35:11 2008 +0000

    fix via epia cn abuild.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 92af509faacae2191201d8f0994bbcd788c5960f
Author: Tom Sylla <tsylla@gmail.com>
Date:   Sat Jun 7 11:36:30 2008 +0000

    Add dump support for Winbond (NSC) PC87427. Dumps available from real hardware.
    
    Signed-off-by: Tom Sylla <tsylla@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6196416c279e0dd95fd132affb9266407311e6d6
Author: Peter Stuge <peter@stuge.se>
Date:   Tue Jun 3 00:22:00 2008 +0000

    Ward writes:
    
    SST SST49LF160C is confirmed to work for PROBE READ ERASE WRITE, at least on
    2 MCP55-based boards (gigabyte m57sli v1 and supermicro h8dmr).
    
    On the m57sli board, it only works > 512K when booted into coreboot; the
    proprietary bios seems to do something weird where it locks rom access down
    to the first 512K of the chip.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39d4e5f790614db81be84ee6f221c6a055ccb175
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 28 08:40:23 2008 +0000

    abuild: fix gnu getopt detection (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 41b35b52d83305ea242dc13fd841703bf594c3a9
Author: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Date:   Tue May 27 23:51:55 2008 +0000

    Revert r3357 and fix it as intended to (forgotten header commit instead of typo)
    
    Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 012fbc796d3c44f08a465627a615717837848aed
Author: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Date:   Tue May 27 22:20:30 2008 +0000

    Fix typo introduced in r3356 that breaks build (trivial).
    
    Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68229f35d1ec67bf53fb416a62bc9edb05456e06
Author: Peter Stuge <peter@stuge.se>
Date:   Tue May 27 20:54:09 2008 +0000

    flashrom: MX25L4005, S25FL016A, W39V040B, W39V080A, SST49LF008A tests.
    
    I have tested MX25L4005, S25FL016A and W39V080A myself.
    
    Thanks also to the following testers:
    SST49LF008A Bernhard M. Wiedemann
    W39V040B Dan Lenski
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 508381145807200278b3e5d40b9f9e91c56f6d42
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 27 20:07:47 2008 +0000

    coreinfo:  Specify a name, listname and desc item for coreinfo
    
    These values are consumed by the chooser payload.  listname is
    presented on the chooser menu.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc697ad028be74df40fde7eb3f18fc12d75a3d1d
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 27 20:06:54 2008 +0000

    libpayload: Add PAYLOAD_INFO macro
    
    Adds the PAYLOAD_INFO macro to store payload information in a data
    section in the ELF which can be consumed by other entities.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9ce08dc8c0bde500b3845146b97c58e6d097d7c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 27 20:06:30 2008 +0000

    not sure why this ever worked. Add --xml / -x to the supported options (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9e734c29cf03497e3efd38d3ad9e3218c80be6aa
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 27 19:57:53 2008 +0000

    libpayload:  Add a function to verify the checksum on a LAR file
    
    This function verifies the checksum on a LAR file.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 02a4e7f6f8f0060c731301b2e211040555f5fcb8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 27 18:29:26 2008 +0000

    sync latest version of abuild (0.6) (trivial patch)
    
    - parallel building
    - fix non-gnu-getopt systems
    - silent mode
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ee9e1a39118dc2857178bb57e70a4c55115a5418
Author: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Date:   Tue May 27 09:10:52 2008 +0000

    Mark SST49LF004A/B as tested (trivial).
    
    Tested by me on actual hardware (all operations) - Artec Group DBE62 with SST 49LF004B
    
    Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5dfee60cac47b9318a948988f5eca85d70ab386d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon May 26 23:12:25 2008 +0000

    Mark the following chips as tested (trivial).
    
      - AMD Am29F040B
      - SST SST39SF020A
      - Winbond W29C020C
      - Winbond W29EE011
      - Winbond W49F002U
    
    All of them tested by me on actual hardware (all operations).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6eb5012a8c74756bcb4534e22775ecf073461b88
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu May 22 22:47:04 2008 +0000

    A bunch of cosmetic improvements (trivial).
    
     - Fix typos and inconsistencies.
     - Drop duplicate line which tells us the chip name twice.
     - Also print the chip vendor, not only the name.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a02c8eeedd8085ec4df032a9c6a0ebfcb2805b7
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu May 22 21:26:42 2008 +0000

    Mark more chips as tested (all operations), tested on ASUS P4B266 (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dccaf5fd00479564708b8931d19855aa4e6564ea
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu May 22 21:19:38 2008 +0000

    Add support for the ASUS P4B266 board.
    
    Tested on actual hardware.
    
    This patch add an ich_gpio_raise() function which can be re-used by other
    board-specific funtions which need to raise GPIOs on ICHx southbridges.
    
    This also fixes bug #7, see http://tracker.coreboot.org/trac/coreboot/ticket/7,
    as it turned out the ICH2 (and other ICHx) code works fine.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f40532c2b31140422d5938ed7b15b4c5181ebffd
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Thu May 22 13:42:23 2008 +0000

    Add support for Amic A25L40P SPI flash.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b1cde877c39cbab29fffa28a5654958c07b723c
Author: Andriy Gapon <avg@icyb.net.ua>
Date:   Thu May 22 13:22:45 2008 +0000

    Changes to make flashrom compile (and work) on FreeBSD.
    This patch addresses different argument order of outX() calls,
    FreeBSD-specific headers, difference in certain type names and system
    interface names, and also FreeBSD-specific way of gaining IO port
    access.
    
    Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42319797a68f873b142dc26cd1f4031c9ba52fcf
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed May 21 22:10:38 2008 +0000

    This is a simple patch which allows payloads to be placed in memory in
    the range of 0xf0000-0x100000, where the Coreboot tables live in v2.
    As long as the payload doesn't need the tables, it seems harmless, so
    why not just print a warning?
    
    This allows v2 to load "legacybios" without having to have a separate loader.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    It'll be fine for testing and doesn't really break anything that did
    work before...
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29413c76ab0e46b21d90c9f1a4e966669233d5a4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed May 21 13:49:03 2008 +0000

    Add KEY_ESC (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4cc35fdfa9d80f976f29b5cc9f8de1a558e6b31a
Author: Peter Stuge <peter@stuge.se>
Date:   Wed May 21 07:10:15 2008 +0000

    Myles reported SST49LF080A status -> TESTED_PREW
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98cc0566ca958310e76b5242f7d49c1637bf0533
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 20 20:16:34 2008 +0000

    coreinfo:  Use the ESC key to exit the payload
    
    Enable the ESC key to close coreinfo - useful if you are using a chooser
    and want to return to it.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b1c7c16451fc8bf12a20fe61a645b14216b3229
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 20 20:16:03 2008 +0000

    coreinfo:  Fix the subwindow refresh based on the libpayload changes
    
    Changes to libpayload to fix subwindows broke coreinfo.  This fixes it,
    and improves performance by eliminating the entire screen refresh every
    second.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9dac1b4cca496e5293ca888d4f08411d8580ca08
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 20 20:10:49 2008 +0000

    libpayload:  Add an exec() and i386_do_exec() function
    
    Add functions for libpayload to execute other payloads in memory,
    and have those functions return cleanly.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 506980808d2f525e294cdd364b2b4e08276ab8d9
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 20 20:09:42 2008 +0000

    libpayload:  Add larfptr function
    
    Add a function to get a pointer to the start of a LAR entry.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d43841defc07cd84b1dde502a65f4f22c8d8374e
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 20 20:08:11 2008 +0000

    libpayload:  Fix curses subwindows
    
    This fixes subwindows in curses so that they draw and refresh correctly.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9d10dc4ffc144bc8d952047c39f7fc1b109193e8
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Tue May 20 18:10:24 2008 +0000

    Add post-RAM init code for the Fintek F71805F Super I/O.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Richard Stellingwerff <remenic@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fcb2a311c765b9e1d519ed5fa2263d1bd5b33656
Author: Aaron Lwe <aaron.lwe@gmail.com>
Date:   Mon May 19 12:17:43 2008 +0000

    Add support for the VIA EPIA-CN baord, which uses C7 + CN700 + VT8237R.
    
    This also contains various improvements of the CN700 code in svn.
    
    Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 710e8b1ad0e01bea150cc66085176482b677cc19
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat May 17 21:33:35 2008 +0000

    Initial support for the Intel 82845 (Brookdale) and ICH2 (trivial).
    
    Tested on hardware:
    Intel Northbridge: 8086:1a30 (i845)
    Intel Southbridge: 8086:2440 (ICH2)
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce1fb9d4e96d6553ddee1b5bda9a58148c81057c
Author: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Date:   Sat May 17 01:08:58 2008 +0000

    flashrom: Support Pm49FL004/2 Block Locking Registers
    
    The PMC chips understand both LPC and FWH flash commands. When in FWH mode
    (MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block
    Locking Registers by default lock the flash chip for write and erase - in
    addition to any chipset write protection.
    
    This patch adds unlock operations before Pm49FL004/2 write and erase, and
    it includes an svn mv pm49fl004.c pm49fl00x.c
    
    Thanks go to Nikolay for this patch.
    
    Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Bari Ari <bari@onelabs.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb047a6a54ffd872a4059d04a3f2a8b59ae9ab29
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri May 16 21:11:53 2008 +0000

    I looked at the datasheet and erase_sector_39sf020() is totally and
    completely wrong. It was a straight cut'n'paste from SST 28SF040 code
    and the person doing the cut'n'paste didn't even bother to check the
    data sheet. The SST 39SF020 is completely incompatible with the 28SF040.
    
    No need for replacement. According to the data sheet, standard JEDEC
    commands will work and we have those commands in the tree already.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85e46e6bd68b18ebd2734f30dc8516f44310630b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri May 16 18:56:24 2008 +0000

    Doesn't have to be executable (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ee5c9e21b6f2b3f7a76f27b90bd8f4b240839c7
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri May 16 18:08:54 2008 +0000

    Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to all
    the possible IRQs generated by the SIO. This included IRQ 7 as the default
    parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's
    own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards
    that were setting it to prevent the conflict and crash when the MFGPT driver
    loads.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0fd8ccd7e71772c9827bffd5632ec4f218e26783
Author: Joseph Smith <joe@settoplinux.org>
Date:   Fri May 16 15:43:35 2008 +0000

    New Target and initial support for the Thomson IP1000.
    
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9fa5d2abab83c855538e59eb11f14bd68ce793c
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri May 16 14:39:39 2008 +0000

    ICH8 and ICH9 have an almost identical SPI interface, only the location
    of the SPIBAR differs. Add ICH8 support to the ICH9 code.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed24da499db0d7ef8ebfc4b441a566d02dfff242
Author: Dominik Geyer <dominik.geyer@kontron.com>
Date:   Fri May 16 13:00:28 2008 +0000

    Add support for the Atmel AT25DF321 SPI flash (tested).
    Change ST M25P32 status to tested.
    
    Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fac0afb87d216e51284b934042cfeb6f27e70864
Author: Dominik Geyer <dominik.geyer@kontron.com>
Date:   Fri May 16 12:55:55 2008 +0000

    Add support for SPI chips on ICH9. This is done by using the generic SPI
    interface.
    
    Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e7b11577641b3f78eda07000583ebdd5e62fed4c
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri May 16 00:19:52 2008 +0000

    Enable IT8716F LPC-to-SPI write cycle translation in flashrom if the
    IT8716F decodes any address to the attached SPI ROM.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e8eb7d261dcc2c10d7f25ad9b58bd47c2263a2f
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu May 15 22:32:08 2008 +0000

    Print detailed status register information for SST25VF series flash.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da69582ce45d4302cb0265b56a65f0787603a29a
Author: Joseph Smith <joe@settoplinux.org>
Date:   Thu May 15 13:44:33 2008 +0000

    This patch allows the RCA RM4100 to reboot. Upon rebooting in auto.c it detects if the memory is already initialized, if so it issues a hard reset through the southbridge.
    
    Signed-off-by: Joseph Smith <joe@settoplinux.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3da00de8d304e80fb32c0e66ce1c85e7fe4da93
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu May 15 03:24:43 2008 +0000

    Lots of new SST flash chip IDs. Only a subset has been added to
    flashchips.c, but the IDs in flash.h will make lookups easier if anybody
    wants to add support for them.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4868c44b56424d3f0c28ad1a6aa95bdd7eae04b
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu May 15 03:19:49 2008 +0000

    Add support for the JEDEC RES (Read Electronic Signature and Resume from
    Powerdown) SPI command to flashrom to identify older SPI chips which
    can't handle JEDEC RDID. Since RES gives a one-byte identifier which is
    shared among many different vendors and even different sizes, we want to
    match RES as a last resort if RDID returns 0xff 0xff 0xff.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    This is a heavily reworked version of a patch by Fredrik Tolf, which was
    Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7d29013db37b25e842d5208d0c5664282715055
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed May 14 22:56:47 2008 +0000

    Some NSC Super I/Os can have their config port at 0x15c (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a6b6b51df7681931cea26c6e13d7a4fcd4650d3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed May 14 21:20:55 2008 +0000

    Cosmetics, whitespace, coding style, partially ident-aided (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 621c09563b5300b2ea9821d0e4aec9224bb1c97f
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Wed May 14 20:10:02 2008 +0000

    libpayload:  implement wborder function
    
    Implement the wborder function for curses to draw a box around a window.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3148935557fb9f11922e989c1fb40d86d2628d34
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Wed May 14 20:07:31 2008 +0000

    libpayload: Fix the putc function
    
    Reverse rows and columns on the video putc() function, and watch printf
    work again.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9b99450ce759587c3702afc3271e89c137cee11
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 14 20:05:00 2008 +0000

    add ICH7-M and ICH7 DH to inteltool (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f09561ec4697be3745c2c5f3318680323b08baf
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed May 14 14:51:22 2008 +0000

    Add more infrastructure for flashrom ICH9 support.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 58a1cc1d3494daa1002bac617420373e097becee
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 14 14:47:32 2008 +0000

    fix license mentioning in manpage (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9f7af6ef40e9ae2c535f9dc60b6bb53389242374
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 14 14:22:59 2008 +0000

    trivial patch: move maintainable parts to the top and add ICH7-M DH southbridge
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d466e6a8746c6dcdba8969618a3258093ae2392b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 14 13:52:50 2008 +0000

    trivial patch to fix options. Thanks to Uwe Hermann for the hint!
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e173f9904cc8623e81246b6a5a141021c19522b7
Author: Claus Gindhart <claus.gindhart@kontron.com>
Date:   Wed May 14 12:22:38 2008 +0000

    Add the Intel 6300ESB as known chipset to the chipset struct enables.
    
    Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42aab08d842e3156621e8e10797d87fe561f4a5d
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed May 14 12:09:31 2008 +0000

    Fix crash caused by division by zero for unknown flash chips.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68db3a2bdc335519003c7f18ead043d7507718aa
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed May 14 12:03:06 2008 +0000

    Check the JEDEC vendor ID for correct parity. Flash chips which can be
    detected by JEDEC probe routines all have vendor IDs with correct
    parity. Use a parity check as additional hint whether a vendor ID makes
    sense.
    Note: Device IDs have no parity requirements whatsoever.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b69e46bca3ee8e25ee45ba04ff812e507fccb0fc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 14 11:38:22 2008 +0000

    Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7
    have different register meanings, so they get their own lookup tables.
    
    This is a trivial patch.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1984067a8619efe8d4c5bdc44cb27346b126bd2d
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed May 14 04:27:02 2008 +0000

    Add lots of ATMEL SPI flash chips to flash.h.
    Add a few flashchips already mentioned in flash.h to flashchips.c
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b77fb6bd5276f566c02b10a3019f051f37834fc4
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue May 13 23:03:12 2008 +0000

    flashrom: Move all IT87xx specific SPI routines from spi.c to a separate
    file it87spi.c.
    No behavioural changes, but greatly improved SPI abstraction.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03646bebbea8f2f4cace53be797dc727413ae69d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 13 22:14:21 2008 +0000

    Add new revised inteltool that dumps all kinds of chipset information and drop old
    gpio_dump utility.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 56cc34a9a74aac4a51b0f79b2685be642ade9c3f
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue May 13 21:29:48 2008 +0000

    This is a trivial patch which fixes the tint build by removing the extra
    typedef for time_t.  The other half bumps the tint patch revision in buildrom
    to take advantage of it.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 967214d55974ef5b12a799f583d585bbd8b1c9b4
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue May 13 14:58:23 2008 +0000

    flashrom: Move the SPI #defines from spi.c to spi.h
    This patch has no code changes.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a2e7c48d381e54be759429b0cbbfb5c0feaf0587
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue May 13 14:01:22 2008 +0000

    Change the SPI parts of flashrom to prepare for a merge of
    ICH9 SPI support. In theory, this patch has no behaviour changes.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d3fdf9b627090bf579be778d53953f5f600c687
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon May 12 21:19:53 2008 +0000

    MX25L3205 and W25x40 have been confirmed to probe/read/erase/write OK
    by Harald Gutmann.
    SST39VF040 has been confirmed to probe OK by misi e.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c95f2a737a78611bc366fb53010d90baf3be8efb
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon May 12 14:25:31 2008 +0000

    Add SST39VF512, SST39VF010, SST39VF040 support to flashrom. The SST39LF
    series has the same IDs.
    Add short AMIC vendor ID to flashrom.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d0e687ac390dc56265b465eb2338c3f73822cd7c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun May 11 16:13:24 2008 +0000

    Fix the build when serial console support is disabled (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 134aaaec5085c1722ee70584d651c9a4fe817716
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun May 11 15:51:31 2008 +0000

    Quickfix to repair 'make clean; make menuconfig' (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd0b5631ded5e1679980d2db78c0d996326f0f3a
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sat May 10 23:40:51 2008 +0000

    Improve flashrom SPI abstraction, second step.
    This paves the way to have a fully generic generic_spi_command without
    knowledge about any SPI controller.
    
    The third step would be calling SPI controller functions via a function
    pointer.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31ab0314d1ccd36f9240c4c0aafd0a3700605cb9
Author: Peter Stuge <peter@stuge.se>
Date:   Sat May 10 23:07:52 2008 +0000

    flashrom: Rename generic_spi_*() functions to spi_*()
    
    This is a very early step toward cleaning up SPI code in flashrom.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa36f5048f608917ff3503f36d2e18165ce0787d
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Fri May 9 15:32:46 2008 +0000

    coreboot-v2:  Disable second serial port on Norwich
    
    There isn't really any good reason to have the second serial port
    enabled on Norwich, and this makes the X DDC code stop working.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bbd337e3643740bbf06e562baafa728d36d4a5e5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu May 8 14:37:12 2008 +0000

    Add support for dumping ITE IT8718F EC registers (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8cb24580058d5e7fd5776b6df910e43c7bd77ce2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu May 8 13:50:23 2008 +0000

    Don't split up register list in two blocks, otherwise "Register dump:"
    will be printed twice in the output (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 15da8ed98b7e82303a9e9ad633b3cbb42f40f4f5
Author: Claus Gindhart <claus.gindhart@kontron.com>
Date:   Thu May 8 00:31:44 2008 +0000

    flashrom: Probe for up to 3 flash chips.
    
    Currently there is an ongoing technology migration from LPC/FWH to SPI chips.
    For this reason some boards have multiple chips of different technologies
    onboard. This patch makes flashrom probe for up to 3 chips and if more than
    one chip is found flashrom exits, asking the user to specify -c.
    
    [root@localhost src]# ./flashrom
    ...
    Multiple flash chips were detected: SST49LF008A M25P16@ICH9
    Please specify which chip to use with the -c <chipname> option.
    [root@localhost src]#
    
    Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Claus Gindhart <claus.gindhart@kontron.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 83a965d2efb778c05e080862f77701c9c034c13f
Author: Ed Swierk <eswierk@arastra.com>
Date:   Wed May 7 21:57:12 2008 +0000

    Implement GPIO configuration routines for the Intel 3100 southbridge,
    allowing you to specify per-mainboard GPIO settings.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa6e378c4e411ffbb7affb8bead096d281a12cf0
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Wed May 7 20:43:15 2008 +0000

    coreinfo:  Add a module for browsing the boot LAR
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 681ec27e2c64763bba02ef816d41b6b366559f03
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Wed May 7 20:34:02 2008 +0000

    libpayload: Add LAR walking support
    
    Add suport for walking LARs.  These try to emulate the f*
    functions from POSIX, though they are obviously different
    in their behavior.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 35993a231ecb4957d18719801cc4519b1df80d70
Author: Ed Swierk <eswierk@arastra.com>
Date:   Wed May 7 19:21:18 2008 +0000

    Fix a typo in lbtdump output (trivial).
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Ed Swierk <eswierk@arastra.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 193378698e6cfbf774b2d9fff58c7a56880fe919
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 6 22:15:31 2008 +0000

    coreinfo:  Show the current time and date in the menu
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit de7fc55920cdb2cf5e3a7d547ad1d03e0b08aa5c
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 6 22:03:16 2008 +0000

    We were in the risk of running out of space in the option menu at
    the bottom of the screen - this turns the function keys into
    categories and then list specific items as part of the category.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ce2666249c429aa541f5e440cc7f30edb8a5c78
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 6 22:00:55 2008 +0000

    The previous commit had more in it then I wanted - so I am reverting
    this and re-commiting so that the history and comments are correct.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 646ee3eae942880f254a6ce0726ffd0cd902c8f0
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue May 6 21:32:52 2008 +0000

    coreinfo:  Move the rdtsc.h include into the #ifdef CONFIG_MODULE_CPUINFO
    
    rdtsc.h shouldn't be included unless we really need it (and use it).
    Trivial.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9d9518ff54607f8576d45a8664bc9cf88981d6db
Author: Marc Jones <marc.jones@amd.com>
Date:   Tue May 6 16:56:47 2008 +0000

    cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a
    pci_write_config8.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c314b2fcecda9ce360e5dbb6fdebc51b11554792
Author: Myles Watson <mylesgw@gmail.com>
Date:   Tue May 6 15:17:43 2008 +0000

    This patch changes Config-lab.lb for qemu to use lzma like the other targets.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2342f8b343c49803f44803b5732613119f17cd50
Author: Aaron Lwe <aaron.lwe@gmail.com>
Date:   Tue May 6 15:02:22 2008 +0000

    This patch adds pc keyboard init function call for qemu in v2 since some payloads assume
    Coreboot initializes it.  Coreboot v3 already does it.
    
    Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f9141758ef41080c0aaa93bc6cef6309085f70d
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Tue May 6 13:26:32 2008 +0000

    Fix various issues on MSI MS-7135 board.
    
     - W83627THF is strapped to 0x4e, not 0x2e
     - there's no device 9 on PCI-E x1 bus, it should be device 0
     - add mptable entries for AGR slot, based on info in user manual
     - enable floppy drive controller so that some legacy VGA ROMs will work
    
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 33c57f8403bb5bd0415aebb713c28ea7d7c14e3b
Author: Ward Vandewege <ward@gnu.org>
Date:   Mon May 5 20:50:58 2008 +0000

    This patch changes the payload path for Config.lb; this board is supported by
    buildrom and this bit was forgotten during r3092.
    
    This is a trivial patch.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4934fc03cbbf1373d30c08fa9b7d68144eec4ece
Author: Peter Stuge <peter@stuge.se>
Date:   Sat May 3 04:34:37 2008 +0000

    flashrom: Add a tested bitmap field to the flash chip table.
    
    Two bits indicate OK and BAD for each operation PROBE READ ERASE WRITE.
    8 bits out of 32 are in use now. No bits set means nothing has been tested.
    For chips with at least one operation that is not tested or not working, the
    user is asked to email a report to a special email adress so that the table
    can be updated.
    
    All chips are TEST_UNTESTED for now.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a9a5f49d8f69ed131f902f04f651ac96bd6f80cc
Author: Ed Swierk <eswierk@arastra.com>
Date:   Wed Apr 30 18:29:35 2008 +0000

    By default, the Intel 3100 LPC interface enables only I/O range 0x3f8
    for both serial ports, making it challenging to use COM2 for the early
    console.
    
    Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e21f836e4e65dd60c369e40ee7a38b17ccb20e44
Author: Bari Ari <bari@onelabs.com>
Date:   Tue Apr 29 13:46:38 2008 +0000

    flashrom: Enable ROM decode range to 1MB for vt8237r
    
    Signed-off-by: Bari Ari <bari@onelabs.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b19973eb8b39a5267790e2458bab3ef3180ae06a
Author: Claus Gindhart <claus.gindhart@kontron.com>
Date:   Mon Apr 28 17:51:09 2008 +0000

    The generic jedec.c does not work for the ST M50FLW flash
    devices, because they need an unlock command first.
    For this reason, ST M50FLW support is moved to a
    new HW support module, because any change in jedec.c
    would bear the risk to cause problems with the already
    supported devices.
    
    It's already tested with ST M50FLW080A; the other
    chips of this family i dont have available, so i couldnt
    test it.
    
    Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26e08b5abea3d7b6806ed5727b93257e7ed98bf2
Author: Peter Stuge <peter@stuge.se>
Date:   Mon Apr 28 14:47:30 2008 +0000

    flashrom: Handle NULL probe, erase and write function pointers in the
    flashchips table. The read pointer was already checked properly.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e2271430c53d24976ec3b0869dd8993cfba6d768
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Fri Apr 25 23:11:02 2008 +0000

    libpayload:  Add gettimeofday() and friends
    
    Add a gettimeofday() implementation - it works pretty well, but it
    drifts a little bit so its not very suitable for keeping time.  It
    works best to track changes in time over small periods of time.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d772e1e7feb3d782564fe7f46374d4ae8a5f4c36
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Fri Apr 25 23:10:23 2008 +0000

    libpayload:  Fix a small but aggressive bug in printf()
    
    This was causing the returned counter value to be one more then it
    should be when printing a single character.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 63f181f97c0b89f5fe80f96df7b6288a59f5ad42
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Fri Apr 25 23:09:39 2008 +0000

    libpayload:  Enable keyboard translation so that we can use scancode set 1
    
    The qemu keyboard controller defaults to using scancode set 2, we use set 1.
    Turn on the translate mode in the keyboard controller to force the issue.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24a040475918ad2977a52677f59b10f7ce085afc
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Fri Apr 25 23:08:47 2008 +0000

    libpayload:  Fix malloc allocation
    
    Apparently the previous version worked on luck.  Fix the allocation
    and add parens to better guide the compiler.  Also, halt() if
    the heap is poisoned (like by an overrun).  Finally, fix calloc()
    so that it actually works.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c781584936361a921a9f1f6b0491341aaae5c2b8
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Fri Apr 25 23:07:39 2008 +0000

    libpayload:  Add the null terminator to the end of the duplicated string
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20ce60c9aa8a2f5548ec8ab8bd248ef2067b27ae
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri Apr 25 22:56:57 2008 +0000

    Change abuild ROM_IMAGE_SIZE to match the standard s_c_fam10 Config.lb.
    The FAM10 code takes up more space in the uncompressed "ROMCC" portion
    of coreboot. Also, It is still growing as features are added.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 65e08040f912698752b239f499f3efc7f1c0ac0c
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri Apr 25 21:34:25 2008 +0000

    Remove inline from FAM10 CPU initialization functions.
    This doesn't save any space for me but it is the right thing to allow GCC to
    optimize.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ca3ec2e5c8d03e2b73d9aaaf6758047cd32b433
Author: Aaron Lwe <aaron.lwe@gmail.com>
Date:   Fri Apr 25 02:02:33 2008 +0000

    Fix so pci device memory allocation does not use memory base address at 0xfec00000, this is reserved for APIC.
    
    Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
    Acked-by: Joseph Smith <joe@settoplinux.org>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6fd385d154d4adac4a868e5c481c12420f9bfc5f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 25 00:38:41 2008 +0000

    Payload location fix for buildrom (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c1cbff217ac8cd04427ee6cc330261656605b13f
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu Apr 24 20:03:13 2008 +0000

    Add CPUID processor name string support for Fam10 CPUs.
    Peter did a nice job cleaning up my initial patch. Thanks!
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Signed-off-by: Peter Stuge <peter@stuge.se>
    
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 403b89a14f379759fb2a297dfab14ec9dbfffa7a
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu Apr 24 19:49:59 2008 +0000

    On APs the ClLinesToNbDis was being left enabled from CAR setup.
    Disabling it should help performance.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 202625e61f2f91bb2df0a121245ac2ebd13a7948
Author: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Date:   Thu Apr 24 13:37:01 2008 +0000

    This board (http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX)
    is based on amd-lx800/cs5536.
    
    Tutorial: http://www.coreboot.org/IEI_LX_800_Build_Tutorial
    
    Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20ba8eb7abc973ad70844b29412dc958f0629866
Author: Claus Gindhart <claus.gindhart@kontron.com>
Date:   Thu Apr 24 09:07:57 2008 +0000

    Flash pages, which where excluded from updating using the exclude or the
    layout option, as well as areas, whose flash contents already contain the
    desired data, will be skipped.
    These ensures absolute data security of critical areas (BIOS boot block),
    e.g. against a sudden power off or a CPU hangup during flashing. As a
    nice side effect, it speeds up the flash process, if the BIOS to be flashed
    is very similar to the version in flash.
    
    Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a1491314150eac4494d551917ad5e705977c7603
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Apr 23 22:54:40 2008 +0000

    Same old story: Fam10 needs more space again. My calculations say it
    needs 172 more bytes, give it 512 and hope that's enough for a while.
    Trivial.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3e498181301a37c3b25062916188ae6462e244d
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Apr 23 22:01:55 2008 +0000

    Trivial payload location changes for buildrom.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e4c98d28992b2c0724d6465738cf93eeda39b914
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Apr 23 21:06:08 2008 +0000

    These config files are so that buildrom can use these two boards.
    
    Myles
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d1d3b23f07282d4a8bda4814b21cc6938475843
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Apr 23 20:40:55 2008 +0000

    This is the sata irq patch for s2895 and ultra40. It also changes some broken
    white space in the s2892 and s2891 mptable.c files.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0eec1a8e8e5574b1cbe8f1354446a978f2402860
Author: Myles Watson <mylesgw@gmail.com>
Date:   Wed Apr 23 17:55:25 2008 +0000

    Fix irqs for secondary ports on both sata controllers.
    
    Signed-off-by: Myles Watson <mylesgw@gmail.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb33e4a2fefe2fe6071d2595bbbb56514203acd0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Apr 23 09:27:18 2008 +0000

    Detect SMSC SCH5027 (trivial).
    
    This chip seems to be very similar to the SMSC DME1737, for coreboot
    purposes it might even work without any code changes.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4a4116440b4218ec1d3a93f9ce1ddda1ee5d4fe
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed Apr 23 00:40:39 2008 +0000

    This patch fixes the 3 broken sata ports on the Tyan s2891 (primary port on
    secondary controller was ok). There were two problems: the master sata
    controller was not being initialized, and the irqs for the secondary ports on
    both controllers were not being set in the mptable.
    
    Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem.
    
    While all ports work reliably under a recent kernel (2.6.24), sata is about
    half as fast as under the proprietary bios, according to bonnie++. That still
    needs fixing...
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Myles Watson <mylesgw@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a74a8ffa0702a05eadf92605e77bc8c9a86b377a
Author: Marc Jones <marc.jones@amd.com>
Date:   Tue Apr 22 23:32:56 2008 +0000

    Clean up and remove late initialization code that is no longer needed.
    
    Pstate intialization has moved to early init because it requires a warm reset.
    Add CPUID setup and disable SMM access to late initialization.
    Much of this code is leftover from porting from K8.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f0174b5a9c976401797d241c61b4fdf0f425cc6f
Author: Marc Jones <marc.jones@amd.com>
Date:   Tue Apr 22 23:27:53 2008 +0000

    Find matching settings for each CPUs FID, VID, and P-state registers and initialize them.
    
    Supports single and split plane systems. Set P0 on all cores for best performance.
    All APs will be in hlt(C1).
    
    The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8127dc41d1fde1118cdbe3bf6b592312b5b85c02
Author: Marc Jones <marc.jones@amd.com>
Date:   Tue Apr 22 23:20:07 2008 +0000

    Update the FAM10 microcode to current versions.
    In addition, AP microcode is now updated in early initialization to support errata settings that require it.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c74e3627233558c62e93beb37efa271f0f353f8d
Author: Marc Jones <marc.jones@amd.com>
Date:   Tue Apr 22 23:09:34 2008 +0000

    Missed this file in the previous check-in, r3248.
    
    Add early MSR and PCI register initialization.
    This fixes many default setting as well as erratas.
    Some CPU core functions were moved from the HT init and platform specific code
    to the generic Fam10 CPU code.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da4ce6b45157060447cb02fa15349f7de3f531ff
Author: Marc Jones <marc.jones@amd.com>
Date:   Tue Apr 22 22:11:31 2008 +0000

    Add early MSR and PCI register initialization.
    This fixes many default setting as well as erratas.
    Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ab8cddf02f592a34f3c555ba78a11eaf66a59c0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Apr 22 20:19:53 2008 +0000

    Add support for a 'bootlog' module to coreinfo.
    
    It displays the coreboot printk buffer in RAM and let's you scroll through it.
    This feature is only available for coreboot v3 though, as v2 doesn't have a
    printk-buffer feature, yet.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 16acf8b393c5a7933e86f3c7a42a614ad296402e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Apr 22 16:56:21 2008 +0000

    Show index numbers in the NVRAM dump, similar to the PCI config space dump.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f4410b7ddc6dcfcbd0997d9050696333d1cce95
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Apr 21 22:33:58 2008 +0000

    libpayload:  Fix keyboard buglet
    
    This solves the multiple keystroke issue that popped up recently.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7bc63fd2cbe5b512b982ee0a0c5a1552f4f3e249
Author: Christopher Kilgour <techie@whiterocker.com>
Date:   Sat Apr 19 13:32:19 2008 +0000

    This trivial patch adds the SMSC SCH3112 Super I/O chip ID to the
    generic SMSC support, and corrects a small typo.
    
    With this patch, coreboot v2 on a mainboard with SCH3112 has been
    demonstrated to correctly use the serial port.  No other chip
    functions were tested.
    
    Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59711210093b028a69e3292a2558a5c40339c5d2
Author: Ed Swierk <eswierk@arastra.com>
Date:   Fri Apr 18 20:48:22 2008 +0000

    Replace buildtarget's check for --build-id with something
    a bit less awkward (pun intended).
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68aab269fafb8cd1a64fd0acbd33c9cdcf633829
Author: Ed Swierk <eswierk@arastra.com>
Date:   Fri Apr 18 20:47:11 2008 +0000

    Alter buildtarget to invoke the cross-compiler when
    checking for --build-id, if the user has specified one by setting CC
    in the environment; there's no point in checking the native linker in
    this case.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d0a12ac7c69ee6222de955491e3b0a5818a6469
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Apr 16 00:46:08 2008 +0000

    Change default payload location for easier buildrom support (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b53ec3da90381816d1d87b211dade69c98c7dfd
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Apr 15 17:24:08 2008 +0000

    Move curses/speaker.c to drivers/ as it's not curses-specific (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53693031c54f95fdc60fce6a67fd3405dec72d1b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Apr 15 16:47:20 2008 +0000

    Add the patch for building tint as payload, as well as a small README,
    into the payloads/external/tint directory.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50eff2147de057c28701a121ac9dde1b0997f4c0
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Sat Apr 12 20:09:46 2008 +0000

    Correct upper boundary for isxdigit.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be504d1d8dfaf39a626cbb74450d26aa5eb05871
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 11 20:16:24 2008 +0000

    Drop unneeded #includes, add EXIT_SUCCESS/EXIT_FAILURE (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 72199bc49a7ac72fd89c1ddf105c000d457b01ad
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 11 19:43:55 2008 +0000

    Rewrite and filling of libc/ctype.c (thus adjusting copyright line).
    
    Use a simple one-liner for each of the functions. You can surely optimize
    the code some more, but I chose not to do that in order to keep it readable.
    When compiling with -Os the size differences are minimal.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b103345a14cf3fe28f32573833dd06af66dfadaf
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 11 18:38:04 2008 +0000

    Convert BIN2HEX/HEX2BIN to functions and add the abs() family
    of functions while we're at it.
    
    hex2bin() now also supports upper-case input characters.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fad8c2bd7ca3605fdae3548b8a932aa309871931
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 11 18:01:50 2008 +0000

    Various small consistency fixes (trivial):
    
     - Use _FOO_H include guard format everywhere.
    
     - Add missing speaker.c prototypes to libpayload.h.
    
     - Consistently use short form u8/u16/u32 instead of uint8_t et. al.
    
     - kcofig: Use 'depends on' instead of 'depends', which seems deprecated.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54315533cc8f162d5251458c6b9fa9f38c3f47f0
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Fri Apr 11 15:48:21 2008 +0000

    libpayload:  Add a Geode video driver
    
    Add a Geode video driver in lieu of VGA on Geode LX devices
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3aeb93a52d03e1b3dfcf30c66956b18f7f600d7
Author: Marc Jones (marc.jones <Marc Jones (marc.jones@amd.com)>
Date:   Fri Apr 11 03:20:28 2008 +0000

    Bring Fam10 memory controller init up to date with the latest AMD BKDG
    recomendations.
    Changes include the following:
    fix > 4GB dqs tests
    fix channel interleaving
    ecc memory scrub updates
    MC tristating updates
    debug print changes
    fix memory hoisting across nodes -
        The DRAM Hole Address Register is set via devx in each node, but the Node
        number <-> DRAM Base mapping and the Node number <-> DstNode mapping is
        set in Node 0. The memmap is setup on node0 and copied to the other nodes
        later. so dev, not devx. The bug was the hole was always being set on the
        first node.
    
    Signed-off-by: Marc Jones (marc.jones@amd.com)
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 234e87f137faff67c391c4df678a82b763089119
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Apr 10 22:50:44 2008 +0000

    libpayload: Support functions for Geode
    
    The Geode video driver will require a number of support functions,
    including udelay(), PCI bus walking and MSRs.  This adds those functions
    in preparation for the actual code.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 30939bdffd0435df4aa0830b2da1ef06ceebfba3
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Apr 10 22:49:02 2008 +0000

    libpayload:  Add video console framework
    
    Add a framework for multiple video console drivers.  This is to prepare
    for the Geode driver.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bac89d088cf102851122925b31404b7ae52c21c3
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Apr 10 17:57:42 2008 +0000

    libpayload: Avoid .svn files in the header install
    
    Slight tweak to to the install target to avoid copying .svn
    files.  Trivial self ack.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1cb92bc77f7be88b267be180a767b333a9d34a00
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Apr 10 00:05:41 2008 +0000

    coreinfo:  Make coreinfo use the gcc-wrappers from libpayload
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 804f4df5bdbe5244c8f4f15c5d50d223f8a11c34
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Apr 9 23:48:48 2008 +0000

    Make the sample Makefile a bit more generic, so it can be adapted more
    easily for other payloads. Also, add a 'distclean' target (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3e728fbdfa6a92a9b07e46d0ae0da7259e29d35
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Wed Apr 9 23:05:59 2008 +0000

    libpayload: Implement gcc wrappers for libpayload
    
    libpayload uses a ton of flags and other scary gcc and ld options.  These
    wrappers hide most of that from the user, so that using libpayload is as
    easy as lpgcc -o hello hello.c
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c5a78ac56ad9078fe70c2753c46ca4d500840ee8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Apr 8 23:38:15 2008 +0000

    Add missing prototypes for libc/rand.c functions (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea72559d5d750b46c20ce2044f34efddc7d89032
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Apr 8 23:30:22 2008 +0000

    Small curses fixes/additions for libpayload (trivial).
    
     - Properly set LINES and COLS, needed for a real curses application.
    
     - Implement notimeout() and wtimeout(), which are trivial.
    
     - Implement a dummy flushinp() for now as it's needed by a curses
       application I'm porting, will be replaced by something useful later.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 672d0ae15655aa8c28e2ac0e698e501628347b7c
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue Apr 8 23:21:33 2008 +0000

    libpayload:  Add a timeout function for getchar and getch
    
    Implement a timeout option for getchar() to return after so many
    milliseconds.  Also implement the same thing for curses using
    the halfdelay() function.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4eb5089821b014d84fac2ef432da0f7bbaba754e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Apr 7 23:33:50 2008 +0000

    Add rand/rand_r/srand functions for generating pseudo-random bytes.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6092c0f34cde338dcce2cd61cdee8826b4c1a59
Author: Ed Swierk <eswierk@arastra.com>
Date:   Mon Apr 7 22:33:33 2008 +0000

    ST M50FW016 and ST M50FW040 support the 82802ab command set, not jedec.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Joseph Smith <joe@smittys.pointclark.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 78f59f835264c672afd040eb1bd4cf601302332c
Author: Marc Jones (marc.jones <Marc Jones (marc.jones@amd.com)>
Date:   Mon Apr 7 18:11:03 2008 +0000

    Re-add files I deleted by mistake in r3219. They are meant for a different
    patch.
    
    Signed-off-by: Marc Jones (marc.jones@amd.com)
    Acked-by: Marc Jones (marc.jones@amd.com)
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df22f780f1894d1ef2e35d51f430caf8f25211ed
Author: Marc Jones(marc.jones <Marc Jones(marc.jones@amd.com)>
Date:   Mon Apr 7 17:49:57 2008 +0000

    Don't check exclusive IRQ fieldin the PIR table.
    This field is rarely used (and not used in the LX tables).
    There is not a good reason to mask off non-exclusive IRQs.
    
    Signed-off-by: Marc Jones(marc.jones@amd.com)
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0dc5697220773719cd18e23c795c55f864f03a1d
Author: Joseph Smith <joe@smittys.pointclark.net>
Date:   Sun Apr 6 04:26:19 2008 +0000

    This patch halts the tco timer early in the boot process on all ICH series southbridges.
    It also keeps the boot processes from rebooting through out the coreboot process.
    
    Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3860404b651d7c92c86a9789f9c163efb7ec9c8a
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Sat Apr 5 01:07:27 2008 +0000

    libpayload: remove unneeded stack stuff
    
    Following on the previous code to streamline the libpayload init code,
    this removes the now unneeded stack structures.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c44dfb6497941cf844feef79aafec23f32635b2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 4 16:49:09 2008 +0000

    Fix the case where the user selects no modules in Kconfig at all.
    Until now, the build would break, and even if it didn't the ELF would
    triple-fault in QEMU.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4afb7fb761ee49595f25de66093bc021cbdfae16
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Apr 4 15:02:45 2008 +0000

    Add a workaround for a bug in some binutils version which strictly
    interpret whitespace as macro argument delimiter. Since the code is
    preprocessed by gcc and the tokenizer may insert whitespace, that can
    fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669
    
    The same change was committed in r3044 to the AMD CAR code.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a69772157e8620f5228c880c06d383c23d84eea0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 4 13:28:10 2008 +0000

    Document a rough estimate of how much space in the ELF file each of the
    coreinfo features / modules will consume (trivial).
    
    The measurements were done with libpayload r3213 (but compiled with -Os),
    and coreinfo r3211 (also compiled with -Os).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1bee6f9b9c456854feff78a72d7ac3fb915454af
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Apr 4 13:16:33 2008 +0000

    Add BIN2HEX and HEX2BIN macros (trivial).
    
    They're generally useful for lots of stuff, but especially for converting
    to/from the compact 160 bit (20 byte) representation of SHA-1 hashes to
    the "hex" representation (same as 'sha1sum' output), which is 40 bytes long.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3995593b6861e62b6a97207d5d6e28385be229bf
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Apr 3 23:01:23 2008 +0000

    Add a SHA-1 implementation to libpayload.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7582274068429db814b130ba83e6f123c961f80
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Apr 3 22:20:35 2008 +0000

    Doing another 'make' after a 'make clean' was broken until now. Fix it
    by not deleting build/config.h during 'make clean' (only in 'make distclean').
    
    Also, change the default behaviour of 'make' from asking the user to
    run 'make config' (or similar) to actually _run_ 'make config' without
    asking questions. It's always possible to explicitly invoke
    'make menuconfig' or 'make xconfig' and so on, of course.
    
    Finally, make _all_ targets (allyesconfig, randconfig, and so on)
    generate a build/config.h file, as we always #include it.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0a89625f55ac3b220b89fe7f122e98ef49af925b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Apr 2 12:35:45 2008 +0000

    Add missing snprintf() to libc/printf.c (trivial).
    This is also taken from the HelenOS project.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b85b6311f1b7497da3484dc9369e80c9140ae5c
Author: Ed Swierk <eswierk@arastra.com>
Date:   Tue Apr 1 17:14:57 2008 +0000

    Setting an integrated southbridge device (like SATA or USB2.0) to
    "off" in Config.lb should cause the PCI device not to respond to
    configuration requests.
    
    Replace the existing code that I naively copied from esb6300 with
    something that actually works on the 3100.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23cd49ab807d7d3ce496740000ad588eb5a0a16a
Author: Joseph Smith <joe@smittys.pointclark.net>
Date:   Tue Apr 1 17:05:22 2008 +0000

    Remove i82801DB files that I meant to delete in r3206.
    
    Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Ed Swierk <eswierk@arastra.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 06ae6395964b2eb84be10533a7e14049778a45a9
Author: Ed Swierk <eswierk@arastra.com>
Date:   Tue Apr 1 02:48:12 2008 +0000

    Tiny style fix for consistency (trivial).
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Ed Swierk <eswierk@arastra.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 868de9838c8ea97b8d27a0bc97828f1964536084
Author: Joseph Smith <joe@smittys.pointclark.net>
Date:   Tue Apr 1 02:42:52 2008 +0000

    Removal of i82801DB (ICH4)
    
    There are no boards that use the i82801DB (ICH4). The code does NOT work.
    
    Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Ed Swierk <eswierk@arastra.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4e052cd5089019dc67b4fa176bca6d8d19de30d
Author: Ed Swierk <eswierk@arastra.com>
Date:   Tue Apr 1 02:36:59 2008 +0000

    The early init code of several Intel southbridge chipsets calls
    pci_locate_device() to locate the SMBus controller and LPC bridge
    devices on the PCI bus. Since these devices are always located at a
    fixed PCI bus:device:function, the code can be simplified by
    hardcoding the devices.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c6b33ce3e2eb287e6a0b25d46b96ba7876fe17a
Author: Klaus Schnass <dev@stuffit.at>
Date:   Mon Mar 31 21:02:29 2008 +0000

    Libpayload fixes to prevent triple-faults when running in QEMU.
    
    Let the linker figure out the correct address and just CALL the
    start_main entry point.
    
    Signed-off-by: Klaus Schnass <dev@stuffit.at>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab5b3e0d985cdfb0d882f52b73a77c6f551918f3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Mar 31 20:30:18 2008 +0000

    Add support for an "NVRAM Dump" screen in coreinfo (optional), as well as for
    displaying the current date/time in the lower-right corner (optional).
    
    Also, only build/use coreinfo modules which were selected in kconfig. This
    makes coreinfo truly modular, and you can save quite a bit of ROM space
    by disabling unwanted parts of coreinfo.
    
    Finally, simplify the Makefile a bit by getting rid of MODULES (and only
    using OBJECTS).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 30d789bcbd528389749339ff03474543af1d5bf1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Mar 31 20:21:49 2008 +0000

    Fix the NVRAM access functions to work correctly for the
    upper 128 bytes of NVRAM (if enabled).
    
    For most chipsets this means using I/O ports 0x72/0x73, but at least
    on some VIA chipsets (I tested the VIA VT8237R on actual hardware)
    these ports won't work and you have to use 0x74/0x75. Thus, make this
    a Kconfig option for now.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d758b8bf6077796db27d055cf7d24f77ea52c4b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Mar 31 15:21:24 2008 +0000

    Whitespace fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b642e6d40a4347a5963e1f469ec863140b0cae59
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Mar 31 15:18:56 2008 +0000

    Rename drivers/cmos.c to drivers/nvram.c (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c16d24e73a52858fa165371fa339a37c1adac403
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Mar 31 15:17:39 2008 +0000

    Due to popular demand, rename "CMOS" to "NVRAM" (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71f846c13769f037fbdf649224d03377948b7fa9
Author: Ed Swierk <eswierk@arastra.com>
Date:   Sun Mar 30 11:31:15 2008 +0000

    Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots
    the system automatically unless software resets the timer
    periodically. The extra reboot extends boot time by several seconds.
    
    The attached patch adds a function to the Intel 3100 southbridge code
    that halts the TCO timer, thus preventing this extra reboot, and calls
    the function early in the boot process on the Mt. Arvon board.
    
    It also fixes a bug in the LPC device initialization -- the ACPI BAR
    enable flag is bit 7, not bit 4.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1e185e8561bc42b0f77159e4fa7ef0c652a2f6eb
Author: Kenji Noguchi <tokyo246@gmail.com>
Date:   Sat Mar 29 17:24:58 2008 +0000

    Add support for the TeleVideo TC7020.
    
    Signed-off-by: Kenji Noguchi <tokyo246@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c2255c66c20cd90f39cc08c1220d93222d5d580
Author: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Date:   Sat Mar 29 16:59:27 2008 +0000

    Now coreboot performs IRQ routing for some boards.
    You can see this by executing commands like this:
    grep -r pci_assign_irqs coreboot/src/*
    
    This basically AMD/LX based boards: pcengines/alix1c,
    digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
    
    Also for AMD/GX1 based boards need a patch
    [http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
    for the right IRQ setup.
    AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
    bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
    
    I have two ideas.
    1. Delete duplicate code from AMD/LX based boards.
    2. Add IRQ routing for AMD/GX1 boards in coreboot.
    
    The pirq.patch for IRQ routing logically consist from of two parts:
    
    First part of pirq.patch independent from type chipsets and assign IRQ for
    ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
    
    Second part of pirq.patch depends of type chipset and set PIRQx lines
    in interrupt router. This part supports only CS5530/5536 interrupt routers.
    
    IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
    
    Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
    TeleVideo TC7020, see
    http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
    
    Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e122af46553c394b1ac4c38dd83ab01c7c34a9c
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Sat Mar 29 16:13:22 2008 +0000

    [libpayload] Work around sign-extending issue
    
    Somewhere characters are getting sign-extended, meaning that the
    attributes of the drawing chars (>= 128) are wrong. Cast the value
    before sending it to VGA.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3195 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42cccdf03b17a7085099386edb41d8fd9092a170
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Mar 29 01:35:21 2008 +0000

    Make a few array entries only as big as they absolutely need to be (trivial).
    
    This decreases the size of the superiotool binary from ca. 1.1 MB to 600 KB.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da0efc4ca5cd880745028abac97589b9afc1d034
Author: Joseph Smith <joe@smittys.pointclark.net>
Date:   Fri Mar 28 03:35:11 2008 +0000

    Fix for irq routing issues.
    Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8cc38d2f13bfacddd5e97c1cb3340bcdca4093b0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 27 23:26:40 2008 +0000

    Add initial support for some basic CMOS read/write functions and the
    bcd2dec()/dec2bcd() functions we'll need for (among other things)
    converting some date/time parameters in CMOS.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a0c0093a09f0a7115ce73abe00b8b75afab4a08c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 27 20:46:49 2008 +0000

    Various tiny fixes (trivial):
    
     - Show PCI IDs as 4-digit numbers always.
    
     - Cosmetic changes to make UI look more consistent.
    
     - Drop MODULE_COUNT #define and use ARRAY_SIZE() where needed.
    
     - Small fix to improve build system (create build/ when not there).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 408c4e1784a35ce9c2920e7cf17d78450515b1d2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 27 19:11:44 2008 +0000

    Drop -Os in libpayload for now, it causes run-time problems for some
    strange reason (broken curses/VGA display, maybe others).
    
    It'll be re-enabled when we fixed that.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c88b537461d2af16812a78c6266ac62695900708
Author: Jon Dufresne <jon.dufresne@gmail.com>
Date:   Tue Mar 25 19:43:01 2008 +0000

    Make the getpir output compile (Closes #70).
    
    Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2216d1b46a86fd5beb20a8e99f176f28c527e0ec
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Mar 24 15:47:49 2008 +0000

    Add a recent kconfig version to coreinfo, in order to make the
    supported features configurable later (currently unused). Store all
    build files and results (coreinfo.elf) in build/ now.
    
    I'm self-acking this as (though non-"trivial") it doesn't affect coreinfo
    in its functionality, this is more or less a "cosmetic" change to the
    build interface ("make" -> "make menuconfig && make").
    
    This is a kconfig checkout from the Linux kernel (where kconfig is being
    actively maintained) from 03/2008. The hash identifying the last commit
    to kconfig is 587c90616a5b44e6ccfac38e64d4fecee51d588c.
    
    The amount of changes to kconfig itself has been kept as small as possible
    to keep the diff small and to ease updating/porting to newer kconfig versions.
    The following changes were performed on the upstream Linux kconfig:
    
     - s/kernel/coreinfo/, and s/Linux/coreinfo/ in various strings.
    
     - Consistently use the env. variable KERNELVERSION in all kconfig
       interfaces -- e.g. config/menuconfig/gconfig/xconfig -- as version number.
    
     - Hardcode our paths/filenames in some places (could be improved upstream).
    
     - Always write .config and build/config.h, no matter which kconfig
       interface is used (config/menuconfig/gconfig/xconfig). We want to
       include build/config.h in our code.
    
     - Adapt the kconfig Makefile for our purposes (build/ directory, rules, etc).
    
    In addition, a few items in the coreinfo Makefile are needed for this to work.
    
    This kconfig setup is successfully tested with all targets from 'make help':
    
      config          - Update current config utilising a line-oriented program
      menuconfig      - Update current config utilising a menu based program
      xconfig         - Update current config utilising a QT based front-end
      gconfig         - Update current config utilising a GTK based front-end
      oldconfig       - Update current config utilising a provided .config as base
      silentoldconfig - Same as oldconfig, but quietly
      randconfig      - New config with random answer to all options
      defconfig       - New config with default answer to all options
      allmodconfig    - New config selecting modules when possible
      allyesconfig    - New config where all options are accepted with yes
      allnoconfig     - New config where all options are answered with no
    
    For 'make defconfig' to work you have to do (which we don't need in coreinfo):
    
      $ mkdir configs; touch configs/defconfig
    
    You can also use 'make foo_defconfig' in which case kconfig will use a
    file called 'configs/foo_defconfig' as basis.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3188 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0bfb5c4fb2a8626ccc6f663d1c8ca8e88f6d6666
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Mar 23 15:34:04 2008 +0000

    Make functions static (where possible) to reduce code size (trivial).
    Also, disable header() for now, as it's not being used.
    
    Here are some stats on size differences:
    
     - ls
    
    23820 coreinfo.old.elf
    23564 coreinfo.new.elf
    
     - size *elf
    
       text    data     bss     dec     hex filename
      15199    2468  181904  199571   30b93 coreinfo.old.elf
      14934    2468  181912  199314   30a92 coreinfo.new.elf
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b0e3f39a39431f6448f4985a10379a580cf4c13c
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Sat Mar 22 15:27:26 2008 +0000

    Make cursor positioning work by using both halves of the
    VGA cursor position register.
    
    Have vga_scroll_up() and vga_clear_line() present row/column
    arguments to the VIDEO() macro in the right order.
    
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    -This line, and those below, will be ignored--
    
    M    libpayload/drivers/vga.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 661e380a75ebc4fa355dc647ed06bd0a2d100b1c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Mar 21 18:37:23 2008 +0000

    Cosmetics, fix typos (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29014056e7fa3ee7a38c49d6de6924de60b9903c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Mar 21 15:47:38 2008 +0000

    Quickfix for libpayload's strcpy() to properly NUL-terminate strings (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 316e07fb04c4de11b8be717c73f9a80baf0fece6
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Thu Mar 20 21:19:50 2008 +0000

    Following patch adds K8M890 support. It initializes the AGP and graphics UMA.
    The V-link setup and HT bridge is redone, because VT8237A has it in another
    device. So far following combination of chipsets should now work:
    
    K8T890CE + VT8237R
    K8M890(CE) + VT8237R
    
    VIA PC1 brige moved to NB code (vt8237r_bridge.c -> k8t890_bridge.c) and
    notes about K8M890 support were added.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14a3feb0686b9c97034de828844f52c75ccc42d1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 20 20:46:44 2008 +0000

    Fix code to allow usage of -Wall in libpayload and the sample (trivial).
    
    This even fixes two bugs:
    
     - get_cpu_speed() didn't return a value.
    
     - The line
         win->_color - PAIR_NUMBER(0);
       should actually be
         win->_color = PAIR_NUMBER(0);
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 35845a2acb869ea028c98c8c2b912ae3c61053e2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 20 20:05:22 2008 +0000

    Smaller fixes to allow using -Wall (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a441bfb46337ed6b59abed56dad35d94802282c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 20 19:54:59 2008 +0000

    Cosmetics, coding style fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f4c8abb6537fa7377969e837dab987abefcf922
Author: Christopher Kilgour <techie@whiterocker.com>
Date:   Thu Mar 20 01:58:08 2008 +0000

    Change kconfig references from 'buildrom' to 'libpayload'.
    
    Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0c1cea29e720d11827f20b4791fa3768c0eea2ac
Author: Christopher Kilgour <techie@whiterocker.com>
Date:   Thu Mar 20 01:56:05 2008 +0000

    Allow 'make menuconfig' to function within libpayload.
    Removes reference to BusyBox.
    
    Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc69e05d90b922bbfc5712dcd4030d9585af4ff8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 20 01:53:30 2008 +0000

    Make the list of functions in libpayload.h more complete (trivial).
    We need to think about the exact API we want to expose later, though.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5aa66da9a146fa91a587f3676275b4551241a47d
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Mar 20 01:15:16 2008 +0000

    Add -Os to the CFLAGS for size improvements.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c7bb9e84fb82ed79a9180dc1ecc9e805d70b765
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Mar 20 01:13:28 2008 +0000

    libpayload: Add -Os to the CFLAGS
    
    Adding -Os to the CFLAGS gains us about 25% smaller code (give or take).
    Unfortunately, it exposes a strange issue where strcpy() suddenly goes
    missing - we think that strcpy() is being provided by libgcc, and that
    for some reason, -Os changes the beahavior.  Oh, well - add a quick
    strcpy() function and we're good.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a406feb179dbe10bbbc1b07abd935a7d04e6524
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 20 01:11:28 2008 +0000

    Cosmetic changes and coding style fixes by running 'indent', with some
    manual fixups afterwards (trivial).
    
    No functionality changes, compile-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7249f7979237d7f14941036dd931545b5c9e73fb
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Mar 20 00:11:05 2008 +0000

    corinfo:  Inital release of the coreinfo code
    
    This is the intial release of the coreinfo payload code.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c52761be0a67f31af13ffd2c6f0217988c8b5175
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 20 00:02:07 2008 +0000

    libpayload: BSD solutions contributed by Uwe
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3029a8fc9025de0e09d1bb3fefe67e391c4160a
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Wed Mar 19 23:59:13 2008 +0000

    libpayload: External code
    
    This is external and properly licensed code that I pulled into the tree.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f6145c3c15789123f6b4a9ce64a517048e753762
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Wed Mar 19 23:56:58 2008 +0000

    libpayload:  The initial chunk of code writen by AMD
    
    This is the initial chunk of code written by me and copyrighted
    by AMD.  Includes everything but a few files that we pulled from
    outside sources.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c221349746299537de9e01a0bcfb28485b15ef84
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Wed Mar 19 20:24:33 2008 +0000

    Following patch will setup KT890 HT automatically. It will find the
    max width of the link and also it will take the frequency of K8 HT
    already done coreboot (and checks if t can run on it).
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cfcc9ca59047a19dd01953c1d906947e2c78ca6a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 18 23:10:24 2008 +0000

    * split model_centaur into model_c3 and model_c7
    * simplify and improve cpuid table
    * add speedstep support for VIA C7 based CPUs
    * also included as many of Uwe's suggestions as possible
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e98edfa38637166002a50714dd0db9beef6c7054
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Mar 18 00:54:10 2008 +0000

    Add ICH9 detection to flashrom. Straight from the datasheet, untested.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 470d3650ade58f4ed16854991cf917a250381924
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 18 00:36:18 2008 +0000

    oops. forgot to add the file.
    
    Support for the Winbond W39V080FA series of chips.
    Support for flashing on the Kontron 986LCD-M board.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 012ed48bf2c28af293c1868f8e0d0371e20ed8ec
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 17 22:59:40 2008 +0000

    Support for the Winbond W39V080FA series of chips.
    Support for flashing on the Kontron 986LCD-M board.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ce4e4caa9c2856c77b666299b9551dfd10a0dab
Author: Ward Vandewege <ward@gnu.org>
Date:   Mon Mar 17 17:06:06 2008 +0000

    The ATI vga rom is only 36K on the Tyan s2891, not 48K.
    
    This is a trivial patch.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 969a9f69e8b2c33068151fd9adaa20356a7bcf66
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Mar 17 13:43:48 2008 +0000

    Various smaller fixes in superiotool:
    
     - Also dump the extra registers (e.g. EC regs) in --list-supported.
    
     - Small fix in the code to allow for building with -pedantic (yes,
       the fix is a bit silly, but it's simple and allows us to use the
       -pedantic flag to keep the code even cleaner and nicer).
    
     - Install the binary in /usr/sbin, as it's meant to be run as root.
    
     - Small typo in README.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a2ccf9fe4ef3f2736a336f861ffc37597829fcbc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Mar 17 13:37:34 2008 +0000

    Add support for the MSI MS-6119 mainboard.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa510c7878e1dc6d74422541d3b26278f692a0a8
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Mar 17 01:37:27 2008 +0000

    Clarify LZMA code license.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f83d7ed962f93406f7884a1e4516e33b0d3fb19
Author: Ed Swierk <eswierk@arastra.com>
Date:   Sun Mar 16 23:43:04 2008 +0000

    oops. sorry, wrong checkin. This patch backs out r3155 and instead contains the
    code it should have contained.
    
    This patch updates the PCI IDs for Intel 3100 devices.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 354e2d3dc1e1c670128114139350420d9c10b8cd
Author: Ed Swierk <eswierk@arastra.com>
Date:   Sun Mar 16 23:39:24 2008 +0000

    This patch implements support for the Intel 3100 Development Kit
    mainboard, aka "Mt. Arvon".
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a9faea8977cae2c1c55b83b214aee6845de1c885
Author: Ed Swierk <eswierk@arastra.com>
Date:   Sun Mar 16 23:36:00 2008 +0000

    This patch implements support for the Intel 3100 integrated
    northbridge and RAM controller.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aaea11b749ccd481a37424c38625873c231f850d
Author: Ed Swierk <eswierk@arastra.com>
Date:   Sun Mar 16 23:34:10 2008 +0000

    Here is an updated patch addressing most of Uwe's and Peter's
    comments. Ripping out the ehci/uhci_init() code doesn't seem to have
    done any harm, and I got rid of a bunch of unused junk in
    i3100_smbus.h
    
    I left the *_set_subsystem() arguments unsigned, as that's how the
    function is declared in include/device/pci.h.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 62eee3ff4fc544ede21d72fcb5a1859b3f571dc8
Author: Ed Swierk <eswierk@arastra.com>
Date:   Sun Mar 16 23:31:04 2008 +0000

    This patch implements support for the Intel 3100 integrated SuperIO and UART.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 791265a367a522c18258c2053ad828fb484b01a3
Author: Ed Swierk <eswierk@arastra.com>
Date:   Sun Mar 16 23:27:50 2008 +0000

    This patch updates the PCI IDs for Intel 3100 devices.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4b901e3efe2cf12ebe02ee63ef7b3a7cb249f64
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 16 22:20:53 2008 +0000

    give the fam10 code a little more space until we have the time to debug this
    properly. Everybody knows this by now.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd6877a46df7137854998982beaefc19c397f97d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Mar 16 19:44:13 2008 +0000

    check whether SST FWH chip was successfully erased on flashchip -E, too
    (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 568667da20f33e8036b212fa257594d03903fe7d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Mar 16 02:06:25 2008 +0000

    Sort list of flash chips alphabetically, add comment (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 582ce71cc5d3948908ce109ff68a8563b1b2030c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Mar 15 23:41:19 2008 +0000

    remove nasty warning that happened due to our vendor detection
    mechanism.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9dcfc00dc6e80d03c149129397153dc3f9b15326
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Mar 15 16:30:39 2008 +0000

    fix typo
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e989be26e6bbca47d4c47b651a864da9763d7adc
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Mar 15 12:26:12 2008 +0000

    BIOS_SPEW is log level 9. There is nothing beyound that line.
    (Thus the patch is trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5671787b9e36ca80b39dcbbfb0307e3c697c8e20
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Mar 15 00:26:50 2008 +0000

    Following patch extends the ROM decoding to last 1MB, allowing to use larger
    flashes such as SST49LF080A: 1024K x8 (8 Mbit)
    
    Tested on my system, the flash is found and if I use coreboot in second half it
    works too.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd52e17448b2a8b49c1add655aa3deb3adebbcbc
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Mar 15 00:19:34 2008 +0000

    Following patch fixes the retrain/reset sequence which caused problem with some
    nVidia cards. The enable link should be enough, retrain is done there.
    
    Tested on my system.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1ce63770a1d18baa41a6382236350814d36895ef
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Mar 14 23:55:58 2008 +0000

    Re-add code erroneously removed in r3140.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 937ae9d9fec2fe527b78fbd96e768b28dca849b6
Author: Joseph Smith <joe@smittys.pointclark.net>
Date:   Fri Mar 14 23:32:03 2008 +0000

    Changes M50FW080 to use 82802ab.c instead of jedec.c. This fixes the problem of not being able to erase the chip.
    
    Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae8a08df3b477d950860915686650de5fff330d1
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Mar 14 17:20:59 2008 +0000

    Prepare for ICH7/ICH8 SPI support by adding some debugging for all
    ICH* chipsets. Functionality (except printing) should be unchanged.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    Ward says:
    This code detects the ICH8 chipset on my laptop, and it appears to use
    SPI.
    
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b202d0a6ebfda908284edf109ad0baf3cb4cb95
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Fri Mar 14 06:12:24 2008 +0000

    Add a Config-abuild.lb for the rca/rm4100 (trivial)
    The problem is explained here: http://www.coreboot.org/pipermail/coreboot/2008-March/032185.html
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c843636c88a4bce6557507026a63f1693354ee1e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Mar 14 01:24:39 2008 +0000

    Fix broken flashrom build.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b0a41b5ca0301772d655841718db41565a7450a
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Mar 14 00:33:42 2008 +0000

    Fix up one forgotten revert in r3140.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8729de48fa73d86abb5ae2e87406ba305d0b3062
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Mar 14 00:02:25 2008 +0000

    Revert the delete of 82802ab.c in r3137.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 912ee57a5968cde002c1fadffed33291a1a35b3c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 13 18:52:51 2008 +0000

    Also print the chip vendor name in --list-supported output (trivial).
    
    Cosmetic changes in some files, partly bending the 80-characters-per-line
    rule in this special case, as the 80-character-limited version looks
    equally crappy even in an 80x25 console/xterm, so let's make it at least
    look good in a high-resolution xterm.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ee2bb3a21e6f19af62c500c109f658197d074c8f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 13 18:41:07 2008 +0000

    Also print the required -m option in --list-supported output (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7b22e3c573085a2e86f69df54ab92f6fe4b1645
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Mar 13 12:43:31 2008 +0000

    Drop 82802ab.c as it is identical to sharplhf00l04.c.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3182122c3bc8477be048106d85bf331499373e70
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Mar 13 02:21:41 2008 +0000

    Update AMD CPU list based on Revision Guide for AMD NPT Family 0Fh Processors,
    Publication #33610, Revision: 3.30, February 2008.
    
    http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b681570e7b0b2a67abd067715df118e7853a0b82
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Mar 12 23:18:04 2008 +0000

    Formatting fixes, no content changes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ad17532a4890e322cf7c522e49fb6733b8c0a6e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Mar 12 12:28:40 2008 +0000

    Drop the useless rom.layout file. It's just an example, likely never
    been used in the last few years, and the contents are available in
    the README already anyway.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 098913dadfcb9e5205112ee05ec3042bbd4cb277
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Mar 12 11:54:51 2008 +0000

    Add --list-supported option to flashrom which lists the supported
    ROM chips, chipsets, and mainboards (Closes #90).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2aa14367774bc19ab4df4ff527e15d5e73258ddd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Mar 10 22:26:18 2008 +0000

    Add GPIO dumping utility for Intel ICH series southbridges.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0719b8e4606b23d4c9822cb7c8121a87068c73ed
Author: Ward Vandewege <ward@gnu.org>
Date:   Mon Mar 10 19:53:30 2008 +0000

    The ATI vga rom is only 36K on the Tyan s2881.
    
    This is a trivial patch.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7aad44c4962656a476dbdf4d5eb54c0e142818d8
Author: Ward Vandewege <ward@gnu.org>
Date:   Mon Mar 10 18:48:52 2008 +0000

    This patch changes the Config.lb files and adds a Config-lab.lb file for the
    tyan s2881 board, in preparation of supporting it in buildrom. Corresponding
    changes for the other buildrom-supported boards were committed in r3092.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a1dc86005bb14c14d1b0f8c69f554912a2d3199
Author: Joseph Smith <joe@smittys.pointclark.net>
Date:   Sun Mar 9 13:24:46 2008 +0000

    Initial support for the Intel 82830 northbridge and RCA RM4100 board.
    
    Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4f536568833fb7b0052a2eda63dd39f05885978
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Mar 8 19:14:42 2008 +0000

    Various cosmetic and coding style fixes for ASUS A8V-E SE (trivial).
    No functional changes, only cosmetics. This is compile-tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 917158f8031dc2595a7e066ac848684cc2fac9cc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Mar 4 17:21:04 2008 +0000

    Drop some duplicate documentation from the README. The manpage and
    'superiotool --help' already provide the same information (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ae23628fb08c784a301c20204587bd7818a56dc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Mar 4 16:29:54 2008 +0000

    Add missing license header to layout.c. The file was written by
    Stefan Reinauer for coresystems GmbH in 2005, as confirmed on IRC.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cbb5ba8633c2ad143366c3bc367f8c4f6434c084
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Mar 1 19:09:01 2008 +0000

    Rename lxbios to nvramtool, step 3 (rename directory).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66d83cfa84f75ad3fba38d3b926da531d800b8a5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Mar 1 19:07:46 2008 +0000

    Rename lxbios to nvramtool, step 2 (rename files).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e565947a554b9145ae5afdc307a6b842bc09883
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Mar 1 19:06:32 2008 +0000

    Rename lxbios to nvramtool.
    
    This is step 1 in a three-step commit:
    
     1. Apply patch, commit.
    
     2. Rename some files:
        $ svn mv lxbios.c nvramtool.c
        $ svn mv lxbios.1 nvramtool.c
        $ svn mv lxbios.spec nvramtool.spec
        $ svn ci
    
     3. Rename lxbios directory:
        $ svn mv lxbios/ nvramtool/
        $ svn ci
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eec5ff4ccb48a640e8a289f1faabee4ff2587005
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Mar 1 18:49:39 2008 +0000

    Small coding style fixes and documentation updates (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a04027efcac0d2f7c88e726bc0bf47fa337ca085
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sat Mar 1 15:33:03 2008 +0000

    Create a genacpi directory below util/ which will hold all acpi related
    code/data generation utilities.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b6b63eac0a7532a35db4a14f774d2e990f4a1fa
Author: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Date:   Thu Feb 28 23:10:38 2008 +0000

    In pci_device.c, the class for VGA was not tested properly, leading to
    no VGA output from coreboot, even after the boot-rom was executed
    properly (CONFIG_PCI_ROM_RUN) or no boot-rom execution with
    CONFIG_VGA_ROM_RUN at all. According to the header file device.h, the
    class field of struct device is '3 bytes: (base,sub,prog-if)'.
    
    Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
    Acked-by: Torsten Duwe <duwe@lst.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17632a205e08272a85eb468c685924b83ec6a5e7
Author: Ward Vandewege <ward@gnu.org>
Date:   Tue Feb 26 04:36:52 2008 +0000

    Temporarily disable the fan control patch from this morning; it turns out to
    stop the CPU fan on the m57sli v1.1 (PLCC) entirely, which is less than
    desirable. I did not notice before because my board ran fine for about 15
    minutes before the CPU overheated.
    
    Thankfully the board has a good failsafe mode - it just switches off when the
    CPU gets too hot, without permanent damage.
    
    I'm debugging this and plan to commit a proper fix later in the week.
    
    This is not really trivial, but the tree is dangerous in the current state so
    I'm self-acking.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0be73bbf3014d3e7a5d519bb6023c99374df3322
Author: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Date:   Mon Feb 25 22:32:41 2008 +0000

    This patch adds support to dump other registers than the primary
    pnp-style configuration registers, using the new option -e/--extra-dump.
    This patch only adds dumping of the Environmental Controller
    configuration registers for the IT8716f chip.
    
    Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
    
    I (Carl-Daniel) checked the data sheets of the whole IT87[012] series
    and although the environment controller is sometimes called fan
    controller, the location of the register is the same for all models.
    
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 56cf01f29d7549f11cdd329d5ca8a2e163665f3a
Author: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Date:   Mon Feb 25 19:36:20 2008 +0000

    This patch adds automatic fan control for the CPU fan on the m57sli
    board.
    
    This is done via the ec_init routine in a source file in the
    mainboard/gigabyte/m57sli directory. A Config variable 'HAVE_FANCTL' has been
    added to notify superio.c to get the ec_init externally.
    
    I (Ward) have tested this on the PLCC and the SOIC/SPI version of this board.
    It works.
    
    Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8684520b94a87cb20de1b9c41dfa902f71cb00d4
Author: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Date:   Mon Feb 25 10:15:10 2008 +0000

    This trivial patch removes an unused local variable, thus getting rid of
    a compiler warning.
    
    Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0be722c5087f382ec372c9f0c98d76c8cf58e711
Author: Ward Vandewege <ward@gnu.org>
Date:   Thu Feb 21 21:00:19 2008 +0000

    The proprietary VGA rom is only 36K on Tyan s2882, not 48K.
    
    Tested on real hardware.
    
    This is a trivial patch.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd3f93e33038be965c971a6974d580f55934b854
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Thu Feb 21 00:56:14 2008 +0000

    Add support for the Via CN700 with a C7 CPU and DDR2 RAM. Only a single DIMM is
    working for now, and more work is needed for it to be fully dynamic. However,
    just about any 128MB-512MB DIMM should work.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f327d9f9540971518e1661e1f50d30ffa6b74173
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Feb 20 17:41:38 2008 +0000

    Route device IRQ through PCI bridge instead in mptable.
    Don't enable pin0 for ioapic of io-4.
    
    1. apic error in kernel for MB with mcp55+io55
    2. some pcie-cards could have pci bridge there, so need to put entries
       for device under them in mptable.
    
    Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8eff1e3d0419f42684fc8a63e1dd0a84eb7e9b50
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Wed Feb 20 15:59:30 2008 +0000

    Initial support for MSI MS-7135 (K8N Neo3) mainboard.
    
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 787e4c9fd5d1d5306589df33328b35746e0cdb35
Author: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Date:   Wed Feb 20 11:11:18 2008 +0000

    flashrom: Add board_enable for Artec Group DBE61 and DBE62
    
    Also add a comment about NULL subsystem IDs leaving the board entry out
    of auto-detection logic.
    
    Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    Acked-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b05d4bb77e5aa53896469481152a1cbacd0396ee
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Feb 19 20:30:25 2008 +0000

     I'm attaching the patch which should fix both problems. Fix the
    undefined u8 type and the bitpos selection in currently unused
    pnp_read_enable function.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb6f88d1d48ab9c5acb33ca4b80b15f7319161dd
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Feb 18 20:43:09 2008 +0000

    Should be part of changeset 3106.
    
    This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7 and 9 are
    changed, but also a SPI flash interface which has enable on bit1 and not bit0.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bcd28f22f473f5ccced4bfc27f3964eeaac6013a
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Feb 18 20:40:02 2008 +0000

    Attached patch fixes two typos in the sio_setup routine (comment + wrong exitLDN
    device) and sets the chipset voltage from 1.6V to 1.5V.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8dcab7816469c6ba2a78f6cd66a1c254e8421f3b
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Feb 18 20:37:49 2008 +0000

    This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7 and 9 are
    changed, but also a SPI flash interface which has enable on bit1 and not bit0.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b8af012b631d8a086a7384c192f706eca25fcb3
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Feb 18 20:35:27 2008 +0000

    Use virtual LDNs. It enables the GPIOs correctly (it preserves the GPIO5/2 from a sio_setup. As side effect I can now
    have GAME and MIDI portsenabled.
    
    It has been tested with my board. It produces same results.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 623df6763cb344fdac0f94b089743a1888e62cee
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Feb 18 20:32:46 2008 +0000

    Some SIO/PNP devices are abusing register 0x30 for multiple LDN enables, like
    mine W83627EHF.
    
    This patch introduces a concept of virtual LDN. Each virtual LDN is unique, but
    maps to original LDN and bit position in register 0x30.
    
    VirtualLDN = origLDN[7:0] | bitpos[10:8]
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b34eea348cb7d6d9c93d17d51a1f322114b8f15d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Feb 15 18:16:06 2008 +0000

    Importing mkelfimage from
    ftp://ftp.lnxi.com/pub/mkelfImage/mkelfImage-2.7.tar.gz
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 46fc14dcc8cdba1d66ae6fa9fdcbbf33265d676e
Author: Clark Rawlins <clark@bit63.org>
Date:   Thu Feb 14 23:22:20 2008 +0000

    With this small change it is possible to build flashrom again when
    specifying custom CFLAGS/LDFLAGS from the make command line like:
    
      make CFLAGS="..." LDFLAGS="..."
    
    I need to do this when building flashrom in a cross compiler environment
    like buildroot for a foreign target.
    
    Signed-off-by: Clark Rawlins <clark@bit63.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9792a034e4d56e16d6db7e45574013585cd5c452
Author: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Date:   Mon Feb 11 14:32:45 2008 +0000

    flashrom: further cleanups to enable_flash_cs5536
    
     - Remove the "enable write to flash" message, as the caller appears to
       already report that.
    
     - Move the 'modprobe msr' suggestions to the first lseek64 error handling, as
       we get an error there already.
    
     - Rename a perror string from "read" to "read msr", as we use the latter
       already in this function for another read.
    
    Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5eb25bf48fa65f1f70888954992feb3e8db49308
Author: Marc Jones <marc.jones@amd.com>
Date:   Sat Feb 9 13:06:45 2008 +0000

    add $(CROSS_COMPILE) to ar calls.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f7b7fb82a24ad8fea85035641cc4760b5857519
Author: Luc Verhaegen <libv@skynet.be>
Date:   Sat Feb 9 02:03:06 2008 +0000

    Flashrom: Add board enable for VIA EPIA SP.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2995cc69f7308a2e9dec527b7b364bdfbe010d79
Author: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Date:   Fri Feb 8 10:10:57 2008 +0000

    Improve error handling and make RCONF_DEFAULT_MSR address be a constant.
    Also, move a big code comment to the top of enable_flash_cs5536().
    
    Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99062ae5adbb6fa498d84ce69abbad6f6edea6c3
Author: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Date:   Fri Feb 8 09:59:58 2008 +0000

    This implements support for devices using AMD Geode companion chip
    CS5536 that have the Boot ROM on NOR flash that is directly connected to
    FLASH_CS3 (Boot Flash Chip Select).
    We need to write enable it in the NORF_CTL MSR register for flashrom to
    be able to write to it, including JEDEC probe commands.
    
    This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on
    the DBE61.
    
    Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d2be99c62d9bbd6af437f6a688abae7559839cd3
Author: Ward Vandewege <ward@gnu.org>
Date:   Thu Feb 7 22:53:53 2008 +0000

    Change payload location in 'normal' - this was missed in r3992 and thus breaks buildrom.
    
    This is a trivial patch.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b0627a3b2b537e1d7da2e4fd1f4373bc77a23aa
Author: Myles Watson <myles@pel.cs.byu.edu>
Date:   Thu Feb 7 22:42:22 2008 +0000

    This is a trivial patch.  I missed one of the ROM names when I converted them to coreboot.rom
    
    Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
    Acked-by: Myles Watson <myles@pel.cs.byu.edu>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2370fd81b4acafdbecce7327141f964e5122bb3c
Author: Ward Vandewege <ward@gnu.org>
Date:   Thu Feb 7 21:50:22 2008 +0000

    Make the check for -fno-stack-protector fail silently, if it fails.
    
    This is a trivial patch.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8c2aa2ce8fb74bd8bf3407e0a20240c7f41eadf
Author: Myles Watson <myles@pel.cs.byu.edu>
Date:   Thu Feb 7 20:37:37 2008 +0000

    Change references to qemu in Coreboot-v2 calls to qemu-x86.
    
    The patch was followed by these svn commands:
    
    svn mv targets/emulation/qemu-i386/ targets/emulation/qemu-x86
    svn mv --force targets/emulation/qemu-i386/ targets/emulation/qemu-x86
    svn mv --force src/mainboard/emulation/qemu-i386/
    src/mainboard/emulation/qemu-x86
    svn mv --force src/cpu/emulation/qemu-i386/ src/cpu/emulation/qemu-x86
    
    Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2b380ad8588a6c6cd9d334a34704ee86dc43550
Author: Myles Watson <myles@pel.cs.byu.edu>
Date:   Wed Feb 6 22:33:50 2008 +0000

    This patch changes the Config.lb files and adds Config-lab.lb files for
    architectures supported by buildrom.
    
    Myles
    
    Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c23b3a57321dfa1b3341608074facde81aa2a8de
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Feb 6 22:07:58 2008 +0000

    Handle JEDEC JEP106W continuation codes in SPI RDID. Some vendors like
    Programmable Micro Corp (PMC) need this.
    Both the serial and parallel flash JEDEC detection routines would
    benefit from a parity/sanity check of the vendor ID. Will do this later.
    
    Add support for the PMC Pm25LV family of SPI flash chips.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Chris Lingard  <chris@stockwith.co.uk>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7c92a6dc4e72ad5d7dba1b23d7a8d7e914cf1e9
Author: Myles Watson <myles@pel.cs.byu.edu>
Date:   Tue Feb 5 21:53:15 2008 +0000

    This patch changes all rom names that aren't coreboot.rom in Config.lb files.
    
    I think that since the directory specifies the architecture and the
    board, it is redundant information to name it something else, and it
    makes it more difficult to automate the build process (buildrom).
    
    Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb5c9fb9e3e5eb6591b197d9b24f06059400d370
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Feb 5 09:21:46 2008 +0000

    Factor out print_conf() from Geode LX mainboard directories. The
    following mainboard files had identical Geode LX specific print_conf()
    implementations:
    mainboard/amd/db800/mainboard.c
    mainboard/amd/norwich/mainboard.c
    mainboard/digitallogic/msm800sev/mainboard.c
    mainboard/pcengines/alix1c/mainboard.c
    Move print_conf() to northbridge/amd/lx/northbridge.c where it belongs.
    
    Add a copyright notice to mainboard/digitallogic/msm800sev/mainboard.c.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 10aca3cae2c7199027f04f3dfeb5f8df7c0ed8f3
Author: Florentin Demetrescu <echelon@free.fr>
Date:   Fri Feb 1 23:14:40 2008 +0000

     This patch fixes the decoding of the IO address range 0x0820->0x0827 into the
    LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI
    interface of the IT8716 SIO chip.
     Changes :
      1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some
    functions of a PNP device can have more than 12 resources (ex the GPIO function
    of IT8716f), in which case one could have an "array overflow" inside the device
    structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at
    device init time..)
      2) - define resource masks for the GPIO function in
    src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO
    ranges which are set into the LPC bridge of the SB are very strange (f.ex.:
    0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the
    GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching
    by the init code
      3) - enable the flash SPI interface into
    src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource
    into the GPIO function). I know that this is problematic because not all m57sli
    boards are SPI, but .. do anyone have a better idea how to handle this?..
    
    Signed-off-by: Florentin Demetrescu <echelon@free.fr>
    
    I (Ward) have verified your patch on a rev2 of this board (it works!) as well
    as on a rev1 (plcc). It does not affect flashing on rev1 nor have any averse
    side effects that I noticed, so I think this patch should go in.
    
    Acked-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8a74c95d175f606aa50fa18ff30e4bed1795053
Author: Ward Vandewege <ward@gnu.org>
Date:   Fri Feb 1 23:07:04 2008 +0000

    This patch reverses an erroneous change that sneaked in during r2972, and broke
    flashrom on the plcc-based rev 1 and 1.1 of the Gigabyte m57sli-s4 board.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3dd1b7e57e0ed6c52889ef14a97fb135c2bbc37
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Jan 28 22:55:47 2008 +0000

    v2:  Fix Serengeti-Cheetah flags too
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71a82254ef53fde91d0e9abcfb90c09257e74ffa
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon Jan 28 19:22:29 2008 +0000

    [V2]:  Add CFLAGS to targets to suck in any passed in flags
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca31bc3cd5bbc50eec9d22b6091c2a3e510c270b
Author: Jon Dufresne <jon.dufresne@gmail.com>
Date:   Mon Jan 28 00:04:23 2008 +0000

    Fix mptable util so the output will compile
    
    Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d27aa6eff5d48367be8c40d1e4b1a9385444078a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jan 27 17:25:49 2008 +0000

    Add support for the Abit BE6-II V2.0 board.
    Tested on actual hardware by Sergei Antonov <saproj@gmail.com>.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Sergei Antonov <saproj@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e2bbcb10d1e477ce3965c5c4a0da902265239811
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jan 27 16:21:21 2008 +0000

    Make the vendor name optional in the -m flashrom parameter when there's only
    one board name that matches. The full syntax still works, and is required
    when two vendors have boards with the same names.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3bbf2ff789791ca6fe3eb9fc7d3c92ce1fc86367
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Sun Jan 27 14:12:54 2008 +0000

    Add a new record type "console" for lbtable, and insert one record
    for each output device we support, so the payload can figure out
    where to find consoles that the user cares about.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d94dead69b150492646453184ae64d15744fc11
Author: Peter Stuge <peter@stuge.se>
Date:   Sun Jan 27 07:17:14 2008 +0000

    Forgot to add Spansion S25FL016A to README, trivial.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 25a37449c5aefa69a8bc134254f38adda1ad36a0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Jan 26 16:57:03 2008 +0000

    This patch fixes the remaining stack protector problem on v2. The DISTRO_CFLAGS were not being
    included on the CC line for cache_as_ram_auto.c
    
    Tested on ubuntu, where formerly it failed.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2db94642992c2db99da7283965f260e16f669738
Author: Marc Jones <marc.jones@amd.com>
Date:   Sat Jan 26 07:35:47 2008 +0000

    Correctly disable the ROM area Write Protect bit in the Geode LX.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    Tested on the pcengines alix1c and works fine.
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 873312d69964b76f398023513f09587e74fdec10
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Jan 25 19:31:26 2008 +0000

    bsh/ksh-clone and make(1)-syntax don't go well together
    (unlike 5 lines later where make syntax is emitted into a file)
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c2a0c144557331ec04a9ab0617e31222011cda6
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Fri Jan 25 18:28:18 2008 +0000

    This patch adds a new record type for lbtable to provide information
    about a serial port. If a port is defined in the board configuration,
    add it to lbtable.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a6177b7204b0a40555486274b8219993304ba42
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Jan 25 15:08:37 2008 +0000

    Various small fixes and updates for lxbios (trivial).
    
     - Update website URL to http://coreboot.org/Lxbios.
    
     - Use svn:keywords property to actually expand the $Id$ entries.
    
     - Update COPYING to the latest version from
       http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2a2a5ee2e498d648e00ac6af1ed859be6c194ea
Author: Peter Stuge <peter@stuge.se>
Date:   Fri Jan 25 01:52:45 2008 +0000

    Add ids and chip entry for Spansion S25FL016A to flashrom, tested,
    working.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14a3af111d5fa6bd72dc1cb4e457f70f23ce507b
Author: Marc Karasek <marc.karasek@sun.com>
Date:   Tue Jan 22 16:09:36 2008 +0000

    Use "--build-id=none" as linker flags if build-id is supported.
    That fixes a compilation failure.
    
    Signed-off-by: Marc Karasek <marc.karasek@sun.com>
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Myles Watson <myles@pel.cs.byu.edu>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb9c1aa54e8167cdcef6b633f55021c4b85ac194
Author: Harald Gutmann <harald.gutmann@gmx.net>
Date:   Tue Jan 22 16:03:19 2008 +0000

    Here is just a little and simple patch to get the MX25L3205D working.
    I've tested and verified the chip myself, and it seems to work
    everything like supposted, since Carl-Daniel has patched flashrom to
    use the read funktion on verifying.
    
    "benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb
    Calibrating delay loop... OK.
    No coreboot table found.
    Found chipset "NVIDIA MCP55", enabling flash write... OK.
    Found board "GIGABYTE GA-M57SLI-S4": enabling flash write...
    Serial flash segment 0xfffe0000-0xffffffff enabled
    Serial flash segment 0x000e0000-0x000fffff enabled
    Serial flash segment 0xffee0000-0xffefffff disabled
    Serial flash segment 0xfff80000-0xfffeffff enabled
    LPC write to serial flash enabled
    serial flash pin 29
    OK.
    MX25L3205 found at physical address 0xffc00000.
    Flash part is MX25L3205 (4096 KB).
    Flash image seems to be a legacy BIOS. Disabling checks.
    Verifying flash... VERIFIED.
    benchvice flashrom # ls -l test.4mb
    -rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb
    
    Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a6941beb43956c6cd30d44b5c6a97c747bc2f63a
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Jan 22 15:19:01 2008 +0000

    Flashrom did not use the read function for verifying, it used direct memory
    access instead. That fails if the flash chip is not mapped completely.
    If the read function is set in struct flashchip, use it for verification
    as well.
    
    This fixes verification of all SPI flash chips >512 kByte behind an
    IT8716F flash translation chip.
    
    "MX25L8005 found at physical address 0xfff00000.
    Flash part is MX25L8005 (1024 KB).
    Flash image seems to be a legacy BIOS. Disabling checks.
    Verifying flash... VERIFIED."
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 468413a337e0cff9da3040907ddaa7b08dc08e2a
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Jan 22 14:37:31 2008 +0000

    Make sure we delay writing the next byte long enough in SPI byte
    programming.
    Minor formatting changes.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 21efd9ffe2bc51463bd4278def63e3c294907da2
Author: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Date:   Mon Jan 21 23:55:08 2008 +0000

    Omitting the wait for SPI ready when there is no data to be read, e.g.
    readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing
    programming time for SST25VF016B to 40-45 secs.
    
    Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 679c62c083d4e4edbc292160d441dbfe6ae3cd40
Author: Bernhard Walle <bernhard.walle@gmx.de>
Date:   Mon Jan 21 15:24:22 2008 +0000

    This patch adds version information to flashrom. Because 'v' and 'V'
    are already in use, the patch uses 'R' (for release) and, of course,
    '--version'.
    
    Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
    Acked-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ce4a19b20f22f74573a93566d4a202e58f00758
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 20 01:59:43 2008 +0000

    last try i hope. Building with a payload changes the result of the rom
    image. Even if the rom image size is not changed, it can make the linking fail.
    It's almost a heisen-bug, only there if you don't watch.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c2bcc893ea9e7539b9b4a066dc796aa8cde6f1ea
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Jan 20 00:24:23 2008 +0000

    give it 2k more space for abuild. let's look into this anyways, but get rid of
    the impression that the cheetah on fam10 is broken just because we're using a
    too new compiler for abuild. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 593f5aab0380177460880ec42687ae04df0dbc8e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Jan 19 09:43:48 2008 +0000

    Add Bingxun Shi <bingxunshi@gmail.com> to the list of contributors (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb348035a38f1f01afeb6928c8abbdc2051ecf80
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Jan 19 09:40:17 2008 +0000

    Small superiotool fix to detect more Winbond W83627EHF chips. The
    patch is tested on actual hardware.
    
    As per datasheet the ID should be 0x886? for those chips.
    Not mentioned in the datasheet, but sensors-detect says
    0x8853 is also possible. Also, the ASUS A8V-E Deluxe
    (W83627EHF) has an ID of 0x8854 (verified on actual hardware).
    
    So assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34a576fb98b2a66a4ea958ae6f3c8240fdf047db
Author: Bingxun Shi <bingxunshi@gmail.com>
Date:   Sat Jan 19 00:32:07 2008 +0000

    This patch is for winbond w83627DHG superio support in superiotool.
    I have test that on my board, it works ;)
    
    Signed-off-by: Bingxun Shi <bingxunshi@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f0f561f899b6c0faf964202045e196b0876e849
Author: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Date:   Sat Jan 19 00:04:46 2008 +0000

    Support SPI flash chips bigger than 512 kByte sitting behind IT8716F
    Super I/O performing LPC-to-SPI flash translation.
    
    Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd474afd08356bb4dbc7f0b73e9927c05defe3d8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Jan 18 18:04:28 2008 +0000

    Document the --list-supported option. Various small fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d84d9ba4450ea2c0dd4f79460b3b4b79739e8566
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Jan 18 17:48:51 2008 +0000

    Minor documentation improvements/fixes in the README and manpage (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7223ab7c4a2620758fd4f80e0f73d2868d589638
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jan 18 16:17:44 2008 +0000

    rename linuxbios_* files in utils repository.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca374d455cad29c546a2d310c331a4ae431c33f9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jan 18 16:16:45 2008 +0000

    rename linuxbios_* files, too.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 997afe6ca576dcc0117891294b5f51f29864f354
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jan 18 15:34:24 2008 +0000

    util/ renames
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f527e70333e9644f4024737240b9be18f4e2d4d4
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jan 18 15:33:49 2008 +0000

    rename linuxbios -> coreboot
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8df401db3bb6419c8fc9339dcc505332dff33bfe
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jan 18 15:33:10 2008 +0000

    for some reasons the externals did not get committed.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8ee1806ac524bc782c93eccc59ee3c929abddb9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jan 18 15:08:58 2008 +0000

    Rename almost all occurences of LinuxBIOS to coreboot.
    Due to the automatic nature of this update, I am self-acking. It worked in
    abuild.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e61e45402aba2b90997f4f02ca8266cf65a229a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Jan 18 10:35:56 2008 +0000

    Please bear with me - another rename checkin. This qualifies as trivial, no
    code is changed.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c72fcde2735c531f8d1e49778aaa4ac901c2bec3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jan 16 16:25:13 2008 +0000

    rename linuxbios to coreboot
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 552cfb7b74cc0f39aee0c6babecdb045c81073e7
Author: Robinson P. Tryon <bishop.robinson@gmail.com>
Date:   Tue Jan 15 22:30:55 2008 +0000

    Add new --list-supported switch for printing the list of Super I/Os
    supported by superiotool (closes #91).
    
    Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6211ae13c3f366c0121a3b195196607f80cf29d3
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Jan 12 22:29:17 2008 +0000

    Fix the documentation of GPIO setup, tell W83627EHF to use external
    suspend clock (undocumented in datasheet, documented in 'W83627HG-AW').
    Introduce sio_init function for all this.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aeea7c1438c46bd7ba0c950a26586ba16f2da19c
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sat Jan 12 21:44:57 2008 +0000

    Via C3 datasheets don't make any mention of microcode updates, and the
    C7 bios programmer's guide explicitly states they're not necessary, and
    leaves it at that. Even if they are possible and exist, we don't have
    any info on it, nor any updates, so drop these unneeded references.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c02d8d88dcca441fcd0015818198e99b4c9c1e02
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jan 11 22:37:27 2008 +0000

    Fix these to use a more standard relative path for payload.
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23b00b8909bb30ef57cabc3c0915d6f7129467df
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jan 11 18:23:47 2008 +0000

    Add the ability to extend CFLAGS as needed for several new distros
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6322baa50c96c5ce24c3f1b9b072fb7451fd5967
Author: Bernhard Walle <bernhard.walle@gmx.de>
Date:   Fri Jan 11 00:32:07 2008 +0000

    This patch removes '\n' from the help output since this looks a bit strange.
    After the patch [...] The line length is still below 80 characters.
    
    Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
    Acked-by: Torsten Duwe <duwe@lst.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed8dc58efa263d0f4a1b63ca455dae9db756a84f
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Jan 10 17:59:25 2008 +0000

    Add a workaround for a bug in some binutils version which strictly
    interpret whitespace as macro argument delimiter. Since the code is
    preprocessed by gcc and the tokenizer may insert whitespace, that can
    fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1923fc41be83ab7c6bdb0262d690729c5f713670
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Jan 10 17:48:25 2008 +0000

    This patch introduces 4k CAR size granularity for the AMD x86 CAR code.
    For the old supported CAR sizes, the newly generated code is
    equivalent, so it should be a no-brainer.
    
    Benefits:
    * a nice code size reduction
    * less #ifdef clutter for Family 10h
    * paranoid checks for CAR size
    * clear abstractions
    
    This has been tested by Marc Jones and Jordan Crouse.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e152be16ef9c96313224702fec2c4dc36e70d57
Author: Harald Gutmann <harald.gutmann@gmx.net>
Date:   Thu Jan 10 13:27:22 2008 +0000

    Enable MX25L8005 support in flashrom. The #defines were already there.
    
    Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 247a423dee40f51b1f6ef07865c55126bd9660d1
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Jan 9 11:37:58 2008 +0000

    Use macros to improve readability of the device-to-pin IRQ assignments
    in GA-2761GXDK mptables.c.
    Thanks to Torsten Duwe for initial code.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: 蔡明耀 (Morgan Tsai) <my_tsai@sis.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 188288a0201b50f8cae4a754fbcf5efbf6e32c05
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Jan 8 19:14:16 2008 +0000

    Fix compilation of Tyan S2735 which was broken by accident in r3038.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2ecb74023b912c62de760cb440a9f7ef4ddb3ff
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Jan 8 17:28:35 2008 +0000

    Remove some DOS line endings accidentially introduced in r3014.
    No code lines affected, so svn blame will not be messed up.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d1aa0a9ebdde08f80406b3ea4e14b9bd8a5e9d4
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Jan 8 17:06:38 2008 +0000

    This patch is an attempt at introducing 4k CAR size granularity for the
    generic x86 CAR code. For the old supported CAR sizes, the newly
    generated code is equivalent, so it should be a no-brainer.
    
    Add a copyright header to the code, the header is derived from the one
    found in the same piece of code in v3.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eaca2c32a32f5078bfc6b8c8d5d6ad43f0fbf96d
Author: Patrick Georgi <patrick@georgi-clan.de>
Date:   Tue Jan 8 10:28:06 2008 +0000

    Ubuntu's gcc doesn't write "install:" in german locales.
    Normalize used locale to "C" before parsing output.
    
    Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7323f1b0c75ccfd271c1fd0133ff12ca5d8ea7a
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Jan 7 13:48:51 2008 +0000

    Add support for the SST25VF040B 4 Mbit SPI flash chip.
    Straight from the data sheet, not tested.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f4c57a96b455333954ecef0ab6a14ac3d009aafa
Author: Torsten Duwe <duwe@lst.de>
Date:   Mon Jan 7 11:13:16 2008 +0000

    Improve readability and remove redundancy by wrapping
    similar smp_write_intsrc calls in preprocessor macros.
    Also add some comments about the actual devices the INTs
    belong to.
    
    Signed-off-by: Torsten Duwe <duwe@lst.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f2f800036d967f18ce93c88908d4d635cbf79fc
Author: Torsten Duwe <duwe@lst.de>
Date:   Sun Jan 6 01:10:54 2008 +0000

    Since a VGA console and the need to run any option ROMs are
    rather independent, lift the implicit (broken) assumption that
    CONSOLE_VGA would also run the ROMs, and transfer it to a new
    config option VGA_ROM_RUN.
    
    This change is minimally intrusive, because all board configs
    that previously assumed CONSOLE_VGA would also run the ROMs
    didn't compile, they had to also specify PCI_ROM_RUN.
    
    Based on patches by Ron Minnich (fix the compile) and Luc Verhaegen
    (separate ROM_RUN from VGA console).
    
    Signed-off-by: Torsten Duwe <duwe@lst.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Luc Verhaegen <libv@skynet.be>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 11e90e06d3409227fd2f04985c226e920ca671b1
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jan 4 17:22:44 2008 +0000

    Add board enable for the gigabyte ga_2761gxdk board
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5f9bd6ac974003df255358ef89d8bcb2b496789
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Jan 4 16:22:09 2008 +0000

    Print at least the vendor for SPI flash chips if the exact chip ID is
    unknown.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 717f66d1ebc4e6ae6e590ec081ae7a8ba698b37f
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Dec 31 14:05:08 2007 +0000

    Unfortunately, EN29F002T, EN29F002AT, EN29F002ANT, EN29F002NT all have
    exactly the same ID. Improve model number printing.
    
    Add EN29F002(A)(N)B support while I'm at it.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Markus Boas <bios@ryven.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85acc09786fe1d3873cda0bba61b30a798071add
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Dec 31 01:49:00 2007 +0000

    Add continuation ID support to jedec.c
    The continuation ID code does not go further than checking for IDs of
    the type 0x7fXX, but does this for vendor and product ID. The current
    published JEDEC spec has a list where the largest vendor ID is 7 bytes
    long, but all leading bytes are 0x7f. The list will grow in the future,
    and using a 64bit variable will not be enough anymore.
    Besides that, it seems that the location of the ID byte after the first
    continuation ID byte is very vendor specific, so we may have to revisit
    that code some time in the future.
    
    (Suggestion for a new encoding:
    Use a two-byte data type for the ID, the lower byte contains the only
    non-0x7f byte, the upper byte contains the number of 0x7f bytes used as
    prefix, which is the bank number minus 1 the vendor ID appears in.)
    
    Add support for EON EN29F002AT.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1704179acdc62da788e12474523fe89dea9fc920
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Dec 31 01:18:26 2007 +0000

    This fixes a few vendor IDs to conform with JEDEC publication 106W
    (JEP106W), adds some device IDs and provides information about
    non-conforming IDs.
    The EON change is left to the patch adding EON chips.
    
    This patch should have no effect on code generation.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1229fe4c9b7d6baef94ccd7ef467e8d3cfc74003
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sun Dec 30 11:59:10 2007 +0000

    The following mainboards had a file named microcode_updates.c in their
    mainboard directories, but the code was not referenced anywhere.
    intel/jarrell
    dell/s1850
    supermicro/x6dhr_ig2
    supermicro/x6dhr_ig
    supermicro/x6dhe_g2
    supermicro/x6dhe_g
    Besides that, the contents of these files were either duplicates of
    src/cpu/intel/model_f3x/microcode_M1DF340E.h or
    src/cpu/intel/model_f3x/microcode_M1DF3413.h.
    
    svn remove the following files:
    src/mainboard/supermicro/x6dhe_g/microcode_updates.c
    src/mainboard/supermicro/x6dhe_g2/microcode_updates.c
    src/mainboard/supermicro/x6dhr_ig/microcode_updates.c
    src/mainboard/supermicro/x6dhr_ig2/microcode_updates.c
    src/mainboard/dell/s1850/microcode_updates.c
    src/mainboard/intel/jarrell/microcode_updates.c
    
    Abuild tested, as expected no failures.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 19cf6a389027c055b2b278ad357e43a7d8c12643
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sat Dec 29 11:05:59 2007 +0000

    All SPI chips mentioned in flashchips.c had their sector size listed as
    page size. Fix that. Page size is uniform 256 bytes for SPI.
    
    A sector/block size field in struct flashchip would be nice, though.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29df7a9662e935ede0996baf7f01ef49aace5063
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sat Dec 29 10:15:58 2007 +0000

    Print the chip status register for all SPI chips on probe if verbose
    output is specified.
    Pretty-print the chip status register (including block lock information)
    for ST M25P family and Macronix MX25L family chips.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d0ad60a795fb27008e2f7f8859a2ba34cf43c9e0
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sat Dec 29 10:14:38 2007 +0000

    Add 25VF016B support to flashrom. Untested, but verified against the
    data sheet.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cb314b939934fd9fc562366a42b328963439fbc
Author: Ed Swierk <eswierk@arastra.com>
Date:   Fri Dec 28 00:23:29 2007 +0000

    Add Intel 3100 integrated northbridge/southbridge/superio PCI IDs.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 679e14e3487998a383b099b181be6fcf2183f671
Author: Torsten Duwe <duwe@lst.de>
Date:   Fri Dec 21 17:21:03 2007 +0000

    Add an interrupt entry for the onboard firewire controller,
    Bus 1, device 10 (function 0 only), routed to IO-APIC pin 18
    (verified on an v1.0 board).
    
    Signed-off-by:  Torsten Duwe <duwe@lst.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc5bccffdeefa99a468ba06f4aefdc0e4305bc09
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Dec 21 16:38:21 2007 +0000

    Change default payload to /tmp/filo.elf (trivial).
    
    It's easier to tell users "copy your payload to /tmp/filo.elf" than have
    them guess paths or modify Config.lb files etc.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8f1bd6a6bb3d92158f0fc4c9b306c40ce35eddc9
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Wed Dec 19 19:30:36 2007 +0000

    More abuild fixes, this should be the last (trivial)
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17217ac298eeea001dde6b04ac496255a4075a44
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Wed Dec 19 18:29:59 2007 +0000

    Fix for newer iasl versions (trivial)
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9a8d11e0c2d67797320652e4dbf1edc1c291c7d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Dec 19 17:59:50 2007 +0000

    trivial fix for abuild.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 56e7046cf7a254998dce638297f35677928dfdec
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Wed Dec 19 08:07:37 2007 +0000

    Small fix to make the abuild happy, add ROM_SIZE to target/*/Config.lb,
    using the default from src/mainboard/*/Options.lb (trivial)
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba8965c0395a295828911cb375e7122051e73962
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Dec 19 01:52:11 2007 +0000

    Changed the stop_this_cpu() to just hlt.
    Removed local APIC INIT (don't worry the APIC and AP are still initialized).
    
    The local APIC INIT seemed to be the incorrect thing to do to stop an AP.
    The Intel Multiprocessor specification indicated that a vector should be set
    and a START should happen following an INIT. Then AP will execute the
    instructions pointed to by the vector. There is no vector or start in
    stop_this_cpu(). This seems to put the AP in an in-between state. In the case
    of Barcelona the AP's MSRs and PCI register are not accessible by the hardware
    debugger.
    
    The better solution seems to be to just put the AP in a hlt and allow the AP
    to go into C1. Then APIC managing software running on the BSP can program the
    AP as needed.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ce8bfd251cfee8a19c09217ace28a5be2684311
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Dec 19 01:49:44 2007 +0000

    Initial AMD Serengeti_Cheetah_FAM10 platform for Barcelona support.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0da5cdeac2b787f5665c3cbc208c3c2adcf331c1
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Dec 19 01:36:46 2007 +0000

    Additional early AMD8111 southbridge support for Barcelona platforms.
    Check that the SMBus controller is found and stop on an error.
    Clean up and add additional path through the 8111 reset functions.
    
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <myles@pel.cs.byu.edu>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ae8c8822068ef1722c08073ffa4ecc25633cbee
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Dec 19 01:32:08 2007 +0000

    Initial AMD Barcelona support for rev Bx.
    These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <myles@pel.cs.byu.edu>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2006b38fed2f5f3680de1736f7fc878823f2f93b
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Dec 19 00:47:09 2007 +0000

    Whitespace and other code cleanup in peperation for AMD Barcelona support.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Myles Watson <myles@pel.cs.byu.edu>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 244dd82fd693aafb0e595941d91b775edebd8fc6
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Dec 17 22:22:40 2007 +0000

    Add support for ST M25P05-A, M25P10-A, M25P20, M25P40, M25P16, M25P32,
    M25P64, M25P128 to flashrom. ST M25P80 support is already there.
    Not tested, but conforming to data sheets and double checked.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e9690bddd5007cd065ffb646eda473a37a49c4e5
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Mon Dec 17 22:10:00 2007 +0000

    Add dump support for NSC PC87317.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ef47da471fe22b7d3ae33145efa85b40c89bbc9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Dec 17 21:34:53 2007 +0000

    Enable IDE legacy port access for all 440BX based boards per default, as
    this is needed (at the very least) to make FILO work on these boards.
    
    Disable UDMA/33 per default, which is slower but the safe choice, as we
    don't know which IDE devices a user has attached, and some don't support
    UDMA/33 very well or at all.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12a3f1edecbbc211327202782fbda027faea38b8
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Dec 17 14:33:32 2007 +0000

    To make it easier to add new SPI chips to flashchips.c, rename functions
    with multiple possible opcodes from linear numbering at the end (_1, _2)
    to include the opcode at the end (_60, _c7). That way, you only have to
    take a short look at the data sheet and choose the right function by
    appending the opcode listed in the data sheet.
    No functional changes.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b408fd23794c6d012be79173021e532d1b47ba6
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sun Dec 16 21:15:27 2007 +0000

    Add support for ST M25P80 chips to flashrom. Detection was tested.
    Print status register before erase to help debugging block locks.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9a677b4b31b5c56d953c549e626d3989d7c3623
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Fri Dec 14 20:00:58 2007 +0000

    Add dump support for SMSC LPC47M192.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7e12e2a9d27e91b86402322b61a272704204a3d
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Fri Dec 14 00:04:16 2007 +0000

    Add dump support for NSC PC97317.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa6dd7407ddd94c81453acad69cef96de22aac3b
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Thu Dec 13 23:56:16 2007 +0000

    Add detection and dump support for NSC PC97307.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48c7032c28a2d9e247caecf411f9d56666f715b5
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Thu Dec 13 23:41:45 2007 +0000

    Add dump support for NSC PC8741x.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 850c01cacf799b0b738587fb31d631025f364a24
Author: Frederico Silva <frederico.silva@gmail.com>
Date:   Mon Dec 10 16:57:59 2007 +0000

    Add support for more atmel chips:
    AT49F002
    AT49F002N
    AT49F002T
    AT49F002NT
    
    Only tested the read function on AT49F002T.
    datasheet @ http://www.atmel.com/atmel/acrobat/doc1017.pdf
    
    Signed-off-by: Frederico Silva <frederico.silva@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 15674b78beb5a9f00d638fe5fc70cabe7f440a66
Author: Myles Watson <myles@pel.cs.byu.edu>
Date:   Sun Dec 9 17:18:29 2007 +0000

    This adds the same line (uses CONFIG_PRECOMPRESSED_PAYLOAD) to every
    Options.lb file that already had a "uses CONFIG_COMPRESSED_PAYLOAD_LZMA"
    line in it.
    
    I figure that only adding it to the files that already have support
    for LZMA payloads makes sure I don't break anything.
    
    Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
    Acked-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94a84dee9eba9dd3e8204a8cc59e8036bb7708f8
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Sat Dec 8 00:17:19 2007 +0000

    Add detection and dump support for NSC PC87309.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 11887f258da9ad90515c69fb82fce0046dac7e1c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Dec 7 23:55:20 2007 +0000

    Add/fix some LDN descriptions (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 25df0c586ab6f57ebfad454a4b3c8388eda2ca69
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Fri Dec 7 21:55:12 2007 +0000

    Fix typo. According to National's datasheet PC87317 has SID = 0xd0 and
    PC97317 has SID = 0xdf. PC87371/PC97371 do not seem to exist.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 435325e7ac4f94e64c9b1c253212564956da4bed
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Dec 5 19:26:55 2007 +0000

    Remove the coherent_ht_car.c file. It is exactly the same as
    coherent_ht.c (save one empty line removed) so there's no use
    to keep it around.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 186a3875dc1868afd209c73c08a9c00eafeab761
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Dec 4 21:49:06 2007 +0000

    Various coding style fixes, constification, fixed typos (trivial).
    
    Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per
    http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17e993214f72149aa86ba68aaa99a02141991996
Author: Ward Vandewege <ward@gnu.org>
Date:   Tue Dec 4 01:15:29 2007 +0000

    Enable vga option rom support for 1MB rom chip, which is what the h8dmr ships with (trivial).
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d795b9a9ec0744b241df5147efd6afbac4e1b64e
Author: Jonathan A. Kollasch <jakllsch@kollasch.net>
Date:   Sun Dec 2 19:03:23 2007 +0000

    Add board-enable for Acorp 6A815EPD.
    
    Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9da69f83d9fd3b872afb38c24b373b0807c76b00
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Nov 30 02:08:26 2007 +0000

    Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s):
    
     - Implement ISA related support:
       - Initialize the RTC
       - Enable access to all BIOS regions (but _not_ write access to ROM)
       - Enable ISA (not EIO) support
       - Without the *_isa.c file, the Super I/O init is never performed
     - Improve IDE support:
       - Add config option to enable Ultra DMA/33 for each disk
       - Add config option to enable legacy IDE port access
     - Implement hard reset support
     - Implement USB controller support
     - Various code cleanups and improvements
    
    The code partially supports southbridges other than the 82371EB (but
    which are very similar), more complete support will follow.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d43b343cf390f67461b3121d101d16ebf9b5975
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Nov 29 15:01:53 2007 +0000

    fix abuild.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59b99d9071b0381e197515cf94aede6e58a766a3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 29 02:43:50 2007 +0000

    Various small fixes (trivial).
    
     - Add missing contributors to the README.
    
     - Drop obsolete -D option from manpage.
    
     - Only list contributors who added non-trivial amounts of code as copyright
       holders (and do not list those who merely provided register dump support
       for Super I/Os). Those contributors are still listed in the README,
       of course. See discussion in the thread starting at
       http://www.linuxbios.org/pipermail/linuxbios/2007-October/025516.html
    
     - Make a function static.
    
     - Fix incorrect URL in code comment. Drop obsolete comments.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e290d38e4bb856b9d12cc3bc5acdd5d21e7f895
Author: Mondrian Nuessle <nuessle@uni-mannheim.de>
Date:   Thu Nov 29 02:28:55 2007 +0000

    Flashrom does not work after booting LinuxBIOS on the Iwill DK8-HTX board,
    according to mcqmcqmcq@fastmail.fm. Fix it.
    
    Signed-off-by: Mondrian Nuessle <nuessle@uni-mannheim.de>
    Acked-by: mcq <mcqmcqmcq@fastmail.fm>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 447aafe5db7a94556537f227761e376a6e2d0530
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 29 01:44:43 2007 +0000

    Restructure/rename/comment a few 82371XX-related PCI IDs (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8708c1b7c3e2d73ec5c88071043f0eb33120fb87
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 29 01:25:29 2007 +0000

    Update AMD CPU IDs in model_fxx_init.c with information from
    the latest version (Rev. 3.73, October 2007) of the 'Revision Guide for
    AMD Athlon 64 and AMD Opteron Processors' datasheet.
    
    Also, add information about the CPU socket for each ID (as per datasheet).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 020724fc70ef3740cc12f6be3dc5c354959029a8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 27 01:24:46 2007 +0000

    Drop the unfinished, non-working Bitworks IMS board.
    
    It never worked in v2 (the v1 port did work AFAIK, though), and it's
    not really useful as reference for other boards anymore (as we now
    have a dozen or so 440BX boards which work in v2).
    
    This is a specialized, custom board (not sold on the "public market"),
    so it's probably not useful for pretty much everyone out there anyway.
    
    We can easily re-add it later (based on one of the other 440BX boards)
    should there be interest and/or someone with the hardware to test.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 254f47ef982113c07774f2df50258924f63dee93
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Nov 26 21:43:21 2007 +0000

    Correction to irq tables.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29cbb367b0a16464d53b2728600381af2bb308c1
Author: Robinson P. Tryon <bishop.robinson@gmail.com>
Date:   Sun Nov 25 21:43:29 2007 +0000

    Dump support for SMSC FDC37C67x.
    
    Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d1bfaa92e8b30dc9a834fa6cdf8c2dd525029441
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sun Nov 25 03:49:43 2007 +0000

    More abuild fixes, the previous ones weren't enough. Hopefully this covers everything.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c29533a37daa2ec09bf88cf4399ecd83e5c427d8
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sun Nov 25 01:08:20 2007 +0000

    Small abuild fix for the iwill dk8_htx and latest iasl. Building this still fails for me, but it's an lzma error and probably Debian's fault.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 44a115706b93d44e2e3da6714ba01915652d1008
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sun Nov 25 00:58:09 2007 +0000

    abuild fix for the asus a8v-e_se and newest iasl version (trivial)
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4617191ca12d23d467feae9e3117807c74acb077
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sun Nov 25 00:50:06 2007 +0000

    abuild fix for the amd serengeti_cheetah and the latest iasl version (trivial)
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 13f7a00200bb14b98b9cac6e73866a69922ae8a4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 25 00:13:51 2007 +0000

    Fix abuild for ASUS MEW-AM.
    
    You cannot set 'default ROM_SIZE = 0' in Options.lb (and override it in
    targets/*/Config.lb). While it'll work for manual builds, abuild doesn't
    cope with that very well. So set a valid value in Options.lb, too.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc454483b427c0e197af911af6bdbd5a04b22b7a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Nov 24 22:09:38 2007 +0000

    Add support for the ASUS MEW-AM board.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4dea67193e691199da60669088020f3c5e7735a2
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Sat Nov 24 21:49:39 2007 +0000

    Add dump support for the PC87366.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 33715eb95c027380b3d6d37d3a91f4839c936195
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 22 14:55:13 2007 +0000

    Mark devices which are not available on the board with "N/A" to
    make it clearer why they are disabled (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f811edefd916dd11cddbe34f90736b197ed69e92
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 22 03:36:18 2007 +0000

    Dump support for the SMSC LPC47B27x (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c8cf4ad422b45de87dc3a4033e71eaa18078924b
Author: Morgan Tsai <my_tsai@sis.com>
Date:   Tue Nov 20 14:11:24 2007 +0000

    1. Fix pirq routing table setting for GA-2761GXDK.
    2. Southbridge PCIe slots are working correctly now.
    3. Disable keyboard & mouse ports for GA-2761GXDK.
    
    Signed-off-by: Morgan Tsai <my_tsai@sis.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74b29b9e333bd05fae4ff1f59029120ff8f280dc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Nov 17 17:13:52 2007 +0000

    Detection support for more Super I/Os. Small fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 70ab323ae61567a005058f6e7bdd1f6990e6e7fd
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 15 15:52:42 2007 +0000

    Various cosmetic fixes and improvements (trivial).
    
     - Use 'static' where appropriate.
     - Use 'const' where appropriate.
     - Indentation fixes.
     - Add comment wrt init code which is only valid for VT8237R.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e13abe53b49fdd61fcf56bc21b578057c5f1c72f
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Nov 14 17:57:04 2007 +0000

    Gigabyte M57SLI: Fix watchdog clocksource to be external, not internal.
    
    Reason: The existing code does not tell us why it sets the watchdog
    clock at all, but since it appears in cache_as_ram_auto.c instead of
    the usual place (Config.lb) there has to be some meaning to it.
    Simply do what the proprietary bios does: Use the external clock source.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34153ac0b8ef4d99de1d56b0e8733ae124f2ba0b
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Nov 14 15:09:30 2007 +0000

    Autodetect presence of serial flash and set up the board accordingly.
    This enables us to have only one configuration and one set of code for
    all revisions of the Gigabyte GA-M57SLI-S4.
    Flash is now setup correctly for both SPI and LPC flash.
    
    Detection of SPI flash in flashrom on rev. 2.x boards now hangs
    instead of failing. However, that is just an effect of the combination
    of incomplete initialization of the SPI controller and paranoid checks
    in the flashrom SPI code.
    If anyone wants to work on that, he needs a logic analyzer or creative
    imagination. Hint: LPC-to-SPI read passthrough, clock signal.
    
    Remaining issues for the M57SLI: Fan/environment control.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31e805dadbf57e9a88be8814b9582d02e97ab745
Author: Morgan Tsai <my_tsai@sis.com>
Date:   Wed Nov 14 01:34:02 2007 +0000

    * Maintaining SiS south bridge device IDs.
    * Strip unnecessary driver modules.
    
    Signed-off-by: Morgan Tsai <my_tsai@sis.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4c28034e58215542d549761eed87c25b7153b909
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 14 00:30:36 2007 +0000

    Add detection and dump support for the SMSC FDC37N958FR (trivial).
    
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5fd9a78a9d1805fdc8a0ef4759980c9deef377d4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 13 23:32:03 2007 +0000

    Small fix to make abuild happy (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59ef59ea9434f30758ac0aabcedd2a1417d451b8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Nov 13 21:20:13 2007 +0000

    Fix ACPI issues brought up with Intel's latest ASL compiler.
    
    iasl now defaults to put created files into the input file's path, not into the
    current directory.
    
    This (trivial) patch fixes the behavior for the northbridge specific ASL code.
    
    Further checkins to be expected.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9fe02e8c65155355e8f076560d21936d8deedc24
Author: Lane Brooks <lbrooks@mit.edu>
Date:   Tue Nov 13 16:45:22 2007 +0000

    [LinuxBIOS] flashrom support for AMD Geode CS5536
    
    Attached is a patch that enables AMD Geode CS5536 chipset support.  I
    have tested it successfully on a MSM800 board from digital logic.
    
    Signed-off-by: Lane Brooks <lbrooks@mit.edu>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b942e75d2f3c0ccf0198019a706a1c156008b27
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 13 16:24:15 2007 +0000

    Random minor cosmetical or coding style fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc3ccdb6434402098c1648af12d932c15d3b35e7
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Nov 13 15:40:21 2007 +0000

    Add support for FID/VID changes messages.
    
    Upon incoming SMAF message from CPU (C3 or FID/VID change), the SB will
    assert SLP# which is connected to LDTSTOP_L on K8 CPUs. Question is for how
    long. Imho for 100us. Which is more than plenty (2us required) I will try
    to justify this once I know what bios to set in SB.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3adc30eed5b0e3c380893560d96bb754796d960c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 13 15:26:56 2007 +0000

    Small fixes. Drop unneeded or incorrect lines (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3c225a7cb459ae03b639b729f3195bea3bafbc60
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Tue Nov 13 15:16:06 2007 +0000

    Add dump support for NSC PC87360.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d6146c377caee1c0dd888b9b08faeb3c8a3c43f
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Nov 13 14:56:54 2007 +0000

    Fix ATMEL 29C020 detection with flashrom. The JEDEC probe routine had
    a delay of 10 us after entering ID mode and this was insufficient for
    the 29C020. The data sheet claims we have to wait 10 ms, but tests have
    shown that 20 us suffice. Allow for variations in chip delays with a
    factor of 2 safety margin.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d591baa22f52661de836bc4a04ea6c010b0d83de
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 13 14:40:45 2007 +0000

    Drop obsolete failover.c, forgot it in the last commit (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7f6046f0a9d2b2c864f21305bb732cb3cef1d9d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 13 14:31:30 2007 +0000

    Various small fixes to make the Tyan S1846 match the format of
    the other supported 440BX boards.
    
    Fix up totally b0rked static device tree in Config.lb.
    Drop useless and duplicated failover.c, use global one.
    Make CPU init actually work (result: massive speed-up).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9fab090e976d8972421114484b6b34cd86b272c1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 13 14:26:54 2007 +0000

    Add support for the Advantech PCM-5820.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a6ddf253ad88099d40e65e59f16a58c31f53d213
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Nov 13 10:47:11 2007 +0000

    Fine-tune the V-link bus between K8T890 and VT8237R and set
    it to 8X transfer rate (up to 1066 MB/s) similar code placed here would be
    needed for VT8237A/S etc. Using VIA recommended values despite they are for
    K8T890CF, this is K8T890CE (still dont know what is exactly different).
    
    This patch enables the parity error reporting on V-Link, so it enables NMI
    generation for the SERR# errors. The NMI may not be generated, maybe port
    61h needs some tuning too.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a422c2d3c6341c7414018233c0b428414b66630f
Author: Frieder Ferlemann <Frieder.Ferlemann@web.de>
Date:   Tue Nov 13 09:09:33 2007 +0000

    Grouping register dumps by 8 register values per group for better readability.
    Remove trailing spaces within the register dumps.
    
    Signed-off-by: Frieder Ferlemann <Frieder.Ferlemann@web.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c22e8625f55553fdeca442488801484edeca4b1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Nov 12 21:02:44 2007 +0000

    Drop superfluous exit_conf_mode*() calls, we don't want to call them twice.
    Small cosmetic fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 390648df6480fff86acd2a51600fc0352aef7597
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Nov 12 11:14:10 2007 +0000

    Fix the remaining issues with GA-M57SLI Super I/O GPIO configuration.
    
    With this patch, flashing the parallel EEPROM on board revisions 1.x
    finally works. Flashing the serial EEPROM of board revisions 2.x is just
    one patch away.
    
    Torsten Duwe says:
    Flash erase on my board was failing reliably. Now it works!
    
    Andreas B. Mundt says:
    For the first time I was able to write with flashrom and LB.
    $flashrom -Vv --write linuxbios.rom
    [...]
    Vendor ID: GIGABYTE, part ID: m57sli
    Found chipset "NVIDIA MCP55", enabling flash write... OK.
    [...]
    SST49LF040B found at physical address 0xfff80000.
    Flash part is SST49LF040B (512 KB).
    LinuxBIOS last image size (not ROM size) is 4096 bytes.
    Manufacturer: GIGABYTE
    Mainboard ID: m57sli
    This firmware image matches this motherboard.
    Programming page: 0007 at address: 0x00070000
    Verifying flash... VERIFIED.
    
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Torsten Duwe <duwe@lst.de>
    Tested-by: Andreas B. Mundt <andi.mundt@web.de>
    Tested-by: Torsten Duwe <duwe@lst.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 18517e8a1fc9fdbf56a01a0122ec5e31e48fa2aa
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Nov 12 02:33:31 2007 +0000

    Try to fix a few loose ends on the GA-M57SLI Super I/O GPIO
    configuration.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Torsten Duwe <duwe@lst.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c716254e16fc1c7fe7bbf35e9110dd3b4495880e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 8 02:28:43 2007 +0000

    Fix up totally broken Super I/O config on the MS-6178. Add
    PIRQ table to make most devices work. Random small fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6503cd9d00a2a3cf3c1c32b26f2097fad7ac9c7f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Nov 7 23:13:43 2007 +0000

    Final set of changes to make Alix1c work.
    
    Fix IRQ tables (Thanks to Marc Jones)
    
    Fix IRQ SLOT #
    
    Comment out ram test in early startup.
    
    make the debug print in lx/raminit.c a debug print, not emerg print
    
    Set the default console log level to 3, but leave in the possibility of
    running with more info (leave maximum at 11)
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cce5040153689f9e4908f04c2bb61819984d221f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 7 22:09:02 2007 +0000

    Add initial support for all known ICH* southbridges to the
    i82801xx code for the following parts:
    
     - AC97 audio/modem
     - Onboard network interface cards (NICs)
     - USB 1.1 controllers
     - SMBus controllers
    
    Some other parts are still missing and will be added later.
    
    Use PCI ID #defines from pci_ids.h everywhere. Constify various structs.
    Also, fix some random cosmetic issues in the code.
    
    All of this is relatively trivial and tested by manually building
    all boards which currently use the i82801xx code.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9f1ae8ddb4011be41822d907bda4bc6db3c90bb
Author: Myles Watson <myles@pel.cs.byu.edu>
Date:   Wed Nov 7 19:07:17 2007 +0000

    Make the LZMA compression option work in buildrom.
    
    Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 908ff5ecac9065e4c903ae37c70e35d6aaf20108
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Wed Nov 7 19:02:35 2007 +0000

    This patch masks the function prototypes in stdlib.h from ROMCC, so that
    ARRAY_SIZE() can be used on ROMCC-dependent systems. Also adds stdlib.h
    to vt8237r_early_smbus.c, so it'll build on those systems.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9f8a67139e60cc0c36190b8801935698f3d00c8
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Wed Nov 7 18:55:06 2007 +0000

    This patch adds the pci ids of c7 cpus to the existing model_centaur. c3
    and c7 init are identical, according to the datasheets, so there's no
    need for another folder. As the comment says, some of these model IDs
    may never be produced, but they are reserved by Via for the c7.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b294582a0fb988767b02fc00087429e3b51b8de0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 7 00:19:42 2007 +0000

    Add PCI IDs for most Intel southbridges of the 82801 series
    (ICH/ICH0 up to the ICH9 family) in preparation for further
    code improvements for the i82801xx southbridge code.
    
    Small fixes in the 6300ESB PCI IDs.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c931625babcfacda301598f4eb0cea37d6e0e08c
Author: Torsten Duwe <duwe@lst.de>
Date:   Mon Nov 5 22:35:01 2007 +0000

    Fix the M57SLI routing table, as apparently set up from LinuxBIOS on
    that board. Shift PCIe pin numbers downwards, and PCI int pins upwards.
    This puts both PCI slots' int A and PCIe 16x int A into the right
    position.
    
    Signed-off-by: Torsten Duwe <duwe@lst.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a358892e2cd6f57c0645dc95120fd253d75e20b7
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Nov 5 22:21:27 2007 +0000

    * Change one PCI vendor ID from Nvidia to SiS
    * Remove dead code
    * Remove unused variables
    * Fix bug where array was one element too small
    * Fix error value truncation, the old code never entered the error path
    * Remove warnings
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39462d71565b44056418e0baf36aeb9ef631a75c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Nov 4 23:37:44 2007 +0000

    make agami aruma compile again.
    
    Rudolf's suggestion making the symbol weak is elegant, but let's allow
    some more discussion.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3ac07e447fd2dbe9074111f386950cdbeedc1e07
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Nov 4 19:03:42 2007 +0000

    another small abuild fix.. add payload compression "uses" for the a8v-e-se
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f6aa126e75f67191f737d558a5559d114cc1565
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sun Nov 4 17:29:01 2007 +0000

    Small fix to make abuild happy on the asus/a8v-e_se (trivial)
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2cb701499141cbafe6449394f718923a1458d4e9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Nov 4 16:50:27 2007 +0000

    Add dummy function for MCFG on those mainboards that provide ACPI but don't
    have PCIe MMCONFIG.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 25d712ac16a853d96b8ec03d64b20f596c013b2c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun Nov 4 16:25:05 2007 +0000

    merge changes to match agami's production environment
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7daa0bbaf707a96cc9e52cc6b310a484ac7800a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 4 04:04:01 2007 +0000

    Various cosmetics, coding style fixes, constifications (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a29ec0633ad1cd277c17bba87d5094b2f981e726
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 4 03:21:37 2007 +0000

    Restructure the PCI IDs list for the ICH* chipsets from ICH/ICH0 up to
    ICH5/ICH5R (more to follow) in preparation of further 82801xx improvements.
    
    Use human-readable names for the PCI ID #defines.
    Rename *_ISA to *_LPC as per datasheet.
    The 82801DBM only has 3 (not 4) USB devices, looks like a copy-paste error.
    
    The fixes in southbridge code are only to keep the build working for now,
    any real improvements will only go into the 82801xx code in future.
    
    This is abuild-tested so it shouldn't break anything.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 02b2365f02cd987b7d4306a82bccaad19494443d
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Sat Nov 3 18:45:42 2007 +0000

    This patch is some small changes to the vt8237r to prepare it for
    the Jetway J7F2 patch that should be coming soon, and also moves most
    defines into vt8237r.h. I've changed some of the values from u32 to u8,
    because that's all they should ever need to be. Also includes
    doxygenized comments!
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e6409f218c2278bfe3b64004478968f0b6207fdc
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sat Nov 3 12:50:26 2007 +0000

    This patch adds support for MCFG table, which allows OS to find the
    MMCONFIG for memory mapped PCIe config.
    
    However this patch is not enough to enable it on Linux, Linux do not trust
    BIOSes too much, so a small patch to kernel to disable the check if this
    region is e820 reserved.
    
    PCI: BIOS Bug: MCFG area at e0000000 is not E820-reserved
    PCI: Not using MMCONFIG.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2936 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec70af6470cc7eff3d416e00a0b9f34f143691fd
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Nov 2 23:27:12 2007 +0000

    This patch changes the "if else" style of parameter matching to table and also changes the rdpreamble parameter, which will cause that more then one DIMM will work for 939 motherboard.
    
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a0025675fadb73219e6bfa3301af69dcb5f0b8b
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Fri Nov 2 23:17:57 2007 +0000

    Asus A8V-E-SE support from Rudolf Marek
    
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b45bfabd2a11b0379ef9187bab7f48a24afbc8c9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 2 17:05:04 2007 +0000

    remaining part of the patch.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa2a670c57e1f9d19047230f1c1f6b254112de6b
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Fri Nov 2 16:18:25 2007 +0000

    Delete a file no longer used by the SiS implementation
    No functional code changes.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 218c26533dc5864dd33387e75476f7c8daf3570c
Author: Morgan Tsai <my_tsai@sis.com>
Date:   Fri Nov 2 16:09:58 2007 +0000

    1. vgabios removed, will go to extra repository
    
    2. Rename sisnb.c to sis761.c
    3. Delete many mis-definition for sis device in
       src/include/device/pci_ids.h
    4. Trim trailing spaces for all files
    
    Signed-off-by: Morgan Tsai <my_tsai@sis.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7162cf7278f1489cbe4b56a7fb95b713735387d9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 2 12:54:49 2007 +0000

    fix up iwill board compilation. Untested, trivial
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 894562f4eb81a83b360e3bd928a0517ae0122b4d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 2 12:35:30 2007 +0000

    fix up IBM servers.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc3f2f06416c75832d5ac828b918468de3b77ab8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 2 11:06:40 2007 +0000

    get arima hdama building again.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66e7d5e5f4b7d5c4f51882cf40cd4306edf495c3
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 2 10:36:15 2007 +0000

    fix juki 511p abuild by adding a Config-abuild.lb. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d8cd7602fb43a7520f396ed8f4fb352e4925022
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 2 09:48:14 2007 +0000

    This patch fixes the superio of the khepri 2100e as detected:
    > superiotool r2922
    > Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x0d) at 0x2e
    
    Don't use the non-working trident driver for the blade3d (onboard vga
    in the rom emulator has not been tested either)
    
    It also adds some preliminary CAR support to the board, so it has a chance to
    build again.
    
    This board was broken since a couple of months, and the changes are minimal, so
    I consider this a trivial change -- It doesn't change anything that was used,
    obviously
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c84a4600783662f2f69989a0005abc31a0c5b83
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 2 00:31:11 2007 +0000

    trivial fix for the .data problem
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9d5c3a8ea4536b470b644531814e019394c4563a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Nov 1 15:15:14 2007 +0000

    This patch is a trivial response to a good comment from Uwe, so I am
    self-acking before it gets lost.
    
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a0181ea03605b1fafe2ec9882384b91655dfe1c2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 31 22:26:51 2007 +0000

    Use the preferred order of 'static const' instead of 'const static'.
    This is the common style in both Linux as well as in LinuxBIOS.
    
    Self-ack as this is pretty trivial and a similar patch was already acked.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 246be7dd6dc732f1bf98f2ad63e2b7d9050aeafe
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 31 22:22:11 2007 +0000

    Use the preferred order of 'static const' instead of 'const static'.
    This is the common style in both Linux as well as in LinuxBIOS.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e7537f134d8484f3b8560e00a838bdacce4ea884
Author: Torsten Duwe <duwe@lst.de>
Date:   Wed Oct 31 00:49:38 2007 +0000

    As started in
    http://www.linuxbios.org/pipermail/linuxbios/2007-October/025385.html ,
    but change all apparantly related values that differ on my board with
    legacy BIOS.
    
    This makes both PCI cards appear, as well as the firewire device
    TSB43AB23.
    * PCI 01:07.0 appears fully functional
    * PCI 01:08.0 (closer to the board edge) appears, but no interrupts
    * PCI 01:0a.0 (FireWire) untested
    
    Since none of these was even present without the patch I suggest to
    apply it.
    
    Signed-off-by: Torsten Duwe <duwe@lst.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Tested-by: Harald Gutmann <harald.gutmann@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a8e2a0b852a3594a0031c62b7a57f9c442eafec4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 31 00:26:08 2007 +0000

    Add initial support for the Compaq Deskpro EN SFF P600.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d90afe6fddf31d6c3d7fafdcb01fb88e8482dcd
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 31 00:25:06 2007 +0000

    Add initial support for the Biostar M6TBA.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a910cbe3bfd62e8b55c55171e0da33113bb6ee7d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 31 00:23:57 2007 +0000

    Add initial support for the AZZA PT-6IBD.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84b2ae00251d84f7e0c272264b7a11296c94c552
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 31 00:22:32 2007 +0000

    Add initial support for the A-Trend ATC-6220.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7fe1ce14fb1f95ae074acc48775ce7edca6d5f22
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 31 00:07:31 2007 +0000

    Add initial support for the GIGABYTE GA-6BXC.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26f0abd6274e807a781bab9646065a6913864966
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 31 00:00:57 2007 +0000

    Add initial support for the ASUS P3B-F.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be0e24b578a39d4571f76c5f55f82451f725344e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 30 23:59:47 2007 +0000

    Add initial support for the ASUS P2B-F.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 113c2013bb185b2931630b869ec9e1cb985542dc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 30 23:57:59 2007 +0000

    Various smaller fixes to make the ASUS P2B match the format
    of all the other boards in this patch series.
    
    Add missing PIRQ table to make most devices work.
    Enable VGA support. Add flashrom flashing protection code.
    Make CPU init actually work (result: massive speed-up).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68d8a56cc56ab9805bee85c08f7211ef8455ca4d
Author: Joseph Smith <joe@smittys.pointclark.net>
Date:   Tue Oct 30 21:55:11 2007 +0000

    Various fixes and improvements of the 82801xx code.
    
    Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4590dae6aaed753ecac00351262936084807d48
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Tue Oct 30 17:53:53 2007 +0000

    [LINUXBIOS] Add the CPU_OPT flag to facilitate passing flags into the build
    
    buildROM passes build flags through the CPU_OPT environment variable -
    especially -fno-stack-protector for those of us lucky enough to have
    Debian/Ubuntu.  This adds  to the cache_as_ram_auto.inc target
    for the GA-2761GXDK so that the resulting cpu0.S is clean.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bbb2ff3cebd99df0d69f4e6f471d02ab99447f80
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 30 17:21:45 2007 +0000

    Small rename to make abuild happy (trivial).
    
    This is not yet enough to actually successfully build the board, but
    now abuild at least _attempts_ to build it.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94ec5eccd97ee7728fb0c7392adfb9ddd1747439
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 30 17:06:28 2007 +0000

    Drop empty directories (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7cc3bf319a2f3c517faa16137c51bc9eac5ccb00
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 30 15:58:59 2007 +0000

    Rename the SiS761GX/SiS966 board to the correct name, GIGABYTE GA-2761GXDK.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 418bc919d0e6e1b2b2688dd6f61fe6a378454017
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Oct 30 03:09:39 2007 +0000

    Add support for the VIA VT8237R southbridge.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: <corey.osgood@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af6e745173cc3b4eb7ec39fa05df59cdf513fb8e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Oct 30 02:24:49 2007 +0000

    move target directory to have the same name as the directory in the
    mainboard/ path. Also add a Config.lb for abuild. It's required for the
    three images variant as abuild doesnt detect this automatically.
    Trivial patch - it does not even fix the build yet. Patches welcome.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 83b52e719373f4f34bebbe47f81c7e3b4dc20a78
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Oct 30 02:17:49 2007 +0000

    fix the readwrite/readonly clashes for the pci_driver structs in the sis
    code. This is trivial, I did it for the other components before.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f32325ed8a186efdc379c1890036a511e30069e9
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Tue Oct 30 01:12:20 2007 +0000

    K8 resource dump utility from Rudolf Marek
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 825c809efe1cba676dcc6f795c26ddc24055b930
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 30 00:56:50 2007 +0000

    Add support for Intel 440MX systems.
    Add support for the Fujitsu MBM29F400TC flash part.
    
    Detection and reading works, writing is not tested.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1602dd5fddf3ada03508738218d760a7544ace50
Author: Morgan Tsai <my_tsai@sis.com>
Date:   Mon Oct 29 21:00:14 2007 +0000

    Thanks to the great efforts of Morgan Tsai of SiS we support the SiS966
    southbridge now:
    
    From: Morgan Tsai <my_tsai@sis.com>
    
    It supports SiS761GX / SiS966 chipset, only for AMD K8 platform so far.
    Due to integrated VGA sharing system memory, some code in southbridge
    folder have to init northbridge.
    
    Copyright (C) 2007 Morgan Tsai <my_tsai@sis.com>
    Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
    
    Change Log:
    
    Newly support GIGABYTE GA-2761GXDK
    CPU type: AMD AM2 socket
    Northbridge: SiS 761GX
    Southbridge: SiS 966
    SuperIO: ITE8716F
    
    Signed-off-by: Morgan Tsai <my_tsai@sis.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 55e6ebaf6a90102bfb09e467d768cf861a340e5f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 27 20:05:21 2007 +0000

    Move ARRAY_SIZE to stdlib.h to make it available to all code (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b80a8d4bc5b49c8921f57c3bf83f04c79817e46
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Oct 27 19:45:49 2007 +0000

    Drop duplicated and unneeded #defines from some northbridges (trivial).
    This is generic PCI stuff, not nothbridge-specific in any way.
    The respective #defines are already present in src/include/device/pci_def.h.
    
    Abuild-tested, so shouldn't break anything.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 65bc460e01c22cf0f347903735d0860756dc0777
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Oct 26 14:57:46 2007 +0000

    This code gets us to a working linux boot on the alix1c. I have not tested
    Ethernet yet. The fixes are a board-specific fake spd_read_byte, cleaning up
    comments, and just in general customizing for the 1c.
    
    The lxraminit
    change fixes a bug (&& used instead of ||), adds some debug prints which were
    VERY useful debugging the alix1c, changes fatal error messages from print_debug
    to print_emerg, and adds two functions:
    banner, which just prints out a string with a banner, and
    hcf, which print an emergency message and then pushes null bytes
    into the uart forever, just to make sure that no bytes get lost
    for any reason.
    
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d02e1e0d813eb4d986d26b5f4e98e5c12d46ea6
Author: Juergen Beisert <juergen@kreuzholzen.de>
Date:   Fri Oct 26 14:42:21 2007 +0000

    Add support for the AXUS TC320 thin client.
    
    This board uses nearly the same devices as the BCOM Winnet100, so most of
    the new code here is from the BCOM Winnet100. They differ in the IRQ routing
    table only.
    
    BTW: The AXUS board uses standard DIMM memory and can be run at 100MHz SDRAM
    clock speed (it runs reliably here since month).
    
    Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5384dac57e0568b39fa459f5d12dfa2d1199a948
Author: Peter Lemenkov <lemenkov@gmail.com>
Date:   Thu Oct 25 04:11:11 2007 +0000

    Added Am29LV040B
    
    Looking through the sources of Uniflash utility I found that this chip
    is no more no less than low-voltage variant of Am29F040B but with
    different ID.
    
    So I created a very quick patch (attached).
    
    Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb00e7ab94e93dd8e4c16a025df42d8de89da3e8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 24 20:17:04 2007 +0000

    Some fixes for the BCOM WinNET100, mostly in Config.lb:
    
     - Add missing entry for the NIC:
    
         device pci 0f.0 on end           # Ethernet (onboard)
    
     - Drop the following lines:
    
         register "com1" = "{115200}"
         register "com2" = "{38400}"
    
       Those entries hardcode the BAUD rate (as far as I can tell, please
       correct me if I'm wrong). We don't want that -- instead the config option
       TTYS0_BAUD in Options.lb should be used(?) I verified that dropping those
       lines will not break serial output (COM1, 115200, 8n1).
    
     - Enable IDE (PCI device 00:12.2) and add the following register lines
       to tell the CS5530 code to actually enable IDE channel 0:
    
          register "ide0_enable" = "1"
          register "ide1_enable" = "0"     # Not available/needed on this board
    
       Tested with a 2.5" hard drive and FILO, works fine.
    
     - Enable USB (PCI device 00:13.0), not sure why it was commented.
    
     - Enable COM2 as it's used by the smartcard reader.
    
     - Add CONFIG_COMPRESSED_PAYLOAD_LZMA to Options.lb, in order to fix
       abuild for this board.
    
     - Add some more comments.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bf873e4ae3e95e92c829cfec1d1efacbd25ba7ea
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 24 14:42:12 2007 +0000

    Another CONSTification...
    (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50542a884b13e47b28b97147def60617267ff8ff
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 24 11:14:14 2007 +0000

    This change removes all warnings from romcc in my build environment,
    making the output of "make -s" finally usable.. (still trivial, doesn't
    change any logic or remove any code)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a9e5821fdd289bbfc13733011948c2d5f83faa59
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 24 11:12:15 2007 +0000

    smaller changes to silence build warnings. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 124e4a45ca6d1b1765b70fdc14ce03c5df76b257
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 24 11:10:21 2007 +0000

    analog changes for the cpu_driver structures...
    make them const before putting them into the read-only segment...
    (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f1cf1f7c3aba660e4a174e966c4ef366d908565c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 24 09:08:58 2007 +0000

    Ever wondered where those "setting incorrect section attributes for
    rodata.pci_driver" warnings are coming from? We were packing those
    structures into a read-only segment, but forgot to mark them const.
    
    Despite its size, this is a fairly trivial patch created by a simple
    search/replace
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0dff6e3fa95ea13f6ee6cb2d4277e83076d81bad
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Oct 23 22:17:45 2007 +0000

    fix a whole bunch of warnings. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 643eee07541f10fcc3b34a56dc8bf2cf8d93c649
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Oct 23 19:23:52 2007 +0000

    drop unused variable (and thus warning). trivial patch.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b8383611541978804bc7660503a091bef358d5a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Oct 23 18:59:21 2007 +0000

    Add support for the Intel mFCPGA 478 socket. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 862ccfd84f469689922f1e23d98dbefd11f84b97
Author: Ward Vandewege <ward@gnu.org>
Date:   Tue Oct 23 12:06:53 2007 +0000

    The s2882 ships with a 1MB rom chip. The targets/tyan/s2882/Config.lb file
    assumes a 1MB rom chip.
    
    Hence the default position for the VGA bios should also assume a 1MB rom chip,
    not a 512KB chip.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 35823e97fc7b1438833f9527f48acec8e02fff0e
Author: Ward Vandewege <ward@gnu.org>
Date:   Mon Oct 22 20:56:13 2007 +0000

    Fix typo (trivial)
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e6d093ff006ef8b2238c6382bef1b9e7b3c5c697
Author: Ward Vandewege <ward@gnu.org>
Date:   Mon Oct 22 20:55:29 2007 +0000

    Add support for a precompressed LZMA payload (trivial).
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ef39274a3b94dcbdcd9ad15b96b5128d636c32e
Author: Peter Lemenkov <lemenkov@gmail.com>
Date:   Mon Oct 22 20:36:16 2007 +0000

    Flashrom: Add more Vendor IDs and ensure correct sorting in flash.h.
    
    Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d4fc0cff913f0ace9ce150d53713b70eb20cf8f
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Mon Oct 22 19:59:57 2007 +0000

    This patch adds support for K8T890CE northbridge.
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bed2f9c2fe1940a4eb83a22f1c84c8d87e836586
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Oct 22 17:04:39 2007 +0000

    Trivial: remove unused variable.
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4a0b911d189e4a06b5692bb7f16471398b67150
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Oct 22 16:15:28 2007 +0000

    Introduce block and sector erase routines to flashrom, but do not use
    them yet.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d56981f778a0f2de5d31af658c6589672126a32b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Oct 22 10:07:46 2007 +0000

    This is a hack for easier testing of GRUB2 in LinuxBIOSv2
    since it is still our most wide-spread codebase.
    
    The patch is pretty trivial, and nobody except Torsten even looked at
    it in a week, so....
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb56d216fcd798ac598d0bce6b40cdac11ffe6ce
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Oct 21 04:33:02 2007 +0000

    Put the print in the right place. This is trivial patch but a very
    serious issue, so I am self-acking.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd8632846b6b20a77bcf08d90a2b3f97efc22371
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Oct 21 03:51:06 2007 +0000

    I am signing off and acking this trivial patch, as I just wasted several
    days on a function named pll_reset that, on exit, says "Done
    cpuRegInit", and which, in turn, made me think it was a lot farther
    along that it was.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd7602314bd0a4fb96ddc0b055d503fa67a55303
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Oct 18 17:56:42 2007 +0000

    Remove hardcoded wait from SPI write/erase routines and check the chip
    status register instead.
    This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a
    MX25L4005 chip.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69a392b5c644518ace86d43d6dd76d52f0c634af
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 18 00:29:05 2007 +0000

    Documentation fixes and updates (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 79aa01a6c35bfa03ae8010b7044e878d38589e89
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Oct 18 00:24:07 2007 +0000

    Add generic SPI flash erase and write support to flashrom. The first
    chip the code was tested and verified with is the Macronix MX25L4005,
    but other chips should work as well.
    Timeouts are still hardcoded to data sheet maxima, but the status
    register checking code is already there.
    Thanks to Harald Gutmann for the initial code on which this is loosely
    based.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dcb9abdf4ce76910191c5b3abf56d03ad800e1f7
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 17 23:55:15 2007 +0000

    Some cosmetic cleanups in the flashrom code and output.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7dabe5ea0d8af4b60c07a075fa03d4c837d2e698
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 17 23:43:59 2007 +0000

    Drop support for the --human-readable option. It's not any more useful than
    the --dump option, it just means lots of additional work for no gain, IMO.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d937b5243cea29a1144a5e25f768ee06684445f8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 17 23:42:02 2007 +0000

    Print the version number always, not only in verbose mode.
    
    We often want to know the exact version number of superiotool which
    was used to gather a certain output/dump.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a90c14e9c4b61648e800bcea0a7c3a9f153c06b
Author: Idwer Vollering <idwer_v@hotmail.com>
Date:   Wed Oct 17 23:37:36 2007 +0000

    Add dump support for the Winbond W83697SF.
    
    Signed-off-by: Idwer Vollering <idwer_v@hotmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e447df1b25e8657b6033bedd37778fb441dc2081
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Oct 17 22:34:40 2007 +0000

    Add a debug message to keyboard init. This helped isolate at least one
    case of keyboard failure (the keyboard initialization was never hit).
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84453c02f7b5e8c7981370db98ab53f283885f8e
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Oct 17 22:30:07 2007 +0000

    Fix wrong values/typos in chipset_enable.c. This has been confirmed by
    Ed Swierk in
    http://www.mail-archive.com/linuxbios@linuxbios.org/msg09788.html .
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb0b3e77875de57d52abdbc8bd77caea24e88a5e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 17 01:57:14 2007 +0000

    Fix up totally broken Super I/O setup on the MSI MS-7260 (K9N Neo).
    
    This has not been working at all until now. With this fix, keyboard,
    mouse, parallel port, and the Super I/O sensors work fine (tested
    on actual hardware).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8dabccdbfd2c4dc6bdb164edf459ada0b5a084a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 16 23:36:34 2007 +0000

    Multiple flashrom fixes:
    
     - Install binary in /usr/sbin (not /usr/bin), as it's a root-only tool.
    
     - Rename manpage from flashrom.1 to flashrom.8, as section 8 contains
       "System administration commands (usually only for root)".
    
     - Actually install the manpage upon 'make install'.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 398b605ddb111038f6f92b0e51a5def9338ff993
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 16 21:56:32 2007 +0000

    Add detection support for the Winbond W83977AF as found in the
    Advantech PCM-5820 board (confirmed by Erwan Velu <erwan@seanodes.com>
    on IRC). Trivial (and tested) patch.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e62537a948685b143f9630d3f5069999ed7bec99
Author: Michael van der Kolff <mvanderkolff@gmail.com>
Date:   Tue Oct 16 21:18:43 2007 +0000

    Add Gigabyte M61P-S3 SPI flash support to board_enable.c
    
    Signed-off-by: Michael van der Kolff <mvanderkolff@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 259aaf00f586ae75fbf94e8e2eb0db77aa1095c9
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Oct 16 21:09:06 2007 +0000

    Convert the existing it8716f_* functions to generic_spi_* functions by
    applying abstraction and wrapping.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52bc99367c270b88f758f3a19634640ae0553f91
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Oct 16 18:21:22 2007 +0000

    Add resource size and resource granularity reporting to device_util.c.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc34cab5cbc99f30f9fecc97894230593107ee24
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 16 18:15:25 2007 +0000

    Fix the detection for the Winbond W83697SF. Unfortunately the revision
    has a slightly different format than that of the W83697UF/UG so we have
    to hack around it a bit.
    
    This patch has been verified to work on real hardware by
    Idwer Vollering <idwer_v@hotmail.com> on IRC (thanks!).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 92d3434f8720f362b27a99849c67d7b28b07227a
Author: Idwer Vollering <idwer_v@hotmail.com>
Date:   Tue Oct 16 00:34:03 2007 +0000

    Dump support for the Winbond W83977TF.
    
    Signed-off-by: Idwer Vollering <idwer_v@hotmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c1c1c0557f53ab8a13aef49721a72be784717be
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 16 00:13:59 2007 +0000

    Completely rip out / replace the ASUS P2B code (which wasn't really working),
    replacing it with a minimal, but working, framework which will be expanded.
    Drop a bunch of useless and duplicated files, add missing license headers.
    
    I'm self-acking it this time, the diff is a huge unreadable mess and the old
    code is broken anyway...
    
    This code is tested to build fine, and can boot a Linux kernel up to a
    login-prompt via FILO (IDE). This is verified on actual hardware.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 16f6171eda2159cd1063099f97aaf1fe63fcae88
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Oct 15 21:45:29 2007 +0000

    (forgot to add spi.c)
    
    Move SPI code out of board_enable.c where it started its life. The SPI
    chip finding and SPI chip accessor code is moved as well. This can be
    split later if we feel like it.
    
    The non-use of svn cp is intentional because the only history we'd have
    to preserve are a few commits which were early prototypes of chip
    identification code. For those who intend to look at that history, they
    can look at board_enable.c revision 2853.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a28edc524b7ab4a64d8c82dcb34b7932c5544b39
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Oct 15 21:44:47 2007 +0000

    Move SPI code out of board_enable.c where it started its life. The SPI
    chip finding and SPI chip accessor code is moved as well. This can be
    split later if we feel like it.
    
    The non-use of svn cp is intentional because the only history we'd have
    to preserve are a few commits which were early prototypes of chip
    identification code. For those who intend to look at that history, they
    can look at board_enable.c revision 2853.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3e03872f35888d99eca28b48e0d423bf8482f7f
Author: Joseph Smith <joe@smittys.pointclark.net>
Date:   Mon Oct 15 21:39:48 2007 +0000

    This patch adds support for the Mobile Intel Celeron CPU (Micro-FC-BGA)
    
    Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 72c0584d374d1bdfff4636f930c1ae52d9c89926
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 15 15:46:59 2007 +0000

    Fix stupid thinko in the Winbond detection code which prevented some
    of the Winbond chips from being detected (trivial fix).
    
    This is verified on real hardware and works fine now.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4910809cad1fdbe122208a1d73b7925aab242ec7
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 14 17:02:15 2007 +0000

    Add dump support for the NSC PC8374L (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2854 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 572268eaa77e999b321fb469b1e9ca6121641ae5
Author: Rudolf Marek <r.marek@assembler.cz>
Date:   Sun Oct 14 00:29:25 2007 +0000

    Fix the resource end in amdk8/northbridge.c.
    
    Without this bugfix, the resource for the PCI/ISA video memory at
    0xa0000 - 0xbffff is too big, i.e. it goes up to 0xcffff instead of
    just 0xbffff as it should.
    
    Here's the diff from two runs of the tool from
    http://www.linuxbios.org/pipermail/linuxbios/2007-June/022449.html
    on the MSI MS-7260 (K9N Neo), with and without the bugfix. After applying,
    the resource size is correct again.
    
    --- dumpres_lb_pci_vgacard_without_resfix.txt
    +++ dumpres_lb_pci_vgacard_with_resfix.txt
    @@ -11,7 +11,7 @@
     MMIO map: #2 0x0000000000 - 0x000000ffff Access: /     Dstnode:0 DstLink 0
     MMIO map: #3 0x0000000000 - 0x000000ffff Access: /     Dstnode:0 DstLink 0
     MMIO map: #4 0x0000000000 - 0x000000ffff Access: /     Dstnode:0 DstLink 0
    -MMIO map: #5 0x00000a0000 - 0x00000cffff Access: R/W     Dstnode:0 DstLink 0
    +MMIO map: #5 0x00000a0000 - 0x00000bffff Access: R/W     Dstnode:0 DstLink 0
     MMIO map: #6 0x00fc000000 - 0x00fd1fffff Access: R/W     Dstnode:0 DstLink 0
     MMIO map: #7 0x00fd200000 - 0x00fd1fffff Access: R/W     Dstnode:0 DstLink 0
     MMIO map: #0  0x000000 - 0x003fff Access: R/W  ISA VGA Dstnode:0 DstLink 0
    
    Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39a5bf74efd9c18b55d6c9354982807e3da37e97
Author: Ulf Jordan <jordan@chalmers.se>
Date:   Sat Oct 13 18:06:12 2007 +0000

    Set the superiotool version number from svn at build time.
    
    Signed-off-by: Ulf Jordan <jordan@chalmers.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45c1556df90b78cf6ac117ca75631a64747843a1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 13 17:06:21 2007 +0000

    Dump support for the SMSC LPC47N227.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c63643dc9053bdb0bc2a4774f72cfc2a1211565c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Oct 12 21:22:40 2007 +0000

    Changes to flashrom to support the K8N-NEO3, first tested at Google on GSOC day :-)
    
    Also minor changes to remove tab-space combinations where possible.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: David Hendricks <david.hendricks@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    Index: jedec.c
    ===================================================================
    --- jedec.c	(revision 2847)
    +++ jedec.c	(working copy)
    @@ -281,7 +281,7 @@
     	// dumb check if erase was successful.
     	for (i = 0; i < total_size; i++) {
     		if (bios[i] != (uint8_t) 0xff) {
    -			printf("ERASE FAILED\n");
    +			printf("ERASE FAILED @%d, val %02x\n", i, bios[i]);
     			return -1;
     		}
     	}
    Index: board_enable.c
    ===================================================================
    --- board_enable.c	(revision 2847)
    +++ board_enable.c	(working copy)
    @@ -153,7 +153,8 @@
     		return 1;
     	}
     	/* Start IO, 33MHz, readcnt input bytes, writecnt output bytes. Note:
    -	   We can't use writecnt directly, but have to use a strange encoding */
    +	 * We can't use writecnt directly, but have to use a strange encoding
    +	 */
     	outb((0x5 << 4) | ((readcnt & 0x3) << 2) | (writeenc), port);
     	do {
     		busy = inb(port) & 0x80;
    @@ -202,43 +203,39 @@
     /*
      * Helper functions for many Winbond Super I/Os of the W836xx range.
      */
    -#define W836_INDEX 0x2E
    -#define W836_DATA  0x2F
    -
     /* Enter extended functions */
    -static void w836xx_ext_enter(void)
    +static void w836xx_ext_enter(uint16_t port)
     {
    -	outb(0x87, W836_INDEX);
    -	outb(0x87, W836_INDEX);
    +	outb(0x87, port);
    +	outb(0x87, port);
     }
    
     /* Leave extended functions */
    -static void w836xx_ext_leave(void)
    +static void w836xx_ext_leave(uint16_t port)
     {
    -	outb(0xAA, W836_INDEX);
    +	outb(0xAA, port);
     }
    
     /* General functions for reading/writing Winbond Super I/Os. */
    -static unsigned char wbsio_read(unsigned char index)
    +static unsigned char wbsio_read(uint16_t index, uint8_t reg)
     {
    -	outb(index, W836_INDEX);
    -	return inb(W836_DATA);
    +	outb(reg, index);
    +	return inb(index+1);
     }
    
    -static void wbsio_write(unsigned char index, unsigned char data)
    +static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data)
     {
    -	outb(index, W836_INDEX);
    -	outb(data, W836_DATA);
    +	outb(reg, index);
    +	outb(data, index+1);
     }
    
    -static void wbsio_mask(unsigned char index, unsigned char data,
    -		       unsigned char mask)
    +static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask)
     {
    -	unsigned char tmp;
    +	uint8_t tmp;
    
    -	outb(index, W836_INDEX);
    -	tmp = inb(W836_DATA) & ~mask;
    -	outb(tmp | (data & mask), W836_DATA);
    +	outb(reg, index);
    +	tmp = inb(index+1) & ~mask;
    +	outb(tmp | (data & mask), index+1);
     }
    
     /**
    @@ -248,37 +245,80 @@
      *  - Agami Aruma
      *  - IWILL DK8-HTX
      */
    -static int w83627hf_gpio24_raise(const char *name)
    +static int w83627hf_gpio24_raise(uint16_t index, const char *name)
     {
    -	w836xx_ext_enter();
    +	w836xx_ext_enter(index);
    
     	/* Is this the w83627hf? */
    -	if (wbsio_read(0x20) != 0x52) {	/* SIO device ID register */
    +	if (wbsio_read(index, 0x20) != 0x52) {	/* Super I/O device ID register */
     		fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
    -			name, wbsio_read(0x20));
    -		w836xx_ext_leave();
    +			name, wbsio_read(index, 0x20));
    +		w836xx_ext_leave(index);
     		return -1;
     	}
    
     	/* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
    -	wbsio_mask(0x2B, 0x10, 0x10);
    +	wbsio_mask(index, 0x2B, 0x10, 0x10);
    
    -	wbsio_write(0x07, 0x08);	/* Select logical device 8: GPIO port 2 */
    +	wbsio_write(index, 0x07, 0x08);	/* Select logical device 8: GPIO port 2 */
    
    -	wbsio_mask(0x30, 0x01, 0x01);	/* Activate logical device. */
    +	wbsio_mask(index, 0x30, 0x01, 0x01);	/* Activate logical device. */
    
    -	wbsio_mask(0xF0, 0x00, 0x10);	/* GPIO24 -> output */
    +	wbsio_mask(index, 0xF0, 0x00, 0x10);	/* GPIO24 -> output */
    
    -	wbsio_mask(0xF2, 0x00, 0x10);	/* Clear GPIO24 inversion */
    +	wbsio_mask(index, 0xF2, 0x00, 0x10);	/* Clear GPIO24 inversion */
    
    -	wbsio_mask(0xF1, 0x10, 0x10);	/* Raise GPIO24 */
    +	wbsio_mask(index, 0xF1, 0x10, 0x10);	/* Raise GPIO24 */
    
    -	w836xx_ext_leave();
    +	w836xx_ext_leave(index);
    
     	return 0;
     }
    
    +static int w83627hf_gpio24_raise_2e(const char *name)
    +{
    +	return w83627hf_gpio24_raise(0x2d, name);
    +}
    +
     /**
    + * Winbond W83627THF: GPIO 4, bit 4
    + *
    + * Suited for:
    + *  - MSI K8N-NEO3
    + */
    +static int w83627thf_gpio4_4_raise(uint16_t index, const char *name)
    +{
    +	w836xx_ext_enter(index);
    +	/* Is this the w83627thf? */
    +	if (wbsio_read(index, 0x20) != 0x82) {	/* Super I/O device ID register */
    +		fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
    +			name, wbsio_read(index, 0x20));
    +		w836xx_ext_leave(index);
    +		return -1;
    +	}
    +
    +	/* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
    +
    +	wbsio_write(index, 0x07, 0x09);	/* Select logical device 9: GPIO port 4 */
    +
    +	wbsio_mask(index, 0x30, 0x02, 0x02);	/* Activate logical device. */
    +
    +	wbsio_mask(index, 0xF4, 0x00, 0x10);	/* GPIO4 bit 4 -> output */
    +
    +	wbsio_mask(index, 0xF6, 0x00, 0x10);	/* Clear GPIO4 bit 4 inversion */
    +
    +	wbsio_mask(index, 0xF5, 0x10, 0x10);	/* Raise GPIO4 bit 4 */
    +
    +	w836xx_ext_leave(index);
    +
    +	return 0;
    +}
    +
    +static int w83627thf_gpio4_4_raise_4e(const char *name)
    +{
    +	return w83627thf_gpio4_4_raise(0x4E, name);
    +}
    +/**
      * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
      *
      * We don't need to do this when using LinuxBIOS, GPIO15 is never lowered there.
    @@ -335,12 +375,12 @@
     	pci_write_byte(dev, 0x59, val);
    
     	/* Raise ROM MEMW# line on Winbond w83697 SuperIO */
    -	w836xx_ext_enter();
    +	w836xx_ext_enter(0x2E);
    
    -	if (!(wbsio_read(0x24) & 0x02))	/* flash rom enabled? */
    -		wbsio_mask(0x24, 0x08, 0x08);	/* enable MEMW# */
    +	if (!(wbsio_read(0x2E, 0x24) & 0x02))	/* flash rom enabled? */
    +		wbsio_mask(0x2E, 0x24, 0x08, 0x08);	/* enable MEMW# */
    
    -	w836xx_ext_leave();
    +	w836xx_ext_leave(0x2E);
    
     	return 0;
     }
    @@ -487,9 +527,11 @@
     	{0x10de, 0x0360, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
     	 "gigabyte", "m57sli", "GIGABYTE GA-M57SLI", it87xx_probe_serial_flash},
     	{0x1022, 0x7468, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
    -	 "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise},
    +	 "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e},
    +	{0x10de, 0x005e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
    +	 "msi", "k8n-neo3", "MSI K8N Neo3", w83627thf_gpio4_4_raise_4e},
     	{0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000,
    -	 "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise},
    +	 "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise_2e},
     	{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01,
     	 NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m},
     	{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118,
    @@ -509,8 +551,8 @@
      * Match boards on LinuxBIOS table gathered vendor and part name.
      * Require main PCI IDs to match too as extra safety.
      */
    -static struct board_pciid_enable *board_match_linuxbios_name(char *vendor,
    -							     char *part)
    +static struct board_pciid_enable *board_match_linuxbios_name(char *vendor,
    +								char *part)
     {
     	struct board_pciid_enable *board = board_pciid_enables;
    
    @@ -525,10 +567,11 @@
     			continue;
    
     		if (board->second_vendor &&
    -		    !pci_dev_find(board->second_vendor, board->second_device))
    +			!pci_dev_find(board->second_vendor, board->second_device))
     			continue;
     		return board;
     	}
    +	printf("NOT FOUND %s:%s\n", vendor, part);
     	return NULL;
     }
    
    @@ -545,20 +588,20 @@
     			continue;
    
     		if (!pci_card_find(board->first_vendor, board->first_device,
    -				   board->first_card_vendor,
    -				   board->first_card_device))
    +					board->first_card_vendor,
    +					board->first_card_device))
     			continue;
    
     		if (board->second_vendor) {
     			if (board->second_card_vendor) {
     				if (!pci_card_find(board->second_vendor,
    -						   board->second_device,
    -						   board->second_card_vendor,
    -						   board->second_card_device))
    +						board->second_device,
    +						board->second_card_vendor,
    +						board->second_card_device))
     					continue;
     			} else {
     				if (!pci_dev_find(board->second_vendor,
    -						  board->second_device))
    +							board->second_device))
     					continue;
     			}
     		}
    @@ -582,7 +625,7 @@
    
     	if (board) {
     		printf("Found board \"%s\": Enabling flash write... ",
    -		       board->name);
    +			board->name);
    
     		ret = board->enable(board->name);
     		if (ret)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6dbc0e12da2f1881910c50dfa8d5c2e8675b6414
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 11 18:30:05 2007 +0000

    Superiotool manpage/documentation improvements (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90216de46223da2abe8b511b8b7ea6253bbcb8fc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 11 10:25:35 2007 +0000

    Set the default video memory to 0 MB for all GX1 boards which don't yet
    use that feature in order to not waste RAM.
    
    Also, add missing CONFIG_VIDEO_MB for the eaglelion/5bcm, which should
    fix the build for that board.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f904a596d01c5ab7c03a36f839de66b1d4d95ce3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 10 17:42:20 2007 +0000

    Revert my last cleanup patch.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5982a0641ba37120cb90f8b28eb07d59b1743a0c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 10 16:31:30 2007 +0000

    Cosmetic changes to make the flashrom output more consistent (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae1ab3edecaa213ab941001acbf66c91b8cc4fc4
Author: Corey Osgood <corey.osgod@gmail.com>
Date:   Wed Oct 10 15:01:48 2007 +0000

    This patch adds the CONFIG_VIDEO_MB option to boards that
    currently don't have it but need it to compile with the new Geode GX1
    VGA support. This sets the size at 4MB, which was the size previously
    defined in the VGA code.
    
    Signed-off-by: Corey Osgood <corey.osgod@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96fb22d9b053f64919e51a5d7f702e0f8386aa1e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 9 23:58:35 2007 +0000

    Minor cosmetic changes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d744d906a7048a3e200fd0af2967aa3c5886879b
Author: Juergen Beisert <juergen@kreuzholzen.de>
Date:   Tue Oct 9 23:26:19 2007 +0000

    Add support for the BCOM WinNET100 (used in the IGEL-316 thin client).
    
    See http://www.linuxbios.org/BCOM_WINNET100_Build_Tutorial for hardware
    description and build tutorials.
    
    Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0446dbbd600d2a797e1cc0cf9f6791a95670d4ab
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 8 01:59:46 2007 +0000

    Fixup a register dump attached to the wrong Super I/O. Seems something
    went wrong in one of the recent commits.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14f304ace1fa238ad0b821e5e139c74d280d3188
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 8 01:11:11 2007 +0000

    Add detection support for lots more SMSC Super I/Os (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 557a9018edb3e335706d0cc0ad80be4b1c137e72
Author: Juergen Beisert <juergen127@kreuzholzen.de>
Date:   Sun Oct 7 22:46:51 2007 +0000

    Make the reserved video memory on Geode GX1 based systems configurable.
    This makes sense on systems with small memories when the VGA feature is
    not used (CONFIG_VIDEO_MB = 0 in this case).
    
    On Geode GX1 based systems the following amount of memory should be reserved
    when VGA support is enabled:
     - 1MiB for VGA and SVGA resolutions
     - 2MiB for XGA resolution
     - 4MiB for SXGA resolution
    
    Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a166bb1e0036a40412c0fe9367c40302c4186f35
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 7 22:25:49 2007 +0000

    Add missing '\n' to a printk_debug() and some other small fixes
    while I'm at it (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 44bb777062aaef6f5c680103711f0991c3a3f436
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 7 21:50:29 2007 +0000

    Some more ITE chips and small fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abeb63df5f94e0ecb00dd31abf259326c6243db1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 7 21:48:26 2007 +0000

    Detection support for a bunch of NSC Super I/Os (trivial).
    Also, dump support for the NSC PC87351.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 37f166982efed9613142522e5a475d5dcc3aaeab
Author: Juergen Beisert <juergen127@kreuzholzen.de>
Date:   Sun Oct 7 21:00:02 2007 +0000

    Fix some issues with spaces in the code and Doxygen style documentation.
    Painting the splash graphic is now ifdef'ed.
    
    Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e9d4616a9566e29e69d3c967d35126abddd99cee
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 7 20:01:23 2007 +0000

    Print a short message if no Super I/O chip could be detected (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84bf1e250617fbb213fd0ebb9574b11c46346ed0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 7 19:10:24 2007 +0000

    Add a list of contributors to the README (trivial). Also, a small hint
    about where to send additional register dumps.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c387b0b89e67f57d17c1f18ddb0ac6c2c06848d8
Author: David Hendricks <david.hendricks@gmail.com>
Date:   Sun Oct 7 19:04:26 2007 +0000

    Add dump support for the Winbond W83627THF/THG.
    
    Signed-off-by: David Hendricks <david.hendricks@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09203573c158ed3d46d7ee93beb33ec069475a73
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Oct 7 15:26:40 2007 +0000

    Add a manpage for superiotool (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a9c03f0defeebbe4dc0da4319b0ee6840f0090a
Author: Robinson P. Tryon <bishop.robinson@gmail.com>
Date:   Sun Oct 7 15:12:12 2007 +0000

    Dump support for the SMSC FDC37B72x.
    
    Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e1073f1a5483d37dbcf533c3e758d1fba978343e
Author: Robinson P. Tryon <bishop.robinson@gmail.com>
Date:   Sun Oct 7 15:04:17 2007 +0000

    Dump support for the SMSC FDC37B78x.
    
    Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87c499967260335456bc1e290af51a6d9c5db144
Author: Robinson P. Tryon <bishop.robinson@gmail.com>
Date:   Sun Oct 7 14:33:13 2007 +0000

    Dump support for the SMSC FDC37M81x.
    
    Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 409b4f2273293d96755d046dbe86ccbfe2d1e673
Author: Rasmus Wiman <rasmus@wiman.org>
Date:   Fri Oct 5 21:58:03 2007 +0000

    Add dump support for the Winbond W83627HF/F/HG/G.
    
    Signed-off-by: Rasmus Wiman <rasmus@wiman.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4ac32176d146bee42f7a0de880ea01ae45de9663
Author: Juergen Beisert <juergen127@kreuzholzen.de>
Date:   Fri Oct 5 21:00:10 2007 +0000

    This patch will add support for the Geode GX1/CS5530 VGA feature. It's able
    to set up one of five screen resolutions (sorry no autodetection at runtime,
    resolution is selected at buildtime) and displays a graphic in the right
    bottom corner (splash screen).
    
    Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23740c82e2bd45b2755376b58f331ba57c474d72
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 5 15:11:38 2007 +0000

    Add dump support for the SMSC LPC47M10x (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc81769c9c91d57b21b070f24930efc5c5b46f44
Author: Robinson P. Tryon <bishop.robinson@gmail.com>
Date:   Fri Oct 5 13:47:04 2007 +0000

    Add dump support for the ITE IT8661F. Note that this chip will not yet
    be detected, as it needs a non-standard init sequence.
    
    Minor other fix: Drop incorrect 0x2b from LDN 5 of the ITE IT8705F.
    
    Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5debf36d9d988a063c6d1ed98326c0d5e5520008
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 4 18:34:36 2007 +0000

    Add some more Winbond chips (trivial).
    
    Add notes which IDs were taken from sensors-detect (as where we lack
    datasheets, thus cannot verify them) and which we support but sensors-detect
    does not (yet). I'll post patches on the lm-sensors list to sync up
    the detected chips between superiotool and sensors-detect.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit db5f953754ee3ea1acd023070ea555adbd1bb94f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 4 16:28:56 2007 +0000

    Add detection support for the LPC47B387 (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4354103078a7ba35c7b696ad7621f1c1ceaf1d91
Author: Robinson P. Tryon <bishop.robinson@gmail.com>
Date:   Thu Oct 4 15:44:19 2007 +0000

    Add dump support for the ITE IT8705F/AF.
    
    Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b8d03974e11edbdbbd61c6b22d8013dca87be71
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Oct 4 15:23:38 2007 +0000

     * Convert the NSC code to the common code structure all other Super I/Os use.
    
     * Improve the --verbose output a bit more. Print the "Probing..." text for
       all Super I/Os and if a Super I/O is not known, show the data we were
       able to read from the chip (what data this is is very vendor/chip specific).
    
     * Thus the common no_superio_found() is dropped, it's not useful.
       The "read from 0x20" part was wrong for all Super I/Os other than the
       NSC ones anyway.
    
     * Winbond: For the 'olddevid' only use bits 3..0, mask away the others.
    
     * SMSC: Print which ID registers we try to read (in --verbose mode).
    
     * Minor cosmetic fixes.
       * Rename PC8374 to PC8374L (as per datasheet).
       * Rename probe_idregs_simple() to probe_idregs_nsc().
       * Rename dump_readable_ns8374() to dump_readable_pc8374l().
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 573ff508ab3d61ede76cd3b68aaaf7f2bdcfa34a
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu Oct 4 06:26:41 2007 +0000

    [FLASHROM] Fix the help, and print a message when nothing happens
    
    The help implied that writes happen by default, which they don't.  Fix
    the text, and say something when we dont specify any commands.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 209148c535dd61df9e96209a063f315912ca9685
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Oct 3 18:56:51 2007 +0000

    Add a copy of the GPL (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec1edd1cd94f02b6359dea4d6e74205b3aa91e24
Author: Robinson P. Tryon <bishop.robinson@gmail.com>
Date:   Tue Oct 2 23:32:21 2007 +0000

    Print superiotool version when run with --verbose.
    
    Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0de6f0a36f98b3e76a80451fbe6f98c97fdf60b1
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Oct 2 15:49:25 2007 +0000

    This patch aims to restructure SPI flash support in a more reasonable
    way. It introduces a generic SPI host driver for the IT8716F Super I/O
    which will enable easy SPI programming without having to care for the
    peculiarities of the SPI host.
    
    To activate probing for the IT8716F, you have to use the gigabyte:m57sli
    mainboard override. SPI support will then use the gathered SPI host data
    to access the SPI flash.
    
    This has been tested sucessfully by Ward Vandewege <ward@gnu.org> on the
    GA-M57SLI v2.0, which has a MX25L4005 SPI flash part.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3617103cc78c460d98b9d8a6c282ffa227ce3f23
Author: Joseph Smith <joe@smittys.pointclark.net>
Date:   Mon Oct 1 18:32:00 2007 +0000

    Thee lines in i82801xx_pci.c need to be removed. They cause the
    i82801DB to reset. See this thread for more info:
    
    http://article.gmane.org/gmane.linux.bios/26791
    
    Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
    
    
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e4d4ebabbda3eb64a41094cd121e3fdb36f032c8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Oct 1 13:39:02 2007 +0000

    De-uglify the --version output (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit afe83092020d37d1b8629b3b92f9179e925e72fe
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 28 15:45:43 2007 +0000

    Random minor fixes. Use svn revision as superiotool version number.
    Make the -V output more informative.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 945045b1ea380f8224bee426cb91b897562df1c8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 28 15:39:10 2007 +0000

    Add support for some more Fintek chips and an ALi chip.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f45fc234fd37d88d387a192ba748e116f5b9d16
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 28 15:02:17 2007 +0000

    Fix up the SMSC detection code to probe _both_ old- and new-style
    Super I/Os from SMSC. Otherwise not all of them are detected (and there
    could theoretically be _two_ of them in a system, so we should probe
    for both types anyway).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7fe8f5da4d127bb4538e95cab14cd9ee07d33690
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Thu Sep 27 14:29:57 2007 +0000

    Add preliminary SPI flash identification support for SPI chips attached
    to ITE IT8716F Super I/O. Right now this is hardcoded to the Gigabyte
    M57SLI board. It works only with rev 2.0 of the board, but it will bail
    out on earlier versions, so no damage can occur.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03f23221750754de1975764a19efece231185866
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Sep 26 16:41:15 2007 +0000

    Don't arbitrarily enable PERR# and SERR# for PCI devices.
    It is platform specific.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3da36681de646b7581a87d3e461f973797db92d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 26 16:14:16 2007 +0000

    Add detection support for lots more Winbond Super I/Os (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e0ffaa164d2090d5adb39f837d18170c985d607a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 26 15:48:09 2007 +0000

    Dump support for the Fintek F71805 (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f845e02edbb1052eb9d2c5a4a6fb85f4e7c1b975
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Sep 25 01:31:35 2007 +0000

    As per suggestion from Yinghai Lu <yinghailu@gmail.com> this patch
    fixes the problems with PCI add-on cards not being detected or
    initialized on MCP55-based systems (PCI bridge decoding change).
    
    I have tested this on the MSI MS-7260 (K9N Neo) with a PCI VGA card,
    which worked fine in any of the three PCI slots.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48cac24742300f8225b3194bc8d4f3f119f633e5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Sep 24 23:24:46 2007 +0000

    Detection support for the Winbond W83627HF (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ee78d8b064ca41f97bf28b0a6c1af0cf8d2363a
Author: Ward Vandewege <ward@gnu.org>
Date:   Mon Sep 24 22:02:31 2007 +0000

    Fix compilation warning.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 322076cdade5e405cb7102f744f714cd69416ec0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Sep 24 20:00:32 2007 +0000

    Various cosmetic changes and coding style fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f86732a5ed178614ab89cf19905d283877d3a4f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Sep 24 01:40:09 2007 +0000

    Add detection support for quite a number of SMSC Super I/Os. Also, add
    dump support for the SMSC DME1737 and the ASUS A8000. Random minor fixes.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6b4ad4304a57fdcfd6147370235896406f229e61
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Sep 23 13:17:29 2007 +0000

    Minor fixes/improvements in the Fintek code (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a9740db2eef45ed006a700632b7800ff5fc1d2b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 22 20:13:27 2007 +0000

    Fix another, similar typo as in r2800 (trivial).
    Reported by Robert Millan.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa8e9bd6d33a47ebe0baab45b611af366b892a1a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 22 19:51:48 2007 +0000

    Fix typo which causes build error if CK804_USE_NIC is set (trivial).
    This is tested with abuild so shouldn't break anything.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c49b834710a715e7068740b7d83509cc3f63109e
Author: Morgan Tsai <my_tsai@sis.com>
Date:   Sat Sep 22 17:51:48 2007 +0000

    Add SiS device IDs for further update.
    
    Signed-off-by: Morgan Tsai <my_tsai@sis.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9ab798a2f7ac7ea3bc689e2a194bab7f0a99163
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 21 23:13:28 2007 +0000

    Fix abuild for the MSI MS-7260 (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 970d06b10d4f580b38cb7a95759ee8bf41b623c9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 21 15:56:05 2007 +0000

    Add support for the MSI MS-7260 (K9N Neo) mainboard.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 420f6abc11fa7147d1d4785751a9248dfc607c73
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 21 14:48:04 2007 +0000

    Add register dump capability for ITE IT8718F (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eddc473ce0753bfd8aa55cc19bcec991866694fd
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 20 23:57:44 2007 +0000

    Add -D / --dump-readable option which prints the Super I/O register
    contents in human-readable form (e.g. "COM1 enabled" etc.) instead
    of the hex-table format from -d / --dump.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b4db2209f9e01e1a013cc33356bceec57c3a3c80
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 20 23:37:56 2007 +0000

    Decouple the ITE code from fintek.c, it doesn't belong there.
    Add common 'enter configuration mode' function for most Winbond/Fintek/ITE
    chips which use the 0x87 0x87 sequence for that reason.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0702469f163e69257a7cf079eb40ae99f53c815b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 20 22:13:48 2007 +0000

    Fix up and generalize the ITE IT8708F code. It was only working out of
    pure luck (and broken code elsewhere). Needs some more fixing.
    
    Add more LDN descriptions to various Super I/Os.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42670a75ef557db9b93e7dc5dc1d9e1cef246ff5
Author: Ward Vandewege <ward@gnu.org>
Date:   Thu Sep 20 15:01:14 2007 +0000

    The s2891 ships with a 1MB rom chip. The targets/tyan/s2891/Config.lb file assumes a 1MB rom chip.
    
    Hence the default position for the VGA bios should also assume a 1MB rom chip, instead of a 512KB chip.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c290e3362337feffd2086994f5f720d9332d38e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 20 00:00:49 2007 +0000

    Superiotool: Add dump support to the Winbond W83697HF/F.
    Minor coding style changes and code simplifications.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e47495659080e136a405483a6cb4413dbcb09925
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 19 16:26:18 2007 +0000

    Implement usage for --help and put the same information into the README, too.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e7e9ac6078efb61ce7b531b084a410cb73e1b92
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 19 15:52:23 2007 +0000

    Add support for the Winbond W83697HF/F and W83627EHF/EF/EHG/EG.
    Various minor fixes and improvements (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3acf31e4eaa0f143cd8af10f5ce99523ddc53a03
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 19 01:55:35 2007 +0000

    Further code simplifications and improvements.
    
    Add command line option handling code. The following options
    are defined at the moment:
    
    -d|--dump      Dump Super I/O registers.
    -V|--verbose   Verbose mode.
    -v|--version   Show the superiotool version.
    -h|--help      Show a short help text.
    
    Per default (no options) we just probe for a Super I/O
    and print its vendor, name, ID, version, and config port.
    
    Example:
    
    $ ./superiotool
    Found SMSC FDC37N769 Super I/O (id=0x28, rev=0x01) at port=0x03f0
    
    $ ./superiotool -d
    Found SMSC FDC37N769 Super I/O (id=0x28, rev=0x01) at port=0x03f0
    idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
    val 20 90 80 f4 00 00 ff 00 00 00 40 00 0e 28 01 00 00 00 00 00 02 00 01 03 00 00 00 00 00 00 80 00 00 00 00 00 00 ba 00 00 03 00 00 23 03 03 00 00
    def 28 9c 88 70 00 00 ff 00 00 00 00 00 02 28 NA 00 00 80 RR RR NA NA NA 03 RR RR RR RR RR RR 80 00 3c RR RR 00 00 00 00 00 00 00 RR 00 00 03 00 00
    
    $ ./superiotool -s
    ./superiotool: invalid option -- s
    
    $ ./superiotool -h
    Usage: superiotool [-d] [-V] [-v] [-h]
    
    $ ./superiotool -v
    superiotool 0.1
    
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3ef9b740dea1044713b667829cb9c4e2a48785b0
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed Sep 19 00:57:37 2007 +0000

    Add support for a precompressed LZMA payload (trivial).
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 786b0c4ed603742c9ff74d90c594feb8c62565ef
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed Sep 19 00:52:14 2007 +0000

    Sorry, I mixed up two patches. Reverting this change.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 25a6c0f18ce8f2db4483fa8e65a5f5aa5042d958
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 19 00:48:42 2007 +0000

    Split out enter_conf_mode_*()/exit_conf_mode_() functions, we'll soon need
    them. Reduce code duplication a bit by improved 'no dump available' handling.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c73ea4d4fc86a0e3a3c42bec45942e0354dae171
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed Sep 19 00:43:02 2007 +0000

    Add support for a precompressed LZMA payload (trivial).
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit de24a0e58557ac7913e2f8174710f50e4697b1bd
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 19 00:03:14 2007 +0000

    Use uint16_t and friends where appropriate (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d754d2c6c4970e686d004ea4d39c5e6599abf46f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Sep 18 23:30:24 2007 +0000

    Make the code a bit more generic (trivial). Different Super I/Os
    use different config ports.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ff6af762158147b3c47bd1701a389622bd043a5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Sep 18 22:24:34 2007 +0000

    Superiotool: Add support for the SMSC FDC37N769.
    
    Here's what a register dump looks like on my test system:
    
    No Super I/O chip found at 0x002e
    No Super I/O chip found at 0x004e
    No Super I/O chip found at 0x002e
    No Super I/O chip found at 0x004e
    No Super I/O chip found at 0x002e
    No Super I/O chip found at 0x004e
    Super I/O found at 0x03f0: id=0x28, rev=0x01
    SMSC FDC37N769
    idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
    val 20 90 80 f4 00 00 ff 00 00 00 40 00 0e 28 01 00 00 00 00 00 02 00 01 03 00 00 00 00 00 00 80 00 00 00 00 00 00 ba 00 00 03 00 00 23 03 03 00 00
    def 28 9c 88 70 00 00 ff 00 00 00 00 00 02 28 NA 00 00 80 RR RR NA NA NA 03 RR RR RR RR RR RR 80 00 3c RR RR 00 00 00 00 00 00 00 RR 00 00 03 00 00
    Probing 0x0370, failed (0xff), data returns 0xff
    
    I'm self-acking this as it's pretty simple stuff, but please let me
    know if anything could be improved here, or if you think this
    is not trivial enough to warrant self-acking.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8a18a2adbe62aa0928515de1850f8e1722f69b9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Sep 18 00:01:27 2007 +0000

    Add a README for superiotool (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 519419b476a5e5eaa364151ca33da8055a6f7f80
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Sep 16 20:59:01 2007 +0000

    Split out a dump_superio() function from ite.c, and make it slightly more
    generic, so that we can use it for other Super I/Os, too.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4cb7e717327add9165e30cca537225044bdc0fdd
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Sep 16 18:17:44 2007 +0000

    Make 'struct superio_registers' globally available, pretty much
    all Super I/Os can (and should!) use this (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0120e1a3d8ebb450aed5016b4653ce4a7524295e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Sep 16 18:11:03 2007 +0000

    Split up superiotool.c into multiple source files, one per vendor.
    
    As there will be lots more supported Super I/Os soon, the file is
    really getting way too big...
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 18c70d7222bcea65d08e1ff879d8f69f2705e7ab
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Fri Sep 14 14:58:33 2007 +0000

    More range for HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE.
    
    For example: in C51/MCP55 or C51/MCP51
    
    Will allow
    1. C51 at 0x10 to 0x14, and MCP at 0 to 4
    2. C51 at 1 to 4, and MCP at 7 to 0x0a
    
    The reason is c51/mcp51/mcp55 reported unitid is 0x0f (far beyond it
    needed), and will prevent us from putting them on bus 0.
    
    Typical values for c51/mcp55 or c51/mcp51:
    HT_CHAIN_UNITID_BASE = 0x10 # for C51
    HT_CHAIN_END_UNITID_BASE = 0 # for mcp
    
    If only have mcp with c51,
    HT_CHAIN_UNITID_BASE = 0 # for MCP
    #HT_CHAIN_END_UNITID_BASE = 0 # default value 0x20
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3335adb771c5e6bf2fb200285a8af7134446bb71
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Sep 14 00:09:29 2007 +0000

    This is a full rewrite of all the CS5530/CS5530A code. The previous code was
    mostly undocumented, had a broken coding style, contained lots of dead
    code and had several other problems, e.g. it enabled write access to the
    ROM (why?), it unconditionally enabled primary/secondary IDE (which should
    have a config option) and that even _twice_ (which is um... wrong).
    
    The new code
    
     - has 'ide0_enable' and 'ide1_enable' config options (which actually
       work) to enable/disable the primary/secondary IDE interface in
       Config.lb.
    
     - Does _not_ enable write access to the ROM (or is there some good
       reason to do that? If so, it should at least have a config option).
    
     - Contains a bit more documentation.
    
     - Uses readable (and documented) #defines instead of hardcoded magic values.
    
     - aaand... it actually compiles ;-) Yep, that's right. The previous code
       wouldn't even build, as it hadn't been fully ported from v1 (still used
       v1 functions which are simply not available in v2).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 741e1e658f060435cfd5505f96cab55045a889d5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Sep 13 13:47:02 2007 +0000

    I still don't understand a word, but I tried to improve the documentation. (trivial)
    Please fix this if you can.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dde1d709a4c2fe116d26fd9ca41205f615eb6865
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 13 09:55:44 2007 +0000

    Fix abuild run of the MSI MS-6178 (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a9838cf7961746801a6d50cf524a62575fe3c092
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Sep 13 08:38:24 2007 +0000

    Add a common/global failover.c file which can be used by all
    (or at least most) mainboards. This should put and end to
    copy-paste'ing the same file again and again for every mainboard.
    
    Fix the build for the MSI MS-6178 target (wrong location of the common
    failover.c file).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 41b88342b9df6934493c01a825071c32b3bd30f0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Sep 12 22:11:33 2007 +0000

    Add initial support for the Intel 810 based board MSI MS-6178.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7798c888e80772a0a46172da581d039fcb7cd844
Author: Alex Beregszaszi <alex@rtfs.hu>
Date:   Tue Sep 11 15:58:18 2007 +0000

    Change out/in combinations to pci_read/write_byte in
    sis630 chipset enable.
    
    Signed-off-by: Alex Beregszaszi <alex@rtfs.hu>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9b0f7fd910ff7ac48b53262328e63c110910549
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Sep 9 20:24:29 2007 +0000

    Remove useless 'extern' keywords (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 863c1bf525f7fa52ee1f7bc17e2eb95097bd194b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Sep 9 20:21:05 2007 +0000

    Add '(C)' where it's missing (for consistency reasons).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09735cb5175686a54d4b503091408d6440128c9b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Sep 9 20:02:45 2007 +0000

    Add missing license header to udelay.c.
    
    I'm self-ack'ing this, as the origin of the code in udelay.c (and thus
    the license and copyright owner) is pretty clear.
    
    The code which is now in udelay.c was split out from flash_rom.c in r1428,
    and flash_rom.c, in turn, has been around since the beginning and had a
    'Copyright 2000 Silicon Integrated System Corporation' line as well as the
    usual GPLv2-or-later license header.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cbc95f32fb1f3208dbf7cbe08ed1f19f96c28fe6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Sep 9 19:43:31 2007 +0000

    Partial changes and fixup.
    Removed reset.c and added copyright headers.
    Remove debug.c. It is not used and should not be here.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6226f13c11ce9b8daa0d18d5c3996b984cdbd6f0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Sep 8 18:32:53 2007 +0000

    Welcome to PC Engines and the ALIX 1C!
    
    This is a geode LX board. There are timing settings that are not right
    yet, we are still trying to get our board to boot Linux :-)
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9398958cfa76635b7108d5fb2b51073b793ac2b5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 8 14:36:01 2007 +0000

    Add a copy of the GPL in the flashrom repository as it's an independent
    project (being packaged by distros, among other things).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98ef9cefc84e241b1892695446fe8de089ecefbb
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 1 21:20:29 2007 +0000

    Small consistency fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2046ff92f022dfdc76032196663f815b54ac47ed
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 1 21:02:44 2007 +0000

    Various coding style and whitespace fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4c54a5df3553d1e7af99e592f90eec714b6f8cd
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Sat Sep 1 20:24:30 2007 +0000

    Add ITE IT8716F support to probe_superio. This helps especially
    GA-M57SLI board owners who wish to debug remaining problems or handle
    SPI flash of newer board versions.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1ae8e83baa338ac12b8925d8225f2d8e662c4425
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 1 20:20:41 2007 +0000

    Rename probe_superio.c to superiotool.c.
    Flesh out Makefile with all the usual stuff, e.g. install targets etc.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c14e45bfd20caf9623693340beb91184d851e08
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 1 19:44:36 2007 +0000

    Move probe_superio into the global util/ directory.
    Rename it to superiotool while we're at it.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd26392f42e508bf67503b0d44577528a3998bc0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Sep 1 19:42:42 2007 +0000

    Add support for the ITE IT8708F.
    
    Here's a dump from my test system which has an IT8708F:
    
    No SuperI/O chip found at 0x002e
    probing 0x002e, failed (0x87), data returns 0x87
    SuperI/O found at 0x2e: id=0x8708, chipver=0x0
    ITE IT8708
    idx 07 20 21 22 23 24 25 26 27 28 29 2a 2e 2f
    val 02 87 08 00 00 00 00 00 03 01 01 00 00 00
    def NA 87 08 00 00 NA 3f 00 ff ff ff ff 00 00
    switching to LDN 0x0
    idx 30 60 61 70 74 f0 f1
    val 01 03 f0 06 02 00 80
    def 00 03 f0 06 02 00 00
    switching to LDN 0x1
    idx 30 60 61 70 f0
    val 01 03 f8 04 00
    def 00 03 f8 04 00
    switching to LDN 0x2
    idx 30 60 61 70 f0 f1 f2 f3
    val 01 02 f8 03 00 50 01 7f
    def 00 02 f8 03 00 50 00 7f
    switching to LDN 0x3
    idx 30 60 61 62 63 64 65 70 74 f0
    val 01 03 78 07 78 00 80 07 03 0b
    def 00 03 78 07 78 00 80 07 03 03
    switching to LDN 0x4
    idx e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6
    val 80 61 00 00 00 00 00 00 80 00 30 00 80 00 de
    def NA NA 00 00 00 00 00 00 00 00 00 00 00 NA NA
    switching to LDN 0x5
    idx 30 60 61 62 63 70 71 f0
    val 01 00 60 00 64 01 02 0c
    def 01 00 60 00 64 01 02 00
    switching to LDN 0x6
    idx 30 70 71 f0
    val 01 0c 02 00
    def 00 0c 02 00
    switching to LDN 0x7
    idx 70 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c5 c8 c9 ca cb cc cd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc
    val 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 01 01 00 00 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 7f 20 51 00 0e 00 00 00 00 00 00 00
    def 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA NA NA NA NA NA 00 00 00 00 00 00 00 00 00 00 00 NA 00
    switching to LDN 0x8
    idx 30 60 61
    val 00 02 01
    def 00 02 01
    switching to LDN 0x9
    idx 30 60 61 70 f0
    val 00 03 10 0b 06
    def 00 03 10 0b 00
    switching to LDN 0xa
    idx 30 60 61 70 f0
    val 00 03 00 0a 40
    def 00 03 00 0a 00
    No SuperI/O chip found at 0x004e
    No SuperIO chip found at 0x004e
    No SuperIO chip found at 0x004e
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a5a264748d8cea46040646222da904d5930e002
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Aug 31 20:51:00 2007 +0000

    Fix typo for the ITE IT8712F (trivial).
    
    The default for LDN 5 (keyboard), index 0xF0 is not 0x00
    but rather 0x08 as per datasheet.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 210901029090b41d829cc56203c28d93a8ffb189
Author: Torsten Duwe <duwe@lst.de>
Date:   Thu Aug 30 10:29:15 2007 +0000

    Add support for the Athlon64 x2 5000+ CPU.
    
    A trivial one-liner for the CPU I happen to have. The sales docs said it's
    a "G1 revision", but the Rev F code works just fine.
    
    Signed-off-by: Torsten Duwe <duwe@lst.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 736c1d8618e450b96c99c9ca8020134f65b581c8
Author: Markus Boas <ryven@ryven.de>
Date:   Thu Aug 30 10:17:50 2007 +0000

    Add support for the Winbond W29EE011.
    
    Signed-off-by: Markus Boas <ryven@ryven.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b78de6887bc7c3ba0210365e42af071202000a4
Author: Markus Boas <ryven@ryven.de>
Date:   Thu Aug 30 10:11:08 2007 +0000

    Add support for the Winbond W29C040P.
    
    Signed-off-by: Markus Boas <ryven@ryven.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c71f7378606cf8777ac0e01abce6e6ad5e48cd2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Aug 29 17:52:32 2007 +0000

    Change all flashrom license headers to use our standard format.
    No changes in content of the files.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b1786c2bce93da3d480fdd9bed1b40e67876203d
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Aug 28 10:43:57 2007 +0000

    This patch makes ITE Super I/O probing/dumping a little bit more generic,
    fixes minor coding style issues and prepares the table for supporting
    more chips of the ITE IT87xx Super I/O family.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a7890acedc79dc14bfd37b4ba90a0f430cf84c3
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Mon Aug 27 07:28:28 2007 +0000

    This patch rewrites probe_superio almost completely.
    Common code sequences have been factored out, the code has been made
    more generic, has better handling of corner cases and is actually much
    shorter.
    
    It also adds probing for almost all recent (since 1999) ITE Super I/O
    chips to probe_superio. I did verify against all ITE datasheets
    (including those not available any more) that the probing was
    non-destructive.
    
    For the ITE IT8712F, the complete configuration is dumped and as
    comparison the default value from the data sheet is printed.
    More information can be extracted easily, however this needs loads of
    datasheet surfing.
    
    This code has been tested extensively, dumping for other ITE chips will
    follow as a separate patch.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba9ce9f7f986ba2a3f4d88b7cb53e0704b7d2708
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Aug 23 16:08:21 2007 +0000

    Cosmetic fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0a6bb9106263eead0dd35d68be90ab52223488d5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Aug 23 15:20:38 2007 +0000

    Drop duplicated code (copies of plain JEDEC functions).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2fe239134cf3f8b74267d1472c03a99d9ab13bcc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Aug 23 13:34:59 2007 +0000

    Drop a bunch of useless header files, merge them into flash.h.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a9bbc2cc8bc20fc64d40dc8dd67814ab66e77f5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Aug 23 10:20:40 2007 +0000

    Move code into *.c files, there's no reason to have it in header files.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3436698b6a91a921d7091d141b01c396bdc25dc1
Author: Ed Swierk <eswierk@arastra.com>
Date:   Mon Aug 13 04:10:32 2007 +0000

    Fix bug in probe_28sf040() causing flash corruption on SST49LF160C verify.
    
    The first byte of the flash chip was read at the start of the function
    and later written back to address 0 if the flash chip was not identified
    as SST28SF040, which means most of the time. This write caused corruption
    of flash contents when verifying a SST49LF160C part.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d43255bef8ca14f707c1e21dd42d8a6afdf991c
Author: Luc Verhaegen <libv@skynet.be>
Date:   Sat Aug 11 16:59:11 2007 +0000

    flashrom: Add board enable for the EPoX EP-BX3.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ab22686b8f0e018dff299c50ff775880f018d38
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Jul 27 03:32:45 2007 +0000

    flashrom: Add missing supported flash chips to the README (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae293d74f9b509067bc4c2a85f511c10107bf048
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Wed Jul 25 17:55:45 2007 +0000

    This patch adds support for the M50FLW040A, M50FLW040B, M50FLW080A,
    M50FLW080B, M50FW080, M50FW016, M50LPW116, M29W010B flash chips made
    by ST to flashrom.
    
    The patch is based on the data sheets of the chips and has not been
    tested at all.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a262082ba547952cff1361d3ff1d6357fbe9a33
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Tue Jul 24 18:18:05 2007 +0000

    This patch adds support for ST M50FW040 and ST M29W040B to flashrom.
    Only reading from the chips was tested; writing support is untested.
    
    Thanks to Gürkan Sengün <gurkan@linuks.mine.nu> for testing!
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 451762dabc6cdb8d5e1c40aa0184a673979f5572
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Jul 12 20:07:54 2007 +0000

    Fix Agami Aruma target (the only one using the part)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c0a689cc1fe004342f3fa8ad4bb71f432380f8e3
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Jul 12 17:02:52 2007 +0000

    trivial: clarify comment on ADM1026_DEVICE address
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6540ae5ea0a52e05ceb31675a2419d07197db738
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Jul 12 16:35:42 2007 +0000

    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6cf687783bc9c54146cf85ce5e526e63ab7047fb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Jul 12 15:56:02 2007 +0000

    some agami i2c merges
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3fa1363ee5d7a1400203bd1486f8e80a8cacc992
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Jul 12 13:13:56 2007 +0000

    [Arg! Forgot to 'svn add', sorry]
    
    Generic driver for pretty much all known Standard Microsystems Corporation
    (SMSC) Super I/O chips.
    
    Most of the SMSC Super I/O chips seem to be similar enough (for our
    purposes) so that we can handle them with a unified driver.
    
    So far only the ASUS A8000 has been tested on real hardware!
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa4bedf98e779a918aded88f98775d37542cd5fd
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Jul 12 13:12:47 2007 +0000

    Generic driver for pretty much all known Standard Microsystems Corporation
    (SMSC) Super I/O chips.
    
    Most of the SMSC Super I/O chips seem to be similar enough (for our
    purposes) so that we can handle them with a unified driver.
    
    So far only the ASUS A8000 has been tested on real hardware!
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Corey Osgood <corey.osgood@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9bcad23ba15a34372eb2256916580375049f29ce
Author: Luc Verhaegen <libv@skynet.be>
Date:   Wed Jul 4 17:51:49 2007 +0000

    Flashrom: Add support for Tyan Tomcat K7M.
    
    Same board enable as Asus A7V8-MX. Tested by Reinhard Max.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a0aaa752dd69a4454ddc94df1196607c14ea7756
Author: Marc Jones <marc.jones@amd.com>
Date:   Wed Jun 20 23:45:44 2007 +0000

    Artec Group dbe61 mainboard support.
    Now uses CAR.
    New code for SPD-less memory implementation.
    Updated IRQ routing.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dfb3c130d5cdd3a01531c23c3d15e7a1010bf221
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Jun 19 22:47:11 2007 +0000

    Various minor cosmetics and coding style fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c72ff11281233c097441e809a52b560b1a131196
Author: Marc Jones <marc.jones@amd.com>
Date:   Tue Jun 19 22:07:16 2007 +0000

    The GPIOs used for UART2 RX and TX were reversed.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cbb8d8ad24cf356d67f8f3a29014342252b9a5b1
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Tue Jun 19 07:33:39 2007 +0000

    This patch fixes up a couple mistakes I made with the i82810 and mew-vw to make
    the system boot to a command line.
    
    This patch comments out the code to set up the vga framebuffer to allow
    the system to boot, without this fix the system hangs during elfboot.
    
    The only line that is absolutely necessary to change is the SMRAM setup,
    however I've commented out all vga setup to make it very obvious to both
    the kernel/payload and anyone looking at the code that vga isn't
    currently working. This setup might also be better handled in
    northbridge.c, if it doesn't need to be done before ram init, yet
    another reason to comment it all. In the future, LinuxBIOS needs to be
    told that the graphics memory area, 1mb or 512kb (at the user or
    developer's option), is reserved for the onchip vga, but I'm not sure if
    it's taken at the top or bottom of the memory, yet. LB may also need to
    set a base address for the AGP aperture and/or be told that range is
    reserved as well, whether this was originally the job of the system bios
    or vga bios is still a mystery. It also corrects the number of entries
    in irq_tables.c, without this fix the kernel would probably complain and
    hang due to unmapped IRQs.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 440113f00ba67a54ff7ceff772fffa46325a7e8e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Jun 14 21:45:21 2007 +0000

    small agami aruma configuration updates (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc53b3c1cafb75f48b8ab1f37addf2875b640d46
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Jun 14 19:52:27 2007 +0000

    Fix the static device tree of the ASI MB-5BLMP target. This was broken in
    more than just one way. This version should be (more) correct.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd55e86a52a98c1acae30bc699eaaa12f416de51
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu Jun 14 17:00:50 2007 +0000

    his patch fixes the CAS map for -.5 and -1 CAS settings. The -.5 setting should only shift the mask one bit, not two.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Jordan Crouse <jordan.crouse@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9e56e9cd3f5b4b35917c010de60369285bb39da
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Thu Jun 14 12:04:19 2007 +0000

    Small bugfix in i82801xx_lpc.c.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c0eb5e08305ad6caa145631f9c67cf1b1a378b36
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Thu Jun 14 12:02:38 2007 +0000

    Add initial support for the Intel 82810 northbridge.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e99bd105af97ad905114bd76ae09326a10def8cf
Author: Corey Osgood <corey.osgood@gmail.com>
Date:   Thu Jun 14 06:10:57 2007 +0000

    This patch adds support for the Intel i82810 northbridge and various i82801xx
    southbridges, along with the Asus MEW-VM. With this, my machine attempts to
    boot linux, but does so very slowly and fails during the boot process, probably
    because of the irq tables.
    
    Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
    Acked-by: Joseph Smith <joe@smittys.pointclark.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd88057f73b83e5bfd9d0fe57b28c87c98d73b12
Author: Marc Jones <marc.jones@amd.com>
Date:   Tue Jun 12 22:54:41 2007 +0000

    Add the AMD DB800 (AKA Salsa) mainboard.
    The DB800 is the AMD LX Reference Design Kit platform.
    For details see: http://www.amd.com/geodelxdb800
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc359473e23e4873b5f30f27680242fc939aa23b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Jun 7 22:16:30 2007 +0000

    Minor tweaks in the 440BX RAM init code (trivial).
    Still hardcoded for Tyan S1846.
    
    This slightly increases performance, but it's still pretty horrible.
    Some RAM settings are causing a dramatically slow system (confirmed
    by comparing memtest performance results of the proprietary BIOS
    and our code). Haven't found the problem, yet.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 538b849695feccfd6a1419652de2608f0f5bdf1b
Author: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Date:   Thu Jun 7 20:52:42 2007 +0000

    Add support for the IEI JUKI-511P and IEI ROCKY-512 half-size boards.
    
    Both are very similar, thus both use the JUKI-511P target.
    
    Linux with patches from Juergen Beisert
    (http://www.linuxbios.org/pipermail/linuxbios/2007-May/020932.html)
    boots and work fine (ide, usb, ethernet, serial, keyboard and sound
    work normally).
    
    Problems:
     - Filo loads a bzImage only from ide0 (ide1 doesn't work yet).
     - Video doesn't work, yet.
    
    Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e29a664b5438e1e7e4aaea0b51ea4a7b622aa934
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Jun 6 21:35:45 2007 +0000

    Fix up and document the AMD CS5530/CS5530A support in flashrom.
    
    The previous code was pretty unreadable, undocumented and did some totally
    unrelated things (such as mucking with the game port or port 0x92).
    
    This version is tested with a 256 KB chip and should work for the
    CS5530 and CS5530A.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ecbe8e5d5cac1c37d9ce40bae39d4f763075fce0
Author: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Date:   Wed Jun 6 10:26:00 2007 +0000

    Add support for the Winbond W83977F-A Super I/O.
    
    Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66020709559e481e1d9b062156fe01016db25c60
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Jun 5 15:02:18 2007 +0000

    flashrom: Document the newly supported IBM x3455 board and the
    now-supported Broadcom HT-1000 chipset (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e2a42ae3288e1054fe367bee27f3894a7300f33
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jun 5 12:51:52 2007 +0000

    Move GPIO settings to board specific code for IBM x3455
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 444e39ee6d0a0458d751e48db33380af2dcad7d1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Jun 5 10:28:39 2007 +0000

    Add support for BCM HT1000 chipset to flashrom. Tested on IBM x3455.
    (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 973b0680a1e9cb76d90a4c1499d6041f71440ad9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jun 3 23:19:19 2007 +0000

    Switch the Tyan S1846 to a fallback-only boot per default to allow
    bigger payloads (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e96adbbabad9fe2bdf310ce75a3b550e55b67f4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jun 3 21:57:55 2007 +0000

    Tyan S1846: Minor fixes in static device tree (trivial):
    
     - Linux booted with the proprietary BIOS reports 2e.f as PS/2 mouse
       in the output of 'lspnp -v'.
    
     - The floppy on 2e.f was a typo, should have been 2e.e from the beginning.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4ce039feee84dac65e50f886e013b01e68995450
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jun 3 20:39:47 2007 +0000

    Fix the static device tree of the Tyan S1846. Especially the
    Super I/O part was incorrect.
    
    Also, add ide0_enable/ide1_enable variables, and enable both the
    primary and secondary IDE interface per default.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 56a9125453cff37477d638e9266f0bd55bdd8528
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Jun 3 16:57:27 2007 +0000

    Intel 82371EB: Some code simplifications (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f027280d39d58fa145a0c966ed6c3068de54cdbf
Author: Marc Jones <marc.jones@amd.com>
Date:   Sat Jun 2 23:55:17 2007 +0000

    The UART disable code was causing a hang and was worked around with a
    return that skipped the disable code. This patch removes the return and
    fixes the UART disable code.
    
    The problem was that the disable code was ORing bits into the Legacy_IO
    MSR causing issues with the LPC SIOs init code that would manifest as a
    hang because the IO would not be decoded correctly. ANDing to clear the
    bits fixes the issue.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 22c6afcae4481a593d31334a31ecf412909fd921
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue May 29 19:26:37 2007 +0000

    Drop duplicate 82371AB device IDs (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a5599c10cf2271e4b809630ffc6b5c4a509cb510
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue May 29 12:06:06 2007 +0000

    Use the common LinuxBIOS license header format.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1410c2d2192c4f2e782ac9af97c9df0165c3974e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue May 29 10:37:52 2007 +0000

    Intel 82371EB: Add IDE init support.
    
    In a mainboard's Config.lb file you can configure whether the primary
    and/or secondary IDE interfaces shall be enabled.
    
    Also, various fixups in the rest of the southbridge code, most notably
    the early SMBus code, plus some documentation improvements.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Corey Osgood <corey_osgood@verizon.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 861f96403777c8f4475ca94613c5142075dd0cdf
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon May 28 14:37:06 2007 +0000

    Lower the RAM init delays we use on the Intel 440BX.
    
    As per JEDEC, we should wait 200us until voltages and clocks are stable.
    Then apply NOPs for 200 clock cycles (for simplicity we use 200us here).
    
    All other delays are so low that we get away with just waiting 1us.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f5a6fd253c3d289bd70917504f59255038d476a2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun May 27 23:31:31 2007 +0000

    Various 440BX and Tyan S1846 related minor changes and fixes (trivial):
    
     - Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's
       available on all boards, regardless of what DIMMs you use.
       Tested on the Tyan S1846, works fine.
    
     - Properly set the PAM registers to allow the region from 768 KB - 1 MB
       to be used as normal RAM (required for the above).
    
     - Document all of this properly. Add/improve other documentation, too.
    
     - Simplify and document code in northbridge.c.
    
     - Cosmetics and coding style.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4cb85533dd14731048b65d8f2e165a271b98953e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun May 27 21:43:58 2007 +0000

    Init for the Intel 82371EB southbridge: make all ROM/BIOS regions
    accessible (but not writable), so that reading/loading a payload
    from that area can work (for instance).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4834a4f2063509cbdb2ab20114f18664d5e9caf2
Author: Sven Kapferer <skapfere@rumms.uni-mannheim.de>
Date:   Sat May 26 13:56:34 2007 +0000

    This patch fixes the processor name string for Rev F. CPUs.
    It moves the complete naming functionality to
    src/cpu/amd/model_fxx/processor_name.c.
    
    The current code sets the processor name string twice for Rev. F CPUs.
    
    In src/cpu/amd/model_fxx/model_fxx_init.c the function
    amd_set_name_string_f is called first. Several lines later
    init_processor_name is called which doesn't recognize newer CPUs and
    actually programs incorrect values, thus overwriting the previously set
    CPU name. For example, this resulted in identifying an Opteron 2218 as a
    Turion processor.
    
    This patch removes the amd_set_name_string_f function from
    src/cpu/amd/model_fxx/model_fxx_init.c and adds support for Rev. F CPUs
    to src/cpu/amd/model_fxx/processor_name.c as described in the Revision
    Guide for AMD NPT Family 0Fh Processors, AMD Document ID 33610 Rev 3.00,
    October 2006.
    
    Signed-off-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd3afc052492e577774b1978f47f2ed28cea7d01
Author: Philipp Degler <pdegler@rumms.uni-mannheim.de>
Date:   Thu May 24 20:39:48 2007 +0000

    Add initial support for the ASUS A8N-E board.
    
    Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 63b087a8abba3516ddde5c3984b9803948e77396
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu May 24 19:46:32 2007 +0000

    Drop the src/southbridge/amd/cs5536_lx directory and its contents, as
    the new src/southbridge/amd/cs5536 code completely replaces it.
    
    The Artecgroup dbe61 board currently uses it, but that is broken anyway
    at the moment. A fix to use the new CS5536 code for it is being worked on.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da0eec07fbd5e56a95b54e11d5356aa59b486d95
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu May 24 19:17:29 2007 +0000

    Minor cosmetics (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4adc7421f5b7c175c34f87d939309034f701d62c
Author: Philipp Degler <pdegler@rumms.uni-mannheim.de>
Date:   Thu May 24 18:44:50 2007 +0000

    Various IT8712F fixes:
    
     - Add missing IT8712F_GPIO definition.
     - Add functions for entering and exiting MB PnP mode.
     - Add some more device init lines to pnp_dev_info[].
    
    Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ecfa2963d4d8d80a01eddbecba87124dee3c516
Author: Philipp Degler <pdegler@rumms.uni-mannheim.de>
Date:   Thu May 24 13:55:45 2007 +0000

    Small patch that adds an error message in case the keyboard selftest fails.
    
    Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1bccabc16c9044919c9e6eeb1977cf256ded0ae9
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu May 24 09:26:39 2007 +0000

    drop leftover includes (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0c6c4fcaf96b9191dfdcabe5cd63c66223c61c3b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu May 24 09:08:36 2007 +0000

    some copyright analysis
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8924fdd22b2399bb09a09b4b35317202c391f858
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu May 24 08:48:10 2007 +0000

    factor out register mapping code (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a18501dae89c0ede2a208f8f72449e2357d2c88b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 23 18:24:58 2007 +0000

    Unify mmap error messages in flashrom (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8eea5cd1c641495bdc635e61575597a82629ef8
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed May 23 17:20:56 2007 +0000

    big cosmetic offensive on flashrom. (trivial)
    * Give decent names to virt_addr and virt_addr_2
    * add some comments
    * move virtual addresses to the end of the struct,
      so they dont mess up the initializer.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2d1428120a9fee473b38492c6cf062ca8341e93
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue May 22 15:04:28 2007 +0000

    reverting 2683, NAK by YhLu, patch not necessary.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 344e45748a13808a63b76668243a33ef29d97bc5
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue May 22 10:12:49 2007 +0000

    Add missing license headers, minor cosmetic fixes in existing headers.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8953dc0953ea74f42e442e857948589302f5476
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon May 21 21:39:08 2007 +0000

    Add support for the Winbond W39V040FA chip.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0af4856017431f0e9ef99e6a99e2a2da9f50f593
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon May 21 21:36:03 2007 +0000

    Drop the (non-working, almost non-existant) support for
    
     - the Transmeta TM5800 northbridge
    
     - the Densitron DPX114 mainboard (the only one using the TM5800)
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1e79f12654d99bf786d5d2249bfbf61cd92523ff
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon May 21 21:33:24 2007 +0000

    Drop romcc related stuff, as this board only uses CAR.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 931d92217627ae05a6f5b01198fae74854bd6f49
Author: Ward Vandewege <ward@gnu.org>
Date:   Mon May 21 20:50:48 2007 +0000

    The Gigabyte m57sli-s4 board supports Rev. F CPUs.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca7b4f5c494377fee2f885a65752f7b92d5ac2d6
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon May 21 18:38:29 2007 +0000

    fix some typos, clarify comments and drop dead code (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ecad5df6b787ce3ce8e471fc7e836e4957b0f247
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon May 21 18:11:17 2007 +0000

    This is the last remainder from Yinghai's mega patch. It fixes issues with
    devices conflicting with the northbridge devices on PCI bus 0.
    
    Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c141282193880a722bbb26f694fdebf37d5dd2bb
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sun May 20 17:28:55 2007 +0000

    fix lbtdump after last checkin. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 917bf6b99e04320949c99289d456d9f9a79b4dee
Author: Ben Hewson <ben@hewson-venieri.com>
Date:   Sun May 20 17:10:17 2007 +0000

    Here is a small fix to prevent a segmentation fault in lbtdump.
    
    The format specifier in the printf statements have been changed from
    %08lx to %08llx or similar where uint64_t are being displayed.
    
    Signed-off-by: Ben Hewson <ben@hewson-venieri.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7f4040af820372764a4038acb80f42f60148aced
Author: Jeremy Jackson <jerj@coplanar.net>
Date:   Sun May 20 16:36:01 2007 +0000

    Add additional CPU device ID:
    
    CPU: vendor AMD device
    30ff2
    CPU: family 0f, model 3f, stepping 02
    
    All I know is this makes it boot when it didn't before, YMMV.
    
    Signed-off-by: Jeremy Jackson <jerj@coplanar.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a56b99879680890283a4f0a9788b950d48b41986
Author: Luc Verhaegen <libv@skynet.be>
Date:   Sun May 20 16:16:13 2007 +0000

    Flashrom: add support for ASUS P5A (Socket 7, ALi based).
    
    * Add support for the ALi M1533 to chipset_enable.c
    * Add some SMBus poking needed for the ASUS P5A, to board_enable.c
    
    Since PCI subsystem IDs are worthless with this board, people will
    have to name the board directly.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a2193e6f1a82a837c3562bb4b311fd2c3c5f007
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat May 19 19:22:55 2007 +0000

    Fix typos (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cbd53554df3088e905577d013bdd864fb82d3fb7
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat May 19 17:28:40 2007 +0000

    Minor cosmetics (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0196f82218e6bd99f62327d97b7499e2dc52c08e
Author: Ward Vandewege <ward@gnu.org>
Date:   Sat May 19 16:07:08 2007 +0000

    Initialize the fans on the adt7463 chip to be dynamically regulated by the
    hardware, rather than always on at full speed. Set temperature treshold values
    to safe defaults, rather than the not-so-safe power-on defaults.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    
    Acked-by: Yinghai Lu <yinghailu@gmail.com>
    Acked-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a9db88d5ccf08b0bf627ae848b27ff7ed10f352
Author: Luis Correia <luis.f.correia@gmail.com>
Date:   Thu May 17 16:00:30 2007 +0000

    Add missing license header (closes #53).
    
    Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 819f5810b6979fda870285d1ce8192ff26d9c883
Author: Corey Osgood <corey_osgood@verizon.net>
Date:   Thu May 17 11:20:18 2007 +0000

    Whitespace fixes (trivial).
    
    Signed-off-by: Corey Osgood <corey_osgood@verizon.net>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cbe4e1f3d2674236f5e934a3e7c33e750c278cd1
Author: Roger Zauner <roger@eskimo.com>
Date:   Wed May 16 06:58:15 2007 +0000

    Cosmetic changes: push includes to top of file in chip.h files.
    
    Signed-off-by: Roger Zauner <roger@eskimo.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4c0d39fc592857a076f48fbf9552ced2ed702ffe
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue May 15 10:26:16 2007 +0000

    Simplify spd_read_byte() functions (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f1ff2c38d2fcee9fba0d6b28cd701db7e93b3c62
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue May 15 07:11:09 2007 +0000

    Various cosmetic fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c161808985145e8b120c7923c0677c302673b5a9
Author: Luis Correia <luis.f.correia@gmail.com>
Date:   Tue May 15 06:57:57 2007 +0000

    IEI NOVA-4899R: Add missing license headers.
    
    Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4c8c56753c966197edb0c334ee5ad84825d1b297
Author: Luis Correia <luis.f.correia@gmail.com>
Date:   Tue May 15 06:56:12 2007 +0000

    IEI NOVA-4899R: Correctly configure Super I/O PNP devices.
    
    Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 197daeda5a17757630ed5043ffcc33b96a1c4ca2
Author: Luis Correia <luis.f.correia@gmail.com>
Date:   Tue May 15 06:55:03 2007 +0000

    IEI NOVA-4899R: Fix incorrect irq_tables.c.
    
    Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8bcf08b1194536f4f9ecb4ce74df941d18f4d439
Author: Luis Correia <luis.f.correia@gmail.com>
Date:   Tue May 15 06:50:06 2007 +0000

    IEI NOVA-4899R: Drop unused files.
    
    Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d83f79f3b8101be55f157c8ecc9e8f210ecae080
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon May 14 11:33:41 2007 +0000

    AMD Norwich: minor cosmetic fixes and drop dead code (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4aae668fed2dc32b86009b283d880c68d56d1369
Author: Ward Vandewege <ward@gnu.org>
Date:   Fri May 11 19:23:57 2007 +0000

    Clean up whitespace in preparation for another patch to fix fan control.
    
    This is nothing more than the result of running
    
      indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs adm1027.c
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 298a693c6b5909d93fc25c95a975c3f8433aff1d
Author: Roger Zauner <roger@eskimo.com>
Date:   Fri May 11 11:17:58 2007 +0000

    The Super I/O needs 0x87 sent twice to 0x2e (or 0x4e) to enable extended
    function (power-on strapping). Although this is already done in superio.c,
    it's not being done when w83627thf_early_serial.c is executed.
    As such, no console_init() without it.
    
    Signed-off-by: Roger Zauner <roger@eskimo.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f03e4e97ce8dae953735a595a04a62e7b01f6c93
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu May 10 23:59:20 2007 +0000

    Fixup the 440BX northbridge.c (self-ack as this wasn't working anyway).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d03b7d428978ce53dc9aa5e7df6ada2f78c96c61
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu May 10 23:53:11 2007 +0000

    This fix properly hides the UDC and OTG PCI headers when the cs5536 is
    setup as the host on USB port4. In client mode the headers remain
    available. Also fixes an outb to 0x80 to use the post_code() function.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit deabf510bff37c1f3a1fd3ec50b88db17d38b802
Author: Peter Stuge <peter@stuge.se>
Date:   Thu May 10 23:50:27 2007 +0000

    Changes by Richard Smith and Peter Stuge from the LinuxBIOS symposium 2006.
    
    With CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0, 1 million outb():s are used
    for timer calibration, which takes about one second.
    
    All EPIA-M boards have timer2 so we use it to boot faster.
    
    Only some EPIA boards have the Nehemiah CPU with timer2 so we default to IO
    calibration but add the TSC options so that they can be set in Config.lb.
    
    src/mainboard/via/epia*/reset.c is dead code (entire file within #if 0) so we
    set HAVE_HARD_RESET=0 for both boards.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ddf845f620eb43d9ea2e8b0b265c321c6e797e6f
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu May 10 23:22:27 2007 +0000

    This patch cleans up and clarifies Geode source code comments.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03625f4daf8bd92b8be64d795f8e46c01cc7468d
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu May 10 23:13:18 2007 +0000

    This patch cleans up \r left in the print strings. They were required for romcc code but no longer needed in cache as ram code.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a909ee6185ac7e784d7aae26c359506a72756793
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu May 10 23:12:18 2007 +0000

    This patch updates the PCI ID of the Geode IDE device to include the revision.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e1dd5e96c83dee11d0dbd6c5b7ab2a3651d9f7ec
Author: Ceri Coburn <ceri.coburn@gmail.com>
Date:   Thu May 10 22:46:17 2007 +0000

    Fixed a bug within the 440BX RAM size calculation. Since the DRB values
    on the 440BX are 8 MB units we need to shift left by 13 to get it into KB.
    
    Signed-off-by: Ceri Coburn <ceri.coburn@gmail.com>
    Signed-off-by: Roger Zauner <roger@eskimo.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 00dc8595a63483e0cc93e8518993d12f4fe8227a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu May 10 22:21:13 2007 +0000

    indent is by no means as harmless as one might think ;-)
    trivial fix.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f05e85b390244e596dd0fc73bb774607b0c1ff9a
Author: Alex Mauer <hawke@hawkesnest.net>
Date:   Thu May 10 19:02:19 2007 +0000

    The attached patch sets the MA map type correctly for all DIMMs I was
    able to find to test with the Epia.
    
    Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1346a27dee50e200b6e36bf378aa8ed10457b8f2
Author: Marc Jones <marc.jones@amd.com>
Date:   Thu May 10 18:49:58 2007 +0000

    This patch removes auto.c from the Norwich mainboard directory.
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2a133f7851dd819fe4d99adebbd8fb4c173ae579
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu May 10 18:43:57 2007 +0000

    Fix the indent and whitespace to match LinuxBIOS standards
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9934b813da2556ab8159cfc13fb993ae98b04db4
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu May 10 18:32:28 2007 +0000

    Fix the indent and whitespace to match LinuxBIOS standards
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8030bd9245f2f6fb7418595d58dc4326f6621f3
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu May 10 18:16:03 2007 +0000

    Fix the indent and whitespace to match LinuxBIOS standards
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 89d7cd2c833245078d917bf7d85b3a7ba4fd6c03
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu May 10 18:00:24 2007 +0000

    Fix the indent and whitespace to match LinuxBIOS standards
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4fcb3ba93f483e194630710f61edde6572b2dc70
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu May 10 17:58:11 2007 +0000

    Add missing licenses to several of the files.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b29209f5f73f1f35d1e092d2bfa10a8dd1bec7db
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu May 10 17:57:03 2007 +0000

    Add missing licenses to several of the files.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a846a5effcf46afac9f65df49ce5350b36dc1096
Author: Roger Zauner <roger@eskimo.com>
Date:   Wed May 9 17:54:25 2007 +0000

    The superio needs 0x87 sent twice to 0x3f0 to enable extended function
    (power-on strapping). Although this is already done in superio.c, it's
    not being done when w83977tf_early_serial.c is executed. As such, no
    console_init() without it.
    
    Signed-off-by: Roger Zauner <roger@eskimo.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a59a7788b49ceb52571093667a595566691061ed
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed May 9 15:11:03 2007 +0000

    Uncomment compression config variables. This should fix the abuild
    problems with the asi/mb_5bmlp (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7dc7cc196a4bd5ba1cfafc87b193b89ae01a470
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed May 9 10:17:44 2007 +0000

    Fix coding style of flashrom by running indent on all files:
    
      indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]
    
    Some minor fixups were required, and maybe a few more cosmetic
    changeѕ are needed.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 33d1af37ae58c34288ae5fad9879a2ea2b752620
Author: Corey Osgood <corey_osgood@verizon.net>
Date:   Wed May 9 08:11:52 2007 +0000

    This patch uses auto.c from Uwe's tyan s1846 for both boards, with some
    minor changes, to bring them up to par. It also should remove (but might
    just clean out) the irq_tables.c from both boards, because they were
    just copied from Via Epia to begin with, and weren't usable. As far as I
    can tell, these are the only changes needed to the targets for now,
    aside from fixups to reset.c when the time comes. Both have been build
    tested, but not checked on hardware since I don't have it. I have left
    Uwe as the copyright holder since the only changes I've made are trivial.
    
    Signed-off-by: Corey Osgood <corey_osgood@verizon.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a440f7fd8c2db22ef84b7b85839cdcbbb1afdc09
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed May 9 07:52:14 2007 +0000

    Add initial support for the ASI/BCom MB-5BLMP mainboard, as used in
    the IGEL Winnet III thin client.
    
    It boots a Linux kernel, but there are some problems. The login
    prompt is never reached, it simply hangs at some point.
    One possible reason is the IRQ table, which needs fixing.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6b83e46f3bb3434600c26fdfab3b802028d431a3
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue May 8 16:04:36 2007 +0000

    New irq table, and a correct setting for
    the 5c register in the southbridge so that interrupts are routed
    correctly.
    With this patch, ethernet works quite well.
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50b0b8702cf389778f644a12857102b4683dcffe
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Mon May 7 22:26:46 2007 +0000

    Add missing licenses to several of the files.
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa6c11eb40325f241c6a98300fa1dcfec90f8ca8
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat May 5 03:54:13 2007 +0000

    This is the final patch to enable the msm800sev to build. This patch
    adds a symbol to the model_lx/cache_as_ram.inc, and modifies some
    files in the mainboard directory. This patch has been tested but there
    is a remaining problem which I am tracking down. Expect one more patch
    to "get it all working".
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ef8b0f62b5d222d575b6e6e314fc309d10488b5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat May 5 00:10:31 2007 +0000

    With this patch, the msm800sev runs FILO and boots a kernel.
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    -This line, and those below, will be ignored--
    
    M    cs5536.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 75869ff4111ded406e7bf702132a17005da85be1
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri May 4 23:15:28 2007 +0000

    This patch as a cache_as_ram_auto.c for the msm800sev.
    
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f64633e2c79624973998deb90e855f278856e36b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri May 4 21:52:18 2007 +0000

    Drop src/mainboard/amd/norwich/debug.c as it is not used.
    
    I'm self-acking as this is pretty trivial. I tested both a normal build
    and an abuild-run, and nothing breaks.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3438421fd3df961edac0a024c183510dde926a3e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri May 4 21:33:40 2007 +0000

    Some minor fixes in it8716f/superio.c:
     - Add Ward Vandewege <ward@gnu.org> as copyright holder.
     - Use explicit 'uint16_t' instead of 'unsigned long'.
     - Minor cosmetics.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ward Vandewege <ward@gnu.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b93f9cadb2a13f53cf8a6c405b2fd623898f418c
Author: Ben Hewson <ben@hewson-venieri.com>
Date:   Fri May 4 19:43:57 2007 +0000

    patch to fix the IDE configuration on EPIA boards. At some point this
    broke and stopped FILO
    from being able to boot.
    
    The fix is a simple one line change  plus a comment to
    src/mainboard/via/epia/auto.c to write to the IDE
    configuration register 0x42 .  This has always been done here, however
    at some point
    something broke it.
    
    The same register was also being set correctly  in ide_init(), however
    for some reason
    this does not work. Possibly the register needs to be set before the IDE
    peripheral is enabled
    or maybe it is a timing issue.
    
    The section of code in ide_init() (
    src/southbridge/via/vt8231/vt8231_ide.c ) that does
    write to register 0x42 has been commented out as it is superfluous
    and I have added a comment to indicate the reason, should someone at a
    future date wonder
    why.
    
    I have also changed the default COM speed from 19200 to 115200 in
    src/mainboard/via/epia/Options.lb
    There has been mention before about the EPIA board not being able to use
    115200 but I have seen
    no such problems with my board.
    
    Signed-off-by: Ben Hewson <ben@hewson-venieri.com>
    This patch worked for me and allowed me to boot Debian kernel
    2.5.16-4-486  on an epia 800 mhz system.  It is able to consistently get
    through the initialization and start init now.
    
    However, after that it crashes at various points in the boot process.
    
    Acked-by: Alex Mauer <hawke@hawkesnest.net>
    
    Note from comitter: I am commiting this, although:
    1. it's not the exact right way to fix it up, the chip.h for the sb
    should change
    2. Alex reports problems, which are almost certainly memory issues.
    
    But it is as close as we've gotten. I can't test it.
    
    Ron Minnich
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 08da4f1fce68748c2aea8ef5ff4109ea6d3f0d82
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri May 4 19:09:01 2007 +0000

    This repairs the other Geode mainboards so they'll build with the new
    Geode changes.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a67d4fd1ffffc76c328717f2519e3d7e7792f2b8
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri May 4 19:05:36 2007 +0000

    This patch re-implements support for the CS5536 companion chip for the
    AMD GX and LX processors.   This aguments the previous code, which was
    very specific to the OLPC platform with general purpose support and
    better integration with the VSA and CPUs.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 734daf699ceb8603f53003ab36eb85b8a76e3cf9
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri May 4 18:58:42 2007 +0000

    This patch adds support for the northbridge integrated into the AMD
    Geode LX platform, including memory and graphics. (rediffed for whitespace)
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c9083ba4a1cd280fe70c0eec78e562d714a2dc7
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri May 4 18:47:52 2007 +0000

    This patch adds support for the AMD Norwich development platform
    based on the Geode LX processor.  The Norwich is the canonical
    Geode reference, and will server as a good basis for other
    Geode based platforms.
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc8176c5526ec9124aa99559f9432210be364dfe
Author: Marc Jones <marc.jones@amd.com>
Date:   Fri May 4 18:24:55 2007 +0000

    This patch adds support for the AMD Geode LX CPU. (rediffed)
    
    Signed-off-by: Marc Jones <marc.jones@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5941c25fe8e2118c93ef695ea3b30b65e016cdc1
Author: Luc Verhaegen <libv@skynet.be>
Date:   Fri May 4 04:47:04 2007 +0000

    Add WinBond Super IO helpers.
    
    * These helpers severely clear up winbond superio usage.
    * Removed board_iwill_dk8_htx as it can be replaced by
      board_agami_aruma (Mondrian Nuessle).
    * Renamed board_agami_aruma to w83627hf_gpio24_raise.
    * Clarified comments in w83627hf_gpio24_raise, and added
      some things from the old iwill code.
    * Moved all board functions name argument to const.
      (warning breaks build)
    * Moved iwill entry in board_pciid_enables.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ea18cf5dd22caa62e4bb2a6369208eae53b179c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri May 4 00:51:17 2007 +0000

    Cosmetics (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6818245b1e4eb0db4c808b20b83d9e3ceb583d05
Author: Jordan Crouse <jordan.crouse@amd.com>
Date:   Thu May 3 21:36:51 2007 +0000

    Add missing license headers to some Geode LX related files.
    
    The following original authors agreed to the license:
    
     - Ronald G. Minnich <rminnich@gmail.com>
     - Indrek Kruusa <indrek.kruusa@artecdesign.ee>
     - Stefan Reinauer <stepan@coresystems.de>
     - Andrei Birjukov <andrei.birjukov@artecdesign.ee>
    
    Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24c9612490daf25d56c51c6a7cf819297623c952
Author: Mondrian Nuessle <nuessle@uni-mannheim.de>
Date:   Thu May 3 10:09:23 2007 +0000

    Enable flashing on the IWILL DK8-HTX board by configuring the Super I/O
    to set the right GPIO pins, so write protection is disabled.
    
    Signed-off-by: Mondrian Nuessle <nuessle@uni-mannheim.de>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d436a4b4bc035a3756a57ae8e632e16f7a95b9c9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu May 3 08:50:37 2007 +0000

    Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB,
    as that is not RAM but used for other stuff.
    
    First try at PCI init added to src/mainboard/tyan/s1846/Config.lb.
    
    Use a real payload (FILO) per default now.
    
    Note: this cannot boot a payload, yet, but it gets a lot further now.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 941a6f078ece125a5c116315c82fcd3cb1feaf42
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Apr 30 23:27:27 2007 +0000

    Fix typo: s/PRINT_DEBUG_/PRINT_DEBUG/ (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7580f87f7ad469de61cd4ffd4c978532c4bbb0e3
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Apr 28 02:22:59 2007 +0000

    Add initial support for the following flash chips:
    
     - Atmel AT29C020
     - STMicroelectronics M29F002B
     - STMicroelectronics M29F002T
     - STMicroelectronics M29F002NT
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Signed-off-by: Roger Zauner <roger@eskimo.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 989de36703684e3686de730b1a56e41eeca5d5d5
Author: Ward Vandewege <ward@gnu.org>
Date:   Fri Apr 27 21:24:53 2007 +0000

    Add fan control support to ITE IT8716F.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e08333349e01961a1019283ce03d02dae56e3a7
Author: Ward Vandewege <ward@gnu.org>
Date:   Thu Apr 26 20:55:45 2007 +0000

    Activate EC for access to fan speeds and temperature sensors.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dabbf5777b172f13748569b442e2b5e2fe0c2f00
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Apr 25 00:23:39 2007 +0000

    Revert the image size increasing for abuild. It breaks more boards than
    it fixes. It seems many of the other boards run out of space for the
    payload.
    
    Thus, this patch only increases the image size for the three boards
    
     - tyan/s2912
     - nvidia/l1_2pvv
     - gigabyte/m57sli
    
    by adding a custom Config-abuild.lb file for each of them.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f83c1826386b7d8af12cc353b9a5226222b814bb
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Apr 24 21:54:21 2007 +0000

    Increase image size for abuild. This should fix the build of these boards:
    
     - tyan/s2912
     - nvidia/l1_2pvv
     - gigabyte/m57sli
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cdc5cc671197d7b3e5505626650ccc39ead25486
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Apr 24 18:40:02 2007 +0000

    trivial: fix filename in comment.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b80dbf0caa606f2485a73215496748c4b0c830fa
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Apr 22 19:08:13 2007 +0000

    Add explicit license headers to all files in src/device.
    
    For files derived from the Linux kernel we merely add a small header
    which states the origin of the file and the copyright owners of the
    modifications to the file.
    We know all files from Linux are licensed under the GPLv2.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f278ad828a59a1c39f5fa8ed9461fcd2506fd2b
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Apr 22 19:03:34 2007 +0000

    Use __PAYLOAD__ instead of PAYLOAD as replacement template for abuild.
    
    Comment out code which currently doesn't compile. Needs fixing later.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a94b4c6bc1b4fd0dfeac4d4bfae13700a79d2f6e
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Apr 22 01:17:36 2007 +0000

    Update URL for the PCI IRQ Routing Table Specification (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29800b76eebd10444044b5cfb2269a7566059615
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Apr 21 18:17:50 2007 +0000

    Make the output of getpir look a bit less crappy (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9d5eec13a9aa1034323c9d9b37593c565ca57b6d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 14 16:34:32 2007 +0000

    This patch makes a some elf debugging information available at log level
    debug instead of spew. (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f1291cfdfc6db3922b8aa4672b5511104671788a
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 14 16:32:59 2007 +0000

    Exit on return code of read_layout and print error message to stderr
    instead of stdout (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0594222eceb5ba642edf813373dd7c979520fcd3
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Thu Apr 12 01:23:12 2007 +0000

    On behalf of AMD:
    
    Drop AMD prototype mainboards that were for internal testing &
    validation use only.
    
    Note: These boards could never be purchased. No reasons to worry.
    Questions welcome via private mail.
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f0cf523a9e9e04fbf924859e3b8cbdb9d3d61931
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 12 00:47:22 2007 +0000

    add uses CONFIG_COMPRESSED_PAYLOAD_* to allow building the board in
    abuild with a payload. Trivial
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17e27509a0a5605f2ab411b65d4aff6dad229c50
Author: Peter Stuge <peter@stuge.se>
Date:   Thu Apr 12 00:28:32 2007 +0000

    Fix two boards broken by the large patches of late.
    
    artecgroup/dbe61
    Add CONFIG_COMPRESSED_PAYLOAD_NRV2B to Options.lb since it's used in
    Config.lb.
    Change default for CONFIG_PCI_ROM_RUN to 1 so VGA ROM can run.
    
    technologic/ts5300
    Removed CONFIG_CONSOLE_VGA, the embedded board has no VGA without the
    development addon card anyways.
    Changes to target Config.lb so it actually builds.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b615c7bb3a01a1a3bfefb9f9e882c762ca4e19bd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Apr 12 00:12:41 2007 +0000

    Vendor specific patch, thus self-acked.
    
    * going back to old board specific dsdt for agami aruma.
      This is hopefully dropped again some day, but until then
      here's a working solution.
    * Some minor Agami specific changes.
    * drop obsolete bringup workaround hyperclocking.diff
    * increase image size again, x86emu wants it.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f7b1deca3829acb3f6d2912e24900292b1b8d6e
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 11 23:38:50 2007 +0000

    Config file update for Agami Aruma board.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f43cb68606443b6d0f74d63ebe652f869fdded93
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Apr 11 23:36:02 2007 +0000

    Trivial patch: Make buildrom a little bit more verbose.
    It shows the remaining space in an image now.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 78b5e37e8c086696594cd05edf0c4fd9527aa1fc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Apr 11 23:31:45 2007 +0000

    Rename flash_rom.c to flashrom.c. The tool is called 'flashrom' after
    all.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 46d65e85a1c0449f86497264d5958b3d85784767
Author: Jeremy Jackson <jerj@coplanar.net>
Date:   Wed Apr 11 18:44:42 2007 +0000

    Jeremy Jackson wrote:
    I'm guessing nobody has tried compiling it with 64bit userspace?
    
    Patch makes it compile cleanly and stops a "SEGV instead of working"
    issue.
    
    I also added a few checks for errors on system calls.
    
    Signed-off-by: Jeremy Jackson <jerj@coplanar.net>
    
    Reworked and
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4880353e03c62baacecaf634bc66c91be423f853
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Apr 9 22:59:22 2007 +0000

    flashrom: Add VIA CX700 to the list of supported southbridges (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6d7a1152c756a7e497536046bfb8619c8aa377b
Author: Roman Kononov <kononov@dls.net>
Date:   Mon Apr 9 22:50:12 2007 +0000

    This patch corrects r2587. It makes sure that the VGA is initialized
    when CONFIG_CONSOLE_VGA==0 and CONFIG_PCI_ROM_RUN==1
    
    Signed-off-by: Roman Kononov <kononov@dls.net>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e5cc9dcd03ef8705e5db462229f24be0e3dce9a
Author: Randall Philipson <rtphilipson@cox.net>
Date:   Mon Apr 9 22:27:45 2007 +0000

    add support for CX700 builtin southbridge
    Signed-off-by: Randall Philipson <rtphilipson@cox.net>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24cc7bf4366a9ba49a895d31c151dfba937c3827
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Apr 7 13:27:14 2007 +0000

    increase image size for abuild (trivial)
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0888c3613cec67642fb8d46055991ddaa06fb902
Author: Peter Stuge <peter@stuge.se>
Date:   Sat Apr 7 09:17:00 2007 +0000

    Fix epia-m build after u8/u16/u32 changes in Yh Lu's patch.
    
    Signed-off-by: Peter Stuge <peter@stuge.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 00a018f5118a999f1948a09a389fc9a0edd8bc5a
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Fri Apr 6 21:06:44 2007 +0000

    YhLu's patch from January 18th.
    
    hypertransport specific updates
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da38d60a708bea7e981d70e42f69b6e625a98178
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Fri Apr 6 20:59:54 2007 +0000

    This commit is part of YhLu's patch from January 18th.
    
    Drop a lot of debugging code from northbridge.c
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 75812a66bba98547683935c51d52dc25684ead85
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Fri Apr 6 20:58:37 2007 +0000

    YhLu's patch from January 18th. This part is mostly cleaning up
    dead code and adding a few fixmes.
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 47cb7c71c9c0296152fe573a88d81a080c61c334
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Fri Apr 6 20:27:40 2007 +0000

    next part of YhLu's large patch. I am not sure whether the tables.c
    changes are correct. If someone could look into this, thank you.
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ad9a2c63ef9e898600a71ce071228a6323afb2ac
Author: Ed Swierk <eswierk@arastra.com>
Date:   Fri Apr 6 20:01:44 2007 +0000

    Disable USB console on the m57sli for now.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c29b546eb128439ccbbfa4d99ea9f118793042ac
Author: Yinghai Lu <yinghai.lu at amd.com>
Date:   Fri Apr 6 19:59:11 2007 +0000

    Part IV
    
    Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
    Signed-off-by: Ed Swierk <eswierk at arastra.com>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ward Vandewege <ward at gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 30b4abeedc98db5a607f434af67e2fe2626ef111
Author: Yinghai Lu <yinghai.lu at amd.com>
Date:   Fri Apr 6 19:57:42 2007 +0000

    Part III of YhLu's patch from January 18th
    
    Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
    Signed-off-by: Ed Swierk <eswierk at arastra.com>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ward Vandewege <ward at gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3cf00e4bab084a231cbd7cafab3c02342c400e0
Author: Yinghai Lu <yinghai.lu at amd.com>
Date:   Fri Apr 6 19:51:02 2007 +0000

    two more directories from YhLu's mcp55 megapatch.
    
    Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
    Signed-off-by: Ed Swierk <eswierk at arastra.com>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ward Vandewege <ward at gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 21332b80d09adac3e6bb54c92e2a5e19db86a784
Author: Yinghai Lu <yinghai.lu at amd.com>
Date:   Fri Apr 6 19:49:05 2007 +0000

    This is part of the outstanding mcp55 commit from January 18th. It will
    likely break the build, since it is only a small part, but it needs to
    go in at some point and doing it directory by directory makes things
    easier.
    
    Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
    Signed-off-by: Ed Swierk <eswierk at arastra.com>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Ward Vandewege <ward at gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 778a42b129aef01be41633051b494e4462588e6b
Author: Roman Kononov <kononov195-lbl@yahoo.com>
Date:   Fri Apr 6 18:34:39 2007 +0000

    This patch makes sure that VGA is initialized before it is used. Without
    this fix, LinuxBIOS crashes if the CONSOLE_LOG_LEVEL is high enough.
    
    Additionally, The VGA option rom will be executed if either
    CONFIG_PCI_ROM_RUN=1 or CONFIG_CONSOLE_VGA=1.
    
    Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba43064d3276f3c96bb057ecdfd293cb2ae11a97
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 6 12:14:51 2007 +0000

    Trivial patch:
    
    * Drop empty file (0 bytes) northbridge/amd/amdk8/cpu_rev.c
      and references to it.
    * move config option decision to preprocessor instead of code
      since config options can not change during runtime
    * slightly more verbose output in built_opt_tbl.c
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03cafbfdfe10d6797740c4456fd3a80c499e1c0b
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Apr 6 11:58:03 2007 +0000

    Trivial (cosmetic) cleanup:
    * Only open /dev/mem once and do it early.
    * Drop extern for function prototypes.
    * Minimize ts5300 impact in probe_flash()
    
    This cleanup will making ICH7 SPI support quite some easier.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8944499617828164dff09203e5a259f1bb517399
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Apr 5 19:58:29 2007 +0000

    Fix typo, add datasheet info, minor cosmetic fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e775edc4cb3b6c202f1553b86159f5c993acbe5d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Apr 5 18:53:37 2007 +0000

    Coding style and cosmetics (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a01d0ea87c47d92eb139c0ca3f428e617c1049e7
Author: Corey Osgood <corey_osgood@verizon.net>
Date:   Thu Apr 5 18:48:21 2007 +0000

    Add early serial support for the Fintek F81705F Super I/O.
    
    Signed-off-by: Corey Osgood <corey_osgood@verizon.net>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8c64378112fd61a698d545562dfbafaa353243d
Author: Luc Verhaegen <libv@skynet.be>
Date:   Wed Apr 4 22:45:58 2007 +0000

    flashrom: split flash_enable.c into chipset_enable.c and board_enable.c
    
    This splits up the ROM Write enable code into chipset specific and
    board specific parts. This of course means that a lot of code is
    plainly moved about.
    
    * Allows for linuxbios name matching and pci-subsystem id matching.
      The latter uses a double set to properly distuinguish boards despite
      of some known vendors being lax about it.
    * Fixes GPIO15 being raised on every VT8235 southbridge, regardless of what
      that line actually controls; rom on EPIA-M, backlight on mitac 8999 laptop.
    * Adds flashrom support for Asus A7V400-MX (KM400 + VT8235)
    * Island aruma was renamed agami aruma, the board specific code now got
      adjusted. A set of pci-ids was retrieved from source code.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17d667b411685de57ea181cc496b29fea6d27d91
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Apr 3 10:45:53 2007 +0000

    Add initial framework for the Tyan S1846.
    
    It's not fully working, among other things because the Intel
    440BX northbridge isn't working, yet.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23d1e35d4d2fd25c710c5b54bfe171d8d2db0cea
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Apr 2 16:57:32 2007 +0000

    The *_early_serial.c pre-RAM code should do just that -- enable the serial
    port(s), and nothing else. The code in superio.c will initialize the
    rest when RAM is available...
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cbef76ecf3b991a17549f36b09e73d0a103e6f13
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Apr 1 20:00:32 2007 +0000

    Drop useless and partly even incorrect comments (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 195237f2e1b42c144cb27fde0a6773b20c8cd01a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Apr 1 19:44:21 2007 +0000

    Coding style fixes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a9c892d58c746aef0cb530481c214e63a6a6871
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Apr 1 17:24:03 2007 +0000

    Initial Intel 440BX RAM initialization framework.
    
    This does _not_ fully work, yet. You will _not_ be able to boot any
    payload with this code, yet.
    
    Add missing license headers.
    
    Base the northbridge.c file on the Intel 855PM version, that comes
    closer to what we want.
    
    The raminit.c file is written from scratch and hardcodes several
    values for now. This needs to be fixed later by reading the
    correct values via SPD.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d9d0bae8ac4ca1dce6bcdd549290b5b47fa37b1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Mar 31 19:48:38 2007 +0000

    Flashrom: Add support for the ICH7-DH southbridge (untested).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a66263ff69f1098ee665371240cb3ef873dfff1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Mar 31 19:45:24 2007 +0000

    Add support for the NSC PC87309 Super I/O.
    
    Pre-RAM serial output on COM1 and COM2 has been tested. The rest is not
    yet tested on real hardware.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5445639f06312f01dce1ac0d8335f0d66104c604
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Mar 22 14:51:45 2007 +0000

    This is a trivial cosmetic fix. Without it, the error message might look like:
    Image size doesnt match: Success
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 999bc60d5fb76f557c94ff55d753773cdc6bfa1c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Mar 20 13:43:50 2007 +0000

    fix a stupid cut and paste error.
    
    This is pretty trivial, as it was correct in the original non-CAR code.
    Suddently, CAR works nicely.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36b601ca3cd46344f844b7ef8fb304958d4091ad
Author: Corey Osgood <corey_osgood@verizon.net>
Date:   Sat Mar 17 14:00:23 2007 +0000

    Add initial pre-RAM serial output support for the VIA VT82C686(A/B)
    southbridge (with integrated Super-I/O).
    
    Signed-off-by: Corey Osgood <corey_osgood@verizon.net>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Corey Osgood <corey_osgood@verizon.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 681d7887f4f166a970d690b7321ec88cc4d024a7
Author: Ed Swierk <eswierk@arastra.com>
Date:   Tue Mar 6 23:49:49 2007 +0000

    The attached patch adds additional PCI IDs for MCP55 LPC devices to
    flashrom. 0x0360 is needed to support the DFI LANParty NF590SLI, and I
    am deducing the others based on pci_ids.h in the Linux kernel.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b515cbaf4ba0092359f16a2ae00a8488cecd9f2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Mar 3 15:01:29 2007 +0000

    Document POST codes emitted by LinuxBIOSv2.
    
    The list was created by Richard Smith <smithbone@gmail.com>, see
    http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/74.
    
    It is probably not complete, yet.
    
    (Closes #74)
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 47ce57acd769a0ec6858402fdf9900d69ab51592
Author: Luc Verhaegen <libv@skynet.be>
Date:   Fri Mar 2 22:16:38 2007 +0000

    flashrom: Fix wrong VT8235 flash enable failed warning.
    
    * Fix harmless but worrying warning where the return value of
      pci_write_byte is misinterpreted.
    * Hash together VT8231 and VT8235 code into VT823x. VT8231 is the better
      implementation, but lacked the write protect disable code that's
      apparently needed for VT8235.
    
    Signed-off-by: Luc Verhaegen <libv@skynet.be>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a81bb03b797ed5ed35e874692526482cdcb7c12f
Author: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Date:   Fri Mar 2 14:21:09 2007 +0000

    This patch splits console.c into 3 different files to get a better
    overview of the code, facilitate future cleanups and reduce the
    diff to Yinghai's tree at the same time.
    No functional changes, only moving lines between files.
    Copyright headers will be added later. Right now we benefit from
    keeping the diff as small as possible.
    
    Most of the work was done by Yinghai Lu.
    
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 412b8675c32bdd11723460a0b746cda5198f5995
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Mar 2 12:29:40 2007 +0000

    Add missing it8716f_early_init.c file, which got lost in the commit of
    http://www.openbios.org/pipermail/linuxbios/2007-February/018330.html
    in revision 2559.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53b9c1e798c00b790d346d8460c5a216d851af09
Author: David Hendricks <david.hendricks@gmail.com>
Date:   Fri Mar 2 02:25:36 2007 +0000

    Add Winbond W39V080A support to Flashrom.
    
    Signed-off-by: David Hendricks <david.hendricks@gmail.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 811f5c10eed458dab58cb2fcea5c95b2851ab353
Author: Ward Vandewege <ward@gnu.org>
Date:   Wed Feb 28 21:50:15 2007 +0000

    Add support for the Gigabyte m57sli-s4 board to flashrom.
    
    Signed-off-by: Ward Vandewege <ward@gnu.org>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d57241fab5d4b941f72811a9ce9edafca3993ba1
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Wed Feb 28 11:17:02 2007 +0000

    This is (most of) the usb2 debug console code ripped out of
    Uwe's version of yh_rest_of_patch.patch (13.02.07 - [PATCH]
    Rest of huge MCP55 patch).
    
    I dropped a lot of stuff, like broken indenting, removed copyright messages,
    and this printk_ram_* stuff (what the heck is this supposed to be)
    
    This codebase is really a mess. Further tarball contributions without a
    _CLEANED UP_ patch will be denied, especially if they are not from an up to
    date svn tree.
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f5411cfca8e1b4552e13a3a286358e917bb5382
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Feb 27 22:21:59 2007 +0000

    Add a note that the resulting LinuxBIOS images are licensed under the
    terms of the GPL, version 2 (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e6fdf9707519caf41db2a15a72a1ca98415c2d5c
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Feb 27 14:11:18 2007 +0000

    This is another fixup round for Yinghai Lu's great patch.
    
    It does the ROM_STREAM -> PAYLOAD rename that afaik was done after
    Yinghai sent his work to legal, so it is required to get that code
    building.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 72e87062f494d90bc61c0ea15c05539ce109df9a
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Feb 26 13:52:42 2007 +0000

    List more possible payloads in the README (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2a3223952e1e560bd59f841c22f8a3a23aa7c7da
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Sat Feb 24 17:39:11 2007 +0000

    Improve ITE IT8716F support.
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e15c4ca5ca4f32779a0bcf355f817276fe7022ab
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Feb 24 15:18:22 2007 +0000

    Remove unused defines.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a20213dde1b40415f127a344416cb45a1115a61
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Feb 19 19:11:20 2007 +0000

    Fix some CHIP_NAME() entries to use canonical names.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7014ef83b90a566298bfb57e335eb8d46f246d92
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Feb 17 17:08:13 2007 +0000

    Fix typo (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4bdbb428182c6acb0c745abd8780ef8b153a11f1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Feb 17 16:24:41 2007 +0000

    Move HOWTO/ into documentation/ where it belongs (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f55b58d53362426ed09c094de6548aa1ca7afd23
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Sat Feb 17 14:28:11 2007 +0000

    Initial support for the following new mainboards:
    
    * Nvidia l1_2pvv
    * Gigabyte m57sli
    * Supermicro h8dmr
    * Tyan s2912 -- with HTX
    
    The boards will currently _not_ compile, two further patches
    from Yinghai Lu are still missing. Please be patient :)
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3ecf5002b38525f1b991a21602dde39f1a859f75
Author: Ed Swierk <eswierk@arastra.com>
Date:   Fri Feb 16 14:36:12 2007 +0000

    Currently the flashrom Makefile tries to detect whether pciutils-devel
    is installed, but the test also fails if zlib-devel is missing. This
    patch changes the error message accordingly.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb1fddbab87b5ad5acc57415e25613655722b51b
Author: Bingxun Shi <bingxunshi@gmail.com>
Date:   Fri Feb 9 00:26:10 2007 +0000

    Add support for the MSI K9ND Master Series (ms9282) board.
    
    Signed-off-by: Bingxun Shi <bingxunshi@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4020dd5ac52132cd717631e9131286856051fa63
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Feb 6 19:53:51 2007 +0000

    Include src/include/boot/linuxbios_tables.h in the flashrom source
    tree to make it compilable independant of the LinuxBIOS source code.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f9cf1373c6b9431fd6b84571237a8dee2ab93cd
Author: Adam Kaufman <adam.kaufman@pinnacle.com>
Date:   Tue Feb 6 19:47:50 2007 +0000

    This patch is a rework of Adam Kaufman's Solaris patch.
    
    * flash.h:
      - add a license header
      - add system definitions
    * flash_enable.c:
      - put io priviledge access in one single place
      - add includes required for Solaris.
    * lbtable.c, flash_rom.c, 82802ab.c:
      - use MEM_DEV so it works on Solaris
    * sst49lfxxxc.c, sharplhf00l04.c, sst_fwhub.c, 82802ab.c
      - drop unneeded include to sys/io.h
    * Makefile
      - adapt to Solaris specifics.
    
    Signed-off-by: Adam Kaufman <adam.kaufman@pinnacle.com>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Adam Kaufman <adam.kaufman@pinnacle.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc7ceb1fd1473f0338fee8140356f130d0b615ba
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Sat Feb 3 15:28:20 2007 +0000

    Add support for the Winbond W83627EHG Super I/O.
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Bingxun Shi  <bingxunshi@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c5708d19fd3fc00df9f1cd18a9db93742acc70df
Author: bxshi <bingxunshi@gmail.com>
Date:   Sat Feb 3 15:23:34 2007 +0000

    Nvidia MCP55 uses CMD to send/receive bytes instead of DAT0,
    that's the same as broadcom/bcm5785.
    
    Signed-off-by: bxshi <bingxunshi@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit de7f81f48a35cf09eb661e3da3a92b35d3c61aee
Author: Roman Kononov <kononov195-lbl@yahoo.com>
Date:   Sat Feb 3 10:43:48 2007 +0000

    This eliminates an illegal and annoying warning.
    
    'rom' is the current read pointer.
    'rom_end' points to last valid byte of the stream.
    
    Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 958a1f308a272cb0fcb0e280e2815893a86df457
Author: Roman Kononov <kononov195-lbl@yahoo.com>
Date:   Fri Feb 2 22:40:10 2007 +0000

    I have Sun Ultra40 workstation. Southbridge is nVidia CrushK8-04/nforce
    2200 (too many names, sounds like a criminal).
    
    1) Linuxbios loads kernel A; kernel A loads kernel B. Everything works
    fine.
    
    2) Then I push the reset button.
    
    3) Linuxbios loads kernel A; kernel A loads kernel B. Kernel B complains
    about wrong checksum of the mptable and crushes later.
    
    An investigation showed that in 3), short after kernel A (v2.6.19.2)
    sets
    the Bus Master Enable bit of the nVidia's USB1 controller
    (pci_set_master()),
    the mptable gets two bytes at physical address 0x80 damaged.
    
    Nothing is plugged to the USB ports. Other two Sun workstations had the
    same
    behavior. This does not make sense to me unless the controller has a HW
    bug.
    
    I believe, this should better be fixed in the kernel USB driver.
    
    For now this patch offers a possibility for linuxbios to reset the USB
    controller by setting HostControllerReset bit in HcCommandStatus
    Register.
    It is enablead by using 'register "usb1_hc_reset"="1"' in 'chip
    southbridge/nvidia/ck804' section of the mainboard's Config.lb.
    
    Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ff54db47fd116b8b460fa1453623dea487fb0234
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Feb 2 17:08:04 2007 +0000

    Remove hardcoded gcc versions otherwise the build will break for
    most people.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 18878e036f4f111ace50e1ff540b5deab63f20d9
Author: Ed Swierk <eswierk@arastra.com>
Date:   Thu Feb 1 22:43:27 2007 +0000

    Fix typo which breaks the build ('defalut' should be 'default').
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3aaf6a99e98734e3e21d0fb248da85c3007aa2c
Author: Ed Swierk <eswierk@arastra.com>
Date:   Thu Feb 1 01:53:55 2007 +0000

    This patch adds the MCP55 PCI IDs (without which the southbridge code
    won't compile), and breaks an unnecessary dependency on the usbdebug
    code.
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57e700f4f467afdad89e75820a7fae47f6b8b7ae
Author: Roman Kononov <kononov195-lbl@yahoo.com>
Date:   Thu Feb 1 00:44:27 2007 +0000

    great check-in message:
    
    Linuxbios boots an Opteron motherboard with 1GB memory.
    
    Linuxbios directly loads a recent linux kernel.
    The memory layout is like this:
    
    BIOS-provided physical RAM map:
       BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
       BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
       BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
       BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved)
       BIOS-e820: 00000000000f0400 - 0000000040000000 (usable)
    
    The f0000-f0400 region contains IRQ and ACPI tables.
    
    At some point the kernel builds a resource table containing
    all physical address ranges and type of hardware the addresses
    are mapped to. The table is accessible via /proc/iomem:
    
    # cat /proc/iomem
    00000000-00000e17 : reserved
    00000e18-0009ffff : System RAM
    000a0000-000bffff : Video RAM area
    000c0000-000cbfff : Video ROM
    000f0000-000fffff : System ROM
    e0000000-efffffff : PCI Bus #03
        e0000000-efffffff : 0000:03:00.0
    f0000000-f3ffffff : GART
    f4000000-f60fffff : PCI Bus #03
        f4000000-f4ffffff : 0000:03:00.0
        f5000000-f5ffffff : 0000:03:00.0
        f6000000-f601ffff : 0000:03:00.0
    f6100000-f6100fff : 0000:00:01.0
    f6101000-f6101fff : 0000:00:02.0
        f6101000-f6101fff : ohci_hcd
    f6102000-f6102fff : 0000:00:04.0
    f6103000-f6103fff : 0000:00:07.0
        f6103000-f6103fff : sata_nv
    f6104000-f6104fff : 0000:00:08.0
        f6104000-f6104fff : sata_nv
    f6105000-f6105fff : 0000:00:0a.0
    f6106000-f61060ff : 0000:00:02.1
    f6200000-f620ffff : 0000:40:01.0
    
    As you can see, the 00000000000f0400-0000000040000000
    region is not listed.
    
    It is not listed because the kernel unconditionally adds
    "000f0000-000fffff : System ROM" first (look for
    "request_resource(&iomem_resource, &system_rom_resource)"),
    and then the attempt to add f0400-40000000 range fails
    because of overlapping.
    
    The kernel does not care that the range is not listed there.
    Kexec does. It uses the /proc/iomem file to instruct the
    kexec system call how to place the segments of a new kernel
    in the physical memory. Kexec fails to start a new kernel
    because it cannot locate enough physical memory.
    
    This must be fixed either in linux or linuxbios.
    
    Assuming that linuxbios is to be fixed, I cooked a patch
    which provides this memory layout:
    
    BIOS-provided physical RAM map:
       BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
       BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
       BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
       BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
       BIOS-e820: 0000000000100000 - 0000000040000000 (usable)
    
    The /proc/iomem contains:
    
    # cat /proc/iomem
    00000000-00000e17 : reserved
    00000e18-0009ffff : System RAM
    000a0000-000bffff : Video RAM area
    000c0000-000cbfff : Video ROM
    000f0000-000fffff : System ROM
    00100000-3fffffff : System RAM
        00100000-00203c61 : Kernel code
        00203c62-00248c3f : Kernel data
    e0000000-efffffff : PCI Bus #03
        e0000000-efffffff : 0000:03:00.0
    f0000000-f3ffffff : GART
    f4000000-f60fffff : PCI Bus #03
        f4000000-f4ffffff : 0000:03:00.0
        f5000000-f5ffffff : 0000:03:00.0
        f6000000-f601ffff : 0000:03:00.0
    f6100000-f6100fff : 0000:00:01.0
    f6101000-f6101fff : 0000:00:02.0
        f6101000-f6101fff : ohci_hcd
    f6102000-f6102fff : 0000:00:04.0
    f6103000-f6103fff : 0000:00:07.0
        f6103000-f6103fff : sata_nv
    f6104000-f6104fff : 0000:00:08.0
        f6104000-f6104fff : sata_nv
    f6105000-f6105fff : 0000:00:0a.0
    f6106000-f61060ff : 0000:00:02.1
    f6200000-f620ffff : 0000:40:01.0
    
    Kexec is happier with the patch.
    
    Regards,
    
    Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0980049a629acea1c069f19bede02b5d5a2feab7
Author: Roman Kononov <kononov195-lbl@yahoo.com>
Date:   Thu Feb 1 00:40:51 2007 +0000

    This fixes a small typo.
    
    Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c65bd562a8653cdf7e273917a9f5dcea1f5f99b7
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Thu Feb 1 00:10:05 2007 +0000

    Add support for the NVIDIA MCP55 southbridge.
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Yinghai Lu <yinghai.lu@amd.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 097d9a2d57fce2bd1bbe0d9c3628b75c1a25a934
Author: Alan Carvalho de Assis <acassis@gmail.com>
Date:   Sat Jan 27 13:39:06 2007 +0000

    Add support for the SST 49LF160C.
    
    Signed-off-by: Alan Carvalho de Assis <acassis@gmail.com>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e4ee4f5045f752b2189fb47155e76db69e234f0
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Jan 24 11:09:03 2007 +0000

    Delete superfluous and incorrect comment (trivial).
    See also http://www.openbios.org/pipermail/linuxbios/2007-January/018042.html.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 298f89850d009b2e7caf9739814f0aa16a143d13
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Mon Jan 22 20:21:17 2007 +0000

    Add support for the SST-49LF004C, SST-49LF008C, SST-49LF016C in flashrom.
    Also add suport for NVIDIA MCP55.
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Peter Stuge <peter@stuge.se>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a5bc46579719205967ba3acbeea765a6a4c2356
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Jan 17 10:57:42 2007 +0000

    trivial enhancement
    * add fintek superio support
    * add license header
    * add clean target in makefile
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96206510e3076859b16c20ebba1a84d989f4a48d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Jan 16 11:56:35 2007 +0000

    Change 'ram' to 'RAM' in user-visible output (closes #60).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9095e30f2dbac3c53a380a20d15d4698449dab20
Author: Jon Dufresne <jon.dufresne@gmail.com>
Date:   Thu Dec 28 12:00:58 2006 +0000

    A patch to add initial support for the i82801db southbridge based
    heavily on the code for i82801dbm and i82801er
    
    Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a5fc22fd6b45e96534802dd1069060990f4077ff
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Wed Dec 20 20:21:05 2006 +0000

    htx card on io apic on htx slot of dk8_htx
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Acked-by: Yinghai Lu <yinghai.lu@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c3874e8f880d6d9e4f3012d38ddd1f34ff2ec18
Author: Yinghai Lu <yinghai.lu@amd.com>
Date:   Wed Dec 20 20:15:33 2006 +0000

    ck804 pref mem 4G above support
    
    Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
    Acked-by: Yinghai Lu <yinghai.lu@amd.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c2c86465849189b267de215bad3d9109f5740e15
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Dec 20 14:59:56 2006 +0000

    Improve flashrom description in the manpage a bit (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7adaa11dcf6d4dbd62af182901bac487491767be
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Dec 20 14:53:22 2006 +0000

    Update flashrom requirements in the README (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be13dc72d91bd3c5791fb2a3a18ee610860404ee
Author: Ed Swierk <eswierk@arastra.com>
Date:   Fri Dec 15 12:56:28 2006 +0000

    Apply linuxbios-rename-other-payload-options.patch
    (Patch 2, refs #14)
    
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8bb1dc5c776699d2037923c6594e2e998c7bec09
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Dec 15 11:55:58 2006 +0000

    ouch. always abuild with payloads! trivial fix.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a7a5b49c570bf4a183178327c77ed4828d25416
Author: Ed Swierk <eswierk@arastra.com>
Date:   Fri Dec 15 11:42:16 2006 +0000

    Apply linuxbios-rename-compressed-payload-options.patch, refs #14
    Signed-off-by: Ed Swierk <eswierk@arastra.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 208948787ec767dcdd2443a89f312bfba00ea2cc
Author: Jon Dufresne <jon.dufresne@gmail.com>
Date:   Thu Dec 14 14:54:00 2006 +0000

    In the file mainboard/intel/i82801dbm/i82801dbm.c the variable
    southbridge_intel_i82801dbm_control should be named
    southbridge_intel_i82801dbm_ops. Otherwise a compile error occurs if this
    device is included in Config.lb of the mainboard.
    
    Closes #62
    
    Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af433f2197671cd02adb29305cce91c57c0438db
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Dec 14 14:26:46 2006 +0000

    Add support for the SMSC FDC37M60x Super I/O (tested on FDC37M602).
    
    Serial output on serial port 1 is tested and works, the rest probably not yet.
    
    Closes #59.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abad5ef8540dee99cb3ac6778ebf079409254da2
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Dec 14 00:59:41 2006 +0000

    Add an install target to the flashrom Makefile which installs flashrom
    into /usr/local/bin. Closes #54.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3938bbbbfc59042c014910ed93e939185d511a8
Author: chn <chn@virtutech.se>
Date:   Thu Dec 14 00:43:50 2006 +0000

    In src/southbridge/intel/i82801ca, first the smbus registers are mapped at i/o
    space offset 0x1000, and later is the acpi registers also mapped at 0x1000.
    This patch fixes this behavior. Closes #44
    
    Signed-off-by: <chn@virtutech.se>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a522df039b3085004dbff39fec675039d57b1fab
Author: Jon Dufresne <jon.dufresne@gmail.com>
Date:   Thu Dec 14 00:40:09 2006 +0000

    Add mtrr support for pentium m cpus
    
    For cache to work the x86_setup_mtrrs() must be called.
    
    Closes #61
    
    Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0fac1e56d70b048309d0406a92b8bf2e8253ca78
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Thu Dec 14 00:31:38 2006 +0000

    This is a typo that went into one of the abuild files. it will break abuild
    on this board for everyone but me. Closes #58
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de> (trivial patch)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 218e7ed10a6456f128ccd344b074b86ba2c65251
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Dec 5 15:27:46 2006 +0000

    Use the common LinuxBIOS license header (trivial). Refs #5.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d82baa1a2e9a10fc74e225cc9d472a8cf742dfa7
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Dec 5 14:13:10 2006 +0000

    Add missing license headers to some files (info based on svn history).
    
    Adapt some existing license headers to use the common LinuxBIOS
    format. Please note that this does not make any qualitative
    license changes, merely cosmetic syntax changes (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2519 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fe6d118b089848c2f1676e7e828901fffdbef2cf
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Dec 4 08:20:40 2006 +0000

    Update list of supported flash chips in the flashrom README (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6104bd1634a62ac42ec5f208b4cf15ec17767289
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Dec 4 08:15:47 2006 +0000

    List the supported flash chips and southbridges in the flashrom
    README file (trivial).
    
    Closes #52.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc95add598ca7d75b85b30394c1b8d9f6ea8e3a8
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Dec 3 23:46:36 2006 +0000

    Remove
      #include <device/device.h>
    from all *_early_serial.c ITE Super I/O files, as arch/romcc_io.h already
    #defines device_t, thus adding device/device.h breaks the build (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2516 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5718338edb0714e7eb737dd34e6a13e969cc4070
Author: Eric Biederman <ebiederman@lnxi.com>
Date:   Sat Dec 2 16:48:48 2006 +0000

    fix romcc preprocessor bug
    Signed-off-by: Eric Biederman <ebiederman@lnxi.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2a44fbf2a014f48aceb3e601a391c7377d346caf
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Dec 1 15:25:21 2006 +0000

    Status update (trivial).
    
    See http://www.linuxbios.org/pipermail/linuxbios/2006-November/017195.html
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6b2475dd8198f3f6b43b96d48b2f4e3de75042a4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Dec 1 13:14:55 2006 +0000

    Explicitly set the CLKIN to 24 MHz on all ITE Super I/Os, otherwise
    serial output might not always work correctly (trivial).
    
    Thanks Philipp Degler <pdegler@rumms.uni-mannheim.de> for testing and
    reporting this issue.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39b13f4fa0b17b496ded754b875213b72d951129
Author: Jon Dufresne <jon.dufresne@gmail.com>
Date:   Fri Dec 1 09:41:11 2006 +0000

    Add missing #includes to some ITE Super I/O files.
    
    Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d91ecb8764072e31520cea3fc464c1ae3782489
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 30 21:26:45 2006 +0000

    Add convenience macros PAM0..PAM6 (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e2436360b9870f8ecde93e26d06f19139781932
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Mon Nov 27 16:32:49 2006 +0000

    add Config.lb files for abuild. This fixes both boards (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eba69b60781262da7503bb394940ac84429aaf29
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 26 19:07:20 2006 +0000

    Cosmetic fix of the nova4899r CHIP_NAME().
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3e15652a103bbe703064e3beea6171c58ca2a5e1
Author: Luis Correia <luis.f.correia@gmail.com>
Date:   Sun Nov 26 19:05:16 2006 +0000

    Add support for the IEI NOVA-4899R 5.25 SBC mainboard (patch submitted by
    Luis Correia <luis.f.correia@gmail.com>). The code is loosely based on
    the Eaglelion 5bcm mainboard.
    
    Warning: this is work in progress!
    
    As of now, it does boot with serial console only (no vga), and two ethernet
    cards work sometimes. This has to do with the IRQ assignments, which are a
    complete mess. USB is now apparently working, but I can't make any device
    to be recognized.
    
    The PCI slot is still unusable due to the IRQ thing.
    
    Audio, other serial ports, irda, floppy and paralell port support is
    unknown aka untested yet.
    
    (closes #32)
    
    Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
    Acked-by: Acked-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2508 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98b75f0e2426c3a0ced242b07bb1afdde0bb5f18
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 22 15:27:29 2006 +0000

    Fix location of the bug tracker in the manpage (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 998a57c477cf8d73754da3bfe1b3091aa0f88477
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 22 11:41:32 2006 +0000

    Update of the src/include/spd.h file with the following improvements:
    
     * Added information on the relevant datasheet(s) and where to get them.
     * Added missing #defines for some other config bytes.
     * Documented all config bytes a bit better.
     * Renamed some #defines to hopefully make their names clearer.
    
    (closes #38)
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3ab63e1401a695883dd23156046a8ad50393b165
Author: Giampiero Giancipoli <gianci@email.it>
Date:   Wed Nov 22 00:29:51 2006 +0000

    apply patch from Giampiero Giancipoli <gianci@email.it>:
    
    Fixed write_page_write_jedec() in jedec.c. Added a check-reprogram loop
    in the same function, to come around the high page write failure rate on
    some boards.
    
    This patch includes the changes suggested by Ron to simplify the control
    flow.
    
    It also includes trivial changes by me to make flashrom build on newer
    systems (libpci needs libz now). I also made a small type case compile fix
    and proper return code handling in one or two places.
    
    Signed-off-by: Giampiero Giancipoli <gianci@email.it>
    Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 440d6f9f8a3417a9ed59fcbf223a5bc750bdf42d
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Nov 21 23:51:08 2006 +0000

    Add support for ASD AE49F2008
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de> (trivial patch)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a998642f553b5f280319ae9eddc66b19c3c8b89
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Nov 21 23:48:51 2006 +0000

    flashrom: Only write the flash if the image has the same size
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9e2019200f2316d5997e7593e7f4bae08c560541
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 21 15:09:05 2006 +0000

    Rename SM_ID to SYNCMOS_ID (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71d310fa9ef9848e4ba9a4714138ff8b3c9bee07
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 21 15:02:27 2006 +0000

    Add support for the SyncMOS S29C51001T, S29C51004T, and S29C31004T
    flash chips to flashrom (closes: #50).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d083e7927eb5cd6169c7dccc8580692fcee1cfbe
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Nov 20 20:32:35 2006 +0000

    Cosmetic fixes and typos (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0eb7424004525bf1776c25e16b58996bcd850395
Author: Giampiero Giancipoli <gianci@email.it>
Date:   Mon Nov 20 20:03:07 2006 +0000

    Support for the 256K SyncMos S29C51002T flash.
    
    Signed-off-by: Giampiero Giancipoli <gianci@email.it>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c22851011f21d6ec4d44172ed403b47e7d22171d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 19 19:24:06 2006 +0000

    Fix hardcoding of iasl path. iasl is in the user path in the
    pmtools packages of upcoming SUSE 10.2, too, so the problem will
    go away. (new package installed on linuxbios.org, too)
    
    See also
    http://www.linuxbios.org/pipermail/linuxbios/2006-September/015968.html
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed7bab8b0dabca6a3d8936b7b868e547c884006c
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Nov 11 18:46:38 2006 +0000

    Add missing bracket in comment, and fix whitespace (trivial).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca6312010da56b1e01e1b53f5f4305e96b4e11f5
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Fri Nov 10 13:30:28 2006 +0000

    * fix the automatic build system by compressing payloads if possible
      and leaving enough room for a real payload (not /dev/null)
    
      This is a wonderful example why "uses" sucks.
    
    * add Config-abuild.lb for those boards that dont build with
      the default settings and a real payload:
      arima/hdama, amd/quartet, amd/serengeti_cheetah, ibm/e326
    
    * if lzma is installed and a real payload is used, try compressing
      it.
    
    * fix a small bug in "abuild --help"
    
    This patch is acked by me because its due to infrastructural changes only.
    Flames welcome.
    
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c0defea8b60855302df680696b54f2112c2f649f
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Nov 10 09:04:12 2006 +0000

    Add an include file which contains the register definitions for the
    Intel 440BX northbridge (Closes #39).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Richard Smith <smithbone@gmail.com>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7980d8941ac80ce3aba5f42c5c1371c2c53e370
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Nov 7 13:48:46 2006 +0000

    Instead of checking the first byte only, the whole part is checked now. This
    will detect any improper erase, closes #31
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c65113cec7c628ab55f71114db5b13b2f2967db4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Nov 7 11:16:21 2006 +0000

    Fix some code comments of the Intel PIIX4/PIIX4E/PIIX4M code.
    Add detailed instructions on how and where to get the datasheet,
    its name, and order number (Closes #34).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 10fd79ae81fc97bded227ec587acfcdc895539db
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Tue Nov 7 10:22:20 2006 +0000

    Support for VIA VT82C686 in flashrom utility (trivial)
    closes #30
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 918a7cf8e4a81a79260d42d78815131619e46b6d
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Mon Nov 6 10:51:15 2006 +0000

    Fix bug in 'sed' invocation in abuild, which causes build errors in
    certain situations (Closes #22, refs #14).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7aa29b9436e1c3ddf367713720bc1e74667a1d4
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 5 18:50:49 2006 +0000

    Use the canonical name of the vendors/devices and the
    same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@linuxbios.org>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bdb50fe40a3b58993cecf91929a75e68a7408960
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sun Nov 5 18:26:08 2006 +0000

    Add support for Intel PIIX4/PIIX4E/PIIX4M-based mainboards to flashrom.
    Tested on real hardware, reading, detecting and writing various chips works.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a9e273593fd83ef78fd34d2e60a6606dada3b41c
Author: Luis Correia <luis.f.correia@gmail.com>
Date:   Sun Nov 5 12:18:58 2006 +0000

    Fix a typo in elfboot.c. Closes #27
    
    Signed-off-by: Luis Correia <luis.f.correia@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1549f2a557058000d65d913ffb8b60487bdc09ab
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Sat Nov 4 23:19:00 2006 +0000

    Various minor cosmetic changes in the ITE Super I/Os, mostly whitespace
    changes and fixing of comments.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit faea4c59abb37c80b530df0b5901eb3a89fb2dea
Author: bxshi <bxshi@msik.com.cn>
Date:   Thu Nov 2 16:02:33 2006 +0000

    Sorry, this is the last commit I will do this way, but MSI has waited a
    long time and I could not get into the tracker.
    
    These are patches to enable ms9185 support. Abuild passes.
    
    Signed-off-by: bxshi <bxshi@msik.com.cn>
    Acked-by: Ronald G. Minnich <rminnich@gmail.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c33b7b81e611526998d1b58b7177e7bdf63dacc
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Thu Nov 2 14:11:34 2006 +0000

    Remove some unneeded #includes from most mainboard.c files.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4c56c33ac345fcf93fbfa9321e2d536f0b10218
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 1 14:31:00 2006 +0000

    Adapt GPL license headers to match the current conventions.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6fb43c85f185e34dacb65f0b56dd1b4ee1c19cda
Author: Richard Smith <smithbone@gmail.com>
Date:   Wed Nov 1 14:21:31 2006 +0000

    drop unsupported unfinished mainboard Advantech SOM GX DB533-C
    
    Signed-off-by: Richard Smith <smithbone@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f28674ec3c3349640733effc6026e7148b447550
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Wed Nov 1 12:52:49 2006 +0000

    Rename some variables from *ITE* to *ite* for consistency reasons (refs #4).
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 700b38a0d545230d0802f8121b9da05549092533
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 28 16:03:37 2006 +0000

    small tracker test (trivial change). closes #3
    fix bug report address
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0caddbd4fe97998e45f3ca33caf06054fe4bfd50
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 28 16:00:24 2006 +0000

    Small tracker test (trivial change). closes #3
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f044ede24656e7cf52eb8baca647ed3db851c874
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Oct 27 18:22:13 2006 +0000

    This change fixes a long-standing bug, whereby we do not set ret for an
    un-inited vector, which we should have done.
    Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
    
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cf201870797d542915b2c52fa596b27c1616a821
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 27 11:40:01 2006 +0000

    svn mv src/northbridge/intel/E7520 src/northbridge/intel/e7520
    svn mv src/northbridge/intel/E7525 src/northbridge/intel/e7525
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 586470c646ac1b8753858b013b268f049a28b818
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 27 11:38:22 2006 +0000

    Rename E7520 to e7520, and E7525 to e7525 in the code. The next commit
    will then rename the E7520 and E7525 directories respectively.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e0e1d425274d5e2c90e19eec6ef125d1fffd73a1
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 27 11:30:27 2006 +0000

    Fix the CHIP_NAME() entries of all mainboards to have the same format
    and (hopefully) the correct canonical name of the vendor and board.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 733681583ca9bf96288df2449bb61cd69e3b9345
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 25 19:08:12 2006 +0000

    enhance web page (trivial)
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Closes #3
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a1405725e0faf41522d65b180e28574c249a008
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Wed Oct 25 19:02:34 2006 +0000

    support submitting tests to the test system in abuild. initial support.
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    Closes #3
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d6107410848dbdbb0aebb58d889dd0afa4cfcd9
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 24 23:08:10 2006 +0000

    Rename src/superio/NSC to src/superio/nsc.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d86417bfa379de85ba7a52ba626bbdfbed389438
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Tue Oct 24 23:00:42 2006 +0000

    Change all occurences of NSC to nsc in the code. The next commit
    will then rename the src/superio/NSC directory to src/superio/nsc.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f327e655ce3bb6f9569b57d7a5ab28a9eab18ca2
Author: Ronald G. Minnich <rminnich@lanl.gov>
Date:   Tue Oct 24 18:47:29 2006 +0000

    reduce verbosity on OLPC btest boards.
    
    Signed-off-by: Ronald G. Minnich <rminnich@lanl.gov>
    Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
    
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 814b458b633dcf478e9e375d0a3b741b3a153c0f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Oct 24 12:46:55 2006 +0000

    fix leftover typo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e5b6a82ad4ffe044d4eeeb9bd3b42c0d07579df
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Oct 24 09:40:21 2006 +0000

    fix typo during rename. Subversion would not let
    me fix this before committing first.
    
    Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9d6be3ec42fc0ad138150d988b3e400168318e2d
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Oct 24 09:37:04 2006 +0000

    fix naming convention, turn X.
    another commit is following
    Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
    Acked-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d8261d416c5333a4ff73e0980a5b7838a66e19b
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Oct 24 09:25:35 2006 +0000

    rename Iwill to iwill to keep naming scheme consistent
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b216e8fa653fd995b028060cf729f5e12fb5ffb2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Oct 24 09:23:23 2006 +0000

    remove DK8HTX, it's an old duplicate version of dk8_htx
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 107b8feb68021c6309595ecbeb5a273b870b0e6f
Author: stepan <stepan@coresystems.de>
Date:   Fri Oct 20 22:21:18 2006 +0000

    get rid of the border.
    Signed-Off-By: stepan@coresystems.de
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 10d55b47cfed19a1f796da77d02996d4a26ee754
Author: Uwe Hermann <uwe@hermann-uwe.de>
Date:   Fri Oct 20 21:50:01 2006 +0000

    Added a README file for LinuxBIOS.
    
    Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4225c84523aa6b4657f110b0ef74d0353932006
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Oct 19 19:08:00 2006 +0000

    add proper licensing information. thanks to Uwe Hermann.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2132f1a605383e9c7bc477a7f07c46035f455d12
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Oct 19 19:06:28 2006 +0000

    fix from Uwe Hermann:  updated patch to fix a wiki syntax bug in the output...
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd845a04a901475ad85472a94789c34f151cf541
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 18 16:00:10 2006 +0000

    add the CAFE IRQ support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69fd463a1b2f774ab0628737242d4b414635d327
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 18 15:46:24 2006 +0000

    add btest mainboard
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31101c9201a536146ac70429e1bd73502ad24527
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 18 15:23:28 2006 +0000

    add the btest mainboard
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0a3f60775baa549d559b9b89c4777efd43e0c81c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Oct 17 20:58:47 2006 +0000

    add xsl stylesheet for wiki table generation
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c1c3fdc79fab5b0d1572ea8f606c280b2df9676c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Oct 14 21:35:30 2006 +0000

    add ADLO to v2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ed51d19331945915d2a879d11d72a7d1a8751b7
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Oct 14 21:04:49 2006 +0000

    * add vt8237 support (Uwe Hermann)
    * add more MCP51 support (me)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a112bb0bca518692ba6413d5dd5c73234777d664
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Oct 13 21:48:38 2006 +0000

    s2895 failover build
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ab46b9026d8f0fe330ab1ab3dedb70a7e84acff
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Oct 13 20:10:09 2006 +0000

    return missed
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4bb8887ac447be339c4e84b03cca681392e48361
Author: Ronald G. Minnich <Ronald G. Minnich>
Date:   Fri Oct 13 19:58:52 2006 +0000

    change things that make no sense on ultra40. serial output now works!
    Signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c34e3ab71e79dc1acf5effcba2830241b2ff7f7e
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Oct 12 00:58:20 2006 +0000

    DK8 HTX with CAR and acpi, and easy support for HTX
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d3eabbd77c6724f2b8c5d610273af25e7655a1ee
Author: stepan <stepan@coresystems.de>
Date:   Mon Oct 9 22:35:45 2006 +0000

    replace table based crc with computational one. by Ed Swierk.
    X-Signed-Off-By: <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa8e3d409f5b59295aa5038c094e3ee3dd87d8d1
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 7 22:59:03 2006 +0000

    here's a small patch to add support for the SST 49LF020A to flashrom.
    by Uwe Hermann <uwe@hermann-uwe.de>
    X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b6a0a9fb8aacad62558a767b5de12b711e226dc0
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 7 00:23:51 2006 +0000

    Tiny patch to show the size of the detected flash part
    from Uwe Hermann <uwe@hermann-uwe.de>
    X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f694db93807fbda6d7ed60378f1046a1cdf3aa97
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 7 00:21:13 2006 +0000

    Fix flashrom for sst49lf080a and small print bug,
    by Roman Kononov <kononov195-lbl@yahoo.com>.
    X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebafa4df425445a63725ce23b7d40dab6d5e99cd
Author: Stefan Reinauer <stepan@coresystems.de>
Date:   Sat Oct 7 00:13:24 2006 +0000

    Add serial stream payload support from Ed Swierk <eswierk@arastra.com>
    X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 197a4a8dbbbb03f25fd43d652173517be3e37d59
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Oct 6 16:05:14 2006 +0000

    MEMCLK to DDRXXX
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7110f9261f455b9d88925b367536aa02071ac949
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Oct 5 06:59:56 2006 +0000

    K8_4RANK to QRANK
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab9f49d2fabe92ca79ec95888ca91969446ae756
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Oct 5 06:24:21 2006 +0000

    init.o
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1792b2e8011ce6e894d3b36b1d47d78411f5b0f8
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Oct 5 00:27:44 2006 +0000

    make ppc happy for console
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d74d76de46e733fa4866f47b58be60feb472f1f
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 4 23:57:49 2006 +0000

    get_bus_cong using sysconf instead
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d95465d08f5be0ec46fe3b1f801b98f7c5a43f81
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 4 23:09:09 2006 +0000

    add missed asl for ht chain
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31ed8983c3a87856c89791561e2a281beedfb3ba
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 4 22:57:26 2006 +0000

    qemu abuild fix
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f9624d211a247c032a31b22c3b47158f7083c9e
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 4 22:56:21 2006 +0000

    CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support in
    serengeti_cheeatah
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 93a5a194c5863262ed9b9fabc4cd40efcf1fddd9
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 4 21:05:23 2006 +0000

    failover_failover apc lds
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 15b8ea74735044bf6cd88b178ce0468e027aca7c
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 4 21:04:49 2006 +0000

    socket 939
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d22a5dc69f018f2861410e8628623537f009e2c
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 4 21:00:01 2006 +0000

    amdk8_sysconf
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4b278c02c1da92219ebeb34204b9768934aeca3
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 4 20:46:15 2006 +0000

    AMD Rev F support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e3757d11c565a8fe68dc2a2c34975e98304533c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Sep 25 09:15:52 2006 +0000

    rename abuild.sh to abuild.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3315c1fc2b8076bcaace1242b1d69ef246230d5
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Sep 24 23:02:26 2006 +0000

    clean up epia targets
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 984371554b8f937ce0cf068db3bf37633990fa6c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 21 20:55:58 2006 +0000

    add irq for keyboard and mouse
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0bece04105ce217cf9d15b44f76c2010ada5d328
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Sep 21 13:09:22 2006 +0000

    abuild manpage and other fixes from Uwe Hermann. Thank you!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ad85dbc65d884d82f2f9c9d4fa1c5cc3ab5dc42
Author: Ronald G. Minnich <Ronald G. Minnich>
Date:   Wed Sep 20 16:39:30 2006 +0000

    Lots of lx fixes. CLeanup mainly. THings now build
    Signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e8bfbb387cc6fea5155d4b67e2b222af167e20bc
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Sep 20 16:32:59 2006 +0000

    This driver is a mistake, removing it.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit efba85f00e16c541eb8205b8dbb5611dc18b9544
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 19 19:30:11 2006 +0000

    commit moire changes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 21acfcb0d515553cd9c6d42fbd48b458572c8fbe
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 19 17:38:57 2006 +0000

    add target
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f23b6cd7d97a25aecaa29adb5dcb39afa296af6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 19 17:37:32 2006 +0000

    add the msm800srv ; put the usb in the right place.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a341ee2646bed2d7f50c4b42f44acf18962f04fa
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 19 16:44:14 2006 +0000

    put this in the right place.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9560dd88c6626da7cf3af9018b3c9479f83c4a6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 19 04:03:40 2006 +0000

    resize OLPC flash
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3cf8a28e92b574645cf80ea63ccfbc6ea5919a4
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 19 03:47:35 2006 +0000

    Fix the name for buildrom script
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 830a79eeab1d71840ff1fce59dd2ac76c91b1d22
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 19 03:43:30 2006 +0000

    add an OLPC target for qemu
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d6810c60cda5a47b13813b590c57d39b719c013
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Sep 18 22:52:24 2006 +0000

    add the _lx flavor of the 5536. This will later be merged into the
    cs5536, but I don't want to mess up the OLPC, and we really need the lx
    support NOW.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2cf779d8d17ce2737ee1b49f6faecb7e76ac6b92
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Sep 18 22:50:51 2006 +0000

    fix old bug in the src/devices/pci_device.c
    add devices for the lx and artecgroup/dbe61
    point artecgroup at cs5536_lx as it is so different.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0740c31cff42e97ab16353d38a58b4bffdbb124d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Sep 18 04:23:23 2006 +0000

    A fix for hynix dram problems seen at 366/244
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50f84bdea8648d8890e2f3be09f81514094d64f8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 15 23:14:37 2006 +0000

    run preprocessor on hand-crafted config files in abuild, too
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7fe2b7cd5cadb11a8bd3500c15a09c51f326b7fa
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 15 17:00:11 2006 +0000

    add option to build autobuild images with real payloads
    instead of /dev/null.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 46bcaa303bc471f4605de794b1ec569850eb9bb9
Author: Ronald G. Minnich <Ronald G. Minnich>
Date:   Fri Sep 15 14:53:55 2006 +0000

    fix variable name for ts5300
    Signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b2f98af71e33427124b15fde811137776808573f
Author: Ronald G. Minnich <Ronald G. Minnich>
Date:   Thu Sep 14 20:08:10 2006 +0000

    fix stupid missing " type
    Signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53f486a3ea77d465de5e9387df69367e56a93ee0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 14 16:31:14 2006 +0000

    fix some really yuck stuff.
    
    now things might work.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cba07dd682f0142474f0aa235e97b6fcbc34d760
Author: Carl-Daniel Hailfinger <Carl-Daniel Hailfinger>
Date:   Thu Sep 14 15:12:36 2006 +0000

    additions and mods for lzma.
    Signed-off-by: Carl-Daniel Hailfinger
    Signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d9441276f144f0ffc5fe1523daaa63f916b9a25
Author: Indrek Kruusa <Indrek Kruusa>
Date:   Wed Sep 13 21:59:09 2006 +0000

    changes for the lx and artecgroup mobo
    Signed-off-by: Indrek Kruusa
    Approved-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c16ebde91142174ab4199a9b0eb2d2d2232b107
Author: Indrek Kruusa <Indrek Kruusa>
Date:   Wed Sep 13 21:25:20 2006 +0000

    new presents from artec group :-)
    Signed-off-by:  Indrek Kruusa
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9c100bdb7ba2b9d1d68e5d11df561372e3db360
Author: Jordan Crouse <Jordan Crouse>
Date:   Wed Sep 13 19:30:15 2006 +0000

    add file for dcon support
    signed-off-by: Jordan Crouse
    Signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e361efd7d7d592b0061d30aba2f41f5d088f8dc7
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Sep 13 19:29:31 2006 +0000

    Add DCON support.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66c335b8cc72b07ba082daad94b852b871175e34
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Sep 13 07:55:23 2006 +0000

    fix cardbus interrups (signed off by Nick Barker)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 613cb6171f50f2f897489f861593330fa1e10fc2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Sep 13 07:52:41 2006 +0000

    - fix irq routing for epia-mii cardbus slot. (signed off by Nick Barker)
    - some minor cleanups
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cf0050d68f5dfc2e88a532844784bd5993fbac6
Author: Ronald G. Minnich <Ronald G. Minnich>
Date:   Wed Sep 13 04:33:07 2006 +0000

    Slow down the clock, per Tom Sylla
    Signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cf642bad3fdd2205ffdd83a3222a39855b1ceff
Author: Ronald G. Minnich <Ronald G. Minnich>
Date:   Wed Sep 13 04:12:35 2006 +0000

    fix for qemu northbridge, from Ed Swierk
    Signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aefa3d74f950ad684fceed55d4c955593d33a14a
Author: Ronald G. Minnich <Ronald G. Minnich>
Date:   Wed Sep 13 01:57:47 2006 +0000

    warm boot patch from richard smith.
    signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ef4c598fb76a490a8a57455c244a8be03c7097e
Author: ronald g. minnich <ronald g. minnich>
Date:   Wed Sep 13 01:14:45 2006 +0000

    Fix the irq_tables
    signed-off-by: ronald g. minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cdb89be9e826e7ab2d13ff36cf12ac9603e845b6
Author: ronald g. minnich <ronald g. minnich>
Date:   Wed Sep 13 01:10:08 2006 +0000

    mods for qemu, these build
    signed-off-by: ronald g. minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94b17c6a3c26dee2696d1116ab2e964959d9e56c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 8 17:44:42 2006 +0000

    add romcc manpage from Uwe Hermann
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3e03d03a17bf35a5c9be77f324b98d44962757cd
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 8 16:34:51 2006 +0000

    hurry hurry before we might start 3.0 ;-)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b59906c1e9dc6e3e4902382cc3e9f4aa205ced34
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 7 15:31:27 2006 +0000

    remove dangerous call to normal image; no backup on OLPC
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42fb3164ed84b6c768c4c1ce3cf8b298cb9a569f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Sep 6 16:42:51 2006 +0000

    Uwe Hermann:
    Here's a patch which makes all "option ROM_SIZE" lines use x*y format
    which is a lot easier to read and modify, without having to use your
    brain or a calculator ;-)
    
    Tested with abuild, no errors.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca98f32dd558a9e03c09e7635ef951a80f90e48a
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Sep 6 16:15:02 2006 +0000

    Add support for ITE it8705f from Uwe Hermann
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2073ce2675b5d18dd86a8e4cb651a2185c9bf18a
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Sep 6 16:12:39 2006 +0000

    Patch from Uwe Hermann:
    
    * support for it8716f.
    * minor fixes for it8712f, it8671f, it8673f
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e918a3ab00d88662c35f5c266f4cede6caf01c69
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Sep 6 15:48:48 2006 +0000

    Add patch from Uwe Hermann to support more ICH southbridges
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61be08bd3e7f411ffb544d3ded2ae14ca225e982
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Aug 29 17:41:14 2006 +0000

    merge latest code from Uwe Hermann
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abaf71a2d5a62d0de88c2f69b038f8646835ffe3
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Aug 29 00:45:42 2006 +0000

    it8661f support from Uwe Hermann
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bcd1f2310d4d953a2d41baee7f7e9fc555b4df6e
Author: Richard Smith <smithbone@gmail.com>
Date:   Mon Aug 28 16:18:32 2006 +0000

    - Much better USB P4 fix.
    
    This one actualy works.  You cannot just go mucking about with stuff that the VSA
    has under its thumb.  Bad Things happen.  This does it the VSA way.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6af77aeb4093d74d7098fbad08e2625b0e6eb08b
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Aug 25 19:29:57 2006 +0000

    Support for two new ITE superio parts: it8712f
    and it8673f from Uwe Hermann.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 051427c40a626a67b58ab11f0ab12e8b1e3d658c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Aug 25 19:21:42 2006 +0000

    Print a warning if southbridge is not known to flashrom.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa60e7f9d06d9a54e8bcc9e6f90eb3bc6ae4095e
Author: Richard Smith <smithbone@gmail.com>
Date:   Fri Aug 25 16:14:31 2006 +0000

    - USB P4 as host fix
    
    This should make the USB P4 work as a USB host
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 64443b8c4970cc61ca4501d041d9e6983d02bef9
Author: Richard Smith <smithbone@gmail.com>
Date:   Fri Aug 25 14:06:48 2006 +0000

    - fix a silly pointer dereference thinko in my previous commit
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59ba228f921169bb12347932237c7500ccd58b41
Author: Richard Smith <smithbone@gmail.com>
Date:   Fri Aug 25 05:01:30 2006 +0000

    - Added suport for enabling USB P4 on the olpc
    
    USB P4 is disabled by default and we need to setup the mux bits proper
    to make it work.  This is the frame work for that.  All thats needed
    is the right address values
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 689c1448392ed93dfafc51a2dba39ba37631ce29
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Aug 23 14:33:54 2006 +0000

    Removing $Id$ tags as they have no meaning in SVN
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eca92fb37127246b3c1f323442322e93ed65861d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Aug 23 14:28:37 2006 +0000

    Uwe Hermann:
    here's a patch which replaces all DOS newlines with Unix newlines, and
    removes some useless $Rev$, $Id$, and $Header$ tags.
    (part 1)
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a1540b606f55e8b91ac6502af62f1b0c091efe3
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Aug 23 11:47:58 2006 +0000

    enable graphs created by dot.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e4ff2a51df82d0adac1e486f38fdf870f47c3f76
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Aug 23 10:52:12 2006 +0000

    fix special chars in document.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 60902ed3a1155f062a78baa5962ca7903ec1d621
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Aug 22 13:21:39 2006 +0000

    drop extensions directory. it has never been used.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1ac1cf527d8d83a6eeffbd79c87a83d1ee59151c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Aug 18 19:25:25 2006 +0000

    delete unused device.
    set rom to 512k
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a02b7d54eab215592c72e1a9dd9f998de98abd8
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Aug 17 20:31:09 2006 +0000

    add smsc part. Mod sun board to use smsc part for now
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bff323b93b8cdee0362d1351b8fde54fd2c66e45
Author: Ronald G. Minnich <Ronald G. Minnich>
Date:   Wed Aug 16 14:38:00 2006 +0000

    updates to make gx1 IRQ map work. not tested;
    signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 157e1ab47c961361e3dc5680aea21f72c9b0d5d2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Aug 16 14:22:10 2006 +0000

    share decompression code.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 60146861aa2878585ef27b55cccba269a2a87d4f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Aug 15 13:52:51 2006 +0000

    this file is already included by auto.c on all targets.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df6fb720b9b1cf745f192553d977f445c17a774f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Aug 12 22:03:36 2006 +0000

    update license template.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9d65e6ec02f459d539b605317a32bdaecb114117
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Aug 11 23:48:14 2006 +0000

    cleanup patch from Uwe Hermann.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2375 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e5522c39c09a61770c4014b237d2c53c78535ea9
Author: Richard Smith <smithbone@gmail.com>
Date:   Fri Aug 11 08:15:19 2006 +0000

    - revert Config.1M.lb back to PLCC size and add new SPI config file
    
    SPI config file is 1M-128k to allow for EC code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 273595c6f7adf87f733e95285948aa9dc7564ef1
Author: Richard Smith <smithbone@gmail.com>
Date:   Fri Aug 11 06:49:39 2006 +0000

    - fix dependency rule for Makefile and Makefile.settings
    
    The make dependency rule for Makefile and Makefile.settings was completely broken.  No way it ever worked.
    OLPC buildrom flushed out this issue.
    
    If you updated the Config.lb file in your target/<mfg>/<mainboard> directory and then switched to
    target/<mfg>/<mainboard>/<target> and ran 'make' you would get a permission denied error due to the
    make file trying to run 'config.py' directly rather than 'python config.py'
    We never saw this because we always run target/buildtarget <target> and that sets up everything
    correctly.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8519dc8dc1fb10addc6166caee6affc2413503c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Aug 11 00:08:37 2006 +0000

    build 1024-128k binary as per requests.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4c556c5ccb59e6ea9865ef7f65402e3c63fd3e9c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Aug 10 09:38:39 2006 +0000

    fix serial initialization (from Uwe Hermann)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af9cd4d0cf085a1b48e80b658841599b3831b8cd
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Aug 10 03:23:48 2006 +0000

    change from AMD for the IRQ10 problem.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 08af3f535dd4446857e378b5dd87eb8ce35f823b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 9 02:21:49 2006 +0000

    mods for the ultra40 bringup. This now builds.
    
    amd gx2 north -- don't set anything in the north, it conflicts with vsa
    settings. So we have our own pci_set_resources that is essentially a
    no-op -- just calls the kids.
    
    olpc rev_a config -- DISABLE the compressed rom stream. This SHOULD NOT
    have been set -- it is untested and caused real trouble.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e53d03c2113ea08e3b604341835504c49333b95b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 8 21:42:18 2006 +0000

    fix up the links for the ultra 40 -- i/o on ht 1 on each cpu
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a758acab7fe1561b4b40098efeb66f6da6db01c9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 8 18:02:12 2006 +0000

    fix up config space.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90e68aef683a89c0560cd56fd18baba2570b4512
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Aug 7 20:02:02 2006 +0000

    initial work on sunw ultra40. It's wrong :-)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4253844428c990324ee8f5a887e7af3b80db8b6e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Aug 7 16:48:11 2006 +0000

    add support for ite/it8671f superio from Uwe Hermann.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ac4ca2b17eb218c25663bcbb16e082506853f9d2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Aug 4 08:58:17 2006 +0000

    p2b uses i82371eb as well.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a14b46895c563d7b8eb9363397f10ba3f5d656ee
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Aug 4 07:50:59 2006 +0000

    final rename orgy. sorry for the inconvenience. This should fix it again
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c76b85d6a7414854b61a658758b3147a397e3947
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Aug 4 07:47:28 2006 +0000

    ouch. it's 8_2_371. I'll fix it. This commit breaks compilation
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d34758f05a06ab42a030b07c97b13cd18d2ce1ba
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Aug 4 07:45:45 2006 +0000

    rename southbridge i440bx to its actual name i8371eb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e3464109e47945b1a4d7e3dd0c6e291593de70a
Author: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Date:   Thu Aug 3 16:48:18 2006 +0000

    Changelog:
    
    * src/cpu/amd/model_lx/model_lx_init.c
      L2 cache initialization removed (moved to northbridge.c)
    * src/include/cpu/amd/lxdef.h
      more checked values
    * src/northbridge/amd/lx/northbridge.c
      L2 cache initialization added
      cpubug() commented out
    * src/northbridge/amd/lx/raminit.c
      empty function sdram_set_registers() is in use, don't remove
    * src/mainboard/artecgroup/dbe61/Config.lb
      irqmap changes
    * src/mainboard/artecgroup/dbe61/irq_tables.c
      tentative changes to irq table (currently not in use)
    * src/mainboard/artecgroup/dbe61/mainboard.c
      irq assigned manually to NIC
    * src/mainboard/artecgroup/dbe61/Options.lb
      gcc 4.0 is OK
    * targets/artecgroup/dbe61/Config.lb
      64K for VSA is OK at moment
    
    Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
    Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ad7c06535694959952b7d64a9649cb9534abd2a
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Aug 3 16:19:27 2006 +0000

    slightly changed C.D. Hailfinger's precompressed rom stream patch
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9327d22641992459a8e57f4d5125fdce72f7f263
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Aug 3 10:49:09 2006 +0000

    some documentation updates by Uwe and some smaller ones by me.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 085cb4b4ca9a51e42f0665850e2cc9879bfbfa76
Author: Jonathan McDowell <noodles@earth.li>
Date:   Wed Aug 2 12:46:13 2006 +0000

    Allow setting of serial port speed in EPIA-M config file.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5eca3489b7e7feadd2af97835fa6c88db9e38ad9
Author: Jonathan McDowell <noodles@earth.li>
Date:   Wed Aug 2 12:26:47 2006 +0000

    Add newer Via Nehemiah stepping levels.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f4c0b596a21918b0d023a39096c99e3d44ef19be
Author: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Date:   Wed Aug 2 11:30:32 2006 +0000

    Geode LX: this patch adds configuration/status/self-test MSR definitions
    for L2 cache and fixes wrong  P2D defines.
    This also patch adds L2 cache initialization for Geode LX CPU.
    
    Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
    Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4278e99383c926e2056a92b4bebb885ee6fdbea6
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jul 31 23:37:17 2006 +0000

    Add support for SST39SF040 and SST39SF010A
    apply C.-D. Hailfinger's patch for Winbond part (untested)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d7088c459c140d99a98e05c3be02e02592bb607e
Author: Richard Smith <smithbone@gmail.com>
Date:   Sun Jul 30 00:23:20 2006 +0000

    - Fix some copy bugs and thinkos in the i440bx SMbus
    read code.  SBbus reads to RAM now work. Yah!
    - Rename the register constants to something I can look at
    more easily.
    - Make the logic flow match the flow from V1 assembly
    - #if 0 out other SMbus functions that are still broken.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 01789b630f9bc52bdd2a490bd63c2250a55f0cfd
Author: Richard Smith <smithbone@gmail.com>
Date:   Sat Jul 29 18:01:43 2006 +0000

    - fixup Bitworks/IMS to use private copy of SMbus debug routines
    
    Re-enable the SPD dump routine in this Bitworks/IMS code and make
    it work like the Asus/p2b.  This avoids having to hack the
    sdram/generic_dump_spd.c for a single mem controller.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 924f92faa2f66d09f3ad79a946e3867c105372a7
Author: Richard Smith <smithbone@gmail.com>
Date:   Sat Jul 29 17:40:36 2006 +0000

    - Add support _framework_ for the Asus p2b.
    - New superIO winbond/w83977tf
    - Add single memory controller SBbus debug routine
    into a file private to the i440bx
    
    This adds support the start of support for an Asus p2b
    mainboard.  Current limitations are the same as for the
    Bitworks IMS board.  Reads from the SMbus don't work.
    
    Moving dump_spd_registers() into its own private copy
    solves the problem of having to go hack on the version that
    included in src/sdram to only do one memory controller.
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e9dc231209c1a293b5a92a9ea78eb07ce0a3086
Author: Ron Minnich <Ron Minnich>
Date:   Fri Jul 28 16:06:16 2006 +0000

    This patch adds support for the AMD LX cpu.
    
    There is one global change to pci_ids.h. The rest are changes for LX. I
    ran abuild and it is ok.  Not all artec design changes are included as
    some of them would adversely affect other mainboards. Indrek will need
    to test.
    
    
    Signed-off-by: Ron Minnich
    Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec
    design.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e534daa05ae7057ad615e15fa3021b19f4850fd0
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Jul 27 23:29:02 2006 +0000

    add flashrom manpage from Uwe Hermann
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59fc4db642bcf9c0a80785524e0740b03bfcacfe
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jul 27 04:05:43 2006 +0000

    "Hey Ron - Attached is a simple patch that enables the upper banks on the
    UART.  If the upper banks are enabled, then the Linux 8250 driver knows
    how to set baud speeds greater then 115200.  This was prompted by David
    Woodhouse.
    
    Jordan"
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb8eab482ff09ec256456312ef2d6e7710123551
Author: Richard Smith <smithbone@gmail.com>
Date:   Mon Jul 24 04:25:47 2006 +0000

    add framework for i440bx chipset
    add support for NSC pc87351 SuperIO
    add Bitworks/IMS manboard config
    
    This is a very basic framework for the i440bx chipset and the
    Bitworks IMS board that uses it.  Most things are
    structure only.
    
    Known issues:
    - SMbus reads to the RAM SPD come back
    all zero.
    - dump_spd_registers() is commented out since it breaks with
    the default setting of generic_dump_spd.c where it wants
    2 memory controllers.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4788effb045ae1f71d89c78a0b16a93d5ba79e89
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jul 21 23:21:01 2006 +0000

    restore the old code for enabling flash. The new amd code did not work.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da7ee9fa07b4eaebd6e16faa678d814d9ba03ef1
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jul 21 19:21:38 2006 +0000

    These changes incorporate steve goodrich'es fixes, and one bug that is
    disabled.
    
    cs5536: add new entires for SB  control etc.
    cs5536.c: chip_enabled function moved to chip_init, so it only gets run
    once.
    IRQ setup improved
    gx2def.h: new defines added
    vr.h: new file, with new def's for virtual register control.
    mainboard config.lb: new entries added for nb and sb control.
    chipsetinit.c: new controls added -- I forget all the details :-)
    grphinit.c: new function added
    northbridge.c: new IRQ control added. FlashChipSetup added, controlled
    by chip info setupflash struct member. Currently, if enabled, this hangs
    OLPC in linux PCI scan.
    chip.h: new struct members added for unwanted device enable, flash setup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 35befb75ead1b4bc34ef351bec2a411a3ee70519
Author: Josiah England <josiah@lanl.gov>
Date:   Thu Jul 20 15:35:04 2006 +0000

    New analysis tool with preliminary source usage information gathering.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87f194dd9e2977b0f3a274706b7f2b4795615c7d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jul 19 16:58:43 2006 +0000

    this code is for writing the mp table, so only execute it when
    we actually have one.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f1cb2342630e806399b2febafc8c215a8bf6059
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jul 19 15:32:49 2006 +0000

    move mptable to 960k to 1M
    https://openbios.org/roundup/linuxbios/issue55
    
    This patch is a little bit enhanced, it keeps the ppc table consistent,
    which Yinghai's original patch did not.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e32243a9b1ee4b4008bed424908d98e99610b8ad
Author: Scott Tsai, scott.tsai <AT>
Date:   Wed Jul 19 15:13:21 2006 +0000

    From: Scott Tsai, scott.tsai <AT> arima.com.tw
    Tested on my home Shuttle SB51G box.
    data sheet:
    http://www.alldatasheet.com/datasheet-pdf/pdf/47674/WINBOND/W49V002FAP.html
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 792ebfecd35ae750dd9fc2c851760fe0bce2a62c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jul 19 14:26:41 2006 +0000

    closing issue 44: rename ram clocks in cmos.layout
    
    https://openbios.org/roundup/linuxbios/issue44
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef0a24381be2e9a7dff9810c88c78285fb7823c7
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Jul 18 18:09:36 2006 +0000

    fixing aruma build as suggested by mail ;-)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f780d0229594680d8d752680e0912a25a74f09de
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Jul 18 16:53:19 2006 +0000

    sorry for the inconvenience. this is a test commit.
    breaking a build is intentional. It will be fixed in a bit.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e26d66e9dda7e197ed82e7b38bed1417ee04790d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Jul 11 09:04:52 2006 +0000

    fix handling of mkelfImage'd binaries
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 75d1b24537477dd07f4202cb6d06cf07c30c6117
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Jun 30 20:07:50 2006 +0000

    add support for EFST F49B002UA (untested)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 707097fc1ccf86373e38706adfdd0f648e89c51b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 27 02:26:06 2006 +0000

    fix interrupt for f5 (ehci)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aad235e9069ec1fd855a88b149520ba4d4b67a10
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 27 01:38:17 2006 +0000

    changes per steve goodrich.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0a683fa9c710251d3f673378cab2b78ff29cc38f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jun 26 16:51:06 2006 +0000

    create valid xmlfiles that pass xmllint
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6472a0e274bbdd374cd2af70c890066f28d0a2dc
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Jun 25 09:56:45 2006 +0000

    add support for PMC 49FL002 as used in the RD1-PMC2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 92e8b809b46c59742ae486ed5a52a0e0e25156b0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Jun 24 14:46:26 2006 +0000

    fix typo on duplicate line.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5560a34c88d683ce882e27f86625f526dd8d2254
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Jun 23 20:10:21 2006 +0000

    fix compilation of s2892.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53a00b7138fcf65190f33974118dfeb36e9f67cb
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jun 23 03:39:10 2006 +0000

    match settings per steve goodrich.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88fb1a6c371c9f368157bdb907f70d46bb670311
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jun 22 04:37:27 2006 +0000

    set up interrupt values for the southbridge, and add a function to
    manage them. Make pci_level_irq global. Add value settings for OLPC
    rev_a board. Comment out no-longer-needed code in olpc mainboard.c
    -- it is replaced by the settings in Config.lb, and the support
    in cs5536.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9d0b30dd2b33d04859986be85b125c3005b2a277
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 20 03:53:54 2006 +0000

    Fixes from AMD. Tested to build on rumba and olpc, and builds.
    Tested to booting linux on olpc, and boots.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f96360315b874f615739352d5b51a4a79d0f765
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Jun 18 07:44:45 2006 +0000

    delete two empty files
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3951027f57c56cde468d0d717842c42fb7a197f7
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Jun 18 07:41:48 2006 +0000

    * delete two empty files
    * commit SMM lock code.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d7bb590187052e96113d45378f0182f7d692e40
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Jun 18 02:28:07 2006 +0000

    fix idiiot typo I did not catch.
    
    add support for conditional enable of uarta interrupt.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48415d5cf6f317aa7d7c30623ed2b36b29710d8e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Jun 18 01:29:42 2006 +0000

    add irq mapper support for OLPC and other boards that need this mapping
    done for the gx2 north. tested on OLPC.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ab0fa9fedbfd3f0b21b84aed280bc8971ea324f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jun 14 23:22:04 2006 +0000

    add k8 processor name handling as required by the k8 revision guide.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f560285bd5362bb6a5e042b2df9afe696feb1bf1
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jun 14 15:58:41 2006 +0000

    new flash part
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd14d4414aab2b196bdf4499a3590187bf9c782d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jun 14 13:56:28 2006 +0000

    remove erroneous cache disable.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 73c92a4a7c1f9f0ff4451a5b34da9d18978e90e2
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jun 12 20:37:33 2006 +0000

    ron forget an svn add.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90dc0db6dea4b6b26a9cf99c3a804f61ae6260d0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jun 12 20:36:51 2006 +0000

    Get rid of #if 01 and debug prints that are compiled out.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 878a6696baf2504635eb7f32941f76a6e8125aee
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Jun 11 03:03:56 2006 +0000

    add a 1M target for big roms
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb937496428272c5bc9001d98fb99a70961f7df4
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Jun 10 22:57:15 2006 +0000

    changes from AMD for making OLPC video work.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 890ee09a3224f1cfc832f7c8f03e6c2f076aeb20
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jun 8 14:19:49 2006 +0000

    further development of OLPC. Set vsm size to 35k. add PCI IRQ for USB.
    Set linuxbios size to 28k. Drop debug level to 8.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 192b7bc44570f7b4268141f81ffca7a6b5f6fe21
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat May 27 00:22:02 2006 +0000

    add full xml logging to abuild to work on the complete information
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d1fe3700e5860f5a69d07cf0d5f63c9592c4174
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri May 26 16:23:00 2006 +0000

    fix two mainboards that have been broken by someone who does not use abuild.sh
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5fcfdbf899139d71f2bcd0ab4a9628b06abd967
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu May 25 22:08:23 2006 +0000

    add DK8HTX support.
    
    VSAs now required to be nrv2 compressed
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d0cffada3cbdd801d984242939b6f51ef1e090fc
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu May 25 12:40:03 2006 +0000

    fix broadcom/blast, tyan/s2735, tyan/s2891, tyan/s2895 broken by r2307
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9dd8d56192f617bb0afd20a59622f69b92353b2d
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu May 18 17:09:14 2006 +0000

    co processor support with s2891
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a8e36da2dcb67062c442795482095002587763f
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu May 18 17:02:17 2006 +0000

    init the ECC for BSP and AP at the same time. So reduce init cpus time
    from 2.1x to 1.1x or from 4x(SERIAL_CPU_INIT) to 1.1x
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b396cdcf268c1c9865c51517461b031f8995917
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu May 18 16:54:30 2006 +0000

    add option to decide to use onboard vga or addon card.
    CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bad9d105cf908bbb032768a1605265654b38ca3a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu May 18 03:07:16 2006 +0000

    cleanup some of the compressed rom stream ugliness -- more to do!
    olpc and rumba can now boot linux out of flash. vsa was resized to 64K.
    olpc and rumba now used compressed payload -- thanks stefan!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5d573c28e7520085ff7b687c05834292d615860a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue May 16 02:51:16 2006 +0000

    Commit for IDE NAND FLASH
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98e904ea7cfe9ef1ffeda4d3eaac2d42a5345760
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon May 15 04:44:15 2006 +0000

    OLPC now builds and works just fine.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9a335cb9b70bc8b0a5ebd099e1f2194ecaeef27
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri May 12 20:05:08 2006 +0000

    correct it, finally.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6084160f2de64cf937f4aab37c17f56f579a4d9a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri May 12 18:42:34 2006 +0000

    memory size in cf07
    goodrich pll code
    disable havedmi
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 437f28ece937933d10f853e30227021f89c5b5ea
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue May 9 05:25:31 2006 +0000

    Fix an error in the config files.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 49a89f19f269dc9bc0192f6aeba918a476e097cb
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat May 6 02:54:45 2006 +0000

    Use a real variable to configure rom base for vsa ...
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ad97691c40a0008e62a0d857df4be77443026374
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat May 6 02:35:08 2006 +0000

    For a kernel-only OLPC.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 694d20e2d62f2193168f87377eaf245df80e5014
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri May 5 18:18:33 2006 +0000

    This is to enable COM1 early.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1656c18d76773afe2b48dd8bf29d8f4e0b40d6ba
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri May 5 03:54:31 2006 +0000

    reorder early startup so that it might work.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 070a10f7593014f1ae8a0f15d34293f59790f9cf
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu May 4 23:05:49 2006 +0000

    mods for early printing on OLPC
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab4f5d0c10b23021608eaec56836a7d063837f3f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu May 4 10:08:04 2006 +0000

    fix the tree
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ac38a33f630112bc2b4caa35162a540afaa2d09
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu May 4 01:05:22 2006 +0000

    don't wait core0 started twice
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52377deec00798261a09bac6263291f9461756bb
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu May 4 00:58:14 2006 +0000

    core range and set_init_ram_access
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b73fd5648838eeb92f2d3255db8740f2fbd10442
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu May 4 00:48:49 2006 +0000

    rm unused file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 608d4b2c444515784a0ee54e018bb8a68456eb4a
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu May 4 00:47:15 2006 +0000

    merge zrom to rom_stream and print olen ilen
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4c475321341e16250cdc7b6eb1183e1a3cf62c74
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed May 3 23:10:00 2006 +0000

    oops! Slap me on the head for this one. Quick fix for ward until
    YhLu's suggestions are all there..
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c01fe5d1b674231546c070f035b0ab3c2d8ba3f5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed May 3 03:30:23 2006 +0000

    more changes; rumba enet works fine now.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc7b71cffa92173541ab17c8d2959cbb369a44b5
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue May 2 12:07:36 2006 +0000

    enable compressed payload per default
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ead73689db79fecc3e17215d100ab52ce4377657
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue May 2 12:05:13 2006 +0000

    add automatic payload compression method to LinuxBIOS
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d3ba4aaa245b1af50f70443ba01ec0baf883995f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue May 2 03:07:11 2006 +0000

    Fall back to pre-broken settings and setup for GX2.
    We lost a few things, but this is still worth it.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae3cbe951b414d9c2d2338f77e00132f7251cf94
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Apr 29 00:12:30 2006 +0000

    typo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 64f07fb21ce77994e929c1cadc61f0c77b7dd04e
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 27 20:44:53 2006 +0000

    remove more code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c1a4b2b0e56d5c12622e5c0841cabf599311c896
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 27 18:40:15 2006 +0000

    code cleanup, comments added
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b947b147348ee31285637e1c4f08c6e52e512f4d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Apr 27 17:46:27 2006 +0000

    more code removal and removal of incorrect register settings.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94571a4767bff35961d8dd81a36752442ec7405d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Apr 27 17:37:23 2006 +0000

    removing redundant and unneeded calls to functions.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3716427e7f63fd00e8117fca2027f2fe3a5bbf00
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Apr 27 15:10:55 2006 +0000

    we don't need msr_init
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7a09b4f19aa5e9d23118d32e523470e590318eb
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Apr 26 22:07:16 2006 +0000

    some todo and comment for ron.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae11b37ea54fc1716797a32223fc0a86aed3aab5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 25 20:34:52 2006 +0000

    no fallback version
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 417d8c44f959128aa345b332e7b8296834623c67
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 25 20:05:38 2006 +0000

    set irq options.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cf120d1a89e81b3bb3c4a201a759054ccc006919
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 25 19:57:39 2006 +0000

    builds and should do the right things for sb for interrupt routing.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c2f49e74aa254c7c415641002c0c2f52ed42a5c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 25 19:40:20 2006 +0000

    to give ollie a look.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ee2bbb90cdc079e3e598c1f20237a32eed43e04
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 25 04:07:44 2006 +0000

    fix the msr.lo for olpc 0x20000019
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c20eb440020803f89f3679c3fa80ddcb233c053
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Apr 24 16:56:05 2006 +0000

    hex values with 0x prefix
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2a7352cb9dd7211c9a7edbef5145dd59df264644
Author: Richard Smith <smithbone@gmail.com>
Date:   Sun Apr 23 23:12:21 2006 +0000

    Adds a CONFIG_MAX_PCI_BUSES to pci_locate_device()
    Default is 255.
    
    This allows mainboard configs for working across various groups
    of boards that differ a device that may not loaded.
    
    If you search for a device that is not loaded and max buses is 255
    then there can be up to a 8 second delay to search the entire PCI space.
    Board configs that know thier max bus can limit this search space.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f1980026865af7b11f27257c36b61d897932186
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Apr 23 19:21:12 2006 +0000

    fix so that olpc uarts come up enabled.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ff8c08e2577ee82446a3b800509ae7786d375979
Author: Richard Smith <smithbone@gmail.com>
Date:   Sun Apr 23 19:16:09 2006 +0000

    Adds support for understanding bus:dev.func to the -d option of testbios
    You may specify '-d bus:dev.func' or '-d dev.func'.  If you do '-d <value>'
    then the behavior reverts back to the orginal where <value> is taken to be
    the 16-bit packed notation of busdevfn.
    
    It also add a sanity check to try and detect when people have not specified
    the -d option and they should have, or when the -d bus:dev.fn evals to a packed
    busdevfn of 0x0000.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 496450c4eb45e44d33d12e0a48d23c9a0182a2ee
Author: Jonathan McDowell <noodles@earth.li>
Date:   Fri Apr 21 16:43:06 2006 +0000

    Lower debug progress messages in vt8623 init to debug level rather than error.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a910a3a02291b8bceeaadaae0c1745124fe0fea8
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 20 22:54:32 2006 +0000

    more 5536 -> 5536 conversion
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bbdaeaf55cf9814c28a753d8144646a88ab3a32c
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 20 21:40:20 2006 +0000

    change to 5536
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 32c315b1ef820c8c22ea33138fac1e2f48859da8
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 20 21:38:14 2006 +0000

    change to 5536
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8f4f8891da8b0a485291c2d5138ad13b530a016
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 20 21:32:43 2006 +0000

    remove dup files
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5d69896c8728d02b7c25f13192b3266b792312e1
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 20 21:31:47 2006 +0000

    add cs5536
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 05c0869fac22cae8a35897310fef64ad94caed01
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 20 21:26:01 2006 +0000

    boot to kernel
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 37784b429dc687fda68e2e779b01145e2c6d3bff
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 20 21:22:40 2006 +0000

    added cs5536
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc5a821f1e19153f4a11b29fca196f686b2f4885
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 20 21:21:25 2006 +0000

    add cs5536 directory
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c97d78b1ac62276ae6f08b5f96f5ccb05e4d2f4
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 20 21:21:13 2006 +0000

    add cs5536 directory
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 965b5ad85bf8f7ab144f81c232fd40e320c22545
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Apr 19 15:11:01 2006 +0000

    resolve conflict
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36c00aa39b9374fbf5f762fb9ebb022bce1f7fa0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 18 22:40:53 2006 +0000

    fix adjustment for sizeram
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61083dad0f03af10192ab65ebb0a2af98b9af8a4
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 18 21:34:32 2006 +0000

    add back in missing line
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 55e10fe3a4e84ef19ad718345808b6c354893ff1
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 18 21:21:10 2006 +0000

    set up timing
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 170ce333ca2d18df9ad1237dc9ac14e5ce235266
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 18 20:42:58 2006 +0000

    add ram resources
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df46cb205d57a91aa0fff142b2dd951e7731731b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 18 16:36:58 2006 +0000

    added the olpc target and support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea9db56d0e78499faf38a5d8e0c2125275c69ef2
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Apr 13 19:44:50 2006 +0000

    add SystemPreInit() and support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8d8fffa0edc8b86f1efab2f3a44c9d53cefe556
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 13 17:00:38 2006 +0000

    minor modification
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cf648c9a99c59f25400f198b99de2f92e57db349
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Apr 11 19:23:57 2006 +0000

    this was in my queue since 2005/10/26
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fbce0ffb92d8665c9cef5cb7be4d9fa6646bd7f2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Apr 11 18:36:42 2006 +0000

    small fixes to get Ward Vandewege's Tyan board booting.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b8cf1d30ab195cfc59f777741c2d2126e12ec26
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Apr 10 23:32:23 2006 +0000

    added chipsetinit function, many defines. addec call to chipsetinit to
    northbridge.c
    builds fine on lippert
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45f6c5e3d450053e53a8ff4a687fd0dcaf2d7475
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Apr 10 16:40:19 2006 +0000

    add cpureginit to romcc code.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 526b2c429e41bbd177853169deb63c1bf00c70a9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Apr 10 16:14:19 2006 +0000

    clean up gx2def.h a bit.
    Add cpureginit.c
    added called to cpureginit to model_gx2_init.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5346533656f32cef8bcdac99bae394286d39af40
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Apr 8 10:04:43 2006 +0000

    drop unsupported momentum apache board. Check
    http://snapshots.linuxbios.org/stats/abuild-LinuxBIOSv2-2247.log
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2a9fcb79f4238fd6d6a15a438034e3d8d5952b7e
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Apr 7 20:35:39 2006 +0000

    15->11 for device num
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4223188335a07700626637aaa584006372b47628
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Apr 7 16:55:20 2006 +0000

    add support for GLIUInit()
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 40fedaf6a97d0712c509cb92f9ad1365f0710eb5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Apr 6 23:35:52 2006 +0000

    add northbridgeinit, also add new constants.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29e2726c4a9c517687b6fba6662908dc992ac701
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Apr 6 22:50:26 2006 +0000

    pseudo fix xe7501devkit
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f01f154635c2fc2cca009b4731389507c3ad98b4
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Apr 6 21:45:24 2006 +0000

    fix constants style
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84e4bf69c7f0b6b4cf685fe0d6abf6ec93b2eff5
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Apr 6 21:40:36 2006 +0000

    interesting behavior, i thought svn could do moves.
    the result should be ok though..
    
    the purpose is dropping the old i82801er southbridge code
    and using the ich5r code instead because its the same chip
    but the code looks more solid and is used by many more systems.
    
    Some of the old i82801er features have been ported (like hpet enable)
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 966d0e6d70b20b6d14e265d59aaad37ce84d2ddb
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Apr 6 21:37:10 2006 +0000

    break the tree really quick due to svn restrictions, next commit fill fix it
    again.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 44f72eb3a3d07ec3c775b748f6a2a16e9e0a3e75
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Apr 6 20:45:10 2006 +0000

    add bug support for 2.1
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69085400f1a661abdb93e10cf7a6a8b4a42e540c
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 6 20:23:29 2006 +0000

    reformat
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5917c62749b9cdb60e54bb409bf74fe50e414aa7
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 6 20:19:04 2006 +0000

    more fix for vsm, not working yet
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8854d30d6edb0e4e7f73cd2ab72b7cec78556846
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Apr 3 22:20:05 2006 +0000

    did I commit the last change?
    try to fix 0x10000026
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 81efd7ab6deedf89af398d9039851d88db3aca0d
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Apr 3 21:29:48 2006 +0000

    comment out reset from MB Config
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b66f54ac6e381f86bdc7416ba2ab02826faf3b18
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Apr 3 21:24:05 2006 +0000

    comment out reset in MB Config
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a791dffeae2097aa0a18f645ce07acfed41b9bc
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Apr 3 20:38:34 2006 +0000

    new cache_as_ram support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ffb7d8a31ae899f611235cd0a7f3579d34cd8cde
Author: Richard Smith <smithbone@gmail.com>
Date:   Sat Apr 1 04:10:44 2006 +0000

    - Adds support for the Advantech eval board.  Configuration was produced
    on a SOM-DB2301 baseboard with a SOM-2354 cpu module.
    
    - Also does a slight tweak to the ram test code to make it more
    obvious when it fails.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b539d78abaae60d0e9e71f53b2e4103b6f33a65
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Mar 31 11:36:06 2006 +0000

    * https://openbios.org/roundup/linuxbios/issue96 - SST_49LF040B flash support for flashrom
    * https://openbios.org/roundup/linuxbios/issue99 - add ICH4-M support to flashrom
    
    both from scott.tsai <AT> arima.com.tw
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f64c13381bc4a22f9747991e5d2fcc1a3976642
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Mar 31 11:26:55 2006 +0000

    * support for Winbond W39V040A
    * Support for ATI SB400 (RS480 chipset)
    * Support for Intel ICH7 (from Scott Tsai, scott.tsai <AT> arima.com.tw)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3efd138a712fe844db2c667a50208358ff423bf
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Mar 26 17:13:31 2006 +0000

    trying to translate some of this.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96f8fb5723d41c5908ef267e2386a08c26be28b0
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Mar 23 19:26:40 2006 +0000

    make older winbond chips work reliably.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a971bddcfecec060d4357a65030cfe128ef790d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Mar 22 17:30:48 2006 +0000

    fix bit-twiddling errors on msr
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96cb65680693bbe20ddd4ab9ffd6247327708867
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Mar 22 16:25:49 2006 +0000

    added this file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd6985bce39b3aec1ad68235752863ee8da6cd9b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Mar 21 23:24:33 2006 +0000

    vsm can be called now, and then hang.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7f809097f86a3196d8c6788a537c0876b3a0df41
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Mar 21 15:24:46 2006 +0000

    add vsm support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e4ad801495e276c26de7b5881118941f777483ac
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Mar 21 03:38:53 2006 +0000

    cpubug is fine.
    adding vsm support now.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 316ea53e291f1f1526b7877075383052e09e3981
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Mar 20 22:20:09 2006 +0000

    fix conflich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a11e6cfd9232d7db4e30d645e6545f5ea1851bb1
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Mar 20 21:37:54 2006 +0000

    compilation fix for gcc 4.0.2 (SUSE10)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af9484a2a8a88ad68c23a509b713646dda4c740b
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Mar 20 21:18:53 2006 +0000

    resolve conflict
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit db44be9405ae4b62b525fb7dad80e20c499cc07b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Mar 20 20:49:34 2006 +0000

    added definitions. added cpubug support. added object. Commented out
    msr set in northbridge that conflicted with the cpubug support.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1293041db08ab9c4a1c80096d76cd1d71e52feae
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Mar 20 19:02:31 2006 +0000

    some more information on the ts series
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4ca49bfec77921441101fd6d84690ce3a6dd607
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Mar 20 17:31:02 2006 +0000

    add a define
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e2632fdbb98a425a27a801d621bb24c32e1d425f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Mar 19 22:30:42 2006 +0000

    redo ts5300 auto.c
    add ts5300 flag as comment in flashrom utility Makefile
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3cb4dc9c6b9f86f2465f85a1eddee301fbab648d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Mar 19 17:50:54 2006 +0000

    small cleanup attempt in sc520 code. there needs to be some major spring
    cleaning
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 677267a82a65c5ad802869171e3de6e5e7e270d4
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Mar 18 00:10:29 2006 +0000

    small ts5300 update, fix endian problem in dummmcr.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34407063c2b9585bdb2c349ef4f3fb27d2981002
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 17 23:03:04 2006 +0000

    added initial msr support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dba3f846f0978812d081245d9e636cd434978067
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Mar 17 22:48:23 2006 +0000

    - sc520 updates. move PAR setup to mainboard auto.c
    - some ts5300 code. Let's push this upstream for now.
    - fix a typo in device.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f4001cd8a7d1e578e22a391150c4c446e13157c0
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Mar 17 22:35:56 2006 +0000

    update dumpmmcr.c utility
    another flash chip that doesn't clog the serial line
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 042f0430d3905786620b3e74ffb8d48ea551b20c
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Mar 17 20:11:38 2006 +0000

    resolving conflict with Ron's work
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a5ce2341ec04f333297cef729892cf886710ea89
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Mar 17 19:52:52 2006 +0000

    reformating, we are going to use it for
    vsa on geode GX.
    
    There was some bug in setting up stack, what was that?
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 410075e0f1e0e0857a727b581cf58775236f0c36
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Mar 17 18:32:10 2006 +0000

    fix mmcrval, small cosmetics to raminit
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec5b166f4136f3575cfcc6091a2202036e7bb2d6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Mar 16 22:23:03 2006 +0000

    add in the msr configuration
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ccce5dd4909404594b3836414f657f0e4e3e0834
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Mar 16 16:57:41 2006 +0000

    - speed up flash verification by only printing 1 of 4096 addresses
    - support for flashing technologic system ts5300 SBC (needs -DTS5300 in
      the makefile)
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b107715f945ffab10c8e5c43b8f16bb13bb2ae2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Mar 16 16:46:19 2006 +0000

    make am29f040b driver more solid by printing every 4096th flash address.
    This fixes the timing when flashing over a serial console.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3ecf106fa9eda9030c5932e25b8c91b54ef6459
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Mar 16 16:44:07 2006 +0000

    support for Am29F016D
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 76ce5deb54ce145676fa2cc970b59cd137b5b983
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Mar 16 00:52:58 2006 +0000

    dump mmcr registers on Elan sc520
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 426da0bc45d95aad6a22ab058496b07e91340855
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Mar 15 23:40:30 2006 +0000

    stupid svn failed.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb7f4cf410cc427c6cfd8e2382c3622b97695508
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Mar 15 00:19:03 2006 +0000

    disable watchdog, and it goes much better!
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a83b9762fce9012161eb39813f357dee673670aa
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Mar 14 20:17:35 2006 +0000

    for different pll values.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a41ff52ba9eceb0ef72eddc8f2c14be5751d85a3
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Mar 14 20:01:51 2006 +0000

    Make the pll stuff parameterized.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c994c973c654817f5e764615776b78b84cd21910
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Mar 14 19:58:14 2006 +0000

    Fix for nehemiah
    other fixes for gx2 ram init.
    
    support for sharplfg00l04 -- not working yet.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d96e098def3ed64be0b775d4a6c058821e33b5ef
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Mar 14 00:11:59 2006 +0000

    go with newer auto.c ...
    but it fails
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71e3326b9c188cad12cce583b298ef35ae1558bf
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Mar 13 22:20:29 2006 +0000

    added pll_reset.c
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2195 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a413ecc6cd84c964456f2e76972a8f1379fc9c6f
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Mar 13 22:18:39 2006 +0000

    added early_setup.c
    removed some messages
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 070a1e02d0b6012283b914338ff64127b1d9ffeb
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Mar 13 22:00:21 2006 +0000

    correct __ROMCC__
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71eae20b305fc894f2d6e35bd5d58084153ea8b6
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Mar 13 21:58:43 2006 +0000

    failed attempt to do early init for cs5535. Almost there but
    still get garbage reading smbus.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec9cdc980fe3f6c5037b76907550e1323958da75
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Mar 2 21:33:01 2006 +0000

    I am so stupid to mix up logical and bitwise NOT.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 416b3d76cdf87d5354085d421510e476b9610067
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Mar 2 18:02:24 2006 +0000

    add smbus access routing for cs5535
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74f36096ae487d947d6d98c185952bfb95605249
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Mar 1 16:11:05 2006 +0000

    a few new items and mods for ollie
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c0fe3190c49aca5339ee37e32c4dfd3e3e824dd0
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Feb 28 23:07:27 2006 +0000

    remove more unused code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2188 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b2528aa653224d903f3b64e3af9aef4cc46fb7b9
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Feb 28 16:30:41 2006 +0000

    remove unused GX1 asm code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bab9446dfd715255d7c8dbefa11a214ffc354cab
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Feb 28 15:39:25 2006 +0000

    semi working with random 1 bit error
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2186 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a51e6f1e560a1dc40ec0c9522733d5f8422f041f
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Feb 27 18:28:30 2006 +0000

    more GX2 commit
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 981367932d3719f7287e6384432411a710de4729
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Feb 24 17:23:46 2006 +0000

    rename files
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b9591dd8b92834c108d2c5fca6b942b6e1d4c03
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Feb 24 17:10:10 2006 +0000

    added support for ICH5
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 30a1175ec8a8e7fe0f773fed2396c440793afa67
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Feb 24 13:47:26 2006 +0000

    new flashchip support by Leon Woestenberg <leonw@mailcan.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 108dd2c01eb5a01605862b3c105f0aad75842795
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Feb 23 21:39:19 2006 +0000

    preliminary GX DRAM initization. It is not working yet.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 02bb7892fe36ea1310b00ae7c3883e99ab4f0a43
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Feb 23 17:16:44 2006 +0000

    added sharp flash
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24c541ba946e576e00add8a7c2942ff799284ac5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Feb 22 22:12:39 2006 +0000

    oops, added a binary
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 394e7c416bb1e431005fe1cbfd62b4366896c27b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Feb 22 22:12:21 2006 +0000

    added new superio. added new simple util.
    modified dell 1850
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7db27ee6483f6b31023030a77fe37bc4c1842ac8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Feb 19 14:43:48 2006 +0000

    gcc 4.1 fixes.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit afd34e61ace6476946f9f30af92e0f714c901013
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Feb 16 17:22:19 2006 +0000

    serverworks HT1000/HT2000, bcm5785/5780 support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d5865d3d48259f43a1d78af8107d46c7a3a73f3
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Feb 13 20:20:28 2006 +0000

    this gets us to working serial output.
    
    memory is next.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d2e13267764af006322c287f12f5d82e80bc12ce
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Feb 11 22:12:17 2006 +0000

    frontrunner now builds
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61322d21a09a99f57e0d3018ffce04d1571ecc3d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Feb 11 22:08:41 2006 +0000

    fix mistake in name
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e0aea3bbed543908c60c3571d709a302e7dc2b8f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Feb 11 22:07:44 2006 +0000

    lippert frontrunner
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 566bf71d5bba5a79eec03b8c5e35e7a54ae5eb2d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Feb 6 17:07:59 2006 +0000

    add this file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 41bac281156a6be10fcef6e34163fd6e49fc922b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Feb 6 16:16:46 2006 +0000

    make doxygen work
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7ac85c30db41ed39338035728bea03ab8411aee
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Jan 28 22:01:56 2006 +0000

    This is the change so that we can readable ldscript.ld
    
    amd/rumba now builds.
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f1e9ea0b62e9652ab7efff791e0d867d43d95fe
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Jan 28 20:05:37 2006 +0000

    GX2 builds
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1baf7843296940ec4b6342110cee0ad410c29ba0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Jan 28 20:03:14 2006 +0000

    added GX2 ids
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f9f977cce9d25603201d64a1241d9cbf89d2f75
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Jan 28 19:56:25 2006 +0000

    rename
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8a1228872aa8940a2cf3fd2b043442086dcde3f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Jan 28 19:55:01 2006 +0000

    rename
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2bb216a880d2358c25b305ce613d8dd5aecd90ac
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jan 27 23:46:30 2006 +0000

    adding preliminary, and almost certainly wrong, rumba support.
    This is just a skeleton, basically, and will most likely not even
    compile yet.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 05c743a5ebf715f788a62fded7e9896e6e6c6d63
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jan 19 23:01:07 2006 +0000

    fixed apic cluster.
    It's still busted.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a00719b2f2b5bd74cfc52d0326c13e115e860eba
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jan 19 18:11:21 2006 +0000

    add a tinylinux config file
    Make the error in buildrom a lot more informative -- how big are the
    things that did not fit? it now tells you.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 264e84adb835ce9bb7eb5d703417ef2a41c0231d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jan 18 17:12:44 2006 +0000

    fix stupid bug with unitialized conf variable
    disable agp slot in config.lb
    fix error in setting up com1 == should be TTYS0_BAUD
    note that the uart8250 struct is a bad design, but so is the
    uart8250 code.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e800b91f38390987756de181f595c5b5492e00b7
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jan 17 21:12:03 2006 +0000

    Typo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce0c9686d97e9a068f0a3e9eaf6856554ff9b06e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jan 17 21:04:53 2006 +0000

    First, a FATAL error, that blows up your BIOS, should NEVER FAIL to
    provide more information. The printk_debug in that failure case is now
    a printk_error.
    
    The msm stuff is for debugging.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a68aeb9033bbf6746236fc9a46e2593a37c4983
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Jan 9 20:42:50 2006 +0000

    don't need copy_secondary_start_to_1m_below for non-smp
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eef3f955c492f845e8511fa3fcd62c03c33d5e8f
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 6 01:56:25 2006 +0000

    enable bsp apic id lifting regarding ioapic setup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8170f729966587912be024df58db9bdbee9ea49
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 6 01:55:42 2006 +0000

    add the dest cpu apic id in ioapic setup so we can lift the bsp apic id
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6edf7a904fdef16b731979f615638e3d60b5005
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Jan 5 00:19:52 2006 +0000

    update comments
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f1c0fc7ff27832c52e1a3305ecb720ec9b29ce1b
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Jan 5 00:18:41 2006 +0000

    latest agami/aruma changes. Compiles but won't boot yet
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0571a95262be0d58dc28a3f0fba2c69dc543b018
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 4 20:42:49 2006 +0000

    CONFIG_LB_TOPK 8M above support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 815ced3f7add6a80110e36cd5e7dd383c70501d8
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 4 20:41:05 2006 +0000

    1M boundary for _RAMBASE=1M, and CONFIG_LB_TOPK 8M above support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 27897c7adc1d1577b137ce62cd7bf05be9a07d54
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 4 16:42:57 2006 +0000

    pass on return values
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 260f1cc55d4ba6cc060d6969044ce9c91a5bac1b
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 4 01:06:13 2006 +0000

    typo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e4d08ee6510ad0747184d3d7aae7d83d4e95cb6
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 4 01:02:17 2006 +0000

    type error fixed...
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2850b5eb206c0b8ae4c04adeab63f9abfa5c1003
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Dec 29 14:55:09 2005 +0000

    fix buildrom compiler warnings with gcc4
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 967c4c4a5108d093fea2fdb0d11e8b73e8bd3c38
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Dec 18 18:40:46 2005 +0000

    redo image checking in conversion case. Please update to this
    release if you are using flashrom.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98de8cdbfe055a80b4d4a265b1463f3826a346e6
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Dec 18 16:41:10 2005 +0000

    * make -v switch print debug messages.
    * do case insensitive comparison of mainboards, as wished on the
      mailinglist
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c02eb2cb54c5013f2bba4622cc1a487bca55d1f
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Dec 14 23:13:13 2005 +0000

    indirect jmp with *
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 30576601f6d29a72d5057ac0051ebe3479abc03c
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Dec 14 20:16:49 2005 +0000

    from issue 53: don't set TOM2 if 4G less mem installed, opt for init_ecc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f63c0297c3e3f31674dbbf193635921b5c20e15
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Dec 14 20:08:23 2005 +0000

    support HDT disassembly when cache as ram auto stage
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 72ee9b0ebefa98e05867712eb303269836ec69b4
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Dec 14 02:39:33 2005 +0000

    issue 51 and 52: set mtrr for ap before stop it, and _RAMBASE above 1M
    support and pgtbl after 1M support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f42e1770f968adbb4d197917d130219d193081a3
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Dec 9 01:58:07 2005 +0000

    make clear_1m_ram.c to support gcc 3 and gcc4
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 653ee54a88b4cb45ec22cb3e986043d900b8564a
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Dec 8 18:47:33 2005 +0000

    fix bus problem with s2885 with issue 47
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3b360022258c4cfb7413cb88457f0c10ab396fa
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Dec 7 19:02:45 2005 +0000

    use CONFIG_LB_MEM_TOPK instead 1M hardcode from issue 50
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 73cc74e4f08fbd41d2025fd20abf9427d94e618a
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Dec 7 16:35:49 2005 +0000

    fix type error for s2895
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b3b1b2d3fbdae2409279a08da80c592da78ab13b
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Dec 6 23:40:58 2005 +0000

    from issue 47, put chain on bus 0, 0x40, 0x80, 0xc0
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 968bbe89cdc0a8bb47852388842bdf4ab625126e
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Dec 6 23:34:09 2005 +0000

    use hcdn to simplify the mptable.c and irqtable.c  --- patch fro issue
    48
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c2d54479d777f4095851f65bda67c6ace26b35b
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Dec 6 22:57:07 2005 +0000

    corrected mptable according to factory DSDT
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bbdd8f4a9f206ca40dea2b15d9458ac048de6c64
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Dec 4 21:52:58 2005 +0000

    1203_hcdn.diff:
    store every HT device unit id base and pass those info to acpi
    https://openbios.org/roundup/linuxbios/issue46
    
    Note: This version drops the two scripts a and c and creates the dsdt on
    the fly from Config.lb using makerule
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e38a19372009f39a8814cdee05faf0251640489c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Dec 4 20:42:37 2005 +0000

    oops. no false positives please.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8913a48d0bc610ba36bdd453d5d4cfeb3128d27
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Dec 4 20:35:56 2005 +0000

    add compilation time to abuild.sh
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 453dfdfdafbc2d10ec9289699a22e8c4fd8c2ad6
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Dec 4 17:50:32 2005 +0000

    implement io based udelay function for all mainboards that lack an apic
    timer (or just failed otherwise due to missing udelay)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a09ab6dc531aa7d14706b6a912e5feb476426ab2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Dec 4 17:08:31 2005 +0000

    get ts5300 compiling, it's mostly a copy of msm586seg
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 648e8da0c2110edba650cad6d322b887930d3b7f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Dec 4 15:47:50 2005 +0000

    small gcc4 patches, some ts5300 updates
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20c6f631aa298184cfdf1d70fae841e473b03789
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Dec 4 00:00:15 2005 +0000

    abuild changes to allow ignoring dummy directories and injecting architectures.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bbbfd9d1906cb2d99385eae845a13a311f77ef78
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Dec 3 23:48:17 2005 +0000

    smaller fixups here and there, allowing some motherboards to compile or
    to fail later than before.
    dos2unix'ed the xe7501devkit files, that might have caused some problems
    before.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd25fe979bee6a2912b671b7f811192c51c5f95f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Dec 3 23:12:07 2005 +0000

    applied 1202_ldscript.diff from issue 45. This fixes images smaller than 64k
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4bd0de0b2ecb0d59fb0703df71062c61e7c34cf6
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Dec 3 22:39:23 2005 +0000

    add cmos checksum range to linuxbios table
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0cf46ca21556e46abd03207ea3300b30233affdf
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Dec 3 19:07:35 2005 +0000

    small update, one comment adjusted, fix epia-m abuild.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57efb8eeb9bbbcc5c3e4bbb71eab0d9e2205994e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Dec 2 23:44:40 2005 +0000

    fix up abuild.sh to new requirements. This might leave some builds
    broken.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12142ada40529fe64d1289d927f07782c920b249
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Dec 2 23:26:13 2005 +0000

    1201_ht_bus0_dev0_fidvid_mb.diff - part 3
    issue 41 - fix up motherboard compilation
    
    target configuration files. Who wants to do some major cleanup here some
    time? The fixed/relative paths in payloads are nasty.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03d56cb18c2ba0965ee46ec20634c52bd7dffefa
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Dec 2 23:17:39 2005 +0000

    issue 41 - fix up mainboard compilation.
    
    new serengeti_leopard specific code
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 373511b2f96807d7a7a6b0b34ad3e7519c311aee
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Dec 2 23:16:01 2005 +0000

    issue 41 - fix up motherboard compilation. There's always hope.
    1201_ht_bus0_dev0_fidvid_mb.diff part 1
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 563fc1686075d370cf4f49f85e21c546c52d2a05
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Dec 2 22:09:18 2005 +0000

    backing out pci device renames
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ce8c54e2ba89059d28790550a8f74907b54b916
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Dec 2 21:52:30 2005 +0000

    1201_ht_bus0_dev0_fidvid_core.diff
    https://openbios.org/roundup/linuxbios/issue41
    Lord have mercy upon us.
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c2455dc0ce210b3da2b14be8885803ff47a781eb
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Dec 1 16:19:24 2005 +0000

    issue 40, make flashrom utility build process more solid.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f5183cfa19ea4d235ac9e1206c8510c8c83ace0e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Dec 1 11:01:01 2005 +0000

    Applying YhLu's patch from issue 37.
    
    a. apic id liftting to way that kernel like and let bsp
       to stay with 0
    b. hw memhole: solve if hole_startk == some node
       basek
    
    This, together with the previous one will break most of
    the tree, but Yinghai Lu is really good
    at fixing things, so...
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 806e146e754a44f96c693cde707065b14f80d8a2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Dec 1 10:54:44 2005 +0000

    Applying 11_26_car_tyan.diff from Yinghai Lu.
    NOTE: This will break the tree so it can be fixed up later
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 70597f96c45e225a42f395cdf16b4ad62459dc3b
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Dec 1 10:51:08 2005 +0000

    mention build dependencies in Makefile.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 45065d90d974108c963ce63af4d5bd267aa7273a
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Nov 27 12:45:28 2005 +0000

    fix intel jarrell build (no issue tracker number since trivial fix)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6384a57e20c15c2266b91254b5f41f455bb2ffd2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Nov 27 12:11:59 2005 +0000

    fix build for all supermicro boards.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a4f0707bb33836953ffe90f6216ee20210cd1fa
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Sat Nov 26 21:55:36 2005 +0000

    flasrom update from Stefan, resovle issue 21
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f622d598db3a6fb7001b6b63e7184272eb19db72
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Nov 26 16:56:05 2005 +0000

    - Apply 11_24_a_s1_core.diff from
      https://openbios.org/roundup/linuxbios/issue24
    - fix up for via epia-m
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7627bca656d365615dbf2c06053430e83565f8d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Nov 26 16:29:08 2005 +0000

    fix ron's issues with abuild.sh (don't hit me for not doing an issue tracker entry)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af77a61a9cf8438e327801a77d0bd33ea1f8481e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Nov 26 11:57:57 2005 +0000

    add another Via C3 cpu id reported by grzegorz@el-kom.pl
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6cc0e084eaf4dbdfa3d2e2295a6b931370c64cb9
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Nov 26 00:10:10 2005 +0000

    first round of agami aruma merge
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c49a8120f5bf4545793b3d26d96f9e7b2b6113e9
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Nov 25 15:28:57 2005 +0000

    final checkin for island -> agami
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f537f9800bac822a03987f32dcf621dc54fdce5d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Nov 25 15:26:41 2005 +0000

    island -> agami
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 444bc4b1c8932ea66531ed05880cf06654deaa62
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Nov 25 15:25:52 2005 +0000

    island -> agami 2/3
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d5795f3d5c6b946639f2f3b0fc6788a8e4ec85fc
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Nov 25 15:24:24 2005 +0000

    island goes agami
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d5c7a7f1794cf846f2b62813c81f0f2a0ac5b54
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Nov 24 10:45:34 2005 +0000

    rename the directory to match the program name
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e0e137844adc8366de58514b10ed962da46ce77b
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Nov 24 10:25:46 2005 +0000

    fix typos reported by Martin Ley
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 164586bad8abe494a765f4ab11740855916f4706
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Nov 24 02:45:45 2005 +0000

    adding support for serengeti leopard
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ee5ee894b81860e54d77d43eba512022e379def4
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Nov 24 02:45:10 2005 +0000

    serengeti
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7a96514e3f260dd78d279526215da43db2c35f8
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Nov 23 21:51:30 2005 +0000

    added missing microcode.h
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6bd192f6c607ea4b90e2d1ef9da19d9b20d5c22
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Nov 23 21:12:47 2005 +0000

    remove rev f ifdef
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb0a64ba77dbf1fa00d07453c76b875cd124cfcb
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Nov 23 21:01:08 2005 +0000

    CAR patch from YH LU
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 872141a40291b73f061ae95a78baadb557efcd83
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Nov 23 20:52:43 2005 +0000

    Split out microcode updates.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebc692873dd38e397b256e935269232789770416
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Nov 23 15:41:10 2005 +0000

    fix so it can use a pre-built test config.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed1f9a75b30c0080dc057240b5bac726a274a062
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Nov 23 05:09:42 2005 +0000

    missed these.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b6b3d22a2f0a44b0fb45de68c22d21457aca42a
Author: Ronald G. Minnich <Ronald G. Minnich>
Date:   Wed Nov 23 04:56:36 2005 +0000

    issue 25, various AMD patches
    Signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9442591f42a8e9bb59fd66976941deb6f7c8ca1e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Nov 22 16:47:40 2005 +0000

    fixed fsf address
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43225bc8042b32d52b31c788daee1e42bd1fa28e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Nov 22 00:07:02 2005 +0000

    EPIA-M fixup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86cbd33837207e06a9ae41efe65ac2401e885c4b
Author: Ronald G. Minnich <Ronald G. Minnich>
Date:   Mon Nov 21 23:22:21 2005 +0000

    This was posted on issue tracker and approve by ron minnich
    Signed-off-by: Ronald G. Minnich
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7272fcb2a466d2554b29e082c8e57038bfc4ebe6
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Nov 17 13:45:46 2005 +0000

    these were factored out.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ddab65fda40936a79c014bab0958fa87fcec422c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Nov 15 14:37:07 2005 +0000

    set to executable
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d304c18e2cf1451a45c69aac61198d896da1e4d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Nov 14 23:04:55 2005 +0000

    comment and unify lb_uint64 handling as discussed on the mailinglist
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8af7998bacc11c66381836c28b099a4407da955c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Nov 12 20:58:26 2005 +0000

    add utility to dump linuxbios table from v1
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2fd467ce3ca96391f787d4e5f8c56878321da160
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Nov 3 08:13:39 2005 +0000

    reverting rev 2082
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed009371030cb97571c8b8dc342f16a9fa124d59
Author: Eswar Nallusamy <contacteswar@gmail.com>
Date:   Wed Nov 2 17:32:49 2005 +0000

    ppc970 initial porting.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 987ca8e08c3307e46dde3b35c6190c504f0cbf19
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Fri Oct 28 18:59:04 2005 +0000

    Make #defined constants more descriptive.
    This was missed in the checkin of raminit.c changes.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 984bab5740dea46b8da14c434c7bae7058565e9d
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 22:24:46 2005 +0000

    - Fixed fat-finger typo enable - enabled
    - Fixed abuild.sh to use larger size for ROM_IMAGE_SIZE.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 737253bf12b4903613233913621ff750cf74d398
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:50:06 2005 +0000

    - See Issue Tracker id-15 "lnxi-patch-15".
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f274d94360a8b5e80b688f5005a8e4a1da8bfe5f
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:46:09 2005 +0000

    - See Issue Tracker id-13 "lnxi-patch-13".
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2077 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fddf46f275f27b20a05ff761c4e267fd619e9664
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:45:17 2005 +0000

    - See Issue Tracker id-12 "lnxi-patch-12".
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cf6df2afb5becca923e398521ae0e2d155cf3aa2
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:41:45 2005 +0000

    - See Issue Tracker id-11.
    - In addition:
    	Kept K8_HT_FREQ_1G_SUPPORT
    	to support older boards.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74cf993a54fd2d9a5730f415a60bdee0117028f2
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:34:06 2005 +0000

    - See Issue Tracker id-10 "lnxi-patch-10".
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a922bac99c185008a4008c2373093096dd4b776d
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:33:00 2005 +0000

    - See Issue Tracker id-9 "lnxi-patch-9".
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24ca17e3eabff21928117dc324aacdad6342a2da
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:31:56 2005 +0000

    - See Issue Tracker id-8 "lnxi-patch-8".
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 00e463f73036fbedf2626e6bdf52cb907355c1c3
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:30:33 2005 +0000

    - See Issue Tracker id-7 "lnxi-patch-7"
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc6281a8fedd68195414d6dc6744914054b3f39d
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:28:41 2005 +0000

    - See Issue Tracker id-6 "lnxi-patch-6-replacement"
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c0d2d783978bf41b4182349f4d313386d1b3bfff
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:26:19 2005 +0000

    - See Issue Tracker id-5 "lnxi-patch-5".
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b26cab08f11ff1d5daa517ee04bdf9ceb5ddc60
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:24:23 2005 +0000

    - See Issue Tracker id-4 "lnxi-patch-4"
    - In addition:
    	modified apic_id lifting to always lift all CPUs.  This may cause problems with older kernels.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a2c09a386970257188824f8901706c5579d5b50
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:07:34 2005 +0000

    - See Issue Tracker ID-3 "lnxi-patch3"
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9c4dd65ac5892530b70d93f586fe1de9f0bc1f7
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Oct 25 21:04:09 2005 +0000

    -  Issue Tracker ID-2 "lnxi-patch-2".
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b18e2048f717d0e274b557dbda0829e8d6d6451
Author: Greg Watson <gwatson@lanl.gov>
Date:   Fri Oct 21 00:52:52 2005 +0000

    Some compilation issue fix for PPC970 port
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d4edc2fcd003990228f505ce717c32b45831f2d
Author: Greg Watson <gwatson@lanl.gov>
Date:   Thu Oct 20 01:44:21 2005 +0000

    changes to support new ppc arch
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 58cb0bf1dfe1fa39760c3edcc68146fe6ed9d474
Author: Greg Watson <gwatson@lanl.gov>
Date:   Wed Oct 19 22:01:33 2005 +0000

    cpu options
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa9ef4195a12feb7b9ccc9bc9dc24806df13c022
Author: Greg Watson <gwatson@lanl.gov>
Date:   Wed Oct 19 21:55:47 2005 +0000

    trying to compile...
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5fc3aa73eb5e978bcd37061c49932b10e80c45c2
Author: Greg Watson <gwatson@lanl.gov>
Date:   Wed Oct 19 20:32:05 2005 +0000

    get include files right
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a83620fda39ed5de8d8cce2579d656825ab1a793
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 19 20:03:05 2005 +0000

    apache will sort build, but get build errors.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f084d4904c26ef0cd87ecd46b83a8fef3871290
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 19 18:19:26 2005 +0000

    initial support for apache.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d30f2e754e5f102dbd20de96bbbea028de28f37
Author: Greg Watson <gwatson@lanl.gov>
Date:   Wed Oct 19 18:18:10 2005 +0000

    start of 970 port
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e7884d1a36e22529c2e0741e07884e45b0a6d4f2
Author: Greg Watson <gwatson@lanl.gov>
Date:   Wed Oct 19 18:07:22 2005 +0000

    start of 970 port
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 58b971e79978448890f8afe688c849bf88f59afc
Author: Greg Watson <gwatson@lanl.gov>
Date:   Wed Oct 19 18:03:08 2005 +0000

    start of 970 port
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1cf26a88841765e7b9477e922199476a92ac4fa4
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 19 17:35:18 2005 +0000

    We are adding this obsolete, deprecated part to support the momentum
    apache board. We're not filling in all the support, since it appears
    nobody uses this part. If you really need parallel port support, add it.
    We hope to remove this part in future if the only board using it
    moves to a newer part.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20d943d9f982f777ac7d97bce56367fc4a2e6a95
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 19 17:02:34 2005 +0000

    adding support for dell 1850
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3182cad1a3835f411bd73cce06d2b3ebc4be4aa4
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 19 17:01:17 2005 +0000

    added the s1850
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab327a3c08a1bd8b33f09827a5f10d91ddb8727d
Author: Jason Schildt <jschildt@gmail.com>
Date:   Thu Oct 13 00:44:34 2005 +0000

    - Added explanation of device tree enable.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ab43fcc48992d46096842b17a00dd51dd835c69
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Oct 5 18:17:45 2005 +0000

    Updating FSF address in the code.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5dab7d650f7cbd71fcf2a48c1039376419c8192e
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Sat Oct 1 07:32:04 2005 +0000

    CK804 sata fix
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 803719a22ddead2da5b3687d176c008428831b85
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Sep 26 16:48:24 2005 +0000

    comments mods. THings are working better, so I'm less unhappy with
    this part :-)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4baa1673e211d1a78489be32cd988bef44fe6bb
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Mon Sep 26 13:54:32 2005 +0000

    * Added support for "fast" (64-clock) refresh
    * Added code to support remap window for 3 - 4 GB systems
    * Fixed premature configuration of true row boundaries that resulted in some sections of DRAM not receiving JEDEC commands (see http://openbios.org/pipermail/linuxbios/2005-June/011752.html).
    * Redefined RCOMP_MMIO so that RCOMP registers can be configured on systems where A20M# is asserted.
    * Disabled subsystem (vendor) ID configuration
    * #ifdef'd out suspicious looking code (see http://openbios.org/pipermail/linuxbios/2005-June/011759.html)
    * Added optional run-time checking of dual-channel compatibility of installed DIMMs
    * Move JEDEC SPD and SDRAM definitions into reusable #include files
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87888630b27ae64218abc1abcf06a213eb342d97
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 23 17:08:58 2005 +0000

    sc520 support -- ethernet works
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a25120a30fd1738fada2df0d5528430f9f9070c1
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 21 13:54:18 2005 +0000

    Bug fixes: read all 16 bits of DMA configuration; set up NMI/SERR handling in I/O space not PCI space. Comment out posted-memory-write code that looks to have been mis-inherited.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef79223156c52e39b7eef0b7df8adc24886828c7
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 21 13:53:44 2005 +0000

    Bug fixes: read all 16 bits of DMA configuration; set up NMI/SERR handling in I/O space not PCI space. Comment out posted-memory-write code that looks to have been mis-inherited.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b140d56f63a4e3d44a38ace759d2735f31f2bb68
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 21 13:51:30 2005 +0000

    Bug fix: enable secondary IDE only if enable_b is set.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3cec9c84339063aea115ec7f76fd5bef415dc7d8
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 21 13:51:12 2005 +0000

    Bug fix: enable secondary IDE only if enable_b is set.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b3d2d4d4412425bae14d810bfc4c10ae7d08043a
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 21 13:50:38 2005 +0000

    Rewrite i82801er_enable to do nothing if device does not have an enable/disable bit.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7557331605ecdcff1276979948dc8c4daf3ed2c3
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 21 13:49:44 2005 +0000

    Rewrite i82801dbm_enable to do nothing if device does not have an enable/disable bit.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e355b2ac604b8419b960ee830e31727a8d3e69b1
Author: Jonathan McDowell <noodles@earth.li>
Date:   Wed Sep 14 16:33:43 2005 +0000

    Cleanup and add more debug output to EPIA-M auto.c.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1718c4771b41c0f43c0c3d3970b5b390f97faa89
Author: Jonathan McDowell <noodles@earth.li>
Date:   Wed Sep 14 16:33:10 2005 +0000

    Make EPIA-M use CONFIG_TSC.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 708743379ae6798a2c5c2087bb860d2d4b54b6b6
Author: Jonathan McDowell <noodles@earth.li>
Date:   Wed Sep 14 16:18:30 2005 +0000

    Clean up vt8235_early_smbus a bit.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85793c2b3fbf20e3a844b69c919783a79763de31
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 14 15:40:07 2005 +0000

    Rename Intel 82801CA constants.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 706aed8eb9c1836d1b6c53b081f789a1d3afaa25
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 14 15:34:03 2005 +0000

    Initial revision.
    Based on i82801er and LB v1 code.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09e4ef670245566f1ee50759976babac17aae55d
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 14 13:56:25 2005 +0000

    Cleanup. Only functional change is to drop hard-coding of vendor/subsystem ID.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb065f0620b529573b53ba2bee11dffbd035cdb8
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 14 13:55:41 2005 +0000

    Add some P64H2-specific definitions, remove some generic PCI ones.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af0cf12eff778207013b4da80738a612f14a3056
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 14 13:54:32 2005 +0000

    Initial revision.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eccc357ea045d465411ea1fddb448c9c35a2149b
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 14 13:53:45 2005 +0000

    Abort cpu_initialize if we detect that we've lost a race.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 059182cc4fbdaff8c8548f28ee3b13326995dbf0
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 14 13:52:06 2005 +0000

    Print a failure message if a sibling CPU fails to start.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b1a5a4a920a59092b4c6d1d634e00786681a2b8
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 14 13:49:04 2005 +0000

    Initial support for Intel XE7501DEVKIT.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ffc83041b7d2600210e581f6ad897e9c14a60afa
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Wed Sep 14 13:48:32 2005 +0000

    Initial support for Intel XE7501DEVKIT.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71ad2f48c5160b709ed85489c5fb3176563b4bb0
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Tue Sep 13 14:56:44 2005 +0000

    Moved E7501-specific definitions here from raminit.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61764f45dca2c5d5b3faaec1c912f3d50e8bd8e9
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Tue Sep 13 14:54:25 2005 +0000

    Initial revision.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e91619ac0595f1fe8adf61df75e79ecf79800e86
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Mon Sep 12 18:55:23 2005 +0000

    Initial revision.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8cbc4751d1991f02efdefcaa8c91c187bbc1d987
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Mon Sep 12 18:43:27 2005 +0000

    Don't write to CMOS when HAVE_OPTION_TABLE = 0.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d94e1d6e9dc794401041e0eb4de20c741d3ac71b
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Mon Sep 12 18:41:30 2005 +0000

    Relocate the GDT to reserved memory, so it won't get clobbered by elfboot(), etc.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b945c7cd8a5cc7dab9fdded8172cd575b6129c9
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Mon Sep 12 18:40:00 2005 +0000

    Attempt to make comments more descriptive.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7c70bcb3ad77596870d6616388df43d28ec9685
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Mon Sep 12 18:38:10 2005 +0000

    Fix hang during secondary CPU sibling init caused by nested spinlocks.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e50570112facc2e80d4456f0a21dbe3e85491453
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Sep 12 15:20:28 2005 +0000

    sc520 now builds fine. On to testing.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e118a047b95112c1d1a28be43e151c1123aa07de
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Sep 12 13:43:59 2005 +0000

    moved to include/cpu/amd/sc520.h
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 64473580ff73497b1ece9879c1f2c04601300cb6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Sep 12 13:42:56 2005 +0000

    added include file for sc520
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c06ca3af71e79345918305e3e0e510cf40d6d44f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Sep 12 13:42:12 2005 +0000

    updated to new svn repo
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ccf52a92f4f0164f03a56a2052ab7e99c8863ef9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Sep 12 13:40:10 2005 +0000

    updating to working version from my pre-svn repo.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f25710285e1ee93ae85fb682d48a6aac3c3b2f8
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 9 21:03:08 2005 +0000

    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a83c99bb971226180b1d2e50771039a14fd67ae
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Fri Sep 9 20:06:21 2005 +0000

    Modifications for building LinuxBIOS under cygwin.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc8a3d2c353926e4917aa71996d5010ddb2036e3
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Fri Sep 9 20:05:03 2005 +0000

    Remove unnecessary #include that prevents cross-compilation with gcc 3.4.3 under Cygwin.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 740bb2a8ed7aae17d5aa9b7486c40d5249a870ae
Author: Steven J. Magnani <steve@digidescorp.com>
Date:   Fri Sep 9 20:02:52 2005 +0000

    Correct transposed arguments in pnp_set_drq().
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 246ae2129eb091da06cf6275bd503dd5730060dc
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Sep 8 17:17:25 2005 +0000

    simplify code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit afa190e046b2f45985c78d4550cc43f96764f33f
Author: Jonathan McDowell <noodles@earth.li>
Date:   Mon Sep 5 09:30:01 2005 +0000

    Add VIA C3 Nehemiah CPUID, as reported by Doug Bell.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ded1368b1aceb47e7d51dc129586e030865626e5
Author: Jonathan McDowell <noodles@earth.li>
Date:   Mon Aug 29 09:54:25 2005 +0000

    Crude fixup of config files currently non parsable by buildtarget.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e251c42197225d3783699343e0805c425aeae8e9
Author: Hamish Guthrie <hamish@prodigi.ch>
Date:   Wed Aug 17 04:48:17 2005 +0000

    Changed udelay in delay_tsc to be more be more considerate of single
    processor environments.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d291aa6a2e5ae309a805c602a3768b6d86d8a2d
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Aug 10 22:51:55 2005 +0000

    more removal for obsolete VGABIOS support
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd7a304bc758df1653e0645f447d1901500442d0
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Aug 10 22:44:30 2005 +0000

    remove obsolete VGA support for EPIA
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 043b409904c8663a2df1f651a91da6366eff6c9b
Author: Jason Schildt <jschildt@gmail.com>
Date:   Wed Aug 10 15:16:44 2005 +0000

    Undoing all HDAMA commits from LNXI from r2005->2003
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 27b85118807be6e2fbf9bbd65d119538ff276db8
Author: Jason Schildt <jschildt@gmail.com>
Date:   Wed Aug 10 14:31:52 2005 +0000

    - reverting back to original romcc.c before hdama checkin broke all
      other builds.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e44b422b3b26a4ce5b98fca12d0f3ef7d7af110
Author: Jason Schildt <jschildt@gmail.com>
Date:   Tue Aug 9 21:53:07 2005 +0000

    - Merge from linuxbios-lnxi (Linux Networx repository) up to public tree.
            - Special version for HDAMA rev G with 33Mhz test and reboot out.
            - Support for CPU rev E, dual core, memory hoisting,
            - corrected an SST flashing problem. Kernel bug work around (NUMA)
            - added a Kernel bug work around for assigning CPU's to memory.
    
     r2@gog:  svnadmin | 2005-08-03 08:47:54 -0600
     Create local LNXI branch
     r1110@gog:  jschildt | 2005-08-09 10:35:51 -0600
     - Merge from Tom Zimmerman's additions to the hdama code for dual core
       and 33Mhz fix.
    
    
     r1111@gog:  jschildt | 2005-08-09 11:07:11 -0600
     Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL
     r1112@gog:  jschildt | 2005-08-09 15:09:32 -0600
     - temporarily removing hdama tag to update to public repository.  Will
       reset tag after update.
    
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc2454eb944c2ea9201bd650d7bc9942d4653a6c
Author: Jonathan McDowell <noodles@earth.li>
Date:   Mon Aug 8 08:16:23 2005 +0000

    Clean up vt1211 SuperIO support and make the EPIA-M config use it.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1950783e00ab866ea2c8d2eba7527cab7ec57747
Author: Jonathan McDowell <noodles@earth.li>
Date:   Mon Aug 8 08:15:22 2005 +0000

    Fix up the VT8623 northbridge support.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 885b267594480bed52adc083c9136eb3a23eb6b2
Author: Jonathan McDowell <noodles@earth.li>
Date:   Mon Aug 8 08:14:34 2005 +0000

    Fixup the EPIA-M motherboard config to use the new VT8235 setup.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53365f511d6c892d4f1e3d478b2188356f9c42b5
Author: Jonathan McDowell <noodles@earth.li>
Date:   Mon Aug 8 07:59:15 2005 +0000

    Tidy + compile fixup VT8235 southbridge support.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8bb8970716183f8f5a9c889b35cbb85b2d37b34e
Author: Jonathan McDowell <noodles@earth.li>
Date:   Mon Aug 8 07:52:20 2005 +0000

    Fixup EPIA-M config file so it's actually parsable by buildtarget.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1000159ee54b279de8356f3745e303d55aede754
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Aug 6 23:03:02 2005 +0000

    update target config file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce8cba4d046492e5423e4d247045bec206b63716
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Aug 6 22:37:26 2005 +0000

    reclone ts5300 from digitallogic sc520 board
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0c6c07348f0ce1438e2dddb3a7821fa7bd932bfe
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Aug 5 19:22:59 2005 +0000

    delete obsolete files
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b4a54424df27a396efd0ccadb959550ceaa9038d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Aug 5 19:02:49 2005 +0000

    FSF changed it's address
    http://savannah.gnu.org/forum/forum.php?forum_id=3766
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cad91fdd795b671b2064b0cc68d82e25ed4c10d4
Author: arch import user (historical) <svn@openbios.org>
Date:   Fri Aug 5 18:55:52 2005 +0000

    more khepri cleanups.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 19ae9403c20dc057690bb159902a5c61515c11ee
Author: arch import user (historical) <svn@openbios.org>
Date:   Fri Aug 5 18:53:31 2005 +0000

    cleanup of khepri target
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2bef9a960a45e7fa0ebcb8a126f03740cbc66b0e
Author: arch import user (historical) <svn@openbios.org>
Date:   Fri Aug 5 18:41:38 2005 +0000

    small update
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0de60ee3344dfd26cd02672a852656e45b88252b
Author: arch import user (historical) <svn@openbios.org>
Date:   Fri Aug 5 18:34:33 2005 +0000

    remove description of obsolete, already dropped patch.
    
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 438938de02ac21d7587457c685dc2259b23eff3e
Author: Jonathan McDowell <noodles@earth.li>
Date:   Thu Aug 4 17:07:25 2005 +0000

    Fix up default Config.lb files to help aid autobuilding of all targets.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9528b8883eba65bf49c3b0d60b415e53fa05f9b3
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Aug 4 14:59:33 2005 +0000

    GCC4 fix
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 053d7220072cc08450f2cb7d4f04ed4b2ba80633
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Aug 3 15:04:53 2005 +0000

    bug fix from Jonathan McDowell <noodles@earth.li>
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09952c1970c27b48a118fa67deea52abdafe8d5a
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Jul 26 18:27:13 2005 +0000

    move x86 CAR related stuff to arch/i386/Config.lb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1748bf28a75166e09963d4252cef793c7bff1af6
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Jul 26 16:39:42 2005 +0000

    Added IBM e326 support. VGA works too.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd1505dae70642fa3400224bf1d48730c9985592
Author: Greg Watson <gwatson@lanl.gov>
Date:   Wed Jul 20 18:33:21 2005 +0000

    backed out
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 78e0b0edf4b58bddb9f3782240a0279dedea66ec
Author: Greg Watson <gwatson@lanl.gov>
Date:   Wed Jul 20 18:28:12 2005 +0000

    Updated ep405pc to latest config system.
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 304f24c2d2ed21ee807d4df78d35424748cb4102
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jul 8 02:56:47 2005 +0000

    missed cache_as_ram_auto.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 13f1c2af8be2cd7f7e99a678f5d428a65b771811
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jul 8 02:49:49 2005 +0000

    eric patch
            1. x86_setup_mtrr take address bit.
            2. generic ht, pcix, pcie beidge...
            3. scan bus and reset_bus
            4. ht read ctrl to decide if the ht chain
               is ready
            5. Intel e7520 and e7525 support
            6. new ich5r support
            7. intel sb 6300 support.
    
    yhlu patch
    	1. split x86_setup_mtrrs to fixed and var
    	2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
    	3. in_conherent.c K8_SCAN_PCI_BUS
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14cde9e96a777f9d75016a13b23fab0480515f58
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Jul 7 21:31:50 2005 +0000

    add ibm e326 support, basically it is the same as e325
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb07bf4acaf7a86b2dd5c38beaa43f5d06c54e7b
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 18:17:43 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-62
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    add eswar code in intel car to disable Hyperthreading
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59140ccdf384346ab0a6112baee175a01ed5bd9f
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 18:17:35 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-61
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    write_pirq_routing_table for x86
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 80e3d96d0aeb52a1e648d6ca3b88611469dd8584
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 18:17:33 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-60
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    More Via EPIA
    
    more via epia stuff, including the trival but fatal bug in auto.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f642a4795ad478baa731720b214c2ccfbdc90c35
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 18:17:30 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-59
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    S4880 mainboard Config.lb
    
    Comment in the Config.lb shoud be '#' rather than the C++ '//'.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9a0e03a6827560e565079b36c63c371c68fb7f6
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 18:17:28 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-58
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    auto.c and failover.c
    
    convert mainboard auto.c and failover.c to post DOM era
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4b26d77e2088924a3eb81cf9e3f16f6ade4578b
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 18:17:26 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-57
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    shit
    
    put "use CONFIG_USE_INIT" in the global Config.lb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7dec0f9ac33b1053de5045d6d72d6f882e0c782a
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 18:17:06 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-56
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    remove junk in s2885 cache_as_ram_auto.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74d081a12c60a9a15f9ec7efde3cecef9732d0c9
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 18:10:16 2005 +0000

    cleanup due to faulty sync
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eec65a6938fbb53d78fb9a40289c539f2181e98d
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 18:09:13 2005 +0000

    cleanup due to failing tla-svn-sync
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d8620eecb35178b73e703afe779b894db723af0
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:23:57 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-55
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    intel car to x86 car
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54d6b08f010d2dc458184a4845f8fbdaaf0da429
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:17:41 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-54
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 93cabf12d1394e74818c9028789d9fe875147980
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:17:39 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-53
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    more safe stack in ram for cache_as_ram
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c5d9e3b6dd2956a8864ab11ed89ddcff671b72c3
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:17:37 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-52
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    USE_DCACHE_RAM instead of CONFIG_DCACHE_RAM in raminit.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ca7636c8f52560e732cdd5b1c7829cda5aa2bde
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:17:25 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    cache_as_ram for AMD and some intel
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b2ed53dd5669c2c3839633bd2b3b4af709a5b149
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:16:23 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-50
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    This now boots to the point of passing the memory test in auto.c. But: we still don't have it working after the "Jumping to LinuxBIOS" step
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69c79d232e73a9b58a396c743cf0e3d1008ed4f5
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:16:21 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-49
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    this is a version that  does not fail, but memory is still not up
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a796d1ffbc3fb9a5df5a7383628fc28ae50a27c
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:16:19 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-48
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 897c78bd152084e56c32206f76f5725e20ae6a9d
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:16:15 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-47
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52871c4ad54e08e80da891bd399d63f71d9a87a3
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:16:13 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-46
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    sc520 fails after NOP
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c9e2af9ce671c97759386013e16530de95a7842c
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:16:11 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-45
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc811185703a1ee01964c938d428d66e96afb30b
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:16:09 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-44
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    Correct VGA support
    
    Make the VGA support for both VGA and no VGA cases.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 785b1b6e994d4d6ffa78e84b9a0353d54ed201bb
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:16:07 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-43
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    Cosmetic
    
    Cosmetic code reformatting and message output
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd0f828412e9bcddd1fc6c64050bbb56c34bec0a
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:16:05 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-42
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    missing commit for emulator update
    
    Which one is more stupid? TLA or me?
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8fb9a5ae3ba8f6e71ac637208a196b095824ad66
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:16:03 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-41
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    Onboard VGA for HDAMA
    
    Added onboard VGA support for Arima/HDAMA
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c9dbc1a04c8064fcb82ebc1aeb610e9f0cdbd12
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:16:00 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-40
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    ibm e325
    
    Bring imb e325 to post device object model era
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34120d1b4ffecca74a7ab327987f911308ba1247
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:15:57 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-39
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    TLA sucks again
    
    This is the third time I try to commit only the emulator changes.
    I hope this patch contains the emulator changes only.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c8cd59f3c9248f0954a5cf215dc3652ccfc8da5
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:15:54 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-38
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    emulator update
    
    x96emu update from Paulo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e5fbd6fc03df87c9276b08219ca15ad17c43dac
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:15:52 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-37
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    TLA is really diffcult to use. How am I going to
    roll back my last commit ?
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit acfaeceffd8b97715905f074a76e0d12f0d83889
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:15:48 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-36
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    emulator update
    
    Correction to the reduce emulator from Paulo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c3f37cb5f741d7b2ba7852a16ffb82ee40968e9
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:15:46 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-35
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    s2881 dual core config
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef03afa405b049a172146aab93cfb81fb21f3945
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:15:30 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 014c3e185fe8e1455e56efeb496715a67ce292bb
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:14:10 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-33
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    remove lsi/53c1030 in MB Config
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 056d6195d8b3bf219d7f3e3207c5ffec145290cf
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:14:08 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-32
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    set CK804 nic mac addr in MMIO instead of pci config
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a07e6ded1c6270d4bb768cc3d6abd7db1990f52e
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:14:06 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-31
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    nvidia onboard lan support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98d0d30f6b8237f888cd44b33292319e3c167a47
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:13:46 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-30
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    Nvidia Ck804 support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 577f185d382c8130f20f0ee7e8466ed8bbebbacc
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:11:02 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-29
    Creator:  Hamish Guthrie <hamish@prodigi.ch>
    
    Added NSC pc97317 super-io and added fill character option to config/Options.lb to speed up flash programming
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fcb591ac680f2b82aacb01e63a4ab91724e1e464
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:10:06 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-28
    Creator:  Hamish Guthrie <hamish@prodigi.ch>
    
    Added Eaglelion sample board for AMD GX1 platform
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c46ce1373ce21155f0a4b3d9feeff308fb3cd93e
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:09:21 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-27
    Creator:  Hamish Guthrie <hamish@prodigi.ch>
    
    Added GX1 cpu files
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d24d6993b6d7bcf7977d74d081e718e1b076d1b0
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:06:46 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-26
    Creator:  Hamish Guthrie <hamish@prodigi.ch>
    
    Added AMD GX1 northbridge and cs5530 Southbridge
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e83d70a4393674ac3b54d1343533fc1d2c489d0
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:04:01 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-25
    Creator:  Hamish Guthrie <hamish@prodigi.ch>
    
    Adds a tree for the Eaglelion mainboard. This board has an AMD GX1 processor in a typical Mini-ATX format with a few ISA and PCI slots.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b47a4d3347972704cc05b1a55c0af582764815aa
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:03:05 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-24
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    AMD MB IDE enable in Config.lb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1940 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b78ea7a28b4c6c703a10138cc3b6596854fff6f
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:03:03 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-23
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    add in stepan's raminit code for the sc520
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a39e0b67ce13f63ebf23282f7b8f1ae1e803d01
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:03:01 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-22
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8b8655647a6b9bf23944cb8efe09719cf132339
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:02:59 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-21
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97c8b517097d81191763ad77343ef1f0a7970ffe
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:01:10 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-20
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1936 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 708023cdea14f2b92a88c582f57fee138c5e8ea2
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 17:00:18 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-19
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c8c720a80138af945f8f5b7fa9d0c6400f23fc9a
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:59:18 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-16
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    add cpu directory and files for sc520
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 613c72abc472307d68a07f8af8e91d9b5ba49a15
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:58:30 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-15
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0a864f51a790bc550f1234d329a8cae919cf93d5
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:58:28 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-14
    Creator:  Ronald G. Minnich <rminnich@lanl.gov>
    
    add console options to via/epia/Options.lb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a2893fd9d8df874b6c6f109b33c63a1b90c9edc
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:58:26 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-13
    Creator:  Li-Ta Lo <ollie@lanl.gov>
    
    trival test commit
    
    This is my first tla commit
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c8cbac3c3c5db374b640e9f9770b76b5078398e
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:57:34 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-12
    Creator:  Stefan Reinauer <stepan@openbios.org>
    
    Add timestamp to mkOptionList.py
    
    mkOptionList.py: add timestamp
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2305364397f9d4b4722e594069d4e2960cc35911
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:49:59 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-10
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    pci_rom.h  smbus device parent device print
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca0084ef9bed2f67618d3d183afb0a2d413595ab
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:49:56 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-9
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    rm tyan VERSION
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0093e36d9b308373dbc513d075ed7ec2bd114ccb
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:49:54 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-8
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 72c3b053d86c68a9e5454a79f0808c898170e21e
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:49:52 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-7
    Creator:  Yinghai Lu <yhlu@tyan.com>
    
    ide_enable in MB Config and jmp_auto ( it will make start in the 64k boundary)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd6067425858d136418986fa77927a6ea76b79ee
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:49:50 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-6
    Creator:  Stefan Reinauer <stepan@openbios.org>
    
    fix dram initialization on island/aruma
    
    Never trust the specs. :-) I messed the different
    cpu numbering notations up before. This makes my
    wrong 8x patch obsolete as well.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14a0f7951a1f3a0b8af466da89dc68b40b598bfa
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:49:07 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-5
    Creator:  Stefan Reinauer <stepan@openbios.org>
    
    start a new changelog
    
    move old changelog away and start a new one that automatically contains
    all checkin comments.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1924 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc5be4791979056cad8a1f718984ba14d73904db
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:48:04 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-4
    Creator:  Eric Biederman <ebiederman@lnxi.com>
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4966de81c341aca7e2ae8f971a112acfaeba89b1
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:48:02 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-3
    Creator:  Eric Biederman <ebiederman@lnxi.com>
    
    Add read[bwl] write[bwl] to arch/io.h for i386
    
    A pending patch requires needs this and ppc already has them
    so it is a good idea to implement them :)
    
    I don't know why this was not implemented earlier.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f8eb7a072f10a5ecea9e879830dce4002ff86bd
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:48:00 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-2
    Creator:  Eric Biederman <ebiederman@lnxi.com>
    
    Bump the version number with the switch to arch
    
    I need an arch test case so bumped the version number.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29ff7b8a3022f8059d5b01147316be1f51b44baf
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 16:47:56 2005 +0000

    Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-1
    Creator:  Stefan Reinauer <stepan@openbios.org>
    
    fix quartet build
    
    increase quartet image size to get it building again.
    Untested since currently I do not have access to a quartet
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d8a7d29723bbdfb00b4104cd383a03b3b6144d8
Author: arch import user (historical) <svn@openbios.org>
Date:   Wed Jul 6 15:39:11 2005 +0000

    cleaning cvs leftovers
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c4c07d4b3a0e9d60fec8c4b9f753514da367087
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Mar 4 22:08:55 2005 +0000

    fixed a bug cause failure on some expensive VGA cards
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be977a14d18e4bda743a9cda25d3d76dfdfaad97
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Mar 4 22:03:07 2005 +0000

    some comment in ACPI table
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef5c64cca5c9a0a7461a18cc8db45ffea9dee5e8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Feb 13 22:42:14 2005 +0000

    simplify
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f9f34228ac05d1a937af612da3792523afd2af1
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Feb 9 17:34:55 2005 +0000

    move apic before nb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f536e7a02be10204609e787bde26242eb937178
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Feb 9 01:25:17 2005 +0000

    VERSION and rom_image_size
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ca78760c7950fa614d4e330da1095145b959793
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Feb 8 11:55:42 2005 +0000

    add cross compiling for abuild.sh
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ab193b52f2942b12956ff4caddfa87b7544f4aa
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Feb 8 11:53:25 2005 +0000

    larger default size
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e943fdb178264473f20df27a18967e72c1503530
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Feb 8 09:35:19 2005 +0000

    * fix build without patches.
    * create vital ACPI information from the linuxbios device tree.
    * pass linuxbios information into dsdt.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df08a1d19697fe4bfc956c5664e8eb5ba6669bd6
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Feb 8 09:29:19 2005 +0000

    generous iteration on the device tree removed.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e30042da3ec36dc1b105c5c082dc098131456b78
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Feb 8 09:11:40 2005 +0000

    fix comment
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 55ba88da9e4df2d47d2eba8c4e3e67a37ae06ed7
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Feb 3 05:35:32 2005 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aabf7f93b37234476c4fe73a52bc2ca20fed9919
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Feb 2 15:17:51 2005 +0000

    make debugging a bit more useful
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4b24ceedbfda80d90632ce68e9da3fc411de9f1
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Feb 2 15:08:23 2005 +0000

    add patches that were rejected in discussion in case they are still needed
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc4dda703b3e7a4ce02b95ba53aa511fe43d2239
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Feb 2 15:03:37 2005 +0000

    new port: island aruma
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d909049bc036bcbba6637b7ae5c65abf165fb09
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Feb 1 01:22:57 2005 +0000

    8 ways works now
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6360187e9e01a27b7f10ce8910ec01cee41fa329
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 27 22:48:12 2005 +0000

    spare one more mtrr
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 830435bb16e8e8dcc1e44f52b0603fcec4345664
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 27 18:38:10 2005 +0000

    coherent.c don't need to read incoherent ht cap
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90b3e09e63565416cc1b72d6f613507a3f5365bc
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 26 22:00:20 2005 +0000

    comment out ht_setup_link
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ff8b96ec51eab90b593ca181e5bf1f3d03e4f114
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 26 17:57:34 2005 +0000

    pre_d0
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb2b06bc3fa6bfaa6ba597629495f39e244d8b5e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 26 09:58:49 2005 +0000

    target port may need to checksum
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 898061220b40a9af688db905689a2789619608c3
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Jan 25 02:17:44 2005 +0000

    -Make 1, 2, 4, 6 installed cpu works.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a2798d28be226d4b037dd1f694d0434034b0eea
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 21 22:58:15 2005 +0000

    move apic cluster before pci_domain in MB Config.lb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5d9af41053f2cd66503b6e8a58676e97a3bbf85
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 21 22:02:09 2005 +0000

    move apic cluster before pci_domain in MB Config.lb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e324731152fa1a64aa210c1f40b8b2afa3dc1623
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 20 20:41:17 2005 +0000

    linkb_to_host
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f5ef301a70c78fd87008caaf9935e5abbbf062f
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jan 20 18:37:00 2005 +0000

    Fix typo in microcode header file include
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d808849a2c4ed90acf3a6f53a0cc09bfb28ca80a
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Jan 19 23:21:00 2005 +0000

    removed unused code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bec039cb93b72b068370662933d961b1cd4aeaea
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Jan 19 23:19:26 2005 +0000

    minor reformat
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af021575308fffc104a7add2ba8183cef079876c
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Jan 19 20:38:09 2005 +0000

    add config option for vga
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d606885166b5425ef648521fe7947fb7b608802
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 19 18:09:58 2005 +0000

    linkb_to_host
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d06b7831866b8ff315e483eeff1b8bd5f93bab69
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 19 14:14:10 2005 +0000

    make it bigger
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b809cb830617058a8a9ee7362417b276fae1345
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 19 14:13:02 2005 +0000

    universal acpi fixes.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd1a959cb2e8eab9a350d2f35eb4a78258732115
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 19 14:12:02 2005 +0000

    more universal acpi code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 777224c7cffe90e4c439cb4b0b111b1a60f82f69
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 19 14:06:41 2005 +0000

    - make acpi usable for more than one motherboard.
    - make pirq normal debug a little bit nicer
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26b2922f1cf61a5076ea81fcd764cce94fc5900f
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 19 01:21:05 2005 +0000

    linkb_to_host
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd915e9672ea555fb1602b2d2d1ec85452fc7efd
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Jan 18 13:31:23 2005 +0000

    No fallback image in this case
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4ea158b2850f2fb1407efc1dc29bb9998abdb127
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Jan 18 13:26:34 2005 +0000

    this is obsolete.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54ab3115e3adc2d7bda94be6371654896bc9d33a
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Jan 18 03:10:46 2005 +0000

    class code reverse
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 328852d24353f439e0419b50aebce39482f6a5cd
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Jan 17 23:47:55 2005 +0000

    fix reboot broken
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f1085b433187f64f3d12961faad6e745a42c286
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Jan 17 21:37:12 2005 +0000

    linkb_to_host and addon display card override onboard card.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c507e4de737108b6acb022ffd1a0b5678ea8062e
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Jan 17 21:32:36 2005 +0000

    linkb_to_host
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 18588446479fbac700d49e3d5b0061e436ca9be6
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jan 17 11:08:08 2005 +0000

    Make building with different libpci versions easier. The defines might go into
    official libpci for 2.2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1d6b46060c303f7902ec414f544984af019b9908
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Sat Jan 15 04:12:27 2005 +0000

    can not enable cache for ram in auto.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e562738f8c80ea15ffa28e63c17fdd3c82e876af
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Jan 15 00:29:10 2005 +0000

    add vga.h / needed by vga text console.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9e4faef7dbb6848c1ea6a21994031d191b209c34
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 14 22:04:49 2005 +0000

    CONFIG_PCI_ROM_RUN
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 688238a50c61993db8667552cdae624e73310239
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 14 21:54:16 2005 +0000

    CONFIG_PCI_ROM_RUN
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e51b8a3723c4ef47da1eceee23ca845b6ce002f
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 14 19:26:52 2005 +0000

    amd version mtrr early
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24f542f47811ab43aa79bef6b55543b268a492e2
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 14 17:17:55 2005 +0000

    onboard pci_rom second run
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bcde1618da1bcaa26419f23d7883064ce1874502
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 14 05:34:09 2005 +0000

    onboard pci_rom disable onboard
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d57e75606501e2f7b72d4377661d8cf8dece0999
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 14 02:59:24 2005 +0000

    onboard pci_rom finally done
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e1f7c7fe0df557d0ad231a97535a44b8f13e5d3b
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 13 21:37:29 2005 +0000

    ht opt bug
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a1222d50cb4c533fa01b83613f58b5c94b880a3
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 13 19:23:24 2005 +0000

    lift apic id fix
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7870ace3941de283f1f8c2f0783f80f897651e2
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 13 19:14:52 2005 +0000

    onboard pci_onboard works
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e74f91a9017ab5412060f71cbf0eb78f53231947
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Jan 13 18:58:41 2005 +0000

    cosmetics. \n is enough here.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6308d58c92b3fd307b25b64563a2846ab6e9ef84
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 13 18:42:22 2005 +0000

    onboard pci_rom
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d8ad7df7002963fb42d59fda6dbc42e6003fd065
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Jan 13 05:51:48 2005 +0000

    fixed a logic bug
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bc5399aa6eeef558edaab07d94340b3780661c61
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Jan 13 05:44:16 2005 +0000

    better embedded ROM support, done blindly
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 75f5b559e69efa17de6bda7913321656e83e0314
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Jan 13 05:21:27 2005 +0000

    remove #include chip.h
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 214ea8a9df759b08dfaaa08f3414b6d0d628010a
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 13 03:50:18 2005 +0000

    onboard pci_rom
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 77cbb99a578bcd5e929e13cc07871d8a5dc15e4b
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 13 03:36:38 2005 +0000

    onboard pci_rom
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c615429d39d7e14f7ea97a63cabcb616d5c2438
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 13 00:04:56 2005 +0000

    onboard pci rom
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c47eeb2cecb65047cf4c6e449b8763ab47c5c8d8
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 12 23:58:49 2005 +0000

    onboard pci rom
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7715f26590fc228009686f12ff143ced7d534823
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 12 23:52:07 2005 +0000

    onboard pci rom
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 515f6c729e0b4878884e74e21d00dbc4b66dcdd9
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Jan 11 22:48:54 2005 +0000

    works for PCI vga cards too
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 51990b350a03eb718f6af0890a2f9a42373106ca
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Jan 11 16:35:56 2005 +0000

    removed validation code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ce1590355efb611fcba12e243b9a5474bda2288
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Jan 11 16:33:31 2005 +0000

    fixed abs() impelmentation
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1854 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8b0356c2c9136493f79d9faddbda1bfac7ca687e
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Jan 11 03:18:39 2005 +0000

    use Paulo's reduced version
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3678ad8e38abee296221cd33e2cbc1e5181f715f
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Jan 11 02:48:22 2005 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 883b8793c9777544101261ebcbed6088e0df1593
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Jan 10 23:16:22 2005 +0000

    added PCI expansion ROM support,
    works for some ATI and Nvidia AGP cards now.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ee97999ad03c2134049ba4554e1f5036924cd6d
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Jan 10 22:27:47 2005 +0000

    nodeid
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a23863a3a43c23b8405524406ddff11edb0a407
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Jan 10 22:20:51 2005 +0000

    nodeid
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20a2a570929820b197476a48291973c0fb62d373
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Jan 10 19:20:38 2005 +0000

    no siblings yet
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0fe9902b508c3421b9a55d5d2a7fc6154f7f2c77
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 7 21:15:39 2005 +0000

    enable apic ext id to keep bsp using apid 0
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90a04ee5a93c0e99cbc46febf5556be6affef03b
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Jan 7 21:12:05 2005 +0000

    enable apic ext id to keep bsp using 0
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31ce35e8ab42cd051c660ed752febc89632e92c6
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Jan 7 04:50:33 2005 +0000

    remove ti_firewire.c, it only enable the bus master
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 84a8028349c022523ca9daaf3beae92952bf5b2d
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Jan 7 02:42:53 2005 +0000

    fixed indentation
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 953e0f6afee264411997d668e94e46a9d36f5151
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 6 04:55:19 2005 +0000

    add NC support to spare mtrrs for 64G memory stored
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1bc5654957dee91bbc20bcbd9484fce09db77a4a
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jan 6 02:23:31 2005 +0000

    clear dead link bug fix and opt_link_read for non coherent link
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6068ec9ef158afb42d9d91fa1509fee5f844be4
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 5 21:13:09 2005 +0000

    compile fix
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb1255ead2398f933489746bc893eb91fa4d2306
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 5 20:57:33 2005 +0000

    enable apic ext id
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23202a9870a76c45fdd57771aa5546ebedf649b3
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Jan 5 20:29:05 2005 +0000

    enable apic ext id
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a734f5372156aac1270700421ded7358291c2f4c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Jan 4 15:16:19 2005 +0000

    adapt to freebios v2. still doesnt handle comments correctly.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a335402bec6511c11ab54c943287e7be7fb1672d
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Jan 3 20:54:43 2005 +0000

    serialize cpus for >2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e089f00ad494ffbb91f605b09b59375ff4eb30b3
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Jan 3 20:00:36 2005 +0000

    optimize read link bug fixed.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bf0ed605149af3560dcc5e6c014c4acb70b9a831
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Jan 3 19:54:47 2005 +0000

    Dynamic RT with 4 ways test OK.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85e76c6af6d67942850113c148f0b14bc05351d8
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Dec 27 17:53:45 2004 +0000

    now rom_address is one of the resources
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e7c26a70ec3307d3d2041df1c03937c045479112
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Dec 27 17:52:54 2004 +0000

    remove unused options
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit af0cc3e1c4bfd624f4ca08d256c627b1838432a1
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Dec 27 17:52:05 2004 +0000

    start consolidate various borken vga support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e8b1c9dbd15269f1418e8270cd8f93f2ef36af2d
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Dec 27 04:25:41 2004 +0000

    clean up VGA and Expansion ROM support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5b772cca556bd4d5544a6da49c59f51709921766
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Dec 24 04:42:59 2004 +0000

    default link bug fix
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a5b4962a7202ac9ba6eeef8ac9550c7907cfb2a
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Dec 23 21:48:01 2004 +0000

    Allocating resource for Expansion ROM
    
    More correct resource allocation for legacy VGA on K8
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a804a713a23ec9662933f7452f1d3235f7a69474
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Dec 22 19:02:41 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e2b2006406cb6b3013557eddd43bdb35eb6b78b5
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Dec 22 03:14:50 2004 +0000

    update broastcast table for K8 4p above
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a5d99bde4d7cc6287079361422a8b95aed3b025
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Dec 22 00:58:50 2004 +0000

    8 ways support changes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1de80941c290ccbdce1a33f2a61f36184d040eff
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Dec 21 22:14:12 2004 +0000

    amd k8 routing table creation dynamically support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c956bbc19c5dec3b882db5ecc9a2074f3afb1e8
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Dec 17 21:08:16 2004 +0000

    non coherent ht chain setup automatically
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20bd731b75cbdb4f2045146ecc92073b368ae402
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Dec 16 10:38:38 2004 +0000

    target config fixup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 970990800ee2862119a012615a51c4ff3554e34e
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Dec 16 02:44:25 2004 +0000

    btext fix
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42b37443ac4f66042a8472938b876e87f66270b4
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Dec 15 16:09:06 2004 +0000

    shame on me.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b14e85111050c7290c1d2d8119f9950528106e4f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Dec 15 16:08:18 2004 +0000

    obviously broken
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 140a3a11ad24d2f15430fc1dc5719c2d5c45eebf
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Dec 14 01:56:55 2004 +0000

    add dump_pci_devices_in_bus
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ec01aa98d0a12f857137c469b15226e30a625331
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Dec 10 20:50:43 2004 +0000

    - Fix the definition of the linuxbios table so all of the compilers
      will generate the struct lb_memory_range the same.
    - Add a few pci_ids.
    - Small readabiltiy clean ups to debug_dev
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7dd86970619976265c2cc167668fa11da07e139
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Dec 10 16:18:43 2004 +0000

    mptable tool
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ac60f8dfe778e7cf0c6e6bd6708efcc7bc91266
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Dec 9 00:37:03 2004 +0000

    get config tool satisfied.. let's see if we get this working..
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 257a58b60d2cdb088d253600bdb45f60e3664fec
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Dec 8 20:10:01 2004 +0000

    added -E option for chip erase, remove duplicated code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 19b6945a40d17703124db0a5f3259bb8e7d6dff7
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Dec 8 02:10:33 2004 +0000

    add retry to write_byte_program_jedec(), 99% success rate
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c48822ae916eb8f14389f1dbb21cd11ab60fe1ab
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Dec 7 17:19:04 2004 +0000

    enable LPC decoding for 1 MB more addresss, for supporting SST49LF00xA/B
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb7c3935c953c7631af8ad8422361099c70b42d8
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Dec 7 03:15:51 2004 +0000

    SST49LF00[2,3,4] should use
    the same driver as 49LF008
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a81285409cf09091b1704d126a38a5126030d2b
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Dec 3 22:39:34 2004 +0000

    allocating resource for legacy VGA frame buffer, it is not 100%
    correct but it works anyway.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 845e8df6738495d11922148d649a666faf374aa0
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Dec 3 19:07:45 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7213d0f513c2a0dbcacbf0a811d01322cd82d25b
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Dec 3 03:39:04 2004 +0000

    i2c mux support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57b6786168683e33c1c6c2d8df6a1e8c0246fbde
Author: Mark Wilkinson <mark.wilkinson@2pmtech.co.uk>
Date:   Wed Dec 1 16:59:05 2004 +0000

    Updates to raminit.c correcting for new version of smbus_read_byte.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e1bc97b07837bc0663d56c9f62b919316f3ddac4
Author: Mark Wilkinson <mark.wilkinson@2pmtech.co.uk>
Date:   Wed Dec 1 16:57:37 2004 +0000

    Updated version of vt8231_early_smbus.c
    
      smbus_read_byte routine updated as per suggestion by rgm
      addition reset & wait_until_ready to allow correct reading of first
      byte on epia systems.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 284c27f29971326bd786e89c1ceb3f51a53203db
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sun Nov 28 04:39:45 2004 +0000

    fixes to make adl855pc compile.
    
    fixes to emulator.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 637b6998650619252b89e29f2add0167780e70db
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Nov 26 01:11:31 2004 +0000

    new config file format - PMC no longer works
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5720da9d758087dd41e9ea7dac111fcfa0b93529
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Nov 26 01:11:03 2004 +0000

    moved from ../sandpointx3_altimus_mpc7410
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 31f6606aeae21010ac1f38f13457325b56ab7d8b
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Nov 26 01:09:49 2004 +0000

    not used here
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 08d2d5a5c2c151e4a342c73b32a4728b3e43fab7
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Nov 26 01:08:16 2004 +0000

    PMC no longer works
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d12eca7273e9c219cd2e84e42b7b75b9149017a9
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Nov 26 01:07:47 2004 +0000

    ../sandpoint contains X3 configuration
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 92555b939d6e7cca7d8c1ded25d05a5a0c6b4683
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Nov 26 00:46:39 2004 +0000

    make sure enable_resource called on children
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0493069aa9f68756aafe14ebbf5cd9db40d12cd3
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Nov 25 17:37:19 2004 +0000

    update comment according to the new DOM
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f0ee1efcaf57c605bbd94f56a3d01dd379df33a8
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Nov 25 17:35:37 2004 +0000

    marked debug device on LPC bus
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 55895a29def5431a7cd4a1921812501518c1026b
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Nov 24 21:19:27 2004 +0000

    new config model
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d62a09c7915ed572dbaf747ddfb1900b5144f209
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Nov 24 21:15:49 2004 +0000

    move pnp code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d47d05bd0aa4efa56aedab9911d796806d946d0c
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Nov 24 21:14:06 2004 +0000

    pci devices are all on the same bus
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb746a3fea84a0265c39ca7d4f423b8a9c2ff78f
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Nov 24 21:13:03 2004 +0000

    removed argument
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0bac237334eda124c82af0fbfa60673fb23fbaf4
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Nov 24 21:12:20 2004 +0000

    added comments
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f4392503553cf31089ad91dc3e1b7546b8936999
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Nov 24 21:11:04 2004 +0000

    fixup debugging info
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c906c2918ab14bef349031773b2774b7f2fb5ca0
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Nov 24 21:09:08 2004 +0000

    scan the static bus
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 58769b7d50c923e83057793d6edee814a78c19ea
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Nov 22 21:45:24 2004 +0000

    - Add the cpu path support.  Oops I failed to commit this earlier
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e5c0ca30a2c57f7cf841c49fd29e87f4eea9bde1
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Nov 22 21:36:46 2004 +0000

    pci_read using wrong device
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abc4a11a9a4de69d77d9f74d0026ca149c9583f6
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 20 21:20:40 2004 +0000

    added missing cpu and cpu_bus support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5697edee0365a7e9464d1c103b2b8290e36a1989
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Nov 18 22:39:43 2004 +0000

    - Add the new files for the motorola mpc107
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a9e632c2ac29c60872e7e4f9314263b34ce5031d
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Nov 18 22:38:08 2004 +0000

    - First stab at getting the ppc ports building and working.
    - The sandpointx3+altimus has been consolidated into one directory for now.
    - Added support for having different versions of the pci access functions
      on a per bus basis if needed.
      Hopefully I have not broken something inadvertently.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bec8acedf18b4d35f95b4a4c254eb925bd4d53bd
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Nov 15 17:01:05 2004 +0000

    - Comment on why optimize_link_read_pointers is safe on an Athlon64
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb364958a06136f1e65499b434dd90191013a4e1
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Nov 15 10:46:44 2004 +0000

    - Don't force spew level debug messages on the kherpi
    - optimize_link_read_pointers compiles now on the solo so don't disable it.
    - Start sorting out the confusion between and object and an initobject on the ppc ports
    - Major bugfix release of romcc to support to remove preprocessor deficiencies.
      The line and column numbers are computed are now correct.  But watch out
      the error messages sometimes report the location of the next token so things
      are still a little skewed.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f6f349828f077f0ee3213f5f3a851fb0ff9b9363
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Nov 13 03:47:52 2004 +0000

    - Allow coherent_ht.c to compile uniprocessor
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3e9b52d554f40b0743cc420dc133b5b5ffd964bd
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Nov 12 21:00:29 2004 +0000

    ooops. sorry
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 204f718fa3424df71497d54b8896ff9c2fe4aa4c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Nov 11 21:30:50 2004 +0000

    fix a little more of ppc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d41ad83befa12b905bdde5fb853898c3569f0e9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Nov 11 14:04:25 2004 +0000

    in loglevel.h, if ASM_CONSOLE_LOGLEVEL is defined, don't try to set it.
    Set adl855pc ROM_SIZE to 1M
    Other minor debug prints until we get this fixed.
    
    We're almost as far along as we were before the Change :-)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 029517c77a1d756ccbb196b5178ba2a1cf952c97
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Nov 11 11:56:00 2004 +0000

    - Refactor the pc keyboard code so it will timeout if the hardware
      is not working instead of haning forever.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69afe2822a960c1d2b0c84854ea6a2cd1eec29f9
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Nov 11 06:53:24 2004 +0000

    mpspec.h: Tweak the write_smp_table macro so that it is safe if passed a complex expression.
    crt0.S.lb: Modified so that it is safe to include console.inc
    console.c:  Added print_debug_ and frieds which are non inline variants of the normal console functions
    div64.h:   Only include limits.h if  ULONG_MAX is not defined and define ULONG_MAX on ppc
    socket_754/Config.lb Conditionally set config chip.h
    socket_940.c We don't need and #if CONFIG_CHIP_NAME we won't be linked in if there are no references.
    slot_2/chip.h: The operations struct need to be spelled cpu_intelt_slot_2_ops
    slot_2/slot2.c: The same spelling fix
    socket_mPGA603/chip.h: again
    socket_mPGA603/socket_mPGA603_400Mhz.c: and again
    socket_mPGA604_533Mhz/Config.lb: Conditionally defing CONFIG_CHIP_NAME
    socket_mPGA604_800Mhz/chip.h: Another spelling fix
    socket_mPGA604_800Mhz.c     and again
    via/model_centaur/model_centaur_init.c: It's not an intel CPU so don't worry about Intel microcode uptdates
    earlymtrr.c:  Remove work around for older versions of romcc
    pci_ids.h:  More ids.
    malloc.c:   We don't need string.h any longer
    uart8250.c: Be consistent when delcaring functions static inline
    arima/hdama/mptable.c: Cleanup to be a little more consistent
    amdk8/coherent_ht.c:
     - Talk about nodes not cpus (In preparation for dual cores)
     - Remove clear_temp_row (as it is no longer needed)
     - Demoted the failure messages to spew.
     - Modified to gracefully handle failure (It should work now if cpus are removed)
     - Handle the non-SMP case in verify_mp_capabilities
     - Add clear_dead_routes which replaces clear_temp_row and does more
     - Reorganize setup_coherent_ht_domain to cleanly handle failure.
     - incoherent_ht.c: Clean up the indenation a little.
    i8259.c: remove blank lines at the start of the file.
    keyboard.c: Make pc_keyboard_init static
    ramtest.c: Add a print out limiter, and cleanup the printout a little.
    amd8111/Config.lb: Mention amd8111_smbus.c
    amd8111_usb.c: Call the structure usb_ops not smbus_ops.
    NSC/pc97307/chip.h: Fix spelling issue
    pc97307/superio.c: Use &ops no &pnp_ops.
    w83627hf/suerio.c: ditto
    w83627thf/suerio.c: ditto
    buildrom.c: Use braces around the body of a for loop.  It's more maintainable.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d54bd4471267bd77f105c48f6c8e12449bd375e
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Nov 11 03:31:16 2004 +0000

    - Remove include of device/chip.h
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 624252450f795242e2ef7fddc7adfceae4b2da4a
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Nov 10 20:13:35 2004 +0000

    - Delete unused funciton realloc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26e32760f90330c88e4b7ea84ff204e67d72196d
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Nov 10 20:11:15 2004 +0000

    - Remove unused start_stop.h
      This file died with the last round of cpu restructuring I just missed it earlier.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8bcb8a2adaeafdd38a7b03087a815f8e4230392b
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Nov 10 18:32:20 2004 +0000

    - Don't use e7501 root_complex
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab49946a564c5245ba7dad2af8891fa1fa3a0936
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Nov 10 18:31:31 2004 +0000

    - Remove e7501 root_complex
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52c2277a1bfadcf9fca9e70a313a9a7f30db0069
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Nov 10 15:12:48 2004 +0000

    adl855pc support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 132368b4c58cf74fc0347f4ab72bdf467e2a62a3
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Nov 9 08:59:23 2004 +0000

    - Clean up the CPP output a little bit
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a649a411d78e07d889fbcc4dbd59af5175e39f33
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Nov 9 00:35:39 2004 +0000

    - Fix silly thinkos in that caused parsing problems in romcc.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7dd185c885dcd5c0777d487f672db386eb9d6842
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Nov 9 00:05:42 2004 +0000

    - Fix minor glitch in romcc where it would not return from a header file
      if it had a preprocessor directive on the last line.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12eb7bc5add438db35d40fe4f7c34c9352b51ff1
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Nov 8 21:16:16 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 41203d9b779d6f1c82de292b839793216f9199e7
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Nov 8 09:31:09 2004 +0000

    - Romcc preprocessor bug fixes, (The code size went down about 350 lines.. :)
    - Preprocessor constant expression evaluation is no long a special case so
      unsigned long values can not be used.
    - Undefined macros are not converted to 0.  But a big warning is printed.
    - Garbage at the of an #include directive is now done in tokens instead of
      in characters.
      This allows comments after an #include directive.
    - Repaired a previously unnoticed regression in constant expression
      evaluation.  Logical expressions can now be evaluated again.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc9e6e35c43ccdfa06b1c93879895ef90ccb4ee2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Nov 5 23:19:46 2004 +0000

    add compiler from crosstool, too
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ad00d73998f56147ecf581c841b4bd72e7654651
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Nov 5 22:14:33 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 44b34e31a54519fe00658cf9e0ebb6a5b01a3702
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Nov 5 22:03:37 2004 +0000

    CONFIG_CHIP_NAME to control config chip.h without .name
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a9c836f93de8373c122d483894599b3eaf4b151
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Nov 5 19:55:46 2004 +0000

    - How did I forget to cvs add this?
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1763 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 692f2c7aed911dc193e96b214b62366ad04c89b2
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Nov 5 19:55:06 2004 +0000

    - First pass at getting the powerpc ports to compile
      The static device tree is not built properly at all yet, but at least we get through it.
      FIXME (What is the proper way to handle add in boards?)
    - Add generic div64 support and ppc div64 support
    - Fix abuild so it properly generates the CC line when cross compiling.
    - Add one more possible ppc cross compiler target
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd51e6ad901d972a28749b8f7c252ef9d41d199f
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Nov 5 18:09:46 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f285ae709988324fee6f919ff7736341745d223
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Nov 5 14:06:24 2004 +0000

    remove nasty workaround, include echo in function again :)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 173f13b81f5a2fea144092fc5fffc01cc2aa56d8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Nov 5 11:57:00 2004 +0000

    add debug function
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4c6846f4178cb0a74ae08b06d897ead512c08e1
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Nov 5 11:47:41 2004 +0000

    ...
    add option so it's possible to ignore broken builds
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1a003244d623ba4854be37793cc51ff9d3185280
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Nov 5 11:41:26 2004 +0000

    - Add another possible powerpc cross compiler prefix
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca883c915ac8ff71dbe5f44a8a5767f3d7cfc37b
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Nov 5 11:24:57 2004 +0000

    - More fixes...
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 709850a21b1bdfb0018aa2a7ee06a7407bbd465c
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Nov 5 10:48:04 2004 +0000

    - Ensure every copy of Options.lb uses:
      CROSS_COMPILE
      CC
      HOSTCC
      OBJCOPY
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d0805e0b55e63957b3641fa70cf1db624389e3f6
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Nov 5 09:03:47 2004 +0000

    - Ensure the  all target is the first commands in the makefile....
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c1b858f0fc15ce8380759a2b3e03f57b4073d50
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Nov 5 08:57:09 2004 +0000

    - Put the rule for the Makefile at the bottom of the makefile!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c1492104629fdd61419887636a3c1ed9a280ecce
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Nov 5 08:50:54 2004 +0000

    - In the makefile header get the name of the Makefile correct
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e99655670a61aebb9d46dd46f8d99ff193051f4
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Nov 5 08:21:05 2004 +0000

    - Massage the code to generate the top level Makefile so the
      generated Makefile has correct dependencies and is somewhat complete.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 41d0fa38af010fdb2f9456ae3f693b1cadcc6bd6
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Nov 5 07:26:56 2004 +0000

    - Modify all of the Opteron motherboards to have a separate logical
      chip for the amdk8/root_complex
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8bd555297e9c8eb8b9a006812f7a64197acff583
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Nov 5 07:04:54 2004 +0000

    - Add a new chip northbridge/amd/amdk8/root_complex
    - Moving the functionality around in northbridge/amd/amdk8/northbridge.c
      to put the pci_domain and the apic bus on the root_complex.
      Everything else remains with the individual northbridges.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7bf1b48bd423065dac1fcc0990dd841dd792ae00
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Nov 5 03:44:01 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3779f6a4cbf1d0c19f40886d5b01db5451f99ff8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Nov 5 00:26:31 2004 +0000

    stepan goes to bed now.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d87ce961f68de8b11271c2ac5ed231ab04fe48cf
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Nov 5 00:25:19 2004 +0000

    - some steps towards cross compile
    - add option to force rebuilds even if they were previously ok
    - add option to build on target only
    - play around
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9562049df52ec154c01a37a9c531bd4e69b4da5c
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Nov 4 23:42:54 2004 +0000

    reformat
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b2d77282e0c7d30e2c487db2af13bb7df71c5867
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Nov 4 22:36:18 2004 +0000

    debug device added
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 652ae6f533c3d6b86cd49bf95e73fe1c6b826add
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Nov 4 21:48:39 2004 +0000

    we decide not to enable BM DAM form them
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8085f032f855474089e5b16fed16d689bf17550c
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Nov 4 21:00:13 2004 +0000

    SI Class code check
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d2bdd38464b6e4984fbfd20d642e6b3d080e1df
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Nov 4 20:31:04 2004 +0000

    removed #if 0 #endif code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f84926efca2f871fa557cccee36f0f773ec7190b
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Nov 4 18:36:06 2004 +0000

    tell people that the segment descriptors are different for ROMCC and
    GCC code.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1995f1af35b53b5c07694df7296f5eb20461b1c6
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Nov 4 18:33:33 2004 +0000

    removed the comment in the very beginning of hardwaremain(). I don't
    think it is relevant now.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23bc47db17a291aca980405157334395f328eb62
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Nov 4 11:09:12 2004 +0000

    Add Options.lb to various motherboard ports
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 018d8dd60f2cc0c82faac0ee2657daa163dd43e7
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Nov 4 11:04:33 2004 +0000

    - Update abuild.sh so it will rebuild successfull builds
    - Move pci_set_method out of hardwaremain.c
    - Re-add debugging name field but only include the CONFIG_CHIP_NAME is
      enabled.  All instances are now wrapped in CHIP_NAME
    - Many minor cleanups so most ports build.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4403f6082372d069e3cabe0918d9af5f9c1dccf6
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Nov 3 00:47:40 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e507c85fe331e8c24bf4ff4d20c880c9affee9d6
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Nov 3 00:10:15 2004 +0000

    This hurts more than it helps. byebye
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e4932dc760160245d861981c0aca600c4929d07b
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Nov 2 20:33:12 2004 +0000

    get qemu-i386 target building again
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3f3e9abf40c4b18681299560a931cae390409f2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Nov 2 20:29:30 2004 +0000

    update to new structure
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bf8bb42d6a0ecd70e3853397eb847688968bd9a9
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Nov 2 18:05:22 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3974363f091180699bc518c6e4e72637b7ab5a96
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Nov 2 17:46:43 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9434c1b661506e9f0b77896c87c36b39b9137da9
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Tue Nov 2 02:34:28 2004 +0000

    Tyan update for ROM_IMAGE_SIZE > 64K
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 097996973221f442d2690ccfd0769b26f0a65a30
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sun Oct 31 23:03:10 2004 +0000

    fix solo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 432aa6a2550e0d2625c4d08cd3d438447abb86a8
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 30 22:59:35 2004 +0000

    - Update console.c to have non-inline versions of functions
    - Add exception.c
      Sorry for not including these ealier.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8a2dddb573faef41ad43ee111d91d4c5259ad59
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 30 08:05:41 2004 +0000

    - To reduce confuse rename the parts of linuxbios bios that run from
      ram linuxbios_ram instead of linuxbios_c and linuxbios_payload...
    - Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86
    - ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB.
    - Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work.
    - Start using romcc's built in preprocessor (This will simplify header compiler checks)
    - Add helper functions for examining all of the resources
    - Remove debug strings from chip.h
    - Add llshell to src/arch/i386/llshell (Sometime later I can try it...)
    - Add the ability to catch exceptions on x86
    - Add gdb_stub support to x86
    - Removed old cpu options
    - Added an option so we can detect movnti support
    - Remove some duplicate definitions from pci_ids.h
    - Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic
    - Minor romcc bug fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0afcba7a3d0e7dc22818ecdfd79230f5fb987f0d
Author: Mark Wilkinson <mark.wilkinson@2pmtech.co.uk>
Date:   Fri Oct 29 16:16:43 2004 +0000

    Changes to allow Via/Epia code to be compiled after recent code changes.
    
    New Files :-
    	src/cpu/via/model_centaur/Config.lb
    	src/cpu/via/model_centaur/model_centaur_init.c
    
    Updated Files :-
    	src/arch/i386/include/arch/smp/mpspec.h
    		- make write_smp_table a define for non smp systems
    	src/cpu/x86/lapic/lapic_cpu_init.c
    		- change possible typo
    	src/mainboard/via/epia/Config.lb
    	src/mainboard/via/epia/Options.lb
    
    	src/mainboard/via/epia/auto.c
    	src/mainboard/via/epia/chip.h
    	src/mainboard/via/epia/failover.c
    		- updated after recent code changes
    	src/northbridge/via/vt8601/chip.h
    	src/northbridge/via/vt8601/northbridge.c
    	src/northbridge/via/vt8601/raminit.c
    		- corrections after recent code changes to allow compiling
    	src/southbridge/via/vt8231/chip.h
    	src/southbridge/via/vt8231/vt8231.c
    		- initial pass to allow compiling after recent code changes.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97035448f3c537cf7e809d677449a169fc73b016
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Oct 28 18:44:38 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 79186eaecdf61d0d53618d1c5d26a6e66850c1ff
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Oct 27 18:54:13 2004 +0000

    - Look for all 8 possible cpus
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a58cd524fb12fe26ecb73147b1977bf4ec72b74c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Oct 27 17:27:10 2004 +0000

    some more porting to the merge
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e53f50082cfac4ec2d06d2ff6515781190ad1c0
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Oct 27 08:53:57 2004 +0000

    sizeram removal/conversion.
    - mem.h and sizeram.h and all includes killed because the are no longer needed.
    - linuxbios_table.c updated to directly look at the device tree for occupied memory areas.
    - first very incomplete stab a converting the ppc code to work with the dynamic device tree
    - Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources).
    - First stab at Pentium-M support
    - add part/init_timer.h making init_timer conditional until there is a better way of handling it.
    - Converted all of the x86 sizeram to northbridge set_resources functions.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 20fc678d65b4cdf6b24bdff45ef04933c538e2e8
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 27 02:12:22 2004 +0000

    spare 4s for restart
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 63f2f721b4c421ba0ad42e6469664eeed126913f
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Oct 27 01:58:26 2004 +0000

    - kill the broken and duplicate 855pm directory.  Hopefully I have kept
     the least broken one.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dfde9bb64953d2f7c792a67e0e231eb5cabcd673
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Oct 27 01:18:47 2004 +0000

    - Actually enable the Pentium-M cpus
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3566b3d545dd13f3760e6aa1fc50159243991e1d
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Oct 27 01:18:16 2004 +0000

    - Bug fixes to the P-III support
    - Initial Pentium-M support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eefdb038981a0fcc93df5c6c934f8138a43873bb
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 27 00:37:30 2004 +0000

    S2885 winbond Superio all resource set
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb198640d8ba755b7022800d0077c41dceae1b94
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Oct 25 19:55:30 2004 +0000

    ops and tsc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cf950ca5a7dc0f9373b9b4db508480a35bb35ac
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Mon Oct 25 19:49:50 2004 +0000

    s2735 minor changes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f637906c4c5a81c923cca157fca933dac186531
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Oct 25 16:01:30 2004 +0000

    added file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ae74b40bfea4d1d78e7469895f4c3f788e0917c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Oct 25 14:57:24 2004 +0000

    from  Mark Wilkinson, some fixes.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e2847c28ef57cf1ee49653dabee6bd3ed1f2525
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 23 03:00:02 2004 +0000

    - For now use port 0x80 based delays in for the e7501 memory initialization.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 60216355d21fae62daf00afa66443b03ed743e2a
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 23 02:47:13 2004 +0000

    - With Xeon cpus it seems best to use the tsc calibrated with timer2 as
      the time source.  The apic timer also has a variable time base.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 720a8f57ef1a1a4264354dd9601c53e12b82ae36
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 23 02:32:23 2004 +0000

    - Update e7501 northbridge.c to work in the new structure.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8abb054c0e7597e2702043db6eb6e86c6ef91cca
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Sat Oct 23 00:05:22 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2560dbdd504dfaaff97174a3dd017edf7378b87a
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Oct 22 21:33:08 2004 +0000

    for S2735 support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e99433157b43e0e1813f0edd732f804a9d6f7207
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Oct 22 21:03:26 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 79cf1be9e47a54a462cbb644bcdfc94d2ac2d286
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Oct 22 18:49:09 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ccf0bc01aa00a026d136685b0f5f95109f6c85df
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Fri Oct 22 18:45:36 2004 +0000

    s2735 half update
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a1653cfea55c82ab12f46e14d7ecd7e7ca5e89a8
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Oct 22 04:41:53 2004 +0000

    - Better memory I/O space distinguishing in amd_mtrr.c
      This is way to much code duplication but for now things work.
    - Fix the typo in amd8111_lpc.c
    - Remove an unused macro, use continue instead of break in mtrr.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f9265fdc6c6609dd801a13415bc7a5378076e78
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Oct 22 02:33:51 2004 +0000

    - kill typo so resources are not mixed up in amdk8/northbridge.c
    - Enable resources on the lpc bus.  PCI now longer do this by
      default for their children unless they are bridges.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23c3d9321f4fdead52080e9a1a261807d0a3cbc8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Oct 21 21:41:57 2004 +0000

    show error logfile
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 584e078231f6c6b59abeb8588c5967972c133a6c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Oct 21 20:52:53 2004 +0000

    adapt config files
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 800a55bb5c2c8e03c3039cf4f1e6163a2fce8f54
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Oct 21 18:51:13 2004 +0000

    get solo building after last infrastructure changes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a49f4161f5631760309ba47b925183736a754717
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Oct 21 17:06:49 2004 +0000

    update failover handling of some amd64 boards
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dbec2d4090e40d1d8e1fd06e8d4180d3fa685d4d
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 21 10:44:08 2004 +0000

    - Bump the LinuxBIOS major version
    - Rename chip_config chip_operations throughout the tree
    - Fix Config.lb on most of the Opteron Ports
    - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
    - Add detection of devices that are on the motherboard (i.e. In Config.lb)
    - Baby step in getting the resource limit handling correct, Ignore fixed resources
    - Only call enable_childrens_resources on devices we know will have children
      For some busses like i2c it is non-sense and we don't want it.
    - Set the resource limits for pnp devices resources.
    - Improve the resource size detection for pnp devices.
    - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
    - Added a header file to hold the prototype of isa_dma_init
    - Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
    - The code compiles and runs so it is time for me to go to bed.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3aa4707d3bef9f529a70a204dbc648968cf7c20
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 21 02:53:25 2004 +0000

    - Explicitly disable the fixed dram extensions bits.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29490a17ced79768a337642f36066c5c07922966
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 21 02:43:15 2004 +0000

    - We already know the cache is disabled so don't bother disabling it.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f19e2c766ac602f51882cf3c1c28c90d12f21c8d
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Oct 21 01:52:21 2004 +0000

    better support enable_dev for amd8111
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6014983babe46d025cdcfb76bc20ff009eb27817
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 20 17:54:01 2004 +0000

    add Option.lb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a61d6a4ae26d02844bf8043525d89b0ef9e0351
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Oct 20 05:07:16 2004 +0000

    Tyan update to work with new CPU Config
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abed01d81d0c55848232a9ebd9bb4c55d036f45d
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Oct 19 23:35:53 2004 +0000

    - Fix typo with reversing memory resources.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 812688bf3cef16d8d431a206e9ceea24e5e87746
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Oct 19 17:49:32 2004 +0000

    change struct chip* to struct device*
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit de24e61df7699a1770a81d6969efa8254bd75a5f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Oct 19 10:30:32 2004 +0000

    - add support for socket 754
    - fix configuration creation for amd solo (doesn't compile yet)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9f12caaf103884678e467a102afe378bd6b98348
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Oct 19 07:00:47 2004 +0000

    initial checkin of automatic linuxbios image build test script
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a172d98233620f24d2566045e335fae0f0a43b46
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Oct 19 05:07:18 2004 +0000

    - Fix bug with > 4GB of memory where PAE was left enabled.
      Why didn't this show up until I had > 4GB on one cpu?
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ea19c134f8c9bc99014b1c0ff661b59310a0d2a
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Oct 18 23:24:25 2004 +0000

    - FIXED resources are also ASSIGNED resources
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7faae8309c91009f2448884a9410a2494bc3b222
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Oct 18 21:21:06 2004 +0000

    - Set the parent's link properly in the bus field
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 04da1d35d11ba195fbf0af8f7ca5149b6ce502a6
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 16 19:58:35 2004 +0000

    - Bump MAX_LINKS to 4 I have actually found an i2c bridge that needs this
    - Fix the hdama Config.lb to not longer use the link keywords oops,
      and instead to have it nest everything properly.
    - Update config.g to not support the link keyword
    - update config.g to not support northbridge/southbridge/cpu/pmc noise words
      we can just use chip now.
    - Remove old link handling from the code
    - Detect and handle duplicate paths so we generate one device with multiple links
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 858ac5c5cd299156cbe79be1cb50f2a7a582b61c
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 16 09:13:23 2004 +0000

    - Make all ports use config.h for if they have chip_config or chip_info structures.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 92986807bb589e2b98470155c580828bb1a2838b
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 16 08:45:29 2004 +0000

    - Cleanup the bugfix in elfboot.c
    - Add forgotten amd8111 chip.h
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3ed1cfad748bf5610d315afba7ec04d6338bd9b
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 16 08:38:58 2004 +0000

    - HDAMA boots!
    - Set the bootstrap processor flag in the mptable.
    - Implement 64bit support in our print statements
    - Fix the reporting of how many cpus we are waiting to stop.
      It is the 1 less than the actual number of cpus running.
    - Actually enable cpu_initialization.
    - Fix firstsiblingdevice in config.g
    - Add IORESOURCE_FIXED to all of the resources set by config.g
    - Fix the apic_cluster rule to add an apic_cluster path not an apic path.
    - Add a div64.h to assist in the 64bit printf.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7003ba4a88a847707c55d593e517eaa70fc8c63d
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 16 06:20:29 2004 +0000

    - First stab at running linuxbios without the old static device tree.
      Things are close but not quite there yet.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 216525d1fd86c13e0f1ebe85ba518cdc1da06fcb
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 16 02:48:37 2004 +0000

    - Fix config.g and the hdama config so everthing builds again.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 688af4be2b92350f0f62268a2ec9b874f2f4bf42
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Oct 15 20:47:41 2004 +0000

    add back stuff from before
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9510aa888b479647652dd5294d3f59d708c7858d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Oct 15 19:28:56 2004 +0000

    fixes for apic, i2c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09b0aeddd31c5cf048d95ec1917efad97489f385
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Oct 15 19:17:43 2004 +0000

    closer
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab55d1f4b4f01a4fffef251f8aaddea0fd906bdc
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Oct 15 15:09:30 2004 +0000

    this now works right.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e2ad5ce6978c48218b6367e4d452baaa28aeb820
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Oct 14 23:05:08 2004 +0000

    fixed function prototype for die()
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3287f0b9a1d8471abf3b18696d0d2a9943f32716
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 23:02:00 2004 +0000

    - Change broken usage of get_resource to find_resource.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 448bd635c0c037544f0dc33846cf37e5ed80ae6a
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 22:52:15 2004 +0000

    - Finish interrupted merge
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e5ac2959bb96c12c7aab1c22236585ea3f4d234b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 14 22:44:26 2004 +0000

    oops.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 119e00e2e1ca7b1c9ef112f2a971cc47c76aabf7
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 22:35:23 2004 +0000

    - Fix fat fingered merge
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3614eebc1380cd2d7e2c74b4274238ace9cca7fc
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 22:29:26 2004 +0000

    - Update so we no longer require console.inc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1944680bfd0a8ff6ec8df06d142ab143806e92f9
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 22:06:29 2004 +0000

    - Sync up northbridge/amd/amdk8
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5d7dafea868f9e0dfc47249c33e819ace04f78e5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 14 21:57:29 2004 +0000

    more or less more or less broken
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 297b06e6f923166fbe43389e941cb6e6c3ab2193
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 21:55:53 2004 +0000

    - Update the header files in reset_test.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 73f2282ea1c349eca90a89e41808ccb3bf7df82e
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 21:43:24 2004 +0000

    - Add a generic device that does nothing
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b933948720bac217e007f8db17355468e632c32
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 14 21:40:58 2004 +0000

    more breakage, thanks to Ron
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03acab694b3f2fcedd2ffc152db0c08bba8eebdd
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 21:25:53 2004 +0000

    - Updates for 64bit resource support, handling missing devices and cpus in the config file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 992cd008f1d4217c3e7dd6d0a1e8445ade5da63d
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 21:10:23 2004 +0000

    - Update the device header files
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b78c1972feed4c57eebba8f94de86a91e32c3fa7
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 20:54:17 2004 +0000

    - First pass through with with device tree enhancement merge.  Most of the mechanisms should
      be in place but don't expect anything to quite work yet.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cadfd4c462673bcb44cdb1f193e52c95a888762a
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 20:52:22 2004 +0000

    - Add arch/cpu.h
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 65186ce66c299c31b5e1dad9efbcc4c05fa5989a
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 20:15:40 2004 +0000

    - remove old cpu header files
    - Update cpu.h for the new cpu initialization scheme
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c84c1906b78b767902bf9d8f18ae8a21d2f1f114
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 20:13:01 2004 +0000

    - Renamed cpu header files
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b84166e8e53476f1ef4d49aca17f99d303b4aa67
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 19:39:27 2004 +0000

    - remove deprecated directories
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fcd5ace00b333ce31b11b02a2243dfbf39307f10
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 19:29:29 2004 +0000

    - Add new cvs code to cvs
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 98e619b1cefcb9871185f4cc3db85fa430dcdbce
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Oct 14 16:25:01 2004 +0000

    - Add chip and a few other bug fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 02fa3b2743b3f37381b6af4ee4362422b9011c8b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 6 17:33:54 2004 +0000

    epia-m support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4fa89208a16e1e2052fff315c76f8f3f07459571
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 6 17:19:49 2004 +0000

    f'ing thing still won't work.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed9f18d545ffa6e4604eacbf1ce8c68913378ab8
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 30 22:50:13 2004 +0000

    mods for i855pm that don't seem too wrong. ha!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4779e80c3e54e6e6c31169908803065b4ef68b2
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 30 16:37:22 2004 +0000

    digital logic stuff, fixes for the smbus code in 82801dbm
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b763af4ca6541734ff7d36a16173f9606c248c9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 30 16:37:01 2004 +0000

    support for sst firmware hub
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b41f6b480ae3bebbb319d9154aebb140fbbcf62
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 28 20:32:17 2004 +0000

    use hex print in id1, id2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a26c8ef2a0bf380d030fa88aa6e0a081c74711f3
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 28 20:09:06 2004 +0000

    add support for ICH4. more i955pm stuff.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c3c27a50d974e183927fc0b31b6c96800e27f5d2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Sep 9 07:19:40 2004 +0000

    add include to fix build
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 817b3f2d35720cdac146cb565a080024050a35c7
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Sep 7 21:31:47 2004 +0000

    code reformat
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39fdcbf9f0e117629cea42ce335529a7061fada6
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Sep 7 21:31:06 2004 +0000

    seperate code generation
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b08c116b9bb3aaf2059935e46f51446a27f93ee
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Sep 7 21:20:53 2004 +0000

    removed unused code, code reformat
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 981faa09e4b7edf498b1b1f353cc100541abb859
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Sep 7 19:24:40 2004 +0000

    rename variable from addr to dev
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43dd85e7ec30f53364c7ac5abc84d55b104ae00f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Aug 30 16:08:30 2004 +0000

    more fixes.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 009f87a30b9b3569a1d41fceae420ca7b97bf2a1
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Aug 27 21:39:59 2004 +0000

    build fix for epia-m so that nobody beats ron to it ;)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6707a45eb14bf28abd2a38e1b95d30d27262f347
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Aug 26 16:13:40 2004 +0000

    just a few changes before we hit the big fun.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1ddc8eaddb54b05a9ecb5ffbf9ba3e3264f63ec3
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 25 18:19:08 2004 +0000

    more updates for 855
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e6552bcf3960c7d10fc3730a2d6b408bfc9a8ca9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 25 15:40:47 2004 +0000

    changes for the dbm part. Still need to remove the sata file ...
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3b0096313a3176370aaac91714d7b81dd0163b9a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 24 22:27:55 2004 +0000

    compiles.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 74bfa2c8b2a72ed88af4a84ebe6e172cd3af566b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 24 22:17:33 2004 +0000

    stupid ron! need to start names with a letter.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7da4d6a089902fb438913b199783b14a9420c102
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 24 17:29:29 2004 +0000

    start of port of adl855pc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0fb38825cb660f08acfc9b352aa52cc00101bc6e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 24 17:23:37 2004 +0000

    fixed up tables.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 182615d635343a33306320833b2606e1f966e35a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 24 16:20:46 2004 +0000

    new intel io hub.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c66444c175a6c4c285b0ff93a25991e28e0bd756
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 24 16:11:50 2004 +0000

    new mainboard
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 300e1b569addfc617db3bd1fa9ee0b33d8c65072
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Aug 23 21:04:36 2004 +0000

    random fixes.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 92d159f27d7ccf8165ce7dae2dd616baa6ca544f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Aug 23 20:41:25 2004 +0000

    dpx114
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 55a6d461a6b71706cacefb9cbcdc86980b545815
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Aug 23 20:25:17 2004 +0000

    new mobo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03935036abaa25e8d248e4eb6bacc00cf0582525
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Aug 23 16:43:25 2004 +0000

    adding 855pm
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 198409afe08df8285f80327307670e9d859c9e2b
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Aug 7 19:58:46 2004 +0000

    create some technologic systems ts530 infrastructure
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 40ab2d1213f65bb540cc6b5ddc1794c0d4db38f1
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Aug 7 19:34:46 2004 +0000

    add Config file for ts5300
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7bc28306682160a77fb2ddb7280e595bbad1eea8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Aug 7 19:20:44 2004 +0000

    initial version of TS5300 target
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f030bab1a8be64fad0dde7bba78ba6ba5cc7355d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Aug 7 19:13:27 2004 +0000

    get AMD Solo building again..
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 815212652994a43d3e05dc864343b722b70a129d
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Jul 8 17:18:27 2004 +0000

    added testbios for V2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4c5060dc2bf8f944c54361f7913d20d02fff65a0
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Jul 8 16:59:06 2004 +0000

    move default_resource_map to its own file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f76a613a9a6cb978ed2d60ea0c5c0a9b195a825b
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Jul 8 16:57:43 2004 +0000

    code reformat, removed unused code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9ab91f5acbe54bf3298e81e69f2eb3079ffb3c54
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Jul 8 16:54:20 2004 +0000

    code reformat
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit badf114438d2518e2d33363603e46c138f1cfd2c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jul 6 16:57:44 2004 +0000

    fixed again.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 737de849d57cc134fc6c972de29b04e9738da88d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jul 6 16:35:50 2004 +0000

    fix for simple error
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e89137b2adfc4d9639e77c1d84bdd688b48cd495
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jul 1 04:21:49 2004 +0000

    remove_logical_cpus need call get_option
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 70093f7875371abe52c4417c6cc3a427d20781c5
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Thu Jul 1 03:55:03 2004 +0000

    Intel E7501 P64H2 ICH5R support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7dea9552d5fa10c5542e744fe1d8e0a81689e3c1
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Jun 29 05:38:37 2004 +0000

    - Small bug fixes to romcc.  The deep problems with not inlining functions remain
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 596a6674fdea6574c6de400af770602b9dc7a567
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jun 28 12:20:42 2004 +0000

    add target for qemu-i386
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7fb8916011f66cc82feaf1a85848ad28209b5613
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jun 28 12:06:20 2004 +0000

    make cpuid and mtrr check conditional. They are not there on cpus older than
    i586/i686.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f2065a4cf9d8a66f237dfb0f7502b19f89a852c9
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jun 28 12:04:06 2004 +0000

    add qemu graphics card initialization driver
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e2b53e14327ea01dff9291815b10709b74b661f2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jun 28 11:59:45 2004 +0000

    add northbridge code for qemu-i386
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4a3bb76aa85ba720b607152d853bd7e1964a9f6c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jun 28 11:57:31 2004 +0000

    commit initial qemu support (see http://fabrice.bellard.free.fr/qemu/)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bbf16821c000ad347bfd2681bdda383028cc011e
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Jun 16 19:06:33 2004 +0000

    add target for amd serenade board
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c7d4db7ff1aaab7cc79bdf0ccce96223c83ef88b
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Wed Jun 16 15:32:43 2004 +0000

    Now it should build on the first try :)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99efe80122395187dbb83b76980c4f0a7539bc3c
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Jun 15 23:55:55 2004 +0000

    add support for AMD Serenade mainboard, why we have phantom devices here?
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ae2ac37396e555041c382bef9d6ee060d2df542
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Jun 15 23:37:34 2004 +0000

    add support for AMD Serenade mainboard, why we have phantom devices here?
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b1a2ff96f4cc6129ba9bfab227b0dbe4af30593
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Jun 15 03:00:35 2004 +0000

    code reformat, is the pirq table correct?
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0b607b39baa652ada1f749e4f4488d6bf450d3c0
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jun 7 10:25:42 2004 +0000

    simplify pirq handling. Only apply consistency fixes on the copied version
    of the pirq table.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab8ff84402e97d544b519ec17a2ee184651b8af6
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Jun 5 14:54:46 2004 +0000

    Add extra phase before memory init.
    Rename sdram_init to memory_init
    NOTE: need to test sandpoint and ep boards!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ce104f487a8248be143b4436b7a4abc3969bb6f
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Jun 5 14:36:23 2004 +0000

    memory and pci up!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f2e63bc7dd27b526d300a7aa712a0af4ec85e3e
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jun 4 22:46:30 2004 +0000

    BDI2000 config file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c72e27616df506e2417e4e8a1a3efd1f198b3cf1
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jun 4 22:28:23 2004 +0000

    enable early uart
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb5f0ce6a74e94b964ab2c37ab41a03a4c8b966d
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jun 4 22:27:33 2004 +0000

    fix addressing
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 91d60a8fcab3e25b35f679fd7260d538bc758f02
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jun 3 16:57:09 2004 +0000

    first cut
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2906362ea7001da74b92339fa7f3fa146f05f919
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jun 3 16:56:01 2004 +0000

    nothing yet
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5b2565a6df7d9f8f9b6354be797ee926586618af
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jun 3 16:55:24 2004 +0000

    fixup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f78ba9dfa635580eaa7a49421c397b939529f1b5
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jun 3 16:53:41 2004 +0000

    prelim sdram
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ba0ce6b79421194bfbca79cc7b32e33c4e018ad
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jun 3 16:51:18 2004 +0000

    briQ timer support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66c07cdc942c4a02dd2d4e2b4be9aba0727afe28
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jun 3 16:30:02 2004 +0000

    Make names more sensible.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca68a91eff7d0053e48f24994b7808acec14a28e
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jun 3 14:39:16 2004 +0000

    Clock (not timer) routines are board specific. Moved to appropriate
    mainboard dir.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0dcb1729044fd5c537a07a71769fcba57ec1149c
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jun 3 14:38:12 2004 +0000

    Clock (not timer) routines are board specific. Moved from mpc74xx dir.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 65046b16f90bea203ba5b8315c895b34d92bc3ac
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jun 3 14:34:31 2004 +0000

    remove brain-dead verify code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 515f6b68a0dad6d3105966d57de05274b3341de7
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Jun 3 07:57:12 2004 +0000

    disable noop usb drivers. remove warnings
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c83b27c91c143d53077b799dc9df520c450ba43
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jun 2 11:25:31 2004 +0000

    brush up language, unify terms, correct some urls.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a78bd03a682bb3b8966e5684fc5b2a22e3058f2
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat May 29 21:26:03 2004 +0000

    - Don't confuse return statements with conditional branches
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb20a721630a2c37110d6b34def7748c883b4a70
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri May 28 15:10:04 2004 +0000

    This will never happen unless the code is buggy (in which case it's easy to
    reenable debugging output).
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34e3a146a95bd917b99e2185a17690f467dab8fb
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri May 28 15:07:03 2004 +0000

    console code cleanup.
     - drop srm console code (not supported anyways)
     - make internal uart8250 console functions static
     - split vsprintf.c into vsprintf.c and vtxprintf.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 319d6730e9db850609f75be2b4fdef2a622e04ef
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri May 28 14:55:28 2004 +0000

    add some debugging
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d67e76568acff164328467a744a76de62b67f026
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri May 28 14:18:45 2004 +0000

    - Added volatile to asm statements in auto.c and failover.c
    - Updated the romcc version in Config.lb
    - Fixed type sizes in romcc_io.h and io.h inl() returning a byte was nasty
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 90089603393a1a67b9a4afe1f2b7237a74e1b21b
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri May 28 14:11:54 2004 +0000

    - Upgrade to romcc version 0.63
      This includes more test cases
      Lots of small bug fixes
      A built in C preprocessor
      Initial support for not inlining everything
      __attribute__((noinline)) works
      Better command line options and help
      Constants arrays can be read at compile time
      Asm statements that are not volatile will now be removed when their outputs go unused
      Loads and stores that are not volatile will be removed when their values go unused
      The number of FIXMES in the code is finally starting to go down.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7664d1cb87876a3b7e622cf1c7e40f1fb7988c9f
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Thu May 27 21:17:13 2004 +0000

    Default and maximum loglevels were too high, fixed.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f52a90ad3e4a93040adfd8ce6fd2b7d4b186376
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Thu May 27 21:10:47 2004 +0000

    Fixed a silly typo :)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d5994ce9c1d0359c93dcb4f1d84911b59b58904e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu May 27 13:54:38 2004 +0000

    fix build. :( sorry, forgot to commit this one.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 76712933a0aa6b79095e83f3e08b94f9002736d3
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu May 27 11:13:24 2004 +0000

    gcc uses slightly different syntax
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4bfb1f6ce039e8cd8064fe0afada5114ba77cfd0
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu May 27 11:09:14 2004 +0000

    cosmetics
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 018dc9d48e4bf75515fb6f2566cb5ef729c81165
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Wed May 26 21:40:24 2004 +0000

    Sample configuration for Iwill DK8S2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb8602b6ea442818bb0bf8f6985e890d0a198918
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Wed May 26 19:18:21 2004 +0000

    GPIO2 and GPIO3 support for HF part.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 994048f24144b34027375ebc397526b27f11e987
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Wed May 26 17:29:59 2004 +0000

    Sample config for Iwill DK8S2 dual Opteron mainboard
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 58133c29fee609d4810bde125a2f18b4d91b72b1
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Wed May 26 17:21:02 2004 +0000

    Early work on IWill DK8S2 motherboard.
    Tweaking in progress.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36a74b0c188c866d1bcf507a61bf2808858ab858
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed May 26 15:54:41 2004 +0000

    cleanup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 38ffff0d724fdbce9bf525f01f3e969de9b583d9
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed May 26 15:43:27 2004 +0000

    move arch/<arch>/config to arch/<arch>/init
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e891783e5ffa8ba9d17f088ee2e9bfa9653184d0
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed May 26 15:27:43 2004 +0000

    indent (left in tree since last indent action)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9220f91f9cb3f6725c874a459af277c508ce910a
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon May 24 19:48:13 2004 +0000

    minor reformat
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9da7ff91f5e2cd428451ebd7477025e1dad7b716
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon May 24 19:04:47 2004 +0000

    added AGP support for AMD K8
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7b095aa1d932099f11800efaf1a5f431e8c8acef
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon May 24 17:35:52 2004 +0000

    minor reformat
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c8ccf8ac0a1ff08e2494588a235462e56eb7b36a
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Mon May 24 17:14:21 2004 +0000

    Definition fixed by Ollie
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e6d1c9fe04d2885799f5740c45174ee192ddc95
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri May 14 17:28:47 2004 +0000

    refactored k8_cpufixup, added IORR support for AGP aperture
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d34b943d366555723d6063da10fd1a1f911d1302
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri May 14 17:23:26 2004 +0000

    refactored mcf3_set_resources
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54f05f6c5cc276bf6c95f5790ac14335efa7554e
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri May 14 17:20:29 2004 +0000

    use #define macro for pci class ids
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 13318d9feaad6b532896c432fbd5e5b22b37f5e6
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu May 13 20:41:49 2004 +0000

    code reformat, remove BY YHL comment
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b7ae8cf8a347460df70e7e7bef10611bba5be438
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu May 13 20:40:12 2004 +0000

    don't enable VGA/ISA here, it is done in device.c:allocate_vga_resource
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a8745ae578531617deab7c5de04d4566e3d0b45
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu May 13 20:39:07 2004 +0000

    code reformat
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5002af6a1895d53978e92217bd7a579f0fdf43e5
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu May 13 20:37:02 2004 +0000

    seperate font file from btext_console.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97027fbede3ec42d1c5591f0501ff0b11812f61c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu May 13 20:08:45 2004 +0000

    add comment and new config file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9e17d4f2e2e40a63776cb2b9f2f99109bb86b7b9
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu May 13 16:49:53 2004 +0000

    back out immature amd8111_enable stuff
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd3f2d794538852e77e852e99fe7d7d43ceee93a
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed May 12 16:34:46 2004 +0000

    remove unused l2 cache configure, if we really need it some time in the
    furutre, it should be in cpu specific fixup code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a60bf67b32090ef97cfb78e7968f5ece9e344063
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon May 10 19:33:27 2004 +0000

    fixed minor bug in APG bridge code. Use AGP_APERTURE_SIZE instead of IOMMU_APERTURE_SIZE
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9f0d0f9669a2421398700292dbb377eff125c4fe
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon May 10 16:05:16 2004 +0000

    rename walk_static_devices
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 75337f7500cbddc1bea2927573c8eadaa4455d7f
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri May 7 21:56:48 2004 +0000

    code reformat, fixed a bug in set/unset logical operation
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 89666e4893bf51eab4f20137f2f65a385d37ec09
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri May 7 21:54:23 2004 +0000

    change walk_static_devices() to scan_static_bus()
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb4c50f6950ac76dad88cc8c7ec8511321be0db0
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri May 7 21:52:47 2004 +0000

    code reformat, doxidization
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3bb314725aee90ae9436ce3b1d7e9e29f8e2d473
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu May 6 21:39:39 2004 +0000

    replace up,across,down with ltd0,ldt1, ldt2
    Although it is not used currently, misuse of terminolog is still a misuse.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9782f7538c3a7c0623d2177d10cc7785336da47c
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed May 5 21:15:42 2004 +0000

    code refromat, doxidization
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ccff4ea0c1773e57b380cf7477febd64b58afea
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed May 5 18:03:42 2004 +0000

    Disable AMD8111 USB2 and remove hard code addr in amd8111 IDE
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52f851dd1da8cefb3fb6e4795dc419d76d2b50b1
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Apr 30 23:11:23 2004 +0000

    put extern keyword in front of declaration, make the compiler do it job
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d16753be863e6c5729af904f4034495b4a58efe9
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 29 20:30:02 2004 +0000

    chaged chip_device_path::enable to chip_device_path::enabled,
    again, I am the only one who can't speak English.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 69c5a905ede8053fd2993ed2e4ff14e9970f2dce
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 29 20:08:54 2004 +0000

    changed dev->enable to dev->enabled. Sorry, I am the only one who can't speak
    English in the project.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fcdd571aee7592bd3f67283e70fba7608091ba04
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Apr 28 18:49:24 2004 +0000

    corrected irq and mp table according to new bus enumeration
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 500497fc34189473f989add8f281bcbf90c341c9
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Apr 28 08:08:06 2004 +0000

    indent
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97c4947ec9af1664e81ee797834a32d3ca2f74fe
Author: Yinghai Lu <yinghailu@gmail.com>
Date:   Wed Apr 28 05:37:36 2004 +0000

    Changes for btext and etherboot and filo merge support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 48d11d557f725ecf89678a1b9df440417b8da225
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Apr 27 17:00:40 2004 +0000

    Fixed the device on bus 0 problem for IBM/E325. The structure mainboard_ibm_e325_control is
    not actually defined in the mainboard.c. It was only declared in chip.h. Why gcc did not tell
    me this mistake and why gcc does not complain about define a structure twice ?
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5782d273eb79ed32d344273cf344b1580a936183
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Apr 26 17:51:20 2004 +0000

    check in the current code for IBM/E325, can somebody help to fix it ?
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1e1a34fdd184a85569b645923b743ec5524fab1d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Apr 26 17:43:30 2004 +0000

    comment out scsi controller init in s2880 mainboard
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b6ce3ec68ccddc58b7650d6250c77773b669e65a
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Apr 24 23:25:56 2004 +0000

    indent files to reduce the noise in further diffs.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 234454d900a000e4dfd969dff6e5b95831ed2918
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Apr 24 23:10:51 2004 +0000

    add missing include files for btext console. add YhLu's fixes to ragexl code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ab88d1179d46e4e5242286b59ee8519fa79bb05
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Apr 24 23:01:33 2004 +0000

    Major merge of YhLu's code from 2004/04/20: add s2875, various other updates,
    cleanups. Drop "driver" code from mainboard directories and use them from the
    driver directory instead
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f05dcb8d7afb3716959b94b8dac20ee551762624
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Apr 24 22:29:44 2004 +0000

    Add btext console (from YhLu)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8581ac215d560598c795caaba95a480459611a60
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Apr 24 22:26:19 2004 +0000

    Don't optimize link read pointers for UP systems (from YhLu)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7e20f402e827314f772e15217061e25ca181b715
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Apr 24 22:10:06 2004 +0000

    Commit YhLu's SATA code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6500af4172c56b374812d6d3fbe41f2bdd84e62f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Apr 24 22:09:38 2004 +0000

    commit YhLu's intel nic code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 09e7b45b996257bb77521aed38a814883b68d3a4
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Apr 24 22:09:12 2004 +0000

    commit YhLu's tg3 code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f898d889b68e025afa7b50b0ad99c2f1844c2109
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Apr 24 22:08:50 2004 +0000

    commit adaptec driver
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3afb677335d5fac6bfde16a281f9fc4d576cd57a
Author: fb2_tyan_0420.change.diff) <fb2_tyan_0420.change.diff)>
Date:   Sat Apr 24 22:03:36 2004 +0000

    commit Yinghai's patches to targets/ (from: fb2_tyan_0420.change.diff)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 70adbaf2cd07779811115984af3aded9a26726fd
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Apr 23 23:13:00 2004 +0000

    configure board properly
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bcfe3ecb2c9ee17116a3bc4091c656acf07f4ffc
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Apr 23 23:10:46 2004 +0000

    use fs stream
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b717e48352fe5466a92431f1597b85f902d75673
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Apr 22 22:31:49 2004 +0000

    start of epia-m port
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9dfed56e6384e66294f19851b8488412b3bb751
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Apr 21 22:54:09 2004 +0000

    wrong argument order
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c36b4275c6a3756cb0118f5b619299ab1772e19a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Apr 21 22:30:47 2004 +0000

    added cache initialization code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12c3154cee6b0c8167d4bf704c5ca25291c7ef71
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Apr 21 22:26:08 2004 +0000

    moved to crt0.S.lb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be167e79cf23bfc530c6973a7879a2451c28e422
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Apr 21 22:13:46 2004 +0000

    i like ori better
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f955af80d957f9435ceaa460fdb5282bb99f9fc8
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Apr 21 22:10:43 2004 +0000

    include cache code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1519 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c6bcedb2c45a0f759d152cd263751184022ab67a
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Apr 21 16:57:05 2004 +0000

    yhlu's pnp patch
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 771b1aefa3415eb644bfa030772f00b2178b368a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Apr 17 02:55:42 2004 +0000

    updated
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e126fa43dcaebb4bc2dda64be2ee7caeb92a6eea
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Apr 17 02:52:22 2004 +0000

    get file names right
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bad27b10c48d2b6ad7fbfeabc91bd1de594eed3b
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Apr 17 02:49:43 2004 +0000

    updated
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e0586200b61cd5bf4a3f59bf7ac68efc6f9ac17
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Apr 17 02:36:47 2004 +0000

    start of epia-m port
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 550999eaca74ba5bd5663c584bc04239def15fc1
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 15 17:33:54 2004 +0000

    hand crafted mptable
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e79fc3fa892f3a44f127239012dd3794cc71bbd
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Apr 15 17:33:21 2004 +0000

    code reformat
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6463ae7f1bd1f7ab60725529cf79af30a0e7297d
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Apr 14 22:24:50 2004 +0000

    seperate checksum and code generating code.
    use mmap instead of file io
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 815a80316448f72ec9501da5c545595c30880e70
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Apr 14 20:54:37 2004 +0000

    hopefully correct IRQ table
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c4c00404b44bd364fd484321602f9dcc4e5e4af
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Apr 13 23:19:27 2004 +0000

    removed unused assignirq.c and aute generated irq_tables.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1dad71bf324188de47036afd738ef9737ce23066
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Apr 13 21:08:28 2004 +0000

    back out incorrect commit on config.g
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd8f02f762f50de5df348c24dbff978c34e74f2c
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Apr 13 21:06:45 2004 +0000

    porting getpir to freebios2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3f5b4660b6c50af57a8599d54b5d84026e0de5cd
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Apr 13 19:10:48 2004 +0000

    add missing return at 205
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e0f0959ebeb2b96b3112a7426d6583cd7d08767f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Apr 13 13:28:23 2004 +0000

    use blade3d driver from drivers/ directory
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ffd67bda4e67b43337dab9df2467cdda2789e29
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Apr 13 10:46:15 2004 +0000

    commit trident blade 3d driver
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 35902425b8e3d346ab38112c95eecafe579f730f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Apr 13 09:44:37 2004 +0000

    submit ati rage driver.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a56d51d54a0b1c119e5f9f8d913b625843ed985
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Sat Mar 27 00:31:03 2004 +0000

    data tye consistence
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39daaac582766e94a6f2f8ad00900e623d514d7a
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Sat Mar 27 00:18:15 2004 +0000

    removed false alarm of erase/write, use verify '-v' if you are not sure about the integrity
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4cd79f3f86e5b57419932917750b022989e36b0c
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Mar 26 21:34:04 2004 +0000

    YhLu fix on multi ht and s2885
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f92e14dd4265cef7bd6554df4c3a3ae13c0e6ce
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Mar 26 20:26:13 2004 +0000

    remove tyan mainboard specific hypertranport.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8cb91dc9f832cb3df7aa74b4990a297d48133cfb
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Mar 26 18:34:48 2004 +0000

    speed up ecc clear by enable MTRR/Cache first.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23e2e18960d5ffed4bc8bb082f1ef8e471307657
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Mar 26 02:32:45 2004 +0000

    cleanup code to remove warnings
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 27916da0a914ee6e096bb98b4e5112511221281f
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Mar 26 02:31:25 2004 +0000

    removed duplicate function
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c34bfd78dd7da7ac0aeb21f30c9eae8e6b2781e
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Mar 25 18:17:36 2004 +0000

    disable pci device dump
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68a5e08499e0481b378174aa0bc3f2d059c178f9
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Mar 25 18:04:18 2004 +0000

    make log message a little prettier
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit edeff59c72f5ae0218a8366d38274947d2b48f8d
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Mar 25 17:50:06 2004 +0000

    YhLu's patch for multi-ht-chain for S2885
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 30667d75a63495e98fc5e228af510f29a6e575fe
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Mar 25 17:35:13 2004 +0000

    sio-enable, because the init is not called. Without the init_keyboard,
    the keyboard will not work under kernel 2.6.3 or later.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7500a7a4a7fec0d8b4a7cc1a4206e7016b462007
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Mar 25 09:49:22 2004 +0000

    remove traces of coherent_ht_mainboard
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88be4dd782e05f4f3d26986ab0251012adca4993
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Mar 25 09:34:58 2004 +0000

    add target configuration files for Tyan s4882, update tyan s2880 and s2885
    config.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 01f887d9f8546be08b51a2752af0473ab51e4214
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Mar 25 09:31:10 2004 +0000

    Merging patches from Yinghai Lu (fb2_s4882_changes.diff.bz2):
    - new motherboard: Tyan s4882
    - minor changes to 2880, s2881, s2885, s4880
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7011f9f0fe2eb5622fc60c82786ef2ae6655c5f5
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Mar 25 04:41:27 2004 +0000

    breaks PPC
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c1a14c203000e28b295d92f033f699df1bb3737
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Mar 24 22:59:47 2004 +0000

    drop obsolete CONNECTION_x_y macros. Use row information instead.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 650b6d0b61087d979f18f57b64ede4ff9d1c56f6
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Mar 24 14:10:45 2004 +0000

    Further trimming freebios2 towards code reuse.
    Unified AMD K8 reset function that can be customized via mainboard Config.lb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b01fb94995a5d1fcd28bcbe7e6e509d69954c7c8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Mar 24 12:28:18 2004 +0000

    small step to clean up mainboard directories. debug.c was basically identical
    on all amd64 motherboards, so it moved to the amdk8 specific code.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e52666931a3e34895b3f3b92641de9774ab722ec
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Mar 23 21:28:05 2004 +0000

    Doxidization, reformat
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9f46132e9627d24f3ad76619cf3340006a4012fb
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Tue Mar 23 17:41:15 2004 +0000

    tighten up option exporting
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f8311ae58ee66ce7ba774bf95894612d92f748d
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Tue Mar 23 17:37:02 2004 +0000

    These changes tighten up rules for exporting options.
    
    1. Exportable options ('export used') used to be exported if referred to in
       a 'uses' statement. These options will now only be exported if the
       option is set, or the default value is changed.
    
    2. Options marked as 'export always' with no default value ('default none')
       used to generate defines with no values 'export k8:='. This behavior
       has changed so that the option will ONLY be exported if it has a value
       assigned using 'set' or 'default'. Otherwise it is an error.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17350f1391d8cf0b30d5cf3583470d0ff786bc9d
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Mar 22 22:21:36 2004 +0000

    ibm e325 work now
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e33bbec41247d90e5669b817bf99e0c8af357f6c
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Mar 22 22:20:49 2004 +0000

    fixed minor typo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit addc53e56d6305d8ee3ae897bc8531511cfe1f46
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Mar 22 22:19:17 2004 +0000

    more jedec standard consolidatation.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2619721692f979656ec26d9a24dd777c875a0e53
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Mar 22 21:44:51 2004 +0000

    fixed to follow linuxbios usage.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a28f1c3183de9ed02e8a5c0de946c3dad60965d0
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Mar 22 16:14:40 2004 +0000

    update configs (use etherboot for now, enable acpi)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bfdc56231b91b8a2d8a40d87821dd6d0d8392515
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Mar 22 04:24:29 2004 +0000

    return to debug
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7ebb9e9eb87ffb400aa09430c582b1a51b7fc5c7
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Mar 22 04:23:57 2004 +0000

    updates for the E325
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 132f2c49003a647c3d063de0efe42a2ed64fc3b3
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Sat Mar 20 17:39:43 2004 +0000

    rmove unused #define and function declaretion
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e8274965d7c6a4b8d92076df74518cbdecf79090
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Sat Mar 20 17:05:01 2004 +0000

    I have no idea what i was trying to show off when I used the while loop rather
    than for loop. Please forgive me, I was too young 4 years ago.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fbf43ac5a6d90468b4f32c0ea0fc29bd41fabf87
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Sat Mar 20 16:46:10 2004 +0000

    consolidate more jedec standard code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a1a1102ea2cd8aed7014c90241f8db7b71847f1
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Mar 19 22:10:07 2004 +0000

    remove duplicated code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9e06c26925282d322b822d60f723d7753e71b2f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 19 21:02:36 2004 +0000

    serial post returns!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7f845867563365bbf054a0ff1cf55bb9732e72e3
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 19 21:01:49 2004 +0000

    fix up for serial post
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 826c38103855718191c43149fd24c50b470d96cd
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 19 20:28:46 2004 +0000

    fixed the memory reset lines.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a0be1fc307d65d819d69b7fee2da9b2daa5b444e
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Fri Mar 19 20:05:42 2004 +0000

    Includes fix from Craig C Forney
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3bd1f94c769005d21c215a6254ce56fc22dc6ebf
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 19 18:09:20 2004 +0000

    simply change for keyboard
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 73da276bc79bec7c66bac7b6c0fafc7957f5e3bf
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 19 18:00:40 2004 +0000

    some fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2bb6988c6aab66886562fa871eff76beb0853468
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 19 16:36:46 2004 +0000

    fixes from Eric's last commits that broke things.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3a59bf1047475d6ba0cd18dae8860c77a19ea21
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Mar 19 15:58:18 2004 +0000

    fix typo that keeps solo from working
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 08376d1c66648aca87377733692102dbf69eb14f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 19 14:57:50 2004 +0000

    fixes for various wrong bits
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4fac6cfef8737a5538c0f5b73811e010bf8432b5
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Mar 19 12:32:09 2004 +0000

    1.1.6 adaptions
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1943d501b4da5ad1de370208a4b64e177c55fe2a
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Mar 19 12:15:19 2004 +0000

    adapt to 1.1.6
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0eed64bf66c91cb75bad04e6dc11c5a0e7c07670
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Mar 19 11:38:26 2004 +0000

    more compile fixes.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 05c4377cce320bb107f1ed87cbdf3920f783e313
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Mar 19 11:27:40 2004 +0000

    compile fix
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3c79ed89beddde0655775da6d5947a56b86f3cf
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Mar 19 00:08:48 2004 +0000

    number of bits should be called log 2 rather than base 2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5b033b1f5dc720a5138fe6a8e8cddee9045069ed
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Mar 18 22:07:14 2004 +0000

    Add e325 stuff
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5136e1500114b7b2dcfb2eb644bed2fc242e82a1
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Mar 18 22:00:56 2004 +0000

    e325 support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 62705ff974fc37241ae992676b11856a30c29ed0
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Thu Mar 18 21:59:05 2004 +0000

    Added support for SST49LF0xxA parts.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ca52c64b43d35bf1533750b6c56d6687881272d
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Thu Mar 18 21:55:22 2004 +0000

    Added support for more SST 49lf0xxA parts
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 52a84d71460ce4518b66507d7e4e652b761a1fad
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Mar 18 20:35:33 2004 +0000

    forgot a semicolon
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f485e684956d0177b77cc58428a55a447793262
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Mar 18 20:31:54 2004 +0000

    removed unused code in pm49fl004, remove experimental delay in sst49lf040
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit df273a58a3b6462242af05ec917b8096952ac9d4
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Mar 18 20:27:33 2004 +0000

    fixed stupid i++ evalution order bug
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26b237ee18cf3f846313d85dcb80fb42041c3529
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Mar 18 19:40:07 2004 +0000

    fixed 32bit v.s. 64bit long int arithematics
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 698f23db22cc71da488eb9bec001fda60cbf0b35
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Mar 17 23:03:37 2004 +0000

    removed spd_dump.c, it has nothing to do with flashing flash parts.
    use standard product ID exit method for w49f002u
    move udelay stuff into its own file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e74ff463c488acdc300a9486b4f1b749e841a30d
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 22:40:12 2004 +0000

    typo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be392c8fe8f53419abb2d5f25c17191b078dc54d
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 22:38:42 2004 +0000

    use IDE stream
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f53bbd89083785e56341b88c48d5c1f12530f582
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 22:37:43 2004 +0000

    use filo boot loader
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 317cde826df9bea683fda5cc4207d3bb10c6bb54
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 22:35:52 2004 +0000

    added spin-up delay
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 115bd0549bfca99a49e5d929820af605dab715b1
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Wed Mar 17 22:22:08 2004 +0000

    move utility functions into new source files
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc2ad05e6f478a16e68d926448c6337f1c4fa436
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 22:11:51 2004 +0000

    remove debugging
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 717d70de26f21756f385a33a3af3676a179a4fb6
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 22:11:11 2004 +0000

    remove more debugging
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bcfa0d38d27aeaf3421bfdfc29c6e0c4047df232
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 22:05:28 2004 +0000

    according to spec, sector size is 2048
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7575fba6f3949596a0cc301e2deca38833c9a982
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 22:04:22 2004 +0000

    remove debugging
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9bc501825962dc630405dcd413ea67a12ebfedf9
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 22:02:12 2004 +0000

    ppc fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 983b189d919e78953e74915506f68e1be59143ba
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Wed Mar 17 21:47:30 2004 +0000

    Added support for SST49LF040
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cfecd14900bdd697985a18af784dec25a3f44a1
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 17:10:32 2004 +0000

    filo boot load support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43ba521bd94fc9ea21faf22f21b4d17085ca3841
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 17:06:06 2004 +0000

    Checking for slaves on the IDE bus seems problematic, at least
    on the Sandpoint. Make it an option.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 582231ed01d56381d0ac714a1157ffe739edcac4
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 17:03:02 2004 +0000

    FAT big endian changes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f6d05f501ec6a28fdc53e3876cab872c11e0ab73
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 17:02:28 2004 +0000

    added funcs
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a795cfc8dad97f71a41a3ba6a4574a4f2e223cf
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Mar 17 17:00:50 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 711c8bddfed6eaee3775d71dd903c9c1daa50342
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 04:04:58 2004 +0000

    added fat support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12f5ef5f876e27b12887e14581de0dc106928170
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:54:08 2004 +0000

    added atapi support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e54edf7a1805ae208de9784bd447fc2a382f6f76
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:52:19 2004 +0000

    from filo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1f50e94d88fa163b5af0b2485fc24b9756800e1d
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:48:44 2004 +0000

    byte swapping
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 96ce0b4bd147af313baf05612e80b959b61290f0
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:46:41 2004 +0000

    removed unused code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f62047061dcbfebef2471792a0dac5b13a78579
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:43:29 2004 +0000

    byteorder routines
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e54d55b9d935745c2aa3f07712b857af42506c0d
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:40:51 2004 +0000

    added rx support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5c51c3d9d945ae77c93073db5624728959cf4c74
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:40:29 2004 +0000

    tidy
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54b165820246b73cb23643aa8c3e2e8fb567e5ee
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:40:03 2004 +0000

    added realloc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef71326b8e4a2d5e69b8f1537b04c9257b7b8240
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:39:09 2004 +0000

    filesystem support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f566ca1c0cc9e3b2984fe684e7df07d5dc73c53
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:37:11 2004 +0000

    byte swapping
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1624782bbe44018a1784cf78839bc4ec95802fdf
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:34:52 2004 +0000

    extra functions
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd27f5ee344dcaf5c843adbff4f3f3a115dbbd40
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:34:26 2004 +0000

    added realloc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3cd7fc7640b18b3ccefabee2dc03432217c6ed58
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:33:34 2004 +0000

    filesystem support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d2478e962772c46eccdb9a93359710b0ca01dce
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:31:42 2004 +0000

    use CONFIG_IDE for ide support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8a31c510c51f190ae5e1d3d5989ba8cb3f162b9
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:30:18 2004 +0000

    Fix file broken by Erics changes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cfaeaf6d2dd62476fc3234976d042fae16336b21
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:28:05 2004 +0000

    ide support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8603e2ac2b8595f04e60987bcbb19284e82d5e8
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:18:32 2004 +0000

    filesystem support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b9f5c112ccd0e39b0652ba8496e2ebd0cb0c5fb8
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Mar 13 03:09:57 2004 +0000

    filesystem support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc2ae8ee9f3b90876d30d80ffedaefa3fcb243f2
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 12 23:45:38 2004 +0000

    added device numbers
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b3da970964339dabeedd4384ae21ce4917825937
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 12 23:38:20 2004 +0000

    starting point for 87366
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd714cf120bdea2faf638efeaf4617c80522ce16
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 12 23:02:05 2004 +0000

    new support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a6aca79ff038db75f2ef3cbddedb79caefac5358
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Fri Mar 12 22:29:41 2004 +0000

    fixed halt on ht rest by change bus numver
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 142babf1e5348288ad852c6cab3b10c931f73206
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 12 16:54:31 2004 +0000

    forgot to do a cvs add
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e4fc0ab250bd88ad8833a90d9338fd5b35881ebc
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Mar 12 15:13:38 2004 +0000

    fixes for tyan
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a40a17c50cd10afea78bc5c1e41e486b9c4aa078
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Mar 12 12:18:25 2004 +0000

    cosmetics.. we'll not see more that 256cpus in linuxbios for a while
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5cd81730ecef18690f92d193b0381c103a5b3d9b
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Mar 11 15:01:31 2004 +0000

    - Moved hlt() to it's own header.
    - Reworked pnp superio device support.  Now complete superio support is less than 100 lines.
    - Added support for hard coding resource assignments in Config.lb
    - Minor bug fixes to romcc
    - Initial support for catching the x86 processor BIST error codes.  I've only seen
      this trigger once in production during a very suspcious reset but...
    - added raminit_test to test the code paths in raminit.c for the Opteron
    - Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED
      so we can tell what we have really done.
    - Added generic AGP/IOMMU setting code to x86
    - Added an implementation of memmove and removed reserved identifiers from memcpy
    - Added minimal support for booting on pre b3 stepping K8 cores
    - Moved the checksum on amd8111 boards because our default location was on top of
      extended RTC registers
    - On the Hdama added support for enabling i2c hub so we can get at the temperature
      sensors.  Not that i2c bus was implemented well enough to make that useful.
    - Redid the Opteron port so we should only need one reset and most of memory initialization
      is done in cpu_fixup.  This is much, much faster.
    - Attempted to make the VGA IO region assigment work.  The code seems to work now...
    - Redid the error handling in amdk8/raminit.c to distinguish between a bad value
      and a smbus error, and moved memory clearing out to cpufixup.
    - Removed CONFIG_KEYBOARD as it was useless.  See pc87360/superio.c for how to
      setup a legacy keyboard properly.
    - Reworked the register values for standard hardware, moving the defintions from
      chip.h into the headers of the initialization routines.  This is much saner
      and is actually implemented.
    - Made the hdama port an under clockers BIOS.  I debuged so many interesting problems.
    - On amd8111_lpc added setup of architectural/legacy hardware
    - Enabled PCI error reporting as much as possible.
    - Enhanded build_opt_tbl to generate a header of the cmos option locations so
      that romcc compiled code can query the cmos options.
    - In romcc gracefully handle function names that degenerate into function pointers
    - Bumped the version to 1.1.6 as we are getting closer to 2.0
    
      TODO finish optimizing the HT links of non dual boards
      TODO make all Opteron board work again
      TODO convert all superio devices to use the new helpers
      TODO convert the via/epia to freebios2 conventions
      TODO cpu fixup/setup by cpu type
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f31d5542f6e193595da0f66aea68602910984861
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Mar 9 15:56:38 2004 +0000

    go verbose for now!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ffc6d2861489dae06415706293078a69666fe8c3
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Mar 9 15:33:08 2004 +0000

    drop dead code.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3d26484cc98bc24a7d375a45637671dc6b67585
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Mar 7 22:24:05 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit efa1f324afd56dae5c6917dd1715a3efaf3886e3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Mar 7 22:17:05 2004 +0000

    config.g
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c762e55fc9324299f993be7c4e1dfd56d07b3103
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Mar 7 17:38:43 2004 +0000

    fix caching problem
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7780fc6404defb1ffdada30b441c876e8073c6e2
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Mar 7 17:37:41 2004 +0000

    fix memory settings
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ac00a0a7e2a4a7dccf4cde3f4d7550c07df216a2
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Mar 7 17:28:59 2004 +0000

    fix caching problem
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dd9651017a39bbe64ed7de8f91df7e51ce7b374d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Feb 27 13:37:44 2004 +0000

    generalize code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3259784926c8282dbccdd9cdae43a3023718c80f
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Feb 23 22:33:10 2004 +0000

    correct the DstNode bit mask for IO/MM registers
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87144668b1c101f18955bb5c946afd172b85ed50
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Tue Feb 17 21:51:58 2004 +0000

    removed unused set_var_mtrr() (use intel_set_var_mtrr() instead).
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ac3888da5eb48fb8e769153ce9b98b21eeadbbf6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Feb 13 23:09:54 2004 +0000

    fix makefile
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c4bea221e038e40044100875119ad4e5aad0876f
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Feb 10 21:34:18 2004 +0000

    now we support 8111 and these parts.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1375 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f69f7e252f1cca6a891dcaffcad763e91189e7b8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Feb 10 17:30:04 2004 +0000

    add option rom section
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c0f4e2aecbec701d5e6d7f21c29c7deec6bfdf03
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Feb 10 16:53:55 2004 +0000

    small ACPI addon
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2d3cf24580cbc4182cb08c21bb421fffe44741dd
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Feb 10 11:21:18 2004 +0000

    fix broken stuff :-(((
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 854e45292b71a0f2777d8ec2edc0d9d6fd1326bf
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Mon Feb 9 22:47:38 2004 +0000

    final merge of YhLu's stuff
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c34d5ca790c5cad0c6366122b56fd8da02c5794a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Feb 8 20:17:01 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd8e17a8f16846bb35a6a2fd07720a5b087e92d8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Feb 5 10:00:35 2004 +0000

    enable hpet timer hardware.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b8a7578a120f70470a733292908b97261e9c518a
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Feb 4 09:11:51 2004 +0000

    - Update to the latest config.g
    - Everything except if statements should work correctly
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 06feb88cc60f78c2b3c7036208da68c4c1dc05e1
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Feb 3 16:11:35 2004 +0000

    create MADT tables, too.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7648c2942448bdbb2813868ac305df24a69fcd0
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Jan 29 17:31:34 2004 +0000

    acpi fixes:
     * move acpi to right position
     * change acpi checksums
     * clean hpet area before creating table
     * calculate hpet checksum
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4ece6620745bd288821d879c96be12fa5fb13ae
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 29 01:54:24 2004 +0000

    configure superio
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 64528cb29979382e382ccebd978d00b11d43dad8
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 29 01:53:36 2004 +0000

    use static config
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 053f89b05735901b5af990b41b68b408ddaea1b9
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 29 00:58:07 2004 +0000

    chip initialization
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 016c1b3d8a265c342c6f1fe15efc864082ed8ac6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jan 29 00:04:13 2004 +0000

    almost there.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e45714874ef75ed29bc5306ee86218a355b57dce
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jan 28 23:54:50 2004 +0000

    incomplete (wrong) support for this chip.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 688b385aec24157e2112d0efa06868b4f8dfb97c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 28 16:56:14 2004 +0000

    please forgive me... ;)
     * initial acpi support code
     * fix header
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 22489894e189616bb5694cfed8bd951951e68fae
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jan 27 17:08:03 2004 +0000

    will mainboards
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abf9fea4a0c975f56190d061efef9ddeb6b84f81
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jan 26 10:54:44 2004 +0000

    unify debug messages, fix typo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36fdcb8e2bd1e815b385ead72bd936458eae0d7b
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jan 26 10:16:59 2004 +0000

    Allow using an APIC without mptable.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a8d4ae27cbcc7b6de3cd54770d51ffa6707dd6e
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 22 01:06:19 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 909472367fe4bbc91c43c0d8c4d9acb10d95e737
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 22 01:03:41 2004 +0000

    memory mapped I/O
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9233e47d9f389a215112094ed5592a6c022417a0
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 22 01:02:56 2004 +0000

    UART0_IO_BASE no longer used
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 746376d641fd8f87987acbeb7de293ab14f4d4b2
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 22 01:00:22 2004 +0000

    cache.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aabdf02cdd461b0b3623fd047851ae9d2e872ef8
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 22 01:00:07 2004 +0000

    updated for other boards
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c5acd90b53f90363ed691a6fd63675af78fea971
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 22 00:45:13 2004 +0000

    try to get memory mapped i/o to work
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86da2207882bfaa9cc2f7772675d5e5717ac0a10
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 22 00:21:29 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 49ad3fe4c3714519bce35760c6354cf404ee881a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 22 00:09:10 2004 +0000

    get memory mapped i/o working
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a186938b0e6ea484ee87008c0e353bae8593261
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 22 00:04:58 2004 +0000

    clear IR & DR and enable FP
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 47624a8e1356fa0f60641bc71f9e096db133820f
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 22 00:02:12 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6cc2a5c4c420c7a520e5c173bb57bce2d817e665
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jan 22 00:01:20 2004 +0000

    init.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 063f3d9395fde6b7fafe22d82e0d3b1be51694f9
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jan 21 23:56:37 2004 +0000

    default values seem to work fine
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 87561c7acd3fc44f51aefe323b9c7a6e3575f086
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jan 21 23:55:59 2004 +0000

    pass ide base address to driver
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 456764dd30dd93a64afed195e4dad1436905b8ac
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jan 21 23:52:49 2004 +0000

    changed routine name
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8af609f2fe4652bb54d62a5615ecdcada18bcaf0
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jan 21 23:50:56 2004 +0000

    trying to get it right...
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8a1678fb9084a98eea4100b9a10ab52576565709
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 21 16:40:41 2004 +0000

    adapt irq values to pirq table
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a65b14ab50f55894b2d9c84c073cffea0cb1e05d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 21 16:26:44 2004 +0000

    simpler irq tables
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd4be244bb0aa951f15dda2246a83f6da5734b55
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 21 16:05:40 2004 +0000

    update mp table and pirq table
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b020d53352c1bbe1084c9c499b45cfb345fc8677
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jan 14 17:21:22 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bf5b58480129dcd6a770f3f2b237511fb295918e
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jan 14 17:08:14 2004 +0000

    allow TTYS0_DIV to be set explicitly
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 696ba78a1359b311b85c55aead4511f76a1b1607
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jan 14 16:47:55 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c39094e20ee3a99d24284aeb48c1a84068dd8d52
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jan 14 16:41:17 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd1f22cfeff3da84189aff8da95ac0a8a7c3fa53
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jan 14 15:46:30 2004 +0000

    small fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d0ac932cb5c80514856d1f17623f4c78abfd82c
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Tue Jan 13 22:26:04 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ff2ab96495c3128fc4adebd6a3affe294036fe7
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Tue Jan 13 22:18:03 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 24aa3c8cf1de47c2732c73c4450417b8c79cf2c6
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Tue Jan 13 22:01:09 2004 +0000

    Options for briQ
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f6e4357130b0930fcdcf94f3c35460bd23be58c8
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Tue Jan 13 21:59:17 2004 +0000

    Total Impact briQ
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f0721563b48ff7e2ad1bd7398da2747ec1a3b055
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Jan 12 20:00:43 2004 +0000

    Tyan mainboard changes form YhLu
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12eee5111f4a6ba87f48bb7db9c7d42f1ea77d07
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Mon Jan 12 17:45:27 2004 +0000

    Tyan S2885 changes form yhlu
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit db7f47cbbffb532deacb2be4fbfa15f6f3a4ef55
Author: Li-Ta Lo <ollie@lanl.gov>
Date:   Thu Jan 8 21:15:49 2004 +0000

    Change PCI_BRIDGE_CONTROL to PCI_BRIDGE_CTL_VGA
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88c4ed576f672def4afc59e71e0d9b9e6f2b7648
Author: David W. Hendricks <dwh@lanl.gov>
Date:   Mon Jan 5 10:16:24 2004 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3e8f1f7fc6819724632a6fe381708a9ece1aced
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Dec 17 18:03:26 2003 +0000

    printk before hardwaremain()
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 16f4e2cb1ffdc976e66aef202960782235a872ba
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Dec 17 18:01:44 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b362c498014a79928f9adb99edf7c0ae4d700cc
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Dec 17 17:51:35 2003 +0000

    use new pci config setup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5965169dada590e728cd0b7140b17bac0f63d336
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Dec 17 17:39:53 2003 +0000

    Don't compare low 8 bits, which are revision.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8549836ef46625aa31ed8554e557652a7d5bc2a4
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Dec 17 17:34:30 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 886b1788c97dfc94c3c7af6f62b7bf6f5a6f303a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Dec 17 17:32:58 2003 +0000

    pci configuration
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fde64ff3a126d57bc55bc11f915c33a7cd26406e
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Dec 17 17:29:21 2003 +0000

    clock.c need in startup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6c11dfc4dea30839dbc618b1eb6045192b1b532a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Dec 17 17:28:12 2003 +0000

    needed for 4xx startup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4b949c340ac98de451a71a8464bb61c6bc6380bf
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Dec 17 17:27:20 2003 +0000

    added _outsw_ns
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 139ef8aa682059b11793639bc49cc76d28916713
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Dec 17 17:25:32 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 17729a2ebdcd9c014b6fbc6ac7fee948fd24b1d0
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Dec 8 21:48:01 2003 +0000

    - Set all of the fields in config_busses before we use it not afterwards.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0cb44b5cdf6ca00e885ecd70aafac255425cda2b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Dec 8 21:29:26 2003 +0000

    make it a manifest constant
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 80b5240c75e31f708b55578954dbe923baf4c4d7
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Dec 8 21:06:55 2003 +0000

    fixed irq slot count
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 766ae4a4d14c178ffda5e43e0eeb9021d3cbeaa3
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Dec 8 17:29:32 2003 +0000

    missing file.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4ab9f1722a7789e6f3811038fde2c0fe9b7908bb
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Dec 6 00:11:56 2003 +0000

    - Fix amdk8_scan_root_bus and amdk8_scan_chains so multiple HT chains
      can be scanned in any order
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a4aef6d3bbcace86288b3c1b0c5beb865effbd98
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Dec 5 06:16:19 2003 +0000

    - Lower DEBUG_CONSISTENCY to 1 2 is only really useful when debugging
    the register allocator.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 12d2e683f45f19fe62d5893ce7b7329009a9a00c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Dec 2 20:43:08 2003 +0000

    s4880
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7c8d35273f40f14f865b54550610d94cd49d4902
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Dec 2 17:56:31 2003 +0000

    fix quartet and S4880 spd initialization.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f4f1d48d9dd93c58ef4f8233f36aa6246b7deb5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Dec 2 04:07:18 2003 +0000

    new
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8aa7bccc9dcc51213f3b15f91f2d4985203f16dd
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Dec 2 03:58:19 2003 +0000

    from Yh Lu
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 13f8c07850ef34af891f0cffe287a0209b57f259
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Nov 27 11:25:01 2003 +0000

    update
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 221cb417ff63ea5f84a994d135b5c276c5be9b51
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Nov 27 11:01:47 2003 +0000

    fix AMD Solo target
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71212882bf8e00a28c6dff8cdeb47149506f0b9d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Nov 25 09:21:37 2003 +0000

    ignore build files.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 37414ca2c6e59649f8eee4da4a37b5ae57617dcf
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Sat Nov 22 15:15:47 2003 +0000

    initial version of LinuxBIOS on AMD64 paper
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dcac0161d443c6846092afedd58bb84e84e458ad
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Nov 20 23:09:08 2003 +0000

    fix stupid typo.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2816e883492eda094687432106323c7cd6080f6d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Nov 19 12:30:07 2003 +0000

    use fake spdrom on quartet
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7899a5fbb5f189eb5de2ce9750a37e55dc9ab80c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Nov 19 12:29:08 2003 +0000

    add FAKE_SPDROM option to fake spd on machines that don't have one.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 93cbf82e6e7d7ca41bbdec14cd030da0468c63f0
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Nov 19 12:28:07 2003 +0000

    faking spd setup for now on quartet ;)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d099e7fac6b9e1c49957c0f21cc346ab5e58b22
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Nov 17 20:55:54 2003 +0000

    dont know what happened here
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7c48c5bb1d865d31a8f2451580773d1bdc9aeb90
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Nov 17 17:33:14 2003 +0000

    fix default
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 370845147f9c74f79a9922b888819ef0d8f4bfcd
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:54:16 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 354955799b8c07cf9b8913b7499f6eed9792acab
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:47:53 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61065bc537782791c66ec54f75fc2b6504833f95
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:31:12 2003 +0000

    used pre-hardwaremain()
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d4295f2f830d0ab73346eb15eddf59838b48372
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:29:30 2003 +0000

    options for better control of rom layout
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 83348820150d5491d5ccc5ba9921fe5c007c16dd
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:28:05 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d57923c870a518a5431675b8c8453be9049cf884
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:26:02 2003 +0000

    added sizeram and init routines
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8fc392b4270d19ff76fef8e4e3236f74ce7e551a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:25:19 2003 +0000

    updated names
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 29581a3473af1d58a1aea6fe3fd9173ef5b654cd
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:20:20 2003 +0000

    done in C now
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4d7b729e4bffafde517628f9cc22bff929816439
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:16:56 2003 +0000

    setup and initialize cache correctly
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b3883f393ec9e06f5afa4a7c24c87a8791e2b459
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:16:09 2003 +0000

    cache is 32Kb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c1556ac427e14f9275da6526a621bb07546609b9
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:15:01 2003 +0000

    need this code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c70b5d2f3a7d6da24dd0f4c136382c93694b36c4
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:11:55 2003 +0000

    jumping to payload
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e14d10930f2d5f3c61d7d151f28b2d0a0a71f853
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:09:30 2003 +0000

    make sure stack resides in cache
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 78c19a11ebe9843aaee9c328205794b4c643a460
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Nov 15 15:04:58 2003 +0000

    setup for v2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4718ff415b0e0c6f32412a609b507d98f82b850
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Nov 10 14:34:46 2003 +0000

    automatically detect southbridge link. this should allow to get rid of most
    of the special resource maps spread over the opteron ports and make the code
    more generic
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da754e0586297faf0d3b5c378dce4226913833bc
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:35:11 2003 +0000

    updated for v2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e52d92c20f83479ccb6d644ecf362bdbc2316ff
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:33:59 2003 +0000

    running out of flash
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e3da4d3ce8ecf4e5424931a4ceba5bd8c82840cf
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:29:42 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c8ea12d672e9bbca92257448ad0c887a206beb46
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:29:05 2003 +0000

    support for init objects
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2f726c3e83da564b90f72b97cede8458c148f0ed
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:26:56 2003 +0000

    updated for v2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 33ddaac6fda0b114f95b6fefc13e08639a7d0e19
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:13:57 2003 +0000

    changes for v2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 91deab98a9adea9a4f2251ba73f46ca86f2acdaa
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:11:34 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54d4e651635c17979f27a615b18ba3550a91e7ea
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:04:55 2003 +0000

    fixed warning
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 86a17433e3b0447bf75e4cca87e337e1d2e49ac5
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:04:18 2003 +0000

    ticks_since_boot needed for sandpoint
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c8ee08a9bb7f3498ea1547991f314e990eb5463f
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:03:46 2003 +0000

    printk for init
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1c5a7f198c345c7b78387c033a5fcb1557ee05d3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:03:25 2003 +0000

    used in init code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a0725a74a877f7ee7ea781aae255637f935571ad
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:02:54 2003 +0000

    not needed when using init
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 43f74f7e4aadb4cc4c119ab9a018cdc5d0fd00f0
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 9 23:02:21 2003 +0000

    split for initobject
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6dc0d8c72d6c77e17bebe5d4099df2d6e2ab8f0b
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Nov 7 00:12:25 2003 +0000

    config.g change
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 526fce7f20c98500d62503815900e3e2401e601d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Nov 6 16:59:09 2003 +0000

    Make solo build again.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7d756ee6be9a89d88e3037836f297248c5181803
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Nov 6 16:32:20 2003 +0000

    fix build for quartet.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f552e9317f27171e08229d0c30aadfcc37125b14
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Nov 6 16:31:40 2003 +0000

    push verbosity as high as possible
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 01e375b4017288def095be8cf2d48fab147f448c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Nov 5 19:55:20 2003 +0000

    fixes for epia, attempts to fix arima
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8cb747942cc50e82cff381c935a5d816e1ceb801
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Nov 5 18:55:44 2003 +0000

    New option behavior:
    1. Options can only be set with 'option' statement in the target
       configuration file. Options can be set as many times as needed.
    2  Option DEFAULT values can be changed (or set) in any configuration file.
       Changing a default value will display a warning message.
    3. A default value is changed with the statement 'default <op> = <val>'.
    4. Setting an option overrides the default value.
    5. The 'mainboard' and 'arch' statements now set options implicitly. No
       'uses' statement is required.
    
    The idea is that parts will define default values for options that
    they need/use. Option overrides are only done in the target file.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae83b3641505a34acaedc031a9ca08957fdea217
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Nov 5 18:45:51 2003 +0000

    new option default format
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed46258ca924834244b03bbcc17231366dbbfe69
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Nov 5 18:21:30 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 097e6497abbeb65c698dce8f858e0d5f32a15da8
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Nov 5 16:36:57 2003 +0000

    fix volatile
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 433ae3fb4eb9ea8b371bac5df03357ee70a12ee4
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Nov 4 16:31:29 2003 +0000

    fix stupid stepan's bugs
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 978c16fb7077e5aaf2c138cdade21df43a7aaa06
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Nov 4 12:21:15 2003 +0000

    add hook for spdrom iohub selection
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 163309a7e649b3ec1a685321a53d6e35d2c1d5ff
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Nov 4 12:06:03 2003 +0000

    infrastructure updates to keep linuxbios building (needed for quartet)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ce10c96299d395928f8375a6ccb5f0a20e3fda0
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Nov 4 12:02:43 2003 +0000

    infrastructure updates
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 469bd43194f40481645b2b59ba2b16b05e9ab245
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Nov 4 11:57:10 2003 +0000

    make quartet compile.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab5ab6e55618d67106580bf1869558e7d1a36133
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Nov 3 00:17:17 2003 +0000

    add board_init
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4e17b848f850ddf19d1c8b33fc718cecbfe72476
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 2 20:04:08 2003 +0000

    new init code
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ea6f9dabbd19c0a8223e515e6cb92a749ed23eb9
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 2 18:17:47 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dbfec8f0640c52fb229272b795a1010dc01448da
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 2 17:06:52 2003 +0000

    copied for i386
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14a90f1aafa4ba151c9be224044749bda6ed520e
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 2 17:05:20 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1abd667fdf56ec17b736648c3f6d9a290c400b29
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 2 17:04:49 2003 +0000

    cant be extern unless defined in a library somewhere
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68a040dfa1595d2adbe5bd9a6d7a9ca72cdd5f82
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 2 17:04:06 2003 +0000

    moved to clock.h
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e8da0dafe5bcbd6ae24a2acf6813ac7bb9a222f
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 2 17:03:49 2003 +0000

    new headers
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 95e914781748db585186bb88ab88c02e4a97b8ca
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 2 17:01:47 2003 +0000

    fix timer routines
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5bcd408b8e72a582bfad61da827a51c2349d037a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 2 16:59:24 2003 +0000

    Do sdram setup for fixed memory sizes. This really only works on
    embedded boards that have fixed memory configuration.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6f2e86d2782425e8e5b902c2a2958cda4666f471
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 2 16:58:01 2003 +0000

    trashing stack
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 36ab698a013528c864933b4e8c836ac1dcd87138
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Nov 2 16:57:39 2003 +0000

    get cache setup right
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 40cba39e34ccbba6fd6ea7a3183b133f094a2466
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Oct 28 17:02:10 2003 +0000

    dynamic pirq table fixup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 72bc623a50dd0626300250f6f015c8ad082ebae1
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Oct 27 15:29:19 2003 +0000

    integrate initial version of blade 3d driver
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ccc6c23b3945bab957c8daea5953c19f1ae3473
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Oct 27 14:54:19 2003 +0000

    merge minor solo changes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5484eb6b43979eaf80f9e8966ea4185a51f669d3
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Oct 27 12:52:56 2003 +0000

    rename linuxbios.rom to quartet.rom
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d6fdac4622ca6fa091718dcdbf1e520a0243d013
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Oct 27 10:36:44 2003 +0000

    Call image "khepri.rom"
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 94c1b0ccc03c266b7bd40cba25add6d34b4d97fa
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Oct 25 17:01:29 2003 +0000

    due to popular demand, added flash_and_burn to the freebios2 tree.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 888df97971271655a2b3cacf96d509dadf15fd85
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Oct 24 14:45:21 2003 +0000

    merge latest quartet changes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e4436bd7f640170c03798914baa2c47690df5e61
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Oct 24 13:53:33 2003 +0000

    retightening khepri after last hdama changes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a9974e584cb6fa9baabc89145920403b98fbc930
Author: uid34869 <unknown@example.com>
Date:   Thu Oct 23 19:42:50 2003 +0000

    take out incorrect comments.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 367e5971646ca221bcff6d6003553d7b223b7333
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 23 15:09:58 2003 +0000

    fixes from SONE
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88fbae24bc83b46b1a1f2ba88643462053dae5cf
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 22 21:54:19 2003 +0000

    fixes for EPIA.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7f1105c431d8425cb1027e8c75787c826425c33d
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Oct 22 04:05:19 2003 +0000

    - Update the romcc version
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ade04a436c151d88fc02ca18e2de990d7b569dd
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Oct 22 04:03:46 2003 +0000

    - Update romcc to version 0.37
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fc76dcf0d00f9e1d28d128ffc43320d940f531a6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Oct 21 14:52:47 2003 +0000

    Fixes for SONE
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4398d1e5a9e2d2d384bd917cf679d17d43cd6c57
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Oct 20 19:57:35 2003 +0000

    early mtrr for the p6
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 472e74177c3f25b263ab312f9285dd41da1fe11e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Oct 17 22:21:07 2003 +0000

    Fix from SONE!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b56ef076002ee90ac08fbac5888b8b3374ce582e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 15 20:05:11 2003 +0000

    for tyan. recover from Eric B's error additions to via code :-)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 820dea8a628a862639da3c4a4d465422a94f3a8d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Oct 15 14:20:18 2003 +0000

    more solo fixes...
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3561759620d72df3ed305f826d336ce514e55e5c
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Oct 14 04:29:39 2003 +0000

    - Fix the link check so it actually checks for the appropriate maximum link
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5a71d1dca7484d084ddc016807cc8a740ad08372
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Oct 14 03:33:11 2003 +0000

    - Make the directory for config.py to live in
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34323b52e34aadaa9b1afe70031eb6dde0340232
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Oct 14 03:05:04 2003 +0000

    - Correct the logic in buildtarget to match the logic in config.g for select which
      directory to build in.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ad1b35a12b724b2083102fce493d4b03937a0cb1
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Oct 14 02:36:51 2003 +0000

    - Minor bugfixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb3e1edc0003f0f56954ab4f82fe4a290ff9bdb9
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Oct 13 20:07:42 2003 +0000

    Carefully select the directory for config.py
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3f7c9e655d9ec8cd44bbffbd33b56f3e47764e2
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Oct 13 19:48:13 2003 +0000

    - Move config.py into the appropriate target subdirectory
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 02560b5fa2339f2b1701b25e8628cca2f7df865e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Oct 13 11:49:46 2003 +0000

    move equal with hdama code.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b68571c139f2c73a643e2cce76ce5b00fdb2580d
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Oct 13 10:04:06 2003 +0000

    get solo target building with 1.1.5 sources
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b1c567892a4cd3f57d87d46fd4b6d4d934edbbf
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Oct 13 10:01:13 2003 +0000

    Drop obsolete ldtstop code. enable smbus_write_byte
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit abf9faa786c34b29b1703d45f7ffc10f4403544e
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 12 21:30:44 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 85862124fd6b069f21b4dbfd6bd7dade740ae82f
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 12 21:19:22 2003 +0000

    cache ram startup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f610d2466cb182fcc798bcbf99c1f12072144b2c
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 12 21:18:56 2003 +0000

    pre-mem startup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2caf089187115a524c28d49fa5da3aae18c777e2
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 12 21:17:59 2003 +0000

    naughty, naughty
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fe78c82c40032285c3a8848c0444d7f3bf094446
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 12 21:17:27 2003 +0000

    first cut
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 383f5f6897870d172246f09cdad4799fae342c43
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 12 21:17:04 2003 +0000

    get_bus_freq()
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 97c211e70fdf32d019b784fa75c31c5ed489921a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 12 21:16:35 2003 +0000

    memory turn-on
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 079d53232bfe7b6543c9efdeb19f9f96c5e5831d
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 12 19:07:39 2003 +0000

    get pci ops right
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 47e64e8bed9aed42897f0290bcd711deff65971e
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 12 19:06:53 2003 +0000

    missing directive
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 83b991afff40e12a8b6756af06a472842edb1a66
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Oct 11 06:20:25 2003 +0000

      - O2, enums, and switch statements work in romcc
      - Support for compiling romcc on non x86 platforms
      - new romc options -msse and -mmmx for specifying extra registers to use
      - Bug fixes to device the device disable/enable framework and an amd8111 implementation
      - Move the link specification to the chip specification instead of the path
      - Allow specifying devices with internal bridges.
      - Initial via epia support
     - Opteron errata fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 080038bfbd8fdf08bac12476a3789495e6f705ca
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Oct 7 14:56:48 2003 +0000

    remove SMBUS_MEM_DEVICE_[START|END] traces from code.
    add 8mbit example config for amd solo.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 198f0ddded83565034cad90040c8eaeba46823bd
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Oct 6 15:08:03 2003 +0000

    add missing -m32 flag to compile on opteron natively
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a84c6f81ef85bca8b1413324d0bccb549cf4b00b
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Oct 6 15:04:41 2003 +0000

    add smbus_write_byte() function. currently fails in romcc :(
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2e90c1daa07501f055a2a52107b9c99948eef4f8
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 5 05:16:19 2003 +0000

    no hardcoded addresses!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5b3b9aa5de84d4d564fb2c887f615a0953c945e9
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 5 05:15:48 2003 +0000

    standard functions
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1195 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b6a259b0d26d1829ac38db646d267543daed216a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 5 05:15:10 2003 +0000

    no need for assembly
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e046fbbb2cae62934ba4aae85d56456e7d7b3ff4
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 5 05:14:42 2003 +0000

    new cpu types
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be956f096f51ab8eae32f4ba58b1cd4716d057b1
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 5 05:13:12 2003 +0000

    size memory
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ccf4d34bb746356486d4c02599d9e5c8346b8d81
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 5 05:12:56 2003 +0000

    use standard name
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 95ae7c1e5cb57e6fb69fab163ad68acfed83c320
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 5 05:11:52 2003 +0000

    pci.S moved into arch/ppc/lib/pci_ops.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit be84533ed695ba004f5d22d757e7f57fe64debec
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Oct 5 05:10:52 2003 +0000

    getting options right
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5ebf4d343147743c2c856f62fa5953046efa7483
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Oct 3 02:53:02 2003 +0000

    - Modify the code to C style indenting.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fae510cd84dcf175d27c7cf2a5662afcab2cc76d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 2 23:33:01 2003 +0000

    Some timing in here, but we don't set; it breaks.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ee163f3c1860b47893064b65146f878e112f70f6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 2 22:54:43 2003 +0000

    ram size now set from SPD.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a70483b83bdc733e187ca6955b4edfa02a4d80e0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 2 22:48:28 2003 +0000

    First SPD code in and working!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb3f498296bad22b360796139bc454d141d7ccc9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 2 18:16:07 2003 +0000

    success. It boots as a bproc slave now.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 53311091a63f3fd63f24e296246e040730dfabbe
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 2 04:16:30 2003 +0000

    Fixes but config tool still sucks on this.
    
    Sigh, two passes here we come? DAMMIT!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6dd6c6850785dc55854446503dd2fe851fc6a77e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Oct 2 00:08:42 2003 +0000

    IRQ setup for EPIA
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e0005ba6d19ac79d3a883e0e5eccfce79a03ec40
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 1 23:18:14 2003 +0000

    fix sizing of PCI IRQ table in the Config.lb (there are only 5 slots)
    
    But linux still refuses to believe this table. What's odd is this is the identical table used in V1. Damn.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7cf52c979f784573ad9d9e18207e04afb542945b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 1 22:25:36 2003 +0000

    fixes for epia.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 14e72218f3d60531733834c7b23ea882420fb0f1
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Oct 1 21:14:52 2003 +0000

    uses statement missing
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6358a4a0030f074af76f6bf8dbf5725e11a3b3c0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 1 17:28:48 2003 +0000

    default USE_FALLBACK_IMAGE to 0
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 848d336534edb7996047fb69811d3b5d922d40ef
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 1 16:09:23 2003 +0000

    vga support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab1f21716184faa341ab13a57b69e81d611db6c9
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Oct 1 14:12:57 2003 +0000

    some quartet memory init updates.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8e05d42bf8c02a1d3141721ff424bc9526f0cd19
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 1 05:43:09 2003 +0000

    512kflash builds in epia.512kflash
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 08febd8b675ca1d32e535e11b631e7a655b510ba
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 1 05:42:31 2003 +0000

    new epia target for 512k: targets/via/epia/Config.512kflash.lb
    
    buildtarget now takes either a directory, and uses directory/Config.lb, or
    takes a file
    
    epia defaults to 256k flash
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 320c6a0102a9ccfeffa4eb5eedaec3347b5bc531
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Oct 1 01:45:43 2003 +0000

    Fixes to the smbus code. Now for the fun.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c18170b241c2b242335e8c2d7bbfdbc138133cc1
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 30 23:53:45 2003 +0000

    more fixes for via ... plus a little more spew.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 303349a9d2c266bb342a76f3d55600243ef0b774
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 30 18:18:22 2003 +0000

    fix and complaint.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 00359e91ec36a52fd99f3ad16ec4125ecc3dfb61
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Sep 30 12:02:24 2003 +0000

    remove references to static_devices.o
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd5d0a5f05d1321b01d0eb64aa69eccb6f678263
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Sep 30 11:52:49 2003 +0000

    get rid of static_devices.c
    don't use mptable on solo, it's not an SMP system.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a1d2c58c368df765e7fa6ebdee9f842d303222aa
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Sep 30 09:52:37 2003 +0000

    no filo, since khepri has no ide disks per default
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99dcf231f48433a07cbd47ecb0c23301a6b5b34e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Sep 30 02:16:47 2003 +0000

    The epia now works.
    
    Now to fix the ram ...
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 02360d6672bd95b980f83f464dea4c624b8f8aa2
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Sep 29 11:36:01 2003 +0000

    default is 256 not 512k
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 67a1cb3207faa75240e9c89c6fb6721993dc8c0d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Sep 27 04:28:39 2003 +0000

    ok that's it. I think this might work.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 864a3d347466bda79a71181c5b84a43e820a25c1
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Sep 27 04:18:31 2003 +0000

    a few tweaks etc.
    
    Still probably wrong.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e5fe1d6feda2ac82fe6838d0167215d57039cac
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 23:22:31 2003 +0000

    it's getting through the 8601 but the values are still not right.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 854d234a06b709830ece8d6c2672ff89ae82b4f7
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 22:45:54 2003 +0000

    something is wrong here but not sure what.
    
    But nothing is getting set into the north bridge.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3c17ca23409078b7f77e4b200aee0fd22d0cabc
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 22:10:53 2003 +0000

    via epia is putting out  bytes!
    
    ron
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 42acd12cbc5a5fe6054cdd19de76cbe35d2aef9e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 17:41:21 2003 +0000

    serial supprt.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 11dbdf5d782b94fb40c6f57488333d927d244975
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 17:16:14 2003 +0000

    just to get us back where we were.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 430111b9d1472ef72d9960020eb3eb28e276ca7e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 16:12:23 2003 +0000

    It builds!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aa4b4e031f9f48840aca3c4961d3edf59701eea7
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 15:55:11 2003 +0000

    add cpufixup.o
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b4457afb043786d9b51e7092b7a8ddf3e340e35
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 15:54:34 2003 +0000

    cpu fixup for p6
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 737fe21ebd1f406bc4ecea7a50cae38bd7ef4831
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 26 15:36:03 2003 +0000

    remove fixed ROM_SIZE setting, add default to 256k
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ef5f21807ac7ca8f0553df1867bfd1c225a82f46
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 15:24:54 2003 +0000

    keyboard support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e1313fa183dc7bb2806b298e110490a9cfec300d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 15:23:53 2003 +0000

    added CONFIG_KEYBOARD, default 0
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 987fe0f2a477a133ddf5a912535354ae49565afd
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 14:36:27 2003 +0000

    fix 'deprecated' warnings
    
    more via fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0502b7a64c748ffba5e509b8be400debf0396a0e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 26 11:40:05 2003 +0000

    fix buildrom statement if there's only one romimage specified.
    roms always needs to be an array.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dfe7d53a09a453374a997105dbeb916ff7723bb8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 26 10:07:13 2003 +0000

    ignore target temp build dir
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 261f2bb70abe3297162c50ca89ada85958ea9d99
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 26 10:03:47 2003 +0000

    add cvsignore files for target files. Use gcc -m32 to build on AMD64
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 63afbd4fdce93a7756e574b618f829d41dbf80b9
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 26 09:53:38 2003 +0000

    ignore temp. build directory
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5e837b7791754270de697ad0ecb9286750839f08
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 26 09:47:41 2003 +0000

    get rid of pointer/int cast warnings on 64bit.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c817926a6bd4195cff6b6a0d8fa35b8637cee1b8
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Sep 26 04:45:52 2003 +0000

    via epia; also yh lu tyan.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 10941401e8c040ade7456b0f49ab21c6306791fd
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 25 23:03:18 2003 +0000

    allow default settings in the mainboard file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3ff7bdaad7afa8f926eb8e1b6151d34cd467dbb0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 25 22:04:19 2003 +0000

    new from yh lu
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1621e9303cd9fcd6363553a091358bdfb908b8e9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 25 22:04:04 2003 +0000

    new from tyan
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6e71aec6cda10636a692cde7f6e1156342614ca2
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 25 17:35:30 2003 +0000

    no default rom size
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ca34c040e5b01d08a2eeb041e30f282b9b698145
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 25 17:34:56 2003 +0000

    ROM_SIZE has no default now.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57cef6590b5d8ff6397639de4f016044aac45251
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 25 17:21:57 2003 +0000

    added via vt8231
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b664dd0a0ba1c8d234642d52bd03fbb2b1f9e50
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Sep 25 17:01:28 2003 +0000

    first cut at 8601 support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c22465fc49e89dfb343471770325128333edd60e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Sep 25 13:39:53 2003 +0000

    add another compat chain keepalife fix
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71e3c9ab15761de9d0b3f878352600d77933307a
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Sep 25 13:37:00 2003 +0000

    khepri resource map update to keep compatibility chain
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bb79b0efb810e20becec881e5892b96d0403174e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Sep 25 12:54:55 2003 +0000

    remove last occurence of AMD8111_DEV
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0fff41e261c97dab2a43d52678b161c2d6412951
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Sep 23 22:44:12 2003 +0000

    new target configuration: newisys khepri
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 71e481d24e51c8ae5b02651af1eb0ea20289f425
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Sep 23 20:02:02 2003 +0000

    update hypertransport setup for khepri
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a2241c821a7f1bfdf185c66a11fc6ad093c48277
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Sep 23 18:51:28 2003 +0000

    fix hypertransport setup for quartet.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9719cce5a3ba47fabeb7f8e0897c89cfd679e04f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Sep 23 18:50:35 2003 +0000

    make coherent ht setup capable of non-standard link configurations
    (i.e. with CPU1 not connected to ACROSS link of CPU0)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dcdbdfb46e7075515fef5be386e14c42463f7a5e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Sep 18 14:16:08 2003 +0000

    first shot of legacybios emulation.
    does not work yet.. sorry :-(
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1119 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 59549598c08d5bdcee01bfb91dd9d147edf9fee7
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Sep 17 12:18:40 2003 +0000

    fix romcc compiling 32bit code on amd64
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e27b08d41c4119e48b4d8cec5ecc6a54510d6ed9
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Sep 17 12:17:58 2003 +0000

    add filename to buildrom
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed10c390adf6c0022a8e9fd2b5ae935fc963d138
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Sep 17 11:05:29 2003 +0000

    add filename to buildrom command
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0a5f865a27fadb78c9094aa9e2fc6a1667202306
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 12 12:39:04 2003 +0000

    add cvsignore file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bcb9f858e5cffc76da5fdb3e9618d11b022aa262
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Fri Sep 12 12:35:18 2003 +0000

    add "clean" target
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57398af2a4cff42effd17dac39e8805185ad290c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Sep 11 13:53:29 2003 +0000

    update Config.lb and add khepri ht chain
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1bb45d5a42285e369315e2ef4567deed4172f086
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Sep 11 11:55:18 2003 +0000

    add quartet and dspace targets, disable reboot in Solo target.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 79249e3dbc955c255b1b53107b3a5488775f5690
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Sep 11 11:53:15 2003 +0000

    add new target for DSPACE DS1006 card, make quartet auto.c all verbose
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5282cd08756eb5084d5a86a7e18a87bc6801d5b7
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Tue Sep 9 13:30:58 2003 +0000

    remove old config files, adopt to new config method. fix resource map (?)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dad60489d5dcce58ad6b99f5bc6becc1d4fc7660
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Sep 8 15:01:19 2003 +0000

    automatically build config.py if it's not there.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9714894d4f6505e3c49fdb93bc1e7520861a2996
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Sep 8 14:17:24 2003 +0000

    add solo target config file for new config method
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 75d42640d5fdc1d76ca9874fa0f4dd8715fe1644
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Sep 8 14:03:50 2003 +0000

    update SOLO code (untested but compiling and pretty much complete!?!)
    drop old configuration method.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ff0e8465e828aefb636742c254237799ed23ccd7
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Sep 4 03:00:54 2003 +0000

    - Include hypertransport.h in hypertransport.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6638755a232d7ad8a5eb178804bed7a6847cf1ae
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Sep 4 01:25:55 2003 +0000

    - Remove dead argument to hypertransport_scan_chain
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 481b5688b5f462db7fa0b27b7fdaf8c8f54fc78a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Sep 3 21:30:18 2003 +0000

    moved init_timer() to static initialization
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f72ff36e76d0fb990655da8922ee695a0f8afecc
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Sep 3 12:09:44 2003 +0000

    cosmetics
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0ac6b41e70b2df365f8579c6e14214c42ab4c91b
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Sep 2 17:16:48 2003 +0000

    - 1.1.4
      Major restructuring of hypertransport handling.
      Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically
      Updates to hard_reset handling when resetting because of the need to change hypertransport link
        speeds and widths.
        (a) No longer assume the boot is good just because we get to a hard reset point.
        (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the
           boot counter.
      Updates to arima/hdama mptable so it tracks the new bus numbers
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e9a271e32c53076445ef70da8aec8201c82693ec
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Sep 2 03:36:25 2003 +0000

    - Major update of the dynamic device tree so it can handle
      * subtractive resources
      * merging with the static device tree
      * more device types than just pci
    - The piece to watch out for is the new enable_resources method that was needed in all of the drivers
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d4c14524f53d8e812cf52b57e16c53d259c44ea0
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Sep 1 23:47:37 2003 +0000

    - Update the version number to 1.1.2 and update the NEWS file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 30e143a5f0d7c016428ba729ba06ab144a7a16f5
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Sep 1 23:45:32 2003 +0000

    - Add back in the hard reset code from the freebios1 tree.
      This allows generic code to reset the box.
    - Update the hypertransport code to automatically calculate link
      widths and freequencies, and to call hard_reset if neecessary for
      the changes to go into effect.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1094 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9bdb460a97e87b11167ef22ec2fb737ecb95aa41
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Sep 1 23:17:58 2003 +0000

    - Updates to config.g so that it works more reliably and has initial support
      for paths
    - Renamed some configuration variables
      SMP -> CONFIG_SMP
      MAX_CPUS -> CONFIG_MAX_CPUS
      MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
    - Removed some dead configuration variables
    MAX_CPUS -> CONFIG_MAX_CPUS
    MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
    SMP -> CONFIG_SMP
    FINAL_MAINBOARD_FIXUP
    SIO_BASE
    SIO_SYSTEM_CLK_INPUT
    NO_KEYBOARD
    USE_NORMAL_IMAGE
    SERIAL_CONSOLE
    USE_ELF_BOOT
    ENABLE_FIXED_AND_VARIABLE_MTRRS
    START_CPU_SEG
    DISABLE_WATCHDOG
    ENABLE_IOMMU
    AMD8111_DEV
    
    - Removed some assembly files that are no longer needed
    killed src/southbridge/amd/amd8111/smbus.inc
    killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
    killed src/ram/ramtest.inc
    - Updates to config.g so that it works more reliably and has initial support
      for paths
    - Renamed some configuration variables
      SMP -> CONFIG_SMP
      MAX_CPUS -> CONFIG_MAX_CPUS
      MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
    - Removed some dead configuration variables
    MAX_CPUS -> CONFIG_MAX_CPUS
    MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
    SMP -> CONFIG_SMP
    FINAL_MAINBOARD_FIXUP
    SIO_BASE
    SIO_SYSTEM_CLK_INPUT
    NO_KEYBOARD
    USE_NORMAL_IMAGE
    SERIAL_CONSOLE
    USE_ELF_BOOT
    ENABLE_FIXED_AND_VARIABLE_MTRRS
    START_CPU_SEG
    DISABLE_WATCHDOG
    ENABLE_IOMMU
    AMD8111_DEV
    
    - Removed some assembly files that are no longer needed
    killed src/southbridge/amd/amd8111/smbus.inc
    killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
    killed src/ram/ramtest.inc
    killed src/sdram/generic_dump_spd.inc
    killed src/sdram/generic_dump_spd.inc
    
    - Updated the arima/hdama to build with the new configuration system
    - Updated config.g to list all of the variables with make echo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0e97fe39048fb9ed22f12dfc9d197de2f0b35631
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Aug 29 03:02:00 2003 +0000

    more targets
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b4b031cd446644323b564a62697068eef65fe0ab
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Aug 29 03:00:49 2003 +0000

    new targets
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b980e39c81a1eed2dc3e2d1a939320292b36885c
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Aug 28 17:23:15 2003 +0000

    add first bunch of newisys khepri files.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f4440e65a45aaa7d05ea55a8304630d7fd31ac44
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Aug 28 15:08:43 2003 +0000

    more motherboard specific cleanups
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f5f10d10979688e0d2ac7a01a262c50bf3e08b76
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Aug 28 13:43:03 2003 +0000

    cleaning out motherboard specific changes from the generic directories.
    Moving tyan resource map to tyan directory. Making IOMMU for hammer choosable
    via ENABLE_IOMMU
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa2df758f226f5b06537c6e6f8e27072b94644c5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 27 14:33:13 2003 +0000

    support for new mobos and fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bee6575d7cdc065be6f8b83f9217602e44f29c20
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 26 13:28:50 2003 +0000

    fixed irq tables for hdama
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 235c2545632008bda411d3287fa0fa5f6707144b
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Aug 7 14:11:08 2003 +0000

    more quartet fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 081e8cfd21ca6826fde0d3b318b66c1cd2330eba
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Aug 7 13:38:56 2003 +0000

    fix resource map for quartet
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fa875977e1afe4353fd286f47024cc0538cec8db
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Aug 7 12:32:01 2003 +0000

    fix quartet build
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9ffa475aba06bd4add1da26458937f062bb25cc
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 6 15:14:46 2003 +0000

    I mean it this time. NO more unnecessary 'dir' commands for cpus.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d76ba1492abf3c33708d46f925f13e263083453
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Aug 6 15:06:27 2003 +0000

    end silly multiple sources of /cpu/whatever.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 91232c1ca610e149c6f95e9647849ab821d7d8b8
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Aug 6 10:45:57 2003 +0000

    add XIP_ROM_[BASE|SIZE] to newconfig for quicker bootup
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 27f94bf84689a7b343481831eb1e48855a993e7a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 5 23:33:14 2003 +0000

    turn down the spew level to 7
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f1a6975eff9bf50c8a6a81abe19fd057b9c1018
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 5 23:31:26 2003 +0000

    fixup. SMP works fine.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0c3fd559ec8b4db174dae3045ba3c130dd6988ea
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Tue Aug 5 16:35:34 2003 +0000

    Fixed version skew problem.
    Use warning() and fatal().
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 95bbf58b8c1620a6a6171453a76b3b0ab5de68e4
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 5 13:43:18 2003 +0000

    missing file chip.h
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 312f64a2c2677553a5cf896b8badaa1ffb05069a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Aug 5 02:24:56 2003 +0000

    now needed.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fb0db6ca6d8a1900e72536164803b551bf71d1be
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Aug 5 01:00:48 2003 +0000

    - Update the Makefile to have a proper ALL: target
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 60e185fcc4f2cfe1f8c01011ab976c10b2975f7a
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Aug 4 22:13:57 2003 +0000

    patches from Yh Lu. Tested and working on HDAMA
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a43048d371ad4bfaa7a53b3621770907b5d1879d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Aug 4 21:05:19 2003 +0000

    Commits for the new config static device design, to allow more than one static
    cpu of a certain type and to eliminate the
    cpu p5
    cpu p6
    cpu k7
    
    nonsense in the old config files.
    
    Next step is to hook into Eric's pci device stuff.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bbb6d1020f97b2694f496d87c1f49a0cb2e0bb96
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Aug 4 19:54:48 2003 +0000

    - Fix poor resource allocation estimate.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dfa26a4d8c45e5e7d55992df3ec868b9c1cebd36
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Aug 1 03:01:54 2003 +0000

    - Remove useless definitions
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a265d5c0a0449ade24b999635fecc253c612bee3
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Aug 1 03:01:28 2003 +0000

    - Update cpufixup so we support more than 4GB of memory
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8aeb2a4dbf06470ad7b514e73cafbab96e9b9bc8
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Aug 1 02:52:35 2003 +0000

    - Update raminit.c so it works properly for multiple cpus
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5f7fc31d701409231c1de5d470760610ea1d9ecb
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jul 31 17:44:02 2003 +0000

    fix for newconfig
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1188bd2adc2dd539d5c1a75087b8516b997a630e
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jul 30 11:22:50 2003 +0000

    make solo target build again
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57ffeb0578db71b1c57d9e4137def42aac34fe18
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jul 30 03:05:20 2003 +0000

    updates from YhLu, plus fixes for PPC/K8 issues.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b265254e1c50af2e3b84c0628016dda4ccf253d7
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:35:14 2003 +0000

    Added support for naming instances of parts. This is to allow arbitrary
    device arrangement that can be statically configured during boot.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f4ade7a0a18ce280df9e49a8d016559d497c78b3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:23:02 2003 +0000

    adjust options
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 714caaea388062bb89c320a871347f23c24a790b
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:21:03 2003 +0000

    PPC 4XX support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd0ac35a77541dc1efec34c720e0ff068af0f243
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:18:51 2003 +0000

    use longs
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 04091a67e574d79f0f8d5276e09f2e15217b20e7
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:18:26 2003 +0000

    PVR support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6257e0347d7cf0ba8cdb96ef5bc99224720e224b
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:17:57 2003 +0000

    added new routines
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 06550b75e540b6a096fa9c82d56474d4fcf59d32
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:17:25 2003 +0000

    deal with different reset vector addresses
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cc6b6c4c83bfd8bb074029814ce2a501c2cd64a9
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:16:49 2003 +0000

    made timer more generic
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 008c127074345910de4b7726ccd0cca2d8a89854
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:16:21 2003 +0000

    added ppc_ to function names
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 499b3041b43ec2f6db9dab12c5c6b6d3aa84d105
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:15:13 2003 +0000

    CPU_OPT for cpu specific flags
    _RESET to specify reset vector address (ppc4xx reset vector is at end of
      memory, rather than at beginning of ROM)
    CONFIG_SYS_CLK_FREQ to specify frequency of system clock (needed for ppc4xx
     clock speed calculation)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 821730906b34ba0b4708283b843605fcf51f9d0b
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:11:26 2003 +0000

    corrected cpu path, added clock.o
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d8241562872bc7b0579dba1183adbb1dd8351b0
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:10:46 2003 +0000

    cpus have vendors now
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a1cd3d8290f94b730d7e9b3288667a3f348bb90a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 28 21:06:51 2003 +0000

    moved extern to chip.h
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b34e7c407727e4eadef9f6194c69412604f968ad
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jul 28 04:34:15 2003 +0000

    Fix for RAMBASE.
    
    remove unused make.base.lb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit aead5f2582d2609a5fed9f05bc41aff3ab6c9344
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jul 25 21:43:12 2003 +0000

    change it so linuxbios.rom is the final target.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 138af8aa1d0a6b11933189a4eb0f88db65b10119
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jul 25 21:42:02 2003 +0000

    Fix for ROM_SIZE to ROM_SECTION_SIZE
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f8651ed6c268685bc9e9763041bd6721e1c82059
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jul 25 17:31:53 2003 +0000

    one last fix.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f9e756c3865a4a5e17db368e835ae5a9c23dcf53
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jul 25 17:29:13 2003 +0000

    added a bit of error checking!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 336b4590184bf5e522f213f375f68e3f930d141d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jul 25 17:28:43 2003 +0000

    fix bugs ron added with new options
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 35cce551c4c60d7df4ab099070e684279dddff3c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jul 25 04:32:42 2003 +0000

    Mods for YhLu to enable calls for mainboard init.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ebb645a9fb5d81a8ea701fd53a2bf63bb899d51c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jul 25 03:05:54 2003 +0000

    YhLu's changes to resolve several memory and other problems.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit feaa75960cf1e731934d95b5e954d213bc72becf
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jul 25 02:55:26 2003 +0000

    Corrections for Config.lb for new tool.
    
    Bump up debugging messages and reduce the size of memory test until that is
    running correctly.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d9e77c8a4a844c81040a995af1191d58fc398d3d
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jul 25 02:54:26 2003 +0000

    corrections for new config tool.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8c19a4ffb4af46284ed064bf3064b47dc00ed82f
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 24 21:19:19 2003 +0000

    cpu should be vendor/device too...
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8091adb7dd1fa978ea836c3edd8295285bf8e5f6
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 24 21:11:23 2003 +0000

    missing options
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 33fff7a0dd984526d169fbd860d64c545aaf85d6
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 24 21:05:02 2003 +0000

    moved cpu code to cpu/ppc/mpc74xx
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7dd98995581302666c09c6c437bbe3e61ad6a2c
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 24 21:03:45 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b794667b75e96370a8d409a6dc9781043170e4f9
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 24 15:14:39 2003 +0000

    added uses checking at top level
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb98b1c3190ee3504c865e10b64fc38d12d4d050
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 24 14:20:01 2003 +0000

    #if was reversed
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 505322e48cf2b9f81bb8022a384872f9a890a619
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 24 14:15:35 2003 +0000

    slight changes to static initialization
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9970bfcb7b8ca0916757d4ffcfeba811a7ad4597
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 24 14:14:01 2003 +0000

    new register format
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 92624c10d18e36120015f42337e3ed17234d0161
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 22:20:55 2003 +0000

    ep405pc board
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5bed979a9b65f5eb1e4cb0a4fff8bf6fa32f4f77
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 21:38:02 2003 +0000

    added post-pci pass
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c99bd5f38fed81bfda8ad974aeaa04c21ffe40ab
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 21:36:12 2003 +0000

    allow logging at spew level
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7100d67ae8344f6a3e9454fcf1f87243b66b1041
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 21:34:46 2003 +0000

    code was broken
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39264e2b3b08f5873936763cc8d8ecec44f5366f
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 21:33:03 2003 +0000

    new static configuration
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b87b2b89b23bb69bde2bc89546c94d892e005969
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 21:31:02 2003 +0000

    get serial console right
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5261d05f59f4239f578b064c29571925cf796135
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 21:30:29 2003 +0000

    build parser before configuring
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3bb83b8a00f61bd22a9949baacc4f6ef3efab2a3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 21:29:49 2003 +0000

    static device names start with static_
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ba9ff837b9989bd227937e927409c87a3b3a6a3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 18:52:17 2003 +0000

    add clean to Makefile
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6430c011f4630595f620a0792f2d7b57dc065d86
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 18:51:01 2003 +0000

    get CONFIGURE right
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 23e107f1844b599631c310c2f9872f01da9efce3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 18:50:06 2003 +0000

    fixed defines
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2910a2b5454f8de76c281739ae84814a4a1b47e3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 18:20:17 2003 +0000

    static devices
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit de085393ed0dc30e5d81e3efa6deec54b0624fb6
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 18:14:20 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 252d3ff1f6fb0e6405abc1f79f7f39eb8aabbe96
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jul 23 18:13:19 2003 +0000

    new register format
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3874d40ad6039303decb4e99ff68348d12cb6474
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jul 23 03:11:40 2003 +0000

    Fix the generation of .o from .S
    
    The object rules now have four members, this is getting KLUDGY!
    
    [object, source, type (i.e. suffix), base]
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99d0d7b300a3810e1cd7af514eb810418f01accc
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jul 23 01:45:47 2003 +0000

    getting HDAMA to build.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ffc161e59a917036d6b31e147944f8b54b5b75ae
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jul 23 01:42:29 2003 +0000

    updates for hdama and other things.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4dc7b80151952385c217e924648de151185e24a0
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jul 23 01:41:55 2003 +0000

    updated for new code.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd0adfe86c670c8099c791354a9f7d5526dcf356
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jul 23 01:37:06 2003 +0000

    This config.lb now works with the new config tool and builds a working image
    which boots linux as a payload.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 860ad373efdadde9bbc11ee49b8967a6428a404c
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Jul 21 23:30:29 2003 +0000

    - First pass at code for generic link width and size determination
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c018fba95a5f40c4eaaa20421e8c893dffdb62e
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Jul 21 20:13:45 2003 +0000

    - First pass at s2880 support.
    - SMP cleanups (remove SMP only use CONFIG_SMP)
    - Minor tweaks to romcc to keep it from taking forever compiling
    - failover fixes
    - Get a good implementation of k8_cpufixup and sizeram for the opteron
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d4512cdf976fc071720dbec686cf8a1a40f1db0
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 21 17:28:35 2003 +0000

    added payload
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 634a99110ce8ad99016fed21037b37f93e253a95
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 21 16:51:40 2003 +0000

    fix crt0 includes ordering
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9a0989b941dc44d8ccca929a9a9a471529c5fda2
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jul 21 16:22:17 2003 +0000

    typo fixed.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1b0e79704f5b8d04ad5dbe9781ea01b3a2159b0d
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 21 15:12:38 2003 +0000

    new chip stuff
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2b02b63c545e82d6679a4fb40e4001b499bf572f
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 21 14:00:53 2003 +0000

    new chip configure
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 73a9cf4ccb58eccb4a1383088f7c86f325fdad7f
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Mon Jul 21 13:05:56 2003 +0000

    * update quartet target to latest SMP changes.
    * remove dead code from coherent_ht.c
    * add ldtstop code for link speed changes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8275bad6f640d0da5ead72984f1efe32e6172d7d
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 21 04:20:08 2003 +0000

    more chip stuff
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 54b3d233ed4a66bc9fbc8af7dd742af7d8f2aca3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 21 03:38:42 2003 +0000

    more chip stuff
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d0580343b6c81697f0050b38ea36ee154d242ac2
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Jul 20 23:28:01 2003 +0000

    chip stuff
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b4336cf418d22551bea09d93e1cee79281b110e
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 19 04:28:22 2003 +0000

    - Major cleanup of the bootpath
    - Changes to allow more code to be compiled both ways
    - Working SMP support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fe4414587a4466b848184b8837d4c5a280949824
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Jul 19 04:19:48 2003 +0000

    tidy up
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c361a6b218e89df9a939c9a57054df38759a55c2
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sat Jul 19 04:07:07 2003 +0000

    a few changes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b2e67cdd2ce8a78f79f8ddac806209c2422235f5
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jul 18 17:17:52 2003 +0000

    new config format
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6ae46145e687923876464f4677667ab95b7203d3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jul 18 17:05:10 2003 +0000

    Allow options in mainboard configuration file
    Moved payload into romimage
    More flexible romimage declaration
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ce72e7ee21211d172b44e5eda992e415e68dd7ea
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jul 18 01:06:15 2003 +0000

    fix problems with options, more functionality
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f3961e0491ae72fa53395a00ebcfa19c5ceea9c7
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Jul 17 22:53:27 2003 +0000

    add AMD Quartet target
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 438a3e423e66e563474828901c2aa93f5131c9ff
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Thu Jul 17 22:51:30 2003 +0000

    moved generate_row from coherent_ht.c to board specific auto.c files
    due to different routing defaults of different boards.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 07d72dcfa2d92ad0cc6db19a683ac800ba843fff
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 17 22:25:53 2003 +0000

    added romimage support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 16743b89fb33af958ad7336e9ebf9a700a53c978
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 17 22:11:58 2003 +0000

    new config format
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 375505f5ccd178e4ec60a006067de3d88607ef70
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 17 22:10:11 2003 +0000

    dont export sandpoint options
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a8d2240e6ace307dd11ffb3a26ee58fd1ad1e066
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 17 17:50:11 2003 +0000

    sick of typing python command
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 062d540139467956e8389cb7094a3d1993ca29de
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 17 13:14:07 2003 +0000

    sandpoint options
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b03b33697d44fb4140922d47a4df1edd25a40a74
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jul 17 06:34:30 2003 +0000

    - Update Config so we now have the proper number of cpus
    - Remove some debugging code from auto.c
    - Update coeherent_ht.c so we get the proper broadcast routes.
    - Fix the dram probing code.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2ec0020b3c703122cbe7c1b26ac3ad7ea8074464
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jul 17 05:16:46 2003 +0000

    - Get the correct routing tables entries for the hdama's onboard nics
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@972 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5289938f063e6ff69d2167a660674181f2228d12
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jul 17 04:35:19 2003 +0000

    Config.lb for this new part
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 387a8db88e8c32e16069232e6929596e75ba9135
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jul 17 04:10:42 2003 +0000

    - Remove excess line from pci_device.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d5207593386dc221a97596ba0c82b7474a07a2b3
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jul 17 03:28:00 2003 +0000

    - Remove $Id: from crt0.S.lb
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@969 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4086d16ba216955d6124d99c9aae7ceeb2457a71
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jul 17 03:26:03 2003 +0000

    - Implement an enable method for pci devices.
    - Add initial support for the amd8131
    - Update the mptable to something possible
    - hdama/Config add the amd8131 southbridge
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5fb929e6e399ecf41aec9c6053a0340671534a63
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jul 17 02:15:46 2003 +0000

    - pci_device.c fixes for generic pci bridges to zero the unused portion of bridge resources
    - coherent_ht.c remove dead idle loop.
    - raminit.c Enable a 64MB mmio window just below 4GB
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9b45b04d234e7371f8998fbd210ac5e039507724
Author: Stefan Reinauer <stepan@openbios.org>
Date:   Wed Jul 16 15:23:57 2003 +0000

    fix some glitches in cht code: always enable routing on node7, plus do masking right when setting cpucnt/nodecnt
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 91a8ce7d80bd84f307659d2a9da2d320d91e2a7a
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Jul 16 07:04:58 2003 +0000

    - ldscripb.lb remove another $Id: line..
    - romcc_io.h Add include guards.
    - hdama/Config nothing really but I have been moving the setting back and forth between 1 and 2 cpus
    - auto.c Changed the enabled debugging comments.  This almost works with 2 cpus
    - coherent_ht.c First pass at getting this right.  It can now find 2 cpus and place them
      in some semblance of a working state.
    - raminit.c Fix problems with 4GB of ram. Disable some of the debugging code.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 61b29a9b7227fedea5e53cd0456849d5f20be79b
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Jul 16 01:58:18 2003 +0000

    - Commit a binutils safe version of reset16.inc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ae948f78e6720067f86ef917b41f2628ce8f205e
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Jul 14 20:40:38 2003 +0000

    - Compile fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 50086df616727646027c46116e43799cc9d3a332
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 14 19:02:29 2003 +0000

    new config files
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8052f4d5da886cf2a66d6ad999eaaa6050b3e032
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 14 18:03:07 2003 +0000

    new init format
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 109959d6b125ec404bd83413548ec58e659d693b
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 14 18:00:10 2003 +0000

    new config rules
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 68f9b1b1359b2dcd757d5b26aaf0b494333d2199
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 14 17:16:26 2003 +0000

    new init stuff
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a485fe9f1092955421b61ed398894aaef4cdada7
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jul 14 17:08:57 2003 +0000

    IDE support
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 70572e64c1b96a386ee99f46545ef1b661531baf
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Sun Jul 13 23:30:23 2003 +0000

    *** empty log message ***
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 655bf44cde143433587a82424d67f4d92060bfb4
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 02:15:12 2003 +0000

    - Remove all of the annoying $Id strings
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3d3f438937f9359ecb58f1c18a910a8302404ad5
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:48:30 2003 +0000

    - Use an SMBUS_IO_BASE value that will not conflict with an automatically assigned value
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 548593ad666065a5f63216aebb0176b82e82fda6
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:46:53 2003 +0000

    - generalize generic_sdram.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bd537be3d295f95417a2be6de3e1f4121c7a24a2
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:46:05 2003 +0000

    - Add missing carriage return in ramtest.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c24a5685516802eaedceff50cce0271f51c80751
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:44:36 2003 +0000

    - Solo updates
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 34cadde255a5fd83fb44830f3eabb6c5b5b23aa9
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:40:54 2003 +0000

    - Commit more tests for romcc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 58f74a25147bb93e4e7b7ecb6676ac0c462cf735
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:39:05 2003 +0000

    - Remove use of useless EXT macro
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 64f7162e1746b543a01ae3084d1d615cc8e966d6
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:38:35 2003 +0000

    - Initialize list pointers
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 542fe8056bc0566a4cb5fa2e4c490aaeab673290
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:38:11 2003 +0000

    - Small typo fix in pci_ops.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b3e9b4a534dd83be87d01bba0ce4fdb0bcc82bfd
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:37:33 2003 +0000

    - Implement division and rdtsc support for romcc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 91b5ed107369bb0f65028ccc973183bf0dcb8ae7
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:35:24 2003 +0000

    - Commit a working spd based memory initialization routine
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a07494998123820e2f59718a91e2d27941895a77
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:32:08 2003 +0000

    - Remove bogus memreset parameter from struct mem_controller
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cf008e0ec16be0f9a68a7c7c9bfb8732d9c8f9a7
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:31:13 2003 +0000

    - Add failover.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@944 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4264415c6ee53d5f87ca69f4ce81a51c87797c79
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:29:57 2003 +0000

    - Update to a working version for the hdama board
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e058a1e418d117043a2ff09a8000b31f8097328b
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jul 12 01:21:31 2003 +0000

    - Structure handling fixes.
    - Fix for asm statements with multiple results.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a3c708b5d2b4857b19a992ae9694a29e0fa8d9a2
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jul 11 14:51:29 2003 +0000

    static configuration. Needs new keyword per greg to enable inclusion of a
    part-specific struct into the tree.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@941 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2fceb77c47a168df38ca7f3b6b57ff9acc71679b
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Thu Jul 10 20:55:09 2003 +0000

    new print statement
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d7f46d29e710a789d52db1a2ba9907ca7101e6c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jul 10 14:46:59 2003 +0000

    first cut at generating code.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit bcdce3cfc76353248edc0d234d68af252743f5e5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jul 10 12:38:39 2003 +0000

    fixing trees.
    
    Greg help me, I've screwed up the tree, things are in there more than once, dammit!
    
    screwup in partobj.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 66fe2227dfbfd2086fb0266cdeea1ca904d76198
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Jul 4 15:14:04 2003 +0000

    - Moved 2 of the test cases into tests for failure
    - Reworked the transformation into ssa form and now I catch all unitialized
      variable uses.
    - Several more test cases
    - Bumped the version to 0.34
    - Verified that -O2 the scc_transform now works.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 830c9886eaa6a2b1d8bbc2fd36bf7b3f5f31a0d2
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Jul 4 00:27:33 2003 +0000

    - Minor fixes for handling structure constants and array values that are not sdecls
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 678d816f26d06dbf7315fc95e4fc23a39f7806a5
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jul 3 03:59:38 2003 +0000

    - Allow for a larger rhs on phi variables
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 530b5193e477d1756598700805b35e8a129a241f
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Jul 1 10:05:30 2003 +0000

    - Massive set of cleanups/fixes for romcc.  Lots of corner cases now work
      properly.  And a few long standing bugs have been rooted out and removed.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 57fa1b8279d78b3083b086708d857422ed99beca
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Jul 1 06:51:27 2003 +0000

    - Code to enable and disable use of the sse and mmx registers
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c22ea4f00d4a0f12c8d31a36fe9853cb18c62c9c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jun 30 17:29:31 2003 +0000

    all: now depends on linuxbios.rom
    payload.block is going away
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6a3a3e5c982aa3f04f47126c3ed47b060e49c78e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jun 30 17:23:35 2003 +0000

    placeholder crap for sio
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 776fce944946cfb04e922c098dba604d83ee5bb5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jun 30 17:07:13 2003 +0000

    now builds with *0* tweaks.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b5391cc4b9e22ed1289556a079a5bd56fabf0c51
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Mon Jun 30 17:04:35 2003 +0000

    TAGS are back!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d1ea53995ca8c385db79174d9b2fa133fd52b0aa
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Jun 28 06:49:45 2003 +0000

    - Update romcc so that it more successfully spills registers to the xmm registers
    - Add several more test cases.
    - Bump the version number to .32
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit db59928fd93080e5376e45f7dcf7ddee0262e336
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Thu Jun 26 04:05:37 2003 +0000

    OK, now builds fallback for arima/hdama!
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4f22177aa5fdbdd8166ba59938018fc53a4ad2ba
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Wed Jun 25 15:27:41 2003 +0000

    Simple printing of options. Will make this better.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 584997b5284b7fe50e446d81837252f93376a4eb
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Jun 25 11:34:59 2003 +0000

    - Set the default compiler back to gcc ooops
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 3a51f3bc5e59ed45d428ef0e3515032164394aad
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Jun 25 10:38:10 2003 +0000

    - Error on function prototypes
    - Fix a last couple of structure related bugs
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0f28460efbf4548c8bcfc2b20419f8375cd231c7
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Wed Jun 25 03:20:22 2003 +0000

    more fixes but it appears that options are not picking up the right values.
    
    I set USE_FALLBACK_IMAGE to 1 in the top-level Config, but when it is tested
    in arima/hdama/Config.lb, it is acting as though it is zero.
    
    Also added a print command so it is easier to trace 'if' behavior.
    
    Usage:
    print "string"
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ed27a5e5474b0c23dbedca9519f72265a8f1cf51
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 22:51:16 2003 +0000

    needed rules for DRIVER
    more fixes to various Config.lb
    
    one last problem and we're there
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cb18b80e38c34238279d5fe3584e9ee500df9201
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 22:17:51 2003 +0000

    Just two undefined's left.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit e15dfc1d9fd42550ca3442673e0cd008680409b3
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 19:51:38 2003 +0000

    update to thing to make them work ... still not there though.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 1807c37418cbe777b738ba44a22b091e375fded6
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 19:44:00 2003 +0000

    Fixes to various config files.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dabc15feec808e588281fe4b6b87efb65a8b239e
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 19:37:05 2003 +0000

    fixed paths for GENERATED
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6d22c85326203529651ca33286bb5b6ae0dd38de
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 18:39:11 2003 +0000

    update .lb
    
    we need to get rid of yappsrt.pyc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit cd5382651f5aa8adbd31cde4db934f5dca15608d
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Tue Jun 24 17:37:02 2003 +0000

    ifs now have elses
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2366020f23fa92e3b69e885b1f4a08630ff89195
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Tue Jun 24 17:26:45 2003 +0000

    if statement for options
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 51305ee6cc36300c44cc1f3d4b2c365223b0762e
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Tue Jun 24 16:07:07 2003 +0000

    For new config.g
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 03b59864dfd3d1d06b056fcf530da8ca328fa99c
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Jun 24 14:27:37 2003 +0000

    - A few more fixes to get pointers to structures working correctly.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 432cc669840d110f671fe9fbf36a3a3477995b89
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 14:04:03 2003 +0000

    arima updates
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0044307756b994dd6add4e11b431f2fec3be4f2c
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Jun 24 12:34:45 2003 +0000

    - Fix handling of structures stored in memory
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9c8a06a3792d364e7e47ec353fbf5b18afb45302
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 03:45:36 2003 +0000

    hdama mainboard and target.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c55613345ee6735d6ad8fbf68bca5512f19d2b01
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 03:39:34 2003 +0000

    add a hint for users about why:
    Config.lb:0: Error: Option USE_FALLBACK_IMAGE Undefined.
    might happen (i.e. missing 'use' command)
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7254a89c883fbab349b0b772b3bc982cc817dc5c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 03:36:37 2003 +0000

    oops, greg already did SMBUS, didn't notice.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a7b3cfff275e492309c064f4dcd1e0896ec49ef9
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 03:30:48 2003 +0000

    added SMBUS stuff.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 39b8077ad553878d22d6f865e810b912dbedac5c
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 03:12:14 2003 +0000

    Simply typo in 'target' if directory does not exist
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7edf2ca6ff27671477915f79646f19d47596eb8b
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 24 03:08:57 2003 +0000

    fix non-portable syntax.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 06a927dd6820a03d872934e82b05989a988d4b11
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jun 23 23:52:15 2003 +0000

    Syntax fixes.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 826def7e1dbf96b0ab87c7cef1aec9a46d893501
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jun 23 16:54:12 2003 +0000

    New option stuff.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9cf8c2efdde3e98e685c698933ae6b585492cca3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jun 23 05:00:08 2003 +0000

    _RAMBASE used by linuxbios_c.ld
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5808bac56843a81fe613217e8e5f8f884eab3d65
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jun 23 01:02:54 2003 +0000

    Sandpoint configuration file.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 4890a666a9fa9a052d2369bd85566b3f545382a3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jun 23 01:01:17 2003 +0000

    Global options file
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a946e4a596f3f93ee3b9cc6b0a4285882bf4e1f1
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jun 20 16:46:48 2003 +0000

    tool for building roms, to eliminate icky shell scripts.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 153ea3548f5ac80d30103ace2655faaf05aa2ccb
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Jun 20 14:43:20 2003 +0000

    - Implement goto support
    - Register allocator bug fixes.
      * coalesce_live_ranges now also updates the interference graph of live instructions
      * resolve_tangle now avoids copies to phi
      * correct_tangles is now called in a loop so that all tangles get fixed
    - Bug the version of romcc to 0.30
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7a0ba84dcddf08cdd6a4431c899ae1ee0ed986c
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jun 19 15:14:52 2003 +0000

    - Update the romcc version.
    - Add an additional consistency check to romcc and fix the more obvious problems it has uncovered
      With this update there are no known silent failures in romcc.
    - Update the memory initialization code to setup all 3 of the memory sizing registers properly
    - In auto.c test our dynamic maximum amount of ram.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 9dbd46077615b14f28f6a6b398c392f608af68e1
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jun 19 03:34:54 2003 +0000

    - Remove bogus #if CONFIG_SMP  test
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d3283ec05f51056faa18610e952ccc81cb738313
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Jun 18 11:03:18 2003 +0000

    - A new test case for romcc
    - Minor romcc fixes
    - In smbus_wail_until_done a romcc glitch with || in romcc where it likes
      to run out of registers.  Use | to be explicit that I don't need the short
      circuiting behavior.
    - Remove unused #defines from coherent_ht.c
    - Update the test in auto.c to 512M
    - Add definition of log2 to romcc_io.h
    - Implement SPD memory sizing in raminit.c
    - Reduce the number of memory devices back 2 to for the SOLO board.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 99acb49cf71ee7038216391ae2b0d09675ab6ce5
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 17 16:51:06 2003 +0000

    added config and other test files.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 667393676bf0ea08b6aadfc0119bd87f7cf2cc25
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Tue Jun 17 16:48:07 2003 +0000

    new config file testing the update stuff.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8d9c123812492a80a43112c8dd217fcfb3cee2c5
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Jun 17 08:42:17 2003 +0000

    - Minor mod to reset16.inc to work with newer binutils hopefully this works with older ones...
    - Update apic.h to include the APIC_TASK_PRI register definition
    - Update mptable.c to have a reasonable board OEM and productid
    - Additional testfiles for romcc.
    - Split out auto.c and early failover.c moving their generic bits elsewere
    - Enable cache of the rom
    - Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f96a810f11681ba436b446e9451e02cffcd525f5
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon Jun 16 16:57:34 2003 +0000

    - Reduce the algorithmic complexity of parts of the register allocator
      so the worst case runtime of romcc is much more predictable
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit d3e377a520d6ad5997f2ef7c8fc1b823d6d0e7f2
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Sat Jun 14 15:07:02 2003 +0000

    new config tool
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f7092040fd4aba081aad75116c2b9594149d5c66
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jun 13 22:07:53 2003 +0000

    More FB2 stuff
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 26ba0f5f9bb04e296c3a6320a855639c2f14e83c
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jun 13 17:21:10 2003 +0000

    Freebios2
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 64b2e474b14f3d23565363464e15fe2ec54e248e
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jun 13 17:16:36 2003 +0000

    Updated.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8cff29d63e256ed36217174ac14f9c132ab3076a
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jun 13 17:09:26 2003 +0000

    Added tables.c
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c055fbb274305ff982922eb4d19b04353d3e3fb7
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jun 13 17:02:57 2003 +0000

    Fixes.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 88e467f38e60cbf45bd372832102bb0503886aa3
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jun 13 16:54:40 2003 +0000

    PPC cpu stuff
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 93247c0428f749b7dfbbbfaa0a56d20c0a10ad7c
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jun 13 16:25:21 2003 +0000

    IDE stuff
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0d796734a66b0206166a3e807d01d8d3f23aac22
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Fri Jun 13 16:17:17 2003 +0000

    IDE stream driver
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 7a5416af9574095c6df28fb8192fe4c063afa8da
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jun 12 19:23:51 2003 +0000

    - Modify the freebios tree so the pci config space api is mostly in sync between
      code that runs without ram and code that runs with ram.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 540ae01cd341de75f5eb57906699ca24667d71cc
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Jun 12 17:55:54 2003 +0000

    - Changes to the pci config routines moving them closer to the non romcc API
      The goal is to have the same interface with or without romcc.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 05f26fcb571340b17beaca16939a025a9c0b4cdd
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed Jun 11 21:55:00 2003 +0000

    - Factoring of auto.c
    - Implementation of fallback/normal support for the amd solo board
    - Minor bugfix in romcc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit c927b022c23a55e84d5d6aaac1deb7b95e25a878
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Jun 10 21:25:29 2003 +0000

    - Update romcc to version 0.27
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 6aa31cc754744a83177ea922e71c6bdf02cad5df
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Jun 10 21:22:07 2003 +0000

    - Update romcc to version 0.27 and add more tests.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit dc18ef018d080f050de9e28be913f544d3009cb2
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jun 9 22:08:08 2003 +0000

    Moved from freebios
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit f655bf7f3e0c608f4b9cae1ee76e2be5477f4df6
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jun 9 21:59:27 2003 +0000

    Moved from freebios
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 032211593248d4d9a569ecfd269a2433ea5b1c7c
Author: Greg Watson <jarrah@users.sourceforge.net>
Date:   Mon Jun 9 21:29:23 2003 +0000

    Moved from freebios
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit fd958cea68e7df40c47a3a97762d2433b5a52819
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri Jun 6 14:35:36 2003 +0000

    more specs.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a05b6ddb1544d763b2ee8aafb2de45c1504ea2da
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Wed May 21 16:14:51 2003 +0000

    - Add pci_def.h so romcc compiled files can also get at the
      pci definitions
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 526855741b6abb970024366316b941fb6b3d2cb6
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Mon May 19 19:16:21 2003 +0000

    - Cleanups on the romcc side including a pci interface that uses
      fewer registers, and is easier to hardcode.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 49cf5967ce31af37e61d59a00939f50bc4256761
Author: Ronald G. Minnich <rminnich@gmail.com>
Date:   Fri May 16 23:33:13 2003 +0000

    descriptor for chips
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 302763831dd1be38c59238f6fe32ec4518da28f9
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri May 16 20:47:48 2003 +0000

    - Fix ? expressions previously they were reversed.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit da55d3e258b17dc45bacba9db5c6750df4886563
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue May 13 21:02:26 2003 +0000

    - Intermediate fix to allow register allocator failure
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit a96d6a9dabb41188f1cef2896d1d1160d613b11c
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue May 13 20:45:19 2003 +0000

    - Add a test to make certain romcc is properly allocating registers.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 0babc1c1164dd7ec51fde8141c8687a71997c81b
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri May 9 02:39:00 2003 +0000

    - Implement support for structures, typedefs, and __builtin_rdmsr, __builtin_wrmsr in romcc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ba8c25affb3178006435fd54c2ddef51587cc1bf
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu May 8 00:31:34 2003 +0000

    - Update the test cases for romcc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit ab2ea6b474b6584b8e12eb2b6ac698de05d5efc9
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Apr 26 03:20:53 2003 +0000

    - misc minor fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 2c791ce2c104b529be4485b8480a2ad85ec32d51
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Sat Apr 26 02:14:06 2003 +0000

    - Minor bug fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 501eb25247a86a76ca84ac31c10c40384b6fde95
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Apr 25 03:02:13 2003 +0000

    - Almost implement failover booting on the solo.
      I need a very early Hypertransport setup to get anything more going.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit eb00fa5c11085a323bd3acd1e657cf3ef2b16481
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Fri Apr 25 02:02:25 2003 +0000

    - Commit a working pirq table for the AMD solo
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 825dd3361bd30de3bae3f33d467441e82dacc757
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Apr 24 23:25:29 2003 +0000

    - simple bug fixes
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 497eb854415a0e54609fc747321c75b81c7df7c6
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Apr 24 06:57:32 2003 +0000

    - irq routing table generated by getpir
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8cd55d7f4a90d8c1499dddd319db12e6c4942e51
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Apr 24 06:56:37 2003 +0000

    - More attempts to leave irqs in a working state.
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 5899fd82aa2f5c3855eb6630f702f3239b6b7015
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Thu Apr 24 06:25:08 2003 +0000

    - Small step forward Linux boots and almost works...
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 8ca8d7665d671e10d72b8fcb4d69121d75f7906e
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Apr 22 19:02:15 2003 +0000

    - Initial checkin of the freebios2 tree
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit b138ac83b53da9abf3dc9a87a1cd4b3d3a8150bd
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Apr 22 18:44:01 2003 +0000

    - Checking latest version of romcc
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

commit 77d1a8311f29e65f68351719c5b0b223299ef8a9
Author: Eric Biederman <ebiederm@xmission.com>
Date:   Tue Apr 15 00:44:05 2003 +0000

    - Start the 1.1.x series that will become LinuxBIOS-2.0
    
    
    git-svn-id: svn://svn.coreboot.org/coreboot/trunk@771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
